aboutsummaryrefslogtreecommitdiffstats
path: root/cvmx-pko-defs.h
blob: 8c626a6a6ae13d4b7abc295fcfefffa80d0de140 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
/***********************license start***************
 * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
 * reserved.
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *   * Redistributions in binary form must reproduce the above
 *     copyright notice, this list of conditions and the following
 *     disclaimer in the documentation and/or other materials provided
 *     with the distribution.

 *   * Neither the name of Cavium Networks nor the names of
 *     its contributors may be used to endorse or promote products
 *     derived from this software without specific prior written
 *     permission.

 * This Software, including technical data, may be subject to U.S. export  control
 * laws, including the U.S. Export Administration Act and its  associated
 * regulations, and may be subject to export or import  regulations in other
 * countries.

 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
 * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
 ***********************license end**************************************/


/**
 * cvmx-pko-defs.h
 *
 * Configuration and status register (CSR) type definitions for
 * Octeon pko.
 *
 * This file is auto generated. Do not edit.
 *
 * <hr>$Revision$<hr>
 *
 */
#ifndef __CVMX_PKO_TYPEDEFS_H__
#define __CVMX_PKO_TYPEDEFS_H__

#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050001170ull);
}
#else
#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
#endif
#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050001010ull);
}
#else
#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050001018ull);
}
#else
#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050001020ull);
}
#else
#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050001028ull);
}
#else
#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
#endif
#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset)
{
	if (!(
	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
		cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset);
	return CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8;
}
#else
#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC()
static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
		cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050000020ull);
}
#else
#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
{
	if (!(
	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
		cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset);
	return CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8;
}
#else
#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
#endif
#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
}
#else
#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
}
#else
#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
}
#else
#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050000050ull);
}
#else
#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050000058ull);
}
#else
#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
#endif
#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050000100ull);
}
#else
#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
#endif
#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_PKO_REG_TIMESTAMP CVMX_PKO_REG_TIMESTAMP_FUNC()
static inline uint64_t CVMX_PKO_REG_TIMESTAMP_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
		cvmx_warn("CVMX_PKO_REG_TIMESTAMP not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180050000060ull);
}
#else
#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
#endif

/**
 * cvmx_pko_mem_count0
 *
 * Notes:
 * Total number of packets seen by PKO, per port
 * A write to this address will clear the entry whose index is specified as COUNT[5:0].
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_count0
{
	uint64_t u64;
	struct cvmx_pko_mem_count0_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_32_63               : 32;
	uint64_t count                        : 32; /**< Total number of packets seen by PKO */
#else
	uint64_t count                        : 32;
	uint64_t reserved_32_63               : 32;
#endif
	} s;
	struct cvmx_pko_mem_count0_s          cn30xx;
	struct cvmx_pko_mem_count0_s          cn31xx;
	struct cvmx_pko_mem_count0_s          cn38xx;
	struct cvmx_pko_mem_count0_s          cn38xxp2;
	struct cvmx_pko_mem_count0_s          cn50xx;
	struct cvmx_pko_mem_count0_s          cn52xx;
	struct cvmx_pko_mem_count0_s          cn52xxp1;
	struct cvmx_pko_mem_count0_s          cn56xx;
	struct cvmx_pko_mem_count0_s          cn56xxp1;
	struct cvmx_pko_mem_count0_s          cn58xx;
	struct cvmx_pko_mem_count0_s          cn58xxp1;
	struct cvmx_pko_mem_count0_s          cn63xx;
	struct cvmx_pko_mem_count0_s          cn63xxp1;
};
typedef union cvmx_pko_mem_count0 cvmx_pko_mem_count0_t;

/**
 * cvmx_pko_mem_count1
 *
 * Notes:
 * Total number of bytes seen by PKO, per port
 * A write to this address will clear the entry whose index is specified as COUNT[5:0].
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_count1
{
	uint64_t u64;
	struct cvmx_pko_mem_count1_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_48_63               : 16;
	uint64_t count                        : 48; /**< Total number of bytes seen by PKO */
#else
	uint64_t count                        : 48;
	uint64_t reserved_48_63               : 16;
#endif
	} s;
	struct cvmx_pko_mem_count1_s          cn30xx;
	struct cvmx_pko_mem_count1_s          cn31xx;
	struct cvmx_pko_mem_count1_s          cn38xx;
	struct cvmx_pko_mem_count1_s          cn38xxp2;
	struct cvmx_pko_mem_count1_s          cn50xx;
	struct cvmx_pko_mem_count1_s          cn52xx;
	struct cvmx_pko_mem_count1_s          cn52xxp1;
	struct cvmx_pko_mem_count1_s          cn56xx;
	struct cvmx_pko_mem_count1_s          cn56xxp1;
	struct cvmx_pko_mem_count1_s          cn58xx;
	struct cvmx_pko_mem_count1_s          cn58xxp1;
	struct cvmx_pko_mem_count1_s          cn63xx;
	struct cvmx_pko_mem_count1_s          cn63xxp1;
};
typedef union cvmx_pko_mem_count1 cvmx_pko_mem_count1_t;

/**
 * cvmx_pko_mem_debug0
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug0
{
	uint64_t u64;
	struct cvmx_pko_mem_debug0_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t fau                          : 28; /**< Fetch and add command words */
	uint64_t cmd                          : 14; /**< Command word */
	uint64_t segs                         : 6;  /**< Number of segments/gather size */
	uint64_t size                         : 16; /**< Packet length in bytes */
#else
	uint64_t size                         : 16;
	uint64_t segs                         : 6;
	uint64_t cmd                          : 14;
	uint64_t fau                          : 28;
#endif
	} s;
	struct cvmx_pko_mem_debug0_s          cn30xx;
	struct cvmx_pko_mem_debug0_s          cn31xx;
	struct cvmx_pko_mem_debug0_s          cn38xx;
	struct cvmx_pko_mem_debug0_s          cn38xxp2;
	struct cvmx_pko_mem_debug0_s          cn50xx;
	struct cvmx_pko_mem_debug0_s          cn52xx;
	struct cvmx_pko_mem_debug0_s          cn52xxp1;
	struct cvmx_pko_mem_debug0_s          cn56xx;
	struct cvmx_pko_mem_debug0_s          cn56xxp1;
	struct cvmx_pko_mem_debug0_s          cn58xx;
	struct cvmx_pko_mem_debug0_s          cn58xxp1;
	struct cvmx_pko_mem_debug0_s          cn63xx;
	struct cvmx_pko_mem_debug0_s          cn63xxp1;
};
typedef union cvmx_pko_mem_debug0 cvmx_pko_mem_debug0_t;

/**
 * cvmx_pko_mem_debug1
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug1
{
	uint64_t u64;
	struct cvmx_pko_mem_debug1_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t i                            : 1;  /**< "I"  value used for free operation */
	uint64_t back                         : 4;  /**< Back value used for free operation */
	uint64_t pool                         : 3;  /**< Pool value used for free operation */
	uint64_t size                         : 16; /**< Size in bytes */
	uint64_t ptr                          : 40; /**< Data pointer */
#else
	uint64_t ptr                          : 40;
	uint64_t size                         : 16;
	uint64_t pool                         : 3;
	uint64_t back                         : 4;
	uint64_t i                            : 1;
#endif
	} s;
	struct cvmx_pko_mem_debug1_s          cn30xx;
	struct cvmx_pko_mem_debug1_s          cn31xx;
	struct cvmx_pko_mem_debug1_s          cn38xx;
	struct cvmx_pko_mem_debug1_s          cn38xxp2;
	struct cvmx_pko_mem_debug1_s          cn50xx;
	struct cvmx_pko_mem_debug1_s          cn52xx;
	struct cvmx_pko_mem_debug1_s          cn52xxp1;
	struct cvmx_pko_mem_debug1_s          cn56xx;
	struct cvmx_pko_mem_debug1_s          cn56xxp1;
	struct cvmx_pko_mem_debug1_s          cn58xx;
	struct cvmx_pko_mem_debug1_s          cn58xxp1;
	struct cvmx_pko_mem_debug1_s          cn63xx;
	struct cvmx_pko_mem_debug1_s          cn63xxp1;
};
typedef union cvmx_pko_mem_debug1 cvmx_pko_mem_debug1_t;

/**
 * cvmx_pko_mem_debug10
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug10
{
	uint64_t u64;
	struct cvmx_pko_mem_debug10_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_0_63                : 64;
#else
	uint64_t reserved_0_63                : 64;
#endif
	} s;
	struct cvmx_pko_mem_debug10_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t fau                          : 28; /**< Fetch and add command words */
	uint64_t cmd                          : 14; /**< Command word */
	uint64_t segs                         : 6;  /**< Number of segments/gather size */
	uint64_t size                         : 16; /**< Packet length in bytes */
#else
	uint64_t size                         : 16;
	uint64_t segs                         : 6;
	uint64_t cmd                          : 14;
	uint64_t fau                          : 28;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug10_cn30xx    cn31xx;
	struct cvmx_pko_mem_debug10_cn30xx    cn38xx;
	struct cvmx_pko_mem_debug10_cn30xx    cn38xxp2;
	struct cvmx_pko_mem_debug10_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_49_63               : 15;
	uint64_t ptrs1                        : 17; /**< Internal state */
	uint64_t reserved_17_31               : 15;
	uint64_t ptrs2                        : 17; /**< Internal state */
#else
	uint64_t ptrs2                        : 17;
	uint64_t reserved_17_31               : 15;
	uint64_t ptrs1                        : 17;
	uint64_t reserved_49_63               : 15;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug10_cn50xx    cn52xx;
	struct cvmx_pko_mem_debug10_cn50xx    cn52xxp1;
	struct cvmx_pko_mem_debug10_cn50xx    cn56xx;
	struct cvmx_pko_mem_debug10_cn50xx    cn56xxp1;
	struct cvmx_pko_mem_debug10_cn50xx    cn58xx;
	struct cvmx_pko_mem_debug10_cn50xx    cn58xxp1;
	struct cvmx_pko_mem_debug10_cn50xx    cn63xx;
	struct cvmx_pko_mem_debug10_cn50xx    cn63xxp1;
};
typedef union cvmx_pko_mem_debug10 cvmx_pko_mem_debug10_t;

/**
 * cvmx_pko_mem_debug11
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko.out.sta.state[22:0]
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug11
{
	uint64_t u64;
	struct cvmx_pko_mem_debug11_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t i                            : 1;  /**< "I"  value used for free operation */
	uint64_t back                         : 4;  /**< Back value used for free operation */
	uint64_t pool                         : 3;  /**< Pool value used for free operation */
	uint64_t size                         : 16; /**< Size in bytes */
	uint64_t reserved_0_39                : 40;
#else
	uint64_t reserved_0_39                : 40;
	uint64_t size                         : 16;
	uint64_t pool                         : 3;
	uint64_t back                         : 4;
	uint64_t i                            : 1;
#endif
	} s;
	struct cvmx_pko_mem_debug11_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t i                            : 1;  /**< "I"  value used for free operation */
	uint64_t back                         : 4;  /**< Back value used for free operation */
	uint64_t pool                         : 3;  /**< Pool value used for free operation */
	uint64_t size                         : 16; /**< Size in bytes */
	uint64_t ptr                          : 40; /**< Data pointer */
#else
	uint64_t ptr                          : 40;
	uint64_t size                         : 16;
	uint64_t pool                         : 3;
	uint64_t back                         : 4;
	uint64_t i                            : 1;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug11_cn30xx    cn31xx;
	struct cvmx_pko_mem_debug11_cn30xx    cn38xx;
	struct cvmx_pko_mem_debug11_cn30xx    cn38xxp2;
	struct cvmx_pko_mem_debug11_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_23_63               : 41;
	uint64_t maj                          : 1;  /**< Internal state */
	uint64_t uid                          : 3;  /**< Internal state */
	uint64_t sop                          : 1;  /**< Internal state */
	uint64_t len                          : 1;  /**< Internal state */
	uint64_t chk                          : 1;  /**< Internal state */
	uint64_t cnt                          : 13; /**< Internal state */
	uint64_t mod                          : 3;  /**< Internal state */
#else
	uint64_t mod                          : 3;
	uint64_t cnt                          : 13;
	uint64_t chk                          : 1;
	uint64_t len                          : 1;
	uint64_t sop                          : 1;
	uint64_t uid                          : 3;
	uint64_t maj                          : 1;
	uint64_t reserved_23_63               : 41;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug11_cn50xx    cn52xx;
	struct cvmx_pko_mem_debug11_cn50xx    cn52xxp1;
	struct cvmx_pko_mem_debug11_cn50xx    cn56xx;
	struct cvmx_pko_mem_debug11_cn50xx    cn56xxp1;
	struct cvmx_pko_mem_debug11_cn50xx    cn58xx;
	struct cvmx_pko_mem_debug11_cn50xx    cn58xxp1;
	struct cvmx_pko_mem_debug11_cn50xx    cn63xx;
	struct cvmx_pko_mem_debug11_cn50xx    cn63xxp1;
};
typedef union cvmx_pko_mem_debug11 cvmx_pko_mem_debug11_t;

/**
 * cvmx_pko_mem_debug12
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko.out.ctl.cmnd[63:0]
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug12
{
	uint64_t u64;
	struct cvmx_pko_mem_debug12_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_0_63                : 64;
#else
	uint64_t reserved_0_63                : 64;
#endif
	} s;
	struct cvmx_pko_mem_debug12_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
#else
	uint64_t data                         : 64;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug12_cn30xx    cn31xx;
	struct cvmx_pko_mem_debug12_cn30xx    cn38xx;
	struct cvmx_pko_mem_debug12_cn30xx    cn38xxp2;
	struct cvmx_pko_mem_debug12_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t fau                          : 28; /**< Fetch and add command words */
	uint64_t cmd                          : 14; /**< Command word */
	uint64_t segs                         : 6;  /**< Number of segments/gather size */
	uint64_t size                         : 16; /**< Packet length in bytes */
#else
	uint64_t size                         : 16;
	uint64_t segs                         : 6;
	uint64_t cmd                          : 14;
	uint64_t fau                          : 28;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug12_cn50xx    cn52xx;
	struct cvmx_pko_mem_debug12_cn50xx    cn52xxp1;
	struct cvmx_pko_mem_debug12_cn50xx    cn56xx;
	struct cvmx_pko_mem_debug12_cn50xx    cn56xxp1;
	struct cvmx_pko_mem_debug12_cn50xx    cn58xx;
	struct cvmx_pko_mem_debug12_cn50xx    cn58xxp1;
	struct cvmx_pko_mem_debug12_cn50xx    cn63xx;
	struct cvmx_pko_mem_debug12_cn50xx    cn63xxp1;
};
typedef union cvmx_pko_mem_debug12 cvmx_pko_mem_debug12_t;

/**
 * cvmx_pko_mem_debug13
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko.out.ctl.head[63:0]
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug13
{
	uint64_t u64;
	struct cvmx_pko_mem_debug13_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t i                            : 1;  /**< "I"  value used for free operation */
	uint64_t back                         : 4;  /**< Back value used for free operation */
	uint64_t pool                         : 3;  /**< Pool value used for free operation */
	uint64_t reserved_0_55                : 56;
#else
	uint64_t reserved_0_55                : 56;
	uint64_t pool                         : 3;
	uint64_t back                         : 4;
	uint64_t i                            : 1;
#endif
	} s;
	struct cvmx_pko_mem_debug13_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_51_63               : 13;
	uint64_t widx                         : 17; /**< PDB widx */
	uint64_t ridx2                        : 17; /**< PDB ridx2 */
	uint64_t widx2                        : 17; /**< PDB widx2 */
#else
	uint64_t widx2                        : 17;
	uint64_t ridx2                        : 17;
	uint64_t widx                         : 17;
	uint64_t reserved_51_63               : 13;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug13_cn30xx    cn31xx;
	struct cvmx_pko_mem_debug13_cn30xx    cn38xx;
	struct cvmx_pko_mem_debug13_cn30xx    cn38xxp2;
	struct cvmx_pko_mem_debug13_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t i                            : 1;  /**< "I"  value used for free operation */
	uint64_t back                         : 4;  /**< Back value used for free operation */
	uint64_t pool                         : 3;  /**< Pool value used for free operation */
	uint64_t size                         : 16; /**< Size in bytes */
	uint64_t ptr                          : 40; /**< Data pointer */
#else
	uint64_t ptr                          : 40;
	uint64_t size                         : 16;
	uint64_t pool                         : 3;
	uint64_t back                         : 4;
	uint64_t i                            : 1;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug13_cn50xx    cn52xx;
	struct cvmx_pko_mem_debug13_cn50xx    cn52xxp1;
	struct cvmx_pko_mem_debug13_cn50xx    cn56xx;
	struct cvmx_pko_mem_debug13_cn50xx    cn56xxp1;
	struct cvmx_pko_mem_debug13_cn50xx    cn58xx;
	struct cvmx_pko_mem_debug13_cn50xx    cn58xxp1;
	struct cvmx_pko_mem_debug13_cn50xx    cn63xx;
	struct cvmx_pko_mem_debug13_cn50xx    cn63xxp1;
};
typedef union cvmx_pko_mem_debug13 cvmx_pko_mem_debug13_t;

/**
 * cvmx_pko_mem_debug14
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0]
 * This CSR is a memory of 132 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug14
{
	uint64_t u64;
	struct cvmx_pko_mem_debug14_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_0_63                : 64;
#else
	uint64_t reserved_0_63                : 64;
#endif
	} s;
	struct cvmx_pko_mem_debug14_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_17_63               : 47;
	uint64_t ridx                         : 17; /**< PDB ridx */
#else
	uint64_t ridx                         : 17;
	uint64_t reserved_17_63               : 47;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug14_cn30xx    cn31xx;
	struct cvmx_pko_mem_debug14_cn30xx    cn38xx;
	struct cvmx_pko_mem_debug14_cn30xx    cn38xxp2;
	struct cvmx_pko_mem_debug14_cn52xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t data                         : 64; /**< Command words */
#else
	uint64_t data                         : 64;
#endif
	} cn52xx;
	struct cvmx_pko_mem_debug14_cn52xx    cn52xxp1;
	struct cvmx_pko_mem_debug14_cn52xx    cn56xx;
	struct cvmx_pko_mem_debug14_cn52xx    cn56xxp1;
	struct cvmx_pko_mem_debug14_cn52xx    cn63xx;
	struct cvmx_pko_mem_debug14_cn52xx    cn63xxp1;
};
typedef union cvmx_pko_mem_debug14 cvmx_pko_mem_debug14_t;

/**
 * cvmx_pko_mem_debug2
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug2
{
	uint64_t u64;
	struct cvmx_pko_mem_debug2_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t i                            : 1;  /**< "I"  value used for free operation */
	uint64_t back                         : 4;  /**< Back value used for free operation */
	uint64_t pool                         : 3;  /**< Pool value used for free operation */
	uint64_t size                         : 16; /**< Size in bytes */
	uint64_t ptr                          : 40; /**< Data pointer */
#else
	uint64_t ptr                          : 40;
	uint64_t size                         : 16;
	uint64_t pool                         : 3;
	uint64_t back                         : 4;
	uint64_t i                            : 1;
#endif
	} s;
	struct cvmx_pko_mem_debug2_s          cn30xx;
	struct cvmx_pko_mem_debug2_s          cn31xx;
	struct cvmx_pko_mem_debug2_s          cn38xx;
	struct cvmx_pko_mem_debug2_s          cn38xxp2;
	struct cvmx_pko_mem_debug2_s          cn50xx;
	struct cvmx_pko_mem_debug2_s          cn52xx;
	struct cvmx_pko_mem_debug2_s          cn52xxp1;
	struct cvmx_pko_mem_debug2_s          cn56xx;
	struct cvmx_pko_mem_debug2_s          cn56xxp1;
	struct cvmx_pko_mem_debug2_s          cn58xx;
	struct cvmx_pko_mem_debug2_s          cn58xxp1;
	struct cvmx_pko_mem_debug2_s          cn63xx;
	struct cvmx_pko_mem_debug2_s          cn63xxp1;
};
typedef union cvmx_pko_mem_debug2 cvmx_pko_mem_debug2_t;

/**
 * cvmx_pko_mem_debug3
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug3
{
	uint64_t u64;
	struct cvmx_pko_mem_debug3_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_0_63                : 64;
#else
	uint64_t reserved_0_63                : 64;
#endif
	} s;
	struct cvmx_pko_mem_debug3_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t i                            : 1;  /**< "I"  value used for free operation */
	uint64_t back                         : 4;  /**< Back value used for free operation */
	uint64_t pool                         : 3;  /**< Pool value used for free operation */
	uint64_t size                         : 16; /**< Size in bytes */
	uint64_t ptr                          : 40; /**< Data pointer */
#else
	uint64_t ptr                          : 40;
	uint64_t size                         : 16;
	uint64_t pool                         : 3;
	uint64_t back                         : 4;
	uint64_t i                            : 1;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug3_cn30xx     cn31xx;
	struct cvmx_pko_mem_debug3_cn30xx     cn38xx;
	struct cvmx_pko_mem_debug3_cn30xx     cn38xxp2;
	struct cvmx_pko_mem_debug3_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
#else
	uint64_t data                         : 64;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug3_cn50xx     cn52xx;
	struct cvmx_pko_mem_debug3_cn50xx     cn52xxp1;
	struct cvmx_pko_mem_debug3_cn50xx     cn56xx;
	struct cvmx_pko_mem_debug3_cn50xx     cn56xxp1;
	struct cvmx_pko_mem_debug3_cn50xx     cn58xx;
	struct cvmx_pko_mem_debug3_cn50xx     cn58xxp1;
	struct cvmx_pko_mem_debug3_cn50xx     cn63xx;
	struct cvmx_pko_mem_debug3_cn50xx     cn63xxp1;
};
typedef union cvmx_pko_mem_debug3 cvmx_pko_mem_debug3_t;

/**
 * cvmx_pko_mem_debug4
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug4
{
	uint64_t u64;
	struct cvmx_pko_mem_debug4_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_0_63                : 64;
#else
	uint64_t reserved_0_63                : 64;
#endif
	} s;
	struct cvmx_pko_mem_debug4_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t data                         : 64; /**< WorkQ data or Store0 pointer */
#else
	uint64_t data                         : 64;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug4_cn30xx     cn31xx;
	struct cvmx_pko_mem_debug4_cn30xx     cn38xx;
	struct cvmx_pko_mem_debug4_cn30xx     cn38xxp2;
	struct cvmx_pko_mem_debug4_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t cmnd_segs                    : 3;  /**< Internal state */
	uint64_t cmnd_siz                     : 16; /**< Internal state */
	uint64_t cmnd_off                     : 6;  /**< Internal state */
	uint64_t uid                          : 3;  /**< Internal state */
	uint64_t dread_sop                    : 1;  /**< Internal state */
	uint64_t init_dwrite                  : 1;  /**< Internal state */
	uint64_t chk_once                     : 1;  /**< Internal state */
	uint64_t chk_mode                     : 1;  /**< Internal state */
	uint64_t active                       : 1;  /**< Internal state */
	uint64_t static_p                     : 1;  /**< Internal state */
	uint64_t qos                          : 3;  /**< Internal state */
	uint64_t qcb_ridx                     : 5;  /**< Internal state */
	uint64_t qid_off_max                  : 4;  /**< Internal state */
	uint64_t qid_off                      : 4;  /**< Internal state */
	uint64_t qid_base                     : 8;  /**< Internal state */
	uint64_t wait                         : 1;  /**< Internal state */
	uint64_t minor                        : 2;  /**< Internal state */
	uint64_t major                        : 3;  /**< Internal state */
#else
	uint64_t major                        : 3;
	uint64_t minor                        : 2;
	uint64_t wait                         : 1;
	uint64_t qid_base                     : 8;
	uint64_t qid_off                      : 4;
	uint64_t qid_off_max                  : 4;
	uint64_t qcb_ridx                     : 5;
	uint64_t qos                          : 3;
	uint64_t static_p                     : 1;
	uint64_t active                       : 1;
	uint64_t chk_mode                     : 1;
	uint64_t chk_once                     : 1;
	uint64_t init_dwrite                  : 1;
	uint64_t dread_sop                    : 1;
	uint64_t uid                          : 3;
	uint64_t cmnd_off                     : 6;
	uint64_t cmnd_siz                     : 16;
	uint64_t cmnd_segs                    : 3;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug4_cn52xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t curr_siz                     : 8;  /**< Internal state */
	uint64_t curr_off                     : 16; /**< Internal state */
	uint64_t cmnd_segs                    : 6;  /**< Internal state */
	uint64_t cmnd_siz                     : 16; /**< Internal state */
	uint64_t cmnd_off                     : 6;  /**< Internal state */
	uint64_t uid                          : 2;  /**< Internal state */
	uint64_t dread_sop                    : 1;  /**< Internal state */
	uint64_t init_dwrite                  : 1;  /**< Internal state */
	uint64_t chk_once                     : 1;  /**< Internal state */
	uint64_t chk_mode                     : 1;  /**< Internal state */
	uint64_t wait                         : 1;  /**< Internal state */
	uint64_t minor                        : 2;  /**< Internal state */
	uint64_t major                        : 3;  /**< Internal state */
#else
	uint64_t major                        : 3;
	uint64_t minor                        : 2;
	uint64_t wait                         : 1;
	uint64_t chk_mode                     : 1;
	uint64_t chk_once                     : 1;
	uint64_t init_dwrite                  : 1;
	uint64_t dread_sop                    : 1;
	uint64_t uid                          : 2;
	uint64_t cmnd_off                     : 6;
	uint64_t cmnd_siz                     : 16;
	uint64_t cmnd_segs                    : 6;
	uint64_t curr_off                     : 16;
	uint64_t curr_siz                     : 8;
#endif
	} cn52xx;
	struct cvmx_pko_mem_debug4_cn52xx     cn52xxp1;
	struct cvmx_pko_mem_debug4_cn52xx     cn56xx;
	struct cvmx_pko_mem_debug4_cn52xx     cn56xxp1;
	struct cvmx_pko_mem_debug4_cn50xx     cn58xx;
	struct cvmx_pko_mem_debug4_cn50xx     cn58xxp1;
	struct cvmx_pko_mem_debug4_cn52xx     cn63xx;
	struct cvmx_pko_mem_debug4_cn52xx     cn63xxp1;
};
typedef union cvmx_pko_mem_debug4 cvmx_pko_mem_debug4_t;

/**
 * cvmx_pko_mem_debug5
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64]
 * This CSR is a memory of 12 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug5
{
	uint64_t u64;
	struct cvmx_pko_mem_debug5_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_0_63                : 64;
#else
	uint64_t reserved_0_63                : 64;
#endif
	} s;
	struct cvmx_pko_mem_debug5_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t dwri_mod                     : 1;  /**< Dwrite mod */
	uint64_t dwri_sop                     : 1;  /**< Dwrite sop needed */
	uint64_t dwri_len                     : 1;  /**< Dwrite len */
	uint64_t dwri_cnt                     : 13; /**< Dwrite count */
	uint64_t cmnd_siz                     : 16; /**< Copy of cmnd.size */
	uint64_t uid                          : 1;  /**< UID */
	uint64_t xfer_wor                     : 1;  /**< Transfer work needed */
	uint64_t xfer_dwr                     : 1;  /**< Transfer dwrite needed */
	uint64_t cbuf_fre                     : 1;  /**< Cbuf needs free */
	uint64_t reserved_27_27               : 1;
	uint64_t chk_mode                     : 1;  /**< Checksum mode */
	uint64_t active                       : 1;  /**< Port is active */
	uint64_t qos                          : 3;  /**< Current QOS round */
	uint64_t qcb_ridx                     : 5;  /**< Buffer read  index for QCB */
	uint64_t qid_off                      : 3;  /**< Offset to be added to QID_BASE for current queue */
	uint64_t qid_base                     : 7;  /**< Absolute QID of the queue array base = &QUEUES[0] */
	uint64_t wait                         : 1;  /**< State wait when set */
	uint64_t minor                        : 2;  /**< State minor code */
	uint64_t major                        : 4;  /**< State major code */
#else
	uint64_t major                        : 4;
	uint64_t minor                        : 2;
	uint64_t wait                         : 1;
	uint64_t qid_base                     : 7;
	uint64_t qid_off                      : 3;
	uint64_t qcb_ridx                     : 5;
	uint64_t qos                          : 3;
	uint64_t active                       : 1;
	uint64_t chk_mode                     : 1;
	uint64_t reserved_27_27               : 1;
	uint64_t cbuf_fre                     : 1;
	uint64_t xfer_dwr                     : 1;
	uint64_t xfer_wor                     : 1;
	uint64_t uid                          : 1;
	uint64_t cmnd_siz                     : 16;
	uint64_t dwri_cnt                     : 13;
	uint64_t dwri_len                     : 1;
	uint64_t dwri_sop                     : 1;
	uint64_t dwri_mod                     : 1;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug5_cn30xx     cn31xx;
	struct cvmx_pko_mem_debug5_cn30xx     cn38xx;
	struct cvmx_pko_mem_debug5_cn30xx     cn38xxp2;
	struct cvmx_pko_mem_debug5_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t curr_ptr                     : 29; /**< Internal state */
	uint64_t curr_siz                     : 16; /**< Internal state */
	uint64_t curr_off                     : 16; /**< Internal state */
	uint64_t cmnd_segs                    : 3;  /**< Internal state */
#else
	uint64_t cmnd_segs                    : 3;
	uint64_t curr_off                     : 16;
	uint64_t curr_siz                     : 16;
	uint64_t curr_ptr                     : 29;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug5_cn52xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_54_63               : 10;
	uint64_t nxt_inflt                    : 6;  /**< Internal state */
	uint64_t curr_ptr                     : 40; /**< Internal state */
	uint64_t curr_siz                     : 8;  /**< Internal state */
#else
	uint64_t curr_siz                     : 8;
	uint64_t curr_ptr                     : 40;
	uint64_t nxt_inflt                    : 6;
	uint64_t reserved_54_63               : 10;
#endif
	} cn52xx;
	struct cvmx_pko_mem_debug5_cn52xx     cn52xxp1;
	struct cvmx_pko_mem_debug5_cn52xx     cn56xx;
	struct cvmx_pko_mem_debug5_cn52xx     cn56xxp1;
	struct cvmx_pko_mem_debug5_cn50xx     cn58xx;
	struct cvmx_pko_mem_debug5_cn50xx     cn58xxp1;
	struct cvmx_pko_mem_debug5_cn63xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_56_63               : 8;
	uint64_t ptp                          : 1;  /**< Internal state */
	uint64_t major_3                      : 1;  /**< Internal state */
	uint64_t nxt_inflt                    : 6;  /**< Internal state */
	uint64_t curr_ptr                     : 40; /**< Internal state */
	uint64_t curr_siz                     : 8;  /**< Internal state */
#else
	uint64_t curr_siz                     : 8;
	uint64_t curr_ptr                     : 40;
	uint64_t nxt_inflt                    : 6;
	uint64_t major_3                      : 1;
	uint64_t ptp                          : 1;
	uint64_t reserved_56_63               : 8;
#endif
	} cn63xx;
	struct cvmx_pko_mem_debug5_cn63xx     cn63xxp1;
};
typedef union cvmx_pko_mem_debug5 cvmx_pko_mem_debug5_t;

/**
 * cvmx_pko_mem_debug6
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0]
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug6
{
	uint64_t u64;
	struct cvmx_pko_mem_debug6_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_37_63               : 27;
	uint64_t qid_offres                   : 4;  /**< Internal state */
	uint64_t qid_offths                   : 4;  /**< Internal state */
	uint64_t preempter                    : 1;  /**< Internal state */
	uint64_t preemptee                    : 1;  /**< Internal state */
	uint64_t preempted                    : 1;  /**< Internal state */
	uint64_t active                       : 1;  /**< Internal state */
	uint64_t statc                        : 1;  /**< Internal state */
	uint64_t qos                          : 3;  /**< Internal state */
	uint64_t qcb_ridx                     : 5;  /**< Internal state */
	uint64_t qid_offmax                   : 4;  /**< Internal state */
	uint64_t reserved_0_11                : 12;
#else
	uint64_t reserved_0_11                : 12;
	uint64_t qid_offmax                   : 4;
	uint64_t qcb_ridx                     : 5;
	uint64_t qos                          : 3;
	uint64_t statc                        : 1;
	uint64_t active                       : 1;
	uint64_t preempted                    : 1;
	uint64_t preemptee                    : 1;
	uint64_t preempter                    : 1;
	uint64_t qid_offths                   : 4;
	uint64_t qid_offres                   : 4;
	uint64_t reserved_37_63               : 27;
#endif
	} s;
	struct cvmx_pko_mem_debug6_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_11_63               : 53;
	uint64_t qid_offm                     : 3;  /**< Qid offset max */
	uint64_t static_p                     : 1;  /**< Static port when set */
	uint64_t work_min                     : 3;  /**< Work minor */
	uint64_t dwri_chk                     : 1;  /**< Dwrite checksum mode */
	uint64_t dwri_uid                     : 1;  /**< Dwrite UID */
	uint64_t dwri_mod                     : 2;  /**< Dwrite mod */
#else
	uint64_t dwri_mod                     : 2;
	uint64_t dwri_uid                     : 1;
	uint64_t dwri_chk                     : 1;
	uint64_t work_min                     : 3;
	uint64_t static_p                     : 1;
	uint64_t qid_offm                     : 3;
	uint64_t reserved_11_63               : 53;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug6_cn30xx     cn31xx;
	struct cvmx_pko_mem_debug6_cn30xx     cn38xx;
	struct cvmx_pko_mem_debug6_cn30xx     cn38xxp2;
	struct cvmx_pko_mem_debug6_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_11_63               : 53;
	uint64_t curr_ptr                     : 11; /**< Internal state */
#else
	uint64_t curr_ptr                     : 11;
	uint64_t reserved_11_63               : 53;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug6_cn52xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_37_63               : 27;
	uint64_t qid_offres                   : 4;  /**< Internal state */
	uint64_t qid_offths                   : 4;  /**< Internal state */
	uint64_t preempter                    : 1;  /**< Internal state */
	uint64_t preemptee                    : 1;  /**< Internal state */
	uint64_t preempted                    : 1;  /**< Internal state */
	uint64_t active                       : 1;  /**< Internal state */
	uint64_t statc                        : 1;  /**< Internal state */
	uint64_t qos                          : 3;  /**< Internal state */
	uint64_t qcb_ridx                     : 5;  /**< Internal state */
	uint64_t qid_offmax                   : 4;  /**< Internal state */
	uint64_t qid_off                      : 4;  /**< Internal state */
	uint64_t qid_base                     : 8;  /**< Internal state */
#else
	uint64_t qid_base                     : 8;
	uint64_t qid_off                      : 4;
	uint64_t qid_offmax                   : 4;
	uint64_t qcb_ridx                     : 5;
	uint64_t qos                          : 3;
	uint64_t statc                        : 1;
	uint64_t active                       : 1;
	uint64_t preempted                    : 1;
	uint64_t preemptee                    : 1;
	uint64_t preempter                    : 1;
	uint64_t qid_offths                   : 4;
	uint64_t qid_offres                   : 4;
	uint64_t reserved_37_63               : 27;
#endif
	} cn52xx;
	struct cvmx_pko_mem_debug6_cn52xx     cn52xxp1;
	struct cvmx_pko_mem_debug6_cn52xx     cn56xx;
	struct cvmx_pko_mem_debug6_cn52xx     cn56xxp1;
	struct cvmx_pko_mem_debug6_cn50xx     cn58xx;
	struct cvmx_pko_mem_debug6_cn50xx     cn58xxp1;
	struct cvmx_pko_mem_debug6_cn52xx     cn63xx;
	struct cvmx_pko_mem_debug6_cn52xx     cn63xxp1;
};
typedef union cvmx_pko_mem_debug6 cvmx_pko_mem_debug6_t;

/**
 * cvmx_pko_mem_debug7
 *
 * Notes:
 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0]
 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug7
{
	uint64_t u64;
	struct cvmx_pko_mem_debug7_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
	uint64_t reserved_0_57                : 58;
#else
	uint64_t reserved_0_57                : 58;
	uint64_t tail                         : 1;
	uint64_t qos                          : 5;
#endif
	} s;
	struct cvmx_pko_mem_debug7_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_58_63               : 6;
	uint64_t dwb                          : 9;  /**< Calculated DWB count used for free operation */
	uint64_t start                        : 33; /**< Calculated start address used for free operation */
	uint64_t size                         : 16; /**< Packet length in bytes */
#else
	uint64_t size                         : 16;
	uint64_t start                        : 33;
	uint64_t dwb                          : 9;
	uint64_t reserved_58_63               : 6;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug7_cn30xx     cn31xx;
	struct cvmx_pko_mem_debug7_cn30xx     cn38xx;
	struct cvmx_pko_mem_debug7_cn30xx     cn38xxp2;
	struct cvmx_pko_mem_debug7_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
	uint64_t buf_ptr                      : 33; /**< Command word pointer */
	uint64_t qcb_widx                     : 6;  /**< Buffer write index for QCB */
	uint64_t qcb_ridx                     : 6;  /**< Buffer read  index for QCB */
#else
	uint64_t qcb_ridx                     : 6;
	uint64_t qcb_widx                     : 6;
	uint64_t buf_ptr                      : 33;
	uint64_t buf_siz                      : 13;
	uint64_t tail                         : 1;
	uint64_t qos                          : 5;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug7_cn50xx     cn52xx;
	struct cvmx_pko_mem_debug7_cn50xx     cn52xxp1;
	struct cvmx_pko_mem_debug7_cn50xx     cn56xx;
	struct cvmx_pko_mem_debug7_cn50xx     cn56xxp1;
	struct cvmx_pko_mem_debug7_cn50xx     cn58xx;
	struct cvmx_pko_mem_debug7_cn50xx     cn58xxp1;
	struct cvmx_pko_mem_debug7_cn50xx     cn63xx;
	struct cvmx_pko_mem_debug7_cn50xx     cn63xxp1;
};
typedef union cvmx_pko_mem_debug7 cvmx_pko_mem_debug7_t;

/**
 * cvmx_pko_mem_debug8
 *
 * Notes:
 * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64]
 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug8
{
	uint64_t u64;
	struct cvmx_pko_mem_debug8_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_59_63               : 5;
	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
	uint64_t reserved_0_44                : 45;
#else
	uint64_t reserved_0_44                : 45;
	uint64_t buf_siz                      : 13;
	uint64_t tail                         : 1;
	uint64_t reserved_59_63               : 5;
#endif
	} s;
	struct cvmx_pko_mem_debug8_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t qos                          : 5;  /**< QOS mask to enable the queue when set */
	uint64_t tail                         : 1;  /**< This queue is the last (tail) in the queue array */
	uint64_t buf_siz                      : 13; /**< Command buffer remaining size in words */
	uint64_t buf_ptr                      : 33; /**< Command word pointer */
	uint64_t qcb_widx                     : 6;  /**< Buffer write index for QCB */
	uint64_t qcb_ridx                     : 6;  /**< Buffer read  index for QCB */
#else
	uint64_t qcb_ridx                     : 6;
	uint64_t qcb_widx                     : 6;
	uint64_t buf_ptr                      : 33;
	uint64_t buf_siz                      : 13;
	uint64_t tail                         : 1;
	uint64_t qos                          : 5;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug8_cn30xx     cn31xx;
	struct cvmx_pko_mem_debug8_cn30xx     cn38xx;
	struct cvmx_pko_mem_debug8_cn30xx     cn38xxp2;
	struct cvmx_pko_mem_debug8_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_28_63               : 36;
	uint64_t doorbell                     : 20; /**< Doorbell count */
	uint64_t reserved_6_7                 : 2;
	uint64_t static_p                     : 1;  /**< Static priority */
	uint64_t s_tail                       : 1;  /**< Static tail */
	uint64_t static_q                     : 1;  /**< Static priority */
	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
#else
	uint64_t qos                          : 3;
	uint64_t static_q                     : 1;
	uint64_t s_tail                       : 1;
	uint64_t static_p                     : 1;
	uint64_t reserved_6_7                 : 2;
	uint64_t doorbell                     : 20;
	uint64_t reserved_28_63               : 36;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug8_cn52xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_29_63               : 35;
	uint64_t preempter                    : 1;  /**< Preempter */
	uint64_t doorbell                     : 20; /**< Doorbell count */
	uint64_t reserved_7_7                 : 1;
	uint64_t preemptee                    : 1;  /**< Preemptee */
	uint64_t static_p                     : 1;  /**< Static priority */
	uint64_t s_tail                       : 1;  /**< Static tail */
	uint64_t static_q                     : 1;  /**< Static priority */
	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
#else
	uint64_t qos                          : 3;
	uint64_t static_q                     : 1;
	uint64_t s_tail                       : 1;
	uint64_t static_p                     : 1;
	uint64_t preemptee                    : 1;
	uint64_t reserved_7_7                 : 1;
	uint64_t doorbell                     : 20;
	uint64_t preempter                    : 1;
	uint64_t reserved_29_63               : 35;
#endif
	} cn52xx;
	struct cvmx_pko_mem_debug8_cn52xx     cn52xxp1;
	struct cvmx_pko_mem_debug8_cn52xx     cn56xx;
	struct cvmx_pko_mem_debug8_cn52xx     cn56xxp1;
	struct cvmx_pko_mem_debug8_cn50xx     cn58xx;
	struct cvmx_pko_mem_debug8_cn50xx     cn58xxp1;
	struct cvmx_pko_mem_debug8_cn52xx     cn63xx;
	struct cvmx_pko_mem_debug8_cn52xx     cn63xxp1;
};
typedef union cvmx_pko_mem_debug8 cvmx_pko_mem_debug8_t;

/**
 * cvmx_pko_mem_debug9
 *
 * Notes:
 * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs0, pko.dat.ptr.ptrs3
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.
 */
union cvmx_pko_mem_debug9
{
	uint64_t u64;
	struct cvmx_pko_mem_debug9_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_49_63               : 15;
	uint64_t ptrs0                        : 17; /**< Internal state */
	uint64_t reserved_0_31                : 32;
#else
	uint64_t reserved_0_31                : 32;
	uint64_t ptrs0                        : 17;
	uint64_t reserved_49_63               : 15;
#endif
	} s;
	struct cvmx_pko_mem_debug9_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_28_63               : 36;
	uint64_t doorbell                     : 20; /**< Doorbell count */
	uint64_t reserved_5_7                 : 3;
	uint64_t s_tail                       : 1;  /**< reads as zero (S_TAIL cannot be read) */
	uint64_t static_q                     : 1;  /**< reads as zero (STATIC_Q cannot be read) */
	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
#else
	uint64_t qos                          : 3;
	uint64_t static_q                     : 1;
	uint64_t s_tail                       : 1;
	uint64_t reserved_5_7                 : 3;
	uint64_t doorbell                     : 20;
	uint64_t reserved_28_63               : 36;
#endif
	} cn30xx;
	struct cvmx_pko_mem_debug9_cn30xx     cn31xx;
	struct cvmx_pko_mem_debug9_cn38xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_28_63               : 36;
	uint64_t doorbell                     : 20; /**< Doorbell count */
	uint64_t reserved_6_7                 : 2;
	uint64_t static_p                     : 1;  /**< Static priority (port) */
	uint64_t s_tail                       : 1;  /**< Static tail */
	uint64_t static_q                     : 1;  /**< Static priority */
	uint64_t qos                          : 3;  /**< QOS mask to enable the queue when set */
#else
	uint64_t qos                          : 3;
	uint64_t static_q                     : 1;
	uint64_t s_tail                       : 1;
	uint64_t static_p                     : 1;
	uint64_t reserved_6_7                 : 2;
	uint64_t doorbell                     : 20;
	uint64_t reserved_28_63               : 36;
#endif
	} cn38xx;
	struct cvmx_pko_mem_debug9_cn38xx     cn38xxp2;
	struct cvmx_pko_mem_debug9_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_49_63               : 15;
	uint64_t ptrs0                        : 17; /**< Internal state */
	uint64_t reserved_17_31               : 15;
	uint64_t ptrs3                        : 17; /**< Internal state */
#else
	uint64_t ptrs3                        : 17;
	uint64_t reserved_17_31               : 15;
	uint64_t ptrs0                        : 17;
	uint64_t reserved_49_63               : 15;
#endif
	} cn50xx;
	struct cvmx_pko_mem_debug9_cn50xx     cn52xx;
	struct cvmx_pko_mem_debug9_cn50xx     cn52xxp1;
	struct cvmx_pko_mem_debug9_cn50xx     cn56xx;
	struct cvmx_pko_mem_debug9_cn50xx     cn56xxp1;
	struct cvmx_pko_mem_debug9_cn50xx     cn58xx;
	struct cvmx_pko_mem_debug9_cn50xx     cn58xxp1;
	struct cvmx_pko_mem_debug9_cn50xx     cn63xx;
	struct cvmx_pko_mem_debug9_cn50xx     cn63xxp1;
};
typedef union cvmx_pko_mem_debug9 cvmx_pko_mem_debug9_t;

/**
 * cvmx_pko_mem_port_ptrs
 *
 * Notes:
 * Sets the port to engine mapping, per port.  Ports marked as static priority need not be contiguous,
 * but they must be the lowest numbered PIDs mapped to this EID and must have QOS_MASK=0xff.  If EID==8
 * or EID==9, then PID[1:0] is used to direct the packet to the correct port on that interface.
 * EID==15 can be used for unused PKO-internal ports.
 * BP_PORT==63 means that the PKO-internal port is not backpressured.
 * BP_PORTs are assumed to belong to an interface as follows:
 *   42 <= BP_PORT < 44 -> srio       interface 1
 *   40 <= BP_PORT < 42 -> srio       interface 0
 *   36 <= BP_PORT < 40 -> loopback   interface
 *   32 <= BP_PORT < 36 -> PCIe       interface
 *   0  <= BP_PORT < 16 -> SGMII/Xaui interface 0
 *
 * Note that the SRIO interfaces do not actually provide backpressure.  Thus, ports that use
 * 40 <= BP_PORT < 44 for backpressure will never be backpressured.
 *
 * The reset configuration is the following:
 *   PID EID(ext port) BP_PORT QOS_MASK STATIC_P
 *   -------------------------------------------
 *     0   0( 0)             0     0xff        0
 *     1   1( 1)             1     0xff        0
 *     2   2( 2)             2     0xff        0
 *     3   3( 3)             3     0xff        0
 *     4   0( 0)             4     0xff        0
 *     5   1( 1)             5     0xff        0
 *     6   2( 2)             6     0xff        0
 *     7   3( 3)             7     0xff        0
 *     8   0( 0)             8     0xff        0
 *     9   1( 1)             9     0xff        0
 *    10   2( 2)            10     0xff        0
 *    11   3( 3)            11     0xff        0
 *    12   0( 0)            12     0xff        0
 *    13   1( 1)            13     0xff        0
 *    14   2( 2)            14     0xff        0
 *    15   3( 3)            15     0xff        0
 *   -------------------------------------------
 *    16   0( 0)             0     0xff        0
 *    17   1( 1)             1     0xff        0
 *    18   2( 2)             2     0xff        0
 *    19   3( 3)             3     0xff        0
 *    20   0( 0)             4     0xff        0
 *    21   1( 1)             5     0xff        0
 *    22   2( 2)             6     0xff        0
 *    23   3( 3)             7     0xff        0
 *    24   0( 0)             8     0xff        0
 *    25   1( 1)             9     0xff        0
 *    26   2( 2)            10     0xff        0
 *    27   3( 3)            11     0xff        0
 *    28   0( 0)            12     0xff        0
 *    29   1( 1)            13     0xff        0
 *    30   2( 2)            14     0xff        0
 *    31   3( 3)            15     0xff        0
 *   -------------------------------------------
 *    32   8(32)            32     0xff        0
 *    33   8(33)            33     0xff        0
 *    34   8(34)            34     0xff        0
 *    35   8(35)            35     0xff        0
 *   -------------------------------------------
 *    36   9(36)            36     0xff        0
 *    37   9(37)            37     0xff        0
 *    38   9(38)            38     0xff        0
 *    39   9(39)            39     0xff        0
 *   -------------------------------------------
 *    40  10(40)            40     0xff        0
 *    41  10(41)            41     0xff        0
 *   -------------------------------------------
 *    42  11(42)            42     0xff        0
 *    43  11(43)            43     0xff        0
 *
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_port_ptrs
{
	uint64_t u64;
	struct cvmx_pko_mem_port_ptrs_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_62_63               : 2;
	uint64_t static_p                     : 1;  /**< Set if this PID has static priority */
	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
	uint64_t reserved_16_52               : 37;
	uint64_t bp_port                      : 6;  /**< PID listens to BP_PORT for per-packet backpressure
                                                         Legal BP_PORTs: 0-15, 32-43, 63 (63 means no BP) */
	uint64_t eid                          : 4;  /**< Engine ID to which this port is mapped
                                                         Legal EIDs: 0-3, 8-11, 15 (15 only if port not used) */
	uint64_t pid                          : 6;  /**< Port ID[5:0] */
#else
	uint64_t pid                          : 6;
	uint64_t eid                          : 4;
	uint64_t bp_port                      : 6;
	uint64_t reserved_16_52               : 37;
	uint64_t qos_mask                     : 8;
	uint64_t static_p                     : 1;
	uint64_t reserved_62_63               : 2;
#endif
	} s;
	struct cvmx_pko_mem_port_ptrs_s       cn52xx;
	struct cvmx_pko_mem_port_ptrs_s       cn52xxp1;
	struct cvmx_pko_mem_port_ptrs_s       cn56xx;
	struct cvmx_pko_mem_port_ptrs_s       cn56xxp1;
	struct cvmx_pko_mem_port_ptrs_s       cn63xx;
	struct cvmx_pko_mem_port_ptrs_s       cn63xxp1;
};
typedef union cvmx_pko_mem_port_ptrs cvmx_pko_mem_port_ptrs_t;

/**
 * cvmx_pko_mem_port_qos
 *
 * Notes:
 * Sets the QOS mask, per port.  These QOS_MASK bits are logically and physically the same QOS_MASK
 * bits in PKO_MEM_PORT_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
 * operation without affecting any other port state.  The engine to which port PID is mapped is engine
 * EID.  Note that the port to engine mapping must be the same as was previously programmed via the
 * PKO_MEM_PORT_PTRS CSR.
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_port_qos
{
	uint64_t u64;
	struct cvmx_pko_mem_port_qos_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_61_63               : 3;
	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
	uint64_t reserved_10_52               : 43;
	uint64_t eid                          : 4;  /**< Engine ID to which this port is mapped
                                                         Legal EIDs: 0-3, 8-11 */
	uint64_t pid                          : 6;  /**< Port ID[5:0] */
#else
	uint64_t pid                          : 6;
	uint64_t eid                          : 4;
	uint64_t reserved_10_52               : 43;
	uint64_t qos_mask                     : 8;
	uint64_t reserved_61_63               : 3;
#endif
	} s;
	struct cvmx_pko_mem_port_qos_s        cn52xx;
	struct cvmx_pko_mem_port_qos_s        cn52xxp1;
	struct cvmx_pko_mem_port_qos_s        cn56xx;
	struct cvmx_pko_mem_port_qos_s        cn56xxp1;
	struct cvmx_pko_mem_port_qos_s        cn63xx;
	struct cvmx_pko_mem_port_qos_s        cn63xxp1;
};
typedef union cvmx_pko_mem_port_qos cvmx_pko_mem_port_qos_t;

/**
 * cvmx_pko_mem_port_rate0
 *
 * Notes:
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_port_rate0
{
	uint64_t u64;
	struct cvmx_pko_mem_port_rate0_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_51_63               : 13;
	uint64_t rate_word                    : 19; /**< Rate limiting adder per 8 byte */
	uint64_t rate_pkt                     : 24; /**< Rate limiting adder per packet */
	uint64_t reserved_6_7                 : 2;
	uint64_t pid                          : 6;  /**< Port ID[5:0] */
#else
	uint64_t pid                          : 6;
	uint64_t reserved_6_7                 : 2;
	uint64_t rate_pkt                     : 24;
	uint64_t rate_word                    : 19;
	uint64_t reserved_51_63               : 13;
#endif
	} s;
	struct cvmx_pko_mem_port_rate0_s      cn52xx;
	struct cvmx_pko_mem_port_rate0_s      cn52xxp1;
	struct cvmx_pko_mem_port_rate0_s      cn56xx;
	struct cvmx_pko_mem_port_rate0_s      cn56xxp1;
	struct cvmx_pko_mem_port_rate0_s      cn63xx;
	struct cvmx_pko_mem_port_rate0_s      cn63xxp1;
};
typedef union cvmx_pko_mem_port_rate0 cvmx_pko_mem_port_rate0_t;

/**
 * cvmx_pko_mem_port_rate1
 *
 * Notes:
 * Writing PKO_MEM_PORT_RATE1[PID,RATE_LIM] has the side effect of setting the corresponding
 * accumulator to zero.
 * This CSR is a memory of 44 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_port_rate1
{
	uint64_t u64;
	struct cvmx_pko_mem_port_rate1_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_32_63               : 32;
	uint64_t rate_lim                     : 24; /**< Rate limiting accumulator limit */
	uint64_t reserved_6_7                 : 2;
	uint64_t pid                          : 6;  /**< Port ID[5:0] */
#else
	uint64_t pid                          : 6;
	uint64_t reserved_6_7                 : 2;
	uint64_t rate_lim                     : 24;
	uint64_t reserved_32_63               : 32;
#endif
	} s;
	struct cvmx_pko_mem_port_rate1_s      cn52xx;
	struct cvmx_pko_mem_port_rate1_s      cn52xxp1;
	struct cvmx_pko_mem_port_rate1_s      cn56xx;
	struct cvmx_pko_mem_port_rate1_s      cn56xxp1;
	struct cvmx_pko_mem_port_rate1_s      cn63xx;
	struct cvmx_pko_mem_port_rate1_s      cn63xxp1;
};
typedef union cvmx_pko_mem_port_rate1 cvmx_pko_mem_port_rate1_t;

/**
 * cvmx_pko_mem_queue_ptrs
 *
 * Notes:
 * Sets the queue to port mapping and the initial command buffer pointer, per queue
 * Each queue may map to at most one port.  No more than 16 queues may map to a port.  The set of
 * queues that is mapped to a port must be a contiguous array of queues.  The port to which queue QID
 * is mapped is port PID.  The index of queue QID in port PID's queue list is IDX.  The last queue in
 * port PID's queue array must have its TAIL bit set.  Unused queues must be mapped to port 63.
 * STATIC_Q marks queue QID as having static priority.  STATIC_P marks the port PID to which QID is
 * mapped as having at least one queue with static priority.  If any QID that maps to PID has static
 * priority, then all QID that map to PID must have STATIC_P set.  Queues marked as static priority
 * must be contiguous and begin at IDX 0.  The last queue that is marked as having static priority
 * must have its S_TAIL bit set.
 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_queue_ptrs
{
	uint64_t u64;
	struct cvmx_pko_mem_queue_ptrs_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t s_tail                       : 1;  /**< Set if this QID is the tail of the static queues */
	uint64_t static_p                     : 1;  /**< Set if any QID in this PID has static priority */
	uint64_t static_q                     : 1;  /**< Set if this QID has static priority */
	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
	uint64_t buf_ptr                      : 36; /**< Command buffer pointer, <23:17> MBZ */
	uint64_t tail                         : 1;  /**< Set if this QID is the tail of the queue array */
	uint64_t index                        : 3;  /**< Index[2:0] (distance from head) in the queue array */
	uint64_t port                         : 6;  /**< Port ID to which this queue is mapped */
	uint64_t queue                        : 7;  /**< Queue ID[6:0] */
#else
	uint64_t queue                        : 7;
	uint64_t port                         : 6;
	uint64_t index                        : 3;
	uint64_t tail                         : 1;
	uint64_t buf_ptr                      : 36;
	uint64_t qos_mask                     : 8;
	uint64_t static_q                     : 1;
	uint64_t static_p                     : 1;
	uint64_t s_tail                       : 1;
#endif
	} s;
	struct cvmx_pko_mem_queue_ptrs_s      cn30xx;
	struct cvmx_pko_mem_queue_ptrs_s      cn31xx;
	struct cvmx_pko_mem_queue_ptrs_s      cn38xx;
	struct cvmx_pko_mem_queue_ptrs_s      cn38xxp2;
	struct cvmx_pko_mem_queue_ptrs_s      cn50xx;
	struct cvmx_pko_mem_queue_ptrs_s      cn52xx;
	struct cvmx_pko_mem_queue_ptrs_s      cn52xxp1;
	struct cvmx_pko_mem_queue_ptrs_s      cn56xx;
	struct cvmx_pko_mem_queue_ptrs_s      cn56xxp1;
	struct cvmx_pko_mem_queue_ptrs_s      cn58xx;
	struct cvmx_pko_mem_queue_ptrs_s      cn58xxp1;
	struct cvmx_pko_mem_queue_ptrs_s      cn63xx;
	struct cvmx_pko_mem_queue_ptrs_s      cn63xxp1;
};
typedef union cvmx_pko_mem_queue_ptrs cvmx_pko_mem_queue_ptrs_t;

/**
 * cvmx_pko_mem_queue_qos
 *
 * Notes:
 * Sets the QOS mask, per queue.  These QOS_MASK bits are logically and physically the same QOS_MASK
 * bits in PKO_MEM_QUEUE_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
 * operation without affecting any other queue state.  The port to which queue QID is mapped is port
 * PID.  Note that the queue to port mapping must be the same as was previously programmed via the
 * PKO_MEM_QUEUE_PTRS CSR.
 * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
 * CSR read operations to this address can be performed.  A read of any entry that has not been
 * previously written is illegal and will result in unpredictable CSR read data.
 */
union cvmx_pko_mem_queue_qos
{
	uint64_t u64;
	struct cvmx_pko_mem_queue_qos_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_61_63               : 3;
	uint64_t qos_mask                     : 8;  /**< Mask to control priority across 8 QOS rounds */
	uint64_t reserved_13_52               : 40;
	uint64_t pid                          : 6;  /**< Port ID to which this queue is mapped */
	uint64_t qid                          : 7;  /**< Queue ID */
#else
	uint64_t qid                          : 7;
	uint64_t pid                          : 6;
	uint64_t reserved_13_52               : 40;
	uint64_t qos_mask                     : 8;
	uint64_t reserved_61_63               : 3;
#endif
	} s;
	struct cvmx_pko_mem_queue_qos_s       cn30xx;
	struct cvmx_pko_mem_queue_qos_s       cn31xx;
	struct cvmx_pko_mem_queue_qos_s       cn38xx;
	struct cvmx_pko_mem_queue_qos_s       cn38xxp2;
	struct cvmx_pko_mem_queue_qos_s       cn50xx;
	struct cvmx_pko_mem_queue_qos_s       cn52xx;
	struct cvmx_pko_mem_queue_qos_s       cn52xxp1;
	struct cvmx_pko_mem_queue_qos_s       cn56xx;
	struct cvmx_pko_mem_queue_qos_s       cn56xxp1;
	struct cvmx_pko_mem_queue_qos_s       cn58xx;
	struct cvmx_pko_mem_queue_qos_s       cn58xxp1;
	struct cvmx_pko_mem_queue_qos_s       cn63xx;
	struct cvmx_pko_mem_queue_qos_s       cn63xxp1;
};
typedef union cvmx_pko_mem_queue_qos cvmx_pko_mem_queue_qos_t;

/**
 * cvmx_pko_reg_bist_result
 *
 * Notes:
 * Access to the internal BiST results
 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
 */
union cvmx_pko_reg_bist_result
{
	uint64_t u64;
	struct cvmx_pko_reg_bist_result_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_0_63                : 64;
#else
	uint64_t reserved_0_63                : 64;
#endif
	} s;
	struct cvmx_pko_reg_bist_result_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_27_63               : 37;
	uint64_t psb2                         : 5;  /**< BiST result of the PSB   memories (0=pass, !0=fail) */
	uint64_t count                        : 1;  /**< BiST result of the COUNT memories (0=pass, !0=fail) */
	uint64_t rif                          : 1;  /**< BiST result of the RIF   memories (0=pass, !0=fail) */
	uint64_t wif                          : 1;  /**< BiST result of the WIF   memories (0=pass, !0=fail) */
	uint64_t ncb                          : 1;  /**< BiST result of the NCB   memories (0=pass, !0=fail) */
	uint64_t out                          : 1;  /**< BiST result of the OUT   memories (0=pass, !0=fail) */
	uint64_t crc                          : 1;  /**< BiST result of the CRC   memories (0=pass, !0=fail) */
	uint64_t chk                          : 1;  /**< BiST result of the CHK   memories (0=pass, !0=fail) */
	uint64_t qsb                          : 2;  /**< BiST result of the QSB   memories (0=pass, !0=fail) */
	uint64_t qcb                          : 2;  /**< BiST result of the QCB   memories (0=pass, !0=fail) */
	uint64_t pdb                          : 4;  /**< BiST result of the PDB   memories (0=pass, !0=fail) */
	uint64_t psb                          : 7;  /**< BiST result of the PSB   memories (0=pass, !0=fail) */
#else
	uint64_t psb                          : 7;
	uint64_t pdb                          : 4;
	uint64_t qcb                          : 2;
	uint64_t qsb                          : 2;
	uint64_t chk                          : 1;
	uint64_t crc                          : 1;
	uint64_t out                          : 1;
	uint64_t ncb                          : 1;
	uint64_t wif                          : 1;
	uint64_t rif                          : 1;
	uint64_t count                        : 1;
	uint64_t psb2                         : 5;
	uint64_t reserved_27_63               : 37;
#endif
	} cn30xx;
	struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
	struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
	struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
	struct cvmx_pko_reg_bist_result_cn50xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_33_63               : 31;
	uint64_t csr                          : 1;  /**< BiST result of CSR      memories (0=pass, !0=fail) */
	uint64_t iob                          : 1;  /**< BiST result of IOB      memories (0=pass, !0=fail) */
	uint64_t out_crc                      : 1;  /**< BiST result of OUT_CRC  memories (0=pass, !0=fail) */
	uint64_t out_ctl                      : 3;  /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
	uint64_t out_sta                      : 1;  /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
	uint64_t out_wif                      : 1;  /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
	uint64_t prt_chk                      : 3;  /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
	uint64_t prt_nxt                      : 1;  /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
	uint64_t prt_psb                      : 6;  /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
	uint64_t ncb_inb                      : 2;  /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
	uint64_t prt_qcb                      : 2;  /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
	uint64_t prt_qsb                      : 3;  /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
	uint64_t dat_dat                      : 4;  /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
	uint64_t dat_ptr                      : 4;  /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
#else
	uint64_t dat_ptr                      : 4;
	uint64_t dat_dat                      : 4;
	uint64_t prt_qsb                      : 3;
	uint64_t prt_qcb                      : 2;
	uint64_t ncb_inb                      : 2;
	uint64_t prt_psb                      : 6;
	uint64_t prt_nxt                      : 1;
	uint64_t prt_chk                      : 3;
	uint64_t out_wif                      : 1;
	uint64_t out_sta                      : 1;
	uint64_t out_ctl                      : 3;
	uint64_t out_crc                      : 1;
	uint64_t iob                          : 1;
	uint64_t csr                          : 1;
	uint64_t reserved_33_63               : 31;
#endif
	} cn50xx;
	struct cvmx_pko_reg_bist_result_cn52xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_35_63               : 29;
	uint64_t csr                          : 1;  /**< BiST result of CSR      memories (0=pass, !0=fail) */
	uint64_t iob                          : 1;  /**< BiST result of IOB      memories (0=pass, !0=fail) */
	uint64_t out_dat                      : 1;  /**< BiST result of OUT_DAT  memories (0=pass, !0=fail) */
	uint64_t out_ctl                      : 3;  /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
	uint64_t out_sta                      : 1;  /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
	uint64_t out_wif                      : 1;  /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
	uint64_t prt_chk                      : 3;  /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
	uint64_t prt_nxt                      : 1;  /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
	uint64_t prt_psb                      : 8;  /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
	uint64_t ncb_inb                      : 2;  /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
	uint64_t prt_qcb                      : 2;  /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
	uint64_t prt_qsb                      : 3;  /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
	uint64_t prt_ctl                      : 2;  /**< BiST result of PRT_CTL  memories (0=pass, !0=fail) */
	uint64_t dat_dat                      : 2;  /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
	uint64_t dat_ptr                      : 4;  /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
#else
	uint64_t dat_ptr                      : 4;
	uint64_t dat_dat                      : 2;
	uint64_t prt_ctl                      : 2;
	uint64_t prt_qsb                      : 3;
	uint64_t prt_qcb                      : 2;
	uint64_t ncb_inb                      : 2;
	uint64_t prt_psb                      : 8;
	uint64_t prt_nxt                      : 1;
	uint64_t prt_chk                      : 3;
	uint64_t out_wif                      : 1;
	uint64_t out_sta                      : 1;
	uint64_t out_ctl                      : 3;
	uint64_t out_dat                      : 1;
	uint64_t iob                          : 1;
	uint64_t csr                          : 1;
	uint64_t reserved_35_63               : 29;
#endif
	} cn52xx;
	struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
	struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
	struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
	struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
	struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
	struct cvmx_pko_reg_bist_result_cn52xx cn63xx;
	struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1;
};
typedef union cvmx_pko_reg_bist_result cvmx_pko_reg_bist_result_t;

/**
 * cvmx_pko_reg_cmd_buf
 *
 * Notes:
 * Sets the command buffer parameters
 * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
 * lists to be used when freeing command buffer segments.
 */
union cvmx_pko_reg_cmd_buf
{
	uint64_t u64;
	struct cvmx_pko_reg_cmd_buf_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_23_63               : 41;
	uint64_t pool                         : 3;  /**< Free list used to free command buffer segments */
	uint64_t reserved_13_19               : 7;
	uint64_t size                         : 13; /**< Number of uint64s per command buffer segment */
#else
	uint64_t size                         : 13;
	uint64_t reserved_13_19               : 7;
	uint64_t pool                         : 3;
	uint64_t reserved_23_63               : 41;
#endif
	} s;
	struct cvmx_pko_reg_cmd_buf_s         cn30xx;
	struct cvmx_pko_reg_cmd_buf_s         cn31xx;
	struct cvmx_pko_reg_cmd_buf_s         cn38xx;
	struct cvmx_pko_reg_cmd_buf_s         cn38xxp2;
	struct cvmx_pko_reg_cmd_buf_s         cn50xx;
	struct cvmx_pko_reg_cmd_buf_s         cn52xx;
	struct cvmx_pko_reg_cmd_buf_s         cn52xxp1;
	struct cvmx_pko_reg_cmd_buf_s         cn56xx;
	struct cvmx_pko_reg_cmd_buf_s         cn56xxp1;
	struct cvmx_pko_reg_cmd_buf_s         cn58xx;
	struct cvmx_pko_reg_cmd_buf_s         cn58xxp1;
	struct cvmx_pko_reg_cmd_buf_s         cn63xx;
	struct cvmx_pko_reg_cmd_buf_s         cn63xxp1;
};
typedef union cvmx_pko_reg_cmd_buf cvmx_pko_reg_cmd_buf_t;

/**
 * cvmx_pko_reg_crc_ctl#
 *
 * Notes:
 * Controls datapath reflection when calculating CRC
 *
 */
union cvmx_pko_reg_crc_ctlx
{
	uint64_t u64;
	struct cvmx_pko_reg_crc_ctlx_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_2_63                : 62;
	uint64_t invres                       : 1;  /**< Invert the result */
	uint64_t refin                        : 1;  /**< Reflect the bits in each byte.
                                                          Byte order does not change.
                                                         - 0: CRC is calculated MSB to LSB
                                                         - 1: CRC is calculated MLB to MSB */
#else
	uint64_t refin                        : 1;
	uint64_t invres                       : 1;
	uint64_t reserved_2_63                : 62;
#endif
	} s;
	struct cvmx_pko_reg_crc_ctlx_s        cn38xx;
	struct cvmx_pko_reg_crc_ctlx_s        cn38xxp2;
	struct cvmx_pko_reg_crc_ctlx_s        cn58xx;
	struct cvmx_pko_reg_crc_ctlx_s        cn58xxp1;
};
typedef union cvmx_pko_reg_crc_ctlx cvmx_pko_reg_crc_ctlx_t;

/**
 * cvmx_pko_reg_crc_enable
 *
 * Notes:
 * Enables CRC for the GMX ports.
 *
 */
union cvmx_pko_reg_crc_enable
{
	uint64_t u64;
	struct cvmx_pko_reg_crc_enable_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_32_63               : 32;
	uint64_t enable                       : 32; /**< Mask for ports 31-0 to enable CRC
                                                         Mask bit==0 means CRC not enabled
                                                         Mask bit==1 means CRC     enabled
                                                         Note that CRC should be enabled only when using SPI4.2 */
#else
	uint64_t enable                       : 32;
	uint64_t reserved_32_63               : 32;
#endif
	} s;
	struct cvmx_pko_reg_crc_enable_s      cn38xx;
	struct cvmx_pko_reg_crc_enable_s      cn38xxp2;
	struct cvmx_pko_reg_crc_enable_s      cn58xx;
	struct cvmx_pko_reg_crc_enable_s      cn58xxp1;
};
typedef union cvmx_pko_reg_crc_enable cvmx_pko_reg_crc_enable_t;

/**
 * cvmx_pko_reg_crc_iv#
 *
 * Notes:
 * Determines the IV used by the CRC algorithm
 * * PKO_CRC_IV
 *  PKO_CRC_IV controls the initial state of the CRC algorithm.  Octane can
 *  support a wide range of CRC algorithms and as such, the IV must be
 *  carefully constructed to meet the specific algorithm.  The code below
 *  determines the value to program into Octane based on the algorthim's IV
 *  and width.  In the case of Octane, the width should always be 32.
 *
 *  PKO_CRC_IV0 sets the IV for ports 0-15 while PKO_CRC_IV1 sets the IV for
 *  ports 16-31.
 *
 *   @verbatim
 *   unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
 *   [
 *     int i;
 *     int doit;
 *     unsigned int current_val = algorithm_iv;
 *
 *     for(i = 0; i < w; i++) [
 *       doit = current_val & 0x1;
 *
 *       if(doit) current_val ^= poly;
 *       assert(!(current_val & 0x1));
 *
 *       current_val = (current_val >> 1) | (doit << (w-1));
 *     ]
 *
 *     return current_val;
 *   ]
 *   @endverbatim
 */
union cvmx_pko_reg_crc_ivx
{
	uint64_t u64;
	struct cvmx_pko_reg_crc_ivx_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_32_63               : 32;
	uint64_t iv                           : 32; /**< IV used by the CRC algorithm.  Default is FCS32. */
#else
	uint64_t iv                           : 32;
	uint64_t reserved_32_63               : 32;
#endif
	} s;
	struct cvmx_pko_reg_crc_ivx_s         cn38xx;
	struct cvmx_pko_reg_crc_ivx_s         cn38xxp2;
	struct cvmx_pko_reg_crc_ivx_s         cn58xx;
	struct cvmx_pko_reg_crc_ivx_s         cn58xxp1;
};
typedef union cvmx_pko_reg_crc_ivx cvmx_pko_reg_crc_ivx_t;

/**
 * cvmx_pko_reg_debug0
 *
 * Notes:
 * Note that this CSR is present only in chip revisions beginning with pass2.
 *
 */
union cvmx_pko_reg_debug0
{
	uint64_t u64;
	struct cvmx_pko_reg_debug0_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t asserts                      : 64; /**< Various assertion checks */
#else
	uint64_t asserts                      : 64;
#endif
	} s;
	struct cvmx_pko_reg_debug0_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_17_63               : 47;
	uint64_t asserts                      : 17; /**< Various assertion checks */
#else
	uint64_t asserts                      : 17;
	uint64_t reserved_17_63               : 47;
#endif
	} cn30xx;
	struct cvmx_pko_reg_debug0_cn30xx     cn31xx;
	struct cvmx_pko_reg_debug0_cn30xx     cn38xx;
	struct cvmx_pko_reg_debug0_cn30xx     cn38xxp2;
	struct cvmx_pko_reg_debug0_s          cn50xx;
	struct cvmx_pko_reg_debug0_s          cn52xx;
	struct cvmx_pko_reg_debug0_s          cn52xxp1;
	struct cvmx_pko_reg_debug0_s          cn56xx;
	struct cvmx_pko_reg_debug0_s          cn56xxp1;
	struct cvmx_pko_reg_debug0_s          cn58xx;
	struct cvmx_pko_reg_debug0_s          cn58xxp1;
	struct cvmx_pko_reg_debug0_s          cn63xx;
	struct cvmx_pko_reg_debug0_s          cn63xxp1;
};
typedef union cvmx_pko_reg_debug0 cvmx_pko_reg_debug0_t;

/**
 * cvmx_pko_reg_debug1
 */
union cvmx_pko_reg_debug1
{
	uint64_t u64;
	struct cvmx_pko_reg_debug1_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t asserts                      : 64; /**< Various assertion checks */
#else
	uint64_t asserts                      : 64;
#endif
	} s;
	struct cvmx_pko_reg_debug1_s          cn50xx;
	struct cvmx_pko_reg_debug1_s          cn52xx;
	struct cvmx_pko_reg_debug1_s          cn52xxp1;
	struct cvmx_pko_reg_debug1_s          cn56xx;
	struct cvmx_pko_reg_debug1_s          cn56xxp1;
	struct cvmx_pko_reg_debug1_s          cn58xx;
	struct cvmx_pko_reg_debug1_s          cn58xxp1;
	struct cvmx_pko_reg_debug1_s          cn63xx;
	struct cvmx_pko_reg_debug1_s          cn63xxp1;
};
typedef union cvmx_pko_reg_debug1 cvmx_pko_reg_debug1_t;

/**
 * cvmx_pko_reg_debug2
 */
union cvmx_pko_reg_debug2
{
	uint64_t u64;
	struct cvmx_pko_reg_debug2_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t asserts                      : 64; /**< Various assertion checks */
#else
	uint64_t asserts                      : 64;
#endif
	} s;
	struct cvmx_pko_reg_debug2_s          cn50xx;
	struct cvmx_pko_reg_debug2_s          cn52xx;
	struct cvmx_pko_reg_debug2_s          cn52xxp1;
	struct cvmx_pko_reg_debug2_s          cn56xx;
	struct cvmx_pko_reg_debug2_s          cn56xxp1;
	struct cvmx_pko_reg_debug2_s          cn58xx;
	struct cvmx_pko_reg_debug2_s          cn58xxp1;
	struct cvmx_pko_reg_debug2_s          cn63xx;
	struct cvmx_pko_reg_debug2_s          cn63xxp1;
};
typedef union cvmx_pko_reg_debug2 cvmx_pko_reg_debug2_t;

/**
 * cvmx_pko_reg_debug3
 */
union cvmx_pko_reg_debug3
{
	uint64_t u64;
	struct cvmx_pko_reg_debug3_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t asserts                      : 64; /**< Various assertion checks */
#else
	uint64_t asserts                      : 64;
#endif
	} s;
	struct cvmx_pko_reg_debug3_s          cn50xx;
	struct cvmx_pko_reg_debug3_s          cn52xx;
	struct cvmx_pko_reg_debug3_s          cn52xxp1;
	struct cvmx_pko_reg_debug3_s          cn56xx;
	struct cvmx_pko_reg_debug3_s          cn56xxp1;
	struct cvmx_pko_reg_debug3_s          cn58xx;
	struct cvmx_pko_reg_debug3_s          cn58xxp1;
	struct cvmx_pko_reg_debug3_s          cn63xx;
	struct cvmx_pko_reg_debug3_s          cn63xxp1;
};
typedef union cvmx_pko_reg_debug3 cvmx_pko_reg_debug3_t;

/**
 * cvmx_pko_reg_engine_inflight
 *
 * Notes:
 * Sets the maximum number of inflight packets, per engine.  Values greater than 4 are illegal.
 * Setting an engine's value to 0 effectively stops the engine.
 * Note that engines 4-7 do not exist
 */
union cvmx_pko_reg_engine_inflight
{
	uint64_t u64;
	struct cvmx_pko_reg_engine_inflight_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_48_63               : 16;
	uint64_t engine11                     : 4;  /**< Maximum number of inflight packets for engine11 */
	uint64_t engine10                     : 4;  /**< Maximum number of inflight packets for engine10 */
	uint64_t engine9                      : 4;  /**< Maximum number of inflight packets for engine9 */
	uint64_t engine8                      : 4;  /**< Maximum number of inflight packets for engine8 */
	uint64_t engine7                      : 4;  /**< MBZ */
	uint64_t engine6                      : 4;  /**< MBZ */
	uint64_t engine5                      : 4;  /**< MBZ */
	uint64_t engine4                      : 4;  /**< MBZ */
	uint64_t engine3                      : 4;  /**< Maximum number of inflight packets for engine3 */
	uint64_t engine2                      : 4;  /**< Maximum number of inflight packets for engine2 */
	uint64_t engine1                      : 4;  /**< Maximum number of inflight packets for engine1 */
	uint64_t engine0                      : 4;  /**< Maximum number of inflight packets for engine0 */
#else
	uint64_t engine0                      : 4;
	uint64_t engine1                      : 4;
	uint64_t engine2                      : 4;
	uint64_t engine3                      : 4;
	uint64_t engine4                      : 4;
	uint64_t engine5                      : 4;
	uint64_t engine6                      : 4;
	uint64_t engine7                      : 4;
	uint64_t engine8                      : 4;
	uint64_t engine9                      : 4;
	uint64_t engine10                     : 4;
	uint64_t engine11                     : 4;
	uint64_t reserved_48_63               : 16;
#endif
	} s;
	struct cvmx_pko_reg_engine_inflight_cn52xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_40_63               : 24;
	uint64_t engine9                      : 4;  /**< Maximum number of inflight packets for engine9 */
	uint64_t engine8                      : 4;  /**< Maximum number of inflight packets for engine8 */
	uint64_t engine7                      : 4;  /**< MBZ */
	uint64_t engine6                      : 4;  /**< MBZ */
	uint64_t engine5                      : 4;  /**< MBZ */
	uint64_t engine4                      : 4;  /**< MBZ */
	uint64_t engine3                      : 4;  /**< Maximum number of inflight packets for engine3 */
	uint64_t engine2                      : 4;  /**< Maximum number of inflight packets for engine2 */
	uint64_t engine1                      : 4;  /**< Maximum number of inflight packets for engine1 */
	uint64_t engine0                      : 4;  /**< Maximum number of inflight packets for engine0 */
#else
	uint64_t engine0                      : 4;
	uint64_t engine1                      : 4;
	uint64_t engine2                      : 4;
	uint64_t engine3                      : 4;
	uint64_t engine4                      : 4;
	uint64_t engine5                      : 4;
	uint64_t engine6                      : 4;
	uint64_t engine7                      : 4;
	uint64_t engine8                      : 4;
	uint64_t engine9                      : 4;
	uint64_t reserved_40_63               : 24;
#endif
	} cn52xx;
	struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1;
	struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx;
	struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1;
	struct cvmx_pko_reg_engine_inflight_s cn63xx;
	struct cvmx_pko_reg_engine_inflight_s cn63xxp1;
};
typedef union cvmx_pko_reg_engine_inflight cvmx_pko_reg_engine_inflight_t;

/**
 * cvmx_pko_reg_engine_thresh
 *
 * Notes:
 * When not enabled, packet data may be sent as soon as it is written into PKO's internal buffers.
 * When enabled and the packet fits entirely in the PKO's internal buffer, none of the packet data will
 * be sent until all of it has been written into the PKO's internal buffer.  Note that a packet is
 * considered to fit entirely only if the packet's size is <= BUFFER_SIZE-8.  When enabled and the
 * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until
 * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer
 * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above)
 * Note that engines 4-7 do not exist, so MASK<7:4> MBZ
 */
union cvmx_pko_reg_engine_thresh
{
	uint64_t u64;
	struct cvmx_pko_reg_engine_thresh_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_12_63               : 52;
	uint64_t mask                         : 12; /**< Mask[n]=0 disables packet send threshold for engine n
                                                         Mask[n]=1 enables  packet send threshold for engine n  $PR       NS
                                                         Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */
#else
	uint64_t mask                         : 12;
	uint64_t reserved_12_63               : 52;
#endif
	} s;
	struct cvmx_pko_reg_engine_thresh_cn52xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_10_63               : 54;
	uint64_t mask                         : 10; /**< Mask[n]=0 disables packet send threshold for eng n
                                                         Mask[n]=1 enables  packet send threshold for eng n     $PR       NS
                                                         Mask[n] MBZ for n = 4-7, as engines 4-7 dont exist */
#else
	uint64_t mask                         : 10;
	uint64_t reserved_10_63               : 54;
#endif
	} cn52xx;
	struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1;
	struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx;
	struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1;
	struct cvmx_pko_reg_engine_thresh_s   cn63xx;
	struct cvmx_pko_reg_engine_thresh_s   cn63xxp1;
};
typedef union cvmx_pko_reg_engine_thresh cvmx_pko_reg_engine_thresh_t;

/**
 * cvmx_pko_reg_error
 *
 * Notes:
 * Note that this CSR is present only in chip revisions beginning with pass2.
 *
 */
union cvmx_pko_reg_error
{
	uint64_t u64;
	struct cvmx_pko_reg_error_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_3_63                : 61;
	uint64_t currzero                     : 1;  /**< A packet data pointer has size=0 */
	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
	uint64_t parity                       : 1;  /**< Read parity error at port data buffer */
#else
	uint64_t parity                       : 1;
	uint64_t doorbell                     : 1;
	uint64_t currzero                     : 1;
	uint64_t reserved_3_63                : 61;
#endif
	} s;
	struct cvmx_pko_reg_error_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_2_63                : 62;
	uint64_t doorbell                     : 1;  /**< A doorbell count has overflowed */
	uint64_t parity                       : 1;  /**< Read parity error at port data buffer */
#else
	uint64_t parity                       : 1;
	uint64_t doorbell                     : 1;
	uint64_t reserved_2_63                : 62;
#endif
	} cn30xx;
	struct cvmx_pko_reg_error_cn30xx      cn31xx;
	struct cvmx_pko_reg_error_cn30xx      cn38xx;
	struct cvmx_pko_reg_error_cn30xx      cn38xxp2;
	struct cvmx_pko_reg_error_s           cn50xx;
	struct cvmx_pko_reg_error_s           cn52xx;
	struct cvmx_pko_reg_error_s           cn52xxp1;
	struct cvmx_pko_reg_error_s           cn56xx;
	struct cvmx_pko_reg_error_s           cn56xxp1;
	struct cvmx_pko_reg_error_s           cn58xx;
	struct cvmx_pko_reg_error_s           cn58xxp1;
	struct cvmx_pko_reg_error_s           cn63xx;
	struct cvmx_pko_reg_error_s           cn63xxp1;
};
typedef union cvmx_pko_reg_error cvmx_pko_reg_error_t;

/**
 * cvmx_pko_reg_flags
 *
 * Notes:
 * When set, ENA_PKO enables the PKO picker and places the PKO in normal operation.  When set, ENA_DWB
 * enables the use of DontWriteBacks during the buffer freeing operations.  When not set, STORE_BE inverts
 * bits[2:0] of the STORE0 byte write address.  When set, RESET causes a 4-cycle reset pulse to the
 * entire box.
 */
union cvmx_pko_reg_flags
{
	uint64_t u64;
	struct cvmx_pko_reg_flags_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_4_63                : 60;
	uint64_t reset                        : 1;  /**< Reset oneshot pulse */
	uint64_t store_be                     : 1;  /**< Force STORE0 byte write address to big endian */
	uint64_t ena_dwb                      : 1;  /**< Set to enable DontWriteBacks */
	uint64_t ena_pko                      : 1;  /**< Set to enable the PKO picker */
#else
	uint64_t ena_pko                      : 1;
	uint64_t ena_dwb                      : 1;
	uint64_t store_be                     : 1;
	uint64_t reset                        : 1;
	uint64_t reserved_4_63                : 60;
#endif
	} s;
	struct cvmx_pko_reg_flags_s           cn30xx;
	struct cvmx_pko_reg_flags_s           cn31xx;
	struct cvmx_pko_reg_flags_s           cn38xx;
	struct cvmx_pko_reg_flags_s           cn38xxp2;
	struct cvmx_pko_reg_flags_s           cn50xx;
	struct cvmx_pko_reg_flags_s           cn52xx;
	struct cvmx_pko_reg_flags_s           cn52xxp1;
	struct cvmx_pko_reg_flags_s           cn56xx;
	struct cvmx_pko_reg_flags_s           cn56xxp1;
	struct cvmx_pko_reg_flags_s           cn58xx;
	struct cvmx_pko_reg_flags_s           cn58xxp1;
	struct cvmx_pko_reg_flags_s           cn63xx;
	struct cvmx_pko_reg_flags_s           cn63xxp1;
};
typedef union cvmx_pko_reg_flags cvmx_pko_reg_flags_t;

/**
 * cvmx_pko_reg_gmx_port_mode
 *
 * Notes:
 * The system has a total of 4 + 0 + 4 + 4 + 4 ports and 4 + 0 + 1 + 1 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP + SRIO0 + SRIO1).
 * This CSR sets the number of GMX0 ports and amount of local storage per engine.
 * It has no effect on the number of ports or amount of local storage per engine for PCI, LOOP,
 * SRIO0, or SRIO1.  When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local
 * storage.  Increasing the value of MODEn by 1 decreases the number of GMX ports by a power of 2 and
 * increases the local storage per PKO GMX engine by a power of 2.
 * Modes 0 and 1 are illegal and, if selected, are treated as mode 2.
 *
 * MODE[n] GM[0] PCI   LOOP  GM[0]                      PCI            LOOP            SRIO0           SRIO1
 *         ports ports ports storage/engine             storage/engine storage/engine  storage/engine  storage/engine
 * 0       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
 * 1       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
 * 2       4     4     4       2.5kB                    2.5kB          2.5kB           2.5kB           2.5kB
 * 3       2     4     4       5.0kB                    2.5kB          2.5kB           2.5kB           2.5kB
 * 4       1     4     4      10.0kB                    2.5kB          2.5kB           2.5kB           2.5kB
 */
union cvmx_pko_reg_gmx_port_mode
{
	uint64_t u64;
	struct cvmx_pko_reg_gmx_port_mode_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_6_63                : 58;
	uint64_t mode1                        : 3;  /**< MBZ */
	uint64_t mode0                        : 3;  /**< # of GM0 ports = 16 >> MODE0, 0 <= MODE0 <= 4 */
#else
	uint64_t mode0                        : 3;
	uint64_t mode1                        : 3;
	uint64_t reserved_6_63                : 58;
#endif
	} s;
	struct cvmx_pko_reg_gmx_port_mode_s   cn30xx;
	struct cvmx_pko_reg_gmx_port_mode_s   cn31xx;
	struct cvmx_pko_reg_gmx_port_mode_s   cn38xx;
	struct cvmx_pko_reg_gmx_port_mode_s   cn38xxp2;
	struct cvmx_pko_reg_gmx_port_mode_s   cn50xx;
	struct cvmx_pko_reg_gmx_port_mode_s   cn52xx;
	struct cvmx_pko_reg_gmx_port_mode_s   cn52xxp1;
	struct cvmx_pko_reg_gmx_port_mode_s   cn56xx;
	struct cvmx_pko_reg_gmx_port_mode_s   cn56xxp1;
	struct cvmx_pko_reg_gmx_port_mode_s   cn58xx;
	struct cvmx_pko_reg_gmx_port_mode_s   cn58xxp1;
	struct cvmx_pko_reg_gmx_port_mode_s   cn63xx;
	struct cvmx_pko_reg_gmx_port_mode_s   cn63xxp1;
};
typedef union cvmx_pko_reg_gmx_port_mode cvmx_pko_reg_gmx_port_mode_t;

/**
 * cvmx_pko_reg_int_mask
 *
 * Notes:
 * When a mask bit is set, the corresponding interrupt is enabled.
 *
 */
union cvmx_pko_reg_int_mask
{
	uint64_t u64;
	struct cvmx_pko_reg_int_mask_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_3_63                : 61;
	uint64_t currzero                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[2] above */
	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
	uint64_t parity                       : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
#else
	uint64_t parity                       : 1;
	uint64_t doorbell                     : 1;
	uint64_t currzero                     : 1;
	uint64_t reserved_3_63                : 61;
#endif
	} s;
	struct cvmx_pko_reg_int_mask_cn30xx
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_2_63                : 62;
	uint64_t doorbell                     : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
	uint64_t parity                       : 1;  /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
#else
	uint64_t parity                       : 1;
	uint64_t doorbell                     : 1;
	uint64_t reserved_2_63                : 62;
#endif
	} cn30xx;
	struct cvmx_pko_reg_int_mask_cn30xx   cn31xx;
	struct cvmx_pko_reg_int_mask_cn30xx   cn38xx;
	struct cvmx_pko_reg_int_mask_cn30xx   cn38xxp2;
	struct cvmx_pko_reg_int_mask_s        cn50xx;
	struct cvmx_pko_reg_int_mask_s        cn52xx;
	struct cvmx_pko_reg_int_mask_s        cn52xxp1;
	struct cvmx_pko_reg_int_mask_s        cn56xx;
	struct cvmx_pko_reg_int_mask_s        cn56xxp1;
	struct cvmx_pko_reg_int_mask_s        cn58xx;
	struct cvmx_pko_reg_int_mask_s        cn58xxp1;
	struct cvmx_pko_reg_int_mask_s        cn63xx;
	struct cvmx_pko_reg_int_mask_s        cn63xxp1;
};
typedef union cvmx_pko_reg_int_mask cvmx_pko_reg_int_mask_t;

/**
 * cvmx_pko_reg_queue_mode
 *
 * Notes:
 * Sets the number of queues and amount of local storage per queue
 * The system has a total of 256 queues and (256*8) words of local command storage.  This CSR sets the
 * number of queues that are used.  Increasing the value of MODE by 1 decreases the number of queues
 * by a power of 2 and increases the local storage per queue by a power of 2.
 * MODEn queues storage/queue
 * 0     256     64B ( 8 words)
 * 1     128    128B (16 words)
 * 2      64    256B (32 words)
 */
union cvmx_pko_reg_queue_mode
{
	uint64_t u64;
	struct cvmx_pko_reg_queue_mode_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_2_63                : 62;
	uint64_t mode                         : 2;  /**< # of queues = 256 >> MODE, 0 <= MODE <=2 */
#else
	uint64_t mode                         : 2;
	uint64_t reserved_2_63                : 62;
#endif
	} s;
	struct cvmx_pko_reg_queue_mode_s      cn30xx;
	struct cvmx_pko_reg_queue_mode_s      cn31xx;
	struct cvmx_pko_reg_queue_mode_s      cn38xx;
	struct cvmx_pko_reg_queue_mode_s      cn38xxp2;
	struct cvmx_pko_reg_queue_mode_s      cn50xx;
	struct cvmx_pko_reg_queue_mode_s      cn52xx;
	struct cvmx_pko_reg_queue_mode_s      cn52xxp1;
	struct cvmx_pko_reg_queue_mode_s      cn56xx;
	struct cvmx_pko_reg_queue_mode_s      cn56xxp1;
	struct cvmx_pko_reg_queue_mode_s      cn58xx;
	struct cvmx_pko_reg_queue_mode_s      cn58xxp1;
	struct cvmx_pko_reg_queue_mode_s      cn63xx;
	struct cvmx_pko_reg_queue_mode_s      cn63xxp1;
};
typedef union cvmx_pko_reg_queue_mode cvmx_pko_reg_queue_mode_t;

/**
 * cvmx_pko_reg_queue_ptrs1
 *
 * Notes:
 * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS to allow access to queues 128-255
 * and to allow up mapping of up to 16 queues per port.  When programming queues 128-255, the
 * programming sequence must first write PKO_REG_QUEUE_PTRS1 and then write PKO_MEM_QUEUE_PTRS or
 * PKO_MEM_QUEUE_QOS for each queue.
 * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue
 * programming.
 */
union cvmx_pko_reg_queue_ptrs1
{
	uint64_t u64;
	struct cvmx_pko_reg_queue_ptrs1_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_2_63                : 62;
	uint64_t idx3                         : 1;  /**< [3] of Index (distance from head) in the queue array */
	uint64_t qid7                         : 1;  /**< [7] of Queue ID */
#else
	uint64_t qid7                         : 1;
	uint64_t idx3                         : 1;
	uint64_t reserved_2_63                : 62;
#endif
	} s;
	struct cvmx_pko_reg_queue_ptrs1_s     cn50xx;
	struct cvmx_pko_reg_queue_ptrs1_s     cn52xx;
	struct cvmx_pko_reg_queue_ptrs1_s     cn52xxp1;
	struct cvmx_pko_reg_queue_ptrs1_s     cn56xx;
	struct cvmx_pko_reg_queue_ptrs1_s     cn56xxp1;
	struct cvmx_pko_reg_queue_ptrs1_s     cn58xx;
	struct cvmx_pko_reg_queue_ptrs1_s     cn58xxp1;
	struct cvmx_pko_reg_queue_ptrs1_s     cn63xx;
	struct cvmx_pko_reg_queue_ptrs1_s     cn63xxp1;
};
typedef union cvmx_pko_reg_queue_ptrs1 cvmx_pko_reg_queue_ptrs1_t;

/**
 * cvmx_pko_reg_read_idx
 *
 * Notes:
 * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
 * as memories.  The names of these CSRs begin with the prefix "PKO_MEM_".
 * IDX[7:0] is the read index.  INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
 * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
 * contents of a CSR memory can be read with consecutive CSR read commands.
 */
union cvmx_pko_reg_read_idx
{
	uint64_t u64;
	struct cvmx_pko_reg_read_idx_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_16_63               : 48;
	uint64_t inc                          : 8;  /**< Increment to add to current index for next index */
	uint64_t index                        : 8;  /**< Index to use for next memory CSR read */
#else
	uint64_t index                        : 8;
	uint64_t inc                          : 8;
	uint64_t reserved_16_63               : 48;
#endif
	} s;
	struct cvmx_pko_reg_read_idx_s        cn30xx;
	struct cvmx_pko_reg_read_idx_s        cn31xx;
	struct cvmx_pko_reg_read_idx_s        cn38xx;
	struct cvmx_pko_reg_read_idx_s        cn38xxp2;
	struct cvmx_pko_reg_read_idx_s        cn50xx;
	struct cvmx_pko_reg_read_idx_s        cn52xx;
	struct cvmx_pko_reg_read_idx_s        cn52xxp1;
	struct cvmx_pko_reg_read_idx_s        cn56xx;
	struct cvmx_pko_reg_read_idx_s        cn56xxp1;
	struct cvmx_pko_reg_read_idx_s        cn58xx;
	struct cvmx_pko_reg_read_idx_s        cn58xxp1;
	struct cvmx_pko_reg_read_idx_s        cn63xx;
	struct cvmx_pko_reg_read_idx_s        cn63xxp1;
};
typedef union cvmx_pko_reg_read_idx cvmx_pko_reg_read_idx_t;

/**
 * cvmx_pko_reg_timestamp
 *
 * Notes:
 * None.
 *
 */
union cvmx_pko_reg_timestamp
{
	uint64_t u64;
	struct cvmx_pko_reg_timestamp_s
	{
#if __BYTE_ORDER == __BIG_ENDIAN
	uint64_t reserved_4_63                : 60;
	uint64_t wqe_word                     : 4;  /**< Specifies the 8-byte word in the WQE to which a PTP
                                                         timestamp is written.  Values 0 and 1 are illegal. */
#else
	uint64_t wqe_word                     : 4;
	uint64_t reserved_4_63                : 60;
#endif
	} s;
	struct cvmx_pko_reg_timestamp_s       cn63xx;
	struct cvmx_pko_reg_timestamp_s       cn63xxp1;
};
typedef union cvmx_pko_reg_timestamp cvmx_pko_reg_timestamp_t;

#endif