From f8b73ad2e16934621a86fd1fd67b46aa21521d0b Mon Sep 17 00:00:00 2001 From: Juli Mallett Date: Sun, 11 Mar 2012 04:14:00 +0000 Subject: Import Cavium Octeon SDK 2.3.0 Simple Executive from cnusers.org. --- cvmx-sriomaintx-defs.h | 1329 ++++++++++++++++++++++++------------------------ 1 file changed, 668 insertions(+), 661 deletions(-) (limited to 'cvmx-sriomaintx-defs.h') diff --git a/cvmx-sriomaintx-defs.h b/cvmx-sriomaintx-defs.h index f54e85117fd3..f0e91bc777f8 100644 --- a/cvmx-sriomaintx-defs.h +++ b/cvmx-sriomaintx-defs.h @@ -1,5 +1,5 @@ /***********************license start*************** - * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights + * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights * reserved. * * @@ -15,7 +15,7 @@ * disclaimer in the documentation and/or other materials provided * with the distribution. - * * Neither the name of Cavium Networks nor the names of + * * Neither the name of Cavium Inc. nor the names of * its contributors may be used to endorse or promote products * derived from this software without specific prior written * permission. @@ -26,7 +26,7 @@ * countries. * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" - * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR + * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM @@ -49,14 +49,15 @@ *
$Revision$
* */ -#ifndef __CVMX_SRIOMAINTX_TYPEDEFS_H__ -#define __CVMX_SRIOMAINTX_TYPEDEFS_H__ +#ifndef __CVMX_SRIOMAINTX_DEFS_H__ +#define __CVMX_SRIOMAINTX_DEFS_H__ #if CVMX_ENABLE_CSR_ADDRESS_CHECKING static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); return 0x0000000000000008ull; } @@ -67,7 +68,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); return 0x000000000000000Cull; } @@ -78,18 +80,20 @@ static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_BAR1_IDXX(unsigned long offset, unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id); - return CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4; + return 0x0000000000200010ull + (((offset) & 15) + ((block_id) & 3) * 0x0ull) * 4; } #else -#define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4) +#define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (0x0000000000200010ull + (((offset) & 15) + ((block_id) & 3) * 0x0ull) * 4) #endif #if CVMX_ENABLE_CSR_ADDRESS_CHECKING static inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id); return 0x0000000000200080ull; } @@ -100,7 +104,8 @@ static inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id); return 0x000000000000006Cull; } @@ -111,7 +116,8 @@ static inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id); return 0x0000000000200070ull; } @@ -122,7 +128,8 @@ static inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id); return 0x0000000000000000ull; } @@ -133,7 +140,8 @@ static inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id); return 0x0000000000000004ull; } @@ -144,7 +152,8 @@ static inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id); return 0x000000000000001Cull; } @@ -155,7 +164,8 @@ static inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id); return 0x0000000000002048ull; } @@ -166,7 +176,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_DET(%lu) is invalid on this chip\n", block_id); return 0x0000000000002040ull; } @@ -177,7 +188,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE(%lu) is invalid on this chip\n", block_id); return 0x0000000000002068ull; } @@ -188,7 +200,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(%lu) is invalid on this chip\n", block_id); return 0x0000000000002044ull; } @@ -199,7 +212,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(%lu) is invalid on this chip\n", block_id); return 0x000000000000206Cull; } @@ -210,7 +224,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_HDR(%lu) is invalid on this chip\n", block_id); return 0x0000000000002000ull; } @@ -221,7 +236,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(%lu) is invalid on this chip\n", block_id); return 0x0000000000002010ull; } @@ -232,7 +248,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(%lu) is invalid on this chip\n", block_id); return 0x0000000000002014ull; } @@ -243,7 +260,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(%lu) is invalid on this chip\n", block_id); return 0x000000000000201Cull; } @@ -254,7 +272,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID(%lu) is invalid on this chip\n", block_id); return 0x0000000000002028ull; } @@ -265,7 +284,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(%lu) is invalid on this chip\n", block_id); return 0x0000000000002018ull; } @@ -276,7 +296,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_DET(%lu) is invalid on this chip\n", block_id); return 0x0000000000002008ull; } @@ -287,7 +308,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_EN(%lu) is invalid on this chip\n", block_id); return 0x000000000000200Cull; } @@ -298,7 +320,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(%lu) is invalid on this chip\n", block_id); return 0x0000000000002050ull; } @@ -309,7 +332,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(%lu) is invalid on this chip\n", block_id); return 0x0000000000002054ull; } @@ -320,7 +344,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(%lu) is invalid on this chip\n", block_id); return 0x0000000000002058ull; } @@ -331,7 +356,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(%lu) is invalid on this chip\n", block_id); return 0x000000000000204Cull; } @@ -342,7 +368,8 @@ static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(%lu) is invalid on this chip\n", block_id); return 0x0000000000000068ull; } @@ -353,7 +380,8 @@ static inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(%lu) is invalid on this chip\n", block_id); return 0x0000000000102000ull; } @@ -364,7 +392,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(%lu) is invalid on this chip\n", block_id); return 0x0000000000102004ull; } @@ -375,7 +404,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(%lu) is invalid on this chip\n", block_id); return 0x0000000000107028ull; } @@ -386,7 +416,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_STAT(%lu) is invalid on this chip\n", block_id); return 0x000000000010702Cull; } @@ -397,7 +428,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(%lu) is invalid on this chip\n", block_id); return 0x0000000000107020ull; } @@ -408,7 +440,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_STAT(%lu) is invalid on this chip\n", block_id); return 0x0000000000107024ull; } @@ -419,7 +452,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_CTRL(%lu) is invalid on this chip\n", block_id); return 0x000000000010700Cull; } @@ -430,7 +464,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_DATA(%lu) is invalid on this chip\n", block_id); return 0x0000000000107014ull; } @@ -441,7 +476,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_STAT(%lu) is invalid on this chip\n", block_id); return 0x0000000000107010ull; } @@ -452,7 +488,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_CTRL(%lu) is invalid on this chip\n", block_id); return 0x0000000000107000ull; } @@ -463,7 +500,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_DATA(%lu) is invalid on this chip\n", block_id); return 0x0000000000107008ull; } @@ -474,7 +512,8 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_STAT(%lu) is invalid on this chip\n", block_id); return 0x0000000000107004ull; } @@ -485,18 +524,20 @@ static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_LANE_X_STATUS_0(unsigned long offset, unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) cvmx_warn("CVMX_SRIOMAINTX_LANE_X_STATUS_0(%lu,%lu) is invalid on this chip\n", offset, block_id); - return CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32; + return 0x0000000000001010ull + (((offset) & 3) + ((block_id) & 3) * 0x0ull) * 32; } #else -#define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32) +#define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (0x0000000000001010ull + (((offset) & 3) + ((block_id) & 3) * 0x0ull) * 32) #endif #if CVMX_ENABLE_CSR_ADDRESS_CHECKING static inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_LCS_BA0(%lu) is invalid on this chip\n", block_id); return 0x0000000000000058ull; } @@ -507,7 +548,8 @@ static inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_LCS_BA1(%lu) is invalid on this chip\n", block_id); return 0x000000000000005Cull; } @@ -518,7 +560,8 @@ static inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START0(%lu) is invalid on this chip\n", block_id); return 0x0000000000200000ull; } @@ -529,7 +572,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START1(%lu) is invalid on this chip\n", block_id); return 0x0000000000200004ull; } @@ -540,7 +584,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START0(%lu) is invalid on this chip\n", block_id); return 0x0000000000200008ull; } @@ -551,7 +596,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START1(%lu) is invalid on this chip\n", block_id); return 0x000000000020000Cull; } @@ -562,7 +608,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR2_START(%lu) is invalid on this chip\n", block_id); return 0x0000000000200050ull; } @@ -573,7 +620,8 @@ static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_MAC_CTRL(%lu) is invalid on this chip\n", block_id); return 0x0000000000200068ull; } @@ -584,7 +632,8 @@ static inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PE_FEAT(%lu) is invalid on this chip\n", block_id); return 0x0000000000000010ull; } @@ -595,7 +644,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PE_LLC(%lu) is invalid on this chip\n", block_id); return 0x000000000000004Cull; } @@ -606,7 +656,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL(%lu) is invalid on this chip\n", block_id); return 0x000000000000015Cull; } @@ -617,7 +668,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL2(%lu) is invalid on this chip\n", block_id); return 0x0000000000000154ull; } @@ -628,7 +680,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_0_ERR_STAT(%lu) is invalid on this chip\n", block_id); return 0x0000000000000158ull; } @@ -639,7 +692,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_REQ(%lu) is invalid on this chip\n", block_id); return 0x0000000000000140ull; } @@ -650,7 +704,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_RESP(%lu) is invalid on this chip\n", block_id); return 0x0000000000000144ull; } @@ -661,7 +716,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(%lu) is invalid on this chip\n", block_id); return 0x0000000000000148ull; } @@ -672,7 +728,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id static inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_GEN_CTL(%lu) is invalid on this chip\n", block_id); return 0x000000000000013Cull; } @@ -683,7 +740,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_LT_CTL(%lu) is invalid on this chip\n", block_id); return 0x0000000000000120ull; } @@ -694,7 +752,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_MBH0(%lu) is invalid on this chip\n", block_id); return 0x0000000000000100ull; } @@ -705,7 +764,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_RT_CTL(%lu) is invalid on this chip\n", block_id); return 0x0000000000000124ull; } @@ -716,7 +776,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PORT_TTL_CTL(%lu) is invalid on this chip\n", block_id); return 0x000000000000012Cull; } @@ -727,7 +788,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_PRI_DEV_ID(%lu) is invalid on this chip\n", block_id); return 0x0000000000000060ull; } @@ -738,7 +800,8 @@ static inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_CTRL(%lu) is invalid on this chip\n", block_id); return 0x0000000000200064ull; } @@ -749,7 +812,8 @@ static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_ID(%lu) is invalid on this chip\n", block_id); return 0x0000000000200060ull; } @@ -760,7 +824,8 @@ static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_SERIAL_LANE_HDR(%lu) is invalid on this chip\n", block_id); return 0x0000000000001000ull; } @@ -771,7 +836,8 @@ static inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_SRC_OPS(%lu) is invalid on this chip\n", block_id); return 0x0000000000000018ull; } @@ -782,7 +848,8 @@ static inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id) static inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id) { if (!( - (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) + (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || + (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) cvmx_warn("CVMX_SRIOMAINTX_TX_DROP(%lu) is invalid on this chip\n", block_id); return 0x000000000020006Cull; } @@ -800,14 +867,12 @@ static inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id) * Notes: * The Assembly ID register shows the Assembly ID and Vendor specified in $SRIO_ASMBLY_ID. * - * Clk_Rst: SRIOMAINT(0..1)_ASMBLY_ID hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ASMBLY_ID hclk hrst_n */ -union cvmx_sriomaintx_asmbly_id -{ +union cvmx_sriomaintx_asmbly_id { uint32_t u32; - struct cvmx_sriomaintx_asmbly_id_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_asmbly_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t assy_id : 16; /**< Assembly Identifer */ uint32_t assy_ven : 16; /**< Assembly Vendor Identifer */ #else @@ -817,6 +882,7 @@ union cvmx_sriomaintx_asmbly_id } s; struct cvmx_sriomaintx_asmbly_id_s cn63xx; struct cvmx_sriomaintx_asmbly_id_s cn63xxp1; + struct cvmx_sriomaintx_asmbly_id_s cn66xx; }; typedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t; @@ -831,14 +897,12 @@ typedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t; * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO and Extended * Feature Pointer. * - * Clk_Rst: SRIOMAINT(0..1)_ASMBLY_INFO hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ASMBLY_INFO hclk hrst_n */ -union cvmx_sriomaintx_asmbly_info -{ +union cvmx_sriomaintx_asmbly_info { uint32_t u32; - struct cvmx_sriomaintx_asmbly_info_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_asmbly_info_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t assy_rev : 16; /**< Assembly Revision */ uint32_t ext_fptr : 16; /**< Pointer to the first entry in the extended feature list. */ @@ -849,6 +913,7 @@ union cvmx_sriomaintx_asmbly_info } s; struct cvmx_sriomaintx_asmbly_info_s cn63xx; struct cvmx_sriomaintx_asmbly_info_s cn63xxp1; + struct cvmx_sriomaintx_asmbly_info_s cn66xx; }; typedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t; @@ -862,21 +927,19 @@ typedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t; * Notes: * This register specifies the Octeon address, endian swap and cache status associated with each of * the 16 BAR1 entries. The local address bits used are based on the BARSIZE field located in the - * SRIOMAINT(0..1)_M2S_BAR1_START0 register. This register is only writeable over SRIO if the - * SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. + * SRIOMAINT(0,2..3)_M2S_BAR1_START0 register. This register is only writeable over SRIO if the + * SRIO(0,2..3)_ACC_CTRL.DENY_BAR1 bit is zero. * - * Clk_Rst: SRIOMAINT(0..1)_BAR1_IDX[0:15] hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_BAR1_IDX[0:15] hclk hrst_n */ -union cvmx_sriomaintx_bar1_idxx -{ +union cvmx_sriomaintx_bar1_idxx { uint32_t u32; - struct cvmx_sriomaintx_bar1_idxx_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_bar1_idxx_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31 : 2; uint32_t la : 22; /**< L2/DRAM Address bits [37:16] Not all LA[21:0] bits are used by SRIO hardware, - depending on SRIOMAINT(0..1)_M2S_BAR1_START1[BARSIZE]. + depending on SRIOMAINT(0,2..3)_M2S_BAR1_START1[BARSIZE]. Become L2/DRAM @@ -890,12 +953,12 @@ union cvmx_sriomaintx_bar1_idxx 5 LA[21:5] [37:21] 2MB 6 LA[21:6] [37:22] 4MB 7 LA[21:7] [37:23] 8MB - 8 ** not in pass 1 - 9 ** not in pass 1 - 10 ** not in pass 1 - 11 ** not in pass 1 - 12 ** not in pass 1 - 13 ** not in pass 1 */ + 8 LA[21:8] [37:24] 16MB + 9 LA[21:9] [37:25] 32MB + 10 LA[21:10] [37:26] 64MB + 11 LA[21:11] [37:27] 128MB + 12 LA[21:12] [37:28] 256MB + 13 LA[21:13] [37:29] 512MB */ uint32_t reserved_6_7 : 2; uint32_t es : 2; /**< Endian Swap Mode. 0 = No Swap @@ -918,6 +981,7 @@ union cvmx_sriomaintx_bar1_idxx } s; struct cvmx_sriomaintx_bar1_idxx_s cn63xx; struct cvmx_sriomaintx_bar1_idxx_s cn63xxp1; + struct cvmx_sriomaintx_bar1_idxx_s cn66xx; }; typedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t; @@ -932,14 +996,12 @@ typedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t; * This register displays the status of the doorbells received. If FULL is set the SRIO device will * retry incoming transactions. * - * Clk_Rst: SRIOMAINT(0..1)_BELL_STATUS hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_BELL_STATUS hclk hrst_n */ -union cvmx_sriomaintx_bell_status -{ +union cvmx_sriomaintx_bell_status { uint32_t u32; - struct cvmx_sriomaintx_bell_status_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_bell_status_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_1_31 : 31; uint32_t full : 1; /**< Not able to receive Doorbell Transactions */ #else @@ -949,6 +1011,7 @@ union cvmx_sriomaintx_bell_status } s; struct cvmx_sriomaintx_bell_status_s cn63xx; struct cvmx_sriomaintx_bell_status_s cn63xxp1; + struct cvmx_sriomaintx_bell_status_s cn66xx; }; typedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t; @@ -963,14 +1026,12 @@ typedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t; * This register contains a component tag value for the processing element and the value can be * assigned by software when the device is initialized. * - * Clk_Rst: SRIOMAINT(0..1)_COMP_TAG hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_COMP_TAG hclk hrst_n */ -union cvmx_sriomaintx_comp_tag -{ +union cvmx_sriomaintx_comp_tag { uint32_t u32; - struct cvmx_sriomaintx_comp_tag_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_comp_tag_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t comp_tag : 32; /**< Component Tag for Firmware Use */ #else uint32_t comp_tag : 32; @@ -978,6 +1039,7 @@ union cvmx_sriomaintx_comp_tag } s; struct cvmx_sriomaintx_comp_tag_s cn63xx; struct cvmx_sriomaintx_comp_tag_s cn63xxp1; + struct cvmx_sriomaintx_comp_tag_s cn66xx; }; typedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t; @@ -992,14 +1054,12 @@ typedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t; * This register displays the reset state of the Octeon Core Logic while the SRIO Link is running. * The bit should be set after the software has initialized the chip to allow memory operations. * - * Clk_Rst: SRIOMAINT(0..1)_CORE_ENABLES hclk hrst_n, srst_n + * Clk_Rst: SRIOMAINT(0,2..3)_CORE_ENABLES hclk hrst_n, srst_n */ -union cvmx_sriomaintx_core_enables -{ +union cvmx_sriomaintx_core_enables { uint32_t u32; - struct cvmx_sriomaintx_core_enables_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_core_enables_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_5_31 : 27; uint32_t halt : 1; /**< OCTEON currently in Reset 0 = All OCTEON resources are available. @@ -1045,6 +1105,7 @@ union cvmx_sriomaintx_core_enables } s; struct cvmx_sriomaintx_core_enables_s cn63xx; struct cvmx_sriomaintx_core_enables_s cn63xxp1; + struct cvmx_sriomaintx_core_enables_s cn66xx; }; typedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t; @@ -1056,16 +1117,14 @@ typedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t; * The DeviceVendor Identity field identifies the vendor that manufactured the device * * Notes: - * This register identifies Cavium Networks and the Product ID. + * This register identifies Cavium Inc. and the Product ID. * - * Clk_Rst: SRIOMAINT(0..1)_DEV_ID hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_DEV_ID hclk hrst_n */ -union cvmx_sriomaintx_dev_id -{ +union cvmx_sriomaintx_dev_id { uint32_t u32; - struct cvmx_sriomaintx_dev_id_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_dev_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t device : 16; /**< Product Identity */ uint32_t vendor : 16; /**< Cavium Vendor Identity */ #else @@ -1075,6 +1134,7 @@ union cvmx_sriomaintx_dev_id } s; struct cvmx_sriomaintx_dev_id_s cn63xx; struct cvmx_sriomaintx_dev_id_s cn63xxp1; + struct cvmx_sriomaintx_dev_id_s cn66xx; }; typedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t; @@ -1088,14 +1148,12 @@ typedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t; * Notes: * This register identifies the chip pass and revision derived from the fuses. * - * Clk_Rst: SRIOMAINT(0..1)_DEV_REV hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_DEV_REV hclk hrst_n */ -union cvmx_sriomaintx_dev_rev -{ +union cvmx_sriomaintx_dev_rev { uint32_t u32; - struct cvmx_sriomaintx_dev_rev_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_dev_rev_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_8_31 : 24; uint32_t revision : 8; /**< Chip Pass/Revision */ #else @@ -1105,6 +1163,7 @@ union cvmx_sriomaintx_dev_rev } s; struct cvmx_sriomaintx_dev_rev_s cn63xx; struct cvmx_sriomaintx_dev_rev_s cn63xxp1; + struct cvmx_sriomaintx_dev_rev_s cn66xx; }; typedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t; @@ -1117,16 +1176,14 @@ typedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t; * * Notes: * The logical operations supported from external devices. The Destination OPs register shows the - * operations specified in the SRIO(0..1)_IP_FEATURE.OPS register. + * operations specified in the SRIO(0,2..3)_IP_FEATURE.OPS register. * - * Clk_Rst: SRIOMAINT(0..1)_DST_OPS hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_DST_OPS hclk hrst_n */ -union cvmx_sriomaintx_dst_ops -{ +union cvmx_sriomaintx_dst_ops { uint32_t u32; - struct cvmx_sriomaintx_dst_ops_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_dst_ops_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t gsm_read : 1; /**< PE does not support Read Home operations. This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */ uint32_t i_read : 1; /**< PE does not support Instruction Read. @@ -1208,6 +1265,7 @@ union cvmx_sriomaintx_dst_ops } s; struct cvmx_sriomaintx_dst_ops_s cn63xx; struct cvmx_sriomaintx_dst_ops_s cn63xxp1; + struct cvmx_sriomaintx_dst_ops_s cn66xx; }; typedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t; @@ -1229,24 +1287,23 @@ typedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t; * SRIOMAINT*_ERB_PACK_CAPT_1, SRIOMAINT*_ERB_PACK_CAPT_2, and SRIOMAINT*_ERB_PACK_CAPT_3 * (3) Write VALID in this CSR to 0. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_ATTR_CAPT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ATTR_CAPT hclk hrst_n */ -union cvmx_sriomaintx_erb_attr_capt -{ +union cvmx_sriomaintx_erb_attr_capt { uint32_t u32; - struct cvmx_sriomaintx_erb_attr_capt_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_attr_capt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t inf_type : 3; /**< Type of Information Logged. 000 - Packet 010 - Short Control Symbol (use only first capture register) + 100 - Implementation Specific Error Reporting All Others Reserved */ uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in - SRIOMAINT(0..1)_ERB_ERR_DET that describes the error - captured in SRIOMAINT(0..1)_ERB_*CAPT Registers. + SRIOMAINT(0,2..3)_ERB_ERR_DET that describes the error + captured in SRIOMAINT(0,2..3)_ERB_*CAPT Registers. (For example a value of 5 indicates 31-5 = bit 26) */ - uint32_t err_info : 20; /**< Error Info. (Pass 2) + uint32_t err_info : 20; /**< Error Info. ERR_TYPE Bits Description 0 23 TX Protocol Error 22 RX Protocol Error @@ -1302,9 +1359,8 @@ union cvmx_sriomaintx_erb_attr_capt #endif } s; struct cvmx_sriomaintx_erb_attr_capt_s cn63xx; - struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1 - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t inf_type : 3; /**< Type of Information Logged. 000 - Packet 010 - Short Control Symbol @@ -1328,6 +1384,7 @@ union cvmx_sriomaintx_erb_attr_capt uint32_t inf_type : 3; #endif } cn63xxp1; + struct cvmx_sriomaintx_erb_attr_capt_s cn66xx; }; typedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t; @@ -1343,54 +1400,52 @@ typedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t; * The HW will not update this register (i.e. this register is locked) while * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_DET hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_DET hclk hrst_n */ -union cvmx_sriomaintx_erb_err_det -{ +union cvmx_sriomaintx_erb_err_det { uint32_t u32; - struct cvmx_sriomaintx_erb_err_det_s - { -#if __BYTE_ORDER == __BIG_ENDIAN - uint32_t imp_err : 1; /**< Implementation Specific Error added for Pass 2. */ + struct cvmx_sriomaintx_erb_err_det_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t imp_err : 1; /**< Implementation Specific Error. */ uint32_t reserved_23_30 : 8; uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value - Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Complete Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an unexpected ackID (packet-accepted or packet_retry) - Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control symbols. - Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t out_ack : 1; /**< Received packet with unexpected ackID value - Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value - Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t size : 1; /**< Received packet which exceeds the maximum allowed size of 276 bytes. - Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t inv_char : 1; /**< Received illegal, 8B/10B error or undefined - codegroup within a packet. (Pass 2) - Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + codegroup within a packet. + Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t inv_data : 1; /**< Received data codegroup or 8B/10B error within an - IDLE sequence. (Pass 2) - Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + IDLE sequence. + Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t reserved_6_14 : 9; uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not outstanding. - Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t proterr : 1; /**< An unexpected packet or control symbol was received. - Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t f_toggle : 1; /**< Reserved. */ uint32_t del_err : 1; /**< Received illegal or undefined codegroup. - (either INV_DATA or INV_CHAR) (Pass 2) - Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + (either INV_DATA or INV_CHAR) + Complete Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was received. - Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is not received within the specified timeout interval - Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ + Partial Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ #else uint32_t lnk_tout : 1; uint32_t uns_ack : 1; @@ -1412,9 +1467,8 @@ union cvmx_sriomaintx_erb_err_det #endif } s; struct cvmx_sriomaintx_erb_err_det_s cn63xx; - struct cvmx_sriomaintx_erb_err_det_cn63xxp1 - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_err_det_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_23_31 : 9; uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ @@ -1465,6 +1519,7 @@ union cvmx_sriomaintx_erb_err_det uint32_t reserved_23_31 : 9; #endif } cn63xxp1; + struct cvmx_sriomaintx_erb_err_det_s cn66xx; }; typedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t; @@ -1479,14 +1534,12 @@ typedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t; * The Error Rate register is used with the Error Rate Threshold register to monitor and control the * reporting of transmission errors. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE hclk hrst_n */ -union cvmx_sriomaintx_erb_err_rate -{ +union cvmx_sriomaintx_erb_err_rate { uint32_t u32; - struct cvmx_sriomaintx_erb_err_rate_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_err_rate_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t err_bias : 8; /**< These bits provide the error rate bias value. 0x00 - do not decrement the error rate counter 0x01 - decrement every 1ms (+/-34%) @@ -1521,6 +1574,7 @@ union cvmx_sriomaintx_erb_err_rate } s; struct cvmx_sriomaintx_erb_err_rate_s cn63xx; struct cvmx_sriomaintx_erb_err_rate_s cn63xxp1; + struct cvmx_sriomaintx_erb_err_rate_s cn66xx; }; typedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t; @@ -1535,15 +1589,13 @@ typedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t; * This register contains the bits that control when an error condition is allowed to increment the * error rate counter in the Error Rate Threshold Register and lock the Error Capture registers. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE_EN hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE_EN hclk hrst_n */ -union cvmx_sriomaintx_erb_err_rate_en -{ +union cvmx_sriomaintx_erb_err_rate_en { uint32_t u32; - struct cvmx_sriomaintx_erb_err_rate_en_s - { -#if __BYTE_ORDER == __BIG_ENDIAN - uint32_t imp_err : 1; /**< Enable Implementation Specific Error (Pass 2). */ + struct cvmx_sriomaintx_erb_err_rate_en_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t imp_err : 1; /**< Enable Implementation Specific Error. */ uint32_t reserved_23_30 : 8; uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with bad CRC values */ @@ -1560,10 +1612,9 @@ union cvmx_sriomaintx_erb_err_rate_en which exceeds the maximum size of 276 bytes. */ uint32_t inv_char : 1; /**< Enable error rate counting of received illegal illegal, 8B/10B error or undefined codegroup - within a packet. (Pass 2) */ + within a packet. */ uint32_t inv_data : 1; /**< Enable error rate counting of received data - codegroup or 8B/10B error within IDLE sequence. - (Pass 2) */ + codegroup or 8B/10B error within IDLE sequence. */ uint32_t reserved_6_14 : 9; uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with an ackID that is not outstanding. */ @@ -1571,7 +1622,7 @@ union cvmx_sriomaintx_erb_err_rate_en control symbols received. */ uint32_t f_toggle : 1; /**< Reserved. */ uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined - codegroups (either INV_DATA or INV_CHAR). (Pass 2) */ + codegroups (either INV_DATA or INV_CHAR). */ uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected acknowledge control symbols received. */ uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or @@ -1598,9 +1649,8 @@ union cvmx_sriomaintx_erb_err_rate_en #endif } s; struct cvmx_sriomaintx_erb_err_rate_en_s cn63xx; - struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1 - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_23_31 : 9; uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with bad CRC values */ @@ -1645,6 +1695,7 @@ union cvmx_sriomaintx_erb_err_rate_en uint32_t reserved_23_31 : 9; #endif } cn63xxp1; + struct cvmx_sriomaintx_erb_err_rate_en_s cn66xx; }; typedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t; @@ -1659,14 +1710,12 @@ typedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t; * The Error Rate Threshold register is used to control the reporting of errors to the link status. * Typically the Degraded Threshold is less than the Fail Threshold. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE_THR hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR hclk hrst_n */ -union cvmx_sriomaintx_erb_err_rate_thr -{ +union cvmx_sriomaintx_erb_err_rate_thr { uint32_t u32; - struct cvmx_sriomaintx_erb_err_rate_thr_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_err_rate_thr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t fail_th : 8; /**< These bits provide the threshold value for reporting an error condition due to a possibly broken link. @@ -1694,6 +1743,7 @@ union cvmx_sriomaintx_erb_err_rate_thr } s; struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xx; struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xxp1; + struct cvmx_sriomaintx_erb_err_rate_thr_s cn66xx; }; typedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_t; @@ -1709,14 +1759,12 @@ typedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_ * the EF_ID that identifies this as the error management extensions block header. In this * implementation this is the last block and therefore the EF_PTR is a NULL pointer. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_HDR hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_HDR hclk hrst_n */ -union cvmx_sriomaintx_erb_hdr -{ +union cvmx_sriomaintx_erb_hdr { uint32_t u32; - struct cvmx_sriomaintx_erb_hdr_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features data structure. */ uint32_t ef_id : 16; /**< Single Port ID */ @@ -1727,6 +1775,7 @@ union cvmx_sriomaintx_erb_hdr } s; struct cvmx_sriomaintx_erb_hdr_s cn63xx; struct cvmx_sriomaintx_erb_hdr_s cn63xxp1; + struct cvmx_sriomaintx_erb_hdr_s cn66xx; }; typedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t; @@ -1739,18 +1788,16 @@ typedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t; * * Notes: * This register contains error information. It is locked when a Logical/Transport error is detected - * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be + * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be * written only when error detection is disabled. This register is only required for end point * transactions of 50 or 66 bits. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_H hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ADDR_CAPT_H hclk hrst_n */ -union cvmx_sriomaintx_erb_lt_addr_capt_h -{ +union cvmx_sriomaintx_erb_lt_addr_capt_h { uint32_t u32; - struct cvmx_sriomaintx_erb_lt_addr_capt_h_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_lt_addr_capt_h_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t addr : 32; /**< Most significant 32 bits of the address associated with the error. Information supplied for requests and responses if available. */ @@ -1760,6 +1807,7 @@ union cvmx_sriomaintx_erb_lt_addr_capt_h } s; struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xx; struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xxp1; + struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn66xx; }; typedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_capt_h_t; @@ -1772,17 +1820,15 @@ typedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_cap * * Notes: * This register contains error information. It is locked when a Logical/Transport error is detected - * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be + * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be * written only when error detection is disabled. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_L hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ADDR_CAPT_L hclk hrst_n */ -union cvmx_sriomaintx_erb_lt_addr_capt_l -{ +union cvmx_sriomaintx_erb_lt_addr_capt_l { uint32_t u32; - struct cvmx_sriomaintx_erb_lt_addr_capt_l_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_lt_addr_capt_l_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t addr : 29; /**< Least significant 29 bits of the address associated with the error. Bits 31:24 specify the request HOP count for Maintenance Operations. @@ -1800,6 +1846,7 @@ union cvmx_sriomaintx_erb_lt_addr_capt_l } s; struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xx; struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xxp1; + struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn66xx; }; typedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_capt_l_t; @@ -1812,17 +1859,15 @@ typedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_cap * * Notes: * This register contains error information. It is locked when a Logical/Transport error is detected - * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be + * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be * written only when error detection is disabled. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_CTRL_CAPT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_CTRL_CAPT hclk hrst_n */ -union cvmx_sriomaintx_erb_lt_ctrl_capt -{ +union cvmx_sriomaintx_erb_lt_ctrl_capt { uint32_t u32; - struct cvmx_sriomaintx_erb_lt_ctrl_capt_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_lt_ctrl_capt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ftype : 4; /**< Format Type associated with the error */ uint32_t ttype : 4; /**< Transaction Type associated with the error (For Messages) @@ -1847,7 +1892,7 @@ union cvmx_sriomaintx_erb_lt_ctrl_capt uint32_t wdptr : 1; /**< Word Pointer associated with the error. */ uint32_t reserved_5_5 : 1; uint32_t capt_idx : 5; /**< Capture Index. 31 - Bit set in - SRIOMAINT(0..1)_ERB_LT_ERR_DET. */ + SRIOMAINT(0,2..3)_ERB_LT_ERR_DET. */ #else uint32_t capt_idx : 5; uint32_t reserved_5_5 : 1; @@ -1862,6 +1907,7 @@ union cvmx_sriomaintx_erb_lt_ctrl_capt } s; struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xx; struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xxp1; + struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn66xx; }; typedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_t; @@ -1878,12 +1924,10 @@ typedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_ * * Clk_Rst: SRIOMAINT_ERB_LT_DEV_ID hclk hrst_n */ -union cvmx_sriomaintx_erb_lt_dev_id -{ +union cvmx_sriomaintx_erb_lt_dev_id { uint32_t u32; - struct cvmx_sriomaintx_erb_lt_dev_id_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_lt_dev_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t id16 : 8; /**< This is the most significant byte of the port-write destination deviceID (large transport systems only) @@ -1902,6 +1946,7 @@ union cvmx_sriomaintx_erb_lt_dev_id } s; struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xx; struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xxp1; + struct cvmx_sriomaintx_erb_lt_dev_id_s cn66xx; }; typedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t; @@ -1914,17 +1959,15 @@ typedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t; * * Notes: * This register contains error information. It is locked when a Logical/Transport error is detected - * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be + * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be * written only when error detection is disabled. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_DEV_ID_CAPT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_DEV_ID_CAPT hclk hrst_n */ -union cvmx_sriomaintx_erb_lt_dev_id_capt -{ +union cvmx_sriomaintx_erb_lt_dev_id_capt { uint32_t u32; - struct cvmx_sriomaintx_erb_lt_dev_id_capt_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_lt_dev_id_capt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t dst_id16 : 8; /**< Most significant byte of the large transport destination ID associated with the error */ uint32_t dst_id8 : 8; /**< Least significant byte of the large transport @@ -1944,6 +1987,7 @@ union cvmx_sriomaintx_erb_lt_dev_id_capt } s; struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xx; struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xxp1; + struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn66xx; }; typedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_capt_t; @@ -1964,14 +2008,12 @@ typedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_c * SRIOMAINT*_ERB_LT_DEV_ID_CAPT, and SRIOMAINT*_ERB_LT_CTRL_CAPT * (3) Write this CSR to 0. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ERR_DET hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ERR_DET hclk hrst_n */ -union cvmx_sriomaintx_erb_lt_err_det -{ +union cvmx_sriomaintx_erb_lt_err_det { uint32_t u32; - struct cvmx_sriomaintx_erb_lt_err_det_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_lt_err_det_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t io_err : 1; /**< Received a response of ERROR for an IO Logical Layer Request. This includes all Maintenance and Memory Responses not destined for the RX Soft @@ -2026,13 +2068,13 @@ union cvmx_sriomaintx_erb_lt_err_det soft packet fifo. */ uint32_t msg_tout : 1; /**< An expected incoming message request has not been received within the time-out interval specified in - SRIOMAINT(0..1)_PORT_RT_CTL. When a MSG_TOUT occurs, + SRIOMAINT(0,2..3)_PORT_RT_CTL. When a MSG_TOUT occurs, SRIO (internally) terminates the inflight message with an error. */ uint32_t pkt_tout : 1; /**< A required response has not been received to an outgoing memory, maintenance or message request before the time-out interval specified in - SRIOMAINT(0..1)_PORT_RT_CTL. When an IO or maintenance + SRIOMAINT(0,2..3)_PORT_RT_CTL. When an IO or maintenance read request operation has a PKT_TOUT, the issuing core load or DPI DMA engine receive all ones for the result. When an IO NWRITE_R has a PKT_TOUT, @@ -2077,6 +2119,7 @@ union cvmx_sriomaintx_erb_lt_err_det } s; struct cvmx_sriomaintx_erb_lt_err_det_s cn63xx; struct cvmx_sriomaintx_erb_lt_err_det_s cn63xxp1; + struct cvmx_sriomaintx_erb_lt_err_det_s cn66xx; }; typedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t; @@ -2091,14 +2134,12 @@ typedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t; * This register contains the bits that control if an error condition locks the Logical/Transport * Layer Error Detect and Capture registers and is reported to the system host. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ERR_EN hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ERR_EN hclk hrst_n */ -union cvmx_sriomaintx_erb_lt_err_en -{ +union cvmx_sriomaintx_erb_lt_err_en { uint32_t u32; - struct cvmx_sriomaintx_erb_lt_err_en_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_lt_err_en_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t io_err : 1; /**< Enable reporting of an IO error response. Save and lock original request transaction information in all Logical/Transport Layer Capture CSRs. */ @@ -2159,6 +2200,7 @@ union cvmx_sriomaintx_erb_lt_err_en } s; struct cvmx_sriomaintx_erb_lt_err_en_s cn63xx; struct cvmx_sriomaintx_erb_lt_err_en_s cn63xxp1; + struct cvmx_sriomaintx_erb_lt_err_en_s cn66xx; }; typedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t; @@ -2175,14 +2217,12 @@ typedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t; * The HW will not update this register (i.e. this register is locked) while * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_1 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_1 hclk hrst_n */ -union cvmx_sriomaintx_erb_pack_capt_1 -{ +union cvmx_sriomaintx_erb_pack_capt_1 { uint32_t u32; - struct cvmx_sriomaintx_erb_pack_capt_1_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_pack_capt_1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t capture : 32; /**< Bytes 4 thru 7 of the packet header. */ #else uint32_t capture : 32; @@ -2190,6 +2230,7 @@ union cvmx_sriomaintx_erb_pack_capt_1 } s; struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xx; struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xxp1; + struct cvmx_sriomaintx_erb_pack_capt_1_s cn66xx; }; typedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t; @@ -2205,14 +2246,12 @@ typedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t; * The HW will not update this register (i.e. this register is locked) while * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_2 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_2 hclk hrst_n */ -union cvmx_sriomaintx_erb_pack_capt_2 -{ +union cvmx_sriomaintx_erb_pack_capt_2 { uint32_t u32; - struct cvmx_sriomaintx_erb_pack_capt_2_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_pack_capt_2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t capture : 32; /**< Bytes 8 thru 11 of the packet header. */ #else uint32_t capture : 32; @@ -2220,6 +2259,7 @@ union cvmx_sriomaintx_erb_pack_capt_2 } s; struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xx; struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xxp1; + struct cvmx_sriomaintx_erb_pack_capt_2_s cn66xx; }; typedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t; @@ -2235,14 +2275,12 @@ typedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t; * The HW will not update this register (i.e. this register is locked) while * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_3 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_3 hclk hrst_n */ -union cvmx_sriomaintx_erb_pack_capt_3 -{ +union cvmx_sriomaintx_erb_pack_capt_3 { uint32_t u32; - struct cvmx_sriomaintx_erb_pack_capt_3_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_pack_capt_3_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t capture : 32; /**< Bytes 12 thru 15 of the packet header. */ #else uint32_t capture : 32; @@ -2250,6 +2288,7 @@ union cvmx_sriomaintx_erb_pack_capt_3 } s; struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xx; struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xxp1; + struct cvmx_sriomaintx_erb_pack_capt_3_s cn66xx; }; typedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t; @@ -2266,14 +2305,12 @@ typedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t; * SRIOMAINT*_ERB_ERR_DET. The HW will not update this register (i.e. this register is locked) while * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. * - * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT hclk hrst_n */ -union cvmx_sriomaintx_erb_pack_sym_capt -{ +union cvmx_sriomaintx_erb_pack_sym_capt { uint32_t u32; - struct cvmx_sriomaintx_erb_pack_sym_capt_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_erb_pack_sym_capt_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t capture : 32; /**< Control Character and Control Symbol or Bytes 0 to 3 of Packet Header The Control Symbol consists of @@ -2290,6 +2327,7 @@ union cvmx_sriomaintx_erb_pack_sym_capt } s; struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xx; struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xxp1; + struct cvmx_sriomaintx_erb_pack_sym_capt_s cn66xx; }; typedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_capt_t; @@ -2307,14 +2345,12 @@ typedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_cap * it to see if they have responsibility for initialization. The register can be unlocked by * rewriting the current host value. This will reset the lock and restore the value to 0xFFFF. * - * Clk_Rst: SRIOMAINT(0..1)_HB_DEV_ID_LOCK hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_HB_DEV_ID_LOCK hclk hrst_n */ -union cvmx_sriomaintx_hb_dev_id_lock -{ +union cvmx_sriomaintx_hb_dev_id_lock { uint32_t u32; - struct cvmx_sriomaintx_hb_dev_id_lock_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_hb_dev_id_lock_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31 : 16; uint32_t hostid : 16; /**< Primary 16-bit Device ID */ #else @@ -2324,6 +2360,7 @@ union cvmx_sriomaintx_hb_dev_id_lock } s; struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xx; struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xxp1; + struct cvmx_sriomaintx_hb_dev_id_lock_s cn66xx; }; typedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t; @@ -2337,44 +2374,15 @@ typedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t; * Notes: * This register controls the operation of the SRIO Core buffer mux logic. * - * Clk_Rst: SRIOMAINT(0..1)_IR_BUFFER_CONFIG hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG hclk hrst_n */ -union cvmx_sriomaintx_ir_buffer_config -{ +union cvmx_sriomaintx_ir_buffer_config { uint32_t u32; - struct cvmx_sriomaintx_ir_buffer_config_s - { -#if __BYTE_ORDER == __BIG_ENDIAN - uint32_t tx_wm0 : 4; /**< Transmitter Flow Control Priority 0 Threshold. - Number of Receive Buffers available before packet - can be scheduled for transmission. - Maximum Value 8. - Generally, TX_WM0 Must be > TX_WM1 to reserve - buffers for priority 1-3 packets when transmitting - in transmitter-controlled flow control mode. - TX_WM0 is not used by the hardware when TX_FLOW=0 - or whenever transmitting in - receiver-controlled flow-control mode. */ - uint32_t tx_wm1 : 4; /**< Transmitter Flow Control Priority 1 Threshold. - Number of Receive Buffers available before packet - can be scheduled for transmission. - Maximum Value 8. - Generally, TX_WM1 Must be > TX_WM2 to reserve - buffers for priority 2-3 packets when transmitting - in transmitter-controlled flow control mode. - TX_WM1 is not used by the hardware when TX_FLOW=0 - or whenever transmitting in - receiver-controlled flow-control mode. */ - uint32_t tx_wm2 : 4; /**< Transmitter Flow Control Priority 2 Threshold. - Number of Receive Buffers available before packet - can be scheduled for transmission. - Maximum Value 8. - Generally, TX_WM2 Must be > 0 to reserve a - buffer for priority 3 packets when transmitting - in transmitter-controlled flow control mode. - TX_WM2 is not used by the hardware when TX_FLOW=0 - or whenever transmitting in - receiver-controlled flow-control mode. */ + struct cvmx_sriomaintx_ir_buffer_config_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t tx_wm0 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ + uint32_t tx_wm1 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ + uint32_t tx_wm2 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ uint32_t reserved_3_19 : 17; uint32_t tx_flow : 1; /**< Controls whether Transmitter Flow Control is permitted on this device. @@ -2382,14 +2390,8 @@ union cvmx_sriomaintx_ir_buffer_config 1 - Permitted The reset value of this field is SRIO*_IP_FEATURE[TX_FLOW]. */ - uint32_t tx_sync : 1; /**< Controls whether the synchronizers are enabled - between the SRIO TXCLK and the Internal Clocks. - 0 - Synchronizers are enabled - 1 - Synchronizers are disabled */ - uint32_t rx_sync : 1; /**< Controls whether the synchronizers are enabled - between the SRIO RXCLK and the Internal Clocks. - 0 - Synchronizers are enabled - 1 - Synchronizers are disabled */ + uint32_t tx_sync : 1; /**< Reserved. */ + uint32_t rx_sync : 1; /**< Reserved. */ #else uint32_t rx_sync : 1; uint32_t tx_sync : 1; @@ -2402,13 +2404,14 @@ union cvmx_sriomaintx_ir_buffer_config } s; struct cvmx_sriomaintx_ir_buffer_config_s cn63xx; struct cvmx_sriomaintx_ir_buffer_config_s cn63xxp1; + struct cvmx_sriomaintx_ir_buffer_config_s cn66xx; }; typedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_t; /** * cvmx_sriomaint#_ir_buffer_config2 * - * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2 (Pass 2) + * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2 * * Buffer Configuration 2 * @@ -2418,14 +2421,12 @@ typedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_ * which can result in deadlocks. Disabling a priority is not recommended and can result in system * level failures. * - * Clk_Rst: SRIOMAINT(0..1)_IR_BUFFER_CONFIG2 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2 hclk hrst_n */ -union cvmx_sriomaintx_ir_buffer_config2 -{ +union cvmx_sriomaintx_ir_buffer_config2 { uint32_t u32; - struct cvmx_sriomaintx_ir_buffer_config2_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_buffer_config2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t tx_wm3 : 4; /**< Number of buffers free before a priority 3 packet will be transmitted. A value of 9 will disable this priority. */ @@ -2462,6 +2463,7 @@ union cvmx_sriomaintx_ir_buffer_config2 #endif } s; struct cvmx_sriomaintx_ir_buffer_config2_s cn63xx; + struct cvmx_sriomaintx_ir_buffer_config2_s cn66xx; }; typedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config2_t; @@ -2475,14 +2477,12 @@ typedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config * Notes: * This register can be used for testing. The register is otherwise unused by the hardware. * - * Clk_Rst: SRIOMAINT(0..1)_IR_PD_PHY_CTRL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_PD_PHY_CTRL hclk hrst_n */ -union cvmx_sriomaintx_ir_pd_phy_ctrl -{ +union cvmx_sriomaintx_ir_pd_phy_ctrl { uint32_t u32; - struct cvmx_sriomaintx_ir_pd_phy_ctrl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_pd_phy_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pd_ctrl : 32; /**< Unused Register available for testing */ #else uint32_t pd_ctrl : 32; @@ -2490,6 +2490,7 @@ union cvmx_sriomaintx_ir_pd_phy_ctrl } s; struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xx; struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xxp1; + struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn66xx; }; typedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t; @@ -2504,14 +2505,12 @@ typedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t; * This register is used to monitor PHY status on each lane. They are documented here to assist in * debugging only. The lane numbers take into account the lane swap pin. * - * Clk_Rst: SRIOMAINT(0..1)_IR_PD_PHY_STAT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_PD_PHY_STAT hclk hrst_n */ -union cvmx_sriomaintx_ir_pd_phy_stat -{ +union cvmx_sriomaintx_ir_pd_phy_stat { uint32_t u32; - struct cvmx_sriomaintx_ir_pd_phy_stat_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_pd_phy_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_16_31 : 16; uint32_t ln3_rx : 3; /**< Phy Lane 3 RX Status 0XX = Normal Operation @@ -2563,6 +2562,7 @@ union cvmx_sriomaintx_ir_pd_phy_stat } s; struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xx; struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xxp1; + struct cvmx_sriomaintx_ir_pd_phy_stat_s cn66xx; }; typedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t; @@ -2577,14 +2577,12 @@ typedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t; * This register is used to control platform independent operating modes of the transceivers. These * control bits are uniform across all platforms. * - * Clk_Rst: SRIOMAINT(0..1)_IR_PI_PHY_CTRL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_PI_PHY_CTRL hclk hrst_n */ -union cvmx_sriomaintx_ir_pi_phy_ctrl -{ +union cvmx_sriomaintx_ir_pi_phy_ctrl { uint32_t u32; - struct cvmx_sriomaintx_ir_pi_phy_ctrl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_pi_phy_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t tx_reset : 1; /**< Outgoing PHY Logic Reset. 0=Reset, 1=Normal Op */ uint32_t rx_reset : 1; /**< Incoming PHY Logic Reset. 0=Reset, 1=Normal Op */ uint32_t reserved_29_29 : 1; @@ -2606,6 +2604,7 @@ union cvmx_sriomaintx_ir_pi_phy_ctrl } s; struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xx; struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xxp1; + struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn66xx; }; typedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t; @@ -2618,19 +2617,17 @@ typedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t; * * Notes: * This register displays the status of the link initialization state machine. Changes to this state - * cause the SRIO(0..1)_INT_REG.LINK_UP or SRIO(0..1)_INT_REG.LINK_DOWN interrupts. + * cause the SRIO(0,2..3)_INT_REG.LINK_UP or SRIO(0,2..3)_INT_REG.LINK_DOWN interrupts. * - * Clk_Rst: SRIOMAINT(0..1)_IR_PI_PHY_STAT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_PI_PHY_STAT hclk hrst_n */ -union cvmx_sriomaintx_ir_pi_phy_stat -{ +union cvmx_sriomaintx_ir_pi_phy_stat { uint32_t u32; - struct cvmx_sriomaintx_ir_pi_phy_stat_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_pi_phy_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_12_31 : 20; - uint32_t tx_rdy : 1; /**< Minimum number of Status Transmitted (Pass 2) */ - uint32_t rx_rdy : 1; /**< Minimum number of Good Status Received (Pass 2) */ + uint32_t tx_rdy : 1; /**< Minimum number of Status Transmitted */ + uint32_t rx_rdy : 1; /**< Minimum number of Good Status Received */ uint32_t init_sm : 10; /**< Initialization State Machine 001 - Silent 002 - Seek @@ -2651,9 +2648,8 @@ union cvmx_sriomaintx_ir_pi_phy_stat #endif } s; struct cvmx_sriomaintx_ir_pi_phy_stat_s cn63xx; - struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1 - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_10_31 : 22; uint32_t init_sm : 10; /**< Initialization State Machine 001 - Silent @@ -2672,6 +2668,7 @@ union cvmx_sriomaintx_ir_pi_phy_stat uint32_t reserved_10_31 : 22; #endif } cn63xxp1; + struct cvmx_sriomaintx_ir_pi_phy_stat_s cn66xx; }; typedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t; @@ -2686,18 +2683,17 @@ typedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t; * This register is used to configure events generated by the reception of packets using the soft * packet FIFO. * - * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_CTRL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_CTRL hclk hrst_n */ -union cvmx_sriomaintx_ir_sp_rx_ctrl -{ +union cvmx_sriomaintx_ir_sp_rx_ctrl { uint32_t u32; - struct cvmx_sriomaintx_ir_sp_rx_ctrl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_sp_rx_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_1_31 : 31; uint32_t overwrt : 1; /**< When clear, SRIO drops received packets that should enter the soft packet FIFO when the FIFO is full. - When set, SRIO + In this case, SRIO also increments + SRIOMAINT(0,2..3)_IR_SP_RX_STAT.DROP_CNT. When set, SRIO stalls received packets that should enter the soft packet FIFO when the FIFO is full. SRIO may stop receiving any packets in this stall case if @@ -2710,6 +2706,7 @@ union cvmx_sriomaintx_ir_sp_rx_ctrl } s; struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xx; struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xxp1; + struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn66xx; }; typedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t; @@ -2730,14 +2727,12 @@ typedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t; * instead of the expected 83. In cases over 80 bytes the CRC at 80 bytes is removed but the * trailing CRC and Pad (if necessary) are present. * - * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_DATA hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_DATA hclk hrst_n */ -union cvmx_sriomaintx_ir_sp_rx_data -{ +union cvmx_sriomaintx_ir_sp_rx_data { uint32_t u32; - struct cvmx_sriomaintx_ir_sp_rx_data_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_sp_rx_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_data : 32; /**< This register is used to read packet data from the RX FIFO. */ #else @@ -2746,6 +2741,7 @@ union cvmx_sriomaintx_ir_sp_rx_data } s; struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xx; struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xxp1; + struct cvmx_sriomaintx_ir_sp_rx_data_s cn66xx; }; typedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t; @@ -2766,24 +2762,20 @@ typedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t; * This procedure could lead to situations where SOFT_RX will be set even though there are currently * no packets - the SW interrupt handler would need to properly handle this case * - * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_STAT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_STAT hclk hrst_n */ -union cvmx_sriomaintx_ir_sp_rx_stat -{ +union cvmx_sriomaintx_ir_sp_rx_stat { uint32_t u32; - struct cvmx_sriomaintx_ir_sp_rx_stat_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_sp_rx_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t octets : 16; /**< This field shows how many octets are remaining in the current packet in the RX FIFO. */ uint32_t buffers : 4; /**< This field indicates how many complete packets are stored in the Rx FIFO. */ uint32_t drop_cnt : 7; /**< Number of Packets Received when the RX FIFO was - full and then discarded. - This field always reads zero in Pass 1 */ + full and then discarded. */ uint32_t full : 1; /**< This bit is set when the value of Buffers Filled - equals the number of available reception buffers. - This bit always reads zero in Pass 1 */ + equals the number of available reception buffers. */ uint32_t fifo_st : 4; /**< These bits display the state of the state machine that controls loading of packet data into the RX FIFO. The enumeration of states are as follows: @@ -2800,9 +2792,8 @@ union cvmx_sriomaintx_ir_sp_rx_stat #endif } s; struct cvmx_sriomaintx_ir_sp_rx_stat_s cn63xx; - struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1 - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t octets : 16; /**< This field shows how many octets are remaining in the current packet in the RX FIFO. */ uint32_t buffers : 4; /**< This field indicates how many complete packets are @@ -2826,6 +2817,7 @@ union cvmx_sriomaintx_ir_sp_rx_stat uint32_t octets : 16; #endif } cn63xxp1; + struct cvmx_sriomaintx_ir_sp_rx_stat_s cn66xx; }; typedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t; @@ -2842,17 +2834,15 @@ typedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t; * * Clk_Rst: SRIOMAINT_IR_SP_TX_CTRL hclk hrst_n */ -union cvmx_sriomaintx_ir_sp_tx_ctrl -{ +union cvmx_sriomaintx_ir_sp_tx_ctrl { uint32_t u32; - struct cvmx_sriomaintx_ir_sp_tx_ctrl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_sp_tx_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t octets : 16; /**< Writing a non-zero value (N) to this field arms the packet FIFO for packet transmission. The FIFO control logic will transmit the next N bytes written 4-bytes at a time to the - SRIOMAINT(0..1)_IR_SP_TX_DATA Register and create a + SRIOMAINT(0,2..3)_IR_SP_TX_DATA Register and create a single RapidIO packet. */ uint32_t reserved_0_15 : 16; #else @@ -2862,6 +2852,7 @@ union cvmx_sriomaintx_ir_sp_tx_ctrl } s; struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xx; struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xxp1; + struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn66xx; }; typedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t; @@ -2878,16 +2869,14 @@ typedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t; * generate a response. Bits [7:6] of the 8 bit TID must be set for all Soft Packet FIFO generated * packets. TID values of 0x00 - 0xBF are reserved for hardware generated Tags. The remainer of the * TID[5:0] must be unique for each packet in flight and cannot be reused until a response is received - * in the SRIOMAINT(0..1)_IR_SP_RX_DATA register. + * in the SRIOMAINT(0,2..3)_IR_SP_RX_DATA register. * - * Clk_Rst: SRIOMAINT(0..1)_IR_SP_TX_DATA hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_TX_DATA hclk hrst_n */ -union cvmx_sriomaintx_ir_sp_tx_data -{ +union cvmx_sriomaintx_ir_sp_tx_data { uint32_t u32; - struct cvmx_sriomaintx_ir_sp_tx_data_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_sp_tx_data_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pkt_data : 32; /**< This register is used to write packet data to the Tx FIFO. Reads of this register will return zero. */ #else @@ -2896,6 +2885,7 @@ union cvmx_sriomaintx_ir_sp_tx_data } s; struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xx; struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xxp1; + struct cvmx_sriomaintx_ir_sp_tx_data_s cn66xx; }; typedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t; @@ -2909,14 +2899,12 @@ typedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t; * Notes: * This register is used to monitor the transmission of packets using the soft packet FIFO. * - * Clk_Rst: SRIOMAINT(0..1)_IR_SP_TX_STAT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_TX_STAT hclk hrst_n */ -union cvmx_sriomaintx_ir_sp_tx_stat -{ +union cvmx_sriomaintx_ir_sp_tx_stat { uint32_t u32; - struct cvmx_sriomaintx_ir_sp_tx_stat_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_ir_sp_tx_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t octets : 16; /**< This field shows how many octets are still to be loaded in the current packet. */ uint32_t buffers : 4; /**< This field indicates how many complete packets are @@ -2943,6 +2931,7 @@ union cvmx_sriomaintx_ir_sp_tx_stat } s; struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xx; struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xxp1; + struct cvmx_sriomaintx_ir_sp_tx_stat_s cn66xx; }; typedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t; @@ -2956,14 +2945,12 @@ typedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t; * Notes: * This register contains status information about the local lane transceiver. * - * Clk_Rst: SRIOMAINT(0..1)_LANE_[0:3]_STATUS_0 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_LANE_[0:3]_STATUS_0 hclk hrst_n */ -union cvmx_sriomaintx_lane_x_status_0 -{ +union cvmx_sriomaintx_lane_x_status_0 { uint32_t u32; - struct cvmx_sriomaintx_lane_x_status_0_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_lane_x_status_0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t port : 8; /**< The number of the port within the device to which the lane is assigned. */ uint32_t lane : 4; /**< Lane Number within the port. */ @@ -3022,6 +3009,7 @@ union cvmx_sriomaintx_lane_x_status_0 } s; struct cvmx_sriomaintx_lane_x_status_0_s cn63xx; struct cvmx_sriomaintx_lane_x_status_0_s cn63xxp1; + struct cvmx_sriomaintx_lane_x_status_0_s cn66xx; }; typedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t; @@ -3038,17 +3026,15 @@ typedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t; * not supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to * zero to match in a 34-bit access. SRIO Address 65:50 must be set to zero to match in a 50-bit * access. This coding allows the Maintenance Bar window to appear in specific address spaces. The - * remaining bits are located in SRIOMAINT(0..1)_LCS_BA1. This SRIO maintenance BAR is effectively + * remaining bits are located in SRIOMAINT(0,2..3)_LCS_BA1. This SRIO maintenance BAR is effectively * disabled when LCSBA[30] is set with 34 or 50-bit addressing. * - * Clk_Rst: SRIOMAINT(0..1)_LCS_BA0 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_LCS_BA0 hclk hrst_n */ -union cvmx_sriomaintx_lcs_ba0 -{ +union cvmx_sriomaintx_lcs_ba0 { uint32_t u32; - struct cvmx_sriomaintx_lcs_ba0_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_lcs_ba0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_31_31 : 1; uint32_t lcsba : 31; /**< SRIO Address 65:35 */ #else @@ -3058,6 +3044,7 @@ union cvmx_sriomaintx_lcs_ba0 } s; struct cvmx_sriomaintx_lcs_ba0_s cn63xx; struct cvmx_sriomaintx_lcs_ba0_s cn63xxp1; + struct cvmx_sriomaintx_lcs_ba0_s cn66xx; }; typedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t; @@ -3076,16 +3063,14 @@ typedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t; * This coding allows the Maintenance Bar window to appear in specific address spaces. Accesses * through this BAR are limited to single word (32-bit) aligned transfers of one to four bytes. * Accesses which violate this rule will return an error response if possible and be otherwise - * ignored. The remaining bits are located in SRIOMAINT(0..1)_LCS_BA0. + * ignored. The remaining bits are located in SRIOMAINT(0,2..3)_LCS_BA0. * - * Clk_Rst: SRIOMAINT(0..1)_LCS_BA1 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_LCS_BA1 hclk hrst_n */ -union cvmx_sriomaintx_lcs_ba1 -{ +union cvmx_sriomaintx_lcs_ba1 { uint32_t u32; - struct cvmx_sriomaintx_lcs_ba1_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_lcs_ba1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t lcsba : 11; /**< SRIO Address 34:24 */ uint32_t reserved_0_20 : 21; #else @@ -3095,6 +3080,7 @@ union cvmx_sriomaintx_lcs_ba1 } s; struct cvmx_sriomaintx_lcs_ba1_s cn63xx; struct cvmx_sriomaintx_lcs_ba1_s cn63xxp1; + struct cvmx_sriomaintx_lcs_ba1_s cn66xx; }; typedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t; @@ -3107,17 +3093,15 @@ typedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t; * * Notes: * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR0 Space. See - * SRIOMAINT(0..1)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the - * SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero. + * SRIOMAINT(0,2..3)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the + * SRIO(0,2..3)_ACC_CTRL.DENY_BAR0 bit is zero. * - * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR0_START0 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR0_START0 hclk hrst_n */ -union cvmx_sriomaintx_m2s_bar0_start0 -{ +union cvmx_sriomaintx_m2s_bar0_start0 { uint32_t u32; - struct cvmx_sriomaintx_m2s_bar0_start0_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_m2s_bar0_start0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t addr64 : 16; /**< SRIO Address 63:48 */ uint32_t addr48 : 16; /**< SRIO Address 47:32 */ #else @@ -3127,6 +3111,7 @@ union cvmx_sriomaintx_m2s_bar0_start0 } s; struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xx; struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xxp1; + struct cvmx_sriomaintx_m2s_bar0_start0_s cn66xx; }; typedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t; @@ -3147,17 +3132,16 @@ typedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t; * transactions require matches of all valid address field bits. Reads and Writes through Bar0 * have a size limit of 8 bytes and cannot cross a 64-bit boundry. All accesses with sizes greater * than this limit will be ignored and return an error on any SRIO responses. Note: ADDR48 and - * ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR0_START0. This register is only writeable over - * SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero. + * ADDR64 fields are located in SRIOMAINT(0,2..3)_M2S_BAR0_START0. The ADDR32/66 fields of this register + * are writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_ADR0 bit is zero. The ENABLE field is + * writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_BAR0 bit is zero. * - * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR0_START1 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR0_START1 hclk hrst_n */ -union cvmx_sriomaintx_m2s_bar0_start1 -{ +union cvmx_sriomaintx_m2s_bar0_start1 { uint32_t u32; - struct cvmx_sriomaintx_m2s_bar0_start1_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_m2s_bar0_start1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t addr32 : 18; /**< SRIO Address 31:14 */ uint32_t reserved_3_13 : 11; uint32_t addr66 : 2; /**< SRIO Address 65:64 */ @@ -3171,6 +3155,7 @@ union cvmx_sriomaintx_m2s_bar0_start1 } s; struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xx; struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xxp1; + struct cvmx_sriomaintx_m2s_bar0_start1_s cn66xx; }; typedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t; @@ -3183,19 +3168,21 @@ typedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t; * * Notes: * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR1 Space. See - * SRIOMAINT(0..1)_M2S_BAR1_START1 for more details. This register is only writeable over SRIO if the - * SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. + * SRIOMAINT(0,2..3)_M2S_BAR1_START1 for more details. This register is only writeable over SRIO if the + * SRIO(0,2..3)_ACC_CTRL.DENY_ADR1 bit is zero. * - * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR1_START0 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR1_START0 hclk hrst_n */ -union cvmx_sriomaintx_m2s_bar1_start0 -{ +union cvmx_sriomaintx_m2s_bar1_start0 { uint32_t u32; - struct cvmx_sriomaintx_m2s_bar1_start0_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_m2s_bar1_start0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t addr64 : 16; /**< SRIO Address 63:48 */ - uint32_t addr48 : 16; /**< SRIO Address 47:32 */ + uint32_t addr48 : 16; /**< SRIO Address 47:32 + The SRIO hardware does not use the low order + one or two bits of this field when BARSIZE is 12 + or 13, respectively. + (BARSIZE is SRIOMAINT(0,2..3)_M2S_BAR1_START1[BARSIZE].) */ #else uint32_t addr48 : 16; uint32_t addr64 : 16; @@ -3203,6 +3190,7 @@ union cvmx_sriomaintx_m2s_bar1_start0 } s; struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xx; struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xxp1; + struct cvmx_sriomaintx_m2s_bar1_start0_s cn66xx; }; typedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t; @@ -3218,24 +3206,25 @@ typedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t; * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers and the * address bits do not match enabled BAR0 addresses and if ENABLE is set and the addresses match the * BAR1 addresses then SRIO Memory transactions will map to Octeon Memory Space specified by - * SRIOMAINT(0..1)_BAR1_IDX[31:0] registers. The BARSIZE field determines the size of BAR1, the entry + * SRIOMAINT(0,2..3)_BAR1_IDX[31:0] registers. The BARSIZE field determines the size of BAR1, the entry * select bits, and the size of each entry. A 34-bit address matches BAR1 when it matches * SRIO_Address[33:20+BARSIZE] while all the other bits in ADDR48, ADDR64 and ADDR66 are zero. * A 50-bit address matches BAR1 when it matches SRIO_Address[49:20+BARSIZE] while all the * other bits of ADDR64 and ADDR66 are zero. A 66-bit address matches BAR1 when all of * SRIO_Address[65:20+BARSIZE] match all corresponding address CSR field bits. Note: ADDR48 and - * ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR1_START0. This register is only writeable from SRIO - * if the SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. + * ADDR64 fields are located in SRIOMAINT(0,2..3)_M2S_BAR1_START0. The ADDR32/66 fields of this register + * are writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_ADR1 bit is zero. The remaining fields are + * writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_BAR1 bit is zero. * - * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR1_START1 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR1_START1 hclk hrst_n */ -union cvmx_sriomaintx_m2s_bar1_start1 -{ +union cvmx_sriomaintx_m2s_bar1_start1 { uint32_t u32; - struct cvmx_sriomaintx_m2s_bar1_start1_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_m2s_bar1_start1_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t addr32 : 12; /**< SRIO Address 31:20 + This field is not used by the SRIO hardware for + BARSIZE values 12 or 13. With BARSIZE < 12, the upper 12-BARSIZE bits of this field are used, and the lower BARSIZE bits of this field are unused by the SRIO hardware. */ @@ -3255,21 +3244,16 @@ union cvmx_sriomaintx_m2s_bar1_start1 5 32MB 65:25 24:21 20:0 2MB 6 64MB 65:26 25:22 21:0 4MB 7 128MB 65:27 26:23 22:0 8MB - 8 256MB ** not in pass 1 - 9 512MB ** not in pass 1 - 10 1GB ** not in pass 1 - 11 2GB ** not in pass 1 - 12 4GB ** not in pass 1 - 13 8GB ** not in pass 1 + 8 256MB 65:28 27:24 23:0 16MB + 9 512MB 65:29 28:25 24:0 32MB + 10 1024MB 65:30 29:26 25:0 64MB + 11 2048MB 65:31 30:27 26:0 128MB + 12 4096MB 65:32 31:28 27:0 256MB + 13 8192MB 65:33 32:29 28:0 512MB *The SRIO Transaction Address The entry select bits is the X that select an - SRIOMAINT(0..1)_BAR1_IDXX entry. - - In O63 pass 2, BARSIZE is 4 bits (6:3 in this - CSR), and BARSIZE values 8-13 are implemented, - providing a total possible BAR1 size range from - 1MB up to 8GB. */ + SRIOMAINT(0,2..3)_BAR1_IDXX entry. */ uint32_t addr66 : 2; /**< SRIO Address 65:64 */ uint32_t enable : 1; /**< Enable BAR1 Access */ #else @@ -3281,9 +3265,8 @@ union cvmx_sriomaintx_m2s_bar1_start1 #endif } s; struct cvmx_sriomaintx_m2s_bar1_start1_s cn63xx; - struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1 - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1 { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t addr32 : 12; /**< SRIO Address 31:20 With BARSIZE < 12, the upper 12-BARSIZE bits of this field are used, and the lower BARSIZE @@ -3329,6 +3312,7 @@ union cvmx_sriomaintx_m2s_bar1_start1 uint32_t addr32 : 12; #endif } cn63xxp1; + struct cvmx_sriomaintx_m2s_bar1_start1_s cn66xx; }; typedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t; @@ -3346,16 +3330,16 @@ typedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t; * ADDR66, ADDR64 and ADDR48 fields set to zero and supplies zeros for unused addresses 40:34. * 50-bit address transactions a match of SRIO Address 49:41 and require all the other bits of ADDR64 * and ADDR66 to be zero. 66-bit address transactions require matches of all valid address field - * bits. This register is only writeable over SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR2 bit is zero. + * bits. The ADDR32/48/64/66 fields of this register are writeable over SRIO if the + * SRIO(0,2..3)_ACC_CTRL.DENY_ADR2 bit is zero. The remaining fields are writeable over SRIO if the + * SRIO(0,2..3)_ACC_CTRL.DENY_BAR2 bit is zero. * - * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR2_START hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR2_START hclk hrst_n */ -union cvmx_sriomaintx_m2s_bar2_start -{ +union cvmx_sriomaintx_m2s_bar2_start { uint32_t u32; - struct cvmx_sriomaintx_m2s_bar2_start_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_m2s_bar2_start_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t addr64 : 16; /**< SRIO Address 63:48 */ uint32_t addr48 : 7; /**< SRIO Address 47:41 */ uint32_t reserved_6_8 : 3; @@ -3384,13 +3368,14 @@ union cvmx_sriomaintx_m2s_bar2_start } s; struct cvmx_sriomaintx_m2s_bar2_start_s cn63xx; struct cvmx_sriomaintx_m2s_bar2_start_s cn63xxp1; + struct cvmx_sriomaintx_m2s_bar2_start_s cn66xx; }; typedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t; /** * cvmx_sriomaint#_mac_ctrl * - * SRIOMAINT_MAC_CTRL = SRIO MAC Control (Pass 2) + * SRIOMAINT_MAC_CTRL = SRIO MAC Control * * Control for MAC Features * @@ -3399,15 +3384,21 @@ typedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t; * default values should be supported. This register can be changed at any time while the MAC is * out of reset. * - * Clk_Rst: SRIOMAINT(0..1)_MAC_CTRL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_MAC_CTRL hclk hrst_n */ -union cvmx_sriomaintx_mac_ctrl -{ +union cvmx_sriomaintx_mac_ctrl { uint32_t u32; - struct cvmx_sriomaintx_mac_ctrl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN - uint32_t reserved_19_31 : 13; + struct cvmx_sriomaintx_mac_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_21_31 : 11; + uint32_t sec_spf : 1; /**< Send all Incoming Packets matching Secondary ID to + RX Soft Packet FIFO. This bit is ignored if + RX_SPF is set. */ + uint32_t ack_zero : 1; /**< Generate ACKs for all incoming Zero Byte packets. + Default behavior is to issue a NACK. Regardless + of this setting the SRIO(0,2..3)_INT_REG.ZERO_PKT + interrupt is generated. + SRIO(0,2..3)_INT_REG. */ uint32_t rx_spf : 1; /**< Route all received packets to RX Soft Packet FIFO. No logical layer ERB Errors will be reported. Used for Diagnostics Only. */ @@ -3416,16 +3407,44 @@ union cvmx_sriomaintx_mac_ctrl uint32_t type_mrg : 1; /**< Allow STYPE Merging on Transmit. */ uint32_t lnk_rtry : 16; /**< Number of times MAC will reissue Link Request after timeout. If retry count is exceeded Fatal - Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */ + Port Error will occur (see SRIO(0,2..3)_INT_REG.F_ERROR) */ #else uint32_t lnk_rtry : 16; uint32_t type_mrg : 1; uint32_t eop_mrg : 1; uint32_t rx_spf : 1; - uint32_t reserved_19_31 : 13; + uint32_t ack_zero : 1; + uint32_t sec_spf : 1; + uint32_t reserved_21_31 : 11; #endif } s; - struct cvmx_sriomaintx_mac_ctrl_s cn63xx; + struct cvmx_sriomaintx_mac_ctrl_cn63xx { +#ifdef __BIG_ENDIAN_BITFIELD + uint32_t reserved_20_31 : 12; + uint32_t ack_zero : 1; /**< Generate ACKs for all incoming Zero Byte packets. + Default behavior is to issue a NACK. Regardless + of this setting the SRIO(0..1)_INT_REG.ZERO_PKT + interrupt is generated. + SRIO(0..1)_INT_REG. */ + uint32_t rx_spf : 1; /**< Route all received packets to RX Soft Packet FIFO. + No logical layer ERB Errors will be reported. + Used for Diagnostics Only. */ + uint32_t eop_mrg : 1; /**< Transmitted Packets can eliminate EOP Symbol on + back to back packets. */ + uint32_t type_mrg : 1; /**< Allow STYPE Merging on Transmit. */ + uint32_t lnk_rtry : 16; /**< Number of times MAC will reissue Link Request + after timeout. If retry count is exceeded Fatal + Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */ +#else + uint32_t lnk_rtry : 16; + uint32_t type_mrg : 1; + uint32_t eop_mrg : 1; + uint32_t rx_spf : 1; + uint32_t ack_zero : 1; + uint32_t reserved_20_31 : 12; +#endif + } cn63xx; + struct cvmx_sriomaintx_mac_ctrl_s cn66xx; }; typedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t; @@ -3440,14 +3459,12 @@ typedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t; * The Processing Element Feature register describes the major functionality provided by the SRIO * device. * - * Clk_Rst: SRIOMAINT(0..1)_PE_FEAT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PE_FEAT hclk hrst_n */ -union cvmx_sriomaintx_pe_feat -{ +union cvmx_sriomaintx_pe_feat { uint32_t u32; - struct cvmx_sriomaintx_pe_feat_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_pe_feat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t bridge : 1; /**< Bridge Functions not supported. */ uint32_t memory : 1; /**< PE contains addressable memory. */ uint32_t proc : 1; /**< PE contains a local processor. */ @@ -3476,6 +3493,7 @@ union cvmx_sriomaintx_pe_feat } s; struct cvmx_sriomaintx_pe_feat_s cn63xx; struct cvmx_sriomaintx_pe_feat_s cn63xxp1; + struct cvmx_sriomaintx_pe_feat_s cn66xx; }; typedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t; @@ -3489,14 +3507,12 @@ typedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t; * Notes: * The Processing Element Logical Layer is used for general configuration for the logical interface. * - * Clk_Rst: SRIOMAINT(0..1)_PE_LLC hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PE_LLC hclk hrst_n */ -union cvmx_sriomaintx_pe_llc -{ +union cvmx_sriomaintx_pe_llc { uint32_t u32; - struct cvmx_sriomaintx_pe_llc_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_pe_llc_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_3_31 : 29; uint32_t ex_addr : 3; /**< Controls the number of address bits generated by PE as a source and processed by the PE as a @@ -3512,6 +3528,7 @@ union cvmx_sriomaintx_pe_llc } s; struct cvmx_sriomaintx_pe_llc_s cn63xx; struct cvmx_sriomaintx_pe_llc_s cn63xxp1; + struct cvmx_sriomaintx_pe_llc_s cn66xx; }; typedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t; @@ -3525,36 +3542,37 @@ typedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t; * Notes: * This register contains assorted control bits. * - * Clk_Rst: SRIOMAINT(0..1)_PORT_0_CTL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_CTL hclk hrst_n */ -union cvmx_sriomaintx_port_0_ctl -{ +union cvmx_sriomaintx_port_0_ctl { uint32_t u32; - struct cvmx_sriomaintx_port_0_ctl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_0_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t pt_width : 2; /**< Hardware Port Width. 00 = One Lane supported. - 01 = One/Two Lanes supported. - 10 = One/Four Lanes supported. + 01 = One/Four Lanes supported. + 10 = One/Two Lanes supported. 11 = One/Two/Four Lanes supported. - This is a RO copy of SRIO*_IP_FEATURE[PT_WIDTH]. */ + This value is a copy of SRIO*_IP_FEATURE[PT_WIDTH] + limited by the number of lanes the MAC has. */ uint32_t it_width : 3; /**< Initialized Port Width 000 = Single-lane, Lane 0 001 = Single-lane, Lane 1 or 2 010 = Four-lane 011 = Two-lane + 111 = Link Uninitialized Others = Reserved */ uint32_t ov_width : 3; /**< Override Port Width. Writing this register causes the port to reinitialize. 000 = No Override all lanes possible 001 = Reserved 010 = Force Single-lane, Lane 0 + If Ln 0 is unavailable try Ln 2 then Ln 1 011 = Force Single-lane, Lane 2 - (Lane 1 if only lanes 0,1 are connected) + If Ln 2 is unavailable try Ln 1 then Ln 0 100 = Reserved - 101 = Force Two-lane, Disable Four-Lane - 110 = Force Four-lane, Disable Two-Lane + 101 = Enable Two-lane, Disable Four-Lane + 110 = Enable Four-lane, Disable Two-Lane 111 = All lanes sizes enabled */ uint32_t disable : 1; /**< Port Disable. Setting this bit disables both drivers and receivers. */ @@ -3617,6 +3635,7 @@ union cvmx_sriomaintx_port_0_ctl } s; struct cvmx_sriomaintx_port_0_ctl_s cn63xx; struct cvmx_sriomaintx_port_0_ctl_s cn63xxp1; + struct cvmx_sriomaintx_port_0_ctl_s cn66xx; }; typedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t; @@ -3629,16 +3648,16 @@ typedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t; * * Notes: * These registers are accessed when a local processor or an external device wishes to examine the - * port baudrate information. WARNING: Writes to this register will reinitialize the SRIO link. + * port baudrate information. The Automatic Baud Rate Feature is not available on this device. The + * SUP_* and ENB_* fields are set directly by the QLM_SPD bits as a reference but otherwise have + * no effect. WARNING: Writes to this register will reinitialize the SRIO link. * - * Clk_Rst: SRIOMAINT(0..1)_PORT_0_CTL2 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_CTL2 hclk hrst_n */ -union cvmx_sriomaintx_port_0_ctl2 -{ +union cvmx_sriomaintx_port_0_ctl2 { uint32_t u32; - struct cvmx_sriomaintx_port_0_ctl2_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_0_ctl2_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t sel_baud : 4; /**< Link Baud Rate Selected. 0000 - No rate selected 0001 - 1.25 GBaud @@ -3648,8 +3667,7 @@ union cvmx_sriomaintx_port_0_ctl2 0101 - 6.25 GBaud (reserved) 0110 - 0b1111 - Reserved Indicates the speed of the interface SERDES lanes - (should match the value selected by SUP_* /ENB_* - below). */ + (selected by the QLM*_SPD straps). */ uint32_t baud_sup : 1; /**< Automatic Baud Rate Discovery not supported. */ uint32_t baud_enb : 1; /**< Auto Baud Rate Discovery Enable. */ uint32_t sup_125g : 1; /**< 1.25GB Rate Operation supported. @@ -3710,6 +3728,7 @@ union cvmx_sriomaintx_port_0_ctl2 } s; struct cvmx_sriomaintx_port_0_ctl2_s cn63xx; struct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1; + struct cvmx_sriomaintx_port_0_ctl2_s cn66xx; }; typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t; @@ -3723,23 +3742,22 @@ typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t; * Notes: * This register displays port error and status information. Several port error conditions are * captured here and must be cleared by writing 1's to the individual bits. + * Bits are R/W on 65/66xx pass 1 and R/W1C on pass 1.2 * - * Clk_Rst: SRIOMAINT(0..1)_PORT_0_ERR_STAT hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_ERR_STAT hclk hrst_n */ -union cvmx_sriomaintx_port_0_err_stat -{ +union cvmx_sriomaintx_port_0_err_stat { uint32_t u32; - struct cvmx_sriomaintx_port_0_err_stat_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_0_err_stat_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_27_31 : 5; uint32_t pkt_drop : 1; /**< Output Packet Dropped. */ uint32_t o_fail : 1; /**< Output Port has encountered a failure condition, meaning the port's failed error threshold has - reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_FAIL value. */ + reached SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR.ER_FAIL value. */ uint32_t o_dgrad : 1; /**< Output Port has encountered a degraded condition, meaning the port's degraded threshold has - reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_DGRAD + reached SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR.ER_DGRAD value. */ uint32_t reserved_21_23 : 3; uint32_t o_retry : 1; /**< Output Retry Encountered. This bit is set when @@ -3766,7 +3784,8 @@ union cvmx_sriomaintx_port_0_err_stat error. */ uint32_t reserved_5_7 : 3; uint32_t pt_write : 1; /**< Port has encountered a condition which required it - initiate a Maintenance Port-Write Operation. */ + initiate a Maintenance Port-Write Operation. + Never set by hardware. */ uint32_t reserved_3_3 : 1; uint32_t pt_error : 1; /**< Input or Output Port has encountered an unrecoverable error condition. */ @@ -3800,29 +3819,28 @@ union cvmx_sriomaintx_port_0_err_stat } s; struct cvmx_sriomaintx_port_0_err_stat_s cn63xx; struct cvmx_sriomaintx_port_0_err_stat_s cn63xxp1; + struct cvmx_sriomaintx_port_0_err_stat_s cn66xx; }; typedef union cvmx_sriomaintx_port_0_err_stat cvmx_sriomaintx_port_0_err_stat_t; /** * cvmx_sriomaint#_port_0_link_req * - * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request (Pass 2) + * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request * * Port 0 Manual Link Request * * Notes: * Writing this register generates the link request symbol or eight device reset symbols. The - * progress of the request can be determined by reading SRIOMAINT(0..1)_PORT_0_LINK_RESP. Only a single + * progress of the request can be determined by reading SRIOMAINT(0,2..3)_PORT_0_LINK_RESP. Only a single * request should be generated at a time. * - * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LINK_REQ hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LINK_REQ hclk hrst_n */ -union cvmx_sriomaintx_port_0_link_req -{ +union cvmx_sriomaintx_port_0_link_req { uint32_t u32; - struct cvmx_sriomaintx_port_0_link_req_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_0_link_req_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_3_31 : 29; uint32_t cmd : 3; /**< Link Request Command. 011 - Reset Device @@ -3834,27 +3852,26 @@ union cvmx_sriomaintx_port_0_link_req #endif } s; struct cvmx_sriomaintx_port_0_link_req_s cn63xx; + struct cvmx_sriomaintx_port_0_link_req_s cn66xx; }; typedef union cvmx_sriomaintx_port_0_link_req cvmx_sriomaintx_port_0_link_req_t; /** * cvmx_sriomaint#_port_0_link_resp * - * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response (Pass 2) + * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response * * Port 0 Manual Link Response * * Notes: - * This register only returns responses generated by writes to SRIOMAINT(0..1)_PORT_0_LINK_REQ. + * This register only returns responses generated by writes to SRIOMAINT(0,2..3)_PORT_0_LINK_REQ. * - * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LINK_RESP hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LINK_RESP hclk hrst_n */ -union cvmx_sriomaintx_port_0_link_resp -{ +union cvmx_sriomaintx_port_0_link_resp { uint32_t u32; - struct cvmx_sriomaintx_port_0_link_resp_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_0_link_resp_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t valid : 1; /**< Link Response Valid. 1 = Link Response Received or Reset Device Symbols Transmitted. Value cleared on read. @@ -3874,13 +3891,14 @@ union cvmx_sriomaintx_port_0_link_resp #endif } s; struct cvmx_sriomaintx_port_0_link_resp_s cn63xx; + struct cvmx_sriomaintx_port_0_link_resp_s cn66xx; }; typedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_t; /** * cvmx_sriomaint#_port_0_local_ackid * - * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID (Pass 2) + * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID * * Port 0 Local AckID Control * @@ -3888,16 +3906,14 @@ typedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_ * This register is typically only written when recovering from a failed link. It may be read at any * time the MAC is out of reset. Writes to the O_ACKID field will be used for both the O_ACKID and * E_ACKID. Care must be taken to ensure that no packets are pending at the time of a write. The - * number of pending packets can be read in the TX_INUSE field of SRIO(0..1)_MAC_BUFFERS. + * number of pending packets can be read in the TX_INUSE field of SRIO(0,2..3)_MAC_BUFFERS. * - * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LOCAL_ACKID hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LOCAL_ACKID hclk hrst_n */ -union cvmx_sriomaintx_port_0_local_ackid -{ +union cvmx_sriomaintx_port_0_local_ackid { uint32_t u32; - struct cvmx_sriomaintx_port_0_local_ackid_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_0_local_ackid_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_30_31 : 2; uint32_t i_ackid : 6; /**< Next Expected Inbound AckID. Bit 29 is used for IDLE2 and should be zero. */ @@ -3917,6 +3933,7 @@ union cvmx_sriomaintx_port_0_local_ackid #endif } s; struct cvmx_sriomaintx_port_0_local_ackid_s cn63xx; + struct cvmx_sriomaintx_port_0_local_ackid_s cn66xx; }; typedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ackid_t; @@ -3928,23 +3945,17 @@ typedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ac * Port General Control * * Notes: - * Clk_Rst: SRIOMAINT(0..1)_PORT_GEN_CTL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_GEN_CTL hclk hrst_n * */ -union cvmx_sriomaintx_port_gen_ctl -{ +union cvmx_sriomaintx_port_gen_ctl { uint32_t u32; - struct cvmx_sriomaintx_port_gen_ctl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_gen_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t host : 1; /**< Host Device. The HOST reset value is based on corresponding - MIO_RST_CTL*[PRTMODE], whose reset value is - selected by the corresponding QLM*_HOST_MODE strap - on a chip cold reset (and can be later modified by - software). HOST resets to 1 when - MIO_RST_CTL*[PRTMODE] selects RC (i.e. host) mode, - else 0. */ + MIO_RST_CTL*[PRTMODE]. HOST resets to 1 when + this field selects RC (i.e. host) mode, else 0. */ uint32_t menable : 1; /**< Master Enable. Must be set for device to issue read, write, doorbell, message requests. */ uint32_t discover : 1; /**< Discovered. The device has been discovered by the @@ -3959,6 +3970,7 @@ union cvmx_sriomaintx_port_gen_ctl } s; struct cvmx_sriomaintx_port_gen_ctl_s cn63xx; struct cvmx_sriomaintx_port_gen_ctl_s cn63xxp1; + struct cvmx_sriomaintx_port_gen_ctl_s cn66xx; }; typedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t; @@ -3975,18 +3987,16 @@ typedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t; * link-response. Each count represents 200ns. The minimum timeout period is the TIMEOUT x 200nS * and the maximum is twice that number. A value less than 32 may not guarantee that all timeout * errors will be reported correctly. When the timeout period expires the packet or link request is - * dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0..1)_ERB_ERR_DET register. A + * dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0,2..3)_ERB_ERR_DET register. A * value of 0 in this register will allow the packet or link request to be issued but it will timeout * immediately. This value is not recommended for normal operation. * - * Clk_Rst: SRIOMAINT(0..1)_PORT_LT_CTL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_LT_CTL hclk hrst_n */ -union cvmx_sriomaintx_port_lt_ctl -{ +union cvmx_sriomaintx_port_lt_ctl { uint32_t u32; - struct cvmx_sriomaintx_port_lt_ctl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_lt_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t timeout : 24; /**< Timeout Value */ uint32_t reserved_0_7 : 8; #else @@ -3996,6 +4006,7 @@ union cvmx_sriomaintx_port_lt_ctl } s; struct cvmx_sriomaintx_port_lt_ctl_s cn63xx; struct cvmx_sriomaintx_port_lt_ctl_s cn63xxp1; + struct cvmx_sriomaintx_port_lt_ctl_s cn66xx; }; typedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t; @@ -4007,15 +4018,13 @@ typedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t; * Port Maintenance Block Header 0 * * Notes: - * Clk_Rst: SRIOMAINT(0..1)_PORT_MBH0 hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_MBH0 hclk hrst_n * */ -union cvmx_sriomaintx_port_mbh0 -{ +union cvmx_sriomaintx_port_mbh0 { uint32_t u32; - struct cvmx_sriomaintx_port_mbh0_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_mbh0_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ef_ptr : 16; /**< Pointer to Error Management Block. */ uint32_t ef_id : 16; /**< Extended Feature ID (Generic Endpoint Device) */ #else @@ -4025,6 +4034,7 @@ union cvmx_sriomaintx_port_mbh0 } s; struct cvmx_sriomaintx_port_mbh0_s cn63xx; struct cvmx_sriomaintx_port_mbh0_s cn63xxp1; + struct cvmx_sriomaintx_port_mbh0_s cn66xx; }; typedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t; @@ -4041,22 +4051,20 @@ typedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t; * response being sent to receiving the corresponding response. This is used for all outgoing packet * types including memory, maintenance, doorbells and message operations. When the timeout period * expires the packet is disgarded and the error is logged in the PKT_TOUT field of the - * SRIOMAINT(0..1)_ERB_LT_ERR_DET register. The second use of this register is as a timeout period + * SRIOMAINT(0,2..3)_ERB_LT_ERR_DET register. The second use of this register is as a timeout period * between incoming message segments of the same message. If a message segment is received then the - * MSG_TOUT field of the SRIOMAINT(0..1)_ERB_LT_ERR_DET register is set if the next segment has not been + * MSG_TOUT field of the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET register is set if the next segment has not been * received before the time expires. In both cases, each count represents 200ns. The minimum * timeout period is the TIMEOUT x 200nS and the maximum is twice that number. A value less than 32 * may not guarantee that all timeout errors will be reported correctly. A value of 0 disables the * logical layer timeouts and is not recommended for normal operation. * - * Clk_Rst: SRIOMAINT(0..1)_PORT_RT_CTL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_RT_CTL hclk hrst_n */ -union cvmx_sriomaintx_port_rt_ctl -{ +union cvmx_sriomaintx_port_rt_ctl { uint32_t u32; - struct cvmx_sriomaintx_port_rt_ctl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_rt_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t timeout : 24; /**< Timeout Value */ uint32_t reserved_0_7 : 8; #else @@ -4066,13 +4074,14 @@ union cvmx_sriomaintx_port_rt_ctl } s; struct cvmx_sriomaintx_port_rt_ctl_s cn63xx; struct cvmx_sriomaintx_port_rt_ctl_s cn63xxp1; + struct cvmx_sriomaintx_port_rt_ctl_s cn66xx; }; typedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t; /** * cvmx_sriomaint#_port_ttl_ctl * - * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control (Pass 2) + * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control * * Packet Time to Live * @@ -4080,22 +4089,24 @@ typedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t; * This register controls the timeout for outgoing packets. It is used to make sure packets are * being transmitted and acknowledged within a reasonable period of time. The timeout value * corresponds to TIMEOUT x 200ns and a value of 0 disables the timer. The actualy value of the - * should be greater than the physical layer timout specified in SRIOMAINT(0..1)_PORT_LT_CTL and is - * typically a less SRIOMAINT(0..1)_PORT_LT_CTL timeout than the response timeout specified in - * SRIOMAINT(0..1)_PORT_RT_CTL. When the timeout expires the TTL interrupt is asserted, any packets - * currently being transmitted are dropped, the SRIOMAINT(0..1)_TX_DROP.DROP bit is set (causing any - * scheduled packets to be dropped), the SRIOMAINT(0..1)_TX_DROP.DROP_CNT is incremented and the SRIO - * output state is set to IDLE (all errors are cleared). Software must clear the - * SRIOMAINT(0..1)_TX_DROP.DROP bit to resume transmitting packets. - * - * Clk_Rst: SRIOMAINT(0..1)_PORT_RT_CTL hclk hrst_n + * should be greater than the physical layer timout specified in SRIOMAINT(0,2..3)_PORT_LT_CTL and is + * typically a less SRIOMAINT(0,2..3)_PORT_LT_CTL timeout than the response timeout specified in + * SRIOMAINT(0,2..3)_PORT_RT_CTL. A second application of this timer is to remove all the packets waiting + * to be transmitted including those already in flight. This may necessary in the case of a link + * going down (see SRIO(0,2..3)_INT_REG.LINK_DWN). This can accomplished by setting the TIMEOUT to small + * value all so that all TX packets can be dropped. In either case, when the timeout expires the TTL + * interrupt is asserted, any packets currently being transmitted are dropped, the + * SRIOMAINT(0,2..3)_TX_DROP.DROP bit is set (causing any scheduled packets to be dropped), the + * SRIOMAINT(0,2..3)_TX_DROP.DROP_CNT is incremented for each packet and the SRIO output state is set to + * IDLE (all errors are cleared). Software must clear the SRIOMAINT(0,2..3)_TX_DROP.DROP bit to resume + * transmitting packets. + * + * Clk_Rst: SRIOMAINT(0,2..3)_PORT_RT_CTL hclk hrst_n */ -union cvmx_sriomaintx_port_ttl_ctl -{ +union cvmx_sriomaintx_port_ttl_ctl { uint32_t u32; - struct cvmx_sriomaintx_port_ttl_ctl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_port_ttl_ctl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t timeout : 24; /**< Timeout Value */ uint32_t reserved_0_7 : 8; #else @@ -4104,6 +4115,7 @@ union cvmx_sriomaintx_port_ttl_ctl #endif } s; struct cvmx_sriomaintx_port_ttl_ctl_s cn63xx; + struct cvmx_sriomaintx_port_ttl_ctl_s cn66xx; }; typedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t; @@ -4116,16 +4128,14 @@ typedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t; * * Notes: * This register defines the primary 8 and 16 bit device IDs used for large and small transport. An - * optional secondary set of device IDs are located in SRIOMAINT(0..1)_SEC_DEV_ID. + * optional secondary set of device IDs are located in SRIOMAINT(0,2..3)_SEC_DEV_ID. * - * Clk_Rst: SRIOMAINT(0..1)_PRI_DEV_ID hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_PRI_DEV_ID hclk hrst_n */ -union cvmx_sriomaintx_pri_dev_id -{ +union cvmx_sriomaintx_pri_dev_id { uint32_t u32; - struct cvmx_sriomaintx_pri_dev_id_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_pri_dev_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31 : 8; uint32_t id8 : 8; /**< Primary 8-bit Device ID */ uint32_t id16 : 16; /**< Primary 16-bit Device ID */ @@ -4137,6 +4147,7 @@ union cvmx_sriomaintx_pri_dev_id } s; struct cvmx_sriomaintx_pri_dev_id_s cn63xx; struct cvmx_sriomaintx_pri_dev_id_s cn63xxp1; + struct cvmx_sriomaintx_pri_dev_id_s cn66xx; }; typedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t; @@ -4152,14 +4163,12 @@ typedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t; * The corresponding secondary ID must be written before the ID is enabled. The secondary IDs should * not be enabled if the values of the primary and secondary IDs are identical. * - * Clk_Rst: SRIOMAINT(0..1)_SEC_DEV_CTRL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_SEC_DEV_CTRL hclk hrst_n */ -union cvmx_sriomaintx_sec_dev_ctrl -{ +union cvmx_sriomaintx_sec_dev_ctrl { uint32_t u32; - struct cvmx_sriomaintx_sec_dev_ctrl_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_sec_dev_ctrl_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_2_31 : 30; uint32_t enable8 : 1; /**< Enable matches to secondary 8-bit Device ID */ uint32_t enable16 : 1; /**< Enable matches to secondary 16-bit Device ID */ @@ -4171,6 +4180,7 @@ union cvmx_sriomaintx_sec_dev_ctrl } s; struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xx; struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xxp1; + struct cvmx_sriomaintx_sec_dev_ctrl_s cn66xx; }; typedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t; @@ -4184,18 +4194,16 @@ typedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t; * Notes: * This register defines the secondary 8 and 16 bit device IDs used for large and small transport. * The corresponding secondary ID must be written before the ID is enabled in the - * SRIOMAINT(0..1)_SEC_DEV_CTRL register. The primary set of device IDs are located in - * SRIOMAINT(0..1)_PRI_DEV_ID register. The secondary IDs should not be written to the same values as the + * SRIOMAINT(0,2..3)_SEC_DEV_CTRL register. The primary set of device IDs are located in + * SRIOMAINT(0,2..3)_PRI_DEV_ID register. The secondary IDs should not be written to the same values as the * corresponding primary IDs. * - * Clk_Rst: SRIOMAINT(0..1)_SEC_DEV_ID hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_SEC_DEV_ID hclk hrst_n */ -union cvmx_sriomaintx_sec_dev_id -{ +union cvmx_sriomaintx_sec_dev_id { uint32_t u32; - struct cvmx_sriomaintx_sec_dev_id_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_sec_dev_id_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_24_31 : 8; uint32_t id8 : 8; /**< Secondary 8-bit Device ID */ uint32_t id16 : 16; /**< Secondary 16-bit Device ID */ @@ -4207,6 +4215,7 @@ union cvmx_sriomaintx_sec_dev_id } s; struct cvmx_sriomaintx_sec_dev_id_s cn63xx; struct cvmx_sriomaintx_sec_dev_id_s cn63xxp1; + struct cvmx_sriomaintx_sec_dev_id_s cn66xx; }; typedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t; @@ -4221,14 +4230,12 @@ typedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t; * The error management extensions block header register contains the EF_PTR to the next EF_BLK and * the EF_ID that identifies this as the Serial Lane Status Block. * - * Clk_Rst: SRIOMAINT(0..1)_SERIAL_LANE_HDR hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_SERIAL_LANE_HDR hclk hrst_n */ -union cvmx_sriomaintx_serial_lane_hdr -{ +union cvmx_sriomaintx_serial_lane_hdr { uint32_t u32; - struct cvmx_sriomaintx_serial_lane_hdr_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_serial_lane_hdr_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features data structure. */ uint32_t ef_id : 16; @@ -4239,6 +4246,7 @@ union cvmx_sriomaintx_serial_lane_hdr } s; struct cvmx_sriomaintx_serial_lane_hdr_s cn63xx; struct cvmx_sriomaintx_serial_lane_hdr_s cn63xxp1; + struct cvmx_sriomaintx_serial_lane_hdr_s cn66xx; }; typedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t; @@ -4251,16 +4259,14 @@ typedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t; * * Notes: * The logical operations initiated by the Cores. The Source OPs register shows the operations - * specified in the SRIO(0..1)_IP_FEATURE.OPS register. + * specified in the SRIO(0,2..3)_IP_FEATURE.OPS register. * - * Clk_Rst: SRIOMAINT(0..1)_SRC_OPS hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_SRC_OPS hclk hrst_n */ -union cvmx_sriomaintx_src_ops -{ +union cvmx_sriomaintx_src_ops { uint32_t u32; - struct cvmx_sriomaintx_src_ops_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_src_ops_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t gsm_read : 1; /**< PE does not support Read Home operations. This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */ uint32_t i_read : 1; /**< PE does not support Instruction Read. @@ -4342,43 +4348,43 @@ union cvmx_sriomaintx_src_ops } s; struct cvmx_sriomaintx_src_ops_s cn63xx; struct cvmx_sriomaintx_src_ops_s cn63xxp1; + struct cvmx_sriomaintx_src_ops_s cn66xx; }; typedef union cvmx_sriomaintx_src_ops cvmx_sriomaintx_src_ops_t; /** * cvmx_sriomaint#_tx_drop * - * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop (Pass 2) + * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop * * Outging SRIO Packet Drop Control/Status * * Notes: * This register controls and provides status for dropping outgoing SRIO packets. The DROP bit * should only be cleared when no packets are currently being dropped. This can be guaranteed by - * clearing the SRIOMAINT(0..1)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the + * clearing the SRIOMAINT(0,2..3)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the * O_ENABLE afterwards. * - * Clk_Rst: SRIOMAINT(0..1)_MAC_CTRL hclk hrst_n + * Clk_Rst: SRIOMAINT(0,2..3)_MAC_CTRL hclk hrst_n */ -union cvmx_sriomaintx_tx_drop -{ +union cvmx_sriomaintx_tx_drop { uint32_t u32; - struct cvmx_sriomaintx_tx_drop_s - { -#if __BYTE_ORDER == __BIG_ENDIAN + struct cvmx_sriomaintx_tx_drop_s { +#ifdef __BIG_ENDIAN_BITFIELD uint32_t reserved_17_31 : 15; uint32_t drop : 1; /**< All outgoing packets are dropped. Any packets requiring a response will return 1's after the - SRIOMAINT(0..1)_PORT_RT_CTL Timeout expires. This bit + SRIOMAINT(0,2..3)_PORT_RT_CTL Timeout expires. This bit is set automatically when the TTL Timeout occurs or can be set by software and must always be cleared by software. */ uint32_t drop_cnt : 16; /**< Number of packets dropped by transmit logic. Packets are dropped whenever a packet is ready to be transmitted and a TTL Timeouts occur, the DROP - bit is set or the SRIOMAINT(0..1)_ERB_ERR_RATE_THR + bit is set or the SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR FAIL_TH has been reached and the DROP_PKT bit is - set in SRIOMAINT(0..1)_PORT_0_CTL. */ + set in SRIOMAINT(0,2..3)_PORT_0_CTL. This counter wraps + on overflow and is cleared only on reset. */ #else uint32_t drop_cnt : 16; uint32_t drop : 1; @@ -4386,6 +4392,7 @@ union cvmx_sriomaintx_tx_drop #endif } s; struct cvmx_sriomaintx_tx_drop_s cn63xx; + struct cvmx_sriomaintx_tx_drop_s cn66xx; }; typedef union cvmx_sriomaintx_tx_drop cvmx_sriomaintx_tx_drop_t; -- cgit v1.2.3