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-rw-r--r--test/Transforms/InstCombine/minmax-fold.ll81
-rw-r--r--test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll54
2 files changed, 135 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/minmax-fold.ll b/test/Transforms/InstCombine/minmax-fold.ll
index e39f7f491cbc..bf46cefd8ab3 100644
--- a/test/Transforms/InstCombine/minmax-fold.ll
+++ b/test/Transforms/InstCombine/minmax-fold.ll
@@ -339,3 +339,84 @@ define i32 @test75(i32 %x) {
ret i32 %retval
}
+; The next 3 min tests should canonicalize to the same form...and not infinite loop.
+
+define double @PR31751_umin1(i32 %x) {
+; CHECK-LABEL: @PR31751_umin1(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %x, 2147483647
+; CHECK-NEXT: [[CONV1:%.*]] = select i1 [[TMP1]], i32 %x, i32 2147483647
+; CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[CONV1]] to double
+; CHECK-NEXT: ret double [[TMP2]]
+;
+ %cmp = icmp slt i32 %x, 0
+ %sel = select i1 %cmp, i32 2147483647, i32 %x
+ %conv = sitofp i32 %sel to double
+ ret double %conv
+}
+
+define double @PR31751_umin2(i32 %x) {
+; CHECK-LABEL: @PR31751_umin2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %x, 2147483647
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 2147483647
+; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[SEL]] to double
+; CHECK-NEXT: ret double [[CONV]]
+;
+ %cmp = icmp ult i32 %x, 2147483647
+ %sel = select i1 %cmp, i32 %x, i32 2147483647
+ %conv = sitofp i32 %sel to double
+ ret double %conv
+}
+
+define double @PR31751_umin3(i32 %x) {
+; CHECK-LABEL: @PR31751_umin3(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %x, 2147483647
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TMP1]], i32 %x, i32 2147483647
+; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[SEL]] to double
+; CHECK-NEXT: ret double [[CONV]]
+;
+ %cmp = icmp ugt i32 %x, 2147483647
+ %sel = select i1 %cmp, i32 2147483647, i32 %x
+ %conv = sitofp i32 %sel to double
+ ret double %conv
+}
+
+; The next 3 max tests should canonicalize to the same form...and not infinite loop.
+
+define double @PR31751_umax1(i32 %x) {
+; CHECK-LABEL: @PR31751_umax1(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 %x, -2147483648
+; CHECK-NEXT: [[CONV1:%.*]] = select i1 [[TMP1]], i32 %x, i32 -2147483648
+; CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[CONV1]] to double
+; CHECK-NEXT: ret double [[TMP2]]
+;
+ %cmp = icmp sgt i32 %x, -1
+ %sel = select i1 %cmp, i32 2147483648, i32 %x
+ %conv = sitofp i32 %sel to double
+ ret double %conv
+}
+
+define double @PR31751_umax2(i32 %x) {
+; CHECK-LABEL: @PR31751_umax2(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 %x, -2147483648
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 %x, i32 -2147483648
+; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[SEL]] to double
+; CHECK-NEXT: ret double [[CONV]]
+;
+ %cmp = icmp ugt i32 %x, 2147483648
+ %sel = select i1 %cmp, i32 %x, i32 2147483648
+ %conv = sitofp i32 %sel to double
+ ret double %conv
+}
+
+define double @PR31751_umax3(i32 %x) {
+; CHECK-LABEL: @PR31751_umax3(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 %x, -2147483648
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TMP1]], i32 %x, i32 -2147483648
+; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[SEL]] to double
+; CHECK-NEXT: ret double [[CONV]]
+;
+ %cmp = icmp ult i32 %x, 2147483648
+ %sel = select i1 %cmp, i32 2147483648, i32 %x
+ %conv = sitofp i32 %sel to double
+ ret double %conv
+}
diff --git a/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll b/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll
new file mode 100644
index 000000000000..b3b696d42c59
--- /dev/null
+++ b/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll
@@ -0,0 +1,54 @@
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -loop-reduce %s | FileCheck %s
+
+; Test for assert resulting from inconsistent isLegalAddressingMode
+; answers when the address space was dropped from the query.
+
+target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+
+%0 = type { i32, double, i32, float }
+
+; CHECK-LABEL: @lsr_crash_preserve_addrspace_unknown_type(
+; CHECK: %tmp4 = bitcast %0 addrspace(3)* %tmp to double addrspace(3)*
+; CHECK: %scevgep5 = getelementptr double, double addrspace(3)* %tmp4, i32 1
+; CHEC: load double, double addrspace(3)* %scevgep5
+
+; CHECK: %scevgep = getelementptr i32, i32 addrspace(3)* %tmp1, i32 4
+; CHECK:%tmp14 = load i32, i32 addrspace(3)* %scevgep
+define void @lsr_crash_preserve_addrspace_unknown_type() #0 {
+bb:
+ br label %bb1
+
+bb1: ; preds = %bb17, %bb
+ %tmp = phi %0 addrspace(3)* [ undef, %bb ], [ %tmp18, %bb17 ]
+ %tmp2 = getelementptr inbounds %0, %0 addrspace(3)* %tmp, i64 0, i32 1
+ %tmp3 = load double, double addrspace(3)* %tmp2, align 8
+ br label %bb4
+
+bb4: ; preds = %bb1
+ br i1 undef, label %bb8, label %bb5
+
+bb5: ; preds = %bb4
+ unreachable
+
+bb8: ; preds = %bb4
+ %tmp9 = getelementptr inbounds %0, %0 addrspace(3)* %tmp, i64 0, i32 0
+ %tmp10 = load i32, i32 addrspace(3)* %tmp9, align 4
+ %tmp11 = icmp eq i32 0, %tmp10
+ br i1 %tmp11, label %bb12, label %bb17
+
+bb12: ; preds = %bb8
+ %tmp13 = getelementptr inbounds %0, %0 addrspace(3)* %tmp, i64 0, i32 2
+ %tmp14 = load i32, i32 addrspace(3)* %tmp13, align 4
+ %tmp15 = icmp eq i32 0, %tmp14
+ br i1 %tmp15, label %bb16, label %bb17
+
+bb16: ; preds = %bb12
+ unreachable
+
+bb17: ; preds = %bb12, %bb8
+ %tmp18 = getelementptr inbounds %0, %0 addrspace(3)* %tmp, i64 2
+ br label %bb1
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }