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-rw-r--r--test/CodeGen/AArch64/win64-jumptable.ll48
-rw-r--r--test/CodeGen/AArch64/wineh-try-catch-cbz.ll40
-rw-r--r--test/CodeGen/AArch64/wineh-try-catch.ll4
-rw-r--r--test/CodeGen/WebAssembly/select.ll25
-rw-r--r--test/CodeGen/WebAssembly/simd-select.ll12
-rw-r--r--test/CodeGen/X86/code-model-elf.ll66
-rw-r--r--test/CodeGen/X86/pr40891.ll22
7 files changed, 205 insertions, 12 deletions
diff --git a/test/CodeGen/AArch64/win64-jumptable.ll b/test/CodeGen/AArch64/win64-jumptable.ll
new file mode 100644
index 000000000000..8148a593c91b
--- /dev/null
+++ b/test/CodeGen/AArch64/win64-jumptable.ll
@@ -0,0 +1,48 @@
+; RUN: llc -o - %s -mtriple=aarch64-windows -aarch64-enable-compress-jump-tables=0 | FileCheck %s
+
+define void @f(i32 %x) {
+entry:
+ switch i32 %x, label %sw.epilog [
+ i32 0, label %sw.bb
+ i32 1, label %sw.bb1
+ i32 2, label %sw.bb2
+ i32 3, label %sw.bb3
+ ]
+
+sw.bb: ; preds = %entry
+ tail call void @g(i32 0) #2
+ br label %sw.epilog
+
+sw.bb1: ; preds = %entry
+ tail call void @g(i32 1) #2
+ br label %sw.epilog
+
+sw.bb2: ; preds = %entry
+ tail call void @g(i32 2) #2
+ br label %sw.epilog
+
+sw.bb3: ; preds = %entry
+ tail call void @g(i32 3) #2
+ br label %sw.epilog
+
+sw.epilog: ; preds = %entry, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
+ tail call void @g(i32 10) #2
+ ret void
+}
+
+declare void @g(i32)
+
+; CHECK: .text
+; CHECK: f:
+; CHECK: .seh_proc f
+; CHECK: b g
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: .LJTI0_0:
+; CHECK: .word .LBB0_2-.LJTI0_0
+; CHECK: .word .LBB0_3-.LJTI0_0
+; CHECK: .word .LBB0_4-.LJTI0_0
+; CHECK: .word .LBB0_5-.LJTI0_0
+; CHECK: .section .xdata,"dr"
+; CHECK: .seh_handlerdata
+; CHECK: .text
+; CHECK: .seh_endproc
diff --git a/test/CodeGen/AArch64/wineh-try-catch-cbz.ll b/test/CodeGen/AArch64/wineh-try-catch-cbz.ll
new file mode 100644
index 000000000000..7c64328f0a7d
--- /dev/null
+++ b/test/CodeGen/AArch64/wineh-try-catch-cbz.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s | FileCheck %s
+
+; Make sure the prologue is sane. (Doesn't need to exactly match this,
+; but the original issue only reproduced if the cbz was immediately
+; after the frame setup.)
+
+; CHECK: sub sp, sp, #32
+; CHECK-NEXT: stp x29, x30, [sp, #16]
+; CHECK-NEXT: add x29, sp, #16
+; CHECK-NEXT: orr x1, xzr, #0xfffffffffffffffe
+; CHECK-NEXT: stur x1, [x29, #-16]
+; CHECK-NEXT: cbz w0, .LBB0_2
+
+target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-windows-msvc19.11.0"
+
+; Function Attrs: uwtable
+define dso_local void @"?f@@YAXH@Z"(i32 %x) local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
+entry:
+ %cmp = icmp eq i32 %x, 0
+ br i1 %cmp, label %try.cont, label %if.then
+
+if.then: ; preds = %entry
+ invoke void @"?g@@YAXXZ"()
+ to label %try.cont unwind label %catch.dispatch
+
+catch.dispatch: ; preds = %if.then
+ %0 = catchswitch within none [label %catch] unwind to caller
+
+catch: ; preds = %catch.dispatch
+ %1 = catchpad within %0 [i8* null, i32 64, i8* null]
+ catchret from %1 to label %try.cont
+
+try.cont: ; preds = %entry, %if.then, %catch
+ ret void
+}
+
+declare dso_local void @"?g@@YAXXZ"() local_unnamed_addr #1
+
+declare dso_local i32 @__CxxFrameHandler3(...)
diff --git a/test/CodeGen/AArch64/wineh-try-catch.ll b/test/CodeGen/AArch64/wineh-try-catch.ll
index 940a86282d39..f4bb9d50a434 100644
--- a/test/CodeGen/AArch64/wineh-try-catch.ll
+++ b/test/CodeGen/AArch64/wineh-try-catch.ll
@@ -22,8 +22,8 @@
; CHECK: add x29, sp, #32
; CHECK: sub sp, sp, #624
; CHECK: mov x19, sp
-; CHECK: orr x1, xzr, #0xfffffffffffffffe
-; CHECK: stur x1, [x19]
+; CHECK: orr x0, xzr, #0xfffffffffffffffe
+; CHECK: stur x0, [x19]
; Now check that x is stored at fp - 20. We check that this is the same
; location accessed from the funclet to retrieve x.
diff --git a/test/CodeGen/WebAssembly/select.ll b/test/CodeGen/WebAssembly/select.ll
index daa934f44844..ef18d9183e50 100644
--- a/test/CodeGen/WebAssembly/select.ll
+++ b/test/CodeGen/WebAssembly/select.ll
@@ -17,8 +17,10 @@ define i32 @select_i32_bool(i1 zeroext %a, i32 %b, i32 %c) {
; CHECK-LABEL: select_i32_bool_nozext:
; CHECK-NEXT: .functype select_i32_bool_nozext (i32, i32, i32) -> (i32){{$}}
-; SLOW-NEXT: i32.select $push0=, $1, $2, $0{{$}}
-; SLOW-NEXT: return $pop0{{$}}
+; SLOW-NEXT: i32.const $push0=, 1{{$}}
+; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
+; SLOW-NEXT: i32.select $push2=, $1, $2, $pop1{{$}}
+; SLOW-NEXT: return $pop2{{$}}
define i32 @select_i32_bool_nozext(i1 %a, i32 %b, i32 %c) {
%cond = select i1 %a, i32 %b, i32 %c
ret i32 %cond
@@ -55,8 +57,10 @@ define i64 @select_i64_bool(i1 zeroext %a, i64 %b, i64 %c) {
; CHECK-LABEL: select_i64_bool_nozext:
; CHECK-NEXT: .functype select_i64_bool_nozext (i32, i64, i64) -> (i64){{$}}
-; SLOW-NEXT: i64.select $push0=, $1, $2, $0{{$}}
-; SLOW-NEXT: return $pop0{{$}}
+; SLOW-NEXT: i32.const $push0=, 1{{$}}
+; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
+; SLOW-NEXT: i64.select $push2=, $1, $2, $pop1{{$}}
+; SLOW-NEXT: return $pop2{{$}}
define i64 @select_i64_bool_nozext(i1 %a, i64 %b, i64 %c) {
%cond = select i1 %a, i64 %b, i64 %c
ret i64 %cond
@@ -157,3 +161,16 @@ define double @select_f64_ne(i32 %a, double %b, double %c) {
%cond = select i1 %cmp, double %b, double %c
ret double %cond
}
+
+; CHECK-LABEL: pr40805:
+; CHECK-NEXT: .functype pr40805 (i32, i32, i32) -> (i32){{$}}
+; SLOW-NEXT: i32.const $push0=, 1{{$}}
+; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
+; SLOW-NEXT: i32.select $push2=, $1, $2, $pop1{{$}}
+; SLOW-NEXT: return $pop2{{$}}
+define i32 @pr40805(i32 %x, i32 %y, i32 %z) {
+ %a = and i32 %x, 1
+ %b = icmp ne i32 %a, 0
+ %c = select i1 %b, i32 %y, i32 %z
+ ret i32 %c
+}
diff --git a/test/CodeGen/WebAssembly/simd-select.ll b/test/CodeGen/WebAssembly/simd-select.ll
index c871f60e6454..c3af6f9abe60 100644
--- a/test/CodeGen/WebAssembly/simd-select.ll
+++ b/test/CodeGen/WebAssembly/simd-select.ll
@@ -29,7 +29,7 @@ define <16 x i8> @vselect_v16i8(<16 x i1> %c, <16 x i8> %x, <16 x i8> %y) {
; CHECK-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
-define <16 x i8> @select_v16i8(i1 %c, <16 x i8> %x, <16 x i8> %y) {
+define <16 x i8> @select_v16i8(i1 zeroext %c, <16 x i8> %x, <16 x i8> %y) {
%res = select i1 %c, <16 x i8> %x, <16 x i8> %y
ret <16 x i8> %res
}
@@ -99,7 +99,7 @@ define <8 x i16> @vselect_v8i16(<8 x i1> %c, <8 x i16> %x, <8 x i16> %y) {
; CHECK-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
-define <8 x i16> @select_v8i16(i1 %c, <8 x i16> %x, <8 x i16> %y) {
+define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %x, <8 x i16> %y) {
%res = select i1 %c, <8 x i16> %x, <8 x i16> %y
ret <8 x i16> %res
}
@@ -170,7 +170,7 @@ define <4 x i32> @vselect_v4i32(<4 x i1> %c, <4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
-define <4 x i32> @select_v4i32(i1 %c, <4 x i32> %x, <4 x i32> %y) {
+define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %x, <4 x i32> %y) {
%res = select i1 %c, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %res
}
@@ -240,7 +240,7 @@ define <2 x i64> @vselect_v2i64(<2 x i1> %c, <2 x i64> %x, <2 x i64> %y) {
; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
-define <2 x i64> @select_v2i64(i1 %c, <2 x i64> %x, <2 x i64> %y) {
+define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %x, <2 x i64> %y) {
%res = select i1 %c, <2 x i64> %x, <2 x i64> %y
ret <2 x i64> %res
}
@@ -313,7 +313,7 @@ define <4 x float> @vselect_v4f32(<4 x i1> %c, <4 x float> %x, <4 x float> %y) {
; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
-define <4 x float> @select_v4f32(i1 %c, <4 x float> %x, <4 x float> %y) {
+define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %x, <4 x float> %y) {
%res = select i1 %c, <4 x float> %x, <4 x float> %y
ret <4 x float> %res
}
@@ -383,7 +383,7 @@ define <2 x double> @vselect_v2f64(<2 x i1> %c, <2 x double> %x, <2 x double> %y
; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
-define <2 x double> @select_v2f64(i1 %c, <2 x double> %x, <2 x double> %y) {
+define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %x, <2 x double> %y) {
%res = select i1 %c, <2 x double> %x, <2 x double> %y
ret <2 x double> %res
}
diff --git a/test/CodeGen/X86/code-model-elf.ll b/test/CodeGen/X86/code-model-elf.ll
index 56d3f4c102f0..f7ffd6ea1eb7 100644
--- a/test/CodeGen/X86/code-model-elf.ll
+++ b/test/CodeGen/X86/code-model-elf.ll
@@ -37,6 +37,8 @@ target triple = "x86_64--linux"
@global_data = dso_local global [10 x i32] [i32 1, i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0], align 16
@static_data = internal global [10 x i32] zeroinitializer, align 16
@extern_data = external global [10 x i32], align 16
+@thread_data = external thread_local global i32, align 4
+
define dso_local i32* @lea_static_data() #0 {
; SMALL-STATIC-LABEL: lea_static_data:
@@ -373,6 +375,70 @@ define dso_local void ()* @lea_extern_fn() #0 {
ret void ()* @extern_fn
}
+; FIXME: The result is same for small, medium and large model, because we
+; specify pie option in the test case. And the type of tls is initial exec tls.
+; For pic code. The large model code for pic tls should be emitted as below.
+
+; .L3:
+; leaq .L3(%rip), %rbx
+; movabsq $_GLOBAL_OFFSET_TABLE_-.L3, %r11
+; addq %r11, %rbx
+; leaq thread_data@TLSGD(%rip), %rdi
+; movabsq $__tls_get_addr@PLTOFF, %rax
+; addq %rbx, %rax
+; call *%rax
+; movl (%rax), %eax
+
+; The medium and small model code for pic tls should be emitted as below.
+; data16
+; leaq thread_data@TLSGD(%rip), %rdi
+; data16
+; data16
+; rex64
+; callq __tls_get_addr@PLT
+; movl (%rax), %eax
+
+define dso_local i32 @load_thread_data() #0 {
+; SMALL-STATIC-LABEL: load_thread_data:
+; SMALL-STATIC: # %bb.0:
+; SMALL-STATIC-NEXT: movq thread_data@GOTTPOFF(%rip), %rax
+; SMALL-STATIC-NEXT: movl %fs:(%rax), %eax
+; SMALL-STATIC-NEXT: retq
+;
+; MEDIUM-STATIC-LABEL: load_thread_data:
+; MEDIUM-STATIC: # %bb.0:
+; MEDIUM-STATIC-NEXT: movq thread_data@GOTTPOFF(%rip), %rax
+; MEDIUM-STATIC-NEXT: movl %fs:(%rax), %eax
+; MEDIUM-STATIC-NEXT: retq
+;
+; LARGE-STATIC-LABEL: load_thread_data:
+; LARGE-STATIC: # %bb.0:
+; LARGE-STATIC-NEXT: movq thread_data@GOTTPOFF(%rip), %rax
+; LARGE-STATIC-NEXT: movl %fs:(%rax), %eax
+; LARGE-STATIC-NEXT: retq
+;
+; SMALL-PIC-LABEL: load_thread_data:
+; SMALL-PIC: # %bb.0:
+; SMALL-PIC-NEXT: movq thread_data@GOTTPOFF(%rip), %rax
+; SMALL-PIC-NEXT: movl %fs:(%rax), %eax
+; SMALL-PIC-NEXT: retq
+;
+; MEDIUM-PIC-LABEL: load_thread_data:
+; MEDIUM-PIC: # %bb.0:
+; MEDIUM-PIC-NEXT: movq thread_data@GOTTPOFF(%rip), %rax
+; MEDIUM-PIC-NEXT: movl %fs:(%rax), %eax
+; MEDIUM-PIC-NEXT: retq
+;
+; LARGE-PIC-LABEL: load_thread_data:
+; LARGE-PIC: # %bb.0:
+; LARGE-PIC-NEXT: movq thread_data@GOTTPOFF(%rip), %rax
+; LARGE-PIC-NEXT: movl %fs:(%rax), %eax
+; LARGE-PIC-NEXT: retq
+;
+ %1 = load i32, i32* @thread_data, align 4
+ ret i32 %1
+}
+
attributes #0 = { noinline nounwind uwtable }
!llvm.module.flags = !{!0, !1, !2}
diff --git a/test/CodeGen/X86/pr40891.ll b/test/CodeGen/X86/pr40891.ll
new file mode 100644
index 000000000000..3f3cfb23d03d
--- /dev/null
+++ b/test/CodeGen/X86/pr40891.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s
+
+; Make sure this sequence doesn't hang in DAG combine.
+
+define <8 x i32> @foo(<8 x i64> %x, <4 x i64> %y) {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vandps %ymm2, %ymm0, %ymm0
+; CHECK-NEXT: vandps {{\.LCPI.*}}, %ymm1, %ymm1
+; CHECK-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
+; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
+; CHECK-NEXT: vpermilps {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
+; CHECK-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,2,3]
+; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: retl
+ %a = shufflevector <4 x i64> %y, <4 x i64> <i64 12345, i64 67890, i64 13579, i64 24680>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %b = and <8 x i64> %x, %a
+ %c = trunc <8 x i64> %b to <8 x i32>
+ ret <8 x i32> %c
+}
+