diff options
Diffstat (limited to 'lib/builtins/clear_cache.c')
| -rw-r--r-- | lib/builtins/clear_cache.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/lib/builtins/clear_cache.c b/lib/builtins/clear_cache.c index 4a01cb46d4ac..9dcab344ad1b 100644 --- a/lib/builtins/clear_cache.c +++ b/lib/builtins/clear_cache.c @@ -33,6 +33,11 @@ uintptr_t GetCurrentProcess(void); #include <machine/sysarch.h> #endif +#if defined(__OpenBSD__) && defined(__mips__) + #include <sys/types.h> + #include <machine/sysarch.h> +#endif + #if defined(__linux__) && defined(__mips__) #include <sys/cachectl.h> #include <sys/syscall.h> @@ -96,6 +101,8 @@ void __clear_cache(void *start, void *end) { * Intel processors have a unified instruction and data cache * so there is nothing to do */ +#elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__)) + FlushInstructionCache(GetCurrentProcess(), start, end - start); #elif defined(__arm__) && !defined(__APPLE__) #if defined(__FreeBSD__) || defined(__NetBSD__) struct arm_sync_icache_args arg; @@ -123,8 +130,6 @@ void __clear_cache(void *start, void *end) { : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags)); assert(start_reg == 0 && "Cache flush syscall failed."); - #elif defined(_WIN32) - FlushInstructionCache(GetCurrentProcess(), start, end - start); #else compilerrt_abort(); #endif @@ -142,6 +147,8 @@ void __clear_cache(void *start, void *end) { #else syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE); #endif +#elif defined(__mips__) && defined(__OpenBSD__) + cacheflush(start, (uintptr_t)end - (uintptr_t)start, BCACHE); #elif defined(__aarch64__) && !defined(__APPLE__) uint64_t xstart = (uint64_t)(uintptr_t) start; uint64_t xend = (uint64_t)(uintptr_t) end; @@ -156,12 +163,14 @@ void __clear_cache(void *start, void *end) { * uintptr_t in case this runs in an IPL32 environment. */ const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); - for (addr = xstart; addr < xend; addr += dcache_line_size) + for (addr = xstart & ~(dcache_line_size - 1); addr < xend; + addr += dcache_line_size) __asm __volatile("dc cvau, %0" :: "r"(addr)); __asm __volatile("dsb ish"); const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); - for (addr = xstart; addr < xend; addr += icache_line_size) + for (addr = xstart & ~(icache_line_size - 1); addr < xend; + addr += icache_line_size) __asm __volatile("ic ivau, %0" :: "r"(addr)); __asm __volatile("isb sy"); #elif defined (__powerpc64__) |