aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM/ARMExpandPseudoInsts.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp')
-rw-r--r--lib/Target/ARM/ARMExpandPseudoInsts.cpp11
1 files changed, 4 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 56f5728ecfb8..a7b299677c1c 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -932,13 +932,10 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
.addReg(DestLo, getKillRegState(Dest.isDead()))
.addReg(DesiredLo, getKillRegState(Desired.isDead())));
- unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr;
- MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr))
- .addReg(StatusReg, RegState::Define | RegState::Dead)
- .addReg(DestHi, getKillRegState(Dest.isDead()))
- .addReg(DesiredHi, getKillRegState(Desired.isDead()));
- AddDefaultPred(MIB);
- MIB.addReg(ARM::CPSR, RegState::Kill);
+ BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
+ .addReg(DestHi, getKillRegState(Dest.isDead()))
+ .addReg(DesiredHi, getKillRegState(Desired.isDead()))
+ .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
BuildMI(LoadCmpBB, DL, TII->get(Bcc))