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-rw-r--r--lib/Target/AArch64/AArch64InstrFormats.td4
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index 15d61cd1ad26..7caf32dbde2a 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -4639,7 +4639,9 @@ class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
multiclass FPCondComparison<bit signalAllNans, string mnemonic,
SDPatternOperator OpNode = null_frag> {
- def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic, []> {
+ def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic,
+ [(set NZCV, (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm), (i32 imm:$nzcv),
+ (i32 imm:$cond), NZCV))]> {
let Inst{23-22} = 0b11;
let Predicates = [HasFullFP16];
}