path: root/docs/ReleaseNotes.rst
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Diffstat (limited to 'docs/ReleaseNotes.rst')
1 files changed, 45 insertions, 10 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst
index 549021e0e6e6..573fcb822aba 100644
--- a/docs/ReleaseNotes.rst
+++ b/docs/ReleaseNotes.rst
@@ -30,7 +30,8 @@ from now, will be version 5.0.0.
Non-comprehensive list of changes in this release
-* Minimum compiler version to build has been raised to GCC 4.8 and VS 2015.
+* The minimum compiler version required for building LLVM has been raised to
+ 4.8 for GCC and 2015 for Visual Studio.
* The C API functions ``LLVMAddFunctionAttr``, ``LLVMGetFunctionAttr``,
``LLVMRemoveFunctionAttr``, ``LLVMAddAttribute``, ``LLVMRemoveAttribute``,
@@ -56,15 +57,8 @@ Non-comprehensive list of changes in this release
with LLVM option ``-adce-remove-loops`` when the loop body otherwise has
no live operations.
-* The GVNHoist pass is now enabled by default. The new pass based on Global
- Value Numbering detects similar computations in branch code and replaces
- multiple instances of the same computation with a unique expression. The
- transform benefits code size and generates better schedules. GVNHoist is
- more aggressive at ``-Os`` and ``-Oz``, hoisting more expressions at the
- expense of execution time degradations.
- * The llvm-cov tool can now export coverage data as json. Its html output mode
- has also improved.
+* The llvm-cov tool can now export coverage data as json. Its html output mode
+ has also improved.
Improvements to ThinLTO (-flto=thin)
@@ -225,6 +219,10 @@ Changes to the ARM Targets
A lot of work has also been done in LLD for ARM, which now supports more
relocations and TLS.
+Note: From the next release (5.0), the "vulcan" target will be renamed to
+"thunderx2t99", including command line options, assembly directives, etc. This
+release (4.0) will be the last one to accept "vulcan" as its name.
Changes to the AVR Target
@@ -274,6 +272,15 @@ Changes to the MIPS Target
* Fixed several crashes involving FastISel.
* Corrected the corrected definitions for aui/daui/dahi/dati for MIPSR6.
+Changes to the X86 Target
+**During this release the X86 target has:**
+* Added support AMD Ryzen (znver1) CPUs.
+* Gained support for using VEX encoding on AVX-512 CPUs to reduce code size when possible.
+* Improved AVX-512 codegen.
Changes to the OCaml bindings
@@ -299,6 +306,34 @@ x86/x86_64 systems like Linux, OS X, FreeBSD and Windows and also Linux on ARM
and PowerPC (32/64 bit). Ports to other architectures like AArch64 and MIPS64
are underway.
+Portable Computing Language (pocl)
+In addition to producing an easily portable open source OpenCL
+implementation, another major goal of `pocl <http://pocl.sourceforge.net/>`_
+is improving performance portability of OpenCL programs with
+compiler optimizations, reducing the need for target-dependent manual
+optimizations. An important part of pocl is a set of LLVM passes used to
+statically parallelize multiple work-items with the kernel compiler, even in
+the presence of work-group barriers. This enables static parallelization of
+the fine-grained static concurrency in the work groups in multiple ways.
+TTA-based Co-design Environment (TCE)
+`TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing customized
+processors based on the Transport Triggered Architecture (TTA).
+The toolset provides a complete co-design flow from C/C++
+programs down to synthesizable VHDL/Verilog and parallel program binaries.
+Processor customization points include register files, function units,
+supported operations, and the interconnection network.
+TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
+optimizations and also for parts of code generation. It generates new
+LLVM-based code generators "on the fly" for the designed TTA processors and
+loads them in to the compiler backend as runtime libraries to avoid
+per-target recompilation of larger parts of the compiler chain.
Additional Information