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-rw-r--r--cvmx-rad-defs.h355
1 files changed, 212 insertions, 143 deletions
diff --git a/cvmx-rad-defs.h b/cvmx-rad-defs.h
index 374fabe0f880..edd5964dbc6a 100644
--- a/cvmx-rad-defs.h
+++ b/cvmx-rad-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_RAD_TYPEDEFS_H__
-#define __CVMX_RAD_TYPEDEFS_H__
+#ifndef __CVMX_RAD_DEFS_H__
+#define __CVMX_RAD_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC()
static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070001000ull);
}
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC()
static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070001008ull);
}
@@ -78,7 +78,7 @@ static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC()
static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070001010ull);
}
@@ -89,7 +89,7 @@ static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC()
static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000080ull);
}
@@ -100,7 +100,7 @@ static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC()
static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000008ull);
}
@@ -111,7 +111,7 @@ static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC()
static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000000ull);
}
@@ -122,7 +122,7 @@ static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000100ull);
}
@@ -133,7 +133,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000108ull);
}
@@ -144,7 +144,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000150ull);
}
@@ -155,7 +155,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000158ull);
}
@@ -166,7 +166,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000160ull);
}
@@ -177,7 +177,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000110ull);
}
@@ -188,7 +188,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000118ull);
}
@@ -199,7 +199,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000120ull);
}
@@ -210,7 +210,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000128ull);
}
@@ -221,7 +221,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000130ull);
}
@@ -232,7 +232,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000138ull);
}
@@ -243,7 +243,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000140ull);
}
@@ -254,7 +254,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC()
static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000148ull);
}
@@ -265,7 +265,7 @@ static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC()
static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000088ull);
}
@@ -276,7 +276,7 @@ static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC()
static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000090ull);
}
@@ -287,7 +287,7 @@ static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC()
static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000010ull);
}
@@ -298,7 +298,7 @@ static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC()
static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001180070000018ull);
}
@@ -314,12 +314,10 @@ static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
* CSR read operations to this address can be performed. A read of any entry that has not been
* previously written is illegal and will result in unpredictable CSR read data.
*/
-union cvmx_rad_mem_debug0
-{
+union cvmx_rad_mem_debug0 {
uint64_t u64;
- struct cvmx_rad_mem_debug0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_mem_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t iword : 64; /**< IWord */
#else
uint64_t iword : 64;
@@ -329,8 +327,13 @@ union cvmx_rad_mem_debug0
struct cvmx_rad_mem_debug0_s cn52xxp1;
struct cvmx_rad_mem_debug0_s cn56xx;
struct cvmx_rad_mem_debug0_s cn56xxp1;
+ struct cvmx_rad_mem_debug0_s cn61xx;
struct cvmx_rad_mem_debug0_s cn63xx;
struct cvmx_rad_mem_debug0_s cn63xxp1;
+ struct cvmx_rad_mem_debug0_s cn66xx;
+ struct cvmx_rad_mem_debug0_s cn68xx;
+ struct cvmx_rad_mem_debug0_s cn68xxp1;
+ struct cvmx_rad_mem_debug0_s cnf71xx;
};
typedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t;
@@ -342,12 +345,10 @@ typedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t;
* CSR read operations to this address can be performed. A read of any entry that has not been
* previously written is illegal and will result in unpredictable CSR read data.
*/
-union cvmx_rad_mem_debug1
-{
+union cvmx_rad_mem_debug1 {
uint64_t u64;
- struct cvmx_rad_mem_debug1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_mem_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t p_dat : 64; /**< P data */
#else
uint64_t p_dat : 64;
@@ -357,8 +358,13 @@ union cvmx_rad_mem_debug1
struct cvmx_rad_mem_debug1_s cn52xxp1;
struct cvmx_rad_mem_debug1_s cn56xx;
struct cvmx_rad_mem_debug1_s cn56xxp1;
+ struct cvmx_rad_mem_debug1_s cn61xx;
struct cvmx_rad_mem_debug1_s cn63xx;
struct cvmx_rad_mem_debug1_s cn63xxp1;
+ struct cvmx_rad_mem_debug1_s cn66xx;
+ struct cvmx_rad_mem_debug1_s cn68xx;
+ struct cvmx_rad_mem_debug1_s cn68xxp1;
+ struct cvmx_rad_mem_debug1_s cnf71xx;
};
typedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t;
@@ -370,12 +376,10 @@ typedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t;
* CSR read operations to this address can be performed. A read of any entry that has not been
* previously written is illegal and will result in unpredictable CSR read data.
*/
-union cvmx_rad_mem_debug2
-{
+union cvmx_rad_mem_debug2 {
uint64_t u64;
- struct cvmx_rad_mem_debug2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_mem_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t q_dat : 64; /**< Q data */
#else
uint64_t q_dat : 64;
@@ -385,8 +389,13 @@ union cvmx_rad_mem_debug2
struct cvmx_rad_mem_debug2_s cn52xxp1;
struct cvmx_rad_mem_debug2_s cn56xx;
struct cvmx_rad_mem_debug2_s cn56xxp1;
+ struct cvmx_rad_mem_debug2_s cn61xx;
struct cvmx_rad_mem_debug2_s cn63xx;
struct cvmx_rad_mem_debug2_s cn63xxp1;
+ struct cvmx_rad_mem_debug2_s cn66xx;
+ struct cvmx_rad_mem_debug2_s cn68xx;
+ struct cvmx_rad_mem_debug2_s cn68xxp1;
+ struct cvmx_rad_mem_debug2_s cnf71xx;
};
typedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t;
@@ -397,12 +406,10 @@ typedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t;
* Access to the internal BiST results
* Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
*/
-union cvmx_rad_reg_bist_result
-{
+union cvmx_rad_reg_bist_result {
uint64_t u64;
- struct cvmx_rad_reg_bist_result_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_bist_result_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t sta : 1; /**< BiST result of the STA memories */
uint64_t ncb_oub : 1; /**< BiST result of the NCB_OUB memories */
@@ -420,8 +427,13 @@ union cvmx_rad_reg_bist_result
struct cvmx_rad_reg_bist_result_s cn52xxp1;
struct cvmx_rad_reg_bist_result_s cn56xx;
struct cvmx_rad_reg_bist_result_s cn56xxp1;
+ struct cvmx_rad_reg_bist_result_s cn61xx;
struct cvmx_rad_reg_bist_result_s cn63xx;
struct cvmx_rad_reg_bist_result_s cn63xxp1;
+ struct cvmx_rad_reg_bist_result_s cn66xx;
+ struct cvmx_rad_reg_bist_result_s cn68xx;
+ struct cvmx_rad_reg_bist_result_s cn68xxp1;
+ struct cvmx_rad_reg_bist_result_s cnf71xx;
};
typedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t;
@@ -434,12 +446,10 @@ typedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t;
* lists to be used when freeing command buffer segments. The PTR field is overwritten with the next
* pointer each time that the command buffer segment is exhausted.
*/
-union cvmx_rad_reg_cmd_buf
-{
+union cvmx_rad_reg_cmd_buf {
uint64_t u64;
- struct cvmx_rad_reg_cmd_buf_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_cmd_buf_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_58_63 : 6;
uint64_t dwb : 9; /**< Number of DontWriteBacks */
uint64_t pool : 3; /**< Free list used to free command buffer segments */
@@ -457,8 +467,13 @@ union cvmx_rad_reg_cmd_buf
struct cvmx_rad_reg_cmd_buf_s cn52xxp1;
struct cvmx_rad_reg_cmd_buf_s cn56xx;
struct cvmx_rad_reg_cmd_buf_s cn56xxp1;
+ struct cvmx_rad_reg_cmd_buf_s cn61xx;
struct cvmx_rad_reg_cmd_buf_s cn63xx;
struct cvmx_rad_reg_cmd_buf_s cn63xxp1;
+ struct cvmx_rad_reg_cmd_buf_s cn66xx;
+ struct cvmx_rad_reg_cmd_buf_s cn68xx;
+ struct cvmx_rad_reg_cmd_buf_s cn68xxp1;
+ struct cvmx_rad_reg_cmd_buf_s cnf71xx;
};
typedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t;
@@ -469,12 +484,10 @@ typedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t;
* MAX_READ is a throttle to control NCB usage. Values >8 are illegal.
*
*/
-union cvmx_rad_reg_ctl
-{
+union cvmx_rad_reg_ctl {
uint64_t u64;
- struct cvmx_rad_reg_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t max_read : 4; /**< Maximum number of outstanding data read commands */
uint64_t store_le : 1; /**< Force STORE0 byte write address to little endian */
@@ -490,20 +503,23 @@ union cvmx_rad_reg_ctl
struct cvmx_rad_reg_ctl_s cn52xxp1;
struct cvmx_rad_reg_ctl_s cn56xx;
struct cvmx_rad_reg_ctl_s cn56xxp1;
+ struct cvmx_rad_reg_ctl_s cn61xx;
struct cvmx_rad_reg_ctl_s cn63xx;
struct cvmx_rad_reg_ctl_s cn63xxp1;
+ struct cvmx_rad_reg_ctl_s cn66xx;
+ struct cvmx_rad_reg_ctl_s cn68xx;
+ struct cvmx_rad_reg_ctl_s cn68xxp1;
+ struct cvmx_rad_reg_ctl_s cnf71xx;
};
typedef union cvmx_rad_reg_ctl cvmx_rad_reg_ctl_t;
/**
* cvmx_rad_reg_debug0
*/
-union cvmx_rad_reg_debug0
-{
+union cvmx_rad_reg_debug0 {
uint64_t u64;
- struct cvmx_rad_reg_debug0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_57_63 : 7;
uint64_t loop : 25; /**< Loop offset */
uint64_t reserved_22_31 : 10;
@@ -531,20 +547,23 @@ union cvmx_rad_reg_debug0
struct cvmx_rad_reg_debug0_s cn52xxp1;
struct cvmx_rad_reg_debug0_s cn56xx;
struct cvmx_rad_reg_debug0_s cn56xxp1;
+ struct cvmx_rad_reg_debug0_s cn61xx;
struct cvmx_rad_reg_debug0_s cn63xx;
struct cvmx_rad_reg_debug0_s cn63xxp1;
+ struct cvmx_rad_reg_debug0_s cn66xx;
+ struct cvmx_rad_reg_debug0_s cn68xx;
+ struct cvmx_rad_reg_debug0_s cn68xxp1;
+ struct cvmx_rad_reg_debug0_s cnf71xx;
};
typedef union cvmx_rad_reg_debug0 cvmx_rad_reg_debug0_t;
/**
* cvmx_rad_reg_debug1
*/
-union cvmx_rad_reg_debug1
-{
+union cvmx_rad_reg_debug1 {
uint64_t u64;
- struct cvmx_rad_reg_debug1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t cword : 64; /**< CWord */
#else
uint64_t cword : 64;
@@ -554,20 +573,23 @@ union cvmx_rad_reg_debug1
struct cvmx_rad_reg_debug1_s cn52xxp1;
struct cvmx_rad_reg_debug1_s cn56xx;
struct cvmx_rad_reg_debug1_s cn56xxp1;
+ struct cvmx_rad_reg_debug1_s cn61xx;
struct cvmx_rad_reg_debug1_s cn63xx;
struct cvmx_rad_reg_debug1_s cn63xxp1;
+ struct cvmx_rad_reg_debug1_s cn66xx;
+ struct cvmx_rad_reg_debug1_s cn68xx;
+ struct cvmx_rad_reg_debug1_s cn68xxp1;
+ struct cvmx_rad_reg_debug1_s cnf71xx;
};
typedef union cvmx_rad_reg_debug1 cvmx_rad_reg_debug1_t;
/**
* cvmx_rad_reg_debug10
*/
-union cvmx_rad_reg_debug10
-{
+union cvmx_rad_reg_debug10 {
uint64_t u64;
- struct cvmx_rad_reg_debug10_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug10_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t flags : 8; /**< OCTL flags */
uint64_t size : 16; /**< OCTL size (bytes) */
uint64_t ptr : 40; /**< OCTL pointer */
@@ -581,20 +603,23 @@ union cvmx_rad_reg_debug10
struct cvmx_rad_reg_debug10_s cn52xxp1;
struct cvmx_rad_reg_debug10_s cn56xx;
struct cvmx_rad_reg_debug10_s cn56xxp1;
+ struct cvmx_rad_reg_debug10_s cn61xx;
struct cvmx_rad_reg_debug10_s cn63xx;
struct cvmx_rad_reg_debug10_s cn63xxp1;
+ struct cvmx_rad_reg_debug10_s cn66xx;
+ struct cvmx_rad_reg_debug10_s cn68xx;
+ struct cvmx_rad_reg_debug10_s cn68xxp1;
+ struct cvmx_rad_reg_debug10_s cnf71xx;
};
typedef union cvmx_rad_reg_debug10 cvmx_rad_reg_debug10_t;
/**
* cvmx_rad_reg_debug11
*/
-union cvmx_rad_reg_debug11
-{
+union cvmx_rad_reg_debug11 {
uint64_t u64;
- struct cvmx_rad_reg_debug11_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug11_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63 : 51;
uint64_t q : 1; /**< OCTL q flag */
uint64_t p : 1; /**< OCTL p flag */
@@ -616,20 +641,23 @@ union cvmx_rad_reg_debug11
struct cvmx_rad_reg_debug11_s cn52xxp1;
struct cvmx_rad_reg_debug11_s cn56xx;
struct cvmx_rad_reg_debug11_s cn56xxp1;
+ struct cvmx_rad_reg_debug11_s cn61xx;
struct cvmx_rad_reg_debug11_s cn63xx;
struct cvmx_rad_reg_debug11_s cn63xxp1;
+ struct cvmx_rad_reg_debug11_s cn66xx;
+ struct cvmx_rad_reg_debug11_s cn68xx;
+ struct cvmx_rad_reg_debug11_s cn68xxp1;
+ struct cvmx_rad_reg_debug11_s cnf71xx;
};
typedef union cvmx_rad_reg_debug11 cvmx_rad_reg_debug11_t;
/**
* cvmx_rad_reg_debug12
*/
-union cvmx_rad_reg_debug12
-{
+union cvmx_rad_reg_debug12 {
uint64_t u64;
- struct cvmx_rad_reg_debug12_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug12_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_15_63 : 49;
uint64_t asserts : 15; /**< Various assertion checks */
#else
@@ -641,20 +669,23 @@ union cvmx_rad_reg_debug12
struct cvmx_rad_reg_debug12_s cn52xxp1;
struct cvmx_rad_reg_debug12_s cn56xx;
struct cvmx_rad_reg_debug12_s cn56xxp1;
+ struct cvmx_rad_reg_debug12_s cn61xx;
struct cvmx_rad_reg_debug12_s cn63xx;
struct cvmx_rad_reg_debug12_s cn63xxp1;
+ struct cvmx_rad_reg_debug12_s cn66xx;
+ struct cvmx_rad_reg_debug12_s cn68xx;
+ struct cvmx_rad_reg_debug12_s cn68xxp1;
+ struct cvmx_rad_reg_debug12_s cnf71xx;
};
typedef union cvmx_rad_reg_debug12 cvmx_rad_reg_debug12_t;
/**
* cvmx_rad_reg_debug2
*/
-union cvmx_rad_reg_debug2
-{
+union cvmx_rad_reg_debug2 {
uint64_t u64;
- struct cvmx_rad_reg_debug2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t owordp : 64; /**< OWordP */
#else
uint64_t owordp : 64;
@@ -664,20 +695,23 @@ union cvmx_rad_reg_debug2
struct cvmx_rad_reg_debug2_s cn52xxp1;
struct cvmx_rad_reg_debug2_s cn56xx;
struct cvmx_rad_reg_debug2_s cn56xxp1;
+ struct cvmx_rad_reg_debug2_s cn61xx;
struct cvmx_rad_reg_debug2_s cn63xx;
struct cvmx_rad_reg_debug2_s cn63xxp1;
+ struct cvmx_rad_reg_debug2_s cn66xx;
+ struct cvmx_rad_reg_debug2_s cn68xx;
+ struct cvmx_rad_reg_debug2_s cn68xxp1;
+ struct cvmx_rad_reg_debug2_s cnf71xx;
};
typedef union cvmx_rad_reg_debug2 cvmx_rad_reg_debug2_t;
/**
* cvmx_rad_reg_debug3
*/
-union cvmx_rad_reg_debug3
-{
+union cvmx_rad_reg_debug3 {
uint64_t u64;
- struct cvmx_rad_reg_debug3_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t owordq : 64; /**< OWordQ */
#else
uint64_t owordq : 64;
@@ -687,20 +721,23 @@ union cvmx_rad_reg_debug3
struct cvmx_rad_reg_debug3_s cn52xxp1;
struct cvmx_rad_reg_debug3_s cn56xx;
struct cvmx_rad_reg_debug3_s cn56xxp1;
+ struct cvmx_rad_reg_debug3_s cn61xx;
struct cvmx_rad_reg_debug3_s cn63xx;
struct cvmx_rad_reg_debug3_s cn63xxp1;
+ struct cvmx_rad_reg_debug3_s cn66xx;
+ struct cvmx_rad_reg_debug3_s cn68xx;
+ struct cvmx_rad_reg_debug3_s cn68xxp1;
+ struct cvmx_rad_reg_debug3_s cnf71xx;
};
typedef union cvmx_rad_reg_debug3 cvmx_rad_reg_debug3_t;
/**
* cvmx_rad_reg_debug4
*/
-union cvmx_rad_reg_debug4
-{
+union cvmx_rad_reg_debug4 {
uint64_t u64;
- struct cvmx_rad_reg_debug4_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rword : 64; /**< RWord */
#else
uint64_t rword : 64;
@@ -710,20 +747,23 @@ union cvmx_rad_reg_debug4
struct cvmx_rad_reg_debug4_s cn52xxp1;
struct cvmx_rad_reg_debug4_s cn56xx;
struct cvmx_rad_reg_debug4_s cn56xxp1;
+ struct cvmx_rad_reg_debug4_s cn61xx;
struct cvmx_rad_reg_debug4_s cn63xx;
struct cvmx_rad_reg_debug4_s cn63xxp1;
+ struct cvmx_rad_reg_debug4_s cn66xx;
+ struct cvmx_rad_reg_debug4_s cn68xx;
+ struct cvmx_rad_reg_debug4_s cn68xxp1;
+ struct cvmx_rad_reg_debug4_s cnf71xx;
};
typedef union cvmx_rad_reg_debug4 cvmx_rad_reg_debug4_t;
/**
* cvmx_rad_reg_debug5
*/
-union cvmx_rad_reg_debug5
-{
+union cvmx_rad_reg_debug5 {
uint64_t u64;
- struct cvmx_rad_reg_debug5_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_53_63 : 11;
uint64_t niropc7 : 3; /**< NCBI ropc (stage7 grant) */
uint64_t nirque7 : 2; /**< NCBI rque (stage7 grant) */
@@ -767,20 +807,23 @@ union cvmx_rad_reg_debug5
struct cvmx_rad_reg_debug5_s cn52xxp1;
struct cvmx_rad_reg_debug5_s cn56xx;
struct cvmx_rad_reg_debug5_s cn56xxp1;
+ struct cvmx_rad_reg_debug5_s cn61xx;
struct cvmx_rad_reg_debug5_s cn63xx;
struct cvmx_rad_reg_debug5_s cn63xxp1;
+ struct cvmx_rad_reg_debug5_s cn66xx;
+ struct cvmx_rad_reg_debug5_s cn68xx;
+ struct cvmx_rad_reg_debug5_s cn68xxp1;
+ struct cvmx_rad_reg_debug5_s cnf71xx;
};
typedef union cvmx_rad_reg_debug5 cvmx_rad_reg_debug5_t;
/**
* cvmx_rad_reg_debug6
*/
-union cvmx_rad_reg_debug6
-{
+union cvmx_rad_reg_debug6 {
uint64_t u64;
- struct cvmx_rad_reg_debug6_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t cnt : 8; /**< CCTL count[7:0] (bytes) */
uint64_t size : 16; /**< CCTL size (bytes) */
uint64_t ptr : 40; /**< CCTL pointer */
@@ -794,20 +837,23 @@ union cvmx_rad_reg_debug6
struct cvmx_rad_reg_debug6_s cn52xxp1;
struct cvmx_rad_reg_debug6_s cn56xx;
struct cvmx_rad_reg_debug6_s cn56xxp1;
+ struct cvmx_rad_reg_debug6_s cn61xx;
struct cvmx_rad_reg_debug6_s cn63xx;
struct cvmx_rad_reg_debug6_s cn63xxp1;
+ struct cvmx_rad_reg_debug6_s cn66xx;
+ struct cvmx_rad_reg_debug6_s cn68xx;
+ struct cvmx_rad_reg_debug6_s cn68xxp1;
+ struct cvmx_rad_reg_debug6_s cnf71xx;
};
typedef union cvmx_rad_reg_debug6 cvmx_rad_reg_debug6_t;
/**
* cvmx_rad_reg_debug7
*/
-union cvmx_rad_reg_debug7
-{
+union cvmx_rad_reg_debug7 {
uint64_t u64;
- struct cvmx_rad_reg_debug7_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_15_63 : 49;
uint64_t cnt : 15; /**< CCTL count[22:8] (bytes) */
#else
@@ -819,20 +865,23 @@ union cvmx_rad_reg_debug7
struct cvmx_rad_reg_debug7_s cn52xxp1;
struct cvmx_rad_reg_debug7_s cn56xx;
struct cvmx_rad_reg_debug7_s cn56xxp1;
+ struct cvmx_rad_reg_debug7_s cn61xx;
struct cvmx_rad_reg_debug7_s cn63xx;
struct cvmx_rad_reg_debug7_s cn63xxp1;
+ struct cvmx_rad_reg_debug7_s cn66xx;
+ struct cvmx_rad_reg_debug7_s cn68xx;
+ struct cvmx_rad_reg_debug7_s cn68xxp1;
+ struct cvmx_rad_reg_debug7_s cnf71xx;
};
typedef union cvmx_rad_reg_debug7 cvmx_rad_reg_debug7_t;
/**
* cvmx_rad_reg_debug8
*/
-union cvmx_rad_reg_debug8
-{
+union cvmx_rad_reg_debug8 {
uint64_t u64;
- struct cvmx_rad_reg_debug8_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t flags : 8; /**< ICTL flags */
uint64_t size : 16; /**< ICTL size (bytes) */
uint64_t ptr : 40; /**< ICTL pointer */
@@ -846,20 +895,23 @@ union cvmx_rad_reg_debug8
struct cvmx_rad_reg_debug8_s cn52xxp1;
struct cvmx_rad_reg_debug8_s cn56xx;
struct cvmx_rad_reg_debug8_s cn56xxp1;
+ struct cvmx_rad_reg_debug8_s cn61xx;
struct cvmx_rad_reg_debug8_s cn63xx;
struct cvmx_rad_reg_debug8_s cn63xxp1;
+ struct cvmx_rad_reg_debug8_s cn66xx;
+ struct cvmx_rad_reg_debug8_s cn68xx;
+ struct cvmx_rad_reg_debug8_s cn68xxp1;
+ struct cvmx_rad_reg_debug8_s cnf71xx;
};
typedef union cvmx_rad_reg_debug8 cvmx_rad_reg_debug8_t;
/**
* cvmx_rad_reg_debug9
*/
-union cvmx_rad_reg_debug9
-{
+union cvmx_rad_reg_debug9 {
uint64_t u64;
- struct cvmx_rad_reg_debug9_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_debug9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t eod : 1; /**< ICTL eod flag */
uint64_t ini : 1; /**< ICTL init flag */
@@ -881,20 +933,23 @@ union cvmx_rad_reg_debug9
struct cvmx_rad_reg_debug9_s cn52xxp1;
struct cvmx_rad_reg_debug9_s cn56xx;
struct cvmx_rad_reg_debug9_s cn56xxp1;
+ struct cvmx_rad_reg_debug9_s cn61xx;
struct cvmx_rad_reg_debug9_s cn63xx;
struct cvmx_rad_reg_debug9_s cn63xxp1;
+ struct cvmx_rad_reg_debug9_s cn66xx;
+ struct cvmx_rad_reg_debug9_s cn68xx;
+ struct cvmx_rad_reg_debug9_s cn68xxp1;
+ struct cvmx_rad_reg_debug9_s cnf71xx;
};
typedef union cvmx_rad_reg_debug9 cvmx_rad_reg_debug9_t;
/**
* cvmx_rad_reg_error
*/
-union cvmx_rad_reg_error
-{
+union cvmx_rad_reg_error {
uint64_t u64;
- struct cvmx_rad_reg_error_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_error_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t doorbell : 1; /**< A doorbell count has overflowed */
#else
@@ -906,8 +961,13 @@ union cvmx_rad_reg_error
struct cvmx_rad_reg_error_s cn52xxp1;
struct cvmx_rad_reg_error_s cn56xx;
struct cvmx_rad_reg_error_s cn56xxp1;
+ struct cvmx_rad_reg_error_s cn61xx;
struct cvmx_rad_reg_error_s cn63xx;
struct cvmx_rad_reg_error_s cn63xxp1;
+ struct cvmx_rad_reg_error_s cn66xx;
+ struct cvmx_rad_reg_error_s cn68xx;
+ struct cvmx_rad_reg_error_s cn68xxp1;
+ struct cvmx_rad_reg_error_s cnf71xx;
};
typedef union cvmx_rad_reg_error cvmx_rad_reg_error_t;
@@ -918,12 +978,10 @@ typedef union cvmx_rad_reg_error cvmx_rad_reg_error_t;
* When a mask bit is set, the corresponding interrupt is enabled.
*
*/
-union cvmx_rad_reg_int_mask
-{
+union cvmx_rad_reg_int_mask {
uint64_t u64;
- struct cvmx_rad_reg_int_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_int_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t doorbell : 1; /**< Bit mask corresponding to RAD_REG_ERROR[0] above */
#else
@@ -935,8 +993,13 @@ union cvmx_rad_reg_int_mask
struct cvmx_rad_reg_int_mask_s cn52xxp1;
struct cvmx_rad_reg_int_mask_s cn56xx;
struct cvmx_rad_reg_int_mask_s cn56xxp1;
+ struct cvmx_rad_reg_int_mask_s cn61xx;
struct cvmx_rad_reg_int_mask_s cn63xx;
struct cvmx_rad_reg_int_mask_s cn63xxp1;
+ struct cvmx_rad_reg_int_mask_s cn66xx;
+ struct cvmx_rad_reg_int_mask_s cn68xx;
+ struct cvmx_rad_reg_int_mask_s cn68xxp1;
+ struct cvmx_rad_reg_int_mask_s cnf71xx;
};
typedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t;
@@ -947,12 +1010,10 @@ typedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t;
* The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0.
*
*/
-union cvmx_rad_reg_polynomial
-{
+union cvmx_rad_reg_polynomial {
uint64_t u64;
- struct cvmx_rad_reg_polynomial_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_polynomial_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t coeffs : 8; /**< coefficients of GF(2^8) irreducible polynomial */
#else
@@ -964,8 +1025,13 @@ union cvmx_rad_reg_polynomial
struct cvmx_rad_reg_polynomial_s cn52xxp1;
struct cvmx_rad_reg_polynomial_s cn56xx;
struct cvmx_rad_reg_polynomial_s cn56xxp1;
+ struct cvmx_rad_reg_polynomial_s cn61xx;
struct cvmx_rad_reg_polynomial_s cn63xx;
struct cvmx_rad_reg_polynomial_s cn63xxp1;
+ struct cvmx_rad_reg_polynomial_s cn66xx;
+ struct cvmx_rad_reg_polynomial_s cn68xx;
+ struct cvmx_rad_reg_polynomial_s cn68xxp1;
+ struct cvmx_rad_reg_polynomial_s cnf71xx;
};
typedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t;
@@ -979,12 +1045,10 @@ typedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t;
* The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire
* contents of a CSR memory can be read with consecutive CSR read commands.
*/
-union cvmx_rad_reg_read_idx
-{
+union cvmx_rad_reg_read_idx {
uint64_t u64;
- struct cvmx_rad_reg_read_idx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_rad_reg_read_idx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t inc : 16; /**< Increment to add to current index for next index */
uint64_t index : 16; /**< Index to use for next memory CSR read */
@@ -998,8 +1062,13 @@ union cvmx_rad_reg_read_idx
struct cvmx_rad_reg_read_idx_s cn52xxp1;
struct cvmx_rad_reg_read_idx_s cn56xx;
struct cvmx_rad_reg_read_idx_s cn56xxp1;
+ struct cvmx_rad_reg_read_idx_s cn61xx;
struct cvmx_rad_reg_read_idx_s cn63xx;
struct cvmx_rad_reg_read_idx_s cn63xxp1;
+ struct cvmx_rad_reg_read_idx_s cn66xx;
+ struct cvmx_rad_reg_read_idx_s cn68xx;
+ struct cvmx_rad_reg_read_idx_s cn68xxp1;
+ struct cvmx_rad_reg_read_idx_s cnf71xx;
};
typedef union cvmx_rad_reg_read_idx cvmx_rad_reg_read_idx_t;