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-rw-r--r--cvmx-pemx-defs.h504
1 files changed, 375 insertions, 129 deletions
diff --git a/cvmx-pemx-defs.h b/cvmx-pemx-defs.h
index bb0269a277ea..fb5c4e640a53 100644
--- a/cvmx-pemx-defs.h
+++ b/cvmx-pemx-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,18 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_PEMX_TYPEDEFS_H__
-#define __CVMX_PEMX_TYPEDEFS_H__
+#ifndef __CVMX_PEMX_DEFS_H__
+#define __CVMX_PEMX_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1))))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 15)) && ((block_id <= 1))))))
cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
}
@@ -64,10 +68,28 @@ static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long
#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_BAR2_MASK(unsigned long block_id)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_PEMX_BAR2_MASK(%lu) is invalid on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -78,7 +100,11 @@ static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id)
static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -89,7 +115,11 @@ static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id)
static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -100,7 +130,11 @@ static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id)
static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -111,7 +145,11 @@ static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id)
static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -122,7 +160,11 @@ static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id)
static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -133,7 +175,11 @@ static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id)
static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -144,7 +190,11 @@ static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id)
static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -155,7 +205,11 @@ static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id)
static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -166,7 +220,11 @@ static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id)
static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -174,10 +232,28 @@ static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id)
#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_PEMX_INB_READ_CREDITS(unsigned long block_id)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
+ cvmx_warn("CVMX_PEMX_INB_READ_CREDITS(%lu) is invalid on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull;
+}
+#else
+#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_INT_ENB(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -188,7 +264,11 @@ static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id)
static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_INT_ENB_INT(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -199,7 +279,11 @@ static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id)
static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_INT_SUM(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -210,7 +294,11 @@ static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id)
static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -221,7 +309,11 @@ static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id)
static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -232,7 +324,11 @@ static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id)
static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -243,7 +339,9 @@ static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id)
static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1))))))
cvmx_warn("CVMX_PEMX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
}
@@ -254,7 +352,9 @@ static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned lon
static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1))))))
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1))))))
cvmx_warn("CVMX_PEMX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
}
@@ -265,7 +365,11 @@ static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned l
static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PEMX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
return CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull;
}
@@ -280,12 +384,10 @@ static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id)
*
* Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
*/
-union cvmx_pemx_bar1_indexx
-{
+union cvmx_pemx_bar1_indexx {
uint64_t u64;
- struct cvmx_pemx_bar1_indexx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_bar1_indexx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t addr_idx : 16; /**< Address bits [37:22] sent to L2C */
uint64_t ca : 1; /**< Set '1' when access is not to be cached in L2. */
@@ -299,24 +401,56 @@ union cvmx_pemx_bar1_indexx
uint64_t reserved_20_63 : 44;
#endif
} s;
+ struct cvmx_pemx_bar1_indexx_s cn61xx;
struct cvmx_pemx_bar1_indexx_s cn63xx;
struct cvmx_pemx_bar1_indexx_s cn63xxp1;
+ struct cvmx_pemx_bar1_indexx_s cn66xx;
+ struct cvmx_pemx_bar1_indexx_s cn68xx;
+ struct cvmx_pemx_bar1_indexx_s cn68xxp1;
+ struct cvmx_pemx_bar1_indexx_s cnf71xx;
};
typedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t;
/**
+ * cvmx_pem#_bar2_mask
+ *
+ * PEM_BAR2_MASK = PEM BAR2 MASK
+ *
+ * The mask pattern that is ANDED with the address from PCIe core for BAR2 hits.
+ */
+union cvmx_pemx_bar2_mask {
+ uint64_t u64;
+ struct cvmx_pemx_bar2_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_38_63 : 26;
+ uint64_t mask : 35; /**< The value to be ANDED with the address sent to
+ the Octeon memory. */
+ uint64_t reserved_0_2 : 3;
+#else
+ uint64_t reserved_0_2 : 3;
+ uint64_t mask : 35;
+ uint64_t reserved_38_63 : 26;
+#endif
+ } s;
+ struct cvmx_pemx_bar2_mask_s cn61xx;
+ struct cvmx_pemx_bar2_mask_s cn66xx;
+ struct cvmx_pemx_bar2_mask_s cn68xx;
+ struct cvmx_pemx_bar2_mask_s cn68xxp1;
+ struct cvmx_pemx_bar2_mask_s cnf71xx;
+};
+typedef union cvmx_pemx_bar2_mask cvmx_pemx_bar2_mask_t;
+
+/**
* cvmx_pem#_bar_ctl
*
- * PEM_BAR_CTUS = PEM BAR Control
+ * PEM_BAR_CTL = PEM BAR Control
*
* Contains control for BAR accesses.
*/
-union cvmx_pemx_bar_ctl
-{
+union cvmx_pemx_bar_ctl {
uint64_t u64;
- struct cvmx_pemx_bar_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_bar_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63 : 57;
uint64_t bar1_siz : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
@@ -336,8 +470,13 @@ union cvmx_pemx_bar_ctl
uint64_t reserved_7_63 : 57;
#endif
} s;
+ struct cvmx_pemx_bar_ctl_s cn61xx;
struct cvmx_pemx_bar_ctl_s cn63xx;
struct cvmx_pemx_bar_ctl_s cn63xxp1;
+ struct cvmx_pemx_bar_ctl_s cn66xx;
+ struct cvmx_pemx_bar_ctl_s cn68xx;
+ struct cvmx_pemx_bar_ctl_s cn68xxp1;
+ struct cvmx_pemx_bar_ctl_s cnf71xx;
};
typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;
@@ -348,12 +487,10 @@ typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;
*
* Contains the diffrent interrupt summary bits of the PEM.
*/
-union cvmx_pemx_bist_status
-{
+union cvmx_pemx_bist_status {
uint64_t u64;
- struct cvmx_pemx_bist_status_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t retry : 1; /**< Retry Buffer. */
uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */
@@ -375,8 +512,13 @@ union cvmx_pemx_bist_status
uint64_t reserved_8_63 : 56;
#endif
} s;
+ struct cvmx_pemx_bist_status_s cn61xx;
struct cvmx_pemx_bist_status_s cn63xx;
struct cvmx_pemx_bist_status_s cn63xxp1;
+ struct cvmx_pemx_bist_status_s cn66xx;
+ struct cvmx_pemx_bist_status_s cn68xx;
+ struct cvmx_pemx_bist_status_s cn68xxp1;
+ struct cvmx_pemx_bist_status_s cnf71xx;
};
typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;
@@ -387,12 +529,10 @@ typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;
*
* Results from BIST runs of PEM's memories.
*/
-union cvmx_pemx_bist_status2
-{
+union cvmx_pemx_bist_status2 {
uint64_t u64;
- struct cvmx_pemx_bist_status2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_bist_status2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */
uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */
@@ -418,8 +558,13 @@ union cvmx_pemx_bist_status2
uint64_t reserved_10_63 : 54;
#endif
} s;
+ struct cvmx_pemx_bist_status2_s cn61xx;
struct cvmx_pemx_bist_status2_s cn63xx;
struct cvmx_pemx_bist_status2_s cn63xxp1;
+ struct cvmx_pemx_bist_status2_s cn66xx;
+ struct cvmx_pemx_bist_status2_s cn68xx;
+ struct cvmx_pemx_bist_status2_s cn68xxp1;
+ struct cvmx_pemx_bist_status2_s cnf71xx;
};
typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;
@@ -430,12 +575,10 @@ typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;
*
* Allows read access to the configuration in the PCIe Core.
*/
-union cvmx_pemx_cfg_rd
-{
+union cvmx_pemx_cfg_rd {
uint64_t u64;
- struct cvmx_pemx_cfg_rd_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_cfg_rd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t data : 32; /**< Data. */
uint64_t addr : 32; /**< Address to read. A write to this register
starts a read operation. */
@@ -444,8 +587,13 @@ union cvmx_pemx_cfg_rd
uint64_t data : 32;
#endif
} s;
+ struct cvmx_pemx_cfg_rd_s cn61xx;
struct cvmx_pemx_cfg_rd_s cn63xx;
struct cvmx_pemx_cfg_rd_s cn63xxp1;
+ struct cvmx_pemx_cfg_rd_s cn66xx;
+ struct cvmx_pemx_cfg_rd_s cn68xx;
+ struct cvmx_pemx_cfg_rd_s cn68xxp1;
+ struct cvmx_pemx_cfg_rd_s cnf71xx;
};
typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;
@@ -456,12 +604,10 @@ typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;
*
* Allows write access to the configuration in the PCIe Core.
*/
-union cvmx_pemx_cfg_wr
-{
+union cvmx_pemx_cfg_wr {
uint64_t u64;
- struct cvmx_pemx_cfg_wr_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_cfg_wr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t data : 32; /**< Data to write. A write to this register starts
a write operation. */
uint64_t addr : 32; /**< Address to write. A write to this register starts
@@ -471,8 +617,13 @@ union cvmx_pemx_cfg_wr
uint64_t data : 32;
#endif
} s;
+ struct cvmx_pemx_cfg_wr_s cn61xx;
struct cvmx_pemx_cfg_wr_s cn63xx;
struct cvmx_pemx_cfg_wr_s cn63xxp1;
+ struct cvmx_pemx_cfg_wr_s cn66xx;
+ struct cvmx_pemx_cfg_wr_s cn68xx;
+ struct cvmx_pemx_cfg_wr_s cn68xxp1;
+ struct cvmx_pemx_cfg_wr_s cnf71xx;
};
typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;
@@ -483,12 +634,10 @@ typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;
*
* Bit set for outstanding tag read.
*/
-union cvmx_pemx_cpl_lut_valid
-{
+union cvmx_pemx_cpl_lut_valid {
uint64_t u64;
- struct cvmx_pemx_cpl_lut_valid_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_cpl_lut_valid_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag
expecting a completion. */
@@ -497,24 +646,33 @@ union cvmx_pemx_cpl_lut_valid
uint64_t reserved_32_63 : 32;
#endif
} s;
+ struct cvmx_pemx_cpl_lut_valid_s cn61xx;
struct cvmx_pemx_cpl_lut_valid_s cn63xx;
struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
+ struct cvmx_pemx_cpl_lut_valid_s cn66xx;
+ struct cvmx_pemx_cpl_lut_valid_s cn68xx;
+ struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
+ struct cvmx_pemx_cpl_lut_valid_s cnf71xx;
};
typedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t;
/**
* cvmx_pem#_ctl_status
*
- * PEM_CTL_STATUS = PEM Control Status
+ * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1
+ * For normal operation(sgmii or 1000Base-X), this bit must be 0.
+ * See pcsx.csr for xaui logic analyzer mode.
+ * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
+ *
+ *
+ * PEM_CTL_STATUS = PEM Control Status
*
- * General control and status of the PEM.
+ * General control and status of the PEM.
*/
-union cvmx_pemx_ctl_status
-{
+union cvmx_pemx_ctl_status {
uint64_t u64;
- struct cvmx_pemx_ctl_status_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t auto_sd : 1; /**< Link Hardware Autonomous Speed Disable. */
uint64_t dnum : 5; /**< Primary bus device number. */
@@ -569,8 +727,13 @@ union cvmx_pemx_ctl_status
uint64_t reserved_48_63 : 16;
#endif
} s;
+ struct cvmx_pemx_ctl_status_s cn61xx;
struct cvmx_pemx_ctl_status_s cn63xx;
struct cvmx_pemx_ctl_status_s cn63xxp1;
+ struct cvmx_pemx_ctl_status_s cn66xx;
+ struct cvmx_pemx_ctl_status_s cn68xx;
+ struct cvmx_pemx_ctl_status_s cn68xxp1;
+ struct cvmx_pemx_ctl_status_s cnf71xx;
};
typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;
@@ -581,12 +744,10 @@ typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;
*
* General debug info.
*/
-union cvmx_pemx_dbg_info
-{
+union cvmx_pemx_dbg_info {
uint64_t u64;
- struct cvmx_pemx_dbg_info_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_dbg_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63 : 33;
uint64_t ecrc_e : 1; /**< Received a ECRC error.
radm_ecrc_err */
@@ -698,8 +859,13 @@ union cvmx_pemx_dbg_info
uint64_t reserved_31_63 : 33;
#endif
} s;
+ struct cvmx_pemx_dbg_info_s cn61xx;
struct cvmx_pemx_dbg_info_s cn63xx;
struct cvmx_pemx_dbg_info_s cn63xxp1;
+ struct cvmx_pemx_dbg_info_s cn66xx;
+ struct cvmx_pemx_dbg_info_s cn68xx;
+ struct cvmx_pemx_dbg_info_s cn68xxp1;
+ struct cvmx_pemx_dbg_info_s cnf71xx;
};
typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;
@@ -710,12 +876,10 @@ typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;
*
* Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set.
*/
-union cvmx_pemx_dbg_info_en
-{
+union cvmx_pemx_dbg_info_en {
uint64_t u64;
- struct cvmx_pemx_dbg_info_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_dbg_info_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63 : 33;
uint64_t ecrc_e : 1; /**< Allows PEM_DBG_INFO[30] to generate an interrupt. */
uint64_t rawwpp : 1; /**< Allows PEM_DBG_INFO[29] to generate an interrupt. */
@@ -783,8 +947,13 @@ union cvmx_pemx_dbg_info_en
uint64_t reserved_31_63 : 33;
#endif
} s;
+ struct cvmx_pemx_dbg_info_en_s cn61xx;
struct cvmx_pemx_dbg_info_en_s cn63xx;
struct cvmx_pemx_dbg_info_en_s cn63xxp1;
+ struct cvmx_pemx_dbg_info_en_s cn66xx;
+ struct cvmx_pemx_dbg_info_en_s cn68xx;
+ struct cvmx_pemx_dbg_info_en_s cn68xxp1;
+ struct cvmx_pemx_dbg_info_en_s cnf71xx;
};
typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;
@@ -795,12 +964,10 @@ typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;
*
* Selection control for the cores diagnostic bus.
*/
-union cvmx_pemx_diag_status
-{
+union cvmx_pemx_diag_status {
uint64_t u64;
- struct cvmx_pemx_diag_status_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_diag_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t pm_dst : 1; /**< Current power management DSTATE. */
uint64_t pm_stat : 1; /**< Power Management Status. */
@@ -814,24 +981,54 @@ union cvmx_pemx_diag_status
uint64_t reserved_4_63 : 60;
#endif
} s;
+ struct cvmx_pemx_diag_status_s cn61xx;
struct cvmx_pemx_diag_status_s cn63xx;
struct cvmx_pemx_diag_status_s cn63xxp1;
+ struct cvmx_pemx_diag_status_s cn66xx;
+ struct cvmx_pemx_diag_status_s cn68xx;
+ struct cvmx_pemx_diag_status_s cn68xxp1;
+ struct cvmx_pemx_diag_status_s cnf71xx;
};
typedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t;
/**
+ * cvmx_pem#_inb_read_credits
+ *
+ * PEM_INB_READ_CREDITS
+ *
+ * The number of in flight reads from PCIe core to SLI
+ */
+union cvmx_pemx_inb_read_credits {
+ uint64_t u64;
+ struct cvmx_pemx_inb_read_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_6_63 : 58;
+ uint64_t num : 6; /**< The number of reads that may be in flight from
+ the PCIe core to the SLI. Min number is 2 max
+ number is 32. */
+#else
+ uint64_t num : 6;
+ uint64_t reserved_6_63 : 58;
+#endif
+ } s;
+ struct cvmx_pemx_inb_read_credits_s cn61xx;
+ struct cvmx_pemx_inb_read_credits_s cn66xx;
+ struct cvmx_pemx_inb_read_credits_s cn68xx;
+ struct cvmx_pemx_inb_read_credits_s cnf71xx;
+};
+typedef union cvmx_pemx_inb_read_credits cvmx_pemx_inb_read_credits_t;
+
+/**
* cvmx_pem#_int_enb
*
* PEM(0..1)_INT_ENB = PEM Interrupt Enable
*
* Enables interrupt conditions for the PEM to generate an RSL interrupt.
*/
-union cvmx_pemx_int_enb
-{
+union cvmx_pemx_int_enb {
uint64_t u64;
- struct cvmx_pemx_int_enb_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63 : 50;
uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an
interrupt to the MIO. */
@@ -879,8 +1076,13 @@ union cvmx_pemx_int_enb
uint64_t reserved_14_63 : 50;
#endif
} s;
+ struct cvmx_pemx_int_enb_s cn61xx;
struct cvmx_pemx_int_enb_s cn63xx;
struct cvmx_pemx_int_enb_s cn63xxp1;
+ struct cvmx_pemx_int_enb_s cn66xx;
+ struct cvmx_pemx_int_enb_s cn68xx;
+ struct cvmx_pemx_int_enb_s cn68xxp1;
+ struct cvmx_pemx_int_enb_s cnf71xx;
};
typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;
@@ -891,12 +1093,10 @@ typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;
*
* Enables interrupt conditions for the PEM to generate an RSL interrupt.
*/
-union cvmx_pemx_int_enb_int
-{
+union cvmx_pemx_int_enb_int {
uint64_t u64;
- struct cvmx_pemx_int_enb_int_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_int_enb_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63 : 50;
uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an
interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
@@ -944,8 +1144,13 @@ union cvmx_pemx_int_enb_int
uint64_t reserved_14_63 : 50;
#endif
} s;
+ struct cvmx_pemx_int_enb_int_s cn61xx;
struct cvmx_pemx_int_enb_int_s cn63xx;
struct cvmx_pemx_int_enb_int_s cn63xxp1;
+ struct cvmx_pemx_int_enb_int_s cn66xx;
+ struct cvmx_pemx_int_enb_int_s cn68xx;
+ struct cvmx_pemx_int_enb_int_s cn68xxp1;
+ struct cvmx_pemx_int_enb_int_s cnf71xx;
};
typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;
@@ -958,12 +1163,10 @@ typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;
*
* Interrupt conditions for the PEM.
*/
-union cvmx_pemx_int_sum
-{
+union cvmx_pemx_int_sum {
uint64_t u64;
- struct cvmx_pemx_int_sum_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63 : 50;
uint64_t crs_dr : 1; /**< Had a CRS Timeout when Retries were disabled. */
uint64_t crs_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
@@ -1005,8 +1208,13 @@ union cvmx_pemx_int_sum
uint64_t reserved_14_63 : 50;
#endif
} s;
+ struct cvmx_pemx_int_sum_s cn61xx;
struct cvmx_pemx_int_sum_s cn63xx;
struct cvmx_pemx_int_sum_s cn63xxp1;
+ struct cvmx_pemx_int_sum_s cn66xx;
+ struct cvmx_pemx_int_sum_s cn68xx;
+ struct cvmx_pemx_int_sum_s cn68xxp1;
+ struct cvmx_pemx_int_sum_s cnf71xx;
};
typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;
@@ -1017,12 +1225,10 @@ typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;
*
* The starting address for addresses to forwarded to the SLI in RC Mode.
*/
-union cvmx_pemx_p2n_bar0_start
-{
+union cvmx_pemx_p2n_bar0_start {
uint64_t u64;
- struct cvmx_pemx_p2n_bar0_start_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_p2n_bar0_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr : 50; /**< The starting address of the 16KB address space that
is the BAR0 address space. */
uint64_t reserved_0_13 : 14;
@@ -1031,8 +1237,13 @@ union cvmx_pemx_p2n_bar0_start
uint64_t addr : 50;
#endif
} s;
+ struct cvmx_pemx_p2n_bar0_start_s cn61xx;
struct cvmx_pemx_p2n_bar0_start_s cn63xx;
struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
+ struct cvmx_pemx_p2n_bar0_start_s cn66xx;
+ struct cvmx_pemx_p2n_bar0_start_s cn68xx;
+ struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
+ struct cvmx_pemx_p2n_bar0_start_s cnf71xx;
};
typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;
@@ -1043,12 +1254,10 @@ typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;
*
* The starting address for addresses to forwarded to the SLI in RC Mode.
*/
-union cvmx_pemx_p2n_bar1_start
-{
+union cvmx_pemx_p2n_bar1_start {
uint64_t u64;
- struct cvmx_pemx_p2n_bar1_start_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_p2n_bar1_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr : 38; /**< The starting address of the 64KB address space
that is the BAR1 address space. */
uint64_t reserved_0_25 : 26;
@@ -1057,8 +1266,13 @@ union cvmx_pemx_p2n_bar1_start
uint64_t addr : 38;
#endif
} s;
+ struct cvmx_pemx_p2n_bar1_start_s cn61xx;
struct cvmx_pemx_p2n_bar1_start_s cn63xx;
struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
+ struct cvmx_pemx_p2n_bar1_start_s cn66xx;
+ struct cvmx_pemx_p2n_bar1_start_s cn68xx;
+ struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
+ struct cvmx_pemx_p2n_bar1_start_s cnf71xx;
};
typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;
@@ -1069,12 +1283,10 @@ typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;
*
* The starting address for addresses to forwarded to the SLI in RC Mode.
*/
-union cvmx_pemx_p2n_bar2_start
-{
+union cvmx_pemx_p2n_bar2_start {
uint64_t u64;
- struct cvmx_pemx_p2n_bar2_start_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_p2n_bar2_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr : 23; /**< The starting address of the 2^41 address space
that is the BAR2 address space. */
uint64_t reserved_0_40 : 41;
@@ -1083,8 +1295,13 @@ union cvmx_pemx_p2n_bar2_start
uint64_t addr : 23;
#endif
} s;
+ struct cvmx_pemx_p2n_bar2_start_s cn61xx;
struct cvmx_pemx_p2n_bar2_start_s cn63xx;
struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
+ struct cvmx_pemx_p2n_bar2_start_s cn66xx;
+ struct cvmx_pemx_p2n_bar2_start_s cn68xx;
+ struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
+ struct cvmx_pemx_p2n_bar2_start_s cnf71xx;
};
typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;
@@ -1095,12 +1312,10 @@ typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;
*
* The ending address for addresses to forwarded to the PCIe peer port.
*/
-union cvmx_pemx_p2p_barx_end
-{
+union cvmx_pemx_p2p_barx_end {
uint64_t u64;
- struct cvmx_pemx_p2p_barx_end_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_p2p_barx_end_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr : 52; /**< The ending address of the address window created
this field and the PEM_P2P_BAR0_START[63:12]
field. The full 64-bits of address are created by:
@@ -1113,6 +1328,9 @@ union cvmx_pemx_p2p_barx_end
} s;
struct cvmx_pemx_p2p_barx_end_s cn63xx;
struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
+ struct cvmx_pemx_p2p_barx_end_s cn66xx;
+ struct cvmx_pemx_p2p_barx_end_s cn68xx;
+ struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
};
typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;
@@ -1123,12 +1341,10 @@ typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;
*
* The starting address and enable for addresses to forwarded to the PCIe peer port.
*/
-union cvmx_pemx_p2p_barx_start
-{
+union cvmx_pemx_p2p_barx_start {
uint64_t u64;
- struct cvmx_pemx_p2p_barx_start_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_p2p_barx_start_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t addr : 52; /**< The starting address of the address window created
by this field and the PEM_P2P_BAR0_END[63:12]
field. The full 64-bits of address are created by:
@@ -1141,6 +1357,9 @@ union cvmx_pemx_p2p_barx_start
} s;
struct cvmx_pemx_p2p_barx_start_s cn63xx;
struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
+ struct cvmx_pemx_p2p_barx_start_s cn66xx;
+ struct cvmx_pemx_p2p_barx_start_s cn68xx;
+ struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
};
typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;
@@ -1152,15 +1371,15 @@ typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;
* Specifies the number of credits the PEM for use in moving TLPs. When this register is written the credit values are
* reset to the register value. A write to this register should take place BEFORE traffic flow starts.
*/
-union cvmx_pemx_tlp_credits
-{
+union cvmx_pemx_tlp_credits {
uint64_t u64;
- struct cvmx_pemx_tlp_credits_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pemx_tlp_credits_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63 : 8;
uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer.
- Legal values are 0x24 to 0x80. */
+ The value in this register should not be changed.
+ Values other than 0x80 can lead to unpredictable
+ behavior */
uint64_t pem_cpl : 8; /**< TLP credits for Completion TLPs in the Peer.
Legal values are 0x24 to 0x80. */
uint64_t pem_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer.
@@ -1184,8 +1403,35 @@ union cvmx_pemx_tlp_credits
uint64_t reserved_56_63 : 8;
#endif
} s;
+ struct cvmx_pemx_tlp_credits_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_56_63 : 8;
+ uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer.
+ The value in this register should not be changed.
+ Values other than 0x80 can lead to unpredictable
+ behavior */
+ uint64_t reserved_24_47 : 24;
+ uint64_t sli_cpl : 8; /**< TLP credits for Completion TLPs in the SLI.
+ Legal values are 0x24 to 0x80. */
+ uint64_t sli_np : 8; /**< TLP credits for Non-Posted TLPs in the SLI.
+ Legal values are 0x4 to 0x10. */
+ uint64_t sli_p : 8; /**< TLP credits for Posted TLPs in the SLI.
+ Legal values are 0x24 to 0x80. */
+#else
+ uint64_t sli_p : 8;
+ uint64_t sli_np : 8;
+ uint64_t sli_cpl : 8;
+ uint64_t reserved_24_47 : 24;
+ uint64_t peai_ppf : 8;
+ uint64_t reserved_56_63 : 8;
+#endif
+ } cn61xx;
struct cvmx_pemx_tlp_credits_s cn63xx;
struct cvmx_pemx_tlp_credits_s cn63xxp1;
+ struct cvmx_pemx_tlp_credits_s cn66xx;
+ struct cvmx_pemx_tlp_credits_s cn68xx;
+ struct cvmx_pemx_tlp_credits_s cn68xxp1;
+ struct cvmx_pemx_tlp_credits_cn61xx cnf71xx;
};
typedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t;
generated by cgit v1.2.3 (git 2.25.1) at 2022-05-18 17:37:30 +0000