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-rw-r--r--cvmx-pcmx-defs.h494
1 files changed, 274 insertions, 220 deletions
diff --git a/cvmx-pcmx-defs.h b/cvmx-pcmx-defs.h
index 6e2495bcabc4..8d42db8148cb 100644
--- a/cvmx-pcmx-defs.h
+++ b/cvmx-pcmx-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_PCMX_TYPEDEFS_H__
-#define __CVMX_PCMX_TYPEDEFS_H__
+#ifndef __CVMX_PCMX_DEFS_H__
+#define __CVMX_PCMX_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
@@ -58,7 +58,9 @@ static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384;
}
@@ -71,7 +73,9 @@ static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384;
}
@@ -84,7 +88,9 @@ static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384;
}
@@ -97,7 +103,9 @@ static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384;
}
@@ -110,7 +118,9 @@ static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384;
}
@@ -123,7 +133,9 @@ static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384;
}
@@ -136,7 +148,9 @@ static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384;
}
@@ -149,7 +163,9 @@ static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384;
}
@@ -162,7 +178,9 @@ static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384;
}
@@ -175,7 +193,9 @@ static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384;
}
@@ -188,7 +208,9 @@ static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384;
}
@@ -201,7 +223,9 @@ static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384;
}
@@ -214,7 +238,9 @@ static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384;
}
@@ -227,7 +253,9 @@ static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384;
}
@@ -240,7 +268,9 @@ static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384;
}
@@ -253,7 +283,9 @@ static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384;
}
@@ -266,7 +298,9 @@ static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384;
}
@@ -279,7 +313,9 @@ static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384;
}
@@ -292,7 +328,9 @@ static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384;
}
@@ -305,7 +343,9 @@ static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384;
}
@@ -318,7 +358,9 @@ static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384;
}
@@ -331,7 +373,9 @@ static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384;
}
@@ -344,7 +388,9 @@ static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384;
}
@@ -357,7 +403,9 @@ static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384;
}
@@ -370,7 +418,9 @@ static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384;
}
@@ -383,7 +433,9 @@ static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384;
}
@@ -396,7 +448,9 @@ static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384;
}
@@ -407,32 +461,30 @@ static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
/**
* cvmx_pcm#_dma_cfg
*/
-union cvmx_pcmx_dma_cfg
-{
+union cvmx_pcmx_dma_cfg {
uint64_t u64;
- struct cvmx_pcmx_dma_cfg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t rdpend : 1; /**< If 0, no L2C read responses pending
+ struct cvmx_pcmx_dma_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rdpend : 1; /**< If 0, no L2C read responses pending | NS
1, L2C read responses are outstanding
NOTE: When restarting after stopping a running TDM
engine, software must wait for RDPEND to read 0
before writing PCMn_TDM_CFG[ENABLE] to a 1 */
uint64_t reserved_54_62 : 9;
- uint64_t rxslots : 10; /**< Number of 8-bit slots to receive per frame
+ uint64_t rxslots : 10; /**< Number of 8-bit slots to receive per frame | NS
(number of slots in a receive superframe) */
uint64_t reserved_42_43 : 2;
- uint64_t txslots : 10; /**< Number of 8-bit slots to transmit per frame
+ uint64_t txslots : 10; /**< Number of 8-bit slots to transmit per frame | NS
(number of slots in a transmit superframe) */
uint64_t reserved_30_31 : 2;
- uint64_t rxst : 10; /**< Number of frame writes for interrupt */
+ uint64_t rxst : 10; /**< Number of frame writes for interrupt | NS */
uint64_t reserved_19_19 : 1;
- uint64_t useldt : 1; /**< If 0, use LDI command to read from L2C
+ uint64_t useldt : 1; /**< If 0, use LDI command to read from L2C | NS
1, use LDT command to read from L2C */
- uint64_t txrd : 10; /**< Number of frame reads for interrupt */
- uint64_t fetchsiz : 4; /**< FETCHSIZ+1 timeslots are read when threshold is
+ uint64_t txrd : 10; /**< Number of frame reads for interrupt | NS */
+ uint64_t fetchsiz : 4; /**< FETCHSIZ+1 timeslots are read when threshold is | NS
reached. */
- uint64_t thresh : 4; /**< If number of bytes remaining in the DMA fifo is <=
+ uint64_t thresh : 4; /**< If number of bytes remaining in the DMA fifo is <=| NS
THRESH, initiate a fetch of timeslot data from the
transmit memory region.
NOTE: there are only 16B of buffer for each engine
@@ -458,31 +510,31 @@ union cvmx_pcmx_dma_cfg
struct cvmx_pcmx_dma_cfg_s cn30xx;
struct cvmx_pcmx_dma_cfg_s cn31xx;
struct cvmx_pcmx_dma_cfg_s cn50xx;
+ struct cvmx_pcmx_dma_cfg_s cn61xx;
+ struct cvmx_pcmx_dma_cfg_s cnf71xx;
};
typedef union cvmx_pcmx_dma_cfg cvmx_pcmx_dma_cfg_t;
/**
* cvmx_pcm#_int_ena
*/
-union cvmx_pcmx_int_ena
-{
+union cvmx_pcmx_int_ena {
uint64_t u64;
- struct cvmx_pcmx_int_ena_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcmx_int_ena_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
- uint64_t rxovf : 1; /**< Enable interrupt if RX byte overflows */
- uint64_t txempty : 1; /**< Enable interrupt on TX byte empty */
- uint64_t txrd : 1; /**< Enable DMA engine frame read interrupts */
- uint64_t txwrap : 1; /**< Enable TX region wrap interrupts */
- uint64_t rxst : 1; /**< Enable DMA engine frame store interrupts */
- uint64_t rxwrap : 1; /**< Enable RX region wrap interrupts */
- uint64_t fsyncextra : 1; /**< Enable FSYNC extra interrupts
+ uint64_t rxovf : 1; /**< Enable interrupt if RX byte overflows | NS */
+ uint64_t txempty : 1; /**< Enable interrupt on TX byte empty | NS */
+ uint64_t txrd : 1; /**< Enable DMA engine frame read interrupts | NS */
+ uint64_t txwrap : 1; /**< Enable TX region wrap interrupts | NS */
+ uint64_t rxst : 1; /**< Enable DMA engine frame store interrupts | NS */
+ uint64_t rxwrap : 1; /**< Enable RX region wrap interrupts | NS */
+ uint64_t fsyncextra : 1; /**< Enable FSYNC extra interrupts | NS
NOTE: FSYNCEXTRA errors are defined as an FSYNC
found in the "wrong" spot of a frame given the
programming of PCMn_CLK_CFG[NUMSLOTS] and
PCMn_CLK_CFG[EXTRABIT]. */
- uint64_t fsyncmissed : 1; /**< Enable FSYNC missed interrupts
+ uint64_t fsyncmissed : 1; /**< Enable FSYNC missed interrupts | NS
NOTE: FSYNCMISSED errors are defined as an FSYNC
missing from the correct spot in a frame given
the programming of PCMn_CLK_CFG[NUMSLOTS] and
@@ -502,27 +554,27 @@ union cvmx_pcmx_int_ena
struct cvmx_pcmx_int_ena_s cn30xx;
struct cvmx_pcmx_int_ena_s cn31xx;
struct cvmx_pcmx_int_ena_s cn50xx;
+ struct cvmx_pcmx_int_ena_s cn61xx;
+ struct cvmx_pcmx_int_ena_s cnf71xx;
};
typedef union cvmx_pcmx_int_ena cvmx_pcmx_int_ena_t;
/**
* cvmx_pcm#_int_sum
*/
-union cvmx_pcmx_int_sum
-{
+union cvmx_pcmx_int_sum {
uint64_t u64;
- struct cvmx_pcmx_int_sum_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcmx_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
- uint64_t rxovf : 1; /**< RX byte overflowed */
- uint64_t txempty : 1; /**< TX byte was empty when sampled */
- uint64_t txrd : 1; /**< DMA engine frame read interrupt occurred */
- uint64_t txwrap : 1; /**< TX region wrap interrupt occurred */
- uint64_t rxst : 1; /**< DMA engine frame store interrupt occurred */
- uint64_t rxwrap : 1; /**< RX region wrap interrupt occurred */
- uint64_t fsyncextra : 1; /**< FSYNC extra interrupt occurred */
- uint64_t fsyncmissed : 1; /**< FSYNC missed interrupt occurred */
+ uint64_t rxovf : 1; /**< RX byte overflowed | NS */
+ uint64_t txempty : 1; /**< TX byte was empty when sampled | NS */
+ uint64_t txrd : 1; /**< DMA engine frame read interrupt occurred | NS */
+ uint64_t txwrap : 1; /**< TX region wrap interrupt occurred | NS */
+ uint64_t rxst : 1; /**< DMA engine frame store interrupt occurred | NS */
+ uint64_t rxwrap : 1; /**< RX region wrap interrupt occurred | NS */
+ uint64_t fsyncextra : 1; /**< FSYNC extra interrupt occurred | NS */
+ uint64_t fsyncmissed : 1; /**< FSYNC missed interrupt occurred | NS */
#else
uint64_t fsyncmissed : 1;
uint64_t fsyncextra : 1;
@@ -538,20 +590,20 @@ union cvmx_pcmx_int_sum
struct cvmx_pcmx_int_sum_s cn30xx;
struct cvmx_pcmx_int_sum_s cn31xx;
struct cvmx_pcmx_int_sum_s cn50xx;
+ struct cvmx_pcmx_int_sum_s cn61xx;
+ struct cvmx_pcmx_int_sum_s cnf71xx;
};
typedef union cvmx_pcmx_int_sum cvmx_pcmx_int_sum_t;
/**
* cvmx_pcm#_rxaddr
*/
-union cvmx_pcmx_rxaddr
-{
+union cvmx_pcmx_rxaddr {
uint64_t u64;
- struct cvmx_pcmx_rxaddr_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcmx_rxaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63 : 28;
- uint64_t addr : 36; /**< Address of the next write to the receive memory
+ uint64_t addr : 36; /**< Address of the next write to the receive memory | NS
region */
#else
uint64_t addr : 36;
@@ -561,20 +613,20 @@ union cvmx_pcmx_rxaddr
struct cvmx_pcmx_rxaddr_s cn30xx;
struct cvmx_pcmx_rxaddr_s cn31xx;
struct cvmx_pcmx_rxaddr_s cn50xx;
+ struct cvmx_pcmx_rxaddr_s cn61xx;
+ struct cvmx_pcmx_rxaddr_s cnf71xx;
};
typedef union cvmx_pcmx_rxaddr cvmx_pcmx_rxaddr_t;
/**
* cvmx_pcm#_rxcnt
*/
-union cvmx_pcmx_rxcnt
-{
+union cvmx_pcmx_rxcnt {
uint64_t u64;
- struct cvmx_pcmx_rxcnt_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcmx_rxcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
- uint64_t cnt : 16; /**< Number of superframes in receive memory region */
+ uint64_t cnt : 16; /**< Number of superframes in receive memory region | NS */
#else
uint64_t cnt : 16;
uint64_t reserved_16_63 : 48;
@@ -583,19 +635,19 @@ union cvmx_pcmx_rxcnt
struct cvmx_pcmx_rxcnt_s cn30xx;
struct cvmx_pcmx_rxcnt_s cn31xx;
struct cvmx_pcmx_rxcnt_s cn50xx;
+ struct cvmx_pcmx_rxcnt_s cn61xx;
+ struct cvmx_pcmx_rxcnt_s cnf71xx;
};
typedef union cvmx_pcmx_rxcnt cvmx_pcmx_rxcnt_t;
/**
* cvmx_pcm#_rxmsk0
*/
-union cvmx_pcmx_rxmsk0
-{
+union cvmx_pcmx_rxmsk0 {
uint64_t u64;
- struct cvmx_pcmx_rxmsk0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Receive mask bits for slots 63 to 0
+ struct cvmx_pcmx_rxmsk0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Receive mask bits for slots 63 to 0 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -604,19 +656,19 @@ union cvmx_pcmx_rxmsk0
struct cvmx_pcmx_rxmsk0_s cn30xx;
struct cvmx_pcmx_rxmsk0_s cn31xx;
struct cvmx_pcmx_rxmsk0_s cn50xx;
+ struct cvmx_pcmx_rxmsk0_s cn61xx;
+ struct cvmx_pcmx_rxmsk0_s cnf71xx;
};
typedef union cvmx_pcmx_rxmsk0 cvmx_pcmx_rxmsk0_t;
/**
* cvmx_pcm#_rxmsk1
*/
-union cvmx_pcmx_rxmsk1
-{
+union cvmx_pcmx_rxmsk1 {
uint64_t u64;
- struct cvmx_pcmx_rxmsk1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Receive mask bits for slots 127 to 64
+ struct cvmx_pcmx_rxmsk1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Receive mask bits for slots 127 to 64 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -625,19 +677,19 @@ union cvmx_pcmx_rxmsk1
struct cvmx_pcmx_rxmsk1_s cn30xx;
struct cvmx_pcmx_rxmsk1_s cn31xx;
struct cvmx_pcmx_rxmsk1_s cn50xx;
+ struct cvmx_pcmx_rxmsk1_s cn61xx;
+ struct cvmx_pcmx_rxmsk1_s cnf71xx;
};
typedef union cvmx_pcmx_rxmsk1 cvmx_pcmx_rxmsk1_t;
/**
* cvmx_pcm#_rxmsk2
*/
-union cvmx_pcmx_rxmsk2
-{
+union cvmx_pcmx_rxmsk2 {
uint64_t u64;
- struct cvmx_pcmx_rxmsk2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Receive mask bits for slots 191 to 128
+ struct cvmx_pcmx_rxmsk2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Receive mask bits for slots 191 to 128 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -646,19 +698,19 @@ union cvmx_pcmx_rxmsk2
struct cvmx_pcmx_rxmsk2_s cn30xx;
struct cvmx_pcmx_rxmsk2_s cn31xx;
struct cvmx_pcmx_rxmsk2_s cn50xx;
+ struct cvmx_pcmx_rxmsk2_s cn61xx;
+ struct cvmx_pcmx_rxmsk2_s cnf71xx;
};
typedef union cvmx_pcmx_rxmsk2 cvmx_pcmx_rxmsk2_t;
/**
* cvmx_pcm#_rxmsk3
*/
-union cvmx_pcmx_rxmsk3
-{
+union cvmx_pcmx_rxmsk3 {
uint64_t u64;
- struct cvmx_pcmx_rxmsk3_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Receive mask bits for slots 255 to 192
+ struct cvmx_pcmx_rxmsk3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Receive mask bits for slots 255 to 192 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -667,19 +719,19 @@ union cvmx_pcmx_rxmsk3
struct cvmx_pcmx_rxmsk3_s cn30xx;
struct cvmx_pcmx_rxmsk3_s cn31xx;
struct cvmx_pcmx_rxmsk3_s cn50xx;
+ struct cvmx_pcmx_rxmsk3_s cn61xx;
+ struct cvmx_pcmx_rxmsk3_s cnf71xx;
};
typedef union cvmx_pcmx_rxmsk3 cvmx_pcmx_rxmsk3_t;
/**
* cvmx_pcm#_rxmsk4
*/
-union cvmx_pcmx_rxmsk4
-{
+union cvmx_pcmx_rxmsk4 {
uint64_t u64;
- struct cvmx_pcmx_rxmsk4_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Receive mask bits for slots 319 to 256
+ struct cvmx_pcmx_rxmsk4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Receive mask bits for slots 319 to 256 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -688,19 +740,19 @@ union cvmx_pcmx_rxmsk4
struct cvmx_pcmx_rxmsk4_s cn30xx;
struct cvmx_pcmx_rxmsk4_s cn31xx;
struct cvmx_pcmx_rxmsk4_s cn50xx;
+ struct cvmx_pcmx_rxmsk4_s cn61xx;
+ struct cvmx_pcmx_rxmsk4_s cnf71xx;
};
typedef union cvmx_pcmx_rxmsk4 cvmx_pcmx_rxmsk4_t;
/**
* cvmx_pcm#_rxmsk5
*/
-union cvmx_pcmx_rxmsk5
-{
+union cvmx_pcmx_rxmsk5 {
uint64_t u64;
- struct cvmx_pcmx_rxmsk5_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Receive mask bits for slots 383 to 320
+ struct cvmx_pcmx_rxmsk5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Receive mask bits for slots 383 to 320 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -709,19 +761,19 @@ union cvmx_pcmx_rxmsk5
struct cvmx_pcmx_rxmsk5_s cn30xx;
struct cvmx_pcmx_rxmsk5_s cn31xx;
struct cvmx_pcmx_rxmsk5_s cn50xx;
+ struct cvmx_pcmx_rxmsk5_s cn61xx;
+ struct cvmx_pcmx_rxmsk5_s cnf71xx;
};
typedef union cvmx_pcmx_rxmsk5 cvmx_pcmx_rxmsk5_t;
/**
* cvmx_pcm#_rxmsk6
*/
-union cvmx_pcmx_rxmsk6
-{
+union cvmx_pcmx_rxmsk6 {
uint64_t u64;
- struct cvmx_pcmx_rxmsk6_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Receive mask bits for slots 447 to 384
+ struct cvmx_pcmx_rxmsk6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Receive mask bits for slots 447 to 384 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -730,19 +782,19 @@ union cvmx_pcmx_rxmsk6
struct cvmx_pcmx_rxmsk6_s cn30xx;
struct cvmx_pcmx_rxmsk6_s cn31xx;
struct cvmx_pcmx_rxmsk6_s cn50xx;
+ struct cvmx_pcmx_rxmsk6_s cn61xx;
+ struct cvmx_pcmx_rxmsk6_s cnf71xx;
};
typedef union cvmx_pcmx_rxmsk6 cvmx_pcmx_rxmsk6_t;
/**
* cvmx_pcm#_rxmsk7
*/
-union cvmx_pcmx_rxmsk7
-{
+union cvmx_pcmx_rxmsk7 {
uint64_t u64;
- struct cvmx_pcmx_rxmsk7_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Receive mask bits for slots 511 to 448
+ struct cvmx_pcmx_rxmsk7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Receive mask bits for slots 511 to 448 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -751,20 +803,20 @@ union cvmx_pcmx_rxmsk7
struct cvmx_pcmx_rxmsk7_s cn30xx;
struct cvmx_pcmx_rxmsk7_s cn31xx;
struct cvmx_pcmx_rxmsk7_s cn50xx;
+ struct cvmx_pcmx_rxmsk7_s cn61xx;
+ struct cvmx_pcmx_rxmsk7_s cnf71xx;
};
typedef union cvmx_pcmx_rxmsk7 cvmx_pcmx_rxmsk7_t;
/**
* cvmx_pcm#_rxstart
*/
-union cvmx_pcmx_rxstart
-{
+union cvmx_pcmx_rxstart {
uint64_t u64;
- struct cvmx_pcmx_rxstart_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcmx_rxstart_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63 : 28;
- uint64_t addr : 33; /**< Starting address for the receive memory region */
+ uint64_t addr : 33; /**< Starting address for the receive memory region | NS */
uint64_t reserved_0_2 : 3;
#else
uint64_t reserved_0_2 : 3;
@@ -775,29 +827,29 @@ union cvmx_pcmx_rxstart
struct cvmx_pcmx_rxstart_s cn30xx;
struct cvmx_pcmx_rxstart_s cn31xx;
struct cvmx_pcmx_rxstart_s cn50xx;
+ struct cvmx_pcmx_rxstart_s cn61xx;
+ struct cvmx_pcmx_rxstart_s cnf71xx;
};
typedef union cvmx_pcmx_rxstart cvmx_pcmx_rxstart_t;
/**
* cvmx_pcm#_tdm_cfg
*/
-union cvmx_pcmx_tdm_cfg
-{
+union cvmx_pcmx_tdm_cfg {
uint64_t u64;
- struct cvmx_pcmx_tdm_cfg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t drvtim : 16; /**< Number of ECLKs from start of bit time to stop
+ struct cvmx_pcmx_tdm_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t drvtim : 16; /**< Number of ECLKs from start of bit time to stop | NS
driving last bit of timeslot (if not driving next
timeslot) */
- uint64_t samppt : 16; /**< Number of ECLKs from start of bit time to sample
+ uint64_t samppt : 16; /**< Number of ECLKs from start of bit time to sample | NS
data bit. */
uint64_t reserved_3_31 : 29;
- uint64_t lsbfirst : 1; /**< If 0, shift/receive MSB first
+ uint64_t lsbfirst : 1; /**< If 0, shift/receive MSB first | NS
1, shift/receive LSB first */
- uint64_t useclk1 : 1; /**< If 0, this PCM is based on BCLK/FSYNC0
+ uint64_t useclk1 : 1; /**< If 0, this PCM is based on BCLK/FSYNC0 | NS
1, this PCM is based on BCLK/FSYNC1 */
- uint64_t enable : 1; /**< If 1, PCM is enabled, otherwise pins are GPIOs
+ uint64_t enable : 1; /**< If 1, PCM is enabled, otherwise pins are GPIOs | NS
NOTE: when TDM is disabled by detection of an
FSYNC error all transmission and reception is
halted. In addition, PCMn_TX/RXADDR are updated
@@ -815,19 +867,19 @@ union cvmx_pcmx_tdm_cfg
struct cvmx_pcmx_tdm_cfg_s cn30xx;
struct cvmx_pcmx_tdm_cfg_s cn31xx;
struct cvmx_pcmx_tdm_cfg_s cn50xx;
+ struct cvmx_pcmx_tdm_cfg_s cn61xx;
+ struct cvmx_pcmx_tdm_cfg_s cnf71xx;
};
typedef union cvmx_pcmx_tdm_cfg cvmx_pcmx_tdm_cfg_t;
/**
* cvmx_pcm#_tdm_dbg
*/
-union cvmx_pcmx_tdm_dbg
-{
+union cvmx_pcmx_tdm_dbg {
uint64_t u64;
- struct cvmx_pcmx_tdm_dbg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t debuginfo : 64; /**< Miscellaneous debug information */
+ struct cvmx_pcmx_tdm_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t debuginfo : 64; /**< Miscellaneous debug information | NS */
#else
uint64_t debuginfo : 64;
#endif
@@ -835,22 +887,22 @@ union cvmx_pcmx_tdm_dbg
struct cvmx_pcmx_tdm_dbg_s cn30xx;
struct cvmx_pcmx_tdm_dbg_s cn31xx;
struct cvmx_pcmx_tdm_dbg_s cn50xx;
+ struct cvmx_pcmx_tdm_dbg_s cn61xx;
+ struct cvmx_pcmx_tdm_dbg_s cnf71xx;
};
typedef union cvmx_pcmx_tdm_dbg cvmx_pcmx_tdm_dbg_t;
/**
* cvmx_pcm#_txaddr
*/
-union cvmx_pcmx_txaddr
-{
+union cvmx_pcmx_txaddr {
uint64_t u64;
- struct cvmx_pcmx_txaddr_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcmx_txaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63 : 28;
- uint64_t addr : 33; /**< Address of the next read from the transmit memory
+ uint64_t addr : 33; /**< Address of the next read from the transmit memory | NS
region */
- uint64_t fram : 3; /**< Frame offset
+ uint64_t fram : 3; /**< Frame offset | NS
NOTE: this is used to extract the correct byte from
each 64b word read from the transmit memory region */
#else
@@ -862,20 +914,20 @@ union cvmx_pcmx_txaddr
struct cvmx_pcmx_txaddr_s cn30xx;
struct cvmx_pcmx_txaddr_s cn31xx;
struct cvmx_pcmx_txaddr_s cn50xx;
+ struct cvmx_pcmx_txaddr_s cn61xx;
+ struct cvmx_pcmx_txaddr_s cnf71xx;
};
typedef union cvmx_pcmx_txaddr cvmx_pcmx_txaddr_t;
/**
* cvmx_pcm#_txcnt
*/
-union cvmx_pcmx_txcnt
-{
+union cvmx_pcmx_txcnt {
uint64_t u64;
- struct cvmx_pcmx_txcnt_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcmx_txcnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
- uint64_t cnt : 16; /**< Number of superframes in transmit memory region */
+ uint64_t cnt : 16; /**< Number of superframes in transmit memory region | NS */
#else
uint64_t cnt : 16;
uint64_t reserved_16_63 : 48;
@@ -884,19 +936,19 @@ union cvmx_pcmx_txcnt
struct cvmx_pcmx_txcnt_s cn30xx;
struct cvmx_pcmx_txcnt_s cn31xx;
struct cvmx_pcmx_txcnt_s cn50xx;
+ struct cvmx_pcmx_txcnt_s cn61xx;
+ struct cvmx_pcmx_txcnt_s cnf71xx;
};
typedef union cvmx_pcmx_txcnt cvmx_pcmx_txcnt_t;
/**
* cvmx_pcm#_txmsk0
*/
-union cvmx_pcmx_txmsk0
-{
+union cvmx_pcmx_txmsk0 {
uint64_t u64;
- struct cvmx_pcmx_txmsk0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Transmit mask bits for slots 63 to 0
+ struct cvmx_pcmx_txmsk0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Transmit mask bits for slots 63 to 0 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -905,19 +957,19 @@ union cvmx_pcmx_txmsk0
struct cvmx_pcmx_txmsk0_s cn30xx;
struct cvmx_pcmx_txmsk0_s cn31xx;
struct cvmx_pcmx_txmsk0_s cn50xx;
+ struct cvmx_pcmx_txmsk0_s cn61xx;
+ struct cvmx_pcmx_txmsk0_s cnf71xx;
};
typedef union cvmx_pcmx_txmsk0 cvmx_pcmx_txmsk0_t;
/**
* cvmx_pcm#_txmsk1
*/
-union cvmx_pcmx_txmsk1
-{
+union cvmx_pcmx_txmsk1 {
uint64_t u64;
- struct cvmx_pcmx_txmsk1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Transmit mask bits for slots 127 to 64
+ struct cvmx_pcmx_txmsk1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Transmit mask bits for slots 127 to 64 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -926,19 +978,19 @@ union cvmx_pcmx_txmsk1
struct cvmx_pcmx_txmsk1_s cn30xx;
struct cvmx_pcmx_txmsk1_s cn31xx;
struct cvmx_pcmx_txmsk1_s cn50xx;
+ struct cvmx_pcmx_txmsk1_s cn61xx;
+ struct cvmx_pcmx_txmsk1_s cnf71xx;
};
typedef union cvmx_pcmx_txmsk1 cvmx_pcmx_txmsk1_t;
/**
* cvmx_pcm#_txmsk2
*/
-union cvmx_pcmx_txmsk2
-{
+union cvmx_pcmx_txmsk2 {
uint64_t u64;
- struct cvmx_pcmx_txmsk2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Transmit mask bits for slots 191 to 128
+ struct cvmx_pcmx_txmsk2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Transmit mask bits for slots 191 to 128 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -947,19 +999,19 @@ union cvmx_pcmx_txmsk2
struct cvmx_pcmx_txmsk2_s cn30xx;
struct cvmx_pcmx_txmsk2_s cn31xx;
struct cvmx_pcmx_txmsk2_s cn50xx;
+ struct cvmx_pcmx_txmsk2_s cn61xx;
+ struct cvmx_pcmx_txmsk2_s cnf71xx;
};
typedef union cvmx_pcmx_txmsk2 cvmx_pcmx_txmsk2_t;
/**
* cvmx_pcm#_txmsk3
*/
-union cvmx_pcmx_txmsk3
-{
+union cvmx_pcmx_txmsk3 {
uint64_t u64;
- struct cvmx_pcmx_txmsk3_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Transmit mask bits for slots 255 to 192
+ struct cvmx_pcmx_txmsk3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Transmit mask bits for slots 255 to 192 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -968,19 +1020,19 @@ union cvmx_pcmx_txmsk3
struct cvmx_pcmx_txmsk3_s cn30xx;
struct cvmx_pcmx_txmsk3_s cn31xx;
struct cvmx_pcmx_txmsk3_s cn50xx;
+ struct cvmx_pcmx_txmsk3_s cn61xx;
+ struct cvmx_pcmx_txmsk3_s cnf71xx;
};
typedef union cvmx_pcmx_txmsk3 cvmx_pcmx_txmsk3_t;
/**
* cvmx_pcm#_txmsk4
*/
-union cvmx_pcmx_txmsk4
-{
+union cvmx_pcmx_txmsk4 {
uint64_t u64;
- struct cvmx_pcmx_txmsk4_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Transmit mask bits for slots 319 to 256
+ struct cvmx_pcmx_txmsk4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Transmit mask bits for slots 319 to 256 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -989,19 +1041,19 @@ union cvmx_pcmx_txmsk4
struct cvmx_pcmx_txmsk4_s cn30xx;
struct cvmx_pcmx_txmsk4_s cn31xx;
struct cvmx_pcmx_txmsk4_s cn50xx;
+ struct cvmx_pcmx_txmsk4_s cn61xx;
+ struct cvmx_pcmx_txmsk4_s cnf71xx;
};
typedef union cvmx_pcmx_txmsk4 cvmx_pcmx_txmsk4_t;
/**
* cvmx_pcm#_txmsk5
*/
-union cvmx_pcmx_txmsk5
-{
+union cvmx_pcmx_txmsk5 {
uint64_t u64;
- struct cvmx_pcmx_txmsk5_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Transmit mask bits for slots 383 to 320
+ struct cvmx_pcmx_txmsk5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Transmit mask bits for slots 383 to 320 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -1010,19 +1062,19 @@ union cvmx_pcmx_txmsk5
struct cvmx_pcmx_txmsk5_s cn30xx;
struct cvmx_pcmx_txmsk5_s cn31xx;
struct cvmx_pcmx_txmsk5_s cn50xx;
+ struct cvmx_pcmx_txmsk5_s cn61xx;
+ struct cvmx_pcmx_txmsk5_s cnf71xx;
};
typedef union cvmx_pcmx_txmsk5 cvmx_pcmx_txmsk5_t;
/**
* cvmx_pcm#_txmsk6
*/
-union cvmx_pcmx_txmsk6
-{
+union cvmx_pcmx_txmsk6 {
uint64_t u64;
- struct cvmx_pcmx_txmsk6_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Transmit mask bits for slots 447 to 384
+ struct cvmx_pcmx_txmsk6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Transmit mask bits for slots 447 to 384 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -1031,19 +1083,19 @@ union cvmx_pcmx_txmsk6
struct cvmx_pcmx_txmsk6_s cn30xx;
struct cvmx_pcmx_txmsk6_s cn31xx;
struct cvmx_pcmx_txmsk6_s cn50xx;
+ struct cvmx_pcmx_txmsk6_s cn61xx;
+ struct cvmx_pcmx_txmsk6_s cnf71xx;
};
typedef union cvmx_pcmx_txmsk6 cvmx_pcmx_txmsk6_t;
/**
* cvmx_pcm#_txmsk7
*/
-union cvmx_pcmx_txmsk7
-{
+union cvmx_pcmx_txmsk7 {
uint64_t u64;
- struct cvmx_pcmx_txmsk7_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t mask : 64; /**< Transmit mask bits for slots 511 to 448
+ struct cvmx_pcmx_txmsk7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t mask : 64; /**< Transmit mask bits for slots 511 to 448 | NS
(1 means transmit, 0 means don't transmit) */
#else
uint64_t mask : 64;
@@ -1052,20 +1104,20 @@ union cvmx_pcmx_txmsk7
struct cvmx_pcmx_txmsk7_s cn30xx;
struct cvmx_pcmx_txmsk7_s cn31xx;
struct cvmx_pcmx_txmsk7_s cn50xx;
+ struct cvmx_pcmx_txmsk7_s cn61xx;
+ struct cvmx_pcmx_txmsk7_s cnf71xx;
};
typedef union cvmx_pcmx_txmsk7 cvmx_pcmx_txmsk7_t;
/**
* cvmx_pcm#_txstart
*/
-union cvmx_pcmx_txstart
-{
+union cvmx_pcmx_txstart {
uint64_t u64;
- struct cvmx_pcmx_txstart_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcmx_txstart_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63 : 28;
- uint64_t addr : 33; /**< Starting address for the transmit memory region */
+ uint64_t addr : 33; /**< Starting address for the transmit memory region | NS */
uint64_t reserved_0_2 : 3;
#else
uint64_t reserved_0_2 : 3;
@@ -1076,6 +1128,8 @@ union cvmx_pcmx_txstart
struct cvmx_pcmx_txstart_s cn30xx;
struct cvmx_pcmx_txstart_s cn31xx;
struct cvmx_pcmx_txstart_s cn50xx;
+ struct cvmx_pcmx_txstart_s cn61xx;
+ struct cvmx_pcmx_txstart_s cnf71xx;
};
typedef union cvmx_pcmx_txstart cvmx_pcmx_txstart_t;