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-rw-r--r--cvmx-pcm-defs.h80
1 files changed, 43 insertions, 37 deletions
diff --git a/cvmx-pcm-defs.h b/cvmx-pcm-defs.h
index 808f1b25ccfa..b68822313ab5 100644
--- a/cvmx-pcm-defs.h
+++ b/cvmx-pcm-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_PCM_TYPEDEFS_H__
-#define __CVMX_PCM_TYPEDEFS_H__
+#ifndef __CVMX_PCM_DEFS_H__
+#define __CVMX_PCM_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
@@ -58,7 +58,9 @@ static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384;
}
@@ -71,7 +73,9 @@ static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384;
}
@@ -84,7 +88,9 @@ static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384;
}
@@ -95,13 +101,11 @@ static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
/**
* cvmx_pcm_clk#_cfg
*/
-union cvmx_pcm_clkx_cfg
-{
+union cvmx_pcm_clkx_cfg {
uint64_t u64;
- struct cvmx_pcm_clkx_cfg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t fsyncgood : 1; /**< FSYNC status
+ struct cvmx_pcm_clkx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t fsyncgood : 1; /**< FSYNC status | NS
If 1, the last frame had a correctly positioned
fsync pulse
If 0, none/extra fsync pulse seen on most recent
@@ -110,23 +114,23 @@ union cvmx_pcm_clkx_cfg
and FSYNCMISSING interrupts are intended for
detecting loss of sync during normal operation. */
uint64_t reserved_48_62 : 15;
- uint64_t fsyncsamp : 16; /**< Number of ECLKs from internal BCLK edge to
+ uint64_t fsyncsamp : 16; /**< Number of ECLKs from internal BCLK edge to | NS
sample FSYNC
NOTE: used to sync to the start of a frame and to
check for FSYNC errors. */
uint64_t reserved_26_31 : 6;
- uint64_t fsynclen : 5; /**< Number of 1/2 BCLKs FSYNC is asserted for
+ uint64_t fsynclen : 5; /**< Number of 1/2 BCLKs FSYNC is asserted for | NS
NOTE: only used when GEN==1 */
- uint64_t fsyncloc : 5; /**< FSYNC location, in 1/2 BCLKS before timeslot 0,
+ uint64_t fsyncloc : 5; /**< FSYNC location, in 1/2 BCLKS before timeslot 0, | NS
bit 0.
NOTE: also used to detect framing errors and
therefore must have a correct value even if GEN==0 */
- uint64_t numslots : 10; /**< Number of 8-bit slots in a frame
+ uint64_t numslots : 10; /**< Number of 8-bit slots in a frame | NS
NOTE: this, along with EXTRABIT and Fbclk
determines FSYNC frequency when GEN == 1
NOTE: also used to detect framing errors and
therefore must have a correct value even if GEN==0 */
- uint64_t extrabit : 1; /**< If 0, no frame bit
+ uint64_t extrabit : 1; /**< If 0, no frame bit | NS
If 1, add one extra bit time for frame bit
NOTE: if GEN == 1, then FSYNC will be delayed one
extra bit time.
@@ -136,20 +140,20 @@ union cvmx_pcm_clkx_cfg
first byte of the frame in the transmit memory
region. LSB vs MSB is determined from the setting
of PCMn_TDM_CFG[LSBFIRST]. */
- uint64_t bitlen : 2; /**< Number of BCLKs in a bit time.
+ uint64_t bitlen : 2; /**< Number of BCLKs in a bit time. | NS
0 : 1 BCLK
1 : 2 BCLKs
2 : 4 BCLKs
3 : operation undefined */
- uint64_t bclkpol : 1; /**< If 0, BCLK rise edge is start of bit time
+ uint64_t bclkpol : 1; /**< If 0, BCLK rise edge is start of bit time | NS
If 1, BCLK fall edge is start of bit time
NOTE: also used to detect framing errors and
therefore must have a correct value even if GEN==0 */
- uint64_t fsyncpol : 1; /**< If 0, FSYNC idles low, asserts high
+ uint64_t fsyncpol : 1; /**< If 0, FSYNC idles low, asserts high | NS
If 1, FSYNC idles high, asserts low
NOTE: also used to detect framing errors and
therefore must have a correct value even if GEN==0 */
- uint64_t ena : 1; /**< If 0, Clock receiving logic is doing nothing
+ uint64_t ena : 1; /**< If 0, Clock receiving logic is doing nothing | NS
1, Clock receiving logic is looking for sync */
#else
uint64_t ena : 1;
@@ -169,19 +173,19 @@ union cvmx_pcm_clkx_cfg
struct cvmx_pcm_clkx_cfg_s cn30xx;
struct cvmx_pcm_clkx_cfg_s cn31xx;
struct cvmx_pcm_clkx_cfg_s cn50xx;
+ struct cvmx_pcm_clkx_cfg_s cn61xx;
+ struct cvmx_pcm_clkx_cfg_s cnf71xx;
};
typedef union cvmx_pcm_clkx_cfg cvmx_pcm_clkx_cfg_t;
/**
* cvmx_pcm_clk#_dbg
*/
-union cvmx_pcm_clkx_dbg
-{
+union cvmx_pcm_clkx_dbg {
uint64_t u64;
- struct cvmx_pcm_clkx_dbg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t debuginfo : 64; /**< Miscellaneous debug information */
+ struct cvmx_pcm_clkx_dbg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t debuginfo : 64; /**< Miscellaneous debug information | NS */
#else
uint64_t debuginfo : 64;
#endif
@@ -189,28 +193,28 @@ union cvmx_pcm_clkx_dbg
struct cvmx_pcm_clkx_dbg_s cn30xx;
struct cvmx_pcm_clkx_dbg_s cn31xx;
struct cvmx_pcm_clkx_dbg_s cn50xx;
+ struct cvmx_pcm_clkx_dbg_s cn61xx;
+ struct cvmx_pcm_clkx_dbg_s cnf71xx;
};
typedef union cvmx_pcm_clkx_dbg cvmx_pcm_clkx_dbg_t;
/**
* cvmx_pcm_clk#_gen
*/
-union cvmx_pcm_clkx_gen
-{
+union cvmx_pcm_clkx_gen {
uint64_t u64;
- struct cvmx_pcm_clkx_gen_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t deltasamp : 16; /**< Signed number of ECLKs to move sampled BCLK edge
+ struct cvmx_pcm_clkx_gen_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t deltasamp : 16; /**< Signed number of ECLKs to move sampled BCLK edge | NS
NOTE: the complete number of ECLKs to move is:
NUMSAMP + 2 + 1 + DELTASAMP
NUMSAMP to compensate for sampling delay
+ 2 to compensate for dual-rank synchronizer
+ 1 for uncertainity
+ DELTASAMP to CMA/debugging */
- uint64_t numsamp : 16; /**< Number of ECLK samples to detect BCLK change when
+ uint64_t numsamp : 16; /**< Number of ECLK samples to detect BCLK change when | NS
receiving clock. */
- uint64_t n : 32; /**< Determines BCLK frequency when generating clock
+ uint64_t n : 32; /**< Determines BCLK frequency when generating clock | NS
NOTE: Fbclk = Feclk * N / 2^32
N = (Fbclk / Feclk) * 2^32
NOTE: writing N == 0 stops the clock generator, and
@@ -224,6 +228,8 @@ union cvmx_pcm_clkx_gen
struct cvmx_pcm_clkx_gen_s cn30xx;
struct cvmx_pcm_clkx_gen_s cn31xx;
struct cvmx_pcm_clkx_gen_s cn50xx;
+ struct cvmx_pcm_clkx_gen_s cn61xx;
+ struct cvmx_pcm_clkx_gen_s cnf71xx;
};
typedef union cvmx_pcm_clkx_gen cvmx_pcm_clkx_gen_t;