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-rw-r--r--cvmx-pcieepx-defs.h2891
1 files changed, 2277 insertions, 614 deletions
diff --git a/cvmx-pcieepx-defs.h b/cvmx-pcieepx-defs.h
index 6af85a186cdf..4562d6d0b547 100644
--- a/cvmx-pcieepx-defs.h
+++ b/cvmx-pcieepx-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_PCIEEPX_TYPEDEFS_H__
-#define __CVMX_PCIEEPX_TYPEDEFS_H__
+#ifndef __CVMX_PCIEEPX_DEFS_H__
+#define __CVMX_PCIEEPX_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id)
@@ -58,7 +58,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG000(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000000ull;
}
@@ -71,7 +75,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG001(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG001(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000004ull;
}
@@ -84,7 +92,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG002(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG002(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000008ull;
}
@@ -97,7 +109,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG003(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG003(%lu) is invalid on this chip\n", block_id);
return 0x000000000000000Cull;
}
@@ -110,7 +126,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG004(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG004(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000010ull;
}
@@ -123,7 +143,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG004_MASK(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG004_MASK(%lu) is invalid on this chip\n", block_id);
return 0x0000000080000010ull;
}
@@ -136,7 +160,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG005(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG005(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000014ull;
}
@@ -149,7 +177,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG005_MASK(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG005_MASK(%lu) is invalid on this chip\n", block_id);
return 0x0000000080000014ull;
}
@@ -162,7 +194,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG006(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG006(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000018ull;
}
@@ -175,7 +211,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG006_MASK(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG006_MASK(%lu) is invalid on this chip\n", block_id);
return 0x0000000080000018ull;
}
@@ -188,7 +228,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG007(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG007(%lu) is invalid on this chip\n", block_id);
return 0x000000000000001Cull;
}
@@ -201,7 +245,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG007_MASK(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG007_MASK(%lu) is invalid on this chip\n", block_id);
return 0x000000008000001Cull;
}
@@ -214,7 +262,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG008(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG008(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000020ull;
}
@@ -227,7 +279,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG008_MASK(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG008_MASK(%lu) is invalid on this chip\n", block_id);
return 0x0000000080000020ull;
}
@@ -240,7 +296,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG009(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG009(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000024ull;
}
@@ -253,7 +313,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG009_MASK(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG009_MASK(%lu) is invalid on this chip\n", block_id);
return 0x0000000080000024ull;
}
@@ -266,7 +330,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG010(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG010(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000028ull;
}
@@ -279,7 +347,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG011(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG011(%lu) is invalid on this chip\n", block_id);
return 0x000000000000002Cull;
}
@@ -292,7 +364,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG012(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG012(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000030ull;
}
@@ -305,7 +381,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG012_MASK(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG012_MASK(%lu) is invalid on this chip\n", block_id);
return 0x0000000080000030ull;
}
@@ -318,7 +398,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG013(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG013(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000034ull;
}
@@ -331,7 +415,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG015(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG015(%lu) is invalid on this chip\n", block_id);
return 0x000000000000003Cull;
}
@@ -344,7 +432,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG016(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG016(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000040ull;
}
@@ -357,7 +449,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG017(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG017(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000044ull;
}
@@ -370,7 +466,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG020(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG020(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000050ull;
}
@@ -383,7 +483,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG021(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG021(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000054ull;
}
@@ -396,7 +500,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG022(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG022(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000058ull;
}
@@ -409,7 +517,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG023(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG023(%lu) is invalid on this chip\n", block_id);
return 0x000000000000005Cull;
}
@@ -422,7 +534,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG028(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG028(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000070ull;
}
@@ -435,7 +551,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG029(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG029(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000074ull;
}
@@ -448,7 +568,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG030(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG030(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000078ull;
}
@@ -461,7 +585,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG031(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG031(%lu) is invalid on this chip\n", block_id);
return 0x000000000000007Cull;
}
@@ -474,7 +602,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG032(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG032(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000080ull;
}
@@ -513,7 +645,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG037(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG037(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000094ull;
}
@@ -526,7 +662,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG038(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG038(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000098ull;
}
@@ -539,7 +679,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG039(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG039(%lu) is invalid on this chip\n", block_id);
return 0x000000000000009Cull;
}
@@ -552,7 +696,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG040(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG040(%lu) is invalid on this chip\n", block_id);
return 0x00000000000000A0ull;
}
@@ -591,7 +739,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG064(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG064(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000100ull;
}
@@ -604,7 +756,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG065(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG065(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000104ull;
}
@@ -617,7 +773,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG066(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG066(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000108ull;
}
@@ -630,7 +790,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG067(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG067(%lu) is invalid on this chip\n", block_id);
return 0x000000000000010Cull;
}
@@ -643,7 +807,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG068(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG068(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000110ull;
}
@@ -656,7 +824,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG069(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG069(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000114ull;
}
@@ -669,7 +841,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG070(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG070(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000118ull;
}
@@ -682,7 +858,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG071(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG071(%lu) is invalid on this chip\n", block_id);
return 0x000000000000011Cull;
}
@@ -695,7 +875,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG072(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG072(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000120ull;
}
@@ -708,7 +892,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG073(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG073(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000124ull;
}
@@ -721,7 +909,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG074(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG074(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000128ull;
}
@@ -734,7 +926,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG448(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG448(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000700ull;
}
@@ -747,7 +943,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG449(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG449(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000704ull;
}
@@ -760,7 +960,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG450(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG450(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000708ull;
}
@@ -773,7 +977,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG451(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG451(%lu) is invalid on this chip\n", block_id);
return 0x000000000000070Cull;
}
@@ -786,7 +994,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG452(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG452(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000710ull;
}
@@ -799,7 +1011,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG453(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG453(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000714ull;
}
@@ -812,7 +1028,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG454(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG454(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000718ull;
}
@@ -825,7 +1045,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG455(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG455(%lu) is invalid on this chip\n", block_id);
return 0x000000000000071Cull;
}
@@ -838,7 +1062,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG456(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG456(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000720ull;
}
@@ -851,7 +1079,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG458(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG458(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000728ull;
}
@@ -864,7 +1096,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG459(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG459(%lu) is invalid on this chip\n", block_id);
return 0x000000000000072Cull;
}
@@ -877,7 +1113,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG460(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG460(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000730ull;
}
@@ -890,7 +1130,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG461(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG461(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000734ull;
}
@@ -903,7 +1147,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG462(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG462(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000738ull;
}
@@ -916,7 +1164,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG463(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG463(%lu) is invalid on this chip\n", block_id);
return 0x000000000000073Cull;
}
@@ -929,7 +1181,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG464(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG464(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000740ull;
}
@@ -942,7 +1198,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG465(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG465(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000744ull;
}
@@ -955,7 +1215,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG466(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG466(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000748ull;
}
@@ -968,7 +1232,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG467(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG467(%lu) is invalid on this chip\n", block_id);
return 0x000000000000074Cull;
}
@@ -981,7 +1249,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG468(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG468(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000750ull;
}
@@ -994,7 +1266,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG490(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG490(%lu) is invalid on this chip\n", block_id);
return 0x00000000000007A8ull;
}
@@ -1007,7 +1283,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG491(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG491(%lu) is invalid on this chip\n", block_id);
return 0x00000000000007ACull;
}
@@ -1020,7 +1300,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG492(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG492(%lu) is invalid on this chip\n", block_id);
return 0x00000000000007B0ull;
}
@@ -1031,7 +1315,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG492(unsigned long block_id)
static inline uint64_t CVMX_PCIEEPX_CFG515(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG515(%lu) is invalid on this chip\n", block_id);
return 0x000000000000080Cull;
}
@@ -1044,7 +1332,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG516(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG516(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000810ull;
}
@@ -1057,7 +1349,11 @@ static inline uint64_t CVMX_PCIEEPX_CFG517(unsigned long block_id)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
cvmx_warn("CVMX_PCIEEPX_CFG517(%lu) is invalid on this chip\n", block_id);
return 0x0000000000000814ull;
}
@@ -1071,12 +1367,10 @@ static inline uint64_t CVMX_PCIEEPX_CFG517(unsigned long block_id)
* PCIE_CFG000 = First 32-bits of PCIE type 0 config space (Device ID and Vendor ID Register)
*
*/
-union cvmx_pcieepx_cfg000
-{
+union cvmx_pcieepx_cfg000 {
uint32_t u32;
- struct cvmx_pcieepx_cfg000_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg000_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t devid : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR
However, the application must not change this field.
For EEPROM loads also see VENDID of this register. */
@@ -1096,8 +1390,13 @@ union cvmx_pcieepx_cfg000
struct cvmx_pcieepx_cfg000_s cn52xxp1;
struct cvmx_pcieepx_cfg000_s cn56xx;
struct cvmx_pcieepx_cfg000_s cn56xxp1;
+ struct cvmx_pcieepx_cfg000_s cn61xx;
struct cvmx_pcieepx_cfg000_s cn63xx;
struct cvmx_pcieepx_cfg000_s cn63xxp1;
+ struct cvmx_pcieepx_cfg000_s cn66xx;
+ struct cvmx_pcieepx_cfg000_s cn68xx;
+ struct cvmx_pcieepx_cfg000_s cn68xxp1;
+ struct cvmx_pcieepx_cfg000_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t;
@@ -1107,12 +1406,10 @@ typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t;
* PCIE_CFG001 = Second 32-bits of PCIE type 0 config space (Command/Status Register)
*
*/
-union cvmx_pcieepx_cfg001
-{
+union cvmx_pcieepx_cfg001 {
uint32_t u32;
- struct cvmx_pcieepx_cfg001_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg001_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dpe : 1; /**< Detected Parity Error */
uint32_t sse : 1; /**< Signaled System Error */
uint32_t rma : 1; /**< Received Master Abort */
@@ -1178,8 +1475,13 @@ union cvmx_pcieepx_cfg001
struct cvmx_pcieepx_cfg001_s cn52xxp1;
struct cvmx_pcieepx_cfg001_s cn56xx;
struct cvmx_pcieepx_cfg001_s cn56xxp1;
+ struct cvmx_pcieepx_cfg001_s cn61xx;
struct cvmx_pcieepx_cfg001_s cn63xx;
struct cvmx_pcieepx_cfg001_s cn63xxp1;
+ struct cvmx_pcieepx_cfg001_s cn66xx;
+ struct cvmx_pcieepx_cfg001_s cn68xx;
+ struct cvmx_pcieepx_cfg001_s cn68xxp1;
+ struct cvmx_pcieepx_cfg001_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t;
@@ -1189,12 +1491,10 @@ typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t;
* PCIE_CFG002 = Third 32-bits of PCIE type 0 config space (Revision ID/Class Code Register)
*
*/
-union cvmx_pcieepx_cfg002
-{
+union cvmx_pcieepx_cfg002 {
uint32_t u32;
- struct cvmx_pcieepx_cfg002_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg002_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t bcc : 8; /**< Base Class Code, writable through PEM(0..1)_CFG_WR
However, the application must not change this field. */
uint32_t sc : 8; /**< Subclass Code, writable through PEM(0..1)_CFG_WR
@@ -1214,8 +1514,13 @@ union cvmx_pcieepx_cfg002
struct cvmx_pcieepx_cfg002_s cn52xxp1;
struct cvmx_pcieepx_cfg002_s cn56xx;
struct cvmx_pcieepx_cfg002_s cn56xxp1;
+ struct cvmx_pcieepx_cfg002_s cn61xx;
struct cvmx_pcieepx_cfg002_s cn63xx;
struct cvmx_pcieepx_cfg002_s cn63xxp1;
+ struct cvmx_pcieepx_cfg002_s cn66xx;
+ struct cvmx_pcieepx_cfg002_s cn68xx;
+ struct cvmx_pcieepx_cfg002_s cn68xxp1;
+ struct cvmx_pcieepx_cfg002_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t;
@@ -1225,12 +1530,10 @@ typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t;
* PCIE_CFG003 = Fourth 32-bits of PCIE type 0 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
*
*/
-union cvmx_pcieepx_cfg003
-{
+union cvmx_pcieepx_cfg003 {
uint32_t u32;
- struct cvmx_pcieepx_cfg003_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg003_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t bist : 8; /**< The BIST register functions are not supported.
All 8 bits of the BIST register are hardwired to 0. */
uint32_t mfd : 1; /**< Multi Function Device
@@ -1259,8 +1562,13 @@ union cvmx_pcieepx_cfg003
struct cvmx_pcieepx_cfg003_s cn52xxp1;
struct cvmx_pcieepx_cfg003_s cn56xx;
struct cvmx_pcieepx_cfg003_s cn56xxp1;
+ struct cvmx_pcieepx_cfg003_s cn61xx;
struct cvmx_pcieepx_cfg003_s cn63xx;
struct cvmx_pcieepx_cfg003_s cn63xxp1;
+ struct cvmx_pcieepx_cfg003_s cn66xx;
+ struct cvmx_pcieepx_cfg003_s cn68xx;
+ struct cvmx_pcieepx_cfg003_s cn68xxp1;
+ struct cvmx_pcieepx_cfg003_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t;
@@ -1270,12 +1578,10 @@ typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t;
* PCIE_CFG004 = Fifth 32-bits of PCIE type 0 config space (Base Address Register 0 - Low)
*
*/
-union cvmx_pcieepx_cfg004
-{
+union cvmx_pcieepx_cfg004 {
uint32_t u32;
- struct cvmx_pcieepx_cfg004_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg004_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lbab : 18; /**< Lower bits of the BAR 0 base address */
uint32_t reserved_4_13 : 10;
uint32_t pf : 1; /**< Prefetchable
@@ -1303,8 +1609,13 @@ union cvmx_pcieepx_cfg004
struct cvmx_pcieepx_cfg004_s cn52xxp1;
struct cvmx_pcieepx_cfg004_s cn56xx;
struct cvmx_pcieepx_cfg004_s cn56xxp1;
+ struct cvmx_pcieepx_cfg004_s cn61xx;
struct cvmx_pcieepx_cfg004_s cn63xx;
struct cvmx_pcieepx_cfg004_s cn63xxp1;
+ struct cvmx_pcieepx_cfg004_s cn66xx;
+ struct cvmx_pcieepx_cfg004_s cn68xx;
+ struct cvmx_pcieepx_cfg004_s cn68xxp1;
+ struct cvmx_pcieepx_cfg004_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t;
@@ -1315,12 +1626,10 @@ typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t;
* The BAR 0 Mask register is invisible to host software and not readable from the application.
* The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR.
*/
-union cvmx_pcieepx_cfg004_mask
-{
+union cvmx_pcieepx_cfg004_mask {
uint32_t u32;
- struct cvmx_pcieepx_cfg004_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg004_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lmask : 31; /**< Bar Mask Low */
uint32_t enb : 1; /**< Bar Enable
o 0: BAR 0 is disabled
@@ -1338,8 +1647,13 @@ union cvmx_pcieepx_cfg004_mask
struct cvmx_pcieepx_cfg004_mask_s cn52xxp1;
struct cvmx_pcieepx_cfg004_mask_s cn56xx;
struct cvmx_pcieepx_cfg004_mask_s cn56xxp1;
+ struct cvmx_pcieepx_cfg004_mask_s cn61xx;
struct cvmx_pcieepx_cfg004_mask_s cn63xx;
struct cvmx_pcieepx_cfg004_mask_s cn63xxp1;
+ struct cvmx_pcieepx_cfg004_mask_s cn66xx;
+ struct cvmx_pcieepx_cfg004_mask_s cn68xx;
+ struct cvmx_pcieepx_cfg004_mask_s cn68xxp1;
+ struct cvmx_pcieepx_cfg004_mask_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t;
@@ -1349,12 +1663,10 @@ typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t;
* PCIE_CFG005 = Sixth 32-bits of PCIE type 0 config space (Base Address Register 0 - High)
*
*/
-union cvmx_pcieepx_cfg005
-{
+union cvmx_pcieepx_cfg005 {
uint32_t u32;
- struct cvmx_pcieepx_cfg005_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg005_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ubab : 32; /**< Contains the upper 32 bits of the BAR 0 base address. */
#else
uint32_t ubab : 32;
@@ -1364,8 +1676,13 @@ union cvmx_pcieepx_cfg005
struct cvmx_pcieepx_cfg005_s cn52xxp1;
struct cvmx_pcieepx_cfg005_s cn56xx;
struct cvmx_pcieepx_cfg005_s cn56xxp1;
+ struct cvmx_pcieepx_cfg005_s cn61xx;
struct cvmx_pcieepx_cfg005_s cn63xx;
struct cvmx_pcieepx_cfg005_s cn63xxp1;
+ struct cvmx_pcieepx_cfg005_s cn66xx;
+ struct cvmx_pcieepx_cfg005_s cn68xx;
+ struct cvmx_pcieepx_cfg005_s cn68xxp1;
+ struct cvmx_pcieepx_cfg005_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t;
@@ -1376,12 +1693,10 @@ typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t;
* The BAR 0 Mask register is invisible to host software and not readable from the application.
* The BAR 0 Mask register is only writable through PEM(0..1)_CFG_WR.
*/
-union cvmx_pcieepx_cfg005_mask
-{
+union cvmx_pcieepx_cfg005_mask {
uint32_t u32;
- struct cvmx_pcieepx_cfg005_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg005_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t umask : 32; /**< Bar Mask High */
#else
uint32_t umask : 32;
@@ -1391,8 +1706,13 @@ union cvmx_pcieepx_cfg005_mask
struct cvmx_pcieepx_cfg005_mask_s cn52xxp1;
struct cvmx_pcieepx_cfg005_mask_s cn56xx;
struct cvmx_pcieepx_cfg005_mask_s cn56xxp1;
+ struct cvmx_pcieepx_cfg005_mask_s cn61xx;
struct cvmx_pcieepx_cfg005_mask_s cn63xx;
struct cvmx_pcieepx_cfg005_mask_s cn63xxp1;
+ struct cvmx_pcieepx_cfg005_mask_s cn66xx;
+ struct cvmx_pcieepx_cfg005_mask_s cn68xx;
+ struct cvmx_pcieepx_cfg005_mask_s cn68xxp1;
+ struct cvmx_pcieepx_cfg005_mask_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t;
@@ -1402,12 +1722,10 @@ typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t;
* PCIE_CFG006 = Seventh 32-bits of PCIE type 0 config space (Base Address Register 1 - Low)
*
*/
-union cvmx_pcieepx_cfg006
-{
+union cvmx_pcieepx_cfg006 {
uint32_t u32;
- struct cvmx_pcieepx_cfg006_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg006_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lbab : 6; /**< Lower bits of the BAR 1 base address */
uint32_t reserved_4_25 : 22;
uint32_t pf : 1; /**< Prefetchable
@@ -1435,8 +1753,13 @@ union cvmx_pcieepx_cfg006
struct cvmx_pcieepx_cfg006_s cn52xxp1;
struct cvmx_pcieepx_cfg006_s cn56xx;
struct cvmx_pcieepx_cfg006_s cn56xxp1;
+ struct cvmx_pcieepx_cfg006_s cn61xx;
struct cvmx_pcieepx_cfg006_s cn63xx;
struct cvmx_pcieepx_cfg006_s cn63xxp1;
+ struct cvmx_pcieepx_cfg006_s cn66xx;
+ struct cvmx_pcieepx_cfg006_s cn68xx;
+ struct cvmx_pcieepx_cfg006_s cn68xxp1;
+ struct cvmx_pcieepx_cfg006_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t;
@@ -1447,12 +1770,10 @@ typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t;
* The BAR 1 Mask register is invisible to host software and not readable from the application.
* The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR.
*/
-union cvmx_pcieepx_cfg006_mask
-{
+union cvmx_pcieepx_cfg006_mask {
uint32_t u32;
- struct cvmx_pcieepx_cfg006_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg006_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lmask : 31; /**< Bar Mask Low */
uint32_t enb : 1; /**< Bar Enable
o 0: BAR 1 is disabled
@@ -1470,8 +1791,13 @@ union cvmx_pcieepx_cfg006_mask
struct cvmx_pcieepx_cfg006_mask_s cn52xxp1;
struct cvmx_pcieepx_cfg006_mask_s cn56xx;
struct cvmx_pcieepx_cfg006_mask_s cn56xxp1;
+ struct cvmx_pcieepx_cfg006_mask_s cn61xx;
struct cvmx_pcieepx_cfg006_mask_s cn63xx;
struct cvmx_pcieepx_cfg006_mask_s cn63xxp1;
+ struct cvmx_pcieepx_cfg006_mask_s cn66xx;
+ struct cvmx_pcieepx_cfg006_mask_s cn68xx;
+ struct cvmx_pcieepx_cfg006_mask_s cn68xxp1;
+ struct cvmx_pcieepx_cfg006_mask_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t;
@@ -1481,12 +1807,10 @@ typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t;
* PCIE_CFG007 = Eighth 32-bits of PCIE type 0 config space (Base Address Register 1 - High)
*
*/
-union cvmx_pcieepx_cfg007
-{
+union cvmx_pcieepx_cfg007 {
uint32_t u32;
- struct cvmx_pcieepx_cfg007_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg007_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ubab : 32; /**< Contains the upper 32 bits of the BAR 1 base address. */
#else
uint32_t ubab : 32;
@@ -1496,8 +1820,13 @@ union cvmx_pcieepx_cfg007
struct cvmx_pcieepx_cfg007_s cn52xxp1;
struct cvmx_pcieepx_cfg007_s cn56xx;
struct cvmx_pcieepx_cfg007_s cn56xxp1;
+ struct cvmx_pcieepx_cfg007_s cn61xx;
struct cvmx_pcieepx_cfg007_s cn63xx;
struct cvmx_pcieepx_cfg007_s cn63xxp1;
+ struct cvmx_pcieepx_cfg007_s cn66xx;
+ struct cvmx_pcieepx_cfg007_s cn68xx;
+ struct cvmx_pcieepx_cfg007_s cn68xxp1;
+ struct cvmx_pcieepx_cfg007_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t;
@@ -1508,12 +1837,10 @@ typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t;
* The BAR 1 Mask register is invisible to host software and not readable from the application.
* The BAR 1 Mask register is only writable through PEM(0..1)_CFG_WR.
*/
-union cvmx_pcieepx_cfg007_mask
-{
+union cvmx_pcieepx_cfg007_mask {
uint32_t u32;
- struct cvmx_pcieepx_cfg007_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg007_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t umask : 32; /**< Bar Mask High */
#else
uint32_t umask : 32;
@@ -1523,8 +1850,13 @@ union cvmx_pcieepx_cfg007_mask
struct cvmx_pcieepx_cfg007_mask_s cn52xxp1;
struct cvmx_pcieepx_cfg007_mask_s cn56xx;
struct cvmx_pcieepx_cfg007_mask_s cn56xxp1;
+ struct cvmx_pcieepx_cfg007_mask_s cn61xx;
struct cvmx_pcieepx_cfg007_mask_s cn63xx;
struct cvmx_pcieepx_cfg007_mask_s cn63xxp1;
+ struct cvmx_pcieepx_cfg007_mask_s cn66xx;
+ struct cvmx_pcieepx_cfg007_mask_s cn68xx;
+ struct cvmx_pcieepx_cfg007_mask_s cn68xxp1;
+ struct cvmx_pcieepx_cfg007_mask_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t;
@@ -1534,12 +1866,10 @@ typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t;
* PCIE_CFG008 = Ninth 32-bits of PCIE type 0 config space (Base Address Register 2 - Low)
*
*/
-union cvmx_pcieepx_cfg008
-{
+union cvmx_pcieepx_cfg008 {
uint32_t u32;
- struct cvmx_pcieepx_cfg008_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg008_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_4_31 : 28;
uint32_t pf : 1; /**< Prefetchable
This field is writable through PEM(0..1)_CFG_WR.
@@ -1565,8 +1895,13 @@ union cvmx_pcieepx_cfg008
struct cvmx_pcieepx_cfg008_s cn52xxp1;
struct cvmx_pcieepx_cfg008_s cn56xx;
struct cvmx_pcieepx_cfg008_s cn56xxp1;
+ struct cvmx_pcieepx_cfg008_s cn61xx;
struct cvmx_pcieepx_cfg008_s cn63xx;
struct cvmx_pcieepx_cfg008_s cn63xxp1;
+ struct cvmx_pcieepx_cfg008_s cn66xx;
+ struct cvmx_pcieepx_cfg008_s cn68xx;
+ struct cvmx_pcieepx_cfg008_s cn68xxp1;
+ struct cvmx_pcieepx_cfg008_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t;
@@ -1577,12 +1912,10 @@ typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t;
* The BAR 2 Mask register is invisible to host software and not readable from the application.
* The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR.
*/
-union cvmx_pcieepx_cfg008_mask
-{
+union cvmx_pcieepx_cfg008_mask {
uint32_t u32;
- struct cvmx_pcieepx_cfg008_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg008_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lmask : 31; /**< Bar Mask Low */
uint32_t enb : 1; /**< Bar Enable
o 0: BAR 2 is disabled
@@ -1600,8 +1933,13 @@ union cvmx_pcieepx_cfg008_mask
struct cvmx_pcieepx_cfg008_mask_s cn52xxp1;
struct cvmx_pcieepx_cfg008_mask_s cn56xx;
struct cvmx_pcieepx_cfg008_mask_s cn56xxp1;
+ struct cvmx_pcieepx_cfg008_mask_s cn61xx;
struct cvmx_pcieepx_cfg008_mask_s cn63xx;
struct cvmx_pcieepx_cfg008_mask_s cn63xxp1;
+ struct cvmx_pcieepx_cfg008_mask_s cn66xx;
+ struct cvmx_pcieepx_cfg008_mask_s cn68xx;
+ struct cvmx_pcieepx_cfg008_mask_s cn68xxp1;
+ struct cvmx_pcieepx_cfg008_mask_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t;
@@ -1611,20 +1949,17 @@ typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t;
* PCIE_CFG009 = Tenth 32-bits of PCIE type 0 config space (Base Address Register 2 - High)
*
*/
-union cvmx_pcieepx_cfg009
-{
+union cvmx_pcieepx_cfg009 {
uint32_t u32;
- struct cvmx_pcieepx_cfg009_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg009_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_0_31 : 32;
#else
uint32_t reserved_0_31 : 32;
#endif
} s;
- struct cvmx_pcieepx_cfg009_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg009_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ubab : 25; /**< Contains the upper 32 bits of the BAR 2 base address. */
uint32_t reserved_0_6 : 7;
#else
@@ -1635,17 +1970,21 @@ union cvmx_pcieepx_cfg009
struct cvmx_pcieepx_cfg009_cn52xx cn52xxp1;
struct cvmx_pcieepx_cfg009_cn52xx cn56xx;
struct cvmx_pcieepx_cfg009_cn52xx cn56xxp1;
- struct cvmx_pcieepx_cfg009_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg009_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ubab : 23; /**< Contains the upper 32 bits of the BAR 2 base address. */
uint32_t reserved_0_8 : 9;
#else
uint32_t reserved_0_8 : 9;
uint32_t ubab : 23;
#endif
- } cn63xx;
- struct cvmx_pcieepx_cfg009_cn63xx cn63xxp1;
+ } cn61xx;
+ struct cvmx_pcieepx_cfg009_cn61xx cn63xx;
+ struct cvmx_pcieepx_cfg009_cn61xx cn63xxp1;
+ struct cvmx_pcieepx_cfg009_cn61xx cn66xx;
+ struct cvmx_pcieepx_cfg009_cn61xx cn68xx;
+ struct cvmx_pcieepx_cfg009_cn61xx cn68xxp1;
+ struct cvmx_pcieepx_cfg009_cn61xx cnf71xx;
};
typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t;
@@ -1656,12 +1995,10 @@ typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t;
* The BAR 2 Mask register is invisible to host software and not readable from the application.
* The BAR 2 Mask register is only writable through PEM(0..1)_CFG_WR.
*/
-union cvmx_pcieepx_cfg009_mask
-{
+union cvmx_pcieepx_cfg009_mask {
uint32_t u32;
- struct cvmx_pcieepx_cfg009_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg009_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t umask : 32; /**< Bar Mask High */
#else
uint32_t umask : 32;
@@ -1671,8 +2008,13 @@ union cvmx_pcieepx_cfg009_mask
struct cvmx_pcieepx_cfg009_mask_s cn52xxp1;
struct cvmx_pcieepx_cfg009_mask_s cn56xx;
struct cvmx_pcieepx_cfg009_mask_s cn56xxp1;
+ struct cvmx_pcieepx_cfg009_mask_s cn61xx;
struct cvmx_pcieepx_cfg009_mask_s cn63xx;
struct cvmx_pcieepx_cfg009_mask_s cn63xxp1;
+ struct cvmx_pcieepx_cfg009_mask_s cn66xx;
+ struct cvmx_pcieepx_cfg009_mask_s cn68xx;
+ struct cvmx_pcieepx_cfg009_mask_s cn68xxp1;
+ struct cvmx_pcieepx_cfg009_mask_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t;
@@ -1682,12 +2024,10 @@ typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t;
* PCIE_CFG010 = Eleventh 32-bits of PCIE type 0 config space (CardBus CIS Pointer Register)
*
*/
-union cvmx_pcieepx_cfg010
-{
+union cvmx_pcieepx_cfg010 {
uint32_t u32;
- struct cvmx_pcieepx_cfg010_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg010_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t cisp : 32; /**< CardBus CIS Pointer
Optional, writable through PEM(0..1)_CFG_WR. */
#else
@@ -1698,8 +2038,13 @@ union cvmx_pcieepx_cfg010
struct cvmx_pcieepx_cfg010_s cn52xxp1;
struct cvmx_pcieepx_cfg010_s cn56xx;
struct cvmx_pcieepx_cfg010_s cn56xxp1;
+ struct cvmx_pcieepx_cfg010_s cn61xx;
struct cvmx_pcieepx_cfg010_s cn63xx;
struct cvmx_pcieepx_cfg010_s cn63xxp1;
+ struct cvmx_pcieepx_cfg010_s cn66xx;
+ struct cvmx_pcieepx_cfg010_s cn68xx;
+ struct cvmx_pcieepx_cfg010_s cn68xxp1;
+ struct cvmx_pcieepx_cfg010_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t;
@@ -1709,12 +2054,10 @@ typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t;
* PCIE_CFG011 = Twelfth 32-bits of PCIE type 0 config space (Subsystem ID and Subsystem Vendor ID Register)
*
*/
-union cvmx_pcieepx_cfg011
-{
+union cvmx_pcieepx_cfg011 {
uint32_t u32;
- struct cvmx_pcieepx_cfg011_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg011_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ssid : 16; /**< Subsystem ID
Assigned by PCI-SIG, writable through PEM(0..1)_CFG_WR. However, the application must not change this field. */
uint32_t ssvid : 16; /**< Subsystem Vendor ID
@@ -1729,8 +2072,13 @@ union cvmx_pcieepx_cfg011
struct cvmx_pcieepx_cfg011_s cn52xxp1;
struct cvmx_pcieepx_cfg011_s cn56xx;
struct cvmx_pcieepx_cfg011_s cn56xxp1;
+ struct cvmx_pcieepx_cfg011_s cn61xx;
struct cvmx_pcieepx_cfg011_s cn63xx;
struct cvmx_pcieepx_cfg011_s cn63xxp1;
+ struct cvmx_pcieepx_cfg011_s cn66xx;
+ struct cvmx_pcieepx_cfg011_s cn68xx;
+ struct cvmx_pcieepx_cfg011_s cn68xxp1;
+ struct cvmx_pcieepx_cfg011_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t;
@@ -1740,12 +2088,10 @@ typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t;
* PCIE_CFG012 = Thirteenth 32-bits of PCIE type 0 config space (Expansion ROM Base Address Register)
*
*/
-union cvmx_pcieepx_cfg012
-{
+union cvmx_pcieepx_cfg012 {
uint32_t u32;
- struct cvmx_pcieepx_cfg012_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg012_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t eraddr : 16; /**< Expansion ROM Address */
uint32_t reserved_1_15 : 15;
uint32_t er_en : 1; /**< Expansion ROM Enable */
@@ -1759,8 +2105,13 @@ union cvmx_pcieepx_cfg012
struct cvmx_pcieepx_cfg012_s cn52xxp1;
struct cvmx_pcieepx_cfg012_s cn56xx;
struct cvmx_pcieepx_cfg012_s cn56xxp1;
+ struct cvmx_pcieepx_cfg012_s cn61xx;
struct cvmx_pcieepx_cfg012_s cn63xx;
struct cvmx_pcieepx_cfg012_s cn63xxp1;
+ struct cvmx_pcieepx_cfg012_s cn66xx;
+ struct cvmx_pcieepx_cfg012_s cn68xx;
+ struct cvmx_pcieepx_cfg012_s cn68xxp1;
+ struct cvmx_pcieepx_cfg012_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t;
@@ -1771,12 +2122,10 @@ typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t;
* The ROM Mask register is invisible to host software and not readable from the application.
* The ROM Mask register is only writable through PEM(0..1)_CFG_WR.
*/
-union cvmx_pcieepx_cfg012_mask
-{
+union cvmx_pcieepx_cfg012_mask {
uint32_t u32;
- struct cvmx_pcieepx_cfg012_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg012_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t mask : 31; /**< Bar Mask Low NS */
uint32_t enb : 1; /**< Bar Enable NS
o 0: BAR ROM is disabled
@@ -1794,8 +2143,13 @@ union cvmx_pcieepx_cfg012_mask
struct cvmx_pcieepx_cfg012_mask_s cn52xxp1;
struct cvmx_pcieepx_cfg012_mask_s cn56xx;
struct cvmx_pcieepx_cfg012_mask_s cn56xxp1;
+ struct cvmx_pcieepx_cfg012_mask_s cn61xx;
struct cvmx_pcieepx_cfg012_mask_s cn63xx;
struct cvmx_pcieepx_cfg012_mask_s cn63xxp1;
+ struct cvmx_pcieepx_cfg012_mask_s cn66xx;
+ struct cvmx_pcieepx_cfg012_mask_s cn68xx;
+ struct cvmx_pcieepx_cfg012_mask_s cn68xxp1;
+ struct cvmx_pcieepx_cfg012_mask_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t;
@@ -1805,12 +2159,10 @@ typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t;
* PCIE_CFG013 = Fourteenth 32-bits of PCIE type 0 config space (Capability Pointer Register)
*
*/
-union cvmx_pcieepx_cfg013
-{
+union cvmx_pcieepx_cfg013 {
uint32_t u32;
- struct cvmx_pcieepx_cfg013_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg013_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_8_31 : 24;
uint32_t cp : 8; /**< First Capability Pointer.
Points to Power Management Capability structure by
@@ -1825,8 +2177,13 @@ union cvmx_pcieepx_cfg013
struct cvmx_pcieepx_cfg013_s cn52xxp1;
struct cvmx_pcieepx_cfg013_s cn56xx;
struct cvmx_pcieepx_cfg013_s cn56xxp1;
+ struct cvmx_pcieepx_cfg013_s cn61xx;
struct cvmx_pcieepx_cfg013_s cn63xx;
struct cvmx_pcieepx_cfg013_s cn63xxp1;
+ struct cvmx_pcieepx_cfg013_s cn66xx;
+ struct cvmx_pcieepx_cfg013_s cn68xx;
+ struct cvmx_pcieepx_cfg013_s cn68xxp1;
+ struct cvmx_pcieepx_cfg013_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t;
@@ -1836,12 +2193,10 @@ typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t;
* PCIE_CFG015 = Sixteenth 32-bits of PCIE type 0 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
*
*/
-union cvmx_pcieepx_cfg015
-{
+union cvmx_pcieepx_cfg015 {
uint32_t u32;
- struct cvmx_pcieepx_cfg015_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg015_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ml : 8; /**< Maximum Latency (Hardwired to 0) */
uint32_t mg : 8; /**< Minimum Grant (Hardwired to 0) */
uint32_t inta : 8; /**< Interrupt Pin
@@ -1862,8 +2217,13 @@ union cvmx_pcieepx_cfg015
struct cvmx_pcieepx_cfg015_s cn52xxp1;
struct cvmx_pcieepx_cfg015_s cn56xx;
struct cvmx_pcieepx_cfg015_s cn56xxp1;
+ struct cvmx_pcieepx_cfg015_s cn61xx;
struct cvmx_pcieepx_cfg015_s cn63xx;
struct cvmx_pcieepx_cfg015_s cn63xxp1;
+ struct cvmx_pcieepx_cfg015_s cn66xx;
+ struct cvmx_pcieepx_cfg015_s cn68xx;
+ struct cvmx_pcieepx_cfg015_s cn68xxp1;
+ struct cvmx_pcieepx_cfg015_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t;
@@ -1875,12 +2235,10 @@ typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t;
* Power Management Next Item Pointer/
* Power Management Capabilities Register)
*/
-union cvmx_pcieepx_cfg016
-{
+union cvmx_pcieepx_cfg016 {
uint32_t u32;
- struct cvmx_pcieepx_cfg016_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg016_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pmes : 5; /**< PME_Support
o Bit 11: If set, PME Messages can be generated from D0
o Bit 12: If set, PME Messages can be generated from D1
@@ -1923,8 +2281,13 @@ union cvmx_pcieepx_cfg016
struct cvmx_pcieepx_cfg016_s cn52xxp1;
struct cvmx_pcieepx_cfg016_s cn56xx;
struct cvmx_pcieepx_cfg016_s cn56xxp1;
+ struct cvmx_pcieepx_cfg016_s cn61xx;
struct cvmx_pcieepx_cfg016_s cn63xx;
struct cvmx_pcieepx_cfg016_s cn63xxp1;
+ struct cvmx_pcieepx_cfg016_s cn66xx;
+ struct cvmx_pcieepx_cfg016_s cn68xx;
+ struct cvmx_pcieepx_cfg016_s cn68xxp1;
+ struct cvmx_pcieepx_cfg016_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t;
@@ -1934,12 +2297,10 @@ typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t;
* PCIE_CFG017 = Eighteenth 32-bits of PCIE type 0 config space (Power Management Control and Status Register)
*
*/
-union cvmx_pcieepx_cfg017
-{
+union cvmx_pcieepx_cfg017 {
uint32_t u32;
- struct cvmx_pcieepx_cfg017_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg017_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pmdia : 8; /**< Data register for additional information (not supported) */
uint32_t bpccee : 1; /**< Bus Power/Clock Control Enable, hardwired to 0 */
uint32_t bd3h : 1; /**< B2/B3 Support, hardwired to 0 */
@@ -1982,8 +2343,13 @@ union cvmx_pcieepx_cfg017
struct cvmx_pcieepx_cfg017_s cn52xxp1;
struct cvmx_pcieepx_cfg017_s cn56xx;
struct cvmx_pcieepx_cfg017_s cn56xxp1;
+ struct cvmx_pcieepx_cfg017_s cn61xx;
struct cvmx_pcieepx_cfg017_s cn63xx;
struct cvmx_pcieepx_cfg017_s cn63xxp1;
+ struct cvmx_pcieepx_cfg017_s cn66xx;
+ struct cvmx_pcieepx_cfg017_s cn68xx;
+ struct cvmx_pcieepx_cfg017_s cn68xxp1;
+ struct cvmx_pcieepx_cfg017_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t;
@@ -1995,13 +2361,12 @@ typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t;
* MSI Next Item Pointer/
* MSI Control Register)
*/
-union cvmx_pcieepx_cfg020
-{
+union cvmx_pcieepx_cfg020 {
uint32_t u32;
- struct cvmx_pcieepx_cfg020_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint32_t reserved_24_31 : 8;
+ struct cvmx_pcieepx_cfg020_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t pvm : 1; /**< Per-vector masking capable */
uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR
However, the application must not change this field. */
uint32_t mme : 3; /**< Multiple Message Enabled
@@ -2024,15 +2389,48 @@ union cvmx_pcieepx_cfg020
uint32_t mmc : 3;
uint32_t mme : 3;
uint32_t m64 : 1;
- uint32_t reserved_24_31 : 8;
+ uint32_t pvm : 1;
+ uint32_t reserved_25_31 : 7;
#endif
} s;
- struct cvmx_pcieepx_cfg020_s cn52xx;
- struct cvmx_pcieepx_cfg020_s cn52xxp1;
- struct cvmx_pcieepx_cfg020_s cn56xx;
- struct cvmx_pcieepx_cfg020_s cn56xxp1;
- struct cvmx_pcieepx_cfg020_s cn63xx;
- struct cvmx_pcieepx_cfg020_s cn63xxp1;
+ struct cvmx_pcieepx_cfg020_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_24_31 : 8;
+ uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PESC(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t mme : 3; /**< Multiple Message Enabled
+ Indicates that multiple Message mode is enabled by system
+ software. The number of Messages enabled must be less than
+ or equal to the Multiple Message Capable value. */
+ uint32_t mmc : 3; /**< Multiple Message Capable, writable through PESC(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t msien : 1; /**< MSI Enabled
+ When set, INTx must be disabled. */
+ uint32_t ncp : 8; /**< Next Capability Pointer
+ Points to PCI Express Capabilities by default,
+ writable through PESC(0..1)_CFG_WR.
+ However, the application must not change this field. */
+ uint32_t msicid : 8; /**< MSI Capability ID */
+#else
+ uint32_t msicid : 8;
+ uint32_t ncp : 8;
+ uint32_t msien : 1;
+ uint32_t mmc : 3;
+ uint32_t mme : 3;
+ uint32_t m64 : 1;
+ uint32_t reserved_24_31 : 8;
+#endif
+ } cn52xx;
+ struct cvmx_pcieepx_cfg020_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg020_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg020_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg020_s cn61xx;
+ struct cvmx_pcieepx_cfg020_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg020_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg020_s cn66xx;
+ struct cvmx_pcieepx_cfg020_s cn68xx;
+ struct cvmx_pcieepx_cfg020_s cn68xxp1;
+ struct cvmx_pcieepx_cfg020_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t;
@@ -2042,12 +2440,10 @@ typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t;
* PCIE_CFG021 = Twenty-second 32-bits of PCIE type 0 config space (MSI Lower 32 Bits Address Register)
*
*/
-union cvmx_pcieepx_cfg021
-{
+union cvmx_pcieepx_cfg021 {
uint32_t u32;
- struct cvmx_pcieepx_cfg021_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg021_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lmsi : 30; /**< Lower 32-bit Address */
uint32_t reserved_0_1 : 2;
#else
@@ -2059,8 +2455,13 @@ union cvmx_pcieepx_cfg021
struct cvmx_pcieepx_cfg021_s cn52xxp1;
struct cvmx_pcieepx_cfg021_s cn56xx;
struct cvmx_pcieepx_cfg021_s cn56xxp1;
+ struct cvmx_pcieepx_cfg021_s cn61xx;
struct cvmx_pcieepx_cfg021_s cn63xx;
struct cvmx_pcieepx_cfg021_s cn63xxp1;
+ struct cvmx_pcieepx_cfg021_s cn66xx;
+ struct cvmx_pcieepx_cfg021_s cn68xx;
+ struct cvmx_pcieepx_cfg021_s cn68xxp1;
+ struct cvmx_pcieepx_cfg021_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t;
@@ -2070,12 +2471,10 @@ typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t;
* PCIE_CFG022 = Twenty-third 32-bits of PCIE type 0 config space (MSI Upper 32 bits Address Register)
*
*/
-union cvmx_pcieepx_cfg022
-{
+union cvmx_pcieepx_cfg022 {
uint32_t u32;
- struct cvmx_pcieepx_cfg022_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg022_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t umsi : 32; /**< Upper 32-bit Address */
#else
uint32_t umsi : 32;
@@ -2085,8 +2484,13 @@ union cvmx_pcieepx_cfg022
struct cvmx_pcieepx_cfg022_s cn52xxp1;
struct cvmx_pcieepx_cfg022_s cn56xx;
struct cvmx_pcieepx_cfg022_s cn56xxp1;
+ struct cvmx_pcieepx_cfg022_s cn61xx;
struct cvmx_pcieepx_cfg022_s cn63xx;
struct cvmx_pcieepx_cfg022_s cn63xxp1;
+ struct cvmx_pcieepx_cfg022_s cn66xx;
+ struct cvmx_pcieepx_cfg022_s cn68xx;
+ struct cvmx_pcieepx_cfg022_s cn68xxp1;
+ struct cvmx_pcieepx_cfg022_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t;
@@ -2096,12 +2500,10 @@ typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t;
* PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 0 config space (MSI Data Register)
*
*/
-union cvmx_pcieepx_cfg023
-{
+union cvmx_pcieepx_cfg023 {
uint32_t u32;
- struct cvmx_pcieepx_cfg023_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg023_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_16_31 : 16;
uint32_t msimd : 16; /**< MSI Data
Pattern assigned by system software, bits [4:0] are Or-ed with
@@ -2115,8 +2517,13 @@ union cvmx_pcieepx_cfg023
struct cvmx_pcieepx_cfg023_s cn52xxp1;
struct cvmx_pcieepx_cfg023_s cn56xx;
struct cvmx_pcieepx_cfg023_s cn56xxp1;
+ struct cvmx_pcieepx_cfg023_s cn61xx;
struct cvmx_pcieepx_cfg023_s cn63xx;
struct cvmx_pcieepx_cfg023_s cn63xxp1;
+ struct cvmx_pcieepx_cfg023_s cn66xx;
+ struct cvmx_pcieepx_cfg023_s cn68xx;
+ struct cvmx_pcieepx_cfg023_s cn68xxp1;
+ struct cvmx_pcieepx_cfg023_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t;
@@ -2127,12 +2534,10 @@ typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t;
* (PCI Express Capabilities List Register/
* PCI Express Capabilities Register)
*/
-union cvmx_pcieepx_cfg028
-{
+union cvmx_pcieepx_cfg028 {
uint32_t u32;
- struct cvmx_pcieepx_cfg028_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg028_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_30_31 : 2;
uint32_t imn : 5; /**< Interrupt Message Number
Updated by hardware, writable through PEM(0..1)_CFG_WR.
@@ -2145,7 +2550,7 @@ union cvmx_pcieepx_cfg028
uint32_t dpt : 4; /**< Device Port Type */
uint32_t pciecv : 4; /**< PCI Express Capability Version */
uint32_t ncp : 8; /**< Next Capability Pointer
- Writable through PEM(0..1)_CFG_WR.
+ writable through PEM(0..1)_CFG_WR.
However, the application must not change this field. */
uint32_t pcieid : 8; /**< PCIE Capability ID */
#else
@@ -2162,8 +2567,13 @@ union cvmx_pcieepx_cfg028
struct cvmx_pcieepx_cfg028_s cn52xxp1;
struct cvmx_pcieepx_cfg028_s cn56xx;
struct cvmx_pcieepx_cfg028_s cn56xxp1;
+ struct cvmx_pcieepx_cfg028_s cn61xx;
struct cvmx_pcieepx_cfg028_s cn63xx;
struct cvmx_pcieepx_cfg028_s cn63xxp1;
+ struct cvmx_pcieepx_cfg028_s cn66xx;
+ struct cvmx_pcieepx_cfg028_s cn68xx;
+ struct cvmx_pcieepx_cfg028_s cn68xxp1;
+ struct cvmx_pcieepx_cfg028_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t;
@@ -2173,12 +2583,10 @@ typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t;
* PCIE_CFG029 = Thirtieth 32-bits of PCIE type 0 config space (Device Capabilities Register)
*
*/
-union cvmx_pcieepx_cfg029
-{
+union cvmx_pcieepx_cfg029 {
uint32_t u32;
- struct cvmx_pcieepx_cfg029_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg029_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_28_31 : 4;
uint32_t cspls : 2; /**< Captured Slot Power Limit Scale
From Message from RC, upstream port only. */
@@ -2221,8 +2629,97 @@ union cvmx_pcieepx_cfg029
struct cvmx_pcieepx_cfg029_s cn52xxp1;
struct cvmx_pcieepx_cfg029_s cn56xx;
struct cvmx_pcieepx_cfg029_s cn56xxp1;
+ struct cvmx_pcieepx_cfg029_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_29_31 : 3;
+ uint32_t flr_cap : 1; /**< Function Level Reset Capable
+ not supported */
+ uint32_t cspls : 2; /**< Captured Slot Power Limit Scale
+ From Message from RC, upstream port only. */
+ uint32_t csplv : 8; /**< Captured Slot Power Limit Value
+ From Message from RC, upstream port only. */
+ uint32_t reserved_16_17 : 2;
+ uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t reserved_12_14 : 3;
+ uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t etfs : 1; /**< Extended Tag Field Supported
+ This bit is writable through PEM(0..1)_CFG_WR.
+ However, the application
+ must not write a 1 to this bit. */
+ uint32_t pfs : 2; /**< Phantom Function Supported
+ This field is writable through PEM(0..1)_CFG_WR.
+ However, Phantom
+ Function is not supported. Therefore, the application must not
+ write any value other than 0x0 to this field. */
+ uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR
+ However, the application must not change this field. */
+#else
+ uint32_t mpss : 3;
+ uint32_t pfs : 2;
+ uint32_t etfs : 1;
+ uint32_t el0al : 3;
+ uint32_t el1al : 3;
+ uint32_t reserved_12_14 : 3;
+ uint32_t rber : 1;
+ uint32_t reserved_16_17 : 2;
+ uint32_t csplv : 8;
+ uint32_t cspls : 2;
+ uint32_t flr_cap : 1;
+ uint32_t reserved_29_31 : 3;
+#endif
+ } cn61xx;
struct cvmx_pcieepx_cfg029_s cn63xx;
struct cvmx_pcieepx_cfg029_s cn63xxp1;
+ struct cvmx_pcieepx_cfg029_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_29_31 : 3;
+ uint32_t flr : 1; /**< Function Level Reset Capability
+ When set, core support of SR-IOV */
+ uint32_t cspls : 2; /**< Captured Slot Power Limit Scale
+ From Message from RC, upstream port only. */
+ uint32_t csplv : 8; /**< Captured Slot Power Limit Value
+ From Message from RC, upstream port only. */
+ uint32_t reserved_16_17 : 2;
+ uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t reserved_12_14 : 3;
+ uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t etfs : 1; /**< Extended Tag Field Supported
+ This bit is writable through PEM(0..1)_CFG_WR.
+ However, the application
+ must not write a 1 to this bit. */
+ uint32_t pfs : 2; /**< Phantom Function Supported
+ This field is writable through PEM(0..1)_CFG_WR.
+ However, Phantom
+ Function is not supported. Therefore, the application must not
+ write any value other than 0x0 to this field. */
+ uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR
+ However, the application must not change this field. */
+#else
+ uint32_t mpss : 3;
+ uint32_t pfs : 2;
+ uint32_t etfs : 1;
+ uint32_t el0al : 3;
+ uint32_t el1al : 3;
+ uint32_t reserved_12_14 : 3;
+ uint32_t rber : 1;
+ uint32_t reserved_16_17 : 2;
+ uint32_t csplv : 8;
+ uint32_t cspls : 2;
+ uint32_t flr : 1;
+ uint32_t reserved_29_31 : 3;
+#endif
+ } cn66xx;
+ struct cvmx_pcieepx_cfg029_cn66xx cn68xx;
+ struct cvmx_pcieepx_cfg029_cn66xx cn68xxp1;
+ struct cvmx_pcieepx_cfg029_cn61xx cnf71xx;
};
typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t;
@@ -2232,12 +2729,10 @@ typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t;
* PCIE_CFG030 = Thirty-first 32-bits of PCIE type 0 config space
* (Device Control Register/Device Status Register)
*/
-union cvmx_pcieepx_cfg030
-{
+union cvmx_pcieepx_cfg030 {
uint32_t u32;
- struct cvmx_pcieepx_cfg030_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg030_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_22_31 : 10;
uint32_t tp : 1; /**< Transaction Pending
Set to 1 when Non-Posted Requests are not yet completed
@@ -2273,7 +2768,8 @@ union cvmx_pcieepx_cfg030
set to Nonfatal and meets the Advisory Nonfatal criteria,
which most ECRC errors
should be. */
- uint32_t reserved_15_15 : 1;
+ uint32_t i_flr : 1; /**< Initiate Function Level Reset
+ (Not Supported) */
uint32_t mrrs : 3; /**< Max Read Request Size
0 = 128B
1 = 256B
@@ -2300,6 +2796,97 @@ union cvmx_pcieepx_cfg030
Larger sizes not supported by OCTEON.
Note: DPI_SLI_PRT#_CFG[MPS] must be set to the same
value for proper functionality. */
+ uint32_t ro_en : 1; /**< Enable Relaxed Ordering
+ This bit is not used. */
+ uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */
+ uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */
+ uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */
+ uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */
+#else
+ uint32_t ce_en : 1;
+ uint32_t nfe_en : 1;
+ uint32_t fe_en : 1;
+ uint32_t ur_en : 1;
+ uint32_t ro_en : 1;
+ uint32_t mps : 3;
+ uint32_t etf_en : 1;
+ uint32_t pf_en : 1;
+ uint32_t ap_en : 1;
+ uint32_t ns_en : 1;
+ uint32_t mrrs : 3;
+ uint32_t i_flr : 1;
+ uint32_t ce_d : 1;
+ uint32_t nfe_d : 1;
+ uint32_t fe_d : 1;
+ uint32_t ur_d : 1;
+ uint32_t ap_d : 1;
+ uint32_t tp : 1;
+ uint32_t reserved_22_31 : 10;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg030_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_22_31 : 10;
+ uint32_t tp : 1; /**< Transaction Pending
+ Set to 1 when Non-Posted Requests are not yet completed
+ and clear when they are completed. */
+ uint32_t ap_d : 1; /**< Aux Power Detected
+ Set to 1 if Aux power detected. */
+ uint32_t ur_d : 1; /**< Unsupported Request Detected
+ Errors are logged in this register regardless of whether
+ error reporting is enabled in the Device Control register.
+ UR_D occurs when we receive something we don't support.
+ Unsupported requests are Nonfatal errors, so UR_D should
+ cause NFE_D. Receiving a vendor defined message should
+ cause an unsupported request. */
+ uint32_t fe_d : 1; /**< Fatal Error Detected
+ Errors are logged in this register regardless of whether
+ error reporting is enabled in the Device Control register.
+ FE_D is set if receive any of the errors in PCIE_CFG066 that
+ has a severity set to Fatal. Malformed TLP's generally fit
+ into this category. */
+ uint32_t nfe_d : 1; /**< Non-Fatal Error detected
+ Errors are logged in this register regardless of whether
+ error reporting is enabled in the Device Control register.
+ NFE_D is set if we receive any of the errors in PCIE_CFG066
+ that has a severity set to Nonfatal and does NOT meet Advisory
+ Nonfatal criteria (PCIe 1.1 spec, Section 6.2.3.2.4), which
+ most poisoned TLP's should be. */
+ uint32_t ce_d : 1; /**< Correctable Error Detected
+ Errors are logged in this register regardless of whether
+ error reporting is enabled in the Device Control register.
+ CE_D is set if we receive any of the errors in PCIE_CFG068
+ for example a Replay Timer Timeout. Also, it can be set if
+ we get any of the errors in PCIE_CFG066 that has a severity
+ set to Nonfatal and meets the Advisory Nonfatal criteria
+ (PCIe 1.1 spec, Section 6.2.3.2.4), which most ECRC errors
+ should be. */
+ uint32_t reserved_15_15 : 1;
+ uint32_t mrrs : 3; /**< Max Read Request Size
+ 0 = 128B
+ 1 = 256B
+ 2 = 512B
+ 3 = 1024B
+ 4 = 2048B
+ 5 = 4096B
+ Note: NPEI_CTL_STATUS2[MRRS] also must be set properly.
+ NPEI_CTL_STATUS2[MRRS] must not exceed the
+ desired max read request size. */
+ uint32_t ns_en : 1; /**< Enable No Snoop */
+ uint32_t ap_en : 1; /**< AUX Power PM Enable */
+ uint32_t pf_en : 1; /**< Phantom Function Enable
+ This bit should never be set - OCTEON requests never use
+ phantom functions. */
+ uint32_t etf_en : 1; /**< Extended Tag Field Enable
+ This bit should never be set - OCTEON requests never use
+ extended tags. */
+ uint32_t mps : 3; /**< Max Payload Size
+ Legal values:
+ 0 = 128B
+ 1 = 256B
+ Larger sizes not supported by OCTEON.
+ Note: NPEI_CTL_STATUS2[MPS] must be set to the same
+ value for proper functionality. */
uint32_t ro_en : 1; /**< Enable Relaxed Ordering */
uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */
uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */
@@ -2326,13 +2913,17 @@ union cvmx_pcieepx_cfg030
uint32_t tp : 1;
uint32_t reserved_22_31 : 10;
#endif
- } s;
- struct cvmx_pcieepx_cfg030_s cn52xx;
- struct cvmx_pcieepx_cfg030_s cn52xxp1;
- struct cvmx_pcieepx_cfg030_s cn56xx;
- struct cvmx_pcieepx_cfg030_s cn56xxp1;
- struct cvmx_pcieepx_cfg030_s cn63xx;
- struct cvmx_pcieepx_cfg030_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg030_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg030_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg030_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg030_s cn61xx;
+ struct cvmx_pcieepx_cfg030_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg030_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg030_s cn66xx;
+ struct cvmx_pcieepx_cfg030_s cn68xx;
+ struct cvmx_pcieepx_cfg030_s cn68xxp1;
+ struct cvmx_pcieepx_cfg030_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t;
@@ -2342,16 +2933,17 @@ typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t;
* PCIE_CFG031 = Thirty-second 32-bits of PCIE type 0 config space
* (Link Capabilities Register)
*/
-union cvmx_pcieepx_cfg031
-{
+union cvmx_pcieepx_cfg031 {
uint32_t u32;
- struct cvmx_pcieepx_cfg031_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint32_t pnum : 8; /**< Port Number, writable through PEM(0..1)_CFG_WR
- However, the application must not change this field. */
- uint32_t reserved_22_23 : 2;
- uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */
+ struct cvmx_pcieepx_cfg031_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t pnum : 8; /**< Port Number
+ writable through PEM(0..1)_CFG_WR, however the application
+ must not change this field. */
+ uint32_t reserved_23_23 : 1;
+ uint32_t aspm : 1; /**< ASPM Optionality Compliance */
+ uint32_t lbnc : 1; /**< Link Bandwidth Notification Capability
+ Set 0 for Endpoint devices. */
uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable */
uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable
Not supported, hardwired to 0x0. */
@@ -2373,11 +2965,14 @@ union cvmx_pcieepx_cfg031
However, the application must not change this field. */
uint32_t mlw : 6; /**< Maximum Link Width
The default value is the value you specify during hardware
- configuration (x1, x4, x8, or x16), writable through PEM(0..1)_CFG_WR. */
+ configuration (x1), writable through PEM(0..1)_CFG_WR
+ however wider cofigurations are not supported. */
uint32_t mls : 4; /**< Maximum Link Speed
- The following values are accepted:
- 0001b: 2.5 GHz supported
- 0010b: 5.0 GHz and 2.5 GHz supported
+ The reset value of this field is controlled by a value sent from
+ the lsb of the MIO_QLM#_SPD register.
+ qlm#_spd[1] RST_VALUE NOTE
+ 1 0001b 2.5 GHz supported
+ 0 0010b 5.0 GHz and 2.5 GHz supported
This field is writable through PEM(0..1)_CFG_WR.
However, the application must not change this field. */
#else
@@ -2390,16 +2985,71 @@ union cvmx_pcieepx_cfg031
uint32_t sderc : 1;
uint32_t dllarc : 1;
uint32_t lbnc : 1;
- uint32_t reserved_22_23 : 2;
+ uint32_t aspm : 1;
+ uint32_t reserved_23_23 : 1;
uint32_t pnum : 8;
#endif
} s;
- struct cvmx_pcieepx_cfg031_s cn52xx;
- struct cvmx_pcieepx_cfg031_s cn52xxp1;
- struct cvmx_pcieepx_cfg031_s cn56xx;
- struct cvmx_pcieepx_cfg031_s cn56xxp1;
- struct cvmx_pcieepx_cfg031_s cn63xx;
- struct cvmx_pcieepx_cfg031_s cn63xxp1;
+ struct cvmx_pcieepx_cfg031_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t pnum : 8; /**< Port Number, writable through PESC(0..1)_CFG_WR
+ However, the application must not change this field. */
+ uint32_t reserved_22_23 : 2;
+ uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */
+ uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable */
+ uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable
+ Not supported, hardwired to 0x0. */
+ uint32_t cpm : 1; /**< Clock Power Management
+ The default value is the value you specify during hardware
+ configuration, writable through PESC(0..1)_CFG_WR.
+ However, the application must not change this field. */
+ uint32_t l1el : 3; /**< L1 Exit Latency
+ The default value is the value you specify during hardware
+ configuration, writable through PESC(0..1)_CFG_WR.
+ However, the application must not change this field. */
+ uint32_t l0el : 3; /**< L0s Exit Latency
+ The default value is the value you specify during hardware
+ configuration, writable through PESC(0..1)_CFG_WR.
+ However, the application must not change this field. */
+ uint32_t aslpms : 2; /**< Active State Link PM Support
+ The default value is the value you specify during hardware
+ configuration, writable through PESC(0..1)_CFG_WR.
+ However, the application must not change this field. */
+ uint32_t mlw : 6; /**< Maximum Link Width
+ The default value is the value you specify during hardware
+ configuration (x1, x2, x4, x8, or x16), writable through PESC(0..1)_CFG_WR.
+ This value will be set to 0x4 or 0x2 depending on the max
+ number of lanes (QLM_CFG == 0 set to 0x2 else 0x4). */
+ uint32_t mls : 4; /**< Maximum Link Speed
+ Default value is 0x1 for 2.5 Gbps Link.
+ This field is writable through PESC(0..1)_CFG_WR.
+ However, 0x1 is the
+ only supported value. Therefore, the application must not write
+ any value other than 0x1 to this field. */
+#else
+ uint32_t mls : 4;
+ uint32_t mlw : 6;
+ uint32_t aslpms : 2;
+ uint32_t l0el : 3;
+ uint32_t l1el : 3;
+ uint32_t cpm : 1;
+ uint32_t sderc : 1;
+ uint32_t dllarc : 1;
+ uint32_t lbnc : 1;
+ uint32_t reserved_22_23 : 2;
+ uint32_t pnum : 8;
+#endif
+ } cn52xx;
+ struct cvmx_pcieepx_cfg031_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg031_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg031_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg031_s cn61xx;
+ struct cvmx_pcieepx_cfg031_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg031_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg031_s cn66xx;
+ struct cvmx_pcieepx_cfg031_s cn68xx;
+ struct cvmx_pcieepx_cfg031_cn52xx cn68xxp1;
+ struct cvmx_pcieepx_cfg031_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t;
@@ -2409,13 +3059,12 @@ typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t;
* PCIE_CFG032 = Thirty-third 32-bits of PCIE type 0 config space
* (Link Control Register/Link Status Register)
*/
-union cvmx_pcieepx_cfg032
-{
+union cvmx_pcieepx_cfg032 {
uint32_t u32;
- struct cvmx_pcieepx_cfg032_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint32_t reserved_30_31 : 2;
+ struct cvmx_pcieepx_cfg032_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t lab : 1; /**< Link Autonomous Bandwidth Status */
+ uint32_t lbm : 1; /**< Link Bandwidth Management Status */
uint32_t dlla : 1; /**< Data Link Layer Active
Not applicable for an upstream Port or Endpoint device,
hardwired to 0. */
@@ -2429,6 +3078,72 @@ union cvmx_pcieepx_cfg032
hardwired to 0. */
uint32_t reserved_26_26 : 1;
uint32_t nlw : 6; /**< Negotiated Link Width
+ Set automatically by hardware after Link initialization.
+ Value is undefined when link is not up. */
+ uint32_t ls : 4; /**< Link Speed
+ 1 == The negotiated Link speed: 2.5 Gbps
+ 2 == The negotiated Link speed: 5.0 Gbps
+ 4 == The negotiated Link speed: 8.0 Gbps (Not Supported) */
+ uint32_t reserved_12_15 : 4;
+ uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable
+ This bit is not applicable and is reserved for endpoints */
+ uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable
+ This bit is not applicable and is reserved for endpoints */
+ uint32_t hawd : 1; /**< Hardware Autonomous Width Disable
+ (Not Supported) */
+ uint32_t ecpm : 1; /**< Enable Clock Power Management
+ Hardwired to 0 if Clock Power Management is disabled in
+ the Link Capabilities register. */
+ uint32_t es : 1; /**< Extended Synch */
+ uint32_t ccc : 1; /**< Common Clock Configuration */
+ uint32_t rl : 1; /**< Retrain Link
+ Not applicable for an upstream Port or Endpoint device,
+ hardwired to 0. */
+ uint32_t ld : 1; /**< Link Disable
+ Not applicable for an upstream Port or Endpoint device,
+ hardwired to 0. */
+ uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */
+ uint32_t reserved_2_2 : 1;
+ uint32_t aslpc : 2; /**< Active State Link PM Control */
+#else
+ uint32_t aslpc : 2;
+ uint32_t reserved_2_2 : 1;
+ uint32_t rcb : 1;
+ uint32_t ld : 1;
+ uint32_t rl : 1;
+ uint32_t ccc : 1;
+ uint32_t es : 1;
+ uint32_t ecpm : 1;
+ uint32_t hawd : 1;
+ uint32_t lbm_int_enb : 1;
+ uint32_t lab_int_enb : 1;
+ uint32_t reserved_12_15 : 4;
+ uint32_t ls : 4;
+ uint32_t nlw : 6;
+ uint32_t reserved_26_26 : 1;
+ uint32_t lt : 1;
+ uint32_t scc : 1;
+ uint32_t dlla : 1;
+ uint32_t lbm : 1;
+ uint32_t lab : 1;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg032_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_30_31 : 2;
+ uint32_t dlla : 1; /**< Data Link Layer Active
+ Not applicable for an upstream Port or Endpoint device,
+ hardwired to 0. */
+ uint32_t scc : 1; /**< Slot Clock Configuration
+ Indicates that the component uses the same physical reference
+ clock that the platform provides on the connector.
+ Writable through PESC(0..1)_CFG_WR.
+ However, the application must not change this field. */
+ uint32_t lt : 1; /**< Link Training
+ Not applicable for an upstream Port or Endpoint device,
+ hardwired to 0. */
+ uint32_t reserved_26_26 : 1;
+ uint32_t nlw : 6; /**< Negotiated Link Width
Set automatically by hardware after Link initialization. */
uint32_t ls : 4; /**< Link Speed
The negotiated Link speed: 2.5 Gbps */
@@ -2468,13 +3183,80 @@ union cvmx_pcieepx_cfg032
uint32_t dlla : 1;
uint32_t reserved_30_31 : 2;
#endif
- } s;
- struct cvmx_pcieepx_cfg032_s cn52xx;
- struct cvmx_pcieepx_cfg032_s cn52xxp1;
- struct cvmx_pcieepx_cfg032_s cn56xx;
- struct cvmx_pcieepx_cfg032_s cn56xxp1;
- struct cvmx_pcieepx_cfg032_s cn63xx;
- struct cvmx_pcieepx_cfg032_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg032_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg032_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg032_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg032_s cn61xx;
+ struct cvmx_pcieepx_cfg032_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg032_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg032_s cn66xx;
+ struct cvmx_pcieepx_cfg032_s cn68xx;
+ struct cvmx_pcieepx_cfg032_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_30_31 : 2;
+ uint32_t dlla : 1; /**< Data Link Layer Active
+ Not applicable for an upstream Port or Endpoint device,
+ hardwired to 0. */
+ uint32_t scc : 1; /**< Slot Clock Configuration
+ Indicates that the component uses the same physical reference
+ clock that the platform provides on the connector.
+ Writable through PEM(0..1)_CFG_WR.
+ However, the application must not change this field. */
+ uint32_t lt : 1; /**< Link Training
+ Not applicable for an upstream Port or Endpoint device,
+ hardwired to 0. */
+ uint32_t reserved_26_26 : 1;
+ uint32_t nlw : 6; /**< Negotiated Link Width
+ Set automatically by hardware after Link initialization. */
+ uint32_t ls : 4; /**< Link Speed
+ 1 == The negotiated Link speed: 2.5 Gbps
+ 2 == The negotiated Link speed: 5.0 Gbps
+ 4 == The negotiated Link speed: 8.0 Gbps (Not Supported) */
+ uint32_t reserved_12_15 : 4;
+ uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable
+ This bit is not applicable and is reserved for endpoints */
+ uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable
+ This bit is not applicable and is reserved for endpoints */
+ uint32_t hawd : 1; /**< Hardware Autonomous Width Disable
+ (Not Supported) */
+ uint32_t ecpm : 1; /**< Enable Clock Power Management
+ Hardwired to 0 if Clock Power Management is disabled in
+ the Link Capabilities register. */
+ uint32_t es : 1; /**< Extended Synch */
+ uint32_t ccc : 1; /**< Common Clock Configuration */
+ uint32_t rl : 1; /**< Retrain Link
+ Not applicable for an upstream Port or Endpoint device,
+ hardwired to 0. */
+ uint32_t ld : 1; /**< Link Disable
+ Not applicable for an upstream Port or Endpoint device,
+ hardwired to 0. */
+ uint32_t rcb : 1; /**< Read Completion Boundary (RCB) */
+ uint32_t reserved_2_2 : 1;
+ uint32_t aslpc : 2; /**< Active State Link PM Control */
+#else
+ uint32_t aslpc : 2;
+ uint32_t reserved_2_2 : 1;
+ uint32_t rcb : 1;
+ uint32_t ld : 1;
+ uint32_t rl : 1;
+ uint32_t ccc : 1;
+ uint32_t es : 1;
+ uint32_t ecpm : 1;
+ uint32_t hawd : 1;
+ uint32_t lbm_int_enb : 1;
+ uint32_t lab_int_enb : 1;
+ uint32_t reserved_12_15 : 4;
+ uint32_t ls : 4;
+ uint32_t nlw : 6;
+ uint32_t reserved_26_26 : 1;
+ uint32_t lt : 1;
+ uint32_t scc : 1;
+ uint32_t dlla : 1;
+ uint32_t reserved_30_31 : 2;
+#endif
+ } cn68xxp1;
+ struct cvmx_pcieepx_cfg032_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t;
@@ -2484,12 +3266,10 @@ typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t;
* PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space
* (Slot Capabilities Register)
*/
-union cvmx_pcieepx_cfg033
-{
+union cvmx_pcieepx_cfg033 {
uint32_t u32;
- struct cvmx_pcieepx_cfg033_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg033_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ps_num : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR
However, the application must not change this field. */
uint32_t nccs : 1; /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR
@@ -2544,12 +3324,10 @@ typedef union cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg033_t;
* PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space
* (Slot Control Register/Slot Status Register)
*/
-union cvmx_pcieepx_cfg034
-{
+union cvmx_pcieepx_cfg034 {
uint32_t u32;
- struct cvmx_pcieepx_cfg034_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg034_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_25_31 : 7;
uint32_t dlls_c : 1; /**< Data Link Layer State Changed
Not applicable for an upstream Port or Endpoint device,
@@ -2616,12 +3394,47 @@ typedef union cvmx_pcieepx_cfg034 cvmx_pcieepx_cfg034_t;
* PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 0 config space
* (Device Capabilities 2 Register)
*/
-union cvmx_pcieepx_cfg037
-{
+union cvmx_pcieepx_cfg037 {
uint32_t u32;
- struct cvmx_pcieepx_cfg037_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg037_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_20_31 : 12;
+ uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported
+ (Not Supported) */
+ uint32_t reserved_12_17 : 6;
+ uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported
+ (Not Supported) */
+ uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing
+ (This bit applies to RCs) */
+ uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom_ops : 1; /**< AtomicOp Routing Supported
+ (Not Applicable for EP) */
+ uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported
+ (Not Supported) */
+ uint32_t ctds : 1; /**< Completion Timeout Disable Supported */
+ uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */
+#else
+ uint32_t ctrs : 4;
+ uint32_t ctds : 1;
+ uint32_t ari : 1;
+ uint32_t atom_ops : 1;
+ uint32_t atom32s : 1;
+ uint32_t atom64s : 1;
+ uint32_t atom128s : 1;
+ uint32_t noroprpr : 1;
+ uint32_t ltrs : 1;
+ uint32_t reserved_12_17 : 6;
+ uint32_t obffs : 2;
+ uint32_t reserved_20_31 : 12;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg037_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_5_31 : 27;
uint32_t ctds : 1; /**< Completion Timeout Disable Supported */
uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported
@@ -2633,13 +3446,89 @@ union cvmx_pcieepx_cfg037
uint32_t ctds : 1;
uint32_t reserved_5_31 : 27;
#endif
- } s;
- struct cvmx_pcieepx_cfg037_s cn52xx;
- struct cvmx_pcieepx_cfg037_s cn52xxp1;
- struct cvmx_pcieepx_cfg037_s cn56xx;
- struct cvmx_pcieepx_cfg037_s cn56xxp1;
- struct cvmx_pcieepx_cfg037_s cn63xx;
- struct cvmx_pcieepx_cfg037_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg037_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg037_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg037_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg037_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_14_31 : 18;
+ uint32_t tph : 2; /**< TPH Completer Supported
+ (Not Supported) */
+ uint32_t reserved_11_11 : 1;
+ uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing
+ (This bit applies to RCs) */
+ uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom_ops : 1; /**< AtomicOp Routing Supported
+ (Not Applicable for EP) */
+ uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported
+ (Not Supported) */
+ uint32_t ctds : 1; /**< Completion Timeout Disable Supported */
+ uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */
+#else
+ uint32_t ctrs : 4;
+ uint32_t ctds : 1;
+ uint32_t ari : 1;
+ uint32_t atom_ops : 1;
+ uint32_t atom32s : 1;
+ uint32_t atom64s : 1;
+ uint32_t atom128s : 1;
+ uint32_t noroprpr : 1;
+ uint32_t reserved_11_11 : 1;
+ uint32_t tph : 2;
+ uint32_t reserved_14_31 : 18;
+#endif
+ } cn61xx;
+ struct cvmx_pcieepx_cfg037_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg037_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg037_cn61xx cn66xx;
+ struct cvmx_pcieepx_cfg037_cn61xx cn68xx;
+ struct cvmx_pcieepx_cfg037_cn61xx cn68xxp1;
+ struct cvmx_pcieepx_cfg037_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_20_31 : 12;
+ uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported
+ (Not Supported) */
+ uint32_t reserved_14_17 : 4;
+ uint32_t tphs : 2; /**< TPH Completer Supported
+ (Not Supported) */
+ uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported
+ (Not Supported) */
+ uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing
+ (This bit applies to RCs) */
+ uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported
+ (Not Supported) */
+ uint32_t atom_ops : 1; /**< AtomicOp Routing Supported
+ (Not Applicable for EP) */
+ uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported
+ (Not Supported) */
+ uint32_t ctds : 1; /**< Completion Timeout Disable Supported */
+ uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */
+#else
+ uint32_t ctrs : 4;
+ uint32_t ctds : 1;
+ uint32_t ari : 1;
+ uint32_t atom_ops : 1;
+ uint32_t atom32s : 1;
+ uint32_t atom64s : 1;
+ uint32_t atom128s : 1;
+ uint32_t noroprpr : 1;
+ uint32_t ltrs : 1;
+ uint32_t tphs : 2;
+ uint32_t reserved_14_17 : 4;
+ uint32_t obffs : 2;
+ uint32_t reserved_20_31 : 12;
+#endif
+ } cnf71xx;
};
typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t;
@@ -2649,12 +3538,46 @@ typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t;
* PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 0 config space
* (Device Control 2 Register/Device Status 2 Register)
*/
-union cvmx_pcieepx_cfg038
-{
+union cvmx_pcieepx_cfg038 {
uint32_t u32;
- struct cvmx_pcieepx_cfg038_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg038_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_15_31 : 17;
+ uint32_t obffe : 2; /**< Optimized Buffer Flush Fill (OBFF) Enable
+ (Not Supported) */
+ uint32_t reserved_11_12 : 2;
+ uint32_t ltre : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Enable
+ (Not Supported) */
+ uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable
+ (Not Supported) */
+ uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable
+ (Not Supported) */
+ uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking
+ (Not Supported)m */
+ uint32_t atom_op : 1; /**< AtomicOp Requester Enable
+ (Not Supported) */
+ uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported
+ (Not Supported) */
+ uint32_t ctd : 1; /**< Completion Timeout Disable */
+ uint32_t ctv : 4; /**< Completion Timeout Value
+ Completion Timeout Programming is not supported
+ Completion timeout is the range of 16 ms to 55 ms. */
+#else
+ uint32_t ctv : 4;
+ uint32_t ctd : 1;
+ uint32_t ari : 1;
+ uint32_t atom_op : 1;
+ uint32_t atom_op_eb : 1;
+ uint32_t id0_rq : 1;
+ uint32_t id0_cp : 1;
+ uint32_t ltre : 1;
+ uint32_t reserved_11_12 : 2;
+ uint32_t obffe : 2;
+ uint32_t reserved_15_31 : 17;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg038_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_5_31 : 27;
uint32_t ctd : 1; /**< Completion Timeout Disable */
uint32_t ctv : 4; /**< Completion Timeout Value
@@ -2665,13 +3588,44 @@ union cvmx_pcieepx_cfg038
uint32_t ctd : 1;
uint32_t reserved_5_31 : 27;
#endif
- } s;
- struct cvmx_pcieepx_cfg038_s cn52xx;
- struct cvmx_pcieepx_cfg038_s cn52xxp1;
- struct cvmx_pcieepx_cfg038_s cn56xx;
- struct cvmx_pcieepx_cfg038_s cn56xxp1;
- struct cvmx_pcieepx_cfg038_s cn63xx;
- struct cvmx_pcieepx_cfg038_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg038_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg038_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg038_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg038_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_10_31 : 22;
+ uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable
+ (Not Supported) */
+ uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable
+ (Not Supported) */
+ uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking
+ (Not Supported)m */
+ uint32_t atom_op : 1; /**< AtomicOp Requester Enable
+ (Not Supported) */
+ uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported
+ (Not Supported) */
+ uint32_t ctd : 1; /**< Completion Timeout Disable */
+ uint32_t ctv : 4; /**< Completion Timeout Value
+ Completion Timeout Programming is not supported
+ Completion timeout is the range of 16 ms to 55 ms. */
+#else
+ uint32_t ctv : 4;
+ uint32_t ctd : 1;
+ uint32_t ari : 1;
+ uint32_t atom_op : 1;
+ uint32_t atom_op_eb : 1;
+ uint32_t id0_rq : 1;
+ uint32_t id0_cp : 1;
+ uint32_t reserved_10_31 : 22;
+#endif
+ } cn61xx;
+ struct cvmx_pcieepx_cfg038_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg038_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg038_cn61xx cn66xx;
+ struct cvmx_pcieepx_cfg038_cn61xx cn68xx;
+ struct cvmx_pcieepx_cfg038_cn61xx cn68xxp1;
+ struct cvmx_pcieepx_cfg038_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t;
@@ -2681,23 +3635,52 @@ typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t;
* PCIE_CFG039 = Fourtieth 32-bits of PCIE type 0 config space
* (Link Capabilities 2 Register)
*/
-union cvmx_pcieepx_cfg039
-{
+union cvmx_pcieepx_cfg039 {
uint32_t u32;
- struct cvmx_pcieepx_cfg039_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg039_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_9_31 : 23;
+ uint32_t cls : 1; /**< Crosslink Supported */
+ uint32_t slsv : 7; /**< Supported Link Speeds Vector
+ Indicates the supported Link speeds of the associated Port.
+ For each bit, a value of 1b indicates that the cooresponding
+ Link speed is supported; otherwise, the Link speed is not
+ supported.
+ Bit definitions are:
+ Bit 1 2.5 GT/s
+ Bit 2 5.0 GT/s
+ Bit 3 8.0 GT/s (Not Supported)
+ Bits 7:4 reserved
+ The reset value of this field is controlled by a value sent from
+ the lsb of the MIO_QLM#_SPD register
+ qlm#_spd[0] RST_VALUE NOTE
+ 1 0001b 2.5 GHz supported
+ 0 0011b 5.0 GHz and 2.5 GHz supported */
+ uint32_t reserved_0_0 : 1;
+#else
+ uint32_t reserved_0_0 : 1;
+ uint32_t slsv : 7;
+ uint32_t cls : 1;
+ uint32_t reserved_9_31 : 23;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg039_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_0_31 : 32;
#else
uint32_t reserved_0_31 : 32;
#endif
- } s;
- struct cvmx_pcieepx_cfg039_s cn52xx;
- struct cvmx_pcieepx_cfg039_s cn52xxp1;
- struct cvmx_pcieepx_cfg039_s cn56xx;
- struct cvmx_pcieepx_cfg039_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg039_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg039_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg039_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg039_s cn61xx;
struct cvmx_pcieepx_cfg039_s cn63xx;
- struct cvmx_pcieepx_cfg039_s cn63xxp1;
+ struct cvmx_pcieepx_cfg039_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg039_s cn66xx;
+ struct cvmx_pcieepx_cfg039_s cn68xx;
+ struct cvmx_pcieepx_cfg039_s cn68xxp1;
+ struct cvmx_pcieepx_cfg039_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t;
@@ -2707,12 +3690,10 @@ typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t;
* PCIE_CFG040 = Fourty-first 32-bits of PCIE type 0 config space
* (Link Control 2 Register/Link Status 2 Register)
*/
-union cvmx_pcieepx_cfg040
-{
+union cvmx_pcieepx_cfg040 {
uint32_t u32;
- struct cvmx_pcieepx_cfg040_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg040_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_17_31 : 15;
uint32_t cdl : 1; /**< Current De-emphasis Level
When the Link is operating at 5 GT/s speed, this bit
@@ -2742,7 +3723,7 @@ union cvmx_pcieepx_cfg040
Compliance state. */
uint32_t tm : 3; /**< Transmit Margin
This field controls the value of the non-de-emphasized
- voltage level at the Transmitter pins:
+ voltage level at the Transmitter signals:
- 000: 800-1200 mV for full swing 400-600 mV for half-swing
- 001-010: values must be monotonic with a non-zero slope
- 011: 200-400 mV for full-swing and 100-200 mV for halfswing
@@ -2774,6 +3755,7 @@ union cvmx_pcieepx_cfg040
the upstream component in its training sequences:
- 0001: 2.5Gb/s Target Link Speed
- 0010: 5Gb/s Target Link Speed
+ - 0100: 8Gb/s Target Link Speed (Not Supported)
All other encodings are reserved.
If a value is written to this field that does not correspond to
a speed included in the Supported Link Speeds field, the
@@ -2782,8 +3764,11 @@ union cvmx_pcieepx_cfg040
used to set the target compliance mode speed when
software is using the Enter Compliance bit to force a link
into compliance mode.
- Out of reset this will have a value of 1 or 2 which is
- selected by qlmCfgx[1]. */
+ The reset value of this field is controlled by a value sent from
+ the lsb of the MIO_QLM#_SPD register.
+ qlm#_spd[0] RST_VALUE NOTE
+ 1 0001b 2.5 GHz supported
+ 0 0010b 5.0 GHz and 2.5 GHz supported */
#else
uint32_t tls : 4;
uint32_t ec : 1;
@@ -2798,9 +3783,8 @@ union cvmx_pcieepx_cfg040
uint32_t reserved_17_31 : 15;
#endif
} s;
- struct cvmx_pcieepx_cfg040_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg040_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_0_31 : 32;
#else
uint32_t reserved_0_31 : 32;
@@ -2809,8 +3793,13 @@ union cvmx_pcieepx_cfg040
struct cvmx_pcieepx_cfg040_cn52xx cn52xxp1;
struct cvmx_pcieepx_cfg040_cn52xx cn56xx;
struct cvmx_pcieepx_cfg040_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg040_s cn61xx;
struct cvmx_pcieepx_cfg040_s cn63xx;
struct cvmx_pcieepx_cfg040_s cn63xxp1;
+ struct cvmx_pcieepx_cfg040_s cn66xx;
+ struct cvmx_pcieepx_cfg040_s cn68xx;
+ struct cvmx_pcieepx_cfg040_s cn68xxp1;
+ struct cvmx_pcieepx_cfg040_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t;
@@ -2820,12 +3809,10 @@ typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t;
* PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space
* (Slot Capabilities 2 Register)
*/
-union cvmx_pcieepx_cfg041
-{
+union cvmx_pcieepx_cfg041 {
uint32_t u32;
- struct cvmx_pcieepx_cfg041_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg041_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_0_31 : 32;
#else
uint32_t reserved_0_31 : 32;
@@ -2846,12 +3833,10 @@ typedef union cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg041_t;
* PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space
* (Slot Control 2 Register/Slot Status 2 Register)
*/
-union cvmx_pcieepx_cfg042
-{
+union cvmx_pcieepx_cfg042 {
uint32_t u32;
- struct cvmx_pcieepx_cfg042_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg042_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_0_31 : 32;
#else
uint32_t reserved_0_31 : 32;
@@ -2870,14 +3855,12 @@ typedef union cvmx_pcieepx_cfg042 cvmx_pcieepx_cfg042_t;
* cvmx_pcieep#_cfg064
*
* PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 0 config space
- * (PCI Express Enhanced Capability Header)
+ * (PCI Express Extended Capability Header)
*/
-union cvmx_pcieepx_cfg064
-{
+union cvmx_pcieepx_cfg064 {
uint32_t u32;
- struct cvmx_pcieepx_cfg064_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg064_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t nco : 12; /**< Next Capability Offset */
uint32_t cv : 4; /**< Capability Version */
uint32_t pcieec : 16; /**< PCIE Express Extended Capability */
@@ -2891,8 +3874,13 @@ union cvmx_pcieepx_cfg064
struct cvmx_pcieepx_cfg064_s cn52xxp1;
struct cvmx_pcieepx_cfg064_s cn56xx;
struct cvmx_pcieepx_cfg064_s cn56xxp1;
+ struct cvmx_pcieepx_cfg064_s cn61xx;
struct cvmx_pcieepx_cfg064_s cn63xx;
struct cvmx_pcieepx_cfg064_s cn63xxp1;
+ struct cvmx_pcieepx_cfg064_s cn66xx;
+ struct cvmx_pcieepx_cfg064_s cn68xx;
+ struct cvmx_pcieepx_cfg064_s cn68xxp1;
+ struct cvmx_pcieepx_cfg064_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t;
@@ -2902,12 +3890,51 @@ typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t;
* PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 0 config space
* (Uncorrectable Error Status Register)
*/
-union cvmx_pcieepx_cfg065
-{
+union cvmx_pcieepx_cfg065 {
uint32_t u32;
- struct cvmx_pcieepx_cfg065_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg065_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */
+ uint32_t reserved_23_23 : 1;
+ uint32_t ucies : 1; /**< Uncorrectable Internal Error Status */
+ uint32_t reserved_21_21 : 1;
+ uint32_t ures : 1; /**< Unsupported Request Error Status */
+ uint32_t ecrces : 1; /**< ECRC Error Status */
+ uint32_t mtlps : 1; /**< Malformed TLP Status */
+ uint32_t ros : 1; /**< Receiver Overflow Status */
+ uint32_t ucs : 1; /**< Unexpected Completion Status */
+ uint32_t cas : 1; /**< Completer Abort Status */
+ uint32_t cts : 1; /**< Completion Timeout Status */
+ uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */
+ uint32_t ptlps : 1; /**< Poisoned TLP Status */
+ uint32_t reserved_6_11 : 6;
+ uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */
+ uint32_t dlpes : 1; /**< Data Link Protocol Error Status */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpes : 1;
+ uint32_t sdes : 1;
+ uint32_t reserved_6_11 : 6;
+ uint32_t ptlps : 1;
+ uint32_t fcpes : 1;
+ uint32_t cts : 1;
+ uint32_t cas : 1;
+ uint32_t ucs : 1;
+ uint32_t ros : 1;
+ uint32_t mtlps : 1;
+ uint32_t ecrces : 1;
+ uint32_t ures : 1;
+ uint32_t reserved_21_21 : 1;
+ uint32_t ucies : 1;
+ uint32_t reserved_23_23 : 1;
+ uint32_t uatombs : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg065_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_21_31 : 11;
uint32_t ures : 1; /**< Unsupported Request Error Status */
uint32_t ecrces : 1; /**< ECRC Error Status */
@@ -2938,13 +3965,91 @@ union cvmx_pcieepx_cfg065
uint32_t ures : 1;
uint32_t reserved_21_31 : 11;
#endif
- } s;
- struct cvmx_pcieepx_cfg065_s cn52xx;
- struct cvmx_pcieepx_cfg065_s cn52xxp1;
- struct cvmx_pcieepx_cfg065_s cn56xx;
- struct cvmx_pcieepx_cfg065_s cn56xxp1;
- struct cvmx_pcieepx_cfg065_s cn63xx;
- struct cvmx_pcieepx_cfg065_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg065_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg065_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg065_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg065_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */
+ uint32_t reserved_21_23 : 3;
+ uint32_t ures : 1; /**< Unsupported Request Error Status */
+ uint32_t ecrces : 1; /**< ECRC Error Status */
+ uint32_t mtlps : 1; /**< Malformed TLP Status */
+ uint32_t ros : 1; /**< Receiver Overflow Status */
+ uint32_t ucs : 1; /**< Unexpected Completion Status */
+ uint32_t cas : 1; /**< Completer Abort Status */
+ uint32_t cts : 1; /**< Completion Timeout Status */
+ uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */
+ uint32_t ptlps : 1; /**< Poisoned TLP Status */
+ uint32_t reserved_6_11 : 6;
+ uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */
+ uint32_t dlpes : 1; /**< Data Link Protocol Error Status */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpes : 1;
+ uint32_t sdes : 1;
+ uint32_t reserved_6_11 : 6;
+ uint32_t ptlps : 1;
+ uint32_t fcpes : 1;
+ uint32_t cts : 1;
+ uint32_t cas : 1;
+ uint32_t ucs : 1;
+ uint32_t ros : 1;
+ uint32_t mtlps : 1;
+ uint32_t ecrces : 1;
+ uint32_t ures : 1;
+ uint32_t reserved_21_23 : 3;
+ uint32_t uatombs : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } cn61xx;
+ struct cvmx_pcieepx_cfg065_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg065_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg065_cn61xx cn66xx;
+ struct cvmx_pcieepx_cfg065_cn61xx cn68xx;
+ struct cvmx_pcieepx_cfg065_cn52xx cn68xxp1;
+ struct cvmx_pcieepx_cfg065_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */
+ uint32_t reserved_23_23 : 1;
+ uint32_t ucies : 1; /**< Uncorrectable Internal Error Status */
+ uint32_t reserved_21_21 : 1;
+ uint32_t ures : 1; /**< Unsupported Request Error Status */
+ uint32_t ecrces : 1; /**< ECRC Error Status */
+ uint32_t mtlps : 1; /**< Malformed TLP Status */
+ uint32_t ros : 1; /**< Receiver Overflow Status */
+ uint32_t ucs : 1; /**< Unexpected Completion Status */
+ uint32_t cas : 1; /**< Completer Abort Status */
+ uint32_t cts : 1; /**< Completion Timeout Status */
+ uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */
+ uint32_t ptlps : 1; /**< Poisoned TLP Status */
+ uint32_t reserved_5_11 : 7;
+ uint32_t dlpes : 1; /**< Data Link Protocol Error Status */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpes : 1;
+ uint32_t reserved_5_11 : 7;
+ uint32_t ptlps : 1;
+ uint32_t fcpes : 1;
+ uint32_t cts : 1;
+ uint32_t cas : 1;
+ uint32_t ucs : 1;
+ uint32_t ros : 1;
+ uint32_t mtlps : 1;
+ uint32_t ecrces : 1;
+ uint32_t ures : 1;
+ uint32_t reserved_21_21 : 1;
+ uint32_t ucies : 1;
+ uint32_t reserved_23_23 : 1;
+ uint32_t uatombs : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } cnf71xx;
};
typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t;
@@ -2954,12 +4059,51 @@ typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t;
* PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 0 config space
* (Uncorrectable Error Mask Register)
*/
-union cvmx_pcieepx_cfg066
-{
+union cvmx_pcieepx_cfg066 {
uint32_t u32;
- struct cvmx_pcieepx_cfg066_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg066_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */
+ uint32_t reserved_23_23 : 1;
+ uint32_t uciem : 1; /**< Uncorrectable Internal Error Mask */
+ uint32_t reserved_21_21 : 1;
+ uint32_t urem : 1; /**< Unsupported Request Error Mask */
+ uint32_t ecrcem : 1; /**< ECRC Error Mask */
+ uint32_t mtlpm : 1; /**< Malformed TLP Mask */
+ uint32_t rom : 1; /**< Receiver Overflow Mask */
+ uint32_t ucm : 1; /**< Unexpected Completion Mask */
+ uint32_t cam : 1; /**< Completer Abort Mask */
+ uint32_t ctm : 1; /**< Completion Timeout Mask */
+ uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */
+ uint32_t ptlpm : 1; /**< Poisoned TLP Mask */
+ uint32_t reserved_6_11 : 6;
+ uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */
+ uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpem : 1;
+ uint32_t sdem : 1;
+ uint32_t reserved_6_11 : 6;
+ uint32_t ptlpm : 1;
+ uint32_t fcpem : 1;
+ uint32_t ctm : 1;
+ uint32_t cam : 1;
+ uint32_t ucm : 1;
+ uint32_t rom : 1;
+ uint32_t mtlpm : 1;
+ uint32_t ecrcem : 1;
+ uint32_t urem : 1;
+ uint32_t reserved_21_21 : 1;
+ uint32_t uciem : 1;
+ uint32_t reserved_23_23 : 1;
+ uint32_t uatombm : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg066_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_21_31 : 11;
uint32_t urem : 1; /**< Unsupported Request Error Mask */
uint32_t ecrcem : 1; /**< ECRC Error Mask */
@@ -2990,13 +4134,91 @@ union cvmx_pcieepx_cfg066
uint32_t urem : 1;
uint32_t reserved_21_31 : 11;
#endif
- } s;
- struct cvmx_pcieepx_cfg066_s cn52xx;
- struct cvmx_pcieepx_cfg066_s cn52xxp1;
- struct cvmx_pcieepx_cfg066_s cn56xx;
- struct cvmx_pcieepx_cfg066_s cn56xxp1;
- struct cvmx_pcieepx_cfg066_s cn63xx;
- struct cvmx_pcieepx_cfg066_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg066_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg066_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg066_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg066_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */
+ uint32_t reserved_21_23 : 3;
+ uint32_t urem : 1; /**< Unsupported Request Error Mask */
+ uint32_t ecrcem : 1; /**< ECRC Error Mask */
+ uint32_t mtlpm : 1; /**< Malformed TLP Mask */
+ uint32_t rom : 1; /**< Receiver Overflow Mask */
+ uint32_t ucm : 1; /**< Unexpected Completion Mask */
+ uint32_t cam : 1; /**< Completer Abort Mask */
+ uint32_t ctm : 1; /**< Completion Timeout Mask */
+ uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */
+ uint32_t ptlpm : 1; /**< Poisoned TLP Mask */
+ uint32_t reserved_6_11 : 6;
+ uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */
+ uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpem : 1;
+ uint32_t sdem : 1;
+ uint32_t reserved_6_11 : 6;
+ uint32_t ptlpm : 1;
+ uint32_t fcpem : 1;
+ uint32_t ctm : 1;
+ uint32_t cam : 1;
+ uint32_t ucm : 1;
+ uint32_t rom : 1;
+ uint32_t mtlpm : 1;
+ uint32_t ecrcem : 1;
+ uint32_t urem : 1;
+ uint32_t reserved_21_23 : 3;
+ uint32_t uatombm : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } cn61xx;
+ struct cvmx_pcieepx_cfg066_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg066_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg066_cn61xx cn66xx;
+ struct cvmx_pcieepx_cfg066_cn61xx cn68xx;
+ struct cvmx_pcieepx_cfg066_cn52xx cn68xxp1;
+ struct cvmx_pcieepx_cfg066_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */
+ uint32_t reserved_23_23 : 1;
+ uint32_t uciem : 1; /**< Uncorrectable Internal Error Mask */
+ uint32_t reserved_21_21 : 1;
+ uint32_t urem : 1; /**< Unsupported Request Error Mask */
+ uint32_t ecrcem : 1; /**< ECRC Error Mask */
+ uint32_t mtlpm : 1; /**< Malformed TLP Mask */
+ uint32_t rom : 1; /**< Receiver Overflow Mask */
+ uint32_t ucm : 1; /**< Unexpected Completion Mask */
+ uint32_t cam : 1; /**< Completer Abort Mask */
+ uint32_t ctm : 1; /**< Completion Timeout Mask */
+ uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */
+ uint32_t ptlpm : 1; /**< Poisoned TLP Mask */
+ uint32_t reserved_5_11 : 7;
+ uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpem : 1;
+ uint32_t reserved_5_11 : 7;
+ uint32_t ptlpm : 1;
+ uint32_t fcpem : 1;
+ uint32_t ctm : 1;
+ uint32_t cam : 1;
+ uint32_t ucm : 1;
+ uint32_t rom : 1;
+ uint32_t mtlpm : 1;
+ uint32_t ecrcem : 1;
+ uint32_t urem : 1;
+ uint32_t reserved_21_21 : 1;
+ uint32_t uciem : 1;
+ uint32_t reserved_23_23 : 1;
+ uint32_t uatombm : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } cnf71xx;
};
typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t;
@@ -3006,12 +4228,51 @@ typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t;
* PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 0 config space
* (Uncorrectable Error Severity Register)
*/
-union cvmx_pcieepx_cfg067
-{
+union cvmx_pcieepx_cfg067 {
uint32_t u32;
- struct cvmx_pcieepx_cfg067_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg067_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */
+ uint32_t reserved_23_23 : 1;
+ uint32_t ucies : 1; /**< Uncorrectable Internal Error Severity */
+ uint32_t reserved_21_21 : 1;
+ uint32_t ures : 1; /**< Unsupported Request Error Severity */
+ uint32_t ecrces : 1; /**< ECRC Error Severity */
+ uint32_t mtlps : 1; /**< Malformed TLP Severity */
+ uint32_t ros : 1; /**< Receiver Overflow Severity */
+ uint32_t ucs : 1; /**< Unexpected Completion Severity */
+ uint32_t cas : 1; /**< Completer Abort Severity */
+ uint32_t cts : 1; /**< Completion Timeout Severity */
+ uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */
+ uint32_t ptlps : 1; /**< Poisoned TLP Severity */
+ uint32_t reserved_6_11 : 6;
+ uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */
+ uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpes : 1;
+ uint32_t sdes : 1;
+ uint32_t reserved_6_11 : 6;
+ uint32_t ptlps : 1;
+ uint32_t fcpes : 1;
+ uint32_t cts : 1;
+ uint32_t cas : 1;
+ uint32_t ucs : 1;
+ uint32_t ros : 1;
+ uint32_t mtlps : 1;
+ uint32_t ecrces : 1;
+ uint32_t ures : 1;
+ uint32_t reserved_21_21 : 1;
+ uint32_t ucies : 1;
+ uint32_t reserved_23_23 : 1;
+ uint32_t uatombs : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg067_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_21_31 : 11;
uint32_t ures : 1; /**< Unsupported Request Error Severity */
uint32_t ecrces : 1; /**< ECRC Error Severity */
@@ -3042,13 +4303,91 @@ union cvmx_pcieepx_cfg067
uint32_t ures : 1;
uint32_t reserved_21_31 : 11;
#endif
- } s;
- struct cvmx_pcieepx_cfg067_s cn52xx;
- struct cvmx_pcieepx_cfg067_s cn52xxp1;
- struct cvmx_pcieepx_cfg067_s cn56xx;
- struct cvmx_pcieepx_cfg067_s cn56xxp1;
- struct cvmx_pcieepx_cfg067_s cn63xx;
- struct cvmx_pcieepx_cfg067_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg067_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg067_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg067_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg067_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */
+ uint32_t reserved_21_23 : 3;
+ uint32_t ures : 1; /**< Unsupported Request Error Severity */
+ uint32_t ecrces : 1; /**< ECRC Error Severity */
+ uint32_t mtlps : 1; /**< Malformed TLP Severity */
+ uint32_t ros : 1; /**< Receiver Overflow Severity */
+ uint32_t ucs : 1; /**< Unexpected Completion Severity */
+ uint32_t cas : 1; /**< Completer Abort Severity */
+ uint32_t cts : 1; /**< Completion Timeout Severity */
+ uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */
+ uint32_t ptlps : 1; /**< Poisoned TLP Severity */
+ uint32_t reserved_6_11 : 6;
+ uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */
+ uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpes : 1;
+ uint32_t sdes : 1;
+ uint32_t reserved_6_11 : 6;
+ uint32_t ptlps : 1;
+ uint32_t fcpes : 1;
+ uint32_t cts : 1;
+ uint32_t cas : 1;
+ uint32_t ucs : 1;
+ uint32_t ros : 1;
+ uint32_t mtlps : 1;
+ uint32_t ecrces : 1;
+ uint32_t ures : 1;
+ uint32_t reserved_21_23 : 3;
+ uint32_t uatombs : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } cn61xx;
+ struct cvmx_pcieepx_cfg067_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg067_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg067_cn61xx cn66xx;
+ struct cvmx_pcieepx_cfg067_cn61xx cn68xx;
+ struct cvmx_pcieepx_cfg067_cn52xx cn68xxp1;
+ struct cvmx_pcieepx_cfg067_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_25_31 : 7;
+ uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */
+ uint32_t reserved_23_23 : 1;
+ uint32_t ucies : 1; /**< Uncorrectable Internal Error Severity */
+ uint32_t reserved_21_21 : 1;
+ uint32_t ures : 1; /**< Unsupported Request Error Severity */
+ uint32_t ecrces : 1; /**< ECRC Error Severity */
+ uint32_t mtlps : 1; /**< Malformed TLP Severity */
+ uint32_t ros : 1; /**< Receiver Overflow Severity */
+ uint32_t ucs : 1; /**< Unexpected Completion Severity */
+ uint32_t cas : 1; /**< Completer Abort Severity */
+ uint32_t cts : 1; /**< Completion Timeout Severity */
+ uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */
+ uint32_t ptlps : 1; /**< Poisoned TLP Severity */
+ uint32_t reserved_5_11 : 7;
+ uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */
+ uint32_t reserved_0_3 : 4;
+#else
+ uint32_t reserved_0_3 : 4;
+ uint32_t dlpes : 1;
+ uint32_t reserved_5_11 : 7;
+ uint32_t ptlps : 1;
+ uint32_t fcpes : 1;
+ uint32_t cts : 1;
+ uint32_t cas : 1;
+ uint32_t ucs : 1;
+ uint32_t ros : 1;
+ uint32_t mtlps : 1;
+ uint32_t ecrces : 1;
+ uint32_t ures : 1;
+ uint32_t reserved_21_21 : 1;
+ uint32_t ucies : 1;
+ uint32_t reserved_23_23 : 1;
+ uint32_t uatombs : 1;
+ uint32_t reserved_25_31 : 7;
+#endif
+ } cnf71xx;
};
typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t;
@@ -3058,12 +4397,35 @@ typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t;
* PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 0 config space
* (Correctable Error Status Register)
*/
-union cvmx_pcieepx_cfg068
-{
+union cvmx_pcieepx_cfg068 {
uint32_t u32;
- struct cvmx_pcieepx_cfg068_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg068_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_15_31 : 17;
+ uint32_t cies : 1; /**< Corrected Internal Error Status */
+ uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */
+ uint32_t rtts : 1; /**< Reply Timer Timeout Status */
+ uint32_t reserved_9_11 : 3;
+ uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */
+ uint32_t bdllps : 1; /**< Bad DLLP Status */
+ uint32_t btlps : 1; /**< Bad TLP Status */
+ uint32_t reserved_1_5 : 5;
+ uint32_t res : 1; /**< Receiver Error Status */
+#else
+ uint32_t res : 1;
+ uint32_t reserved_1_5 : 5;
+ uint32_t btlps : 1;
+ uint32_t bdllps : 1;
+ uint32_t rnrs : 1;
+ uint32_t reserved_9_11 : 3;
+ uint32_t rtts : 1;
+ uint32_t anfes : 1;
+ uint32_t cies : 1;
+ uint32_t reserved_15_31 : 17;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg068_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_14_31 : 18;
uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */
uint32_t rtts : 1; /**< Reply Timer Timeout Status */
@@ -3084,13 +4446,17 @@ union cvmx_pcieepx_cfg068
uint32_t anfes : 1;
uint32_t reserved_14_31 : 18;
#endif
- } s;
- struct cvmx_pcieepx_cfg068_s cn52xx;
- struct cvmx_pcieepx_cfg068_s cn52xxp1;
- struct cvmx_pcieepx_cfg068_s cn56xx;
- struct cvmx_pcieepx_cfg068_s cn56xxp1;
- struct cvmx_pcieepx_cfg068_s cn63xx;
- struct cvmx_pcieepx_cfg068_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg068_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg068_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg068_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg068_cn52xx cn61xx;
+ struct cvmx_pcieepx_cfg068_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg068_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg068_cn52xx cn66xx;
+ struct cvmx_pcieepx_cfg068_cn52xx cn68xx;
+ struct cvmx_pcieepx_cfg068_cn52xx cn68xxp1;
+ struct cvmx_pcieepx_cfg068_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t;
@@ -3100,12 +4466,35 @@ typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t;
* PCIE_CFG069 = Seventieth 32-bits of PCIE type 0 config space
* (Correctable Error Mask Register)
*/
-union cvmx_pcieepx_cfg069
-{
+union cvmx_pcieepx_cfg069 {
uint32_t u32;
- struct cvmx_pcieepx_cfg069_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg069_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_15_31 : 17;
+ uint32_t ciem : 1; /**< Corrected Internal Error Mask */
+ uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */
+ uint32_t rttm : 1; /**< Reply Timer Timeout Mask */
+ uint32_t reserved_9_11 : 3;
+ uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */
+ uint32_t bdllpm : 1; /**< Bad DLLP Mask */
+ uint32_t btlpm : 1; /**< Bad TLP Mask */
+ uint32_t reserved_1_5 : 5;
+ uint32_t rem : 1; /**< Receiver Error Mask */
+#else
+ uint32_t rem : 1;
+ uint32_t reserved_1_5 : 5;
+ uint32_t btlpm : 1;
+ uint32_t bdllpm : 1;
+ uint32_t rnrm : 1;
+ uint32_t reserved_9_11 : 3;
+ uint32_t rttm : 1;
+ uint32_t anfem : 1;
+ uint32_t ciem : 1;
+ uint32_t reserved_15_31 : 17;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg069_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_14_31 : 18;
uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */
uint32_t rttm : 1; /**< Reply Timer Timeout Mask */
@@ -3126,13 +4515,17 @@ union cvmx_pcieepx_cfg069
uint32_t anfem : 1;
uint32_t reserved_14_31 : 18;
#endif
- } s;
- struct cvmx_pcieepx_cfg069_s cn52xx;
- struct cvmx_pcieepx_cfg069_s cn52xxp1;
- struct cvmx_pcieepx_cfg069_s cn56xx;
- struct cvmx_pcieepx_cfg069_s cn56xxp1;
- struct cvmx_pcieepx_cfg069_s cn63xx;
- struct cvmx_pcieepx_cfg069_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg069_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg069_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg069_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg069_cn52xx cn61xx;
+ struct cvmx_pcieepx_cfg069_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg069_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg069_cn52xx cn66xx;
+ struct cvmx_pcieepx_cfg069_cn52xx cn68xx;
+ struct cvmx_pcieepx_cfg069_cn52xx cn68xxp1;
+ struct cvmx_pcieepx_cfg069_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t;
@@ -3142,12 +4535,10 @@ typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t;
* PCIE_CFG070 = Seventy-first 32-bits of PCIE type 0 config space
* (Advanced Error Capabilities and Control Register)
*/
-union cvmx_pcieepx_cfg070
-{
+union cvmx_pcieepx_cfg070 {
uint32_t u32;
- struct cvmx_pcieepx_cfg070_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg070_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_9_31 : 23;
uint32_t ce : 1; /**< ECRC Check Enable */
uint32_t cc : 1; /**< ECRC Check Capable */
@@ -3167,8 +4558,13 @@ union cvmx_pcieepx_cfg070
struct cvmx_pcieepx_cfg070_s cn52xxp1;
struct cvmx_pcieepx_cfg070_s cn56xx;
struct cvmx_pcieepx_cfg070_s cn56xxp1;
+ struct cvmx_pcieepx_cfg070_s cn61xx;
struct cvmx_pcieepx_cfg070_s cn63xx;
struct cvmx_pcieepx_cfg070_s cn63xxp1;
+ struct cvmx_pcieepx_cfg070_s cn66xx;
+ struct cvmx_pcieepx_cfg070_s cn68xx;
+ struct cvmx_pcieepx_cfg070_s cn68xxp1;
+ struct cvmx_pcieepx_cfg070_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t;
@@ -3178,12 +4574,10 @@ typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t;
* PCIE_CFG071 = Seventy-second 32-bits of PCIE type 0 config space
* (Header Log Register 1)
*/
-union cvmx_pcieepx_cfg071
-{
+union cvmx_pcieepx_cfg071 {
uint32_t u32;
- struct cvmx_pcieepx_cfg071_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg071_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dword1 : 32; /**< Header Log Register (first DWORD) */
#else
uint32_t dword1 : 32;
@@ -3193,8 +4587,13 @@ union cvmx_pcieepx_cfg071
struct cvmx_pcieepx_cfg071_s cn52xxp1;
struct cvmx_pcieepx_cfg071_s cn56xx;
struct cvmx_pcieepx_cfg071_s cn56xxp1;
+ struct cvmx_pcieepx_cfg071_s cn61xx;
struct cvmx_pcieepx_cfg071_s cn63xx;
struct cvmx_pcieepx_cfg071_s cn63xxp1;
+ struct cvmx_pcieepx_cfg071_s cn66xx;
+ struct cvmx_pcieepx_cfg071_s cn68xx;
+ struct cvmx_pcieepx_cfg071_s cn68xxp1;
+ struct cvmx_pcieepx_cfg071_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t;
@@ -3204,12 +4603,10 @@ typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t;
* PCIE_CFG072 = Seventy-third 32-bits of PCIE type 0 config space
* (Header Log Register 2)
*/
-union cvmx_pcieepx_cfg072
-{
+union cvmx_pcieepx_cfg072 {
uint32_t u32;
- struct cvmx_pcieepx_cfg072_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg072_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dword2 : 32; /**< Header Log Register (second DWORD) */
#else
uint32_t dword2 : 32;
@@ -3219,8 +4616,13 @@ union cvmx_pcieepx_cfg072
struct cvmx_pcieepx_cfg072_s cn52xxp1;
struct cvmx_pcieepx_cfg072_s cn56xx;
struct cvmx_pcieepx_cfg072_s cn56xxp1;
+ struct cvmx_pcieepx_cfg072_s cn61xx;
struct cvmx_pcieepx_cfg072_s cn63xx;
struct cvmx_pcieepx_cfg072_s cn63xxp1;
+ struct cvmx_pcieepx_cfg072_s cn66xx;
+ struct cvmx_pcieepx_cfg072_s cn68xx;
+ struct cvmx_pcieepx_cfg072_s cn68xxp1;
+ struct cvmx_pcieepx_cfg072_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t;
@@ -3230,12 +4632,10 @@ typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t;
* PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 0 config space
* (Header Log Register 3)
*/
-union cvmx_pcieepx_cfg073
-{
+union cvmx_pcieepx_cfg073 {
uint32_t u32;
- struct cvmx_pcieepx_cfg073_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg073_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dword3 : 32; /**< Header Log Register (third DWORD) */
#else
uint32_t dword3 : 32;
@@ -3245,8 +4645,13 @@ union cvmx_pcieepx_cfg073
struct cvmx_pcieepx_cfg073_s cn52xxp1;
struct cvmx_pcieepx_cfg073_s cn56xx;
struct cvmx_pcieepx_cfg073_s cn56xxp1;
+ struct cvmx_pcieepx_cfg073_s cn61xx;
struct cvmx_pcieepx_cfg073_s cn63xx;
struct cvmx_pcieepx_cfg073_s cn63xxp1;
+ struct cvmx_pcieepx_cfg073_s cn66xx;
+ struct cvmx_pcieepx_cfg073_s cn68xx;
+ struct cvmx_pcieepx_cfg073_s cn68xxp1;
+ struct cvmx_pcieepx_cfg073_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t;
@@ -3256,12 +4661,10 @@ typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t;
* PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 0 config space
* (Header Log Register 4)
*/
-union cvmx_pcieepx_cfg074
-{
+union cvmx_pcieepx_cfg074 {
uint32_t u32;
- struct cvmx_pcieepx_cfg074_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg074_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dword4 : 32; /**< Header Log Register (fourth DWORD) */
#else
uint32_t dword4 : 32;
@@ -3271,8 +4674,13 @@ union cvmx_pcieepx_cfg074
struct cvmx_pcieepx_cfg074_s cn52xxp1;
struct cvmx_pcieepx_cfg074_s cn56xx;
struct cvmx_pcieepx_cfg074_s cn56xxp1;
+ struct cvmx_pcieepx_cfg074_s cn61xx;
struct cvmx_pcieepx_cfg074_s cn63xx;
struct cvmx_pcieepx_cfg074_s cn63xxp1;
+ struct cvmx_pcieepx_cfg074_s cn66xx;
+ struct cvmx_pcieepx_cfg074_s cn68xx;
+ struct cvmx_pcieepx_cfg074_s cn68xxp1;
+ struct cvmx_pcieepx_cfg074_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t;
@@ -3282,22 +4690,26 @@ typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t;
* PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 0 config space
* (Ack Latency Timer and Replay Timer Register)
*/
-union cvmx_pcieepx_cfg448
-{
+union cvmx_pcieepx_cfg448 {
uint32_t u32;
- struct cvmx_pcieepx_cfg448_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg448_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t rtl : 16; /**< Replay Time Limit
The replay timer expires when it reaches this limit. The PCI
Express bus initiates a replay upon reception of a Nak or when
the replay timer expires.
- The default is then updated based on the Negotiated Link Width
- and Max_Payload_Size. */
+ This value will be set correctly by the hardware out of reset
+ or when the negotiated Link-Width or Payload-Size changes. If
+ the user changes this value through a CSR write or by an
+ EEPROM load then they should refer to the PCIe Specification
+ for the correct value. */
uint32_t rtltl : 16; /**< Round Trip Latency Time Limit
The Ack/Nak latency timer expires when it reaches this limit.
- The default is then updated based on the Negotiated Link Width
- and Max_Payload_Size. */
+ This value will be set correctly by the hardware out of reset
+ or when the negotiated Link-Width or Payload-Size changes. If
+ the user changes this value through a CSR write or by an
+ EEPROM load then they should refer to the PCIe Specification
+ for the correct value. */
#else
uint32_t rtltl : 16;
uint32_t rtl : 16;
@@ -3307,8 +4719,13 @@ union cvmx_pcieepx_cfg448
struct cvmx_pcieepx_cfg448_s cn52xxp1;
struct cvmx_pcieepx_cfg448_s cn56xx;
struct cvmx_pcieepx_cfg448_s cn56xxp1;
+ struct cvmx_pcieepx_cfg448_s cn61xx;
struct cvmx_pcieepx_cfg448_s cn63xx;
struct cvmx_pcieepx_cfg448_s cn63xxp1;
+ struct cvmx_pcieepx_cfg448_s cn66xx;
+ struct cvmx_pcieepx_cfg448_s cn68xx;
+ struct cvmx_pcieepx_cfg448_s cn68xxp1;
+ struct cvmx_pcieepx_cfg448_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t;
@@ -3318,12 +4735,10 @@ typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t;
* PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 0 config space
* (Other Message Register)
*/
-union cvmx_pcieepx_cfg449
-{
+union cvmx_pcieepx_cfg449 {
uint32_t u32;
- struct cvmx_pcieepx_cfg449_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg449_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t omr : 32; /**< Other Message Register
This register can be used for either of the following purposes:
o To send a specific PCI Express Message, the application
@@ -3344,8 +4759,13 @@ union cvmx_pcieepx_cfg449
struct cvmx_pcieepx_cfg449_s cn52xxp1;
struct cvmx_pcieepx_cfg449_s cn56xx;
struct cvmx_pcieepx_cfg449_s cn56xxp1;
+ struct cvmx_pcieepx_cfg449_s cn61xx;
struct cvmx_pcieepx_cfg449_s cn63xx;
struct cvmx_pcieepx_cfg449_s cn63xxp1;
+ struct cvmx_pcieepx_cfg449_s cn66xx;
+ struct cvmx_pcieepx_cfg449_s cn68xx;
+ struct cvmx_pcieepx_cfg449_s cn68xxp1;
+ struct cvmx_pcieepx_cfg449_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t;
@@ -3355,12 +4775,10 @@ typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t;
* PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 0 config space
* (Port Force Link Register)
*/
-union cvmx_pcieepx_cfg450
-{
+union cvmx_pcieepx_cfg450 {
uint32_t u32;
- struct cvmx_pcieepx_cfg450_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg450_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lpec : 8; /**< Low Power Entrance Count
The Power Management state will wait for this many clock cycles
for the associated completion of a CfgWr to PCIE_CFG017 register
@@ -3427,8 +4845,13 @@ union cvmx_pcieepx_cfg450
struct cvmx_pcieepx_cfg450_s cn52xxp1;
struct cvmx_pcieepx_cfg450_s cn56xx;
struct cvmx_pcieepx_cfg450_s cn56xxp1;
+ struct cvmx_pcieepx_cfg450_s cn61xx;
struct cvmx_pcieepx_cfg450_s cn63xx;
struct cvmx_pcieepx_cfg450_s cn63xxp1;
+ struct cvmx_pcieepx_cfg450_s cn66xx;
+ struct cvmx_pcieepx_cfg450_s cn68xx;
+ struct cvmx_pcieepx_cfg450_s cn68xxp1;
+ struct cvmx_pcieepx_cfg450_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t;
@@ -3438,12 +4861,63 @@ typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t;
* PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 0 config space
* (Ack Frequency Register)
*/
-union cvmx_pcieepx_cfg451
-{
+union cvmx_pcieepx_cfg451 {
uint32_t u32;
- struct cvmx_pcieepx_cfg451_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg451_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_31_31 : 1;
+ uint32_t easpml1 : 1; /**< Enter ASPM L1 without receive in L0s
+ Allow core to enter ASPM L1 even when link partner did
+ not go to L0s (receive is not in L0s).
+ When not set, core goes to ASPM L1 only after idle period
+ during which both receive and transmit are in L0s. */
+ uint32_t l1el : 3; /**< L1 Entrance Latency
+ Values correspond to:
+ o 000: 1 ms
+ o 001: 2 ms
+ o 010: 4 ms
+ o 011: 8 ms
+ o 100: 16 ms
+ o 101: 32 ms
+ o 110 or 111: 64 ms */
+ uint32_t l0el : 3; /**< L0s Entrance Latency
+ Values correspond to:
+ o 000: 1 ms
+ o 001: 2 ms
+ o 010: 3 ms
+ o 011: 4 ms
+ o 100: 5 ms
+ o 101: 6 ms
+ o 110 or 111: 7 ms */
+ uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used.
+ The number of Fast Training Sequence ordered sets to be
+ transmitted when transitioning from L0s to L0. The maximum
+ number of FTS ordered-sets that a component can request is 255.
+ Note: A value of zero is not supported; a value of
+ zero can cause the LTSSM to go into the recovery state
+ when exiting from L0s. */
+ uint32_t n_fts : 8; /**< N_FTS
+ The number of Fast Training Sequence ordered sets to be
+ transmitted when transitioning from L0s to L0. The maximum
+ number of FTS ordered-sets that a component can request is 255.
+ Note: A value of zero is not supported; a value of
+ zero can cause the LTSSM to go into the recovery state
+ when exiting from L0s. */
+ uint32_t ack_freq : 8; /**< Ack Frequency
+ The number of pending Ack's specified here (up to 255) before
+ sending an Ack. */
+#else
+ uint32_t ack_freq : 8;
+ uint32_t n_fts : 8;
+ uint32_t n_fts_cc : 8;
+ uint32_t l0el : 3;
+ uint32_t l1el : 3;
+ uint32_t easpml1 : 1;
+ uint32_t reserved_31_31 : 1;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg451_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_30_31 : 2;
uint32_t l1el : 3; /**< L1 Entrance Latency
Values correspond to:
@@ -3488,13 +4962,17 @@ union cvmx_pcieepx_cfg451
uint32_t l1el : 3;
uint32_t reserved_30_31 : 2;
#endif
- } s;
- struct cvmx_pcieepx_cfg451_s cn52xx;
- struct cvmx_pcieepx_cfg451_s cn52xxp1;
- struct cvmx_pcieepx_cfg451_s cn56xx;
- struct cvmx_pcieepx_cfg451_s cn56xxp1;
- struct cvmx_pcieepx_cfg451_s cn63xx;
- struct cvmx_pcieepx_cfg451_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg451_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg451_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg451_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg451_s cn61xx;
+ struct cvmx_pcieepx_cfg451_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg451_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg451_s cn66xx;
+ struct cvmx_pcieepx_cfg451_s cn68xx;
+ struct cvmx_pcieepx_cfg451_s cn68xxp1;
+ struct cvmx_pcieepx_cfg451_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t;
@@ -3504,12 +4982,10 @@ typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t;
* PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 0 config space
* (Port Link Control Register)
*/
-union cvmx_pcieepx_cfg452
-{
+union cvmx_pcieepx_cfg452 {
uint32_t u32;
- struct cvmx_pcieepx_cfg452_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg452_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_26_31 : 6;
uint32_t eccrc : 1; /**< Enable Corrupted CRC
Causes corrupt LCRC for TLPs when set,
@@ -3518,6 +4994,68 @@ union cvmx_pcieepx_cfg452
uint32_t reserved_22_24 : 3;
uint32_t lme : 6; /**< Link Mode Enable
o 000001: x1
+ o 000011: x2 (not supported)
+ o 000111: x4 (not supported)
+ o 001111: x8 (not supported)
+ o 011111: x16 (not supported)
+ o 111111: x32 (not supported)
+ This field indicates the MAXIMUM number of lanes supported
+ by the PCIe port.
+ See also MLW.
+ (Note: The value of this field does NOT indicate the number
+ of lanes in use by the PCIe. LME sets the max number of lanes
+ in the PCIe core that COULD be used. As per the PCIe specs,
+ the PCIe core can negotiate a smaller link width) */
+ uint32_t reserved_8_15 : 8;
+ uint32_t flm : 1; /**< Fast Link Mode
+ Sets all internal timers to fast mode for simulation purposes.
+ If during an eeprom load, the first word loaded is 0xffffffff,
+ then the EEPROM load will be terminated and this bit will be set. */
+ uint32_t reserved_6_6 : 1;
+ uint32_t dllle : 1; /**< DLL Link Enable
+ Enables Link initialization. If DLL Link Enable = 0, the PCI
+ Express bus does not transmit InitFC DLLPs and does not
+ establish a Link. */
+ uint32_t reserved_4_4 : 1;
+ uint32_t ra : 1; /**< Reset Assert
+ Triggers a recovery and forces the LTSSM to the Hot Reset
+ state (downstream port only). */
+ uint32_t le : 1; /**< Loopback Enable
+ Initiate loopback mode as a master. On a 0->1 transition,
+ the PCIe core sends TS ordered sets with the loopback bit set
+ to cause the link partner to enter into loopback mode as a
+ slave. Normal transmission is not possible when LE=1. To exit
+ loopback mode, take the link through a reset sequence. */
+ uint32_t sd : 1; /**< Scramble Disable
+ Turns off data scrambling. */
+ uint32_t omr : 1; /**< Other Message Request
+ When software writes a `1' to this bit, the PCI Express bus
+ transmits the Message contained in the Other Message register. */
+#else
+ uint32_t omr : 1;
+ uint32_t sd : 1;
+ uint32_t le : 1;
+ uint32_t ra : 1;
+ uint32_t reserved_4_4 : 1;
+ uint32_t dllle : 1;
+ uint32_t reserved_6_6 : 1;
+ uint32_t flm : 1;
+ uint32_t reserved_8_15 : 8;
+ uint32_t lme : 6;
+ uint32_t reserved_22_24 : 3;
+ uint32_t eccrc : 1;
+ uint32_t reserved_26_31 : 6;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg452_s cn52xx;
+ struct cvmx_pcieepx_cfg452_s cn52xxp1;
+ struct cvmx_pcieepx_cfg452_s cn56xx;
+ struct cvmx_pcieepx_cfg452_s cn56xxp1;
+ struct cvmx_pcieepx_cfg452_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_22_31 : 10;
+ uint32_t lme : 6; /**< Link Mode Enable
+ o 000001: x1
o 000011: x2
o 000111: x4
o 001111: x8 (not supported)
@@ -3571,17 +5109,15 @@ union cvmx_pcieepx_cfg452
uint32_t flm : 1;
uint32_t reserved_8_15 : 8;
uint32_t lme : 6;
- uint32_t reserved_22_24 : 3;
- uint32_t eccrc : 1;
- uint32_t reserved_26_31 : 6;
+ uint32_t reserved_22_31 : 10;
#endif
- } s;
- struct cvmx_pcieepx_cfg452_s cn52xx;
- struct cvmx_pcieepx_cfg452_s cn52xxp1;
- struct cvmx_pcieepx_cfg452_s cn56xx;
- struct cvmx_pcieepx_cfg452_s cn56xxp1;
+ } cn61xx;
struct cvmx_pcieepx_cfg452_s cn63xx;
struct cvmx_pcieepx_cfg452_s cn63xxp1;
+ struct cvmx_pcieepx_cfg452_cn61xx cn66xx;
+ struct cvmx_pcieepx_cfg452_cn61xx cn68xx;
+ struct cvmx_pcieepx_cfg452_cn61xx cn68xxp1;
+ struct cvmx_pcieepx_cfg452_cn61xx cnf71xx;
};
typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t;
@@ -3591,12 +5127,10 @@ typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t;
* PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 0 config space
* (Lane Skew Register)
*/
-union cvmx_pcieepx_cfg453
-{
+union cvmx_pcieepx_cfg453 {
uint32_t u32;
- struct cvmx_pcieepx_cfg453_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg453_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dlld : 1; /**< Disable Lane-to-Lane Deskew
Disables the internal Lane-to-Lane deskew logic. */
uint32_t reserved_26_30 : 5;
@@ -3622,8 +5156,13 @@ union cvmx_pcieepx_cfg453
struct cvmx_pcieepx_cfg453_s cn52xxp1;
struct cvmx_pcieepx_cfg453_s cn56xx;
struct cvmx_pcieepx_cfg453_s cn56xxp1;
+ struct cvmx_pcieepx_cfg453_s cn61xx;
struct cvmx_pcieepx_cfg453_s cn63xx;
struct cvmx_pcieepx_cfg453_s cn63xxp1;
+ struct cvmx_pcieepx_cfg453_s cn66xx;
+ struct cvmx_pcieepx_cfg453_s cn68xx;
+ struct cvmx_pcieepx_cfg453_s cn68xxp1;
+ struct cvmx_pcieepx_cfg453_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t;
@@ -3633,12 +5172,37 @@ typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t;
* PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 0 config space
* (Symbol Number Register)
*/
-union cvmx_pcieepx_cfg454
-{
+union cvmx_pcieepx_cfg454 {
uint32_t u32;
- struct cvmx_pcieepx_cfg454_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg454_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1)
+ Configuration Requests targeted at function numbers above this
+ value will be returned with unsupported request */
+ uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer
+ Increases the timer value for the Flow Control watchdog timer,
+ in increments of 16 clock cycles. */
+ uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer
+ Increases the timer value for the Ack/Nak latency timer, in
+ increments of 64 clock cycles. */
+ uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer
+ Increases the timer value for the replay timer, in increments
+ of 64 clock cycles. */
+ uint32_t reserved_11_13 : 3;
+ uint32_t nskps : 3; /**< Number of SKP Symbols */
+ uint32_t reserved_0_7 : 8;
+#else
+ uint32_t reserved_0_7 : 8;
+ uint32_t nskps : 3;
+ uint32_t reserved_11_13 : 3;
+ uint32_t tmrt : 5;
+ uint32_t tmanlt : 5;
+ uint32_t tmfcwt : 5;
+ uint32_t cx_nfunc : 3;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg454_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_29_31 : 3;
uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer
Increases the timer value for the Flow Control watchdog timer,
@@ -3665,13 +5229,41 @@ union cvmx_pcieepx_cfg454
uint32_t tmfcwt : 5;
uint32_t reserved_29_31 : 3;
#endif
- } s;
- struct cvmx_pcieepx_cfg454_s cn52xx;
- struct cvmx_pcieepx_cfg454_s cn52xxp1;
- struct cvmx_pcieepx_cfg454_s cn56xx;
- struct cvmx_pcieepx_cfg454_s cn56xxp1;
- struct cvmx_pcieepx_cfg454_s cn63xx;
- struct cvmx_pcieepx_cfg454_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg454_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg454_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg454_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg454_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1)
+ Configuration Requests targeted at function numbers above this
+ value will be returned with unsupported request */
+ uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer
+ Increases the timer value for the Flow Control watchdog timer,
+ in increments of 16 clock cycles. */
+ uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer
+ Increases the timer value for the Ack/Nak latency timer, in
+ increments of 64 clock cycles. */
+ uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer
+ Increases the timer value for the replay timer, in increments
+ of 64 clock cycles. */
+ uint32_t reserved_8_13 : 6;
+ uint32_t mfuncn : 8; /**< Max Number of Functions Supported */
+#else
+ uint32_t mfuncn : 8;
+ uint32_t reserved_8_13 : 6;
+ uint32_t tmrt : 5;
+ uint32_t tmanlt : 5;
+ uint32_t tmfcwt : 5;
+ uint32_t cx_nfunc : 3;
+#endif
+ } cn61xx;
+ struct cvmx_pcieepx_cfg454_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg454_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg454_cn61xx cn66xx;
+ struct cvmx_pcieepx_cfg454_cn61xx cn68xx;
+ struct cvmx_pcieepx_cfg454_cn52xx cn68xxp1;
+ struct cvmx_pcieepx_cfg454_cn61xx cnf71xx;
};
typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t;
@@ -3681,12 +5273,10 @@ typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t;
* PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 0 config space
* (Symbol Timer Register/Filter Mask Register 1)
*/
-union cvmx_pcieepx_cfg455
-{
+union cvmx_pcieepx_cfg455 {
uint32_t u32;
- struct cvmx_pcieepx_cfg455_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg455_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t m_cfg0_filt : 1; /**< Mask filtering of received Configuration Requests (RC mode only) */
uint32_t m_io_filt : 1; /**< Mask filtering of received I/O Requests (RC mode only) */
uint32_t msg_ctrl : 1; /**< Message Control
@@ -3733,8 +5323,13 @@ union cvmx_pcieepx_cfg455
struct cvmx_pcieepx_cfg455_s cn52xxp1;
struct cvmx_pcieepx_cfg455_s cn56xx;
struct cvmx_pcieepx_cfg455_s cn56xxp1;
+ struct cvmx_pcieepx_cfg455_s cn61xx;
struct cvmx_pcieepx_cfg455_s cn63xx;
struct cvmx_pcieepx_cfg455_s cn63xxp1;
+ struct cvmx_pcieepx_cfg455_s cn66xx;
+ struct cvmx_pcieepx_cfg455_s cn68xx;
+ struct cvmx_pcieepx_cfg455_s cn68xxp1;
+ struct cvmx_pcieepx_cfg455_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t;
@@ -3744,12 +5339,25 @@ typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t;
* PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 0 config space
* (Filter Mask Register 2)
*/
-union cvmx_pcieepx_cfg456
-{
+union cvmx_pcieepx_cfg456 {
uint32_t u32;
- struct cvmx_pcieepx_cfg456_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg456_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint32_t reserved_4_31 : 28;
+ uint32_t m_handle_flush : 1; /**< Mask Core Filter to handle flush request */
+ uint32_t m_dabort_4ucpl : 1; /**< Mask DLLP abort for unexpected CPL */
+ uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */
+ uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
+#else
+ uint32_t m_vend0_drp : 1;
+ uint32_t m_vend1_drp : 1;
+ uint32_t m_dabort_4ucpl : 1;
+ uint32_t m_handle_flush : 1;
+ uint32_t reserved_4_31 : 28;
+#endif
+ } s;
+ struct cvmx_pcieepx_cfg456_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_2_31 : 30;
uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */
uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
@@ -3758,13 +5366,17 @@ union cvmx_pcieepx_cfg456
uint32_t m_vend1_drp : 1;
uint32_t reserved_2_31 : 30;
#endif
- } s;
- struct cvmx_pcieepx_cfg456_s cn52xx;
- struct cvmx_pcieepx_cfg456_s cn52xxp1;
- struct cvmx_pcieepx_cfg456_s cn56xx;
- struct cvmx_pcieepx_cfg456_s cn56xxp1;
- struct cvmx_pcieepx_cfg456_s cn63xx;
- struct cvmx_pcieepx_cfg456_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pcieepx_cfg456_cn52xx cn52xxp1;
+ struct cvmx_pcieepx_cfg456_cn52xx cn56xx;
+ struct cvmx_pcieepx_cfg456_cn52xx cn56xxp1;
+ struct cvmx_pcieepx_cfg456_s cn61xx;
+ struct cvmx_pcieepx_cfg456_cn52xx cn63xx;
+ struct cvmx_pcieepx_cfg456_cn52xx cn63xxp1;
+ struct cvmx_pcieepx_cfg456_s cn66xx;
+ struct cvmx_pcieepx_cfg456_s cn68xx;
+ struct cvmx_pcieepx_cfg456_cn52xx cn68xxp1;
+ struct cvmx_pcieepx_cfg456_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t;
@@ -3774,12 +5386,10 @@ typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t;
* PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 0 config space
* (Debug Register 0)
*/
-union cvmx_pcieepx_cfg458
-{
+union cvmx_pcieepx_cfg458 {
uint32_t u32;
- struct cvmx_pcieepx_cfg458_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg458_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dbg_info_l32 : 32; /**< Debug Info Lower 32 Bits */
#else
uint32_t dbg_info_l32 : 32;
@@ -3789,8 +5399,13 @@ union cvmx_pcieepx_cfg458
struct cvmx_pcieepx_cfg458_s cn52xxp1;
struct cvmx_pcieepx_cfg458_s cn56xx;
struct cvmx_pcieepx_cfg458_s cn56xxp1;
+ struct cvmx_pcieepx_cfg458_s cn61xx;
struct cvmx_pcieepx_cfg458_s cn63xx;
struct cvmx_pcieepx_cfg458_s cn63xxp1;
+ struct cvmx_pcieepx_cfg458_s cn66xx;
+ struct cvmx_pcieepx_cfg458_s cn68xx;
+ struct cvmx_pcieepx_cfg458_s cn68xxp1;
+ struct cvmx_pcieepx_cfg458_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t;
@@ -3800,12 +5415,10 @@ typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t;
* PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 0 config space
* (Debug Register 1)
*/
-union cvmx_pcieepx_cfg459
-{
+union cvmx_pcieepx_cfg459 {
uint32_t u32;
- struct cvmx_pcieepx_cfg459_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg459_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dbg_info_u32 : 32; /**< Debug Info Upper 32 Bits */
#else
uint32_t dbg_info_u32 : 32;
@@ -3815,8 +5428,13 @@ union cvmx_pcieepx_cfg459
struct cvmx_pcieepx_cfg459_s cn52xxp1;
struct cvmx_pcieepx_cfg459_s cn56xx;
struct cvmx_pcieepx_cfg459_s cn56xxp1;
+ struct cvmx_pcieepx_cfg459_s cn61xx;
struct cvmx_pcieepx_cfg459_s cn63xx;
struct cvmx_pcieepx_cfg459_s cn63xxp1;
+ struct cvmx_pcieepx_cfg459_s cn66xx;
+ struct cvmx_pcieepx_cfg459_s cn68xx;
+ struct cvmx_pcieepx_cfg459_s cn68xxp1;
+ struct cvmx_pcieepx_cfg459_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t;
@@ -3826,12 +5444,10 @@ typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t;
* PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 0 config space
* (Transmit Posted FC Credit Status)
*/
-union cvmx_pcieepx_cfg460
-{
+union cvmx_pcieepx_cfg460 {
uint32_t u32;
- struct cvmx_pcieepx_cfg460_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg460_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_20_31 : 12;
uint32_t tphfcc : 8; /**< Transmit Posted Header FC Credits
The Posted Header credits advertised by the receiver at the
@@ -3849,8 +5465,13 @@ union cvmx_pcieepx_cfg460
struct cvmx_pcieepx_cfg460_s cn52xxp1;
struct cvmx_pcieepx_cfg460_s cn56xx;
struct cvmx_pcieepx_cfg460_s cn56xxp1;
+ struct cvmx_pcieepx_cfg460_s cn61xx;
struct cvmx_pcieepx_cfg460_s cn63xx;
struct cvmx_pcieepx_cfg460_s cn63xxp1;
+ struct cvmx_pcieepx_cfg460_s cn66xx;
+ struct cvmx_pcieepx_cfg460_s cn68xx;
+ struct cvmx_pcieepx_cfg460_s cn68xxp1;
+ struct cvmx_pcieepx_cfg460_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t;
@@ -3860,12 +5481,10 @@ typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t;
* PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 0 config space
* (Transmit Non-Posted FC Credit Status)
*/
-union cvmx_pcieepx_cfg461
-{
+union cvmx_pcieepx_cfg461 {
uint32_t u32;
- struct cvmx_pcieepx_cfg461_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg461_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_20_31 : 12;
uint32_t tchfcc : 8; /**< Transmit Non-Posted Header FC Credits
The Non-Posted Header credits advertised by the receiver at the
@@ -3883,8 +5502,13 @@ union cvmx_pcieepx_cfg461
struct cvmx_pcieepx_cfg461_s cn52xxp1;
struct cvmx_pcieepx_cfg461_s cn56xx;
struct cvmx_pcieepx_cfg461_s cn56xxp1;
+ struct cvmx_pcieepx_cfg461_s cn61xx;
struct cvmx_pcieepx_cfg461_s cn63xx;
struct cvmx_pcieepx_cfg461_s cn63xxp1;
+ struct cvmx_pcieepx_cfg461_s cn66xx;
+ struct cvmx_pcieepx_cfg461_s cn68xx;
+ struct cvmx_pcieepx_cfg461_s cn68xxp1;
+ struct cvmx_pcieepx_cfg461_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t;
@@ -3894,12 +5518,10 @@ typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t;
* PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 0 config space
* (Transmit Completion FC Credit Status )
*/
-union cvmx_pcieepx_cfg462
-{
+union cvmx_pcieepx_cfg462 {
uint32_t u32;
- struct cvmx_pcieepx_cfg462_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg462_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_20_31 : 12;
uint32_t tchfcc : 8; /**< Transmit Completion Header FC Credits
The Completion Header credits advertised by the receiver at the
@@ -3917,8 +5539,13 @@ union cvmx_pcieepx_cfg462
struct cvmx_pcieepx_cfg462_s cn52xxp1;
struct cvmx_pcieepx_cfg462_s cn56xx;
struct cvmx_pcieepx_cfg462_s cn56xxp1;
+ struct cvmx_pcieepx_cfg462_s cn61xx;
struct cvmx_pcieepx_cfg462_s cn63xx;
struct cvmx_pcieepx_cfg462_s cn63xxp1;
+ struct cvmx_pcieepx_cfg462_s cn66xx;
+ struct cvmx_pcieepx_cfg462_s cn68xx;
+ struct cvmx_pcieepx_cfg462_s cn68xxp1;
+ struct cvmx_pcieepx_cfg462_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t;
@@ -3928,12 +5555,10 @@ typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t;
* PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 0 config space
* (Queue Status)
*/
-union cvmx_pcieepx_cfg463
-{
+union cvmx_pcieepx_cfg463 {
uint32_t u32;
- struct cvmx_pcieepx_cfg463_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg463_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_3_31 : 29;
uint32_t rqne : 1; /**< Received Queue Not Empty
Indicates there is data in one or more of the receive buffers. */
@@ -3955,8 +5580,13 @@ union cvmx_pcieepx_cfg463
struct cvmx_pcieepx_cfg463_s cn52xxp1;
struct cvmx_pcieepx_cfg463_s cn56xx;
struct cvmx_pcieepx_cfg463_s cn56xxp1;
+ struct cvmx_pcieepx_cfg463_s cn61xx;
struct cvmx_pcieepx_cfg463_s cn63xx;
struct cvmx_pcieepx_cfg463_s cn63xxp1;
+ struct cvmx_pcieepx_cfg463_s cn66xx;
+ struct cvmx_pcieepx_cfg463_s cn68xx;
+ struct cvmx_pcieepx_cfg463_s cn68xxp1;
+ struct cvmx_pcieepx_cfg463_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t;
@@ -3966,12 +5596,10 @@ typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t;
* PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 0 config space
* (VC Transmit Arbitration Register 1)
*/
-union cvmx_pcieepx_cfg464
-{
+union cvmx_pcieepx_cfg464 {
uint32_t u32;
- struct cvmx_pcieepx_cfg464_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg464_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t wrr_vc3 : 8; /**< WRR Weight for VC3 */
uint32_t wrr_vc2 : 8; /**< WRR Weight for VC2 */
uint32_t wrr_vc1 : 8; /**< WRR Weight for VC1 */
@@ -3987,8 +5615,13 @@ union cvmx_pcieepx_cfg464
struct cvmx_pcieepx_cfg464_s cn52xxp1;
struct cvmx_pcieepx_cfg464_s cn56xx;
struct cvmx_pcieepx_cfg464_s cn56xxp1;
+ struct cvmx_pcieepx_cfg464_s cn61xx;
struct cvmx_pcieepx_cfg464_s cn63xx;
struct cvmx_pcieepx_cfg464_s cn63xxp1;
+ struct cvmx_pcieepx_cfg464_s cn66xx;
+ struct cvmx_pcieepx_cfg464_s cn68xx;
+ struct cvmx_pcieepx_cfg464_s cn68xxp1;
+ struct cvmx_pcieepx_cfg464_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t;
@@ -3998,12 +5631,10 @@ typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t;
* PCIE_CFG465 = Four hundred sixty-sixth 32-bits of PCIE type 0 config space
* (VC Transmit Arbitration Register 2)
*/
-union cvmx_pcieepx_cfg465
-{
+union cvmx_pcieepx_cfg465 {
uint32_t u32;
- struct cvmx_pcieepx_cfg465_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg465_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t wrr_vc7 : 8; /**< WRR Weight for VC7 */
uint32_t wrr_vc6 : 8; /**< WRR Weight for VC6 */
uint32_t wrr_vc5 : 8; /**< WRR Weight for VC5 */
@@ -4019,8 +5650,13 @@ union cvmx_pcieepx_cfg465
struct cvmx_pcieepx_cfg465_s cn52xxp1;
struct cvmx_pcieepx_cfg465_s cn56xx;
struct cvmx_pcieepx_cfg465_s cn56xxp1;
+ struct cvmx_pcieepx_cfg465_s cn61xx;
struct cvmx_pcieepx_cfg465_s cn63xx;
struct cvmx_pcieepx_cfg465_s cn63xxp1;
+ struct cvmx_pcieepx_cfg465_s cn66xx;
+ struct cvmx_pcieepx_cfg465_s cn68xx;
+ struct cvmx_pcieepx_cfg465_s cn68xxp1;
+ struct cvmx_pcieepx_cfg465_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t;
@@ -4030,12 +5666,10 @@ typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t;
* PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 0 config space
* (VC0 Posted Receive Queue Control)
*/
-union cvmx_pcieepx_cfg466
-{
+union cvmx_pcieepx_cfg466 {
uint32_t u32;
- struct cvmx_pcieepx_cfg466_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg466_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t rx_queue_order : 1; /**< VC Ordering for Receive Queues
Determines the VC ordering rule for the receive queues, used
only in the segmented-buffer configuration,
@@ -4087,8 +5721,13 @@ union cvmx_pcieepx_cfg466
struct cvmx_pcieepx_cfg466_s cn52xxp1;
struct cvmx_pcieepx_cfg466_s cn56xx;
struct cvmx_pcieepx_cfg466_s cn56xxp1;
+ struct cvmx_pcieepx_cfg466_s cn61xx;
struct cvmx_pcieepx_cfg466_s cn63xx;
struct cvmx_pcieepx_cfg466_s cn63xxp1;
+ struct cvmx_pcieepx_cfg466_s cn66xx;
+ struct cvmx_pcieepx_cfg466_s cn68xx;
+ struct cvmx_pcieepx_cfg466_s cn68xxp1;
+ struct cvmx_pcieepx_cfg466_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t;
@@ -4098,12 +5737,10 @@ typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t;
* PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 0 config space
* (VC0 Non-Posted Receive Queue Control)
*/
-union cvmx_pcieepx_cfg467
-{
+union cvmx_pcieepx_cfg467 {
uint32_t u32;
- struct cvmx_pcieepx_cfg467_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg467_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_24_31 : 8;
uint32_t queue_mode : 3; /**< VC0 Non-Posted TLP Queue Mode
The operating mode of the Non-Posted receive queue for VC0,
@@ -4137,8 +5774,13 @@ union cvmx_pcieepx_cfg467
struct cvmx_pcieepx_cfg467_s cn52xxp1;
struct cvmx_pcieepx_cfg467_s cn56xx;
struct cvmx_pcieepx_cfg467_s cn56xxp1;
+ struct cvmx_pcieepx_cfg467_s cn61xx;
struct cvmx_pcieepx_cfg467_s cn63xx;
struct cvmx_pcieepx_cfg467_s cn63xxp1;
+ struct cvmx_pcieepx_cfg467_s cn66xx;
+ struct cvmx_pcieepx_cfg467_s cn68xx;
+ struct cvmx_pcieepx_cfg467_s cn68xxp1;
+ struct cvmx_pcieepx_cfg467_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t;
@@ -4148,12 +5790,10 @@ typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t;
* PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 0 config space
* (VC0 Completion Receive Queue Control)
*/
-union cvmx_pcieepx_cfg468
-{
+union cvmx_pcieepx_cfg468 {
uint32_t u32;
- struct cvmx_pcieepx_cfg468_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg468_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_24_31 : 8;
uint32_t queue_mode : 3; /**< VC0 Completion TLP Queue Mode
The operating mode of the Completion receive queue for VC0,
@@ -4187,8 +5827,13 @@ union cvmx_pcieepx_cfg468
struct cvmx_pcieepx_cfg468_s cn52xxp1;
struct cvmx_pcieepx_cfg468_s cn56xx;
struct cvmx_pcieepx_cfg468_s cn56xxp1;
+ struct cvmx_pcieepx_cfg468_s cn61xx;
struct cvmx_pcieepx_cfg468_s cn63xx;
struct cvmx_pcieepx_cfg468_s cn63xxp1;
+ struct cvmx_pcieepx_cfg468_s cn66xx;
+ struct cvmx_pcieepx_cfg468_s cn68xx;
+ struct cvmx_pcieepx_cfg468_s cn68xxp1;
+ struct cvmx_pcieepx_cfg468_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t;
@@ -4198,12 +5843,10 @@ typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t;
* PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space
* (VC0 Posted Buffer Depth)
*/
-union cvmx_pcieepx_cfg490
-{
+union cvmx_pcieepx_cfg490 {
uint32_t u32;
- struct cvmx_pcieepx_cfg490_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg490_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_26_31 : 6;
uint32_t header_depth : 10; /**< VC0 Posted Header Queue Depth
Sets the number of entries in the Posted header queue for VC0
@@ -4227,8 +5870,13 @@ union cvmx_pcieepx_cfg490
struct cvmx_pcieepx_cfg490_s cn52xxp1;
struct cvmx_pcieepx_cfg490_s cn56xx;
struct cvmx_pcieepx_cfg490_s cn56xxp1;
+ struct cvmx_pcieepx_cfg490_s cn61xx;
struct cvmx_pcieepx_cfg490_s cn63xx;
struct cvmx_pcieepx_cfg490_s cn63xxp1;
+ struct cvmx_pcieepx_cfg490_s cn66xx;
+ struct cvmx_pcieepx_cfg490_s cn68xx;
+ struct cvmx_pcieepx_cfg490_s cn68xxp1;
+ struct cvmx_pcieepx_cfg490_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t;
@@ -4238,12 +5886,10 @@ typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t;
* PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space
* (VC0 Non-Posted Buffer Depth)
*/
-union cvmx_pcieepx_cfg491
-{
+union cvmx_pcieepx_cfg491 {
uint32_t u32;
- struct cvmx_pcieepx_cfg491_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg491_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_26_31 : 6;
uint32_t header_depth : 10; /**< VC0 Non-Posted Header Queue Depth
Sets the number of entries in the Non-Posted header queue for
@@ -4267,8 +5913,13 @@ union cvmx_pcieepx_cfg491
struct cvmx_pcieepx_cfg491_s cn52xxp1;
struct cvmx_pcieepx_cfg491_s cn56xx;
struct cvmx_pcieepx_cfg491_s cn56xxp1;
+ struct cvmx_pcieepx_cfg491_s cn61xx;
struct cvmx_pcieepx_cfg491_s cn63xx;
struct cvmx_pcieepx_cfg491_s cn63xxp1;
+ struct cvmx_pcieepx_cfg491_s cn66xx;
+ struct cvmx_pcieepx_cfg491_s cn68xx;
+ struct cvmx_pcieepx_cfg491_s cn68xxp1;
+ struct cvmx_pcieepx_cfg491_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t;
@@ -4278,12 +5929,10 @@ typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t;
* PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space
* (VC0 Completion Buffer Depth)
*/
-union cvmx_pcieepx_cfg492
-{
+union cvmx_pcieepx_cfg492 {
uint32_t u32;
- struct cvmx_pcieepx_cfg492_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg492_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_26_31 : 6;
uint32_t header_depth : 10; /**< VC0 Completion Header Queue Depth
Sets the number of entries in the Completion header queue for
@@ -4307,8 +5956,13 @@ union cvmx_pcieepx_cfg492
struct cvmx_pcieepx_cfg492_s cn52xxp1;
struct cvmx_pcieepx_cfg492_s cn56xx;
struct cvmx_pcieepx_cfg492_s cn56xxp1;
+ struct cvmx_pcieepx_cfg492_s cn61xx;
struct cvmx_pcieepx_cfg492_s cn63xx;
struct cvmx_pcieepx_cfg492_s cn63xxp1;
+ struct cvmx_pcieepx_cfg492_s cn66xx;
+ struct cvmx_pcieepx_cfg492_s cn68xx;
+ struct cvmx_pcieepx_cfg492_s cn68xxp1;
+ struct cvmx_pcieepx_cfg492_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t;
@@ -4318,12 +5972,10 @@ typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t;
* PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 0 config space
* (Port Logic Register (Gen2))
*/
-union cvmx_pcieepx_cfg515
-{
+union cvmx_pcieepx_cfg515 {
uint32_t u32;
- struct cvmx_pcieepx_cfg515_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg515_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_21_31 : 11;
uint32_t s_d_e : 1; /**< SEL_DE_EMPHASIS
Used to set the de-emphasis level for upstream ports. */
@@ -4334,8 +5986,8 @@ union cvmx_pcieepx_cfg515
Indicates the voltage level the PHY should drive. When set to
1, indicates Full Swing. When set to 0, indicates Low Swing */
uint32_t dsc : 1; /**< Directed Speed Change
- Indicates to the LTSSM whether or not to initiate a speed
- change. */
+ o a write of '1' will initiate a speed change
+ o always reads a zero */
uint32_t le : 9; /**< Lane Enable
Indicates the number of lanes to check for exit from electrical
idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2,
@@ -4361,8 +6013,13 @@ union cvmx_pcieepx_cfg515
uint32_t reserved_21_31 : 11;
#endif
} s;
+ struct cvmx_pcieepx_cfg515_s cn61xx;
struct cvmx_pcieepx_cfg515_s cn63xx;
struct cvmx_pcieepx_cfg515_s cn63xxp1;
+ struct cvmx_pcieepx_cfg515_s cn66xx;
+ struct cvmx_pcieepx_cfg515_s cn68xx;
+ struct cvmx_pcieepx_cfg515_s cn68xxp1;
+ struct cvmx_pcieepx_cfg515_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t;
@@ -4372,12 +6029,10 @@ typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t;
* PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 0 config space
* (PHY Status Register)
*/
-union cvmx_pcieepx_cfg516
-{
+union cvmx_pcieepx_cfg516 {
uint32_t u32;
- struct cvmx_pcieepx_cfg516_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg516_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t phy_stat : 32; /**< PHY Status */
#else
uint32_t phy_stat : 32;
@@ -4387,8 +6042,13 @@ union cvmx_pcieepx_cfg516
struct cvmx_pcieepx_cfg516_s cn52xxp1;
struct cvmx_pcieepx_cfg516_s cn56xx;
struct cvmx_pcieepx_cfg516_s cn56xxp1;
+ struct cvmx_pcieepx_cfg516_s cn61xx;
struct cvmx_pcieepx_cfg516_s cn63xx;
struct cvmx_pcieepx_cfg516_s cn63xxp1;
+ struct cvmx_pcieepx_cfg516_s cn66xx;
+ struct cvmx_pcieepx_cfg516_s cn68xx;
+ struct cvmx_pcieepx_cfg516_s cn68xxp1;
+ struct cvmx_pcieepx_cfg516_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t;
@@ -4398,12 +6058,10 @@ typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t;
* PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 0 config space
* (PHY Control Register)
*/
-union cvmx_pcieepx_cfg517
-{
+union cvmx_pcieepx_cfg517 {
uint32_t u32;
- struct cvmx_pcieepx_cfg517_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pcieepx_cfg517_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t phy_ctrl : 32; /**< PHY Control */
#else
uint32_t phy_ctrl : 32;
@@ -4413,8 +6071,13 @@ union cvmx_pcieepx_cfg517
struct cvmx_pcieepx_cfg517_s cn52xxp1;
struct cvmx_pcieepx_cfg517_s cn56xx;
struct cvmx_pcieepx_cfg517_s cn56xxp1;
+ struct cvmx_pcieepx_cfg517_s cn61xx;
struct cvmx_pcieepx_cfg517_s cn63xx;
struct cvmx_pcieepx_cfg517_s cn63xxp1;
+ struct cvmx_pcieepx_cfg517_s cn66xx;
+ struct cvmx_pcieepx_cfg517_s cn68xx;
+ struct cvmx_pcieepx_cfg517_s cn68xxp1;
+ struct cvmx_pcieepx_cfg517_s cnf71xx;
};
typedef union cvmx_pcieepx_cfg517 cvmx_pcieepx_cfg517_t;