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-rw-r--r--cvmx-pci-defs.h537
1 files changed, 204 insertions, 333 deletions
diff --git a/cvmx-pci-defs.h b/cvmx-pci-defs.h
index df38d8d0361e..28be95446314 100644
--- a/cvmx-pci-defs.h
+++ b/cvmx-pci-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_PCI_TYPEDEFS_H__
-#define __CVMX_PCI_TYPEDEFS_H__
+#ifndef __CVMX_PCI_DEFS_H__
+#define __CVMX_PCI_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset)
@@ -776,12 +776,10 @@ static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void)
* Contains address index and control bits for access to memory ranges of Bar-1,
* when PCI supplied address-bits [26:22] == X.
*/
-union cvmx_pci_bar1_indexx
-{
+union cvmx_pci_bar1_indexx {
uint32_t u32;
- struct cvmx_pci_bar1_indexx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_bar1_indexx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_18_31 : 14;
uint32_t addr_idx : 14; /**< Address bits [35:22] sent to L2C */
uint32_t ca : 1; /**< Set '1' when access is not to be cached in L2. */
@@ -812,12 +810,10 @@ typedef union cvmx_pci_bar1_indexx cvmx_pci_bar1_indexx_t;
*
* Contains the bist results for the PNI memories.
*/
-union cvmx_pci_bist_reg
-{
+union cvmx_pci_bist_reg {
uint64_t u64;
- struct cvmx_pci_bist_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_bist_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t rsp_bs : 1; /**< Bist Status For b12_rsp_fifo_bist
The value of this register is available 100,000
@@ -900,12 +896,10 @@ typedef union cvmx_pci_bist_reg cvmx_pci_bist_reg_t;
*
* This register contains the first 32-bits of the PCI config space registers
*/
-union cvmx_pci_cfg00
-{
+union cvmx_pci_cfg00 {
uint32_t u32;
- struct cvmx_pci_cfg00_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg00_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t devid : 16; /**< This is the device ID for OCTEON (90nm shhrink) */
uint32_t vendid : 16; /**< This is the Cavium's vendor ID */
#else
@@ -929,12 +923,10 @@ typedef union cvmx_pci_cfg00 cvmx_pci_cfg00_t;
* PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register)
*
*/
-union cvmx_pci_cfg01
-{
+union cvmx_pci_cfg01 {
uint32_t u32;
- struct cvmx_pci_cfg01_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg01_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dpe : 1; /**< Detected Parity Error */
uint32_t sse : 1; /**< Signaled System Error */
uint32_t rma : 1; /**< Received Master Abort */
@@ -1016,12 +1008,10 @@ typedef union cvmx_pci_cfg01 cvmx_pci_cfg01_t;
* PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID)
*
*/
-union cvmx_pci_cfg02
-{
+union cvmx_pci_cfg02 {
uint32_t u32;
- struct cvmx_pci_cfg02_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg02_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t cc : 24; /**< Class Code (Processor/MIPS)
(was 0x100000 in pass 1 and pass 2) */
uint32_t rid : 8; /**< Revision ID
@@ -1047,12 +1037,10 @@ typedef union cvmx_pci_cfg02 cvmx_pci_cfg02_t;
* PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size)
*
*/
-union cvmx_pci_cfg03
-{
+union cvmx_pci_cfg03 {
uint32_t u32;
- struct cvmx_pci_cfg03_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg03_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t bcap : 1; /**< BIST Capable */
uint32_t brb : 1; /**< BIST Request/busy bit
Note: OCTEON does not support PCI BIST, therefore
@@ -1096,12 +1084,10 @@ typedef union cvmx_pci_cfg03 cvmx_pci_cfg03_t;
* [11:4]: RAZ (to imply 4KB space)
* [31:12]: RW (User may define base address)
*/
-union cvmx_pci_cfg04
-{
+union cvmx_pci_cfg04 {
uint32_t u32;
- struct cvmx_pci_cfg04_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg04_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lbase : 20; /**< Base Address[31:12]
Base Address[30:12] read as zero if
PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */
@@ -1133,12 +1119,10 @@ typedef union cvmx_pci_cfg04 cvmx_pci_cfg04_t;
* PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High)
*
*/
-union cvmx_pci_cfg05
-{
+union cvmx_pci_cfg05 {
uint32_t u32;
- struct cvmx_pci_cfg05_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg05_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t hbase : 32; /**< Base Address[63:32] */
#else
uint32_t hbase : 32;
@@ -1166,12 +1150,10 @@ typedef union cvmx_pci_cfg05 cvmx_pci_cfg05_t;
* [26:4]: RAZ (to imply 128MB space)
* [31:27]: RW (User may define base address)
*/
-union cvmx_pci_cfg06
-{
+union cvmx_pci_cfg06 {
uint32_t u32;
- struct cvmx_pci_cfg06_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg06_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lbase : 5; /**< Base Address[31:27]
In pass 3+:
Base Address[29:27] read as zero if
@@ -1207,12 +1189,10 @@ typedef union cvmx_pci_cfg06 cvmx_pci_cfg06_t;
* PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High)
*
*/
-union cvmx_pci_cfg07
-{
+union cvmx_pci_cfg07 {
uint32_t u32;
- struct cvmx_pci_cfg07_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg07_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t hbase : 32; /**< Base Address[63:32] */
#else
uint32_t hbase : 32;
@@ -1239,12 +1219,10 @@ typedef union cvmx_pci_cfg07 cvmx_pci_cfg07_t;
* [3]: 1 (Prefetchable)
* [31:4]: RAZ
*/
-union cvmx_pci_cfg08
-{
+union cvmx_pci_cfg08 {
uint32_t u32;
- struct cvmx_pci_cfg08_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg08_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t lbasez : 28; /**< Base Address[31:4] (Read as Zero) */
uint32_t pf : 1; /**< Prefetchable Space */
uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
@@ -1272,12 +1250,10 @@ typedef union cvmx_pci_cfg08 cvmx_pci_cfg08_t;
* PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High)
*
*/
-union cvmx_pci_cfg09
-{
+union cvmx_pci_cfg09 {
uint32_t u32;
- struct cvmx_pci_cfg09_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg09_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t hbase : 25; /**< Base Address[63:39] */
uint32_t hbasez : 7; /**< Base Address[38:31] (Read as Zero) */
#else
@@ -1301,12 +1277,10 @@ typedef union cvmx_pci_cfg09 cvmx_pci_cfg09_t;
* PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer)
*
*/
-union cvmx_pci_cfg10
-{
+union cvmx_pci_cfg10 {
uint32_t u32;
- struct cvmx_pci_cfg10_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg10_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t cisp : 32; /**< CardBus CIS Pointer (UNUSED) */
#else
uint32_t cisp : 32;
@@ -1328,12 +1302,10 @@ typedef union cvmx_pci_cfg10 cvmx_pci_cfg10_t;
* PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register)
*
*/
-union cvmx_pci_cfg11
-{
+union cvmx_pci_cfg11 {
uint32_t u32;
- struct cvmx_pci_cfg11_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg11_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ssid : 16; /**< SubSystem ID */
uint32_t ssvid : 16; /**< Subsystem Vendor ID */
#else
@@ -1357,12 +1329,10 @@ typedef union cvmx_pci_cfg11 cvmx_pci_cfg11_t;
* PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register)
*
*/
-union cvmx_pci_cfg12
-{
+union cvmx_pci_cfg12 {
uint32_t u32;
- struct cvmx_pci_cfg12_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg12_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t erbar : 16; /**< Expansion ROM Base Address[31:16] 64KB in size */
uint32_t erbarz : 5; /**< Expansion ROM Base Base Address (Read as Zero) */
uint32_t reserved_1_10 : 10;
@@ -1390,12 +1360,10 @@ typedef union cvmx_pci_cfg12 cvmx_pci_cfg12_t;
* PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register)
*
*/
-union cvmx_pci_cfg13
-{
+union cvmx_pci_cfg13 {
uint32_t u32;
- struct cvmx_pci_cfg13_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg13_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_8_31 : 24;
uint32_t cp : 8; /**< Capabilities Pointer */
#else
@@ -1419,12 +1387,10 @@ typedef union cvmx_pci_cfg13 cvmx_pci_cfg13_t;
* PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register)
*
*/
-union cvmx_pci_cfg15
-{
+union cvmx_pci_cfg15 {
uint32_t u32;
- struct cvmx_pci_cfg15_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg15_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t ml : 8; /**< Maximum Latency */
uint32_t mg : 8; /**< Minimum Grant */
uint32_t inta : 8; /**< Interrupt Pin (INTA#) */
@@ -1452,12 +1418,10 @@ typedef union cvmx_pci_cfg15 cvmx_pci_cfg15_t;
* PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register)
*
*/
-union cvmx_pci_cfg16
-{
+union cvmx_pci_cfg16 {
uint32_t u32;
- struct cvmx_pci_cfg16_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg16_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t trdnpr : 1; /**< Target Read Delayed Transaction for I/O and
non-prefetchable regions discarded. */
uint32_t trdard : 1; /**< Target Read Delayed Transaction for all regions
@@ -1547,12 +1511,10 @@ typedef union cvmx_pci_cfg16 cvmx_pci_cfg16_t;
* PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message
* Enable Register)
*/
-union cvmx_pci_cfg17
-{
+union cvmx_pci_cfg17 {
uint32_t u32;
- struct cvmx_pci_cfg17_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg17_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t tscme : 32; /**< Target Split Completion Message Enable
[31:30]: 00
[29]: Split Completion Error Indication
@@ -1582,12 +1544,10 @@ typedef union cvmx_pci_cfg17 cvmx_pci_cfg17_t;
* PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request
* Pending Sequences)
*/
-union cvmx_pci_cfg18
-{
+union cvmx_pci_cfg18 {
uint32_t u32;
- struct cvmx_pci_cfg18_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg18_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t tdsrps : 32; /**< Target Delayed/Split Request Pending Sequences
The application uses this address to remove a
pending split sequence from the target queue by
@@ -1618,12 +1578,10 @@ typedef union cvmx_pci_cfg18 cvmx_pci_cfg18_t;
* PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register)
*
*/
-union cvmx_pci_cfg19
-{
+union cvmx_pci_cfg19 {
uint32_t u32;
- struct cvmx_pci_cfg19_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg19_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t mrbcm : 1; /**< Master Request (Memory Read) Byte Count/Byte
Enable select.
0 = Byte Enables valid. In PCI mode, a burst
@@ -1761,12 +1719,10 @@ typedef union cvmx_pci_cfg19 cvmx_pci_cfg19_t;
* PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending)
*
*/
-union cvmx_pci_cfg20
-{
+union cvmx_pci_cfg20 {
uint32_t u32;
- struct cvmx_pci_cfg20_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg20_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t mdsp : 32; /**< Master Deferred/Split sequence Pending
For OCTEON, this register is intended for debug use
only and MUST NEVER be written with anything other
@@ -1791,12 +1747,10 @@ typedef union cvmx_pci_cfg20 cvmx_pci_cfg20_t;
* PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register)
*
*/
-union cvmx_pci_cfg21
-{
+union cvmx_pci_cfg21 {
uint32_t u32;
- struct cvmx_pci_cfg21_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg21_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t scmre : 32; /**< Master Split Completion message received with
error message.
For OCTEON, this register is intended for debug use
@@ -1822,12 +1776,10 @@ typedef union cvmx_pci_cfg21 cvmx_pci_cfg21_t;
* PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register)
*
*/
-union cvmx_pci_cfg22
-{
+union cvmx_pci_cfg22 {
uint32_t u32;
- struct cvmx_pci_cfg22_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg22_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t mac : 7; /**< Master Arbiter Control
[31:26]: Used only in Fixed Priority mode
(when [25]=1)
@@ -1890,12 +1842,10 @@ typedef union cvmx_pci_cfg22 cvmx_pci_cfg22_t;
* PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register)
*
*/
-union cvmx_pci_cfg56
-{
+union cvmx_pci_cfg56 {
uint32_t u32;
- struct cvmx_pci_cfg56_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg56_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_23_31 : 9;
uint32_t most : 3; /**< Maximum outstanding Split transactions
Encoded Value \#Max outstanding splits
@@ -1943,12 +1893,10 @@ typedef union cvmx_pci_cfg56 cvmx_pci_cfg56_t;
* PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register)
*
*/
-union cvmx_pci_cfg57
-{
+union cvmx_pci_cfg57 {
uint32_t u32;
- struct cvmx_pci_cfg57_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg57_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_30_31 : 2;
uint32_t scemr : 1; /**< Split Completion Error Message Received */
uint32_t mcrsd : 3; /**< Maximum Cumulative Read Size designed */
@@ -1999,12 +1947,10 @@ typedef union cvmx_pci_cfg57 cvmx_pci_cfg57_t;
* PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register)
*
*/
-union cvmx_pci_cfg58
-{
+union cvmx_pci_cfg58 {
uint32_t u32;
- struct cvmx_pci_cfg58_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg58_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pmes : 5; /**< PME Support (D0 to D3cold) */
uint32_t d2s : 1; /**< D2_Support */
uint32_t d1s : 1; /**< D1_Support */
@@ -2049,12 +1995,10 @@ typedef union cvmx_pci_cfg58 cvmx_pci_cfg58_t;
* PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s))
*
*/
-union cvmx_pci_cfg59
-{
+union cvmx_pci_cfg59 {
uint32_t u32;
- struct cvmx_pci_cfg59_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg59_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pmdia : 8; /**< Power Management data input from application
(PME_DATA) */
uint32_t bpccen : 1; /**< BPCC_En (bus power/clock control) enable */
@@ -2104,12 +2048,10 @@ typedef union cvmx_pci_cfg59 cvmx_pci_cfg59_t;
* PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register)
*
*/
-union cvmx_pci_cfg60
-{
+union cvmx_pci_cfg60 {
uint32_t u32;
- struct cvmx_pci_cfg60_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg60_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_24_31 : 8;
uint32_t m64 : 1; /**< 32/64 b message */
uint32_t mme : 3; /**< Multiple Message Enable(1,2,4,8,16,32) */
@@ -2143,12 +2085,10 @@ typedef union cvmx_pci_cfg60 cvmx_pci_cfg60_t;
* PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register)
*
*/
-union cvmx_pci_cfg61
-{
+union cvmx_pci_cfg61 {
uint32_t u32;
- struct cvmx_pci_cfg61_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg61_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t msi31t2 : 30; /**< App Specific MSI Address [31:2] */
uint32_t reserved_0_1 : 2;
#else
@@ -2172,12 +2112,10 @@ typedef union cvmx_pci_cfg61 cvmx_pci_cfg61_t;
* PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register)
*
*/
-union cvmx_pci_cfg62
-{
+union cvmx_pci_cfg62 {
uint32_t u32;
- struct cvmx_pci_cfg62_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg62_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t msi : 32; /**< MSI Address [63:32] */
#else
uint32_t msi : 32;
@@ -2199,12 +2137,10 @@ typedef union cvmx_pci_cfg62 cvmx_pci_cfg62_t;
* PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register)
*
*/
-union cvmx_pci_cfg63
-{
+union cvmx_pci_cfg63 {
uint32_t u32;
- struct cvmx_pci_cfg63_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cfg63_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_16_31 : 16;
uint32_t msimd : 16; /**< MSI Message Data */
#else
@@ -2229,12 +2165,10 @@ typedef union cvmx_pci_cfg63 cvmx_pci_cfg63_t;
*
* This register is provided to software as a means to determine PCI Bus Type/Speed.
*/
-union cvmx_pci_cnt_reg
-{
+union cvmx_pci_cnt_reg {
uint64_t u64;
- struct cvmx_pci_cnt_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_cnt_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_38_63 : 26;
uint64_t hm_pcix : 1; /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX)
This field represents what OCTEON(in Host mode)
@@ -2348,12 +2282,10 @@ typedef union cvmx_pci_cnt_reg cvmx_pci_cnt_reg_t;
*
* Control status register accessable from both PCI and NCB.
*/
-union cvmx_pci_ctl_status_2
-{
+union cvmx_pci_ctl_status_2 {
uint32_t u32;
- struct cvmx_pci_ctl_status_2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_ctl_status_2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_29_31 : 3;
uint32_t bb1_hole : 3; /**< Big BAR 1 Hole
NOT IN PASS 1 NOR PASS 2
@@ -2598,9 +2530,8 @@ union cvmx_pci_ctl_status_2
#endif
} s;
struct cvmx_pci_ctl_status_2_s cn30xx;
- struct cvmx_pci_ctl_status_2_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_ctl_status_2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_20_31 : 12;
uint32_t erst_n : 1; /**< Reset active Low. */
uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN])
@@ -2727,12 +2658,10 @@ typedef union cvmx_pci_ctl_status_2 cvmx_pci_ctl_status_2_t;
* The value to write to the doorbell 0 register. The value in this register is acted upon when the
* least-significant-byte of this register is written.
*/
-union cvmx_pci_dbellx
-{
+union cvmx_pci_dbellx {
uint32_t u32;
- struct cvmx_pci_dbellx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_dbellx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_16_31 : 16;
uint32_t inc_val : 16; /**< Software writes this register with the
number of new Instructions to be processed
@@ -2761,12 +2690,10 @@ typedef union cvmx_pci_dbellx cvmx_pci_dbellx_t;
* Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the
* least-significant-byte of this register is written.
*/
-union cvmx_pci_dma_cntx
-{
+union cvmx_pci_dma_cntx {
uint32_t u32;
- struct cvmx_pci_dma_cntx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_dma_cntx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dma_cnt : 32; /**< Update with the number of DMAs completed or the
number of bytes sent for DMA's associated with
this counter. When this register is written the
@@ -2793,12 +2720,10 @@ typedef union cvmx_pci_dma_cntx cvmx_pci_dma_cntx_t;
*
* Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value.
*/
-union cvmx_pci_dma_int_levx
-{
+union cvmx_pci_dma_int_levx {
uint32_t u32;
- struct cvmx_pci_dma_int_levx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_dma_int_levx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pkt_cnt : 32; /**< When PCI_DMA_CNT0 exceeds the value in this
DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */
#else
@@ -2822,12 +2747,10 @@ typedef union cvmx_pci_dma_int_levx cvmx_pci_dma_int_levx_t;
*
* Time to wait from DMA being sent before issuing an interrupt.
*/
-union cvmx_pci_dma_timex
-{
+union cvmx_pci_dma_timex {
uint32_t u32;
- struct cvmx_pci_dma_timex_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_dma_timex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t dma_time : 32; /**< Number of PCI clock cycle to wait before
setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2.
After PCI_DMA_CNT0 becomes non-zero.
@@ -2854,12 +2777,10 @@ typedef union cvmx_pci_dma_timex cvmx_pci_dma_timex_t;
*
* The number of instructions to be fetched by the Instruction-0 Engine.
*/
-union cvmx_pci_instr_countx
-{
+union cvmx_pci_instr_countx {
uint32_t u32;
- struct cvmx_pci_instr_countx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_instr_countx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t icnt : 32; /**< Number of Instructions to be fetched by the
Instruction Engine.
A write of any non zero value to this register
@@ -2885,12 +2806,10 @@ typedef union cvmx_pci_instr_countx cvmx_pci_instr_countx_t;
*
* Enables interrupt bits in the PCI_INT_SUM register.
*/
-union cvmx_pci_int_enb
-{
+union cvmx_pci_int_enb {
uint64_t u64;
- struct cvmx_pci_int_enb_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
@@ -2964,9 +2883,8 @@ union cvmx_pci_int_enb
uint64_t reserved_34_63 : 30;
#endif
} s;
- struct cvmx_pci_int_enb_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_enb_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
@@ -3032,9 +2950,8 @@ union cvmx_pci_int_enb
uint64_t reserved_34_63 : 30;
#endif
} cn30xx;
- struct cvmx_pci_int_enb_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_enb_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
@@ -3119,12 +3036,10 @@ typedef union cvmx_pci_int_enb cvmx_pci_int_enb_t;
*
* Enables interrupt bits in the PCI_INT_SUM2 register.
*/
-union cvmx_pci_int_enb2
-{
+union cvmx_pci_int_enb2 {
uint64_t u64;
- struct cvmx_pci_int_enb2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
@@ -3198,9 +3113,8 @@ union cvmx_pci_int_enb2
uint64_t reserved_34_63 : 30;
#endif
} s;
- struct cvmx_pci_int_enb2_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_enb2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
@@ -3266,9 +3180,8 @@ union cvmx_pci_int_enb2
uint64_t reserved_34_63 : 30;
#endif
} cn30xx;
- struct cvmx_pci_int_enb2_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_enb2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
@@ -3353,12 +3266,10 @@ typedef union cvmx_pci_int_enb2 cvmx_pci_int_enb2_t;
*
* The PCI Interrupt Summary Register.
*/
-union cvmx_pci_int_sum
-{
+union cvmx_pci_int_sum {
uint64_t u64;
- struct cvmx_pci_int_sum_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2,
when the mem area is disabled. */
@@ -3497,9 +3408,8 @@ union cvmx_pci_int_sum
uint64_t reserved_34_63 : 30;
#endif
} s;
- struct cvmx_pci_int_sum_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_sum_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2,
when the mem area is disabled. */
@@ -3609,9 +3519,8 @@ union cvmx_pci_int_sum
uint64_t reserved_34_63 : 30;
#endif
} cn30xx;
- struct cvmx_pci_int_sum_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_sum_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2,
when the mem area is disabled. */
@@ -3747,12 +3656,10 @@ typedef union cvmx_pci_int_sum cvmx_pci_int_sum_t;
*
* The PCI Interrupt Summary2 Register copy used for RSL interrupts.
*/
-union cvmx_pci_int_sum2
-{
+union cvmx_pci_int_sum2 {
uint64_t u64;
- struct cvmx_pci_int_sum2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_sum2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2,
when the mem area is disabled. */
@@ -3874,9 +3781,8 @@ union cvmx_pci_int_sum2
uint64_t reserved_34_63 : 30;
#endif
} s;
- struct cvmx_pci_int_sum2_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_sum2_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2,
when the mem area is disabled. */
@@ -3969,9 +3875,8 @@ union cvmx_pci_int_sum2
uint64_t reserved_34_63 : 30;
#endif
} cn30xx;
- struct cvmx_pci_int_sum2_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_int_sum2_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63 : 30;
uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2,
when the mem area is disabled. */
@@ -4091,12 +3996,10 @@ typedef union cvmx_pci_int_sum2 cvmx_pci_int_sum2_t;
* A bit is set in this register relative to the vector received during a MSI. The value in this
* register is acted upon when the least-significant-byte of this register is written.
*/
-union cvmx_pci_msi_rcv
-{
+union cvmx_pci_msi_rcv {
uint32_t u32;
- struct cvmx_pci_msi_rcv_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_6_31 : 26;
uint32_t intr : 6; /**< When an MSI is received on the PCI the bit selected
by data [5:0] will be set in this register. To
@@ -4128,12 +4031,10 @@ typedef union cvmx_pci_msi_rcv cvmx_pci_msi_rcv_t;
* buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the
* least-significant-byte of this register is written.
*/
-union cvmx_pci_pkt_creditsx
-{
+union cvmx_pci_pkt_creditsx {
uint32_t u32;
- struct cvmx_pci_pkt_creditsx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_pkt_creditsx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pkt_cnt : 16; /**< The value written to this field will be
subtracted from PCI_PKTS_SENT0[PKT_CNT]. */
uint32_t ptr_cnt : 16; /**< This field value is added to the
@@ -4160,12 +4061,10 @@ typedef union cvmx_pci_pkt_creditsx cvmx_pci_pkt_creditsx_t;
*
* Number of packets sent to the host memory from PCI Output 0
*/
-union cvmx_pci_pkts_sentx
-{
+union cvmx_pci_pkts_sentx {
uint32_t u32;
- struct cvmx_pci_pkts_sentx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_pkts_sentx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pkt_cnt : 32; /**< Each time a packet is written to the memory via
PCI from PCI Output 0, this counter is
incremented by 1 or the byte count of the packet
@@ -4191,12 +4090,10 @@ typedef union cvmx_pci_pkts_sentx cvmx_pci_pkts_sentx_t;
*
* Interrupt when number of packets sent is equal to or greater than the register value.
*/
-union cvmx_pci_pkts_sent_int_levx
-{
+union cvmx_pci_pkts_sent_int_levx {
uint32_t u32;
- struct cvmx_pci_pkts_sent_int_levx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_pkts_sent_int_levx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pkt_cnt : 32; /**< When corresponding port's PCI_PKTS_SENT0 value
exceeds the value in this register, PCNT0 of the
PCI_INT_SUM and PCI_INT_SUM2 will be set. */
@@ -4221,12 +4118,10 @@ typedef union cvmx_pci_pkts_sent_int_levx cvmx_pci_pkts_sent_int_levx_t;
*
* Time to wait from packet being sent to host from Output-0 before issuing an interrupt.
*/
-union cvmx_pci_pkts_sent_timex
-{
+union cvmx_pci_pkts_sent_timex {
uint32_t u32;
- struct cvmx_pci_pkts_sent_timex_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_pkts_sent_timex_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t pkt_time : 32; /**< Number of PCI clock cycle to wait before
issuing an interrupt to the host when a
packet from this port has been sent to the
@@ -4253,12 +4148,10 @@ typedef union cvmx_pci_pkts_sent_timex cvmx_pci_pkts_sent_timex_t;
*
* Contains control inforamtion related to a received PCI Command 6.
*/
-union cvmx_pci_read_cmd_6
-{
+union cvmx_pci_read_cmd_6 {
uint32_t u32;
- struct cvmx_pci_read_cmd_6_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_read_cmd_6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_9_31 : 23;
uint32_t min_data : 6; /**< The number of words to have buffered in the PNI
before informing the PCIX-Core that we have
@@ -4296,12 +4189,10 @@ typedef union cvmx_pci_read_cmd_6 cvmx_pci_read_cmd_6_t;
*
* Contains control inforamtion related to a received PCI Command C.
*/
-union cvmx_pci_read_cmd_c
-{
+union cvmx_pci_read_cmd_c {
uint32_t u32;
- struct cvmx_pci_read_cmd_c_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_read_cmd_c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_9_31 : 23;
uint32_t min_data : 6; /**< The number of words to have buffered in the PNI
before informing the PCIX-Core that we have
@@ -4339,12 +4230,10 @@ typedef union cvmx_pci_read_cmd_c cvmx_pci_read_cmd_c_t;
*
* Contains control inforamtion related to a received PCI Command 6.
*/
-union cvmx_pci_read_cmd_e
-{
+union cvmx_pci_read_cmd_e {
uint32_t u32;
- struct cvmx_pci_read_cmd_e_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_read_cmd_e_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_9_31 : 23;
uint32_t min_data : 6; /**< The number of words to have buffered in the PNI
before informaing the PCIX-Core that we have
@@ -4382,12 +4271,10 @@ typedef union cvmx_pci_read_cmd_e cvmx_pci_read_cmd_e_t;
*
* The address to start reading Instructions from for Input-3.
*/
-union cvmx_pci_read_timeout
-{
+union cvmx_pci_read_timeout {
uint64_t u64;
- struct cvmx_pci_read_timeout_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_read_timeout_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t enb : 1; /**< Enable the use of the Timeout function. */
uint64_t cnt : 31; /**< The number of eclk cycles to wait after issuing
@@ -4418,12 +4305,10 @@ typedef union cvmx_pci_read_timeout cvmx_pci_read_timeout_t;
* This register contains the Master Split Completion Message(SCM) generated when a master split
* transaction is aborted.
*/
-union cvmx_pci_scm_reg
-{
+union cvmx_pci_scm_reg {
uint64_t u64;
- struct cvmx_pci_scm_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_scm_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t scm : 32; /**< Contains the Split Completion Message (SCM)
driven when a master-split transaction is aborted.
@@ -4459,12 +4344,10 @@ typedef union cvmx_pci_scm_reg cvmx_pci_scm_reg_t;
* This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split
* transaction is aborted.
*/
-union cvmx_pci_tsr_reg
-{
+union cvmx_pci_tsr_reg {
uint64_t u64;
- struct cvmx_pci_tsr_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_tsr_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63 : 28;
uint64_t tsr : 36; /**< Contains the Target Split Attribute field when a
target-split transaction is aborted.
@@ -4504,12 +4387,10 @@ typedef union cvmx_pci_tsr_reg cvmx_pci_tsr_reg_t;
* UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA
* register is read.
*/
-union cvmx_pci_win_rd_addr
-{
+union cvmx_pci_win_rd_addr {
uint64_t u64;
- struct cvmx_pci_win_rd_addr_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_win_rd_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_49_63 : 15;
uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
read as '0'. */
@@ -4520,9 +4401,8 @@ union cvmx_pci_win_rd_addr
uint64_t reserved_49_63 : 15;
#endif
} s;
- struct cvmx_pci_win_rd_addr_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_win_rd_addr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_49_63 : 15;
uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
read as '0'. */
@@ -4545,9 +4425,8 @@ union cvmx_pci_win_rd_addr
#endif
} cn30xx;
struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
- struct cvmx_pci_win_rd_addr_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_win_rd_addr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_49_63 : 15;
uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
read as '0'. */
@@ -4584,12 +4463,10 @@ typedef union cvmx_pci_win_rd_addr cvmx_pci_win_rd_addr_t;
* Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR
* register was written.
*/
-union cvmx_pci_win_rd_data
-{
+union cvmx_pci_win_rd_data {
uint64_t u64;
- struct cvmx_pci_win_rd_data_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_win_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rd_data : 64; /**< The read data. */
#else
uint64_t rd_data : 64;
@@ -4613,12 +4490,10 @@ typedef union cvmx_pci_win_rd_data cvmx_pci_win_rd_data_t;
* Contains the address to be writen to when a write operation is started by writing the
* PCI_WIN_WR_DATA register (see below).
*/
-union cvmx_pci_win_wr_addr
-{
+union cvmx_pci_win_wr_addr {
uint64_t u64;
- struct cvmx_pci_win_wr_addr_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_win_wr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_49_63 : 15;
uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always
read as '0'. */
@@ -4657,12 +4532,10 @@ typedef union cvmx_pci_win_wr_addr cvmx_pci_win_wr_addr_t;
* Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register.
* Writing the least-significant-byte of this register will cause a write operation to take place.
*/
-union cvmx_pci_win_wr_data
-{
+union cvmx_pci_win_wr_data {
uint64_t u64;
- struct cvmx_pci_win_wr_data_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_win_wr_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this
register is written, the Window Write will take
place. */
@@ -4687,12 +4560,10 @@ typedef union cvmx_pci_win_wr_data cvmx_pci_win_wr_data_t;
*
* Contains the mask for the data in the PCI_WIN_WR_DATA Register.
*/
-union cvmx_pci_win_wr_mask
-{
+union cvmx_pci_win_wr_mask {
uint64_t u64;
- struct cvmx_pci_win_wr_mask_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_pci_win_wr_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t wr_mask : 8; /**< The data to be written. When a bit is set '1'
the corresponding byte will not be written. */