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-rw-r--r--cvmx-helper.c818
1 files changed, 692 insertions, 126 deletions
diff --git a/cvmx-helper.c b/cvmx-helper.c
index 3d637041c164..f0e4826e76a8 100644
--- a/cvmx-helper.c
+++ b/cvmx-helper.c
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
*
* Helper functions for common, but complicated tasks.
*
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*/
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
#include <linux/module.h>
@@ -57,12 +57,14 @@
#include <asm/octeon/cvmx-bootmem.h>
#include <asm/octeon/cvmx-sriox-defs.h>
#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-mio-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h>
#include <asm/octeon/cvmx-pip-defs.h>
#include <asm/octeon/cvmx-asxx-defs.h>
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-smix-defs.h>
#include <asm/octeon/cvmx-dbg-defs.h>
+#include <asm/octeon/cvmx-sso-defs.h>
#include <asm/octeon/cvmx-gmx.h>
#include <asm/octeon/cvmx-fpa.h>
@@ -74,6 +76,7 @@
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-helper-board.h>
#include <asm/octeon/cvmx-helper-errata.h>
+#include <asm/octeon/cvmx-helper-cfg.h>
#else
#include "executive-config.h"
#include "cvmx.h"
@@ -93,40 +96,42 @@
#include "cvmx-helper.h"
#include "cvmx-helper-board.h"
#include "cvmx-helper-errata.h"
+#include "cvmx-helper-cfg.h"
#endif
+/*
+ * internal functions that are not exported in the .h file but must be
+ * declared to make gcc happy.
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_get_link_info(int interface,
+ int port);
#ifdef CVMX_ENABLE_PKO_FUNCTIONS
/**
- * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
+ * cvmx_override_pko_queue_priority(int pko_port, uint64_t
* priorities[16]) is a function pointer. It is meant to allow
* customization of the PKO queue priorities based on the port
* number. Users should set this pointer to a function before
* calling any cvmx-helper operations.
*/
-CVMX_SHARED void (*cvmx_override_pko_queue_priority)(int pko_port, uint64_t priorities[16]) = NULL;
+CVMX_SHARED void (*cvmx_override_pko_queue_priority)(int ipd_port,
+ uint64_t *priorities) = NULL;
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
EXPORT_SYMBOL(cvmx_override_pko_queue_priority);
#endif
/**
* cvmx_override_ipd_port_setup(int ipd_port) is a function
- * pointer. It is meant to allow customization of the IPD port
- * setup before packet input/output comes online. It is called
- * after cvmx-helper does the default IPD configuration, but
- * before IPD is enabled. Users should set this pointer to a
+ * pointer. It is meant to allow customization of the IPD
+ * port/port kind setup before packet input/output comes online.
+ * It is called after cvmx-helper does the default IPD configuration,
+ * but before IPD is enabled. Users should set this pointer to a
* function before calling any cvmx-helper operations.
*/
CVMX_SHARED void (*cvmx_override_ipd_port_setup)(int ipd_port) = NULL;
-/* Port count per interface */
-static CVMX_SHARED int interface_port_count[6] = {0,};
-/* Port last configured link info index by IPD/PKO port */
-static CVMX_SHARED cvmx_helper_link_info_t port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
-
-
/**
* Return the number of interfaces the chip has. Each interface
* may have multiple ports. Most chips support two interfaces,
@@ -137,9 +142,17 @@ static CVMX_SHARED cvmx_helper_link_info_t port_link_info[CVMX_PIP_NUM_INPUT_POR
*/
int cvmx_helper_get_number_of_interfaces(void)
{
- if (OCTEON_IS_MODEL(OCTEON_CN63XX))
- return 6;
- else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ return 9;
+ else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+ if (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
+ return 7;
+ else
+ return 8;
+ else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return 6;
+ else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX))
return 4;
else
return 3;
@@ -160,7 +173,10 @@ EXPORT_SYMBOL(cvmx_helper_get_number_of_interfaces);
*/
int cvmx_helper_ports_on_interface(int interface)
{
- return interface_port_count[interface];
+ if (octeon_has_feature(OCTEON_FEATURE_PKND))
+ return cvmx_helper_interface_enumerate(interface);
+ else
+ return __cvmx_helper_get_num_ipd_ports(interface);
}
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
EXPORT_SYMBOL(cvmx_helper_ports_on_interface);
@@ -180,20 +196,113 @@ EXPORT_SYMBOL(cvmx_helper_ports_on_interface);
cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
{
cvmx_gmxx_inf_mode_t mode;
+
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ {
+ cvmx_mio_qlmx_cfg_t qlm_cfg;
+ switch(interface)
+ {
+ case 0:
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
+ /* QLM is disabled when QLM SPD is 15. */
+ if (qlm_cfg.s.qlm_spd == 15)
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+ if (qlm_cfg.s.qlm_cfg == 7)
+ return CVMX_HELPER_INTERFACE_MODE_RXAUI;
+ else if (qlm_cfg.s.qlm_cfg == 2)
+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
+ else if (qlm_cfg.s.qlm_cfg == 3)
+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
+ else
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ break;
+ case 1:
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
+ /* QLM is disabled when QLM SPD is 15. */
+ if (qlm_cfg.s.qlm_spd == 15)
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+ if (qlm_cfg.s.qlm_cfg == 7)
+ return CVMX_HELPER_INTERFACE_MODE_RXAUI;
+ else
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ break;
+ case 2:
+ case 3:
+ case 4:
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface));
+ /* QLM is disabled when QLM SPD is 15. */
+ if (qlm_cfg.s.qlm_spd == 15)
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+ if (qlm_cfg.s.qlm_cfg == 2)
+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
+ else if (qlm_cfg.s.qlm_cfg == 3)
+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
+ else
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ break;
+ case 5:
+ case 6:
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface - 4));
+ /* QLM is disabled when QLM SPD is 15. */
+ if (qlm_cfg.s.qlm_spd == 15)
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+ if (qlm_cfg.s.qlm_cfg == 1)
+ {
+ return CVMX_HELPER_INTERFACE_MODE_ILK;
+ }
+ else
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ break;
+ case 7:
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3));
+ /* QLM is disabled when QLM SPD is 15. */
+ if (qlm_cfg.s.qlm_spd == 15)
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ else if (qlm_cfg.s.qlm_cfg != 0)
+ {
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
+ if (qlm_cfg.s.qlm_cfg != 0)
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ }
+ return CVMX_HELPER_INTERFACE_MODE_NPI;
+ break;
+ case 8:
+ return CVMX_HELPER_INTERFACE_MODE_LOOP;
+ break;
+ default:
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ break;
+ }
+ }
+
if (interface == 2)
return CVMX_HELPER_INTERFACE_MODE_NPI;
if (interface == 3)
{
- if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ if (OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN6XXX)
+ || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
return CVMX_HELPER_INTERFACE_MODE_LOOP;
else
return CVMX_HELPER_INTERFACE_MODE_DISABLED;
}
- if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && (interface == 4 || interface == 5))
+ /* Only present in CN63XX & CN66XX Octeon model */
+ if ((OCTEON_IS_MODEL(OCTEON_CN63XX) && (interface == 4 || interface == 5))
+ || (OCTEON_IS_MODEL(OCTEON_CN66XX) && interface >= 4 && interface <= 7))
{
cvmx_sriox_status_reg_t sriox_status_reg;
+
+ /* cn66xx pass1.0 has only 2 SRIO interfaces. */
+ if ((interface == 5 || interface == 7) && OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(interface-4));
if (sriox_status_reg.s.srio)
return CVMX_HELPER_INTERFACE_MODE_SRIO;
@@ -201,6 +310,60 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
return CVMX_HELPER_INTERFACE_MODE_DISABLED;
}
+ /* Interface 5 always disabled in CN66XX */
+ if (OCTEON_IS_MODEL(OCTEON_CN66XX))
+ {
+ cvmx_mio_qlmx_cfg_t mio_qlm_cfg;
+
+ /* QLM2 is SGMII0 and QLM1 is SGMII1 */
+ if (interface == 0)
+ mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));
+ else if (interface == 1)
+ mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
+ else
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+ if (mio_qlm_cfg.s.qlm_spd == 15)
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+ if (mio_qlm_cfg.s.qlm_cfg == 9)
+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
+ else if (mio_qlm_cfg.s.qlm_cfg == 11)
+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
+ else
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ }
+ else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
+ {
+ cvmx_mio_qlmx_cfg_t qlm_cfg;
+
+ if (interface == 0)
+ {
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));
+ if (qlm_cfg.s.qlm_cfg == 2)
+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
+ else if (qlm_cfg.s.qlm_cfg == 3)
+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
+ else
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ }
+ else if (interface == 1)
+ {
+ /* If QLM 1 is PEV0/PEM1 mode, them QLM0 cannot be SGMII/XAUI */
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
+ if (qlm_cfg.s.qlm_cfg == 1)
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
+ if (qlm_cfg.s.qlm_cfg == 2)
+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
+ else if (qlm_cfg.s.qlm_cfg == 3)
+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
+ else
+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ }
+ }
+
if (interface == 0 && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 && cvmx_sysinfo_get()->board_rev_major == 1)
{
/* Lie about interface type of CN3005 board. This board has a switch on port 1 like
@@ -212,7 +375,13 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
}
/* Interface 1 is always disabled on CN31XX and CN30XX */
- if ((interface == 1) && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if ((interface == 1)
+ && (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN30XX)
+ || OCTEON_IS_MODEL(OCTEON_CN50XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN63XX)
+ || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
return CVMX_HELPER_INTERFACE_MODE_DISABLED;
mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
@@ -228,14 +397,14 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
default:return CVMX_HELPER_INTERFACE_MODE_DISABLED;
}
}
- else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ else if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
{
- switch(mode.cn63xx.mode)
- {
- case 0: return CVMX_HELPER_INTERFACE_MODE_SGMII;
- case 1: return CVMX_HELPER_INTERFACE_MODE_XAUI;
- default: return CVMX_HELPER_INTERFACE_MODE_DISABLED;
- }
+ switch(mode.cn63xx.mode)
+ {
+ case 0: return CVMX_HELPER_INTERFACE_MODE_SGMII;
+ case 1: return CVMX_HELPER_INTERFACE_MODE_XAUI;
+ default: return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+ }
}
else
{
@@ -264,8 +433,8 @@ EXPORT_SYMBOL(cvmx_helper_interface_get_mode);
* contents for a port. The setup performed here is controlled by
* the defines in executive-config.h.
*
- * @param ipd_port Port to configure. This follows the IPD numbering, not the
- * per interface numbering
+ * @param ipd_port Port/Port kind to configure. This follows the IPD numbering,
+ * not the per interface numbering
*
* @return Zero on success, negative on failure
*/
@@ -274,11 +443,33 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port)
cvmx_pip_prt_cfgx_t port_config;
cvmx_pip_prt_tagx_t tag_config;
- port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
- tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
+ if (octeon_has_feature(OCTEON_FEATURE_PKND))
+ {
+ int interface, index, pknd;
+ cvmx_pip_prt_cfgbx_t prt_cfgbx;
+
+ interface = cvmx_helper_get_interface_num(ipd_port);
+ index = cvmx_helper_get_interface_index_num(ipd_port);
+ pknd = cvmx_helper_get_pknd(interface, index);
+
+ port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(pknd));
+ tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(pknd));
+
+ port_config.s.qos = pknd & 0x7;
+
+ /* Default BPID to use for packets on this port-kind */
+ prt_cfgbx.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGBX(pknd));
+ prt_cfgbx.s.bpid = pknd;
+ cvmx_write_csr(CVMX_PIP_PRT_CFGBX(pknd), prt_cfgbx.u64);
+ }
+ else
+ {
+ port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+ tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
- /* Have each port go to a different POW queue */
- port_config.s.qos = ipd_port & 0x7;
+ /* Have each port go to a different POW queue */
+ port_config.s.qos = ipd_port & 0x7;
+ }
/* Process the headers and place the IP header in the work queue */
port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE;
@@ -311,13 +502,102 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port)
return 0;
}
+/**
+ * Enable or disable FCS stripping for all the ports on an interface.
+ *
+ * @param interface
+ * @param nports number of ports
+ * @param has_fcs 0 for disable and !0 for enable
+ */
+static int cvmx_helper_fcs_op(int interface, int nports, int has_fcs)
+{
+ uint64_t port_bit;
+ int index;
+ int pknd;
+ cvmx_pip_sub_pkind_fcsx_t pkind_fcsx;
+ cvmx_pip_prt_cfgx_t port_cfg;
+
+ if (!octeon_has_feature(OCTEON_FEATURE_PKND))
+ return 0;
+
+ port_bit = 0;
+ for (index = 0; index < nports; index++)
+ port_bit |= ((uint64_t)1 << cvmx_helper_get_pknd(interface, index));
+
+ pkind_fcsx.u64 = cvmx_read_csr(CVMX_PIP_SUB_PKIND_FCSX(0));
+ if (has_fcs)
+ pkind_fcsx.s.port_bit |= port_bit;
+ else
+ pkind_fcsx.s.port_bit &= ~port_bit;
+ cvmx_write_csr(CVMX_PIP_SUB_PKIND_FCSX(0), pkind_fcsx.u64);
+
+ for (pknd = 0; pknd < 64; pknd++)
+ {
+ if ((1ull << pknd) & port_bit)
+ {
+ port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(pknd));
+ port_cfg.s.crc_en = (has_fcs) ? 1 : 0;
+ cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), port_cfg.u64);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * Determine the actual number of hardware ports connected to an
+ * interface. It doesn't setup the ports or enable them.
+ *
+ * @param interface Interface to enumerate
+ *
+ * @return The number of ports on the interface, negative on failure
+ */
+int cvmx_helper_interface_enumerate(int interface)
+{
+ switch (cvmx_helper_interface_get_mode(interface)) {
+ /* XAUI is a single high speed port */
+ case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
+ return __cvmx_helper_xaui_enumerate(interface);
+ /* RGMII/GMII/MII are all treated about the same. Most functions
+ refer to these ports as RGMII */
+ case CVMX_HELPER_INTERFACE_MODE_RGMII:
+ case CVMX_HELPER_INTERFACE_MODE_GMII:
+ return __cvmx_helper_rgmii_enumerate(interface);
+ /* SPI4 can have 1-16 ports depending on the device at the other end */
+ case CVMX_HELPER_INTERFACE_MODE_SPI:
+ return __cvmx_helper_spi_enumerate(interface);
+ /* SGMII can have 1-4 ports depending on how many are hooked up */
+ case CVMX_HELPER_INTERFACE_MODE_SGMII:
+ case CVMX_HELPER_INTERFACE_MODE_PICMG:
+ return __cvmx_helper_sgmii_enumerate(interface);
+ /* PCI target Network Packet Interface */
+ case CVMX_HELPER_INTERFACE_MODE_NPI:
+ return __cvmx_helper_npi_enumerate(interface);
+ /* Special loopback only ports. These are not the same
+ * as other ports in loopback mode */
+ case CVMX_HELPER_INTERFACE_MODE_LOOP:
+ return __cvmx_helper_loop_enumerate(interface);
+ /* SRIO has 2^N ports, where N is number of interfaces */
+ case CVMX_HELPER_INTERFACE_MODE_SRIO:
+ return __cvmx_helper_srio_enumerate(interface);
+
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
+ return __cvmx_helper_ilk_enumerate(interface);
+ /* These types don't support ports to IPD/PKO */
+ case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+ case CVMX_HELPER_INTERFACE_MODE_PCIE:
+ default:
+ return 0;
+ }
+}
/**
- * This function probes an interface to determine the actual
- * number of hardware ports connected to it. It doesn't setup the
- * ports or enable them. The main goal here is to set the global
- * interface_port_count[interface] correctly. Hardware setup of the
- * ports will be performed later.
+ * This function probes an interface to determine the actual number of
+ * hardware ports connected to it. It does some setup the ports but
+ * doesn't enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Final hardware setup of
+ * the ports will be performed later.
*
* @param interface Interface to probe
*
@@ -328,48 +608,74 @@ int cvmx_helper_interface_probe(int interface)
/* At this stage in the game we don't want packets to be moving yet.
The following probe calls should perform hardware setup
needed to determine port counts. Receive must still be disabled */
+ int nports;
+ int has_fcs;
+ enum cvmx_pko_padding padding = CVMX_PKO_PADDING_NONE;
+
+ nports = -1;
+ has_fcs = 0;
switch (cvmx_helper_interface_get_mode(interface))
{
/* These types don't support ports to IPD/PKO */
case CVMX_HELPER_INTERFACE_MODE_DISABLED:
case CVMX_HELPER_INTERFACE_MODE_PCIE:
- interface_port_count[interface] = 0;
+ nports = 0;
break;
/* XAUI is a single high speed port */
case CVMX_HELPER_INTERFACE_MODE_XAUI:
- interface_port_count[interface] = __cvmx_helper_xaui_probe(interface);
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
+ nports = __cvmx_helper_xaui_probe(interface);
+ has_fcs = 1;
+ padding = CVMX_PKO_PADDING_60;
break;
/* RGMII/GMII/MII are all treated about the same. Most functions
refer to these ports as RGMII */
case CVMX_HELPER_INTERFACE_MODE_RGMII:
case CVMX_HELPER_INTERFACE_MODE_GMII:
- interface_port_count[interface] = __cvmx_helper_rgmii_probe(interface);
+ nports = __cvmx_helper_rgmii_probe(interface);
+ padding = CVMX_PKO_PADDING_60;
break;
/* SPI4 can have 1-16 ports depending on the device at the other end */
case CVMX_HELPER_INTERFACE_MODE_SPI:
- interface_port_count[interface] = __cvmx_helper_spi_probe(interface);
+ nports = __cvmx_helper_spi_probe(interface);
+ padding = CVMX_PKO_PADDING_60;
break;
/* SGMII can have 1-4 ports depending on how many are hooked up */
case CVMX_HELPER_INTERFACE_MODE_SGMII:
+ padding = CVMX_PKO_PADDING_60;
case CVMX_HELPER_INTERFACE_MODE_PICMG:
- interface_port_count[interface] = __cvmx_helper_sgmii_probe(interface);
+ nports = __cvmx_helper_sgmii_probe(interface);
+ has_fcs = 1;
break;
/* PCI target Network Packet Interface */
case CVMX_HELPER_INTERFACE_MODE_NPI:
- interface_port_count[interface] = __cvmx_helper_npi_probe(interface);
+ nports = __cvmx_helper_npi_probe(interface);
break;
/* Special loopback only ports. These are not the same as other ports
in loopback mode */
case CVMX_HELPER_INTERFACE_MODE_LOOP:
- interface_port_count[interface] = __cvmx_helper_loop_probe(interface);
+ nports = __cvmx_helper_loop_probe(interface);
+ break;
+ /* SRIO has 2^N ports, where N is number of interfaces */
+ case CVMX_HELPER_INTERFACE_MODE_SRIO:
+ nports = __cvmx_helper_srio_probe(interface);
+ break;
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
+ nports = __cvmx_helper_ilk_probe(interface);
+ has_fcs = 1;
+ padding = CVMX_PKO_PADDING_60;
break;
- /* SRIO has 2^N ports, where N is number of interfaces */
- case CVMX_HELPER_INTERFACE_MODE_SRIO:
- interface_port_count[interface] = __cvmx_helper_srio_probe(interface);
- break;
}
- interface_port_count[interface] = __cvmx_helper_board_interface_probe(interface, interface_port_count[interface]);
+ if (nports == -1)
+ return -1;
+
+ if (!octeon_has_feature(OCTEON_FEATURE_PKND))
+ has_fcs = 0;
+
+ nports = __cvmx_helper_board_interface_probe(interface, nports);
+ __cvmx_helper_init_interface(interface, nports, has_fcs, padding);
+ cvmx_helper_fcs_op(interface, nports, has_fcs);
/* Make sure all global variables propagate to other cores */
CVMX_SYNCWS;
@@ -391,14 +697,33 @@ int cvmx_helper_interface_probe(int interface)
*/
static int __cvmx_helper_interface_setup_ipd(int interface)
{
+
+ cvmx_helper_interface_mode_t mode;
int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
- int num_ports = interface_port_count[interface];
+ int num_ports = cvmx_helper_ports_on_interface(interface);
+ int delta;
+
+ if (num_ports == CVMX_HELPER_CFG_INVALID_VALUE)
+ return 0;
+
+ mode = cvmx_helper_interface_get_mode(interface);
+
+ if (mode == CVMX_HELPER_INTERFACE_MODE_LOOP)
+ __cvmx_helper_loop_enable(interface);
+
+ delta = 1;
+ if (octeon_has_feature(OCTEON_FEATURE_PKND))
+ {
+ if (mode == CVMX_HELPER_INTERFACE_MODE_SGMII)
+ delta = 16;
+ }
while (num_ports--)
{
__cvmx_helper_port_setup_ipd(ipd_port);
- ipd_port++;
+ ipd_port += delta;
}
+
return 0;
}
@@ -450,12 +775,13 @@ static int __cvmx_helper_interface_setup_pko(int interface)
priorities and replicate them in the second half.
With per-core PKO queues (PKO lockless operation) all queues have
the same priority. */
- uint64_t priorities[16] = {8,7,6,5,4,3,2,1,8,7,6,5,4,3,2,1};
+ /* uint64_t priorities[16] = {8,7,6,5,4,3,2,1,8,7,6,5,4,3,2,1}; */
+ uint64_t priorities[16] = {[0 ... 15] = 8};
/* Setup the IPD/PIP and PKO for the ports discovered above. Here packet
classification, tagging and output priorities are set */
int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
- int num_ports = interface_port_count[interface];
+ int num_ports = cvmx_helper_ports_on_interface(interface);
while (num_ports--)
{
/* Give the user a chance to override the per queue priorities */
@@ -486,6 +812,21 @@ static int __cvmx_helper_global_setup_pko(void)
fau_to.s.tout_val = 0xfff;
fau_to.s.tout_enb = 0;
cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64);
+
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+ cvmx_pko_reg_min_pkt_t min_pkt;
+
+ min_pkt.u64 = 0;
+ min_pkt.s.size1 = 59;
+ min_pkt.s.size2 = 59;
+ min_pkt.s.size3 = 59;
+ min_pkt.s.size4 = 59;
+ min_pkt.s.size5 = 59;
+ min_pkt.s.size6 = 59;
+ min_pkt.s.size7 = 59;
+ cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64);
+ }
+
return 0;
}
@@ -510,9 +851,11 @@ static int __cvmx_helper_global_setup_backpressure(void)
case CVMX_HELPER_INTERFACE_MODE_DISABLED:
case CVMX_HELPER_INTERFACE_MODE_PCIE:
case CVMX_HELPER_INTERFACE_MODE_SRIO:
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
case CVMX_HELPER_INTERFACE_MODE_NPI:
case CVMX_HELPER_INTERFACE_MODE_LOOP:
case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
break;
case CVMX_HELPER_INTERFACE_MODE_RGMII:
case CVMX_HELPER_INTERFACE_MODE_GMII:
@@ -663,10 +1006,12 @@ static int __cvmx_helper_packet_hardware_enable(int interface)
/* These types don't support ports to IPD/PKO */
case CVMX_HELPER_INTERFACE_MODE_DISABLED:
case CVMX_HELPER_INTERFACE_MODE_PCIE:
+ case CVMX_HELPER_INTERFACE_MODE_LOOP:
/* Nothing to do */
break;
/* XAUI is a single high speed port */
case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
result = __cvmx_helper_xaui_enable(interface);
break;
/* RGMII/GMII/MII are all treated about the same. Most functions
@@ -688,15 +1033,13 @@ static int __cvmx_helper_packet_hardware_enable(int interface)
case CVMX_HELPER_INTERFACE_MODE_NPI:
result = __cvmx_helper_npi_enable(interface);
break;
- /* Special loopback only ports. These are not the same as other ports
- in loopback mode */
- case CVMX_HELPER_INTERFACE_MODE_LOOP:
- result = __cvmx_helper_loop_enable(interface);
- break;
- /* SRIO has 2^N ports, where N is number of interfaces */
+ /* SRIO has 2^N ports, where N is number of interfaces */
case CVMX_HELPER_INTERFACE_MODE_SRIO:
- result = __cvmx_helper_srio_enable(interface);
- break;
+ result = __cvmx_helper_srio_enable(interface);
+ break;
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
+ result = __cvmx_helper_ilk_enable(interface);
+ break;
}
result |= __cvmx_helper_board_hardware_enable(interface);
return result;
@@ -741,6 +1084,154 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
EXPORT_SYMBOL(cvmx_helper_ipd_and_packet_input_enable);
#endif
+#define __CVMX_SSO_RWQ_SIZE 256
+
+int cvmx_helper_initialize_sso(int wqe_entries)
+{
+ int cvm_oct_sso_number_rwq_bufs;
+ char *mem;
+ int i;
+ cvmx_sso_cfg_t sso_cfg;
+ cvmx_fpa_fpfx_marks_t fpa_marks;
+
+ if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+ return 0;
+
+ /*
+ * CN68XX-P1 may reset with the wrong values, put in
+ * the correct values.
+ */
+ fpa_marks.u64 = 0;
+ fpa_marks.s.fpf_wr = 0xa4;
+ fpa_marks.s.fpf_rd = 0x40;
+ cvmx_write_csr(CVMX_FPA_FPF8_MARKS, fpa_marks.u64);
+
+ cvm_oct_sso_number_rwq_bufs = ((wqe_entries - 1) / 26) + 1 + 48 + 8;
+
+ mem = cvmx_bootmem_alloc(__CVMX_SSO_RWQ_SIZE * cvm_oct_sso_number_rwq_bufs, CVMX_CACHE_LINE_SIZE);
+ if (mem == NULL) {
+ cvmx_dprintf("Out of memory initializing sso pool\n");
+ return -1;
+ }
+ /* Make sure RWI/RWO is disabled. */
+ sso_cfg.u64 = cvmx_read_csr(CVMX_SSO_CFG);
+ sso_cfg.s.rwen = 0;
+ cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+
+ for (i = cvm_oct_sso_number_rwq_bufs - 8; i > 0; i--) {
+ cvmx_sso_rwq_psh_fptr_t fptr;
+
+ for (;;) {
+ fptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_PSH_FPTR);
+ if (!fptr.s.full)
+ break;
+ cvmx_wait(1000);
+ }
+ fptr.s.fptr = cvmx_ptr_to_phys(mem) >> 7;
+ cvmx_write_csr(CVMX_SSO_RWQ_PSH_FPTR, fptr.u64);
+ mem = mem + __CVMX_SSO_RWQ_SIZE;
+ }
+
+ for (i = 0; i < 8; i++) {
+ cvmx_sso_rwq_head_ptrx_t head_ptr;
+ cvmx_sso_rwq_tail_ptrx_t tail_ptr;
+
+ head_ptr.u64 = 0;
+ tail_ptr.u64 = 0;
+ head_ptr.s.ptr = cvmx_ptr_to_phys(mem) >> 7;
+ tail_ptr.s.ptr = head_ptr.s.ptr;
+ cvmx_write_csr(CVMX_SSO_RWQ_HEAD_PTRX(i), head_ptr.u64);
+ cvmx_write_csr(CVMX_SSO_RWQ_TAIL_PTRX(i), tail_ptr.u64);
+ mem = mem + __CVMX_SSO_RWQ_SIZE;
+ }
+
+ sso_cfg.u64 = cvmx_read_csr(CVMX_SSO_CFG);
+ sso_cfg.s.rwen = 1;
+ sso_cfg.s.dwb = cvmx_helper_cfg_opt_get(CVMX_HELPER_CFG_OPT_USE_DWB);
+ sso_cfg.s.rwq_byp_dis = 0;
+ sso_cfg.s.rwio_byp_dis = 0;
+ cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+
+ return 0;
+}
+
+int cvmx_helper_uninitialize_sso(void)
+{
+ cvmx_fpa_quex_available_t queue_available;
+ cvmx_sso_cfg_t sso_cfg;
+ cvmx_sso_rwq_pop_fptr_t pop_fptr;
+ cvmx_sso_rwq_psh_fptr_t fptr;
+ cvmx_sso_fpage_cnt_t fpage_cnt;
+ int num_to_transfer, i;
+ char *mem;
+
+ if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+ return 0;
+
+ sso_cfg.u64 = cvmx_read_csr(CVMX_SSO_CFG);
+ sso_cfg.s.rwen = 0;
+ sso_cfg.s.rwq_byp_dis = 1;
+ cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+ cvmx_read_csr(CVMX_SSO_CFG);
+ queue_available.u64 = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(8));
+
+ /* Make CVMX_FPA_QUEX_AVAILABLE(8) % 16 == 0*/
+ for (num_to_transfer = (16 - queue_available.s.que_siz) % 16;
+ num_to_transfer > 0; num_to_transfer--) {
+ do {
+ pop_fptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_POP_FPTR);
+ } while (!pop_fptr.s.val);
+ for (;;) {
+ fptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_PSH_FPTR);
+ if (!fptr.s.full)
+ break;
+ cvmx_wait(1000);
+ }
+ fptr.s.fptr = pop_fptr.s.fptr;
+ cvmx_write_csr(CVMX_SSO_RWQ_PSH_FPTR, fptr.u64);
+ }
+ cvmx_read_csr(CVMX_SSO_CFG);
+
+ do {
+ queue_available.u64 = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(8));
+ } while (queue_available.s.que_siz % 16);
+
+ sso_cfg.s.rwen = 1;
+ sso_cfg.s.rwq_byp_dis = 0;
+ cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+
+ for (i = 0; i < 8; i++) {
+ cvmx_sso_rwq_head_ptrx_t head_ptr;
+ cvmx_sso_rwq_tail_ptrx_t tail_ptr;
+
+ head_ptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_HEAD_PTRX(i));
+ tail_ptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_TAIL_PTRX(i));
+ if (head_ptr.s.ptr != tail_ptr.s.ptr) {
+ cvmx_dprintf("head_ptr.s.ptr != tail_ptr.s.ptr, idx: %d\n", i);
+ }
+
+ mem = cvmx_phys_to_ptr(((uint64_t)head_ptr.s.ptr) << 7);
+ /* Leak the memory */
+ }
+
+ do {
+ do {
+ pop_fptr.u64 = cvmx_read_csr(CVMX_SSO_RWQ_POP_FPTR);
+ if (pop_fptr.s.val) {
+ mem = cvmx_phys_to_ptr(((uint64_t)pop_fptr.s.fptr) << 7);
+ /* Leak the memory */
+ }
+ } while (pop_fptr.s.val);
+ fpage_cnt.u64 = cvmx_read_csr(CVMX_SSO_FPAGE_CNT);
+ } while (fpage_cnt.s.fpage_cnt);
+
+ sso_cfg.s.rwen = 0;
+ sso_cfg.s.rwq_byp_dis = 0;
+ cvmx_write_csr(CVMX_SSO_CFG, sso_cfg.u64);
+
+ return 0;
+}
+
/**
* Initialize the PIP, IPD, and PKO hardware to support
* simple priority based queues for the ethernet ports. Each
@@ -765,7 +1256,7 @@ int cvmx_helper_initialize_packet_io_global(void)
/* Tell L2 to give the IOB statically higher priority compared to the
cores. This avoids conditions where IO blocks might be starved under
very high L2 loads */
- if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
{
cvmx_l2c_ctl_t l2c_ctl;
l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
@@ -783,28 +1274,31 @@ int cvmx_helper_initialize_packet_io_global(void)
if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
{
- /* Make sure SMI/MDIO is enabled so we can query PHYs */
- smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0));
- if (!smix_en.s.en)
- {
- smix_en.s.en = 1;
- cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64);
- }
-
- /* Newer chips actually have two SMI/MDIO interfaces */
- if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
- !OCTEON_IS_MODEL(OCTEON_CN58XX) &&
- !OCTEON_IS_MODEL(OCTEON_CN50XX))
+ int smi_inf = 1;
+ int i;
+
+ /* Newer chips have more than one SMI/MDIO interface */
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ smi_inf = 4;
+ else if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)
+ && !OCTEON_IS_MODEL(OCTEON_CN58XX)
+ && !OCTEON_IS_MODEL(OCTEON_CN50XX))
+ smi_inf = 2;
+
+ for (i = 0; i < smi_inf; i++)
{
- smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1));
+ /* Make sure SMI/MDIO is enabled so we can query PHYs */
+ smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(i));
if (!smix_en.s.en)
{
smix_en.s.en = 1;
- cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64);
+ cvmx_write_csr(CVMX_SMIX_EN(i), smix_en.u64);
}
}
}
+ __cvmx_helper_cfg_init();
+
for (interface=0; interface<num_interfaces; interface++)
result |= cvmx_helper_interface_probe(interface);
@@ -816,7 +1310,8 @@ int cvmx_helper_initialize_packet_io_global(void)
interface, cvmx_helper_ports_on_interface(interface),
cvmx_helper_interface_mode_to_string(cvmx_helper_interface_get_mode(interface)));
result |= __cvmx_helper_interface_setup_ipd(interface);
- result |= __cvmx_helper_interface_setup_pko(interface);
+ if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
+ result |= __cvmx_helper_interface_setup_pko(interface);
}
result |= __cvmx_helper_global_setup_ipd();
@@ -845,6 +1340,34 @@ int cvmx_helper_initialize_packet_io_local(void)
return cvmx_pko_initialize_local();
}
+/**
+ * wait for the pko queue to drain
+ *
+ * @param queue a valid pko queue
+ * @return count is the length of the queue after calling this
+ * function
+ */
+static int cvmx_helper_wait_pko_queue_drain(int queue)
+{
+ const int timeout = 5; /* Wait up to 5 seconds for timeouts */
+ int count;
+ uint64_t start_cycle, stop_cycle;
+
+ count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
+ start_cycle = cvmx_get_cycle();
+ stop_cycle = start_cycle + cvmx_clock_get_rate(CVMX_CLOCK_CORE) * timeout;
+ while (count && (cvmx_get_cycle() < stop_cycle))
+ {
+ cvmx_wait(10000);
+ count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
+ }
+
+ return count;
+}
+
+struct cvmx_buffer_list {
+ struct cvmx_buffer_list *next;
+};
/**
* Undo the initialization performed in
@@ -865,49 +1388,58 @@ int cvmx_helper_shutdown_packet_io_global(void)
int interface;
int num_ports;
int index;
- int pool0_count;
+ struct cvmx_buffer_list *pool0_buffers;
+ struct cvmx_buffer_list *pool0_buffers_tail;
cvmx_wqe_t *work;
/* Step 1: Disable all backpressure */
- for (interface=0; interface<2; interface++)
+ for (interface=0; interface<CVMX_HELPER_MAX_GMX; interface++)
if (cvmx_helper_interface_get_mode(interface) != CVMX_HELPER_INTERFACE_MODE_DISABLED)
cvmx_gmx_set_backpressure_override(interface, 0xf);
step2:
/* Step 2: Wait for the PKO queues to drain */
- num_interfaces = cvmx_helper_get_number_of_interfaces();
- for (interface=0; interface<num_interfaces; interface++)
+ if (octeon_has_feature(OCTEON_FEATURE_PKND))
{
- num_ports = cvmx_helper_ports_on_interface(interface);
- for (index=0; index<num_ports; index++)
+ int queue, max_queue;
+
+ max_queue = __cvmx_helper_cfg_pko_max_queue();
+ for (queue = 0; queue < max_queue; queue++)
+ {
+ if (cvmx_helper_wait_pko_queue_drain(queue))
+ {
+ result = -1;
+ goto step3;
+ }
+ }
+ }
+ else
+ {
+ num_interfaces = cvmx_helper_get_number_of_interfaces();
+ for (interface=0; interface<num_interfaces; interface++)
{
- int pko_port = cvmx_helper_get_ipd_port(interface, index);
- int queue = cvmx_pko_get_base_queue(pko_port);
- int max_queue = queue + cvmx_pko_get_num_queues(pko_port);
- while (queue < max_queue)
+ num_ports = cvmx_helper_ports_on_interface(interface);
+ for (index=0; index<num_ports; index++)
{
- int count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
- uint64_t start_cycle = cvmx_get_cycle();
- uint64_t stop_cycle = start_cycle +
- cvmx_clock_get_rate(CVMX_CLOCK_CORE) * timeout;
- while (count && (cvmx_get_cycle() < stop_cycle))
- {
- cvmx_wait(10000);
- count = cvmx_cmd_queue_length(CVMX_CMD_QUEUE_PKO(queue));
- }
- if (count)
+ int pko_port = cvmx_helper_get_ipd_port(interface, index);
+ int queue = cvmx_pko_get_base_queue(pko_port);
+ int max_queue = queue + cvmx_pko_get_num_queues(pko_port);
+ while (queue < max_queue)
{
- cvmx_dprintf("PKO port %d, queue %d, timeout waiting for idle\n",
- pko_port, queue);
- result = -1;
+ if (cvmx_helper_wait_pko_queue_drain(queue))
+ {
+ result = -1;
+ goto step3;
+ }
+ queue++;
}
- queue++;
}
}
}
+step3:
/* Step 3: Disable TX and RX on all ports */
- for (interface=0; interface<2; interface++)
+ for (interface=0; interface<CVMX_HELPER_MAX_GMX; interface++)
{
switch (cvmx_helper_interface_get_mode(interface))
{
@@ -917,6 +1449,7 @@ step2:
break;
case CVMX_HELPER_INTERFACE_MODE_NPI:
case CVMX_HELPER_INTERFACE_MODE_SRIO:
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
/* We don't handle the NPI/NPEI/SRIO packet engines. The caller
must know these are idle */
break;
@@ -962,6 +1495,7 @@ step2:
cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0);
break;
case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
case CVMX_HELPER_INTERFACE_MODE_SGMII:
case CVMX_HELPER_INTERFACE_MODE_PICMG:
num_ports = cvmx_helper_ports_on_interface(interface);
@@ -1065,9 +1599,8 @@ step2:
}
}
- /* Step 5: Disable IPD and PKO. PIP is taken care of in the next step */
+ /* Step 5 */
cvmx_ipd_disable();
- cvmx_pko_disable();
/* Step 6: Drain all prefetched buffers from IPD/PIP. Note that IPD/PIP
have not been reset yet */
@@ -1077,17 +1610,19 @@ step2:
cvmx_pko_shutdown();
/* Step 8: Disable MAC address filtering */
- for (interface=0; interface<2; interface++)
+ for (interface=0; interface<CVMX_HELPER_MAX_GMX; interface++)
{
switch (cvmx_helper_interface_get_mode(interface))
{
case CVMX_HELPER_INTERFACE_MODE_DISABLED:
case CVMX_HELPER_INTERFACE_MODE_PCIE:
case CVMX_HELPER_INTERFACE_MODE_SRIO:
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
case CVMX_HELPER_INTERFACE_MODE_NPI:
case CVMX_HELPER_INTERFACE_MODE_LOOP:
break;
case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
case CVMX_HELPER_INTERFACE_MODE_GMII:
case CVMX_HELPER_INTERFACE_MODE_RGMII:
case CVMX_HELPER_INTERFACE_MODE_SPI:
@@ -1111,23 +1646,30 @@ step2:
}
}
- /* Step 9: Drain all FPA buffers out of pool 0 before we reset IPD/PIP.
- This is needed to keep IPD_QUE0_FREE_PAGE_CNT in sync. We use pool 1
- for temporary storage */
- pool0_count = 0;
+ /* Step 9: Drain all FPA buffers out of pool 0 before we reset
+ * IPD/PIP. This is needed to keep IPD_QUE0_FREE_PAGE_CNT in
+ * sync. We temporarily keep the buffers in the pool0_buffers
+ * list.
+ */
+ pool0_buffers = NULL;
+ pool0_buffers_tail = NULL;
while (1)
{
- void *buffer = cvmx_fpa_alloc(0);
- if (buffer)
- {
- cvmx_fpa_free(buffer, 1, 0);
- pool0_count++;
+ struct cvmx_buffer_list *buffer = cvmx_fpa_alloc(0);
+ if (buffer) {
+ buffer->next = NULL;
+
+ if (pool0_buffers == NULL)
+ pool0_buffers = buffer;
+ else
+ pool0_buffers_tail->next = buffer;
+
+ pool0_buffers_tail = buffer;
}
else
break;
}
-
/* Step 10: Reset IPD and PIP */
{
cvmx_ipd_ctl_status_t ipd_ctl_status;
@@ -1172,11 +1714,27 @@ step2:
pip_sft_rst.s.rst = 1;
cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
}
+
+ /* Make sure IPD has finished reset. */
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ {
+ if (CVMX_WAIT_FOR_FIELD64(CVMX_IPD_CTL_STATUS, cvmx_ipd_ctl_status_t, rst_done, ==, 0, 1000))
+ {
+ cvmx_dprintf("IPD reset timeout waiting for idle\n");
+ result = -1;
+ }
+ }
}
/* Step 11: Restore the FPA buffers into pool 0 */
- while (pool0_count--)
- cvmx_fpa_free(cvmx_fpa_alloc(1), 0, 0);
+ while (pool0_buffers) {
+ struct cvmx_buffer_list *n = pool0_buffers->next;
+ cvmx_fpa_free(pool0_buffers, 0, 0);
+ pool0_buffers = n;
+ }
+
+ /* Step 12: Release interface structures */
+ __cvmx_helper_shutdown_interfaces();
return result;
}
@@ -1221,7 +1779,7 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
}
link_info = cvmx_helper_link_get(ipd_port);
- if (link_info.u64 == port_link_info[ipd_port].u64)
+ if (link_info.u64 == (__cvmx_helper_get_link_info(interface, index)).u64)
return link_info;
#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -1237,9 +1795,7 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
cvmx_error_enable_group(CVMX_ERROR_GROUP_ETHERNET, ipd_port);
#endif
- /* port_link_info should be the current value, which will be different
- than expect if cvmx_helper_link_set() failed */
- return port_link_info[ipd_port];
+ return link_info;
}
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
EXPORT_SYMBOL(cvmx_helper_link_autoconf);
@@ -1275,6 +1831,7 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
/* Network links are not supported */
break;
case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
result = __cvmx_helper_xaui_link_get(ipd_port);
break;
case CVMX_HELPER_INTERFACE_MODE_GMII:
@@ -1300,6 +1857,9 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
case CVMX_HELPER_INTERFACE_MODE_SRIO:
result = __cvmx_helper_srio_link_get(ipd_port);
break;
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
+ result = __cvmx_helper_ilk_link_get(ipd_port);
+ break;
case CVMX_HELPER_INTERFACE_MODE_NPI:
case CVMX_HELPER_INTERFACE_MODE_LOOP:
/* Network links are not supported */
@@ -1339,6 +1899,7 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
case CVMX_HELPER_INTERFACE_MODE_PCIE:
break;
case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
result = __cvmx_helper_xaui_link_set(ipd_port, link_info);
break;
/* RGMII/GMII/MII are all treated about the same. Most functions
@@ -1357,6 +1918,9 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
case CVMX_HELPER_INTERFACE_MODE_SRIO:
result = __cvmx_helper_srio_link_set(ipd_port, link_info);
break;
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
+ result = __cvmx_helper_ilk_link_set(ipd_port, link_info);
+ break;
case CVMX_HELPER_INTERFACE_MODE_NPI:
case CVMX_HELPER_INTERFACE_MODE_LOOP:
break;
@@ -1365,7 +1929,7 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
no matter how cvmx_helper_link_set is called. We don't change
the value if link_set failed */
if (result == 0)
- port_link_info[ipd_port].u64 = link_info.u64;
+ __cvmx_helper_set_link_info(interface, index, link_info);
return result;
}
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -1400,11 +1964,13 @@ int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, int enable
case CVMX_HELPER_INTERFACE_MODE_DISABLED:
case CVMX_HELPER_INTERFACE_MODE_PCIE:
case CVMX_HELPER_INTERFACE_MODE_SRIO:
+ case CVMX_HELPER_INTERFACE_MODE_ILK:
case CVMX_HELPER_INTERFACE_MODE_SPI:
case CVMX_HELPER_INTERFACE_MODE_NPI:
case CVMX_HELPER_INTERFACE_MODE_LOOP:
break;
case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
result = __cvmx_helper_xaui_configure_loopback(ipd_port, enable_internal, enable_external);
break;
case CVMX_HELPER_INTERFACE_MODE_RGMII: