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-rw-r--r--cvmx-gmxx-defs.h6600
1 files changed, 4573 insertions, 2027 deletions
diff --git a/cvmx-gmxx-defs.h b/cvmx-gmxx-defs.h
index e7e5cea58991..e409db8c3127 100644
--- a/cvmx-gmxx-defs.h
+++ b/cvmx-gmxx-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,336 +49,702 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_GMXX_TYPEDEFS_H__
-#define __CVMX_GMXX_TYPEDEFS_H__
+#ifndef __CVMX_GMXX_DEFS_H__
+#define __CVMX_GMXX_DEFS_H__
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_BAD_REG(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_BAD_REG (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_BAD_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_BIST(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_BIST (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_BIST(block_id) (CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
+static inline uint64_t CVMX_GMXX_BPID_MAPX(unsigned long offset, unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_CLK_EN(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull;
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 4))))))
+ cvmx_warn("CVMX_GMXX_BPID_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8;
}
#else
-#define CVMX_GMXX_CLK_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+static inline uint64_t CVMX_GMXX_BPID_MSK(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_HG2_CONTROL(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull;
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+ cvmx_warn("CVMX_GMXX_BPID_MSK(%lu) is invalid on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull;
}
#else
-#define CVMX_GMXX_HG2_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull)
#endif
+static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_CLK_EN (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + ((block_id) & 0) * 0x8000000ull;
+}
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+static inline uint64_t CVMX_GMXX_EBP_DIS(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_INF_MODE(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull;
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+ cvmx_warn("CVMX_GMXX_EBP_DIS(%lu) is invalid on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull;
}
#else
-#define CVMX_GMXX_INF_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
+static inline uint64_t CVMX_GMXX_EBP_MSK(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_NXA_ADR(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull;
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+ cvmx_warn("CVMX_GMXX_EBP_MSK(%lu) is invalid on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull;
}
#else
-#define CVMX_GMXX_NXA_ADR(block_id) (CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull)
#endif
+static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_HG2_CONTROL (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000550ull) + ((block_id) & 0) * 0x8000000ull;
+}
+static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_INF_MODE (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + ((block_id) & 0) * 0x8000000ull;
+}
+static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_NXA_ADR (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000510ull) + ((block_id) & 0) * 0x8000000ull;
+}
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
+static inline uint64_t CVMX_GMXX_PIPE_STATUS(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull;
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+ cvmx_warn("CVMX_GMXX_PIPE_STATUS(%lu) is invalid on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull;
}
#else
-#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((block_id) & 0) * 0x8000000ull;
+}
static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_PRTX_CFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_PRTX_CFG (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_PRTX_CFG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
+static inline uint64_t CVMX_GMXX_RXAUI_CTL(unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 4)))))
+ cvmx_warn("CVMX_GMXX_RXAUI_CTL(%lu) is invalid on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull;
}
#else
-#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+}
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+}
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_ALL_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_ADR_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_ADR_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_DECISION(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_DECISION (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_DECISION(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_FRM_CHK(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_FRM_CHK (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_FRM_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_FRM_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset, unsigned long block_id)
{
@@ -407,93 +773,188 @@ static inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset, unsigned long
#else
#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_IFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_IFG (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_IFG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_INT_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_INT_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_INT_EN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_INT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_INT_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_INT_REG(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_JABBER(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_JABBER (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_JABBER(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned long block_id)
{
@@ -509,271 +970,547 @@ static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned lon
#else
#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RXX_UDD_SKP(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RXX_UDD_SKP (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RX_BP_DROPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RX_BP_DROPX (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
}
-#else
-#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RX_BP_OFFX(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RX_BP_OFFX (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
}
-#else
-#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_RX_BP_ONX(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RX_BP_ONX (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
}
-#else
-#define CVMX_GMXX_RX_BP_ONX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_RX_HG2_STATUS(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RX_HG2_STATUS (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_RX_HG2_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000548ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_PASS_EN(unsigned long block_id)
{
@@ -798,42 +1535,62 @@ static inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset, unsigned lon
#else
#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_RX_PRTS(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RX_PRTS (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_RX_PRTS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000410ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_RX_PRT_INFO(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RX_PRT_INFO (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_RX_PRT_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
{
@@ -847,141 +1604,276 @@ static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
#else
#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000538ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_RX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_RX_XAUI_CTL (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_RX_XAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000530ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_SMACX(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_SMACX (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_SMACX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_SOFT_BIST(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080007E8ull);
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_SOFT_BIST (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + ((block_id) & 7) * 0x1000000ull;
}
-#else
-#define CVMX_GMXX_SOFT_BIST(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_STAT_BP(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_STAT_BP (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 0) * 0x8000000ull;
+}
+static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TB_REG (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_STAT_BP(block_id) (CVMX_ADD_IO_SEG(0x0001180008000520ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_APPEND(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_APPEND (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_APPEND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_BURST(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_BURST (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_BURST(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset == 0)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_CBFC_XON(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset == 0)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_CBFC_XON (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long block_id)
{
@@ -997,397 +1889,811 @@ static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long blo
#else
#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_MIN_PKT(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_MIN_PKT (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
+static inline uint64_t CVMX_GMXX_TXX_PIPE(unsigned long offset, unsigned long block_id)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 4))))))
+ cvmx_warn("CVMX_GMXX_TXX_PIPE(%lu,%lu) is invalid on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
}
#else
-#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
+#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+}
static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_SLOT(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_SLOT (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_SLOT(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT0(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT0 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT0(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT1(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT1 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT1(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT2(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT2 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT2(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT3(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT3 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT3(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT4(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT4 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT4(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT5(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT5 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT5(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT6(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT6 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT6(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT7(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT7 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT7(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT8(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT8 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT8(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STAT9(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STAT9 (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STAT9(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_STATS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id == 0))))))
- cvmx_warn("CVMX_GMXX_TXX_THRESH(%lu,%lu) is invalid on this chip\n", offset, block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 1)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 1)))
+ return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 2)) && ((block_id == 0)))
+ return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if (((offset <= 3)) && ((block_id <= 4)))
+ return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TXX_THRESH (%lu, %lu) not supported on this chip\n", offset, block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
}
-#else
-#define CVMX_GMXX_TXX_THRESH(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_BP(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_BP (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_BP(block_id) (CVMX_ADD_IO_SEG(0x00011800080004D0ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long block_id)
{
@@ -1400,230 +2706,360 @@ static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long
#else
#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) (CVMX_ADD_IO_SEG(0x0001180008000498ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_CORRUPT(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_CORRUPT (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_CORRUPT(block_id) (CVMX_ADD_IO_SEG(0x00011800080004D8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_HG2_REG1(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_HG2_REG1 (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_HG2_REG1(block_id) (CVMX_ADD_IO_SEG(0x0001180008000558ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_HG2_REG2(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_HG2_REG2 (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_HG2_REG2(block_id) (CVMX_ADD_IO_SEG(0x0001180008000560ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_IFG(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_IFG (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_IFG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000488ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_INT_EN(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_INT_EN (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x0001180008000508ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_INT_REG(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_INT_REG (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180008000500ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_JAM(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_JAM (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_JAM(block_id) (CVMX_ADD_IO_SEG(0x0001180008000490ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_LFSR(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_LFSR (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_LFSR(block_id) (CVMX_ADD_IO_SEG(0x00011800080004F8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_OVR_BP(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_OVR_BP (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_OVR_BP(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) (CVMX_ADD_IO_SEG(0x00011800080004A0ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) (CVMX_ADD_IO_SEG(0x00011800080004A8ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_PRTS(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_PRTS (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_PRTS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000480ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_SPI_CTL(unsigned long block_id)
{
@@ -1683,32 +3119,52 @@ static inline uint64_t CVMX_GMXX_TX_SPI_THRESH(unsigned long block_id)
#else
#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_TX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_TX_XAUI_CTL (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_TX_XAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000528ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0)))))
- cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK(%lu) is invalid on this chip\n", block_id);
- return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((block_id == 0))
+ return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 0) * 0x8000000ull;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 1))
+ return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((block_id <= 4))
+ return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 7) * 0x1000000ull;
+ break;
+ }
+ cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK (block_id = %lu) not supported on this chip\n", block_id);
+ return CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 0) * 0x8000000ull;
}
-#else
-#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000540ull) + ((block_id) & 1) * 0x8000000ull)
-#endif
/**
* cvmx_gmx#_bad_reg
@@ -1720,12 +3176,10 @@ static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
* In XAUI mode, only the lsb (corresponding to port0) of INB_NXA, LOSTSTAT, OUT_OVR, are used.
*
*/
-union cvmx_gmxx_bad_reg
-{
+union cvmx_gmxx_bad_reg {
uint64_t u64;
- struct cvmx_gmxx_bad_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_bad_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63 : 33;
uint64_t inb_nxa : 4; /**< Inbound port > GMX_RX_PRTS */
uint64_t statovr : 1; /**< TX Statistics overflow
@@ -1750,9 +3204,8 @@ union cvmx_gmxx_bad_reg
uint64_t reserved_31_63 : 33;
#endif
} s;
- struct cvmx_gmxx_bad_reg_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_bad_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63 : 33;
uint64_t inb_nxa : 4; /**< Inbound port > GMX_RX_PRTS */
uint64_t statovr : 1; /**< TX Statistics overflow */
@@ -1777,9 +3230,8 @@ union cvmx_gmxx_bad_reg
struct cvmx_gmxx_bad_reg_s cn38xx;
struct cvmx_gmxx_bad_reg_s cn38xxp2;
struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
- struct cvmx_gmxx_bad_reg_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_bad_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63 : 33;
uint64_t inb_nxa : 4; /**< Inbound port > GMX_RX_PRTS */
uint64_t statovr : 1; /**< TX Statistics overflow
@@ -1807,8 +3259,13 @@ union cvmx_gmxx_bad_reg
struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
struct cvmx_gmxx_bad_reg_s cn58xx;
struct cvmx_gmxx_bad_reg_s cn58xxp1;
+ struct cvmx_gmxx_bad_reg_cn52xx cn61xx;
struct cvmx_gmxx_bad_reg_cn52xx cn63xx;
struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1;
+ struct cvmx_gmxx_bad_reg_cn52xx cn66xx;
+ struct cvmx_gmxx_bad_reg_cn52xx cn68xx;
+ struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1;
+ struct cvmx_gmxx_bad_reg_cn52xx cnf71xx;
};
typedef union cvmx_gmxx_bad_reg cvmx_gmxx_bad_reg_t;
@@ -1818,12 +3275,10 @@ typedef union cvmx_gmxx_bad_reg cvmx_gmxx_bad_reg_t;
* GMX_BIST = GMX BIST Results
*
*/
-union cvmx_gmxx_bist
-{
+union cvmx_gmxx_bist {
uint64_t u64;
- struct cvmx_gmxx_bist_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63 : 39;
uint64_t status : 25; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -1857,9 +3312,8 @@ union cvmx_gmxx_bist
uint64_t reserved_25_63 : 39;
#endif
} s;
- struct cvmx_gmxx_bist_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_bist_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t status : 10; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -1881,9 +3335,8 @@ union cvmx_gmxx_bist
struct cvmx_gmxx_bist_cn30xx cn31xx;
struct cvmx_gmxx_bist_cn30xx cn38xx;
struct cvmx_gmxx_bist_cn30xx cn38xxp2;
- struct cvmx_gmxx_bist_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_bist_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t status : 12; /**< BIST Results.
HW sets a bit in BIST for for memory that fails */
@@ -1892,9 +3345,8 @@ union cvmx_gmxx_bist
uint64_t reserved_12_63 : 52;
#endif
} cn50xx;
- struct cvmx_gmxx_bist_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t status : 16; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -1922,9 +3374,8 @@ union cvmx_gmxx_bist
struct cvmx_gmxx_bist_cn52xx cn52xxp1;
struct cvmx_gmxx_bist_cn52xx cn56xx;
struct cvmx_gmxx_bist_cn52xx cn56xxp1;
- struct cvmx_gmxx_bist_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_bist_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63 : 47;
uint64_t status : 17; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -1951,23 +3402,142 @@ union cvmx_gmxx_bist
#endif
} cn58xx;
struct cvmx_gmxx_bist_cn58xx cn58xxp1;
+ struct cvmx_gmxx_bist_s cn61xx;
struct cvmx_gmxx_bist_s cn63xx;
struct cvmx_gmxx_bist_s cn63xxp1;
+ struct cvmx_gmxx_bist_s cn66xx;
+ struct cvmx_gmxx_bist_s cn68xx;
+ struct cvmx_gmxx_bist_s cn68xxp1;
+ struct cvmx_gmxx_bist_s cnf71xx;
};
typedef union cvmx_gmxx_bist cvmx_gmxx_bist_t;
/**
+ * cvmx_gmx#_bpid_map#
+ *
+ * Notes:
+ * GMX will build BPID_VECTOR<15:0> using the 16 GMX_BPID_MAP entries and the BPID
+ * state from IPD. In XAUI/RXAUI mode when PFC/CBFC/HiGig2 is used, the
+ * BPID_VECTOR becomes the logical backpressure. In XAUI/RXAUI mode when
+ * PFC/CBFC/HiGig2 is not used or when in 4xSGMII mode, the BPID_VECTOR can be used
+ * with the GMX_BPID_MSK register to determine the physical backpressure.
+ *
+ * In XAUI/RXAUI mode, the entire BPID_VECTOR<15:0> is available determining physical
+ * backpressure for the single XAUI/RXAUI interface.
+ *
+ * In SGMII mode, BPID_VECTOR is broken up as follows:
+ * SGMII interface0 uses BPID_VECTOR<3:0>
+ * SGMII interface1 uses BPID_VECTOR<7:4>
+ * SGMII interface2 uses BPID_VECTOR<11:8>
+ * SGMII interface3 uses BPID_VECTOR<15:12>
+ *
+ * In all SGMII configurations, and in some XAUI/RXAUI configurations, the
+ * interface protocols only support physical backpressure. In these cases, a single
+ * BPID will commonly drive the physical backpressure for the physical
+ * interface. We provide example programmings for these simple cases.
+ *
+ * In XAUI/RXAUI mode where PFC/CBFC/HiGig2 is not used, an example programming
+ * would be as follows:
+ *
+ * @verbatim
+ * GMX_BPID_MAP0[VAL] = 1;
+ * GMX_BPID_MAP0[BPID] = xaui_bpid;
+ * GMX_BPID_MSK[MSK_OR] = 1;
+ * GMX_BPID_MSK[MSK_AND] = 0;
+ * @endverbatim
+ *
+ * In SGMII mode, an example programming would be as follows:
+ *
+ * @verbatim
+ * for (i=0; i<4; i++) [
+ * if (GMX_PRTi_CFG[EN]) [
+ * GMX_BPID_MAP(i*4)[VAL] = 1;
+ * GMX_BPID_MAP(i*4)[BPID] = sgmii_bpid(i);
+ * GMX_BPID_MSK[MSK_OR] = (1 << (i*4)) | GMX_BPID_MSK[MSK_OR];
+ * ]
+ * ]
+ * GMX_BPID_MSK[MSK_AND] = 0;
+ * @endverbatim
+ */
+union cvmx_gmxx_bpid_mapx {
+ uint64_t u64;
+ struct cvmx_gmxx_bpid_mapx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_17_63 : 47;
+ uint64_t status : 1; /**< Current received BP from IPD */
+ uint64_t reserved_9_15 : 7;
+ uint64_t val : 1; /**< Table entry is valid */
+ uint64_t reserved_6_7 : 2;
+ uint64_t bpid : 6; /**< Backpressure ID the entry maps to */
+#else
+ uint64_t bpid : 6;
+ uint64_t reserved_6_7 : 2;
+ uint64_t val : 1;
+ uint64_t reserved_9_15 : 7;
+ uint64_t status : 1;
+ uint64_t reserved_17_63 : 47;
+#endif
+ } s;
+ struct cvmx_gmxx_bpid_mapx_s cn68xx;
+ struct cvmx_gmxx_bpid_mapx_s cn68xxp1;
+};
+typedef union cvmx_gmxx_bpid_mapx cvmx_gmxx_bpid_mapx_t;
+
+/**
+ * cvmx_gmx#_bpid_msk
+ */
+union cvmx_gmxx_bpid_msk {
+ uint64_t u64;
+ struct cvmx_gmxx_bpid_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_48_63 : 16;
+ uint64_t msk_or : 16; /**< Assert physical BP when the backpressure ID vector
+ combined with MSK_OR indicates BP as follows.
+ phys_bp_msk_or =
+ (BPID_VECTOR<x:y> & MSK_OR<x:y>) != 0
+ phys_bp = phys_bp_msk_or || phys_bp_msk_and
+ In XAUI/RXAUI mode, x=15, y=0
+ In SGMII mode, x/y are set depending on the SGMII
+ interface.
+ SGMII interface0, x=3, y=0
+ SGMII interface1, x=7, y=4
+ SGMII interface2, x=11, y=8
+ SGMII interface3, x=15, y=12 */
+ uint64_t reserved_16_31 : 16;
+ uint64_t msk_and : 16; /**< Assert physical BP when the backpressure ID vector
+ combined with MSK_AND indicates BP as follows.
+ phys_bp_msk_and =
+ (BPID_VECTOR<x:y> & MSK_AND<x:y>) == MSK_AND<x:y>
+ phys_bp = phys_bp_msk_or || phys_bp_msk_and
+ In XAUI/RXAUI mode, x=15, y=0
+ In SGMII mode, x/y are set depending on the SGMII
+ interface.
+ SGMII interface0, x=3, y=0
+ SGMII interface1, x=7, y=4
+ SGMII interface2, x=11, y=8
+ SGMII interface3, x=15, y=12 */
+#else
+ uint64_t msk_and : 16;
+ uint64_t reserved_16_31 : 16;
+ uint64_t msk_or : 16;
+ uint64_t reserved_48_63 : 16;
+#endif
+ } s;
+ struct cvmx_gmxx_bpid_msk_s cn68xx;
+ struct cvmx_gmxx_bpid_msk_s cn68xxp1;
+};
+typedef union cvmx_gmxx_bpid_msk cvmx_gmxx_bpid_msk_t;
+
+/**
* cvmx_gmx#_clk_en
*
- * DO NOT DOCUMENT THIS REGISTER - IT IS NOT OFFICIAL
+ * DON'T PUT IN HRM*
*
*/
-union cvmx_gmxx_clk_en
-{
+union cvmx_gmxx_clk_en {
uint64_t u64;
- struct cvmx_gmxx_clk_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_clk_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t clk_en : 1; /**< Force the clock enables on */
#else
@@ -1979,12 +3549,62 @@ union cvmx_gmxx_clk_en
struct cvmx_gmxx_clk_en_s cn52xxp1;
struct cvmx_gmxx_clk_en_s cn56xx;
struct cvmx_gmxx_clk_en_s cn56xxp1;
+ struct cvmx_gmxx_clk_en_s cn61xx;
struct cvmx_gmxx_clk_en_s cn63xx;
struct cvmx_gmxx_clk_en_s cn63xxp1;
+ struct cvmx_gmxx_clk_en_s cn66xx;
+ struct cvmx_gmxx_clk_en_s cn68xx;
+ struct cvmx_gmxx_clk_en_s cn68xxp1;
+ struct cvmx_gmxx_clk_en_s cnf71xx;
};
typedef union cvmx_gmxx_clk_en cvmx_gmxx_clk_en_t;
/**
+ * cvmx_gmx#_ebp_dis
+ */
+union cvmx_gmxx_ebp_dis {
+ uint64_t u64;
+ struct cvmx_gmxx_ebp_dis_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_16_63 : 48;
+ uint64_t dis : 16; /**< BP channel disable
+ GMX has the ability to remap unused channels
+ in order to get down to GMX_TX_PIPE[NUMP]
+ channels. */
+#else
+ uint64_t dis : 16;
+ uint64_t reserved_16_63 : 48;
+#endif
+ } s;
+ struct cvmx_gmxx_ebp_dis_s cn68xx;
+ struct cvmx_gmxx_ebp_dis_s cn68xxp1;
+};
+typedef union cvmx_gmxx_ebp_dis cvmx_gmxx_ebp_dis_t;
+
+/**
+ * cvmx_gmx#_ebp_msk
+ */
+union cvmx_gmxx_ebp_msk {
+ uint64_t u64;
+ struct cvmx_gmxx_ebp_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_16_63 : 48;
+ uint64_t msk : 16; /**< BP channel mask
+ GMX can completely ignore the channel BP for
+ channels specified by the MSK field. Any channel
+ in which MSK == 1, will never send BP information
+ to PKO. */
+#else
+ uint64_t msk : 16;
+ uint64_t reserved_16_63 : 48;
+#endif
+ } s;
+ struct cvmx_gmxx_ebp_msk_s cn68xx;
+ struct cvmx_gmxx_ebp_msk_s cn68xxp1;
+};
+typedef union cvmx_gmxx_ebp_msk cvmx_gmxx_ebp_msk_t;
+
+/**
* cvmx_gmx#_hg2_control
*
* Notes:
@@ -2007,12 +3627,10 @@ typedef union cvmx_gmxx_clk_en cvmx_gmxx_clk_en_t;
* and GMX*_RX0_UDD_SKP[LEN]=16.) The HW can only auto-generate backpressure via HiGig2 messages
* (optionally, when HG2TX_EN=1) with the HiGig2 protocol.
*/
-union cvmx_gmxx_hg2_control
-{
+union cvmx_gmxx_hg2_control {
uint64_t u64;
- struct cvmx_gmxx_hg2_control_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_hg2_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63 : 45;
uint64_t hg2tx_en : 1; /**< Enable Transmission of HG2 phys and logl messages
When set, also disables HW auto-generated (802.3
@@ -2038,8 +3656,13 @@ union cvmx_gmxx_hg2_control
struct cvmx_gmxx_hg2_control_s cn52xx;
struct cvmx_gmxx_hg2_control_s cn52xxp1;
struct cvmx_gmxx_hg2_control_s cn56xx;
+ struct cvmx_gmxx_hg2_control_s cn61xx;
struct cvmx_gmxx_hg2_control_s cn63xx;
struct cvmx_gmxx_hg2_control_s cn63xxp1;
+ struct cvmx_gmxx_hg2_control_s cn66xx;
+ struct cvmx_gmxx_hg2_control_s cn68xx;
+ struct cvmx_gmxx_hg2_control_s cn68xxp1;
+ struct cvmx_gmxx_hg2_control_s cnf71xx;
};
typedef union cvmx_gmxx_hg2_control cvmx_gmxx_hg2_control_t;
@@ -2049,16 +3672,41 @@ typedef union cvmx_gmxx_hg2_control cvmx_gmxx_hg2_control_t;
* GMX_INF_MODE = Interface Mode
*
*/
-union cvmx_gmxx_inf_mode
-{
+union cvmx_gmxx_inf_mode {
uint64_t u64;
- struct cvmx_gmxx_inf_mode_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_12_63 : 52;
- uint64_t speed : 4; /**< Interface Speed */
- uint64_t reserved_6_7 : 2;
- uint64_t mode : 2; /**< Interface Electrical Operating Mode
+ struct cvmx_gmxx_inf_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_20_63 : 44;
+ uint64_t rate : 4; /**< SERDES speed rate
+ reset value is based on the QLM speed select
+ 0 = 1.25 Gbaud
+ 1 = 3.125 Gbaud
+ (only valid for GMX0 instance)
+ Software must not change RATE from its reset value */
+ uint64_t reserved_12_15 : 4;
+ uint64_t speed : 4; /**< Interface Speed
+ QLM speed pins which select reference clock
+ period and interface data rate. If the QLM PLL
+ inputs are correct, the speed setting correspond
+ to the following data rates (in Gbaud).
+ 0 = 5
+ 1 = 2.5
+ 2 = 2.5
+ 3 = 1.25
+ 4 = 1.25
+ 5 = 6.25
+ 6 = 5
+ 7 = 2.5
+ 8 = 3.125
+ 9 = 2.5
+ 10 = 1.25
+ 11 = 5
+ 12 = 6.25
+ 13 = 3.75
+ 14 = 3.125
+ 15 = QLM disabled */
+ uint64_t reserved_7_7 : 1;
+ uint64_t mode : 3; /**< Interface Electrical Operating Mode
- 0: SGMII (v1.8)
- 1: XAUI (IEEE 802.3-2005) */
uint64_t reserved_3_3 : 1;
@@ -2078,15 +3726,16 @@ union cvmx_gmxx_inf_mode
uint64_t en : 1;
uint64_t p0mii : 1;
uint64_t reserved_3_3 : 1;
- uint64_t mode : 2;
- uint64_t reserved_6_7 : 2;
+ uint64_t mode : 3;
+ uint64_t reserved_7_7 : 1;
uint64_t speed : 4;
- uint64_t reserved_12_63 : 52;
+ uint64_t reserved_12_15 : 4;
+ uint64_t rate : 4;
+ uint64_t reserved_20_63 : 44;
#endif
} s;
- struct cvmx_gmxx_inf_mode_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_inf_mode_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63 : 61;
uint64_t p0mii : 1; /**< Port 0 Interface Mode
- 0: Port 0 is RGMII
@@ -2107,9 +3756,8 @@ union cvmx_gmxx_inf_mode
uint64_t reserved_3_63 : 61;
#endif
} cn30xx;
- struct cvmx_gmxx_inf_mode_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_inf_mode_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t en : 1; /**< Interface Enable
Must be set to enable the packet interface.
@@ -2128,9 +3776,8 @@ union cvmx_gmxx_inf_mode
struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
- struct cvmx_gmxx_inf_mode_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_inf_mode_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t speed : 2; /**< Interface Speed
- 0: 1.250GHz
@@ -2167,11 +3814,30 @@ union cvmx_gmxx_inf_mode
struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
- struct cvmx_gmxx_inf_mode_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_inf_mode_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
- uint64_t speed : 4; /**< Interface Speed */
+ uint64_t speed : 4; /**< Interface Speed
+ QLM speed pins which select reference clock
+ period and interface data rate. If the QLM PLL
+ inputs are correct, the speed setting correspond
+ to the following data rates (in Gbaud).
+ 0 = 5
+ 1 = 2.5
+ 2 = 2.5
+ 3 = 1.25
+ 4 = 1.25
+ 5 = 6.25
+ 6 = 5
+ 7 = 2.5
+ 8 = 3.125
+ 9 = 2.5
+ 10 = 1.25
+ 11 = 5
+ 12 = 6.25
+ 13 = 3.75
+ 14 = 3.125
+ 15 = QLM disabled */
uint64_t reserved_5_7 : 3;
uint64_t mode : 1; /**< Interface Electrical Operating Mode
- 0: SGMII (v1.8)
@@ -2194,8 +3860,120 @@ union cvmx_gmxx_inf_mode
uint64_t speed : 4;
uint64_t reserved_12_63 : 52;
#endif
- } cn63xx;
- struct cvmx_gmxx_inf_mode_cn63xx cn63xxp1;
+ } cn61xx;
+ struct cvmx_gmxx_inf_mode_cn61xx cn63xx;
+ struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1;
+ struct cvmx_gmxx_inf_mode_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_20_63 : 44;
+ uint64_t rate : 4; /**< SERDES speed rate
+ reset value is based on the QLM speed select
+ 0 = 1.25 Gbaud
+ 1 = 3.125 Gbaud
+ (only valid for GMX0 instance)
+ Software must not change RATE from its reset value */
+ uint64_t reserved_12_15 : 4;
+ uint64_t speed : 4; /**< Interface Speed
+ QLM speed pins which select reference clock
+ period and interface data rate. If the QLM PLL
+ inputs are correct, the speed setting correspond
+ to the following data rates (in Gbaud).
+ 0 = 5
+ 1 = 2.5
+ 2 = 2.5
+ 3 = 1.25
+ 4 = 1.25
+ 5 = 6.25
+ 6 = 5
+ 7 = 2.5
+ 8 = 3.125
+ 9 = 2.5
+ 10 = 1.25
+ 11 = 5
+ 12 = 6.25
+ 13 = 3.75
+ 14 = 3.125
+ 15 = QLM disabled */
+ uint64_t reserved_5_7 : 3;
+ uint64_t mode : 1; /**< Interface Electrical Operating Mode
+ - 0: SGMII (v1.8)
+ - 1: XAUI (IEEE 802.3-2005) */
+ uint64_t reserved_2_3 : 2;
+ uint64_t en : 1; /**< Interface Enable
+ Must be set to enable the packet interface.
+ Should be enabled before any other requests to
+ GMX including enabling port back pressure with
+ IPD_CTL_STATUS[PBP_EN] */
+ uint64_t type : 1; /**< Interface Protocol Type
+ - 0: SGMII/1000Base-X
+ - 1: XAUI */
+#else
+ uint64_t type : 1;
+ uint64_t en : 1;
+ uint64_t reserved_2_3 : 2;
+ uint64_t mode : 1;
+ uint64_t reserved_5_7 : 3;
+ uint64_t speed : 4;
+ uint64_t reserved_12_15 : 4;
+ uint64_t rate : 4;
+ uint64_t reserved_20_63 : 44;
+#endif
+ } cn66xx;
+ struct cvmx_gmxx_inf_mode_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_12_63 : 52;
+ uint64_t speed : 4; /**< Interface Speed
+ QLM speed pins which select reference clock
+ period and interface data rate. If the QLM PLL
+ inputs are correct, the speed setting correspond
+ to the following data rates (in Gbaud).
+ 0 = 5
+ 1 = 2.5
+ 2 = 2.5
+ 3 = 1.25
+ 4 = 1.25
+ 5 = 6.25
+ 6 = 5
+ 7 = 2.5
+ 8 = 3.125
+ 9 = 2.5
+ 10 = 1.25
+ 11 = 5
+ 12 = 6.25
+ 13 = 3.75
+ 14 = 3.125
+ 15 = QLM disabled */
+ uint64_t reserved_7_7 : 1;
+ uint64_t mode : 3; /**< Interface Electrical Operating Mode
+ - 0: Reserved
+ - 1: Reserved
+ - 2: SGMII (v1.8)
+ - 3: XAUI (IEEE 802.3-2005)
+ - 4: Reserved
+ - 5: Reserved
+ - 6: Reserved
+ - 7: RXAUI */
+ uint64_t reserved_2_3 : 2;
+ uint64_t en : 1; /**< Interface Enable
+ Must be set to enable the packet interface.
+ Should be enabled before any other requests to
+ GMX including enabling port back pressure with
+ b IPD_CTL_STATUS[PBP_EN] */
+ uint64_t type : 1; /**< Interface Protocol Type
+ - 0: SGMII/1000Base-X
+ - 1: XAUI/RXAUI */
+#else
+ uint64_t type : 1;
+ uint64_t en : 1;
+ uint64_t reserved_2_3 : 2;
+ uint64_t mode : 3;
+ uint64_t reserved_7_7 : 1;
+ uint64_t speed : 4;
+ uint64_t reserved_12_63 : 52;
+#endif
+ } cn68xx;
+ struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1;
+ struct cvmx_gmxx_inf_mode_cn61xx cnf71xx;
};
typedef union cvmx_gmxx_inf_mode cvmx_gmxx_inf_mode_t;
@@ -2205,13 +3983,13 @@ typedef union cvmx_gmxx_inf_mode cvmx_gmxx_inf_mode_t;
* GMX_NXA_ADR = NXA Port Address
*
*/
-union cvmx_gmxx_nxa_adr
-{
+union cvmx_gmxx_nxa_adr {
uint64_t u64;
- struct cvmx_gmxx_nxa_adr_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_6_63 : 58;
+ struct cvmx_gmxx_nxa_adr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_23_63 : 41;
+ uint64_t pipe : 7; /**< Logged pipe for NXP exceptions */
+ uint64_t reserved_6_15 : 10;
uint64_t prt : 6; /**< Logged address for NXA exceptions
The logged address will be from the first
exception that caused the problem. NCB has
@@ -2219,26 +3997,76 @@ union cvmx_gmxx_nxa_adr
(only PRT[3:0]) */
#else
uint64_t prt : 6;
- uint64_t reserved_6_63 : 58;
+ uint64_t reserved_6_15 : 10;
+ uint64_t pipe : 7;
+ uint64_t reserved_23_63 : 41;
#endif
} s;
- struct cvmx_gmxx_nxa_adr_s cn30xx;
- struct cvmx_gmxx_nxa_adr_s cn31xx;
- struct cvmx_gmxx_nxa_adr_s cn38xx;
- struct cvmx_gmxx_nxa_adr_s cn38xxp2;
- struct cvmx_gmxx_nxa_adr_s cn50xx;
- struct cvmx_gmxx_nxa_adr_s cn52xx;
- struct cvmx_gmxx_nxa_adr_s cn52xxp1;
- struct cvmx_gmxx_nxa_adr_s cn56xx;
- struct cvmx_gmxx_nxa_adr_s cn56xxp1;
- struct cvmx_gmxx_nxa_adr_s cn58xx;
- struct cvmx_gmxx_nxa_adr_s cn58xxp1;
- struct cvmx_gmxx_nxa_adr_s cn63xx;
- struct cvmx_gmxx_nxa_adr_s cn63xxp1;
+ struct cvmx_gmxx_nxa_adr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_6_63 : 58;
+ uint64_t prt : 6; /**< Logged address for NXA exceptions
+ The logged address will be from the first
+ exception that caused the problem. NCB has
+ higher priority than PKO and will win. */
+#else
+ uint64_t prt : 6;
+ uint64_t reserved_6_63 : 58;
+#endif
+ } cn30xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn31xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn38xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn50xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn52xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn56xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn58xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn61xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn63xx;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1;
+ struct cvmx_gmxx_nxa_adr_cn30xx cn66xx;
+ struct cvmx_gmxx_nxa_adr_s cn68xx;
+ struct cvmx_gmxx_nxa_adr_s cn68xxp1;
+ struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx;
};
typedef union cvmx_gmxx_nxa_adr cvmx_gmxx_nxa_adr_t;
/**
+ * cvmx_gmx#_pipe_status
+ *
+ * DON'T PUT IN HRM*
+ *
+ */
+union cvmx_gmxx_pipe_status {
+ uint64_t u64;
+ struct cvmx_gmxx_pipe_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_20_63 : 44;
+ uint64_t ovr : 4; /**< Pipe credit return FIFO has overflowed. */
+ uint64_t reserved_12_15 : 4;
+ uint64_t bp : 4; /**< Pipe credit return FIFO has filled up and asserted
+ backpressure to the datapath. */
+ uint64_t reserved_4_7 : 4;
+ uint64_t stop : 4; /**< PKO has asserted backpressure on the pipe credit
+ return interface. */
+#else
+ uint64_t stop : 4;
+ uint64_t reserved_4_7 : 4;
+ uint64_t bp : 4;
+ uint64_t reserved_12_15 : 4;
+ uint64_t ovr : 4;
+ uint64_t reserved_20_63 : 44;
+#endif
+ } s;
+ struct cvmx_gmxx_pipe_status_s cn68xx;
+ struct cvmx_gmxx_pipe_status_s cn68xxp1;
+};
+typedef union cvmx_gmxx_pipe_status cvmx_gmxx_pipe_status_t;
+
+/**
* cvmx_gmx#_prt#_cbfc_ctl
*
* ** HG2 message CSRs end
@@ -2248,12 +4076,10 @@ typedef union cvmx_gmxx_nxa_adr cvmx_gmxx_nxa_adr_t;
* XOFF for a specific port is XOFF<prt> = (PHYS_EN<prt> & PHYS_BP) | (LOGL_EN<prt> & LOGL_BP<prt>)
*
*/
-union cvmx_gmxx_prtx_cbfc_ctl
-{
+union cvmx_gmxx_prtx_cbfc_ctl {
uint64_t u64;
- struct cvmx_gmxx_prtx_cbfc_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_prtx_cbfc_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t phys_en : 16; /**< Determines which ports will have physical
backpressure pause packets.
The value pplaced in the Class Enable Vector
@@ -2294,8 +4120,13 @@ union cvmx_gmxx_prtx_cbfc_ctl
} s;
struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
+ struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx;
struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx;
struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1;
+ struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx;
+ struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx;
+ struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1;
+ struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_prtx_cbfc_ctl cvmx_gmxx_prtx_cbfc_ctl_t;
@@ -2305,13 +4136,13 @@ typedef union cvmx_gmxx_prtx_cbfc_ctl cvmx_gmxx_prtx_cbfc_ctl_t;
* GMX_PRT_CFG = Port description
*
*/
-union cvmx_gmxx_prtx_cfg
-{
+union cvmx_gmxx_prtx_cfg {
uint64_t u64;
- struct cvmx_gmxx_prtx_cfg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_14_63 : 50;
+ struct cvmx_gmxx_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_22_63 : 42;
+ uint64_t pknd : 6; /**< Port Kind used for processing the packet by PKI */
+ uint64_t reserved_14_15 : 2;
uint64_t tx_idle : 1; /**< TX Machine is idle */
uint64_t rx_idle : 1; /**< RX Machine is idle */
uint64_t reserved_9_11 : 3;
@@ -2354,12 +4185,13 @@ union cvmx_gmxx_prtx_cfg
uint64_t reserved_9_11 : 3;
uint64_t rx_idle : 1;
uint64_t tx_idle : 1;
- uint64_t reserved_14_63 : 50;
+ uint64_t reserved_14_15 : 2;
+ uint64_t pknd : 6;
+ uint64_t reserved_22_63 : 42;
#endif
} s;
- struct cvmx_gmxx_prtx_cfg_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_prtx_cfg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation
0 = 512 bitimes (10/100Mbs operation)
@@ -2392,14 +4224,66 @@ union cvmx_gmxx_prtx_cfg
struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
- struct cvmx_gmxx_prtx_cfg_s cn52xx;
- struct cvmx_gmxx_prtx_cfg_s cn52xxp1;
- struct cvmx_gmxx_prtx_cfg_s cn56xx;
- struct cvmx_gmxx_prtx_cfg_s cn56xxp1;
+ struct cvmx_gmxx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_14_63 : 50;
+ uint64_t tx_idle : 1; /**< TX Machine is idle */
+ uint64_t rx_idle : 1; /**< RX Machine is idle */
+ uint64_t reserved_9_11 : 3;
+ uint64_t speed_msb : 1; /**< Link Speed MSB [SPEED_MSB:SPEED]
+ 10 = 10Mbs operation
+ 00 = 100Mbs operation
+ 01 = 1000Mbs operation
+ 11 = Reserved
+ (SGMII/1000Base-X only) */
+ uint64_t reserved_4_7 : 4;
+ uint64_t slottime : 1; /**< Slot Time for Half-Duplex operation
+ 0 = 512 bitimes (10/100Mbs operation)
+ 1 = 4096 bitimes (1000Mbs operation)
+ (SGMII/1000Base-X only) */
+ uint64_t duplex : 1; /**< Duplex
+ 0 = Half Duplex (collisions/extentions/bursts)
+ 1 = Full Duplex
+ (SGMII/1000Base-X only) */
+ uint64_t speed : 1; /**< Link Speed LSB [SPEED_MSB:SPEED]
+ 10 = 10Mbs operation
+ 00 = 100Mbs operation
+ 01 = 1000Mbs operation
+ 11 = Reserved
+ (SGMII/1000Base-X only) */
+ uint64_t en : 1; /**< Link Enable
+ When EN is clear, packets will not be received
+ or transmitted (including PAUSE and JAM packets).
+ If EN is cleared while a packet is currently
+ being received or transmitted, the packet will
+ be allowed to complete before the bus is idled.
+ On the RX side, subsequent packets in a burst
+ will be ignored. */
+#else
+ uint64_t en : 1;
+ uint64_t speed : 1;
+ uint64_t duplex : 1;
+ uint64_t slottime : 1;
+ uint64_t reserved_4_7 : 4;
+ uint64_t speed_msb : 1;
+ uint64_t reserved_9_11 : 3;
+ uint64_t rx_idle : 1;
+ uint64_t tx_idle : 1;
+ uint64_t reserved_14_63 : 50;
+#endif
+ } cn52xx;
+ struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1;
+ struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx;
+ struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1;
struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
- struct cvmx_gmxx_prtx_cfg_s cn63xx;
- struct cvmx_gmxx_prtx_cfg_s cn63xxp1;
+ struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx;
+ struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx;
+ struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1;
+ struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx;
+ struct cvmx_gmxx_prtx_cfg_s cn68xx;
+ struct cvmx_gmxx_prtx_cfg_s cn68xxp1;
+ struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx;
};
typedef union cvmx_gmxx_prtx_cfg cvmx_gmxx_prtx_cfg_t;
@@ -2409,20 +4293,22 @@ typedef union cvmx_gmxx_prtx_cfg cvmx_gmxx_prtx_cfg_t;
* GMX_RX_ADR_CAM = Address Filtering Control
*
*/
-union cvmx_gmxx_rxx_adr_cam0
-{
+union cvmx_gmxx_rxx_adr_cam0 {
uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_adr_cam0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to GMX_RX_ADR_CAM will not
- change the CSR when GMX_PRT_CFG[EN] is enabled
+
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses.
- In XAUI mode, all ports will reflect the data
- written to port0. */
+
+ ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+ in either SGMII or XAUI mode such that any GMX
+ MAC can use any of the 32 common DMAC entries.
+
+ GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+ registers used in XAUI mode. */
#else
uint64_t adr : 64;
#endif
@@ -2438,8 +4324,13 @@ union cvmx_gmxx_rxx_adr_cam0
struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn61xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn63xx;
struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1;
+ struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam0_t;
@@ -2449,20 +4340,22 @@ typedef union cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam0_t;
* GMX_RX_ADR_CAM = Address Filtering Control
*
*/
-union cvmx_gmxx_rxx_adr_cam1
-{
+union cvmx_gmxx_rxx_adr_cam1 {
uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_adr_cam1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to GMX_RX_ADR_CAM will not
- change the CSR when GMX_PRT_CFG[EN] is enabled
+
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses.
- In XAUI mode, all ports will reflect the data
- written to port0. */
+
+ ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+ in either SGMII or XAUI mode such that any GMX
+ MAC can use any of the 32 common DMAC entries.
+
+ GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+ registers used in XAUI mode. */
#else
uint64_t adr : 64;
#endif
@@ -2478,8 +4371,13 @@ union cvmx_gmxx_rxx_adr_cam1
struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn61xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn63xx;
struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1;
+ struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam1_t;
@@ -2489,20 +4387,22 @@ typedef union cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam1_t;
* GMX_RX_ADR_CAM = Address Filtering Control
*
*/
-union cvmx_gmxx_rxx_adr_cam2
-{
+union cvmx_gmxx_rxx_adr_cam2 {
uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_adr_cam2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to GMX_RX_ADR_CAM will not
- change the CSR when GMX_PRT_CFG[EN] is enabled
+
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses.
- In XAUI mode, all ports will reflect the data
- written to port0. */
+
+ ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+ in either SGMII or XAUI mode such that any GMX
+ MAC can use any of the 32 common DMAC entries.
+
+ GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+ registers used in XAUI mode. */
#else
uint64_t adr : 64;
#endif
@@ -2518,8 +4418,13 @@ union cvmx_gmxx_rxx_adr_cam2
struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn61xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn63xx;
struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1;
+ struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_adr_cam2 cvmx_gmxx_rxx_adr_cam2_t;
@@ -2529,20 +4434,22 @@ typedef union cvmx_gmxx_rxx_adr_cam2 cvmx_gmxx_rxx_adr_cam2_t;
* GMX_RX_ADR_CAM = Address Filtering Control
*
*/
-union cvmx_gmxx_rxx_adr_cam3
-{
+union cvmx_gmxx_rxx_adr_cam3 {
uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam3_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_adr_cam3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to GMX_RX_ADR_CAM will not
- change the CSR when GMX_PRT_CFG[EN] is enabled
+
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses.
- In XAUI mode, all ports will reflect the data
- written to port0. */
+
+ ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+ in either SGMII or XAUI mode such that any GMX
+ MAC can use any of the 32 common DMAC entries.
+
+ GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+ registers used in XAUI mode. */
#else
uint64_t adr : 64;
#endif
@@ -2558,8 +4465,13 @@ union cvmx_gmxx_rxx_adr_cam3
struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn61xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn63xx;
struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1;
+ struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam3_t;
@@ -2569,20 +4481,22 @@ typedef union cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam3_t;
* GMX_RX_ADR_CAM = Address Filtering Control
*
*/
-union cvmx_gmxx_rxx_adr_cam4
-{
+union cvmx_gmxx_rxx_adr_cam4 {
uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam4_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_adr_cam4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to GMX_RX_ADR_CAM will not
- change the CSR when GMX_PRT_CFG[EN] is enabled
+
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses.
- In XAUI mode, all ports will reflect the data
- written to port0. */
+
+ ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+ in either SGMII or XAUI mode such that any GMX
+ MAC can use any of the 32 common DMAC entries.
+
+ GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+ registers used in XAUI mode. */
#else
uint64_t adr : 64;
#endif
@@ -2598,8 +4512,13 @@ union cvmx_gmxx_rxx_adr_cam4
struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn61xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn63xx;
struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1;
+ struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam4_t;
@@ -2609,20 +4528,22 @@ typedef union cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam4_t;
* GMX_RX_ADR_CAM = Address Filtering Control
*
*/
-union cvmx_gmxx_rxx_adr_cam5
-{
+union cvmx_gmxx_rxx_adr_cam5 {
uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam5_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_adr_cam5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to GMX_RX_ADR_CAM will not
- change the CSR when GMX_PRT_CFG[EN] is enabled
+
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses.
- In XAUI mode, all ports will reflect the data
- written to port0. */
+
+ ALL GMX_RX[0..3]_ADR_CAM[0..5] CSRs may be used
+ in either SGMII or XAUI mode such that any GMX
+ MAC can use any of the 32 common DMAC entries.
+
+ GMX_RX[1..3]_ADR_CAM[0..5] are the only non-port0
+ registers used in XAUI mode. */
#else
uint64_t adr : 64;
#endif
@@ -2638,25 +4559,114 @@ union cvmx_gmxx_rxx_adr_cam5
struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn61xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn63xx;
struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1;
+ struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_adr_cam5 cvmx_gmxx_rxx_adr_cam5_t;
/**
+ * cvmx_gmx#_rx#_adr_cam_all_en
+ *
+ * GMX_RX_ADR_CAM_ALL_EN = Address Filtering Control Enable
+ *
+ */
+union cvmx_gmxx_rxx_adr_cam_all_en {
+ uint64_t u64;
+ struct cvmx_gmxx_rxx_adr_cam_all_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_32_63 : 32;
+ uint64_t en : 32; /**< CAM Entry Enables
+
+ GMX has 32 DMAC entries that can be accessed with
+ the GMX_RX[0..3]_ADR_CAM[0..5] CSRs.
+ These 32 DMAC entries can be used by any of the
+ four SGMII MACs or the XAUI MAC.
+
+ Each port interface has independent control of
+ which of the 32 DMAC entries to include in the
+ CAM lookup.
+
+ GMX_RXx_ADR_CAM_ALL_EN was not present in legacy
+ GMX implemenations which had only eight DMAC CAM
+ entries. New applications may choose to ignore
+ GMX_RXx_ADR_CAM_EN using GMX_RX_ADR_CAM_ALL_EN
+ instead.
+
+ EN represents the full 32 indepedent per MAC
+ enables.
+
+ Writes to EN will be reflected in
+ GMX_RXx_ADR_CAM_EN[EN] and writes to
+ GMX_RXx_ADR_CAM_EN[EN] will be reflected in EN.
+ Refer to GMX_RXx_ADR_CAM_EN for the CSR mapping.
+
+ In XAUI mode, only GMX_RX0_ADR_CAM_ALL_EN is used
+ and GMX_RX[1,2,3]_ADR_CAM_ALL_EN should not be
+ used. */
+#else
+ uint64_t en : 32;
+ uint64_t reserved_32_63 : 32;
+#endif
+ } s;
+ struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx;
+ struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx;
+};
+typedef union cvmx_gmxx_rxx_adr_cam_all_en cvmx_gmxx_rxx_adr_cam_all_en_t;
+
+/**
* cvmx_gmx#_rx#_adr_cam_en
*
* GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
*
*/
-union cvmx_gmxx_rxx_adr_cam_en
-{
+union cvmx_gmxx_rxx_adr_cam_en {
uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_adr_cam_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
- uint64_t en : 8; /**< CAM Entry Enables */
+ uint64_t en : 8; /**< CAM Entry Enables
+
+ GMX has 32 DMAC entries that can be accessed with
+ the GMX_RX[0..3]_ADR_CAM[0..5] CSRs.
+ These 32 DMAC entries can be used by any of the
+ four SGMII MACs or the XAUI MAC.
+
+ Each port interface has independent control of
+ which of the 32 DMAC entries to include in the
+ CAM lookup.
+
+ Legacy GMX implementations were able to CAM
+ against eight DMAC entries while current
+ implementations use 32 common entries.
+ This register is intended for legacy applications
+ that only require eight DMAC CAM entries per MAC.
+ New applications may choose to ignore
+ GMX_RXx_ADR_CAM_EN using GMX_RXx_ADR_CAM_ALL_EN
+ instead.
+
+ EN controls the enables for the eight legacy CAM
+ entries as follows:
+ port0, EN = GMX_RX0_ADR_CAM_ALL_EN[EN<7:0>]
+ port1, EN = GMX_RX1_ADR_CAM_ALL_EN[EN<15:8>]
+ port2, EN = GMX_RX2_ADR_CAM_ALL_EN[EN<23:16>]
+ port3, EN = GMX_RX3_ADR_CAM_ALL_EN[EN<31:24>]
+
+ The full 32 indepedent per MAC enables are in
+ GMX_RX_ADR_CAM_ALL_EN.
+
+ Therefore, writes to GMX_RXX_ADR_CAM_ALL_EN[EN]
+ will be reflected in EN and writes to EN will be
+ reflected in GMX_RXX_ADR_CAM_ALL_EN[EN].
+
+ In XAUI mode, only GMX_RX0_ADR_CAM_EN is used and
+ GMX_RX[1,2,3]_ADR_CAM_EN should not be used. */
#else
uint64_t en : 8;
uint64_t reserved_8_63 : 56;
@@ -2673,8 +4683,13 @@ union cvmx_gmxx_rxx_adr_cam_en
struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx;
struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1;
+ struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_cam_en_t;
@@ -2686,46 +4701,48 @@ typedef union cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_cam_en_t;
*
* Notes:
* * ALGORITHM
- * Here is some pseudo code that represents the address filter behavior.
- *
- * @verbatim
- * bool dmac_addr_filter(uint8 prt, uint48 dmac) [
- * ASSERT(prt >= 0 && prt <= 3);
- * if (is_bcst(dmac)) // broadcast accept
- * return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
- * if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1) // multicast reject
- * return REJECT;
- * if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2) // multicast accept
- * return ACCEPT;
- *
- * cam_hit = 0;
- *
- * for (i=0; i<8; i++) [
- * if (GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)
- * continue;
- * uint48 unswizzled_mac_adr = 0x0;
- * for (j=5; j>=0; j--) [
- * unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];
- * ]
- * if (unswizzled_mac_adr == dmac) [
- * cam_hit = 1;
- * break;
+ * Here is some pseudo code that represents the address filter behavior.
+ *
+ * @verbatim
+ * bool dmac_addr_filter(uint8 prt, uint48 dmac) [
+ * ASSERT(prt >= 0 && prt <= 3);
+ * if (is_bcst(dmac)) // broadcast accept
+ * return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
+ * if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1) // multicast reject
+ * return REJECT;
+ * if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2) // multicast accept
+ * return ACCEPT;
+ *
+ * cam_hit = 0;
+ *
+ * for (i=0; i<32; i++) [
+ * if (GMX_RX[prt]_ADR_CAM_ALL_EN[EN<i>] == 0)
+ * continue;
+ * uint48 unswizzled_mac_adr = 0x0;
+ * for (j=5; j>=0; j--) [
+ * unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[i>>3]_ADR_CAM[j][ADR<(i&7)*8+7:(i&7)*8>];
+ * ]
+ * if (unswizzled_mac_adr == dmac) [
+ * cam_hit = 1;
+ * break;
+ * ]
* ]
+ *
+ * if (cam_hit)
+ * return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
+ * else
+ * return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
* ]
+ * @endverbatim
*
- * if (cam_hit)
- * return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
- * else
- * return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
- * ]
- * @endverbatim
+ * * XAUI Mode
+ *
+ * In XAUI mode, only GMX_RX0_ADR_CTL is used. GMX_RX[1,2,3]_ADR_CTL should not be used.
*/
-union cvmx_gmxx_rxx_adr_ctl
-{
+union cvmx_gmxx_rxx_adr_ctl {
uint64_t u64;
- struct cvmx_gmxx_rxx_adr_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t cam_mode : 1; /**< Allow or deny DMAC address filter
0 = reject the packet on DMAC address match
@@ -2754,8 +4771,13 @@ union cvmx_gmxx_rxx_adr_ctl
struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn61xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn63xx;
struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn66xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn68xx;
+ struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1;
+ struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_adr_ctl_t;
@@ -2786,12 +4808,10 @@ typedef union cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_adr_ctl_t;
*
* where l2_size = MAX(0, total_packet_size - GMX_RX_UDD_SKP[LEN] - ((GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
*/
-union cvmx_gmxx_rxx_decision
-{
+union cvmx_gmxx_rxx_decision {
uint64_t u64;
- struct cvmx_gmxx_rxx_decision_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_decision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t cnt : 5; /**< The byte count to decide when to accept or filter
a packet. */
@@ -2811,8 +4831,13 @@ union cvmx_gmxx_rxx_decision
struct cvmx_gmxx_rxx_decision_s cn56xxp1;
struct cvmx_gmxx_rxx_decision_s cn58xx;
struct cvmx_gmxx_rxx_decision_s cn58xxp1;
+ struct cvmx_gmxx_rxx_decision_s cn61xx;
struct cvmx_gmxx_rxx_decision_s cn63xx;
struct cvmx_gmxx_rxx_decision_s cn63xxp1;
+ struct cvmx_gmxx_rxx_decision_s cn66xx;
+ struct cvmx_gmxx_rxx_decision_s cn68xx;
+ struct cvmx_gmxx_rxx_decision_s cn68xxp1;
+ struct cvmx_gmxx_rxx_decision_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_decision cvmx_gmxx_rxx_decision_t;
@@ -2827,12 +4852,10 @@ typedef union cvmx_gmxx_rxx_decision cvmx_gmxx_rxx_decision_t;
*
* In XAUI mode prt0 is used for checking.
*/
-union cvmx_gmxx_rxx_frm_chk
-{
+union cvmx_gmxx_rxx_frm_chk {
uint64_t u64;
- struct cvmx_gmxx_rxx_frm_chk_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_chk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */
uint64_t skperr : 1; /**< Skipper error */
@@ -2863,9 +4886,8 @@ union cvmx_gmxx_rxx_frm_chk
struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
- struct cvmx_gmxx_rxx_frm_chk_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_chk_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t niberr : 1; /**< Nibble error (hi_nibble != lo_nibble) */
uint64_t skperr : 1; /**< Skipper error */
@@ -2891,9 +4913,8 @@ union cvmx_gmxx_rxx_frm_chk
uint64_t reserved_10_63 : 54;
#endif
} cn50xx;
- struct cvmx_gmxx_rxx_frm_chk_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_chk_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t skperr : 1; /**< Skipper error */
uint64_t rcverr : 1; /**< Frame was received with Data reception error */
@@ -2921,9 +4942,8 @@ union cvmx_gmxx_rxx_frm_chk
struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
- struct cvmx_gmxx_rxx_frm_chk_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_chk_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t skperr : 1; /**< Skipper error */
uint64_t rcverr : 1; /**< Frame was received with Data reception error */
@@ -2945,8 +4965,13 @@ union cvmx_gmxx_rxx_frm_chk
uint64_t skperr : 1;
uint64_t reserved_9_63 : 55;
#endif
- } cn63xx;
- struct cvmx_gmxx_rxx_frm_chk_cn63xx cn63xxp1;
+ } cn61xx;
+ struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx;
+ struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1;
+ struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx;
+ struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx;
+ struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1;
+ struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx;
};
typedef union cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_chk_t;
@@ -2979,12 +5004,10 @@ typedef union cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_chk_t;
* would constitute an exception which should be handled by the processing
* cores. PAUSE packets should not be forwarded.
*/
-union cvmx_gmxx_rxx_frm_ctl
-{
+union cvmx_gmxx_rxx_frm_ctl {
uint64_t u64;
- struct cvmx_gmxx_rxx_frm_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63 : 51;
uint64_t ptp_mode : 1; /**< Timestamp mode
When PTP_MODE is set, a 64-bit timestamp will be
@@ -3004,7 +5027,8 @@ union cvmx_gmxx_rxx_frm_ctl
PIP_PRT_CFGx[HIGIG_EN] should be 0.
PIP_FRM_CHKx[MAXLEN] should be increased by 8.
PIP_FRM_CHKx[MINLEN] should be increased by 8.
- PIP_TAG_INCx[EN] should be adjusted. */
+ PIP_TAG_INCx[EN] should be adjusted.
+ PIP_PRT_CFGBx[ALT_SKP_EN] should be 0. */
uint64_t reserved_11_11 : 1;
uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks
due to PARITAL packets */
@@ -3062,9 +5086,8 @@ union cvmx_gmxx_rxx_frm_ctl
uint64_t reserved_13_63 : 51;
#endif
} s;
- struct cvmx_gmxx_rxx_frm_ctl_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t pad_len : 1; /**< When set, disables the length check for non-min
sized pkts with padding in the client data */
@@ -3096,9 +5119,8 @@ union cvmx_gmxx_rxx_frm_ctl
uint64_t reserved_9_63 : 55;
#endif
} cn30xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */
uint64_t pre_free : 1; /**< Allows for less strict PREAMBLE checking.
@@ -3129,9 +5151,8 @@ union cvmx_gmxx_rxx_frm_ctl
} cn31xx;
struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
- struct cvmx_gmxx_rxx_frm_ctl_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63 : 53;
uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks
due to PARITAL packets */
@@ -3173,9 +5194,8 @@ union cvmx_gmxx_rxx_frm_ctl
struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte
regardless of the number of previous PREAMBLE
@@ -3218,9 +5238,8 @@ union cvmx_gmxx_rxx_frm_ctl
uint64_t reserved_10_63 : 54;
#endif
} cn56xxp1;
- struct cvmx_gmxx_rxx_frm_ctl_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63 : 53;
uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks
due to PARITAL packets
@@ -3265,9 +5284,8 @@ union cvmx_gmxx_rxx_frm_ctl
#endif
} cn58xx;
struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
- struct cvmx_gmxx_rxx_frm_ctl_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63 : 51;
uint64_t ptp_mode : 1; /**< Timestamp mode
When PTP_MODE is set, a 64-bit timestamp will be
@@ -3287,7 +5305,8 @@ union cvmx_gmxx_rxx_frm_ctl
PIP_PRT_CFGx[HIGIG_EN] should be 0.
PIP_FRM_CHKx[MAXLEN] should be increased by 8.
PIP_FRM_CHKx[MINLEN] should be increased by 8.
- PIP_TAG_INCx[EN] should be adjusted. */
+ PIP_TAG_INCx[EN] should be adjusted.
+ PIP_PRT_CFGBx[ALT_SKP_EN] should be 0. */
uint64_t reserved_11_11 : 1;
uint64_t null_dis : 1; /**< When set, do not modify the MOD bits on NULL ticks
due to PARITAL packets */
@@ -3340,8 +5359,13 @@ union cvmx_gmxx_rxx_frm_ctl
uint64_t ptp_mode : 1;
uint64_t reserved_13_63 : 51;
#endif
- } cn63xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn63xx cn63xxp1;
+ } cn61xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1;
+ struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx;
+ struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1;
+ struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx;
};
typedef union cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_ctl_t;
@@ -3359,12 +5383,10 @@ typedef union cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_ctl_t;
* are within the maximum length parameter to be rejected because they exceed
* the GMX_RX_JABBER[CNT] limit.
*/
-union cvmx_gmxx_rxx_frm_max
-{
+union cvmx_gmxx_rxx_frm_max {
uint64_t u64;
- struct cvmx_gmxx_rxx_frm_max_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t len : 16; /**< Byte count for Max-sized frame check
GMX_RXn_FRM_CHK[MAXERR] enables the check for
@@ -3398,12 +5420,10 @@ typedef union cvmx_gmxx_rxx_frm_max cvmx_gmxx_rxx_frm_max_t;
* In spi4 mode, all spi4 ports use prt0 for checking.
*
*/
-union cvmx_gmxx_rxx_frm_min
-{
+union cvmx_gmxx_rxx_frm_min {
uint64_t u64;
- struct cvmx_gmxx_rxx_frm_min_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t len : 16; /**< Byte count for Min-sized frame check
GMX_RXn_FRM_CHK[MINERR] enables the check for
@@ -3432,12 +5452,10 @@ typedef union cvmx_gmxx_rxx_frm_min cvmx_gmxx_rxx_frm_min_t;
* GMX_RX_IFG = RX Min IFG
*
*/
-union cvmx_gmxx_rxx_ifg
-{
+union cvmx_gmxx_rxx_ifg {
uint64_t u64;
- struct cvmx_gmxx_rxx_ifg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t ifg : 4; /**< Min IFG (in IFG*8 bits) between packets used to
determine IFGERR. Normally IFG is 96 bits.
@@ -3463,8 +5481,13 @@ union cvmx_gmxx_rxx_ifg
struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
struct cvmx_gmxx_rxx_ifg_s cn58xx;
struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
+ struct cvmx_gmxx_rxx_ifg_s cn61xx;
struct cvmx_gmxx_rxx_ifg_s cn63xx;
struct cvmx_gmxx_rxx_ifg_s cn63xxp1;
+ struct cvmx_gmxx_rxx_ifg_s cn66xx;
+ struct cvmx_gmxx_rxx_ifg_s cn68xx;
+ struct cvmx_gmxx_rxx_ifg_s cn68xxp1;
+ struct cvmx_gmxx_rxx_ifg_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_ifg_t;
@@ -3478,12 +5501,10 @@ typedef union cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_ifg_t;
* In XAUI mode prt0 is used for checking.
*
*/
-union cvmx_gmxx_rxx_int_en
-{
+union cvmx_gmxx_rxx_int_en {
uint64_t u64;
- struct cvmx_gmxx_rxx_int_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63 : 35;
uint64_t hg2cc : 1; /**< HiGig2 CRC8 or Control char error interrupt enable */
uint64_t hg2fld : 1; /**< HiGig2 Bad field error interrupt enable */
@@ -3562,9 +5583,8 @@ union cvmx_gmxx_rxx_int_en
uint64_t reserved_29_63 : 35;
#endif
} s;
- struct cvmx_gmxx_rxx_int_en_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63 : 45;
uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */
uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */
@@ -3611,9 +5631,8 @@ union cvmx_gmxx_rxx_int_en
struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
- struct cvmx_gmxx_rxx_int_en_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_en_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */
uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */
@@ -3659,9 +5678,8 @@ union cvmx_gmxx_rxx_int_en
uint64_t reserved_20_63 : 44;
#endif
} cn50xx;
- struct cvmx_gmxx_rxx_int_en_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63 : 35;
uint64_t hg2cc : 1; /**< HiGig2 CRC8 or Control char error interrupt enable */
uint64_t hg2fld : 1; /**< HiGig2 Bad field error interrupt enable */
@@ -3736,9 +5754,8 @@ union cvmx_gmxx_rxx_int_en
} cn52xx;
struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
- struct cvmx_gmxx_rxx_int_en_cn56xxp1
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_27_63 : 37;
uint64_t undat : 1; /**< Unexpected Data
(XAUI Mode only) */
@@ -3807,9 +5824,8 @@ union cvmx_gmxx_rxx_int_en
uint64_t reserved_27_63 : 37;
#endif
} cn56xxp1;
- struct cvmx_gmxx_rxx_int_en_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_en_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */
uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */
@@ -3856,9 +5872,8 @@ union cvmx_gmxx_rxx_int_en
#endif
} cn58xx;
struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
- struct cvmx_gmxx_rxx_int_en_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_en_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63 : 35;
uint64_t hg2cc : 1; /**< HiGig2 CRC8 or Control char error interrupt enable */
uint64_t hg2fld : 1; /**< HiGig2 Bad field error interrupt enable */
@@ -3930,8 +5945,13 @@ union cvmx_gmxx_rxx_int_en
uint64_t hg2cc : 1;
uint64_t reserved_29_63 : 35;
#endif
- } cn63xx;
- struct cvmx_gmxx_rxx_int_en_cn63xx cn63xxp1;
+ } cn61xx;
+ struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx;
+ struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1;
+ struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx;
+ struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx;
+ struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1;
+ struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx;
};
typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;
@@ -3989,7 +6009,7 @@ typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;
* (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.
* Does not check the number of PREAMBLE cycles.
*
- * (C) OVRERR - Not to be included in the HRM
+ * (C) OVRERR -
*
* OVRERR is an architectural assertion check internal to GMX to
* make sure no assumption was violated. In a correctly operating
@@ -4006,12 +6026,10 @@ typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;
*
* (D) In XAUI mode prt0 is used for interrupt logging.
*/
-union cvmx_gmxx_rxx_int_reg
-{
+union cvmx_gmxx_rxx_int_reg {
uint64_t u64;
- struct cvmx_gmxx_rxx_int_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63 : 35;
uint64_t hg2cc : 1; /**< HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
@@ -4111,9 +6129,8 @@ union cvmx_gmxx_rxx_int_reg
uint64_t reserved_29_63 : 35;
#endif
} s;
- struct cvmx_gmxx_rxx_int_reg_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63 : 45;
uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */
uint64_t phy_spd : 1; /**< Change in the RMGII inbound LinkSpeed */
@@ -4162,9 +6179,8 @@ union cvmx_gmxx_rxx_int_reg
struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
- struct cvmx_gmxx_rxx_int_reg_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_reg_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */
uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */
@@ -4212,9 +6228,8 @@ union cvmx_gmxx_rxx_int_reg
uint64_t reserved_20_63 : 44;
#endif
} cn50xx;
- struct cvmx_gmxx_rxx_int_reg_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63 : 35;
uint64_t hg2cc : 1; /**< HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
@@ -4307,9 +6322,8 @@ union cvmx_gmxx_rxx_int_reg
} cn52xx;
struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
- struct cvmx_gmxx_rxx_int_reg_cn56xxp1
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_27_63 : 37;
uint64_t undat : 1; /**< Unexpected Data
(XAUI Mode only) */
@@ -4382,9 +6396,8 @@ union cvmx_gmxx_rxx_int_reg
uint64_t reserved_27_63 : 37;
#endif
} cn56xxp1;
- struct cvmx_gmxx_rxx_int_reg_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_reg_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */
uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex */
@@ -4433,9 +6446,8 @@ union cvmx_gmxx_rxx_int_reg
#endif
} cn58xx;
struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
- struct cvmx_gmxx_rxx_int_reg_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_int_reg_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63 : 35;
uint64_t hg2cc : 1; /**< HiGig2 received message CRC or Control char error
Set when either CRC8 error detected or when
@@ -4528,8 +6540,13 @@ union cvmx_gmxx_rxx_int_reg
uint64_t hg2cc : 1;
uint64_t reserved_29_63 : 35;
#endif
- } cn63xx;
- struct cvmx_gmxx_rxx_int_reg_cn63xx cn63xxp1;
+ } cn61xx;
+ struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx;
+ struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1;
+ struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx;
+ struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx;
+ struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1;
+ struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx;
};
typedef union cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_int_reg_t;
@@ -4551,12 +6568,10 @@ typedef union cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_int_reg_t;
*
* In XAUI mode prt0 is used for checking.
*/
-union cvmx_gmxx_rxx_jabber
-{
+union cvmx_gmxx_rxx_jabber {
uint64_t u64;
- struct cvmx_gmxx_rxx_jabber_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t cnt : 16; /**< Byte count for jabber check
Failing packets set the JABBER interrupt and are
@@ -4578,8 +6593,13 @@ union cvmx_gmxx_rxx_jabber
struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
struct cvmx_gmxx_rxx_jabber_s cn58xx;
struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
+ struct cvmx_gmxx_rxx_jabber_s cn61xx;
struct cvmx_gmxx_rxx_jabber_s cn63xx;
struct cvmx_gmxx_rxx_jabber_s cn63xxp1;
+ struct cvmx_gmxx_rxx_jabber_s cn66xx;
+ struct cvmx_gmxx_rxx_jabber_s cn68xx;
+ struct cvmx_gmxx_rxx_jabber_s cn68xxp1;
+ struct cvmx_gmxx_rxx_jabber_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_jabber_t;
@@ -4589,12 +6609,10 @@ typedef union cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_jabber_t;
* GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
*
*/
-union cvmx_gmxx_rxx_pause_drop_time
-{
+union cvmx_gmxx_rxx_pause_drop_time {
uint64_t u64;
- struct cvmx_gmxx_rxx_pause_drop_time_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_pause_drop_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t status : 16; /**< Time extracted from the dropped PAUSE packet */
#else
@@ -4609,8 +6627,13 @@ union cvmx_gmxx_rxx_pause_drop_time
struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx;
struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx;
struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1;
+ struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_pause_drop_time cvmx_gmxx_rxx_pause_drop_time_t;
@@ -4625,12 +6648,10 @@ typedef union cvmx_gmxx_rxx_pause_drop_time cvmx_gmxx_rxx_pause_drop_time_t;
* and supports the optional in-band status (see section 3.4.1 of the RGMII
* specification, version 1.3 for more information).
*/
-union cvmx_gmxx_rxx_rx_inbnd
-{
+union cvmx_gmxx_rxx_rx_inbnd {
uint64_t u64;
- struct cvmx_gmxx_rxx_rx_inbnd_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_rx_inbnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t duplex : 1; /**< RGMII Inbound LinkDuplex
0=half-duplex
@@ -4666,12 +6687,10 @@ typedef union cvmx_gmxx_rxx_rx_inbnd cvmx_gmxx_rxx_rx_inbnd_t;
* GMX_RX_STATS_CTL = RX Stats Control register
*
*/
-union cvmx_gmxx_rxx_stats_ctl
-{
+union cvmx_gmxx_rxx_stats_ctl {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t rd_clr : 1; /**< RX Stats registers will clear on reads */
#else
@@ -4690,8 +6709,13 @@ union cvmx_gmxx_rxx_stats_ctl
struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn61xx;
struct cvmx_gmxx_rxx_stats_ctl_s cn63xx;
struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_ctl_t;
@@ -4702,12 +6726,10 @@ typedef union cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_ctl_t;
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_octs
-{
+union cvmx_gmxx_rxx_stats_octs {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_octs_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_octs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t cnt : 48; /**< Octet count of received good packets */
#else
@@ -4726,8 +6748,13 @@ union cvmx_gmxx_rxx_stats_octs
struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_s cn61xx;
struct cvmx_gmxx_rxx_stats_octs_s cn63xx;
struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_octs cvmx_gmxx_rxx_stats_octs_t;
@@ -4738,12 +6765,10 @@ typedef union cvmx_gmxx_rxx_stats_octs cvmx_gmxx_rxx_stats_octs_t;
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_octs_ctl
-{
+union cvmx_gmxx_rxx_stats_octs_ctl {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t cnt : 48; /**< Octet count of received pause packets */
#else
@@ -4762,8 +6787,13 @@ union cvmx_gmxx_rxx_stats_octs_ctl
struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx;
struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx;
struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_ctl_t;
@@ -4774,12 +6804,10 @@ typedef union cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_ctl_t;
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_octs_dmac
-{
+union cvmx_gmxx_rxx_stats_octs_dmac {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t cnt : 48; /**< Octet count of filtered dmac packets */
#else
@@ -4798,8 +6826,13 @@ union cvmx_gmxx_rxx_stats_octs_dmac
struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx;
struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx;
struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_dmac_t;
@@ -4810,12 +6843,10 @@ typedef union cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_dmac_t;
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_octs_drp
-{
+union cvmx_gmxx_rxx_stats_octs_drp {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_octs_drp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_octs_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t cnt : 48; /**< Octet count of dropped packets */
#else
@@ -4834,8 +6865,13 @@ union cvmx_gmxx_rxx_stats_octs_drp
struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx;
struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx;
struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_octs_drp cvmx_gmxx_rxx_stats_octs_drp_t;
@@ -4852,12 +6888,10 @@ typedef union cvmx_gmxx_rxx_stats_octs_drp cvmx_gmxx_rxx_stats_octs_drp_t;
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_pkts
-{
+union cvmx_gmxx_rxx_stats_pkts {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_pkts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of received good packets */
#else
@@ -4876,8 +6910,13 @@ union cvmx_gmxx_rxx_stats_pkts
struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn61xx;
struct cvmx_gmxx_rxx_stats_pkts_s cn63xx;
struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_t;
@@ -4893,12 +6932,10 @@ typedef union cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_t;
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_pkts_bad
-{
+union cvmx_gmxx_rxx_stats_pkts_bad {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of bad packets */
#else
@@ -4917,8 +6954,13 @@ union cvmx_gmxx_rxx_stats_pkts_bad
struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx;
struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx;
struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_bad_t;
@@ -4939,12 +6981,10 @@ typedef union cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_bad_t;
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_pkts_ctl
-{
+union cvmx_gmxx_rxx_stats_pkts_ctl {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of received pause packets */
#else
@@ -4963,8 +7003,13 @@ union cvmx_gmxx_rxx_stats_pkts_ctl
struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx;
struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx;
struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_pkts_ctl cvmx_gmxx_rxx_stats_pkts_ctl_t;
@@ -4986,12 +7031,10 @@ typedef union cvmx_gmxx_rxx_stats_pkts_ctl cvmx_gmxx_rxx_stats_pkts_ctl_t;
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_pkts_dmac
-{
+union cvmx_gmxx_rxx_stats_pkts_dmac {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of filtered dmac packets */
#else
@@ -5010,8 +7053,13 @@ union cvmx_gmxx_rxx_stats_pkts_dmac
struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx;
struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx;
struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_dmac_t;
@@ -5020,21 +7068,21 @@ typedef union cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_dmac_t;
*
* GMX_RX_STATS_PKTS_DRP
*
- * Count of all packets received that were dropped due to a full receive
- * FIFO. This counts good and bad packets received - all packets dropped by
- * the FIFO. It does not count packets dropped by the dmac or pause packet
+ * Count of all packets received that were dropped due to a full receive FIFO.
+ * This counts both partial packets in which there was enough space in the RX
+ * FIFO to begin to buffer and the packet and total drops in which no packet was
+ * sent to PKI. This counts good and bad packets received - all packets dropped
+ * by the FIFO. It does not count packets dropped by the dmac or pause packet
* filters.
*
* Notes:
* - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_rxx_stats_pkts_drp
-{
+union cvmx_gmxx_rxx_stats_pkts_drp {
uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of dropped packets */
#else
@@ -5053,8 +7101,13 @@ union cvmx_gmxx_rxx_stats_pkts_drp
struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx;
struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx;
struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1;
+ struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_stats_pkts_drp_t;
@@ -5089,12 +7142,10 @@ typedef union cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_stats_pkts_drp_t;
*
* (7) If LEN != 0, then GMX_RX_FRM_CHK[LENERR] will be disabled and GMX_RX_INT_REG[LENERR] will be zero
*/
-union cvmx_gmxx_rxx_udd_skp
-{
+union cvmx_gmxx_rxx_udd_skp {
uint64_t u64;
- struct cvmx_gmxx_rxx_udd_skp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rxx_udd_skp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t fcssel : 1; /**< Include the skip bytes in the FCS calculation
0 = all skip bytes are included in FCS
@@ -5127,8 +7178,13 @@ union cvmx_gmxx_rxx_udd_skp
struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
+ struct cvmx_gmxx_rxx_udd_skp_s cn61xx;
struct cvmx_gmxx_rxx_udd_skp_s cn63xx;
struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1;
+ struct cvmx_gmxx_rxx_udd_skp_s cn66xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn68xx;
+ struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1;
+ struct cvmx_gmxx_rxx_udd_skp_s cnf71xx;
};
typedef union cvmx_gmxx_rxx_udd_skp cvmx_gmxx_rxx_udd_skp_t;
@@ -5145,12 +7201,10 @@ typedef union cvmx_gmxx_rxx_udd_skp cvmx_gmxx_rxx_udd_skp_t;
*
* In XAUI mode prt0 is used for checking.
*/
-union cvmx_gmxx_rx_bp_dropx
-{
+union cvmx_gmxx_rx_bp_dropx {
uint64_t u64;
- struct cvmx_gmxx_rx_bp_dropx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_bp_dropx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t mark : 6; /**< Number of 8B ticks to reserve in the RX FIFO.
When the FIFO exceeds this count, packets will
@@ -5174,8 +7228,13 @@ union cvmx_gmxx_rx_bp_dropx
struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
+ struct cvmx_gmxx_rx_bp_dropx_s cn61xx;
struct cvmx_gmxx_rx_bp_dropx_s cn63xx;
struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1;
+ struct cvmx_gmxx_rx_bp_dropx_s cn66xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn68xx;
+ struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1;
+ struct cvmx_gmxx_rx_bp_dropx_s cnf71xx;
};
typedef union cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_dropx_t;
@@ -5189,12 +7248,10 @@ typedef union cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_dropx_t;
* In XAUI mode, prt0 is used for checking.
*
*/
-union cvmx_gmxx_rx_bp_offx
-{
+union cvmx_gmxx_rx_bp_offx {
uint64_t u64;
- struct cvmx_gmxx_rx_bp_offx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_bp_offx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t mark : 6; /**< Water mark (8B ticks) to deassert backpressure */
#else
@@ -5213,8 +7270,13 @@ union cvmx_gmxx_rx_bp_offx
struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
struct cvmx_gmxx_rx_bp_offx_s cn58xx;
struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
+ struct cvmx_gmxx_rx_bp_offx_s cn61xx;
struct cvmx_gmxx_rx_bp_offx_s cn63xx;
struct cvmx_gmxx_rx_bp_offx_s cn63xxp1;
+ struct cvmx_gmxx_rx_bp_offx_s cn66xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn68xx;
+ struct cvmx_gmxx_rx_bp_offx_s cn68xxp1;
+ struct cvmx_gmxx_rx_bp_offx_s cnf71xx;
};
typedef union cvmx_gmxx_rx_bp_offx cvmx_gmxx_rx_bp_offx_t;
@@ -5228,14 +7290,12 @@ typedef union cvmx_gmxx_rx_bp_offx cvmx_gmxx_rx_bp_offx_t;
* In XAUI mode, prt0 is used for checking.
*
*/
-union cvmx_gmxx_rx_bp_onx
-{
+union cvmx_gmxx_rx_bp_onx {
uint64_t u64;
- struct cvmx_gmxx_rx_bp_onx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_9_63 : 55;
- uint64_t mark : 9; /**< Hiwater mark (8B ticks) for backpressure.
+ struct cvmx_gmxx_rx_bp_onx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_11_63 : 53;
+ uint64_t mark : 11; /**< Hiwater mark (8B ticks) for backpressure.
Each register is for an individual port. In XAUI
mode, prt0 is used for the unified RX FIFO
GMX_RX_BP_ON must satisfy
@@ -5243,23 +7303,45 @@ union cvmx_gmxx_rx_bp_onx
A value of zero will immediately assert back
pressure. */
#else
+ uint64_t mark : 11;
+ uint64_t reserved_11_63 : 53;
+#endif
+ } s;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_9_63 : 55;
+ uint64_t mark : 9; /**< Hiwater mark (8B ticks) for backpressure.
+ In RGMII mode, the backpressure is given per
+ port. In Spi4 mode, the backpressure is for the
+ entire interface. GMX_RX_BP_ON must satisfy
+ BP_OFF <= BP_ON < (FIFO_SIZE - BP_DROP)
+ The reset value is half the FIFO.
+ Reset value RGMII mode = 0x40 (512bytes)
+ Reset value Spi4 mode = 0x100 (2048bytes)
+ A value of zero will immediately assert back
+ pressure. */
+#else
uint64_t mark : 9;
uint64_t reserved_9_63 : 55;
#endif
- } s;
- struct cvmx_gmxx_rx_bp_onx_s cn30xx;
- struct cvmx_gmxx_rx_bp_onx_s cn31xx;
- struct cvmx_gmxx_rx_bp_onx_s cn38xx;
- struct cvmx_gmxx_rx_bp_onx_s cn38xxp2;
- struct cvmx_gmxx_rx_bp_onx_s cn50xx;
- struct cvmx_gmxx_rx_bp_onx_s cn52xx;
- struct cvmx_gmxx_rx_bp_onx_s cn52xxp1;
- struct cvmx_gmxx_rx_bp_onx_s cn56xx;
- struct cvmx_gmxx_rx_bp_onx_s cn56xxp1;
- struct cvmx_gmxx_rx_bp_onx_s cn58xx;
- struct cvmx_gmxx_rx_bp_onx_s cn58xxp1;
- struct cvmx_gmxx_rx_bp_onx_s cn63xx;
- struct cvmx_gmxx_rx_bp_onx_s cn63xxp1;
+ } cn30xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn68xx;
+ struct cvmx_gmxx_rx_bp_onx_s cn68xxp1;
+ struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx;
};
typedef union cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_bp_onx_t;
@@ -5269,12 +7351,10 @@ typedef union cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_bp_onx_t;
* ** HG2 message CSRs
*
*/
-union cvmx_gmxx_rx_hg2_status
-{
+union cvmx_gmxx_rx_hg2_status {
uint64_t u64;
- struct cvmx_gmxx_rx_hg2_status_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_hg2_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t phtim2go : 16; /**< Physical time to go for removal of physical link
pause. Initial value from received HiGig2 msg pkt
@@ -5298,8 +7378,13 @@ union cvmx_gmxx_rx_hg2_status
struct cvmx_gmxx_rx_hg2_status_s cn52xx;
struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
struct cvmx_gmxx_rx_hg2_status_s cn56xx;
+ struct cvmx_gmxx_rx_hg2_status_s cn61xx;
struct cvmx_gmxx_rx_hg2_status_s cn63xx;
struct cvmx_gmxx_rx_hg2_status_s cn63xxp1;
+ struct cvmx_gmxx_rx_hg2_status_s cn66xx;
+ struct cvmx_gmxx_rx_hg2_status_s cn68xx;
+ struct cvmx_gmxx_rx_hg2_status_s cn68xxp1;
+ struct cvmx_gmxx_rx_hg2_status_s cnf71xx;
};
typedef union cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_hg2_status_t;
@@ -5319,12 +7404,10 @@ typedef union cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_hg2_status_t;
* (2) The mapped pass through output port cannot be the destination port for
* any Octane core traffic.
*/
-union cvmx_gmxx_rx_pass_en
-{
+union cvmx_gmxx_rx_pass_en {
uint64_t u64;
- struct cvmx_gmxx_rx_pass_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_pass_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t en : 16; /**< Which ports to configure in pass through mode */
#else
@@ -5345,12 +7428,10 @@ typedef union cvmx_gmxx_rx_pass_en cvmx_gmxx_rx_pass_en_t;
* GMX_RX_PASS_MAP = Packet pass through port map
*
*/
-union cvmx_gmxx_rx_pass_mapx
-{
+union cvmx_gmxx_rx_pass_mapx {
uint64_t u64;
- struct cvmx_gmxx_rx_pass_mapx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_pass_mapx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t dprt : 4; /**< Destination port to map Spi pass through traffic */
#else
@@ -5375,12 +7456,10 @@ typedef union cvmx_gmxx_rx_pass_mapx cvmx_gmxx_rx_pass_mapx_t;
* In XAUI mode, only the lsb (corresponding to port0) of DROP and COMMIT are used.
*
*/
-union cvmx_gmxx_rx_prt_info
-{
+union cvmx_gmxx_rx_prt_info {
uint64_t u64;
- struct cvmx_gmxx_rx_prt_info_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_prt_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t drop : 16; /**< Per port indication that data was dropped */
uint64_t commit : 16; /**< Per port indication that SOP was accepted */
@@ -5390,9 +7469,8 @@ union cvmx_gmxx_rx_prt_info
uint64_t reserved_32_63 : 32;
#endif
} s;
- struct cvmx_gmxx_rx_prt_info_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_prt_info_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63 : 45;
uint64_t drop : 3; /**< Per port indication that data was dropped */
uint64_t reserved_3_15 : 13;
@@ -5407,9 +7485,8 @@ union cvmx_gmxx_rx_prt_info
struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
struct cvmx_gmxx_rx_prt_info_s cn38xx;
struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
- struct cvmx_gmxx_rx_prt_info_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_prt_info_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t drop : 4; /**< Per port indication that data was dropped */
uint64_t reserved_4_15 : 12;
@@ -5426,8 +7503,25 @@ union cvmx_gmxx_rx_prt_info
struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
struct cvmx_gmxx_rx_prt_info_s cn58xx;
struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
+ struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx;
struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx;
struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1;
+ struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx;
+ struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx;
+ struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1;
+ struct cvmx_gmxx_rx_prt_info_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_18_63 : 46;
+ uint64_t drop : 2; /**< Per port indication that data was dropped */
+ uint64_t reserved_2_15 : 14;
+ uint64_t commit : 2; /**< Per port indication that SOP was accepted */
+#else
+ uint64_t commit : 2;
+ uint64_t reserved_2_15 : 14;
+ uint64_t drop : 2;
+ uint64_t reserved_18_63 : 46;
+#endif
+ } cnf71xx;
};
typedef union cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prt_info_t;
@@ -5441,12 +7535,10 @@ typedef union cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prt_info_t;
* GMX_RX_PRTS[PRTS] must be set to '1' in XAUI mode.
*
*/
-union cvmx_gmxx_rx_prts
-{
+union cvmx_gmxx_rx_prts {
uint64_t u64;
- struct cvmx_gmxx_rx_prts_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_prts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63 : 61;
uint64_t prts : 3; /**< In SGMII/1000Base-X mode, the RX buffer can be
carved into several logical buffers depending on
@@ -5470,8 +7562,13 @@ union cvmx_gmxx_rx_prts
struct cvmx_gmxx_rx_prts_s cn56xxp1;
struct cvmx_gmxx_rx_prts_s cn58xx;
struct cvmx_gmxx_rx_prts_s cn58xxp1;
+ struct cvmx_gmxx_rx_prts_s cn61xx;
struct cvmx_gmxx_rx_prts_s cn63xx;
struct cvmx_gmxx_rx_prts_s cn63xxp1;
+ struct cvmx_gmxx_rx_prts_s cn66xx;
+ struct cvmx_gmxx_rx_prts_s cn68xx;
+ struct cvmx_gmxx_rx_prts_s cn68xxp1;
+ struct cvmx_gmxx_rx_prts_s cnf71xx;
};
typedef union cvmx_gmxx_rx_prts cvmx_gmxx_rx_prts_t;
@@ -5481,12 +7578,10 @@ typedef union cvmx_gmxx_rx_prts cvmx_gmxx_rx_prts_t;
* GMX_RX_TX_STATUS = GMX RX/TX Status
*
*/
-union cvmx_gmxx_rx_tx_status
-{
+union cvmx_gmxx_rx_tx_status {
uint64_t u64;
- struct cvmx_gmxx_rx_tx_status_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63 : 57;
uint64_t tx : 3; /**< Transmit data since last read */
uint64_t reserved_3_3 : 1;
@@ -5507,12 +7602,10 @@ typedef union cvmx_gmxx_rx_tx_status cvmx_gmxx_rx_tx_status_t;
/**
* cvmx_gmx#_rx_xaui_bad_col
*/
-union cvmx_gmxx_rx_xaui_bad_col
-{
+union cvmx_gmxx_rx_xaui_bad_col {
uint64_t u64;
- struct cvmx_gmxx_rx_xaui_bad_col_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_xaui_bad_col_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63 : 24;
uint64_t val : 1; /**< Set when GMX_RX_INT_REG[PCTERR] is set.
(XAUI mode only) */
@@ -5538,20 +7631,23 @@ union cvmx_gmxx_rx_xaui_bad_col
struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx;
struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx;
struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1;
+ struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx;
};
typedef union cvmx_gmxx_rx_xaui_bad_col cvmx_gmxx_rx_xaui_bad_col_t;
/**
* cvmx_gmx#_rx_xaui_ctl
*/
-union cvmx_gmxx_rx_xaui_ctl
-{
+union cvmx_gmxx_rx_xaui_ctl {
uint64_t u64;
- struct cvmx_gmxx_rx_xaui_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_rx_xaui_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t status : 2; /**< Link Status
0=Link OK
@@ -5568,23 +7664,55 @@ union cvmx_gmxx_rx_xaui_ctl
struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
+ struct cvmx_gmxx_rx_xaui_ctl_s cn61xx;
struct cvmx_gmxx_rx_xaui_ctl_s cn63xx;
struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1;
+ struct cvmx_gmxx_rx_xaui_ctl_s cn66xx;
+ struct cvmx_gmxx_rx_xaui_ctl_s cn68xx;
+ struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1;
+ struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_rx_xaui_ctl cvmx_gmxx_rx_xaui_ctl_t;
/**
+ * cvmx_gmx#_rxaui_ctl
+ */
+union cvmx_gmxx_rxaui_ctl {
+ uint64_t u64;
+ struct cvmx_gmxx_rxaui_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_1_63 : 63;
+ uint64_t disparity : 1; /**< Selects which disparity calculation to use when
+ combining or splitting the RXAUI lanes.
+ 0=Interleave lanes before PCS layer
+ As described in the Dune Networks/Broadcom
+ RXAUI v2.1 specification.
+ (obeys 6.25GHz SERDES disparity)
+ 1=Interleave lanes after PCS layer
+ As described in the Marvell RXAUI Interface
+ specification.
+ (does not obey 6.25GHz SERDES disparity)
+ (RXAUI mode only) */
+#else
+ uint64_t disparity : 1;
+ uint64_t reserved_1_63 : 63;
+#endif
+ } s;
+ struct cvmx_gmxx_rxaui_ctl_s cn68xx;
+ struct cvmx_gmxx_rxaui_ctl_s cn68xxp1;
+};
+typedef union cvmx_gmxx_rxaui_ctl cvmx_gmxx_rxaui_ctl_t;
+
+/**
* cvmx_gmx#_smac#
*
* GMX_SMAC = Packet SMAC
*
*/
-union cvmx_gmxx_smacx
-{
+union cvmx_gmxx_smacx {
uint64_t u64;
- struct cvmx_gmxx_smacx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_smacx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t smac : 48; /**< The SMAC field is used for generating and
accepting Control Pause packets */
@@ -5604,8 +7732,13 @@ union cvmx_gmxx_smacx
struct cvmx_gmxx_smacx_s cn56xxp1;
struct cvmx_gmxx_smacx_s cn58xx;
struct cvmx_gmxx_smacx_s cn58xxp1;
+ struct cvmx_gmxx_smacx_s cn61xx;
struct cvmx_gmxx_smacx_s cn63xx;
struct cvmx_gmxx_smacx_s cn63xxp1;
+ struct cvmx_gmxx_smacx_s cn66xx;
+ struct cvmx_gmxx_smacx_s cn68xx;
+ struct cvmx_gmxx_smacx_s cn68xxp1;
+ struct cvmx_gmxx_smacx_s cnf71xx;
};
typedef union cvmx_gmxx_smacx cvmx_gmxx_smacx_t;
@@ -5615,14 +7748,13 @@ typedef union cvmx_gmxx_smacx cvmx_gmxx_smacx_t;
* GMX_SOFT_BIST = Software BIST Control
*
*/
-union cvmx_gmxx_soft_bist
-{
+union cvmx_gmxx_soft_bist {
uint64_t u64;
- struct cvmx_gmxx_soft_bist_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_soft_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
- uint64_t start_bist : 1; /**< Run BIST on all memories in the XAUI CLK domain */
+ uint64_t start_bist : 1; /**< Run BIST on all memories in the XAUI/RXAUI
+ CLK domain */
uint64_t clear_bist : 1; /**< Choose between full BIST and CLEAR bist
0=Run full BIST
1=Only run clear BIST */
@@ -5634,6 +7766,9 @@ union cvmx_gmxx_soft_bist
} s;
struct cvmx_gmxx_soft_bist_s cn63xx;
struct cvmx_gmxx_soft_bist_s cn63xxp1;
+ struct cvmx_gmxx_soft_bist_s cn66xx;
+ struct cvmx_gmxx_soft_bist_s cn68xx;
+ struct cvmx_gmxx_soft_bist_s cn68xxp1;
};
typedef union cvmx_gmxx_soft_bist cvmx_gmxx_soft_bist_t;
@@ -5642,15 +7777,34 @@ typedef union cvmx_gmxx_soft_bist cvmx_gmxx_soft_bist_t;
*
* GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
*
+ *
+ * Notes:
+ * It has no relationship with the TX FIFO per se. The TX engine sends packets
+ * from PKO and upon completion, sends a command to the TX stats block for an
+ * update based on the packet size. The stats operation can take a few cycles -
+ * normally not enough to be visible considering the 64B min packet size that is
+ * ethernet convention.
+ *
+ * In the rare case in which SW attempted to schedule really, really, small packets
+ * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in
+ * real time and can back up the TX engine.
+ *
+ * This counter is the number of cycles in which the TX engine was stalled. In
+ * normal operation, it should always be zeros.
*/
-union cvmx_gmxx_stat_bp
-{
+union cvmx_gmxx_stat_bp {
uint64_t u64;
- struct cvmx_gmxx_stat_bp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_stat_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63 : 47;
- uint64_t bp : 1; /**< Current BP state */
+ uint64_t bp : 1; /**< Current TX stats BP state
+ When the TX stats machine cannot update the stats
+ registers quickly enough, the machine has the
+ ability to BP TX datapath. This is a rare event
+ and will not occur in normal operation.
+ 0 = no backpressure is applied
+ 1 = backpressure is applied to TX datapath to
+ allow stat update operations to complete */
uint64_t cnt : 16; /**< Number of cycles that BP has been asserted
Saturating counter */
#else
@@ -5670,23 +7824,50 @@ union cvmx_gmxx_stat_bp
struct cvmx_gmxx_stat_bp_s cn56xxp1;
struct cvmx_gmxx_stat_bp_s cn58xx;
struct cvmx_gmxx_stat_bp_s cn58xxp1;
+ struct cvmx_gmxx_stat_bp_s cn61xx;
struct cvmx_gmxx_stat_bp_s cn63xx;
struct cvmx_gmxx_stat_bp_s cn63xxp1;
+ struct cvmx_gmxx_stat_bp_s cn66xx;
+ struct cvmx_gmxx_stat_bp_s cn68xx;
+ struct cvmx_gmxx_stat_bp_s cn68xxp1;
+ struct cvmx_gmxx_stat_bp_s cnf71xx;
};
typedef union cvmx_gmxx_stat_bp cvmx_gmxx_stat_bp_t;
/**
+ * cvmx_gmx#_tb_reg
+ *
+ * DON'T PUT IN HRM*
+ *
+ */
+union cvmx_gmxx_tb_reg {
+ uint64_t u64;
+ struct cvmx_gmxx_tb_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_1_63 : 63;
+ uint64_t wr_magic : 1; /**< Enter stats model magic mode */
+#else
+ uint64_t wr_magic : 1;
+ uint64_t reserved_1_63 : 63;
+#endif
+ } s;
+ struct cvmx_gmxx_tb_reg_s cn61xx;
+ struct cvmx_gmxx_tb_reg_s cn66xx;
+ struct cvmx_gmxx_tb_reg_s cn68xx;
+ struct cvmx_gmxx_tb_reg_s cnf71xx;
+};
+typedef union cvmx_gmxx_tb_reg cvmx_gmxx_tb_reg_t;
+
+/**
* cvmx_gmx#_tx#_append
*
* GMX_TX_APPEND = Packet TX Append Control
*
*/
-union cvmx_gmxx_txx_append
-{
+union cvmx_gmxx_txx_append {
uint64_t u64;
- struct cvmx_gmxx_txx_append_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_append_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t force_fcs : 1; /**< Append the Ethernet FCS on each pause packet
when FCS is clear. Pause packets are normally
@@ -5716,8 +7897,13 @@ union cvmx_gmxx_txx_append
struct cvmx_gmxx_txx_append_s cn56xxp1;
struct cvmx_gmxx_txx_append_s cn58xx;
struct cvmx_gmxx_txx_append_s cn58xxp1;
+ struct cvmx_gmxx_txx_append_s cn61xx;
struct cvmx_gmxx_txx_append_s cn63xx;
struct cvmx_gmxx_txx_append_s cn63xxp1;
+ struct cvmx_gmxx_txx_append_s cn66xx;
+ struct cvmx_gmxx_txx_append_s cn68xx;
+ struct cvmx_gmxx_txx_append_s cn68xxp1;
+ struct cvmx_gmxx_txx_append_s cnf71xx;
};
typedef union cvmx_gmxx_txx_append cvmx_gmxx_txx_append_t;
@@ -5727,12 +7913,10 @@ typedef union cvmx_gmxx_txx_append cvmx_gmxx_txx_append_t;
* GMX_TX_BURST = Packet TX Burst Counter
*
*/
-union cvmx_gmxx_txx_burst
-{
+union cvmx_gmxx_txx_burst {
uint64_t u64;
- struct cvmx_gmxx_txx_burst_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_burst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t burst : 16; /**< Burst (refer to 802.3 to set correctly)
Only valid for 1000Mbs half-duplex operation
@@ -5755,20 +7939,23 @@ union cvmx_gmxx_txx_burst
struct cvmx_gmxx_txx_burst_s cn56xxp1;
struct cvmx_gmxx_txx_burst_s cn58xx;
struct cvmx_gmxx_txx_burst_s cn58xxp1;
+ struct cvmx_gmxx_txx_burst_s cn61xx;
struct cvmx_gmxx_txx_burst_s cn63xx;
struct cvmx_gmxx_txx_burst_s cn63xxp1;
+ struct cvmx_gmxx_txx_burst_s cn66xx;
+ struct cvmx_gmxx_txx_burst_s cn68xx;
+ struct cvmx_gmxx_txx_burst_s cn68xxp1;
+ struct cvmx_gmxx_txx_burst_s cnf71xx;
};
typedef union cvmx_gmxx_txx_burst cvmx_gmxx_txx_burst_t;
/**
* cvmx_gmx#_tx#_cbfc_xoff
*/
-union cvmx_gmxx_txx_cbfc_xoff
-{
+union cvmx_gmxx_txx_cbfc_xoff {
uint64_t u64;
- struct cvmx_gmxx_txx_cbfc_xoff_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_cbfc_xoff_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t xoff : 16; /**< Which ports to backpressure
Do not write in HiGig2 mode i.e. when
@@ -5781,20 +7968,23 @@ union cvmx_gmxx_txx_cbfc_xoff
} s;
struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
+ struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx;
struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx;
struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1;
+ struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx;
+ struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx;
+ struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1;
+ struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx;
};
typedef union cvmx_gmxx_txx_cbfc_xoff cvmx_gmxx_txx_cbfc_xoff_t;
/**
* cvmx_gmx#_tx#_cbfc_xon
*/
-union cvmx_gmxx_txx_cbfc_xon
-{
+union cvmx_gmxx_txx_cbfc_xon {
uint64_t u64;
- struct cvmx_gmxx_txx_cbfc_xon_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_cbfc_xon_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t xon : 16; /**< Which ports to stop backpressure
Do not write in HiGig2 mode i.e. when
@@ -5807,8 +7997,13 @@ union cvmx_gmxx_txx_cbfc_xon
} s;
struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
+ struct cvmx_gmxx_txx_cbfc_xon_s cn61xx;
struct cvmx_gmxx_txx_cbfc_xon_s cn63xx;
struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1;
+ struct cvmx_gmxx_txx_cbfc_xon_s cn66xx;
+ struct cvmx_gmxx_txx_cbfc_xon_s cn68xx;
+ struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1;
+ struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx;
};
typedef union cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_cbfc_xon_t;
@@ -5832,12 +8027,10 @@ typedef union cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_cbfc_xon_t;
* CLK_CNT == 5 ==> 25.0MHz TXC clock period (8ns* 5)
* CLK_CNT == 50 ==> 2.5MHz TXC clock period (8ns*50)
*/
-union cvmx_gmxx_txx_clk
-{
+union cvmx_gmxx_txx_clk {
uint64_t u64;
- struct cvmx_gmxx_txx_clk_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_clk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t clk_cnt : 6; /**< Controls the RGMII TXC frequency
When PLL is used, TXC(phase) =
@@ -5867,12 +8060,10 @@ typedef union cvmx_gmxx_txx_clk cvmx_gmxx_txx_clk_t;
* GMX_TX_CTL = TX Control register
*
*/
-union cvmx_gmxx_txx_ctl
-{
+union cvmx_gmxx_txx_ctl {
uint64_t u64;
- struct cvmx_gmxx_txx_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t xsdef_en : 1; /**< Enables the excessive deferral check for stats
and interrupts
@@ -5897,8 +8088,13 @@ union cvmx_gmxx_txx_ctl
struct cvmx_gmxx_txx_ctl_s cn56xxp1;
struct cvmx_gmxx_txx_ctl_s cn58xx;
struct cvmx_gmxx_txx_ctl_s cn58xxp1;
+ struct cvmx_gmxx_txx_ctl_s cn61xx;
struct cvmx_gmxx_txx_ctl_s cn63xx;
struct cvmx_gmxx_txx_ctl_s cn63xxp1;
+ struct cvmx_gmxx_txx_ctl_s cn66xx;
+ struct cvmx_gmxx_txx_ctl_s cn68xx;
+ struct cvmx_gmxx_txx_ctl_s cn68xxp1;
+ struct cvmx_gmxx_txx_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_txx_ctl cvmx_gmxx_txx_ctl_t;
@@ -5908,12 +8104,10 @@ typedef union cvmx_gmxx_txx_ctl cvmx_gmxx_txx_ctl_t;
* GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)
*
*/
-union cvmx_gmxx_txx_min_pkt
-{
+union cvmx_gmxx_txx_min_pkt {
uint64_t u64;
- struct cvmx_gmxx_txx_min_pkt_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_min_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t min_size : 8; /**< Min frame in bytes before the FCS is applied
Padding is only appened when GMX_TX_APPEND[PAD]
@@ -5942,8 +8136,13 @@ union cvmx_gmxx_txx_min_pkt
struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
struct cvmx_gmxx_txx_min_pkt_s cn58xx;
struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
+ struct cvmx_gmxx_txx_min_pkt_s cn61xx;
struct cvmx_gmxx_txx_min_pkt_s cn63xx;
struct cvmx_gmxx_txx_min_pkt_s cn63xxp1;
+ struct cvmx_gmxx_txx_min_pkt_s cn66xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn68xx;
+ struct cvmx_gmxx_txx_min_pkt_s cn68xxp1;
+ struct cvmx_gmxx_txx_min_pkt_s cnf71xx;
};
typedef union cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_min_pkt_t;
@@ -5972,12 +8171,10 @@ typedef union cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_min_pkt_t;
* (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
* of the PAUSE packet (normally 64B).
*/
-union cvmx_gmxx_txx_pause_pkt_interval
-{
+union cvmx_gmxx_txx_pause_pkt_interval {
uint64_t u64;
- struct cvmx_gmxx_txx_pause_pkt_interval_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_pause_pkt_interval_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t interval : 16; /**< Arbitrate for a 802.3 pause packet, HiGig2 message,
or CBFC pause packet every (INTERVAL*512)
@@ -6001,8 +8198,13 @@ union cvmx_gmxx_txx_pause_pkt_interval
struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx;
struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx;
struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx;
};
typedef union cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_interval_t;
@@ -6031,12 +8233,10 @@ typedef union cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_interval_
* (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
* of the PAUSE packet (normally 64B).
*/
-union cvmx_gmxx_txx_pause_pkt_time
-{
+union cvmx_gmxx_txx_pause_pkt_time {
uint64_t u64;
- struct cvmx_gmxx_txx_pause_pkt_time_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_pause_pkt_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t time : 16; /**< The pause_time field placed in outbnd 802.3 pause
packets, HiGig2 messages, or CBFC pause packets.
@@ -6058,8 +8258,13 @@ union cvmx_gmxx_txx_pause_pkt_time
struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx;
struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx;
struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1;
+ struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx;
};
typedef union cvmx_gmxx_txx_pause_pkt_time cvmx_gmxx_txx_pause_pkt_time_t;
@@ -6069,12 +8274,10 @@ typedef union cvmx_gmxx_txx_pause_pkt_time cvmx_gmxx_txx_pause_pkt_time_t;
* GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure
*
*/
-union cvmx_gmxx_txx_pause_togo
-{
+union cvmx_gmxx_txx_pause_togo {
uint64_t u64;
- struct cvmx_gmxx_txx_pause_togo_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_pause_togo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t msg_time : 16; /**< Amount of time remaining to backpressure
From the higig2 physical message pause timer
@@ -6087,9 +8290,8 @@ union cvmx_gmxx_txx_pause_togo
uint64_t reserved_32_63 : 32;
#endif
} s;
- struct cvmx_gmxx_txx_pause_togo_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_pause_togo_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t time : 16; /**< Amount of time remaining to backpressure */
#else
@@ -6107,8 +8309,13 @@ union cvmx_gmxx_txx_pause_togo
struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
+ struct cvmx_gmxx_txx_pause_togo_s cn61xx;
struct cvmx_gmxx_txx_pause_togo_s cn63xx;
struct cvmx_gmxx_txx_pause_togo_s cn63xxp1;
+ struct cvmx_gmxx_txx_pause_togo_s cn66xx;
+ struct cvmx_gmxx_txx_pause_togo_s cn68xx;
+ struct cvmx_gmxx_txx_pause_togo_s cn68xxp1;
+ struct cvmx_gmxx_txx_pause_togo_s cnf71xx;
};
typedef union cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_togo_t;
@@ -6118,12 +8325,10 @@ typedef union cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_togo_t;
* GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure
*
*/
-union cvmx_gmxx_txx_pause_zero
-{
+union cvmx_gmxx_txx_pause_zero {
uint64_t u64;
- struct cvmx_gmxx_txx_pause_zero_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_pause_zero_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t send : 1; /**< When backpressure condition clear, send PAUSE
packet with pause_time of zero to enable the
@@ -6144,27 +8349,93 @@ union cvmx_gmxx_txx_pause_zero
struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
struct cvmx_gmxx_txx_pause_zero_s cn58xx;
struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
+ struct cvmx_gmxx_txx_pause_zero_s cn61xx;
struct cvmx_gmxx_txx_pause_zero_s cn63xx;
struct cvmx_gmxx_txx_pause_zero_s cn63xxp1;
+ struct cvmx_gmxx_txx_pause_zero_s cn66xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn68xx;
+ struct cvmx_gmxx_txx_pause_zero_s cn68xxp1;
+ struct cvmx_gmxx_txx_pause_zero_s cnf71xx;
};
typedef union cvmx_gmxx_txx_pause_zero cvmx_gmxx_txx_pause_zero_t;
/**
+ * cvmx_gmx#_tx#_pipe
+ */
+union cvmx_gmxx_txx_pipe {
+ uint64_t u64;
+ struct cvmx_gmxx_txx_pipe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_33_63 : 31;
+ uint64_t ign_bp : 1; /**< When set, GMX will not throttle the TX machines
+ if the PIPE return FIFO fills up.
+ IGN_BP should be clear in normal operation. */
+ uint64_t reserved_21_31 : 11;
+ uint64_t nump : 5; /**< Number of pipes this port|channel supports.
+ In SGMII mode, each port binds to one pipe.
+ In XAUI/RXAUI mode, the port can bind upto 16
+ consecutive pipes.
+ SGMII mode, NUMP = 0 or 1.
+ XAUI/RXAUI mode, NUMP = 0 or 1-16.
+ 0 = Disabled */
+ uint64_t reserved_7_15 : 9;
+ uint64_t base : 7; /**< When NUMP is non-zero, indicates the base pipe
+ number this port|channel will accept.
+ This port will accept pko packets from pipes in
+ the range of:
+ BASE .. (BASE+(NUMP-1))
+ BASE and NUMP must be constrained such that
+ 1) BASE+(NUMP-1) < 127
+ 2) Each used PKO pipe must map to exactly
+ one port|channel
+ 3) The pipe ranges must be consistent with
+ the PKO configuration. */
+#else
+ uint64_t base : 7;
+ uint64_t reserved_7_15 : 9;
+ uint64_t nump : 5;
+ uint64_t reserved_21_31 : 11;
+ uint64_t ign_bp : 1;
+ uint64_t reserved_33_63 : 31;
+#endif
+ } s;
+ struct cvmx_gmxx_txx_pipe_s cn68xx;
+ struct cvmx_gmxx_txx_pipe_s cn68xxp1;
+};
+typedef union cvmx_gmxx_txx_pipe cvmx_gmxx_txx_pipe_t;
+
+/**
* cvmx_gmx#_tx#_sgmii_ctl
*/
-union cvmx_gmxx_txx_sgmii_ctl
-{
+union cvmx_gmxx_txx_sgmii_ctl {
uint64_t u64;
- struct cvmx_gmxx_txx_sgmii_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_sgmii_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t align : 1; /**< Align the transmission to even cycles
+
+ Recommended value is:
+ ALIGN = !GMX_TX_APPEND[PREAMBLE]
+
+ (See the Transmit Conversion to Code groups
+ section in the SGMII Interface chapter of the
+ HRM for a complete discussion)
+
0 = Data can be sent on any cycle
- Possible to for the TX PCS machine to drop
- first byte of preamble
- 1 = Data will only be sent on even cycles
- There will be no loss of data
+ In this mode, the interface will function at
+ maximum bandwidth. It is possible to for the
+ TX PCS machine to drop first byte of the TX
+ frame. When GMX_TX_APPEND[PREAMBLE] is set,
+ the first byte will be a preamble byte which
+ can be dropped to compensate for an extended
+ IPG.
+
+ 1 = Data will only be sent on even cycles.
+ In this mode, there can be bandwidth
+ implications when sending odd-byte packets as
+ the IPG can extend an extra cycle.
+ There will be no loss of data.
+
(SGMII/1000Base-X only) */
#else
uint64_t align : 1;
@@ -6175,8 +8446,13 @@ union cvmx_gmxx_txx_sgmii_ctl
struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx;
struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx;
struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1;
+ struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_txx_sgmii_ctl cvmx_gmxx_txx_sgmii_ctl_t;
@@ -6186,12 +8462,10 @@ typedef union cvmx_gmxx_txx_sgmii_ctl cvmx_gmxx_txx_sgmii_ctl_t;
* GMX_TX_SLOT = Packet TX Slottime Counter
*
*/
-union cvmx_gmxx_txx_slot
-{
+union cvmx_gmxx_txx_slot {
uint64_t u64;
- struct cvmx_gmxx_txx_slot_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_slot_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t slot : 10; /**< Slottime (refer to 802.3 to set correctly)
10/100Mbs: 0x40
@@ -6213,8 +8487,13 @@ union cvmx_gmxx_txx_slot
struct cvmx_gmxx_txx_slot_s cn56xxp1;
struct cvmx_gmxx_txx_slot_s cn58xx;
struct cvmx_gmxx_txx_slot_s cn58xxp1;
+ struct cvmx_gmxx_txx_slot_s cn61xx;
struct cvmx_gmxx_txx_slot_s cn63xx;
struct cvmx_gmxx_txx_slot_s cn63xxp1;
+ struct cvmx_gmxx_txx_slot_s cn66xx;
+ struct cvmx_gmxx_txx_slot_s cn68xx;
+ struct cvmx_gmxx_txx_slot_s cn68xxp1;
+ struct cvmx_gmxx_txx_slot_s cnf71xx;
};
typedef union cvmx_gmxx_txx_slot cvmx_gmxx_txx_slot_t;
@@ -6224,12 +8503,10 @@ typedef union cvmx_gmxx_txx_slot cvmx_gmxx_txx_slot_t;
* GMX_TX_SOFT_PAUSE = Packet TX Software Pause
*
*/
-union cvmx_gmxx_txx_soft_pause
-{
+union cvmx_gmxx_txx_soft_pause {
uint64_t u64;
- struct cvmx_gmxx_txx_soft_pause_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_soft_pause_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t time : 16; /**< Back off the TX bus for (TIME*512) bit-times */
#else
@@ -6248,8 +8525,13 @@ union cvmx_gmxx_txx_soft_pause
struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
struct cvmx_gmxx_txx_soft_pause_s cn58xx;
struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
+ struct cvmx_gmxx_txx_soft_pause_s cn61xx;
struct cvmx_gmxx_txx_soft_pause_s cn63xx;
struct cvmx_gmxx_txx_soft_pause_s cn63xxp1;
+ struct cvmx_gmxx_txx_soft_pause_s cn66xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn68xx;
+ struct cvmx_gmxx_txx_soft_pause_s cn68xxp1;
+ struct cvmx_gmxx_txx_soft_pause_s cnf71xx;
};
typedef union cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_soft_pause_t;
@@ -6263,12 +8545,10 @@ typedef union cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_soft_pause_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat0
-{
+union cvmx_gmxx_txx_stat0 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t xsdef : 32; /**< Number of packets dropped (never successfully
sent) due to excessive deferal
(SGMII/1000Base-X half-duplex only) */
@@ -6292,8 +8572,13 @@ union cvmx_gmxx_txx_stat0
struct cvmx_gmxx_txx_stat0_s cn56xxp1;
struct cvmx_gmxx_txx_stat0_s cn58xx;
struct cvmx_gmxx_txx_stat0_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat0_s cn61xx;
struct cvmx_gmxx_txx_stat0_s cn63xx;
struct cvmx_gmxx_txx_stat0_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat0_s cn66xx;
+ struct cvmx_gmxx_txx_stat0_s cn68xx;
+ struct cvmx_gmxx_txx_stat0_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat0_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat0 cvmx_gmxx_txx_stat0_t;
@@ -6307,12 +8592,10 @@ typedef union cvmx_gmxx_txx_stat0 cvmx_gmxx_txx_stat0_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat1
-{
+union cvmx_gmxx_txx_stat1 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t scol : 32; /**< Number of packets sent with a single collision
(SGMII/1000Base-X half-duplex only) */
uint64_t mcol : 32; /**< Number of packets sent with multiple collisions
@@ -6334,8 +8617,13 @@ union cvmx_gmxx_txx_stat1
struct cvmx_gmxx_txx_stat1_s cn56xxp1;
struct cvmx_gmxx_txx_stat1_s cn58xx;
struct cvmx_gmxx_txx_stat1_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat1_s cn61xx;
struct cvmx_gmxx_txx_stat1_s cn63xx;
struct cvmx_gmxx_txx_stat1_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat1_s cn66xx;
+ struct cvmx_gmxx_txx_stat1_s cn68xx;
+ struct cvmx_gmxx_txx_stat1_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat1_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat1_t;
@@ -6352,12 +8640,10 @@ typedef union cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat1_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat2
-{
+union cvmx_gmxx_txx_stat2 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t octs : 48; /**< Number of total octets sent on the interface.
Does not count octets from frames that were
@@ -6378,8 +8664,13 @@ union cvmx_gmxx_txx_stat2
struct cvmx_gmxx_txx_stat2_s cn56xxp1;
struct cvmx_gmxx_txx_stat2_s cn58xx;
struct cvmx_gmxx_txx_stat2_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat2_s cn61xx;
struct cvmx_gmxx_txx_stat2_s cn63xx;
struct cvmx_gmxx_txx_stat2_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat2_s cn66xx;
+ struct cvmx_gmxx_txx_stat2_s cn68xx;
+ struct cvmx_gmxx_txx_stat2_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat2_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat2_t;
@@ -6393,12 +8684,10 @@ typedef union cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat2_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat3
-{
+union cvmx_gmxx_txx_stat3 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat3_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t pkts : 32; /**< Number of total frames sent on the interface.
Does not count frames that were truncated due to
@@ -6419,8 +8708,13 @@ union cvmx_gmxx_txx_stat3
struct cvmx_gmxx_txx_stat3_s cn56xxp1;
struct cvmx_gmxx_txx_stat3_s cn58xx;
struct cvmx_gmxx_txx_stat3_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat3_s cn61xx;
struct cvmx_gmxx_txx_stat3_s cn63xx;
struct cvmx_gmxx_txx_stat3_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat3_s cn66xx;
+ struct cvmx_gmxx_txx_stat3_s cn68xx;
+ struct cvmx_gmxx_txx_stat3_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat3_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat3 cvmx_gmxx_txx_stat3_t;
@@ -6437,12 +8731,10 @@ typedef union cvmx_gmxx_txx_stat3 cvmx_gmxx_txx_stat3_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat4
-{
+union cvmx_gmxx_txx_stat4 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat4_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t hist1 : 32; /**< Number of packets sent with an octet count of 64. */
uint64_t hist0 : 32; /**< Number of packets sent with an octet count
of < 64. */
@@ -6462,8 +8754,13 @@ union cvmx_gmxx_txx_stat4
struct cvmx_gmxx_txx_stat4_s cn56xxp1;
struct cvmx_gmxx_txx_stat4_s cn58xx;
struct cvmx_gmxx_txx_stat4_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat4_s cn61xx;
struct cvmx_gmxx_txx_stat4_s cn63xx;
struct cvmx_gmxx_txx_stat4_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat4_s cn66xx;
+ struct cvmx_gmxx_txx_stat4_s cn68xx;
+ struct cvmx_gmxx_txx_stat4_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat4_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat4_t;
@@ -6480,12 +8777,10 @@ typedef union cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat4_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat5
-{
+union cvmx_gmxx_txx_stat5 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat5_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t hist3 : 32; /**< Number of packets sent with an octet count of
128 - 255. */
uint64_t hist2 : 32; /**< Number of packets sent with an octet count of
@@ -6506,8 +8801,13 @@ union cvmx_gmxx_txx_stat5
struct cvmx_gmxx_txx_stat5_s cn56xxp1;
struct cvmx_gmxx_txx_stat5_s cn58xx;
struct cvmx_gmxx_txx_stat5_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat5_s cn61xx;
struct cvmx_gmxx_txx_stat5_s cn63xx;
struct cvmx_gmxx_txx_stat5_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat5_s cn66xx;
+ struct cvmx_gmxx_txx_stat5_s cn68xx;
+ struct cvmx_gmxx_txx_stat5_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat5_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat5_t;
@@ -6524,12 +8824,10 @@ typedef union cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat5_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat6
-{
+union cvmx_gmxx_txx_stat6 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat6_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t hist5 : 32; /**< Number of packets sent with an octet count of
512 - 1023. */
uint64_t hist4 : 32; /**< Number of packets sent with an octet count of
@@ -6550,8 +8848,13 @@ union cvmx_gmxx_txx_stat6
struct cvmx_gmxx_txx_stat6_s cn56xxp1;
struct cvmx_gmxx_txx_stat6_s cn58xx;
struct cvmx_gmxx_txx_stat6_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat6_s cn61xx;
struct cvmx_gmxx_txx_stat6_s cn63xx;
struct cvmx_gmxx_txx_stat6_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat6_s cn66xx;
+ struct cvmx_gmxx_txx_stat6_s cn68xx;
+ struct cvmx_gmxx_txx_stat6_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat6_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat6 cvmx_gmxx_txx_stat6_t;
@@ -6568,12 +8871,10 @@ typedef union cvmx_gmxx_txx_stat6 cvmx_gmxx_txx_stat6_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat7
-{
+union cvmx_gmxx_txx_stat7 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat7_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t hist7 : 32; /**< Number of packets sent with an octet count
of > 1518. */
uint64_t hist6 : 32; /**< Number of packets sent with an octet count of
@@ -6594,8 +8895,13 @@ union cvmx_gmxx_txx_stat7
struct cvmx_gmxx_txx_stat7_s cn56xxp1;
struct cvmx_gmxx_txx_stat7_s cn58xx;
struct cvmx_gmxx_txx_stat7_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat7_s cn61xx;
struct cvmx_gmxx_txx_stat7_s cn63xx;
struct cvmx_gmxx_txx_stat7_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat7_s cn66xx;
+ struct cvmx_gmxx_txx_stat7_s cn68xx;
+ struct cvmx_gmxx_txx_stat7_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat7_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat7_t;
@@ -6614,12 +8920,10 @@ typedef union cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat7_t;
* before the L2 header, then the MCST and BCST counters may not reflect
* reality and should be ignored by software.
*/
-union cvmx_gmxx_txx_stat8
-{
+union cvmx_gmxx_txx_stat8 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat8_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t mcst : 32; /**< Number of packets sent to multicast DMAC.
Does not include BCST packets. */
uint64_t bcst : 32; /**< Number of packets sent to broadcast DMAC.
@@ -6640,8 +8944,13 @@ union cvmx_gmxx_txx_stat8
struct cvmx_gmxx_txx_stat8_s cn56xxp1;
struct cvmx_gmxx_txx_stat8_s cn58xx;
struct cvmx_gmxx_txx_stat8_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat8_s cn61xx;
struct cvmx_gmxx_txx_stat8_s cn63xx;
struct cvmx_gmxx_txx_stat8_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat8_s cn66xx;
+ struct cvmx_gmxx_txx_stat8_s cn68xx;
+ struct cvmx_gmxx_txx_stat8_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat8_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat8_t;
@@ -6655,16 +8964,17 @@ typedef union cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat8_t;
* - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
* - Counters will wrap
*/
-union cvmx_gmxx_txx_stat9
-{
+union cvmx_gmxx_txx_stat9 {
uint64_t u64;
- struct cvmx_gmxx_txx_stat9_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stat9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t undflw : 32; /**< Number of underflow packets */
uint64_t ctl : 32; /**< Number of Control packets (PAUSE flow control)
generated by GMX. It does not include control
- packets forwarded or generated by the PP's. */
+ packets forwarded or generated by the PP's.
+ CTL will count the number of generated PFC frames.
+ CTL will not track the number of generated HG2
+ messages. */
#else
uint64_t ctl : 32;
uint64_t undflw : 32;
@@ -6681,8 +8991,13 @@ union cvmx_gmxx_txx_stat9
struct cvmx_gmxx_txx_stat9_s cn56xxp1;
struct cvmx_gmxx_txx_stat9_s cn58xx;
struct cvmx_gmxx_txx_stat9_s cn58xxp1;
+ struct cvmx_gmxx_txx_stat9_s cn61xx;
struct cvmx_gmxx_txx_stat9_s cn63xx;
struct cvmx_gmxx_txx_stat9_s cn63xxp1;
+ struct cvmx_gmxx_txx_stat9_s cn66xx;
+ struct cvmx_gmxx_txx_stat9_s cn68xx;
+ struct cvmx_gmxx_txx_stat9_s cn68xxp1;
+ struct cvmx_gmxx_txx_stat9_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stat9 cvmx_gmxx_txx_stat9_t;
@@ -6692,12 +9007,10 @@ typedef union cvmx_gmxx_txx_stat9 cvmx_gmxx_txx_stat9_t;
* GMX_TX_STATS_CTL = TX Stats Control register
*
*/
-union cvmx_gmxx_txx_stats_ctl
-{
+union cvmx_gmxx_txx_stats_ctl {
uint64_t u64;
- struct cvmx_gmxx_txx_stats_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t rd_clr : 1; /**< Stats registers will clear on reads */
#else
@@ -6716,8 +9029,13 @@ union cvmx_gmxx_txx_stats_ctl
struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
+ struct cvmx_gmxx_txx_stats_ctl_s cn61xx;
struct cvmx_gmxx_txx_stats_ctl_s cn63xx;
struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1;
+ struct cvmx_gmxx_txx_stats_ctl_s cn66xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn68xx;
+ struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1;
+ struct cvmx_gmxx_txx_stats_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_stats_ctl_t;
@@ -6733,14 +9051,12 @@ typedef union cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_stats_ctl_t;
* In XAUI mode, prt0 is used for checking. Since XAUI mode uses a single TX FIFO and is higher data rate, recommended value is 0x100.
*
*/
-union cvmx_gmxx_txx_thresh
-{
+union cvmx_gmxx_txx_thresh {
uint64_t u64;
- struct cvmx_gmxx_txx_thresh_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_9_63 : 55;
- uint64_t cnt : 9; /**< Number of 16B ticks to accumulate in the TX FIFO
+ struct cvmx_gmxx_txx_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t cnt : 10; /**< Number of 16B ticks to accumulate in the TX FIFO
before sending on the packet interface
This register should be large enough to prevent
underflow on the packet interface and must never
@@ -6750,13 +9066,12 @@ union cvmx_gmxx_txx_thresh
GMX_TX_PRTS==2 : CNT MAX = 0x080
GMX_TX_PRTS==3,4: CNT MAX = 0x040 */
#else
- uint64_t cnt : 9;
- uint64_t reserved_9_63 : 55;
+ uint64_t cnt : 10;
+ uint64_t reserved_10_63 : 54;
#endif
} s;
- struct cvmx_gmxx_txx_thresh_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_txx_thresh_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63 : 57;
uint64_t cnt : 7; /**< Number of 16B ticks to accumulate in the TX FIFO
before sending on the RGMII interface
@@ -6770,17 +9085,39 @@ union cvmx_gmxx_txx_thresh
#endif
} cn30xx;
struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
- struct cvmx_gmxx_txx_thresh_s cn38xx;
- struct cvmx_gmxx_txx_thresh_s cn38xxp2;
+ struct cvmx_gmxx_txx_thresh_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_9_63 : 55;
+ uint64_t cnt : 9; /**< Number of 16B ticks to accumulate in the TX FIFO
+ before sending on the RGMII interface
+ This register should be large enough to prevent
+ underflow on the RGMII interface and must never
+ be set to zero. This register cannot exceed the
+ the TX FIFO depth which is...
+ GMX_TX_PRTS==0,1: CNT MAX = 0x100
+ GMX_TX_PRTS==2 : CNT MAX = 0x080
+ GMX_TX_PRTS==3,4: CNT MAX = 0x040
+ (PASS2 expands from 6 to 9 bits) */
+#else
+ uint64_t cnt : 9;
+ uint64_t reserved_9_63 : 55;
+#endif
+ } cn38xx;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2;
struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
- struct cvmx_gmxx_txx_thresh_s cn52xx;
- struct cvmx_gmxx_txx_thresh_s cn52xxp1;
- struct cvmx_gmxx_txx_thresh_s cn56xx;
- struct cvmx_gmxx_txx_thresh_s cn56xxp1;
- struct cvmx_gmxx_txx_thresh_s cn58xx;
- struct cvmx_gmxx_txx_thresh_s cn58xxp1;
- struct cvmx_gmxx_txx_thresh_s cn63xx;
- struct cvmx_gmxx_txx_thresh_s cn63xxp1;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn52xx;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn56xx;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn58xx;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn61xx;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn63xx;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1;
+ struct cvmx_gmxx_txx_thresh_cn38xx cn66xx;
+ struct cvmx_gmxx_txx_thresh_s cn68xx;
+ struct cvmx_gmxx_txx_thresh_s cn68xxp1;
+ struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx;
};
typedef union cvmx_gmxx_txx_thresh cvmx_gmxx_txx_thresh_t;
@@ -6794,12 +9131,10 @@ typedef union cvmx_gmxx_txx_thresh cvmx_gmxx_txx_thresh_t;
* In XAUI mode, only the lsb (corresponding to port0) of BP is used.
*
*/
-union cvmx_gmxx_tx_bp
-{
+union cvmx_gmxx_tx_bp {
uint64_t u64;
- struct cvmx_gmxx_tx_bp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t bp : 4; /**< Per port BackPressure status
0=Port is available
@@ -6809,9 +9144,8 @@ union cvmx_gmxx_tx_bp
uint64_t reserved_4_63 : 60;
#endif
} s;
- struct cvmx_gmxx_tx_bp_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_bp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63 : 61;
uint64_t bp : 3; /**< Per port BackPressure status
0=Port is available
@@ -6831,8 +9165,23 @@ union cvmx_gmxx_tx_bp
struct cvmx_gmxx_tx_bp_s cn56xxp1;
struct cvmx_gmxx_tx_bp_s cn58xx;
struct cvmx_gmxx_tx_bp_s cn58xxp1;
+ struct cvmx_gmxx_tx_bp_s cn61xx;
struct cvmx_gmxx_tx_bp_s cn63xx;
struct cvmx_gmxx_tx_bp_s cn63xxp1;
+ struct cvmx_gmxx_tx_bp_s cn66xx;
+ struct cvmx_gmxx_tx_bp_s cn68xx;
+ struct cvmx_gmxx_tx_bp_s cn68xxp1;
+ struct cvmx_gmxx_tx_bp_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_2_63 : 62;
+ uint64_t bp : 2; /**< Per port BackPressure status
+ 0=Port is available
+ 1=Port should be back pressured */
+#else
+ uint64_t bp : 2;
+ uint64_t reserved_2_63 : 62;
+#endif
+ } cnf71xx;
};
typedef union cvmx_gmxx_tx_bp cvmx_gmxx_tx_bp_t;
@@ -6842,12 +9191,10 @@ typedef union cvmx_gmxx_tx_bp cvmx_gmxx_tx_bp_t;
* GMX_TX_CLK_MSK = GMX Clock Select
*
*/
-union cvmx_gmxx_tx_clk_mskx
-{
+union cvmx_gmxx_tx_clk_mskx {
uint64_t u64;
- struct cvmx_gmxx_tx_clk_mskx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_clk_mskx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t msk : 1; /**< Write this bit to a 1 when switching clks */
#else
@@ -6866,12 +9213,10 @@ typedef union cvmx_gmxx_tx_clk_mskx cvmx_gmxx_tx_clk_mskx_t;
* GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame
*
*/
-union cvmx_gmxx_tx_col_attempt
-{
+union cvmx_gmxx_tx_col_attempt {
uint64_t u64;
- struct cvmx_gmxx_tx_col_attempt_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_col_attempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t limit : 5; /**< Collision Attempts
(SGMII/1000Base-X half-duplex only) */
@@ -6891,8 +9236,13 @@ union cvmx_gmxx_tx_col_attempt
struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
struct cvmx_gmxx_tx_col_attempt_s cn58xx;
struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
+ struct cvmx_gmxx_tx_col_attempt_s cn61xx;
struct cvmx_gmxx_tx_col_attempt_s cn63xx;
struct cvmx_gmxx_tx_col_attempt_s cn63xxp1;
+ struct cvmx_gmxx_tx_col_attempt_s cn66xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn68xx;
+ struct cvmx_gmxx_tx_col_attempt_s cn68xxp1;
+ struct cvmx_gmxx_tx_col_attempt_s cnf71xx;
};
typedef union cvmx_gmxx_tx_col_attempt cvmx_gmxx_tx_col_attempt_t;
@@ -6911,12 +9261,10 @@ typedef union cvmx_gmxx_tx_col_attempt cvmx_gmxx_tx_col_attempt_t;
* value is 0xeeeeeeee for SGMII/1000Base-X and 4 bytes of the error
* propagation code in XAUI mode.
*/
-union cvmx_gmxx_tx_corrupt
-{
+union cvmx_gmxx_tx_corrupt {
uint64_t u64;
- struct cvmx_gmxx_tx_corrupt_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_corrupt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t corrupt : 4; /**< Per port error propagation
0=Never corrupt packets
@@ -6926,9 +9274,8 @@ union cvmx_gmxx_tx_corrupt
uint64_t reserved_4_63 : 60;
#endif
} s;
- struct cvmx_gmxx_tx_corrupt_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_corrupt_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63 : 61;
uint64_t corrupt : 3; /**< Per port error propagation
0=Never corrupt packets
@@ -6948,8 +9295,23 @@ union cvmx_gmxx_tx_corrupt
struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
struct cvmx_gmxx_tx_corrupt_s cn58xx;
struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
+ struct cvmx_gmxx_tx_corrupt_s cn61xx;
struct cvmx_gmxx_tx_corrupt_s cn63xx;
struct cvmx_gmxx_tx_corrupt_s cn63xxp1;
+ struct cvmx_gmxx_tx_corrupt_s cn66xx;
+ struct cvmx_gmxx_tx_corrupt_s cn68xx;
+ struct cvmx_gmxx_tx_corrupt_s cn68xxp1;
+ struct cvmx_gmxx_tx_corrupt_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_2_63 : 62;
+ uint64_t corrupt : 2; /**< Per port error propagation
+ 0=Never corrupt packets
+ 1=Corrupt packets with ERR */
+#else
+ uint64_t corrupt : 2;
+ uint64_t reserved_2_63 : 62;
+#endif
+ } cnf71xx;
};
typedef union cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_corrupt_t;
@@ -6963,12 +9325,10 @@ typedef union cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_corrupt_t;
* GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
* For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
*/
-union cvmx_gmxx_tx_hg2_reg1
-{
+union cvmx_gmxx_tx_hg2_reg1 {
uint64_t u64;
- struct cvmx_gmxx_tx_hg2_reg1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_hg2_reg1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t tx_xof : 16; /**< TX HiGig2 message for logical link pause when any
bit value changes
@@ -6983,8 +9343,13 @@ union cvmx_gmxx_tx_hg2_reg1
struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
+ struct cvmx_gmxx_tx_hg2_reg1_s cn61xx;
struct cvmx_gmxx_tx_hg2_reg1_s cn63xx;
struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1;
+ struct cvmx_gmxx_tx_hg2_reg1_s cn66xx;
+ struct cvmx_gmxx_tx_hg2_reg1_s cn68xx;
+ struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1;
+ struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx;
};
typedef union cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg1_t;
@@ -6998,12 +9363,10 @@ typedef union cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg1_t;
* GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
* For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
*/
-union cvmx_gmxx_tx_hg2_reg2
-{
+union cvmx_gmxx_tx_hg2_reg2 {
uint64_t u64;
- struct cvmx_gmxx_tx_hg2_reg2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_hg2_reg2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t tx_xon : 16; /**< TX HiGig2 message for logical link pause when any
bit value changes
@@ -7018,8 +9381,13 @@ union cvmx_gmxx_tx_hg2_reg2
struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
+ struct cvmx_gmxx_tx_hg2_reg2_s cn61xx;
struct cvmx_gmxx_tx_hg2_reg2_s cn63xx;
struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1;
+ struct cvmx_gmxx_tx_hg2_reg2_s cn66xx;
+ struct cvmx_gmxx_tx_hg2_reg2_s cn68xx;
+ struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1;
+ struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx;
};
typedef union cvmx_gmxx_tx_hg2_reg2 cvmx_gmxx_tx_hg2_reg2_t;
@@ -7046,12 +9414,10 @@ typedef union cvmx_gmxx_tx_hg2_reg2 cvmx_gmxx_tx_hg2_reg2_t;
* For all other systems, IFG1 and IFG2 can be any value in the range of
* 1-15. Allowing for a total possible IFG sum of 2-30.
*/
-union cvmx_gmxx_tx_ifg
-{
+union cvmx_gmxx_tx_ifg {
uint64_t u64;
- struct cvmx_gmxx_tx_ifg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t ifg2 : 4; /**< 1/3 of the interframe gap timing (in IFG2*8 bits)
If CRS is detected during IFG2, then the
@@ -7078,8 +9444,13 @@ union cvmx_gmxx_tx_ifg
struct cvmx_gmxx_tx_ifg_s cn56xxp1;
struct cvmx_gmxx_tx_ifg_s cn58xx;
struct cvmx_gmxx_tx_ifg_s cn58xxp1;
+ struct cvmx_gmxx_tx_ifg_s cn61xx;
struct cvmx_gmxx_tx_ifg_s cn63xx;
struct cvmx_gmxx_tx_ifg_s cn63xxp1;
+ struct cvmx_gmxx_tx_ifg_s cn66xx;
+ struct cvmx_gmxx_tx_ifg_s cn68xx;
+ struct cvmx_gmxx_tx_ifg_s cn68xxp1;
+ struct cvmx_gmxx_tx_ifg_s cnf71xx;
};
typedef union cvmx_gmxx_tx_ifg cvmx_gmxx_tx_ifg_t;
@@ -7093,13 +9464,14 @@ typedef union cvmx_gmxx_tx_ifg cvmx_gmxx_tx_ifg_t;
* In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
*
*/
-union cvmx_gmxx_tx_int_en
-{
+union cvmx_gmxx_tx_int_en {
uint64_t u64;
- struct cvmx_gmxx_tx_int_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_24_63 : 40;
+ struct cvmx_gmxx_tx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_25_63 : 39;
+ uint64_t xchange : 1; /**< XAUI link status changed - this denotes a change
+ to GMX_RX_XAUI_CTL[STATUS]
+ (XAUI mode only) */
uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be
sent due to XSCOL */
uint64_t late_col : 4; /**< TX Late Collision
@@ -7110,23 +9482,23 @@ union cvmx_gmxx_tx_int_en
(SGMII/1000Base-X half-duplex only) */
uint64_t reserved_6_7 : 2;
uint64_t undflw : 4; /**< TX Underflow */
- uint64_t ncb_nxa : 1; /**< Port address out-of-range from NCB Interface */
+ uint64_t reserved_1_1 : 1;
uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */
#else
uint64_t pko_nxa : 1;
- uint64_t ncb_nxa : 1;
+ uint64_t reserved_1_1 : 1;
uint64_t undflw : 4;
uint64_t reserved_6_7 : 2;
uint64_t xscol : 4;
uint64_t xsdef : 4;
uint64_t late_col : 4;
uint64_t ptp_lost : 4;
- uint64_t reserved_24_63 : 40;
+ uint64_t xchange : 1;
+ uint64_t reserved_25_63 : 39;
#endif
} s;
- struct cvmx_gmxx_tx_int_en_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63 : 45;
uint64_t late_col : 3; /**< TX Late Collision */
uint64_t reserved_15_15 : 1;
@@ -7150,9 +9522,8 @@ union cvmx_gmxx_tx_int_en
uint64_t reserved_19_63 : 45;
#endif
} cn30xx;
- struct cvmx_gmxx_tx_int_en_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_en_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_15_63 : 49;
uint64_t xsdef : 3; /**< TX Excessive deferral (RGMII/halfdup mode only) */
uint64_t reserved_11_11 : 1;
@@ -7172,9 +9543,8 @@ union cvmx_gmxx_tx_int_en
uint64_t reserved_15_63 : 49;
#endif
} cn31xx;
- struct cvmx_gmxx_tx_int_en_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_en_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t late_col : 4; /**< TX Late Collision
(PASS3 only) */
@@ -7195,9 +9565,8 @@ union cvmx_gmxx_tx_int_en
uint64_t reserved_20_63 : 44;
#endif
} cn38xx;
- struct cvmx_gmxx_tx_int_en_cn38xxp2
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_en_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t xsdef : 4; /**< TX Excessive deferral (RGMII/halfdup mode only) */
uint64_t xscol : 4; /**< TX Excessive collisions (RGMII/halfdup mode only) */
@@ -7216,9 +9585,8 @@ union cvmx_gmxx_tx_int_en
#endif
} cn38xxp2;
struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
- struct cvmx_gmxx_tx_int_en_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t late_col : 4; /**< TX Late Collision
(SGMII/1000Base-X half-duplex only) */
@@ -7246,9 +9614,9 @@ union cvmx_gmxx_tx_int_en
struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
struct cvmx_gmxx_tx_int_en_cn38xx cn58xx;
struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1;
- struct cvmx_gmxx_tx_int_en_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_en_s cn61xx;
+ struct cvmx_gmxx_tx_int_en_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63 : 40;
uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be
sent due to XSCOL */
@@ -7275,6 +9643,78 @@ union cvmx_gmxx_tx_int_en
#endif
} cn63xx;
struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1;
+ struct cvmx_gmxx_tx_int_en_s cn66xx;
+ struct cvmx_gmxx_tx_int_en_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_25_63 : 39;
+ uint64_t xchange : 1; /**< XAUI/RXAUI link status changed - this denotes a
+ change to GMX_RX_XAUI_CTL[STATUS]
+ (XAUI/RXAUI mode only) */
+ uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be
+ sent due to XSCOL */
+ uint64_t late_col : 4; /**< TX Late Collision
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t xsdef : 4; /**< TX Excessive deferral
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t xscol : 4; /**< TX Excessive collisions
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t reserved_6_7 : 2;
+ uint64_t undflw : 4; /**< TX Underflow */
+ uint64_t pko_nxp : 1; /**< Port pipe out-of-range from PKO Interface */
+ uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */
+#else
+ uint64_t pko_nxa : 1;
+ uint64_t pko_nxp : 1;
+ uint64_t undflw : 4;
+ uint64_t reserved_6_7 : 2;
+ uint64_t xscol : 4;
+ uint64_t xsdef : 4;
+ uint64_t late_col : 4;
+ uint64_t ptp_lost : 4;
+ uint64_t xchange : 1;
+ uint64_t reserved_25_63 : 39;
+#endif
+ } cn68xx;
+ struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1;
+ struct cvmx_gmxx_tx_int_en_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_25_63 : 39;
+ uint64_t xchange : 1; /**< XAUI link status changed - this denotes a change
+ to GMX_RX_XAUI_CTL[STATUS]
+ (XAUI mode only) */
+ uint64_t reserved_22_23 : 2;
+ uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be
+ sent due to XSCOL */
+ uint64_t reserved_18_19 : 2;
+ uint64_t late_col : 2; /**< TX Late Collision
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t reserved_14_15 : 2;
+ uint64_t xsdef : 2; /**< TX Excessive deferral
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t reserved_10_11 : 2;
+ uint64_t xscol : 2; /**< TX Excessive collisions
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t reserved_4_7 : 4;
+ uint64_t undflw : 2; /**< TX Underflow */
+ uint64_t reserved_1_1 : 1;
+ uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */
+#else
+ uint64_t pko_nxa : 1;
+ uint64_t reserved_1_1 : 1;
+ uint64_t undflw : 2;
+ uint64_t reserved_4_7 : 4;
+ uint64_t xscol : 2;
+ uint64_t reserved_10_11 : 2;
+ uint64_t xsdef : 2;
+ uint64_t reserved_14_15 : 2;
+ uint64_t late_col : 2;
+ uint64_t reserved_18_19 : 2;
+ uint64_t ptp_lost : 2;
+ uint64_t reserved_22_23 : 2;
+ uint64_t xchange : 1;
+ uint64_t reserved_25_63 : 39;
+#endif
+ } cnf71xx;
};
typedef union cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_en_t;
@@ -7288,13 +9728,14 @@ typedef union cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_en_t;
* In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
*
*/
-union cvmx_gmxx_tx_int_reg
-{
+union cvmx_gmxx_tx_int_reg {
uint64_t u64;
- struct cvmx_gmxx_tx_int_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_24_63 : 40;
+ struct cvmx_gmxx_tx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_25_63 : 39;
+ uint64_t xchange : 1; /**< XAUI link status changed - this denotes a change
+ to GMX_RX_XAUI_CTL[STATUS]
+ (XAUI mode only) */
uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be
sent due to XSCOL */
uint64_t late_col : 4; /**< TX Late Collision
@@ -7305,23 +9746,23 @@ union cvmx_gmxx_tx_int_reg
(SGMII/1000Base-X half-duplex only) */
uint64_t reserved_6_7 : 2;
uint64_t undflw : 4; /**< TX Underflow */
- uint64_t ncb_nxa : 1; /**< Port address out-of-range from NCB Interface */
+ uint64_t reserved_1_1 : 1;
uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */
#else
uint64_t pko_nxa : 1;
- uint64_t ncb_nxa : 1;
+ uint64_t reserved_1_1 : 1;
uint64_t undflw : 4;
uint64_t reserved_6_7 : 2;
uint64_t xscol : 4;
uint64_t xsdef : 4;
uint64_t late_col : 4;
uint64_t ptp_lost : 4;
- uint64_t reserved_24_63 : 40;
+ uint64_t xchange : 1;
+ uint64_t reserved_25_63 : 39;
#endif
} s;
- struct cvmx_gmxx_tx_int_reg_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63 : 45;
uint64_t late_col : 3; /**< TX Late Collision */
uint64_t reserved_15_15 : 1;
@@ -7345,9 +9786,8 @@ union cvmx_gmxx_tx_int_reg
uint64_t reserved_19_63 : 45;
#endif
} cn30xx;
- struct cvmx_gmxx_tx_int_reg_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_reg_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_15_63 : 49;
uint64_t xsdef : 3; /**< TX Excessive deferral (RGMII/halfdup mode only) */
uint64_t reserved_11_11 : 1;
@@ -7367,9 +9807,8 @@ union cvmx_gmxx_tx_int_reg
uint64_t reserved_15_63 : 49;
#endif
} cn31xx;
- struct cvmx_gmxx_tx_int_reg_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_reg_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t late_col : 4; /**< TX Late Collision
(PASS3 only) */
@@ -7390,9 +9829,8 @@ union cvmx_gmxx_tx_int_reg
uint64_t reserved_20_63 : 44;
#endif
} cn38xx;
- struct cvmx_gmxx_tx_int_reg_cn38xxp2
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t xsdef : 4; /**< TX Excessive deferral (RGMII/halfdup mode only) */
uint64_t xscol : 4; /**< TX Excessive collisions (RGMII/halfdup mode only) */
@@ -7411,9 +9849,8 @@ union cvmx_gmxx_tx_int_reg
#endif
} cn38xxp2;
struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
- struct cvmx_gmxx_tx_int_reg_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t late_col : 4; /**< TX Late Collision
(SGMII/1000Base-X half-duplex only) */
@@ -7441,9 +9878,9 @@ union cvmx_gmxx_tx_int_reg
struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx;
struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1;
- struct cvmx_gmxx_tx_int_reg_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_int_reg_s cn61xx;
+ struct cvmx_gmxx_tx_int_reg_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63 : 40;
uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be
sent due to XSCOL */
@@ -7470,6 +9907,78 @@ union cvmx_gmxx_tx_int_reg
#endif
} cn63xx;
struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1;
+ struct cvmx_gmxx_tx_int_reg_s cn66xx;
+ struct cvmx_gmxx_tx_int_reg_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_25_63 : 39;
+ uint64_t xchange : 1; /**< XAUI/RXAUI link status changed - this denotes ae
+ change to GMX_RX_XAUI_CTL[STATUS]
+ (XAUI/RXAUI mode only) */
+ uint64_t ptp_lost : 4; /**< A packet with a PTP request was not able to be
+ sent due to XSCOL */
+ uint64_t late_col : 4; /**< TX Late Collision
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t xsdef : 4; /**< TX Excessive deferral
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t xscol : 4; /**< TX Excessive collisions
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t reserved_6_7 : 2;
+ uint64_t undflw : 4; /**< TX Underflow */
+ uint64_t pko_nxp : 1; /**< Port pipe out-of-range from PKO Interface */
+ uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */
+#else
+ uint64_t pko_nxa : 1;
+ uint64_t pko_nxp : 1;
+ uint64_t undflw : 4;
+ uint64_t reserved_6_7 : 2;
+ uint64_t xscol : 4;
+ uint64_t xsdef : 4;
+ uint64_t late_col : 4;
+ uint64_t ptp_lost : 4;
+ uint64_t xchange : 1;
+ uint64_t reserved_25_63 : 39;
+#endif
+ } cn68xx;
+ struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1;
+ struct cvmx_gmxx_tx_int_reg_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_25_63 : 39;
+ uint64_t xchange : 1; /**< XAUI link status changed - this denotes a change
+ to GMX_RX_XAUI_CTL[STATUS]
+ (XAUI mode only) */
+ uint64_t reserved_22_23 : 2;
+ uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be
+ sent due to XSCOL */
+ uint64_t reserved_18_19 : 2;
+ uint64_t late_col : 2; /**< TX Late Collision
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t reserved_14_15 : 2;
+ uint64_t xsdef : 2; /**< TX Excessive deferral
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t reserved_10_11 : 2;
+ uint64_t xscol : 2; /**< TX Excessive collisions
+ (SGMII/1000Base-X half-duplex only) */
+ uint64_t reserved_4_7 : 4;
+ uint64_t undflw : 2; /**< TX Underflow */
+ uint64_t reserved_1_1 : 1;
+ uint64_t pko_nxa : 1; /**< Port address out-of-range from PKO Interface */
+#else
+ uint64_t pko_nxa : 1;
+ uint64_t reserved_1_1 : 1;
+ uint64_t undflw : 2;
+ uint64_t reserved_4_7 : 4;
+ uint64_t xscol : 2;
+ uint64_t reserved_10_11 : 2;
+ uint64_t xsdef : 2;
+ uint64_t reserved_14_15 : 2;
+ uint64_t late_col : 2;
+ uint64_t reserved_18_19 : 2;
+ uint64_t ptp_lost : 2;
+ uint64_t reserved_22_23 : 2;
+ uint64_t xchange : 1;
+ uint64_t reserved_25_63 : 39;
+#endif
+ } cnf71xx;
};
typedef union cvmx_gmxx_tx_int_reg cvmx_gmxx_tx_int_reg_t;
@@ -7479,12 +9988,10 @@ typedef union cvmx_gmxx_tx_int_reg cvmx_gmxx_tx_int_reg_t;
* GMX_TX_JAM = Packet TX Jam Pattern
*
*/
-union cvmx_gmxx_tx_jam
-{
+union cvmx_gmxx_tx_jam {
uint64_t u64;
- struct cvmx_gmxx_tx_jam_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_jam_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t jam : 8; /**< Jam pattern
(SGMII/1000Base-X half-duplex only) */
@@ -7504,8 +10011,13 @@ union cvmx_gmxx_tx_jam
struct cvmx_gmxx_tx_jam_s cn56xxp1;
struct cvmx_gmxx_tx_jam_s cn58xx;
struct cvmx_gmxx_tx_jam_s cn58xxp1;
+ struct cvmx_gmxx_tx_jam_s cn61xx;
struct cvmx_gmxx_tx_jam_s cn63xx;
struct cvmx_gmxx_tx_jam_s cn63xxp1;
+ struct cvmx_gmxx_tx_jam_s cn66xx;
+ struct cvmx_gmxx_tx_jam_s cn68xx;
+ struct cvmx_gmxx_tx_jam_s cn68xxp1;
+ struct cvmx_gmxx_tx_jam_s cnf71xx;
};
typedef union cvmx_gmxx_tx_jam cvmx_gmxx_tx_jam_t;
@@ -7515,12 +10027,10 @@ typedef union cvmx_gmxx_tx_jam cvmx_gmxx_tx_jam_t;
* GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
*
*/
-union cvmx_gmxx_tx_lfsr
-{
+union cvmx_gmxx_tx_lfsr {
uint64_t u64;
- struct cvmx_gmxx_tx_lfsr_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_lfsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t lfsr : 16; /**< The current state of the LFSR used to feed random
numbers to compute truncated binary exponential
@@ -7542,8 +10052,13 @@ union cvmx_gmxx_tx_lfsr
struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
struct cvmx_gmxx_tx_lfsr_s cn58xx;
struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
+ struct cvmx_gmxx_tx_lfsr_s cn61xx;
struct cvmx_gmxx_tx_lfsr_s cn63xx;
struct cvmx_gmxx_tx_lfsr_s cn63xxp1;
+ struct cvmx_gmxx_tx_lfsr_s cn66xx;
+ struct cvmx_gmxx_tx_lfsr_s cn68xx;
+ struct cvmx_gmxx_tx_lfsr_s cn68xxp1;
+ struct cvmx_gmxx_tx_lfsr_s cnf71xx;
};
typedef union cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_lfsr_t;
@@ -7563,12 +10078,10 @@ typedef union cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_lfsr_t;
* through HiGig2 messages (optionally, when GMX*_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2
* protocol.
*/
-union cvmx_gmxx_tx_ovr_bp
-{
+union cvmx_gmxx_tx_ovr_bp {
uint64_t u64;
- struct cvmx_gmxx_tx_ovr_bp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_ovr_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t tx_prt_bp : 16; /**< Per port BP sent to PKO
0=Port is available
@@ -7590,9 +10103,8 @@ union cvmx_gmxx_tx_ovr_bp
uint64_t reserved_48_63 : 16;
#endif
} s;
- struct cvmx_gmxx_tx_ovr_bp_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_ovr_bp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63 : 53;
uint64_t en : 3; /**< Per port Enable back pressure override */
uint64_t reserved_7_7 : 1;
@@ -7611,9 +10123,8 @@ union cvmx_gmxx_tx_ovr_bp
#endif
} cn30xx;
struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
- struct cvmx_gmxx_tx_ovr_bp_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_ovr_bp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t en : 4; /**< Per port Enable back pressure override */
uint64_t bp : 4; /**< Per port BackPressure status to use
@@ -7635,8 +10146,39 @@ union cvmx_gmxx_tx_ovr_bp
struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
+ struct cvmx_gmxx_tx_ovr_bp_s cn61xx;
struct cvmx_gmxx_tx_ovr_bp_s cn63xx;
struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1;
+ struct cvmx_gmxx_tx_ovr_bp_s cn66xx;
+ struct cvmx_gmxx_tx_ovr_bp_s cn68xx;
+ struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1;
+ struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_48_63 : 16;
+ uint64_t tx_prt_bp : 16; /**< Per port BP sent to PKO
+ 0=Port is available
+ 1=Port should be back pressured
+ TX_PRT_BP should not be set until
+ GMX_INF_MODE[EN] has been enabled */
+ uint64_t reserved_10_31 : 22;
+ uint64_t en : 2; /**< Per port Enable back pressure override */
+ uint64_t reserved_6_7 : 2;
+ uint64_t bp : 2; /**< Per port BackPressure status to use
+ 0=Port is available
+ 1=Port should be back pressured */
+ uint64_t reserved_2_3 : 2;
+ uint64_t ign_full : 2; /**< Ignore the RX FIFO full when computing BP */
+#else
+ uint64_t ign_full : 2;
+ uint64_t reserved_2_3 : 2;
+ uint64_t bp : 2;
+ uint64_t reserved_6_7 : 2;
+ uint64_t en : 2;
+ uint64_t reserved_10_31 : 22;
+ uint64_t tx_prt_bp : 16;
+ uint64_t reserved_48_63 : 16;
+#endif
+ } cnf71xx;
};
typedef union cvmx_gmxx_tx_ovr_bp cvmx_gmxx_tx_ovr_bp_t;
@@ -7646,12 +10188,10 @@ typedef union cvmx_gmxx_tx_ovr_bp cvmx_gmxx_tx_ovr_bp_t;
* GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field
*
*/
-union cvmx_gmxx_tx_pause_pkt_dmac
-{
+union cvmx_gmxx_tx_pause_pkt_dmac {
uint64_t u64;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t dmac : 48; /**< The DMAC field placed is outbnd pause pkts */
#else
@@ -7670,8 +10210,13 @@ union cvmx_gmxx_tx_pause_pkt_dmac
struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx;
struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx;
struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx;
};
typedef union cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_dmac_t;
@@ -7681,12 +10226,10 @@ typedef union cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_dmac_t;
* GMX_TX_PAUSE_PKT_TYPE = Packet Interface TX Pause Packet TYPE field
*
*/
-union cvmx_gmxx_tx_pause_pkt_type
-{
+union cvmx_gmxx_tx_pause_pkt_type {
uint64_t u64;
- struct cvmx_gmxx_tx_pause_pkt_type_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_pause_pkt_type_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t type : 16; /**< The TYPE field placed is outbnd pause pkts */
#else
@@ -7705,8 +10248,13 @@ union cvmx_gmxx_tx_pause_pkt_type
struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx;
struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx;
struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1;
+ struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx;
};
typedef union cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_pause_pkt_type_t;
@@ -7724,12 +10272,10 @@ typedef union cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_pause_pkt_type_t;
* highest architected port, then the programmed value should be 3 since
* there are 3 ports in the system - 0, 1, and 2.
*/
-union cvmx_gmxx_tx_prts
-{
+union cvmx_gmxx_tx_prts {
uint64_t u64;
- struct cvmx_gmxx_tx_prts_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_prts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t prts : 5; /**< Number of ports allowed on the interface
(SGMII/1000Base-X only) */
@@ -7749,8 +10295,13 @@ union cvmx_gmxx_tx_prts
struct cvmx_gmxx_tx_prts_s cn56xxp1;
struct cvmx_gmxx_tx_prts_s cn58xx;
struct cvmx_gmxx_tx_prts_s cn58xxp1;
+ struct cvmx_gmxx_tx_prts_s cn61xx;
struct cvmx_gmxx_tx_prts_s cn63xx;
struct cvmx_gmxx_tx_prts_s cn63xxp1;
+ struct cvmx_gmxx_tx_prts_s cn66xx;
+ struct cvmx_gmxx_tx_prts_s cn68xx;
+ struct cvmx_gmxx_tx_prts_s cn68xxp1;
+ struct cvmx_gmxx_tx_prts_s cnf71xx;
};
typedef union cvmx_gmxx_tx_prts cvmx_gmxx_tx_prts_t;
@@ -7760,12 +10311,10 @@ typedef union cvmx_gmxx_tx_prts cvmx_gmxx_tx_prts_t;
* GMX_TX_SPI_CTL = Spi4 TX ModesSpi4
*
*/
-union cvmx_gmxx_tx_spi_ctl
-{
+union cvmx_gmxx_tx_spi_ctl {
uint64_t u64;
- struct cvmx_gmxx_tx_spi_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_spi_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t tpa_clr : 1; /**< TPA Clear Mode
Clear credit counter when satisifed status */
@@ -7791,12 +10340,10 @@ typedef union cvmx_gmxx_tx_spi_ctl cvmx_gmxx_tx_spi_ctl_t;
* GMX_TX_SPI_DRAIN = Drain out Spi TX FIFO
*
*/
-union cvmx_gmxx_tx_spi_drain
-{
+union cvmx_gmxx_tx_spi_drain {
uint64_t u64;
- struct cvmx_gmxx_tx_spi_drain_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_spi_drain_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t drain : 16; /**< Per port drain control
0=Normal operation
@@ -7822,12 +10369,10 @@ typedef union cvmx_gmxx_tx_spi_drain cvmx_gmxx_tx_spi_drain_t;
* GMX_TX_SPI_MAX = RGMII TX Spi4 MAX
*
*/
-union cvmx_gmxx_tx_spi_max
-{
+union cvmx_gmxx_tx_spi_max {
uint64_t u64;
- struct cvmx_gmxx_tx_spi_max_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_spi_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_23_63 : 41;
uint64_t slice : 7; /**< Number of 16B blocks to transmit in a burst before
switching to the next port. SLICE does not always
@@ -7856,9 +10401,8 @@ union cvmx_gmxx_tx_spi_max
uint64_t reserved_23_63 : 41;
#endif
} s;
- struct cvmx_gmxx_tx_spi_max_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_spi_max_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t max2 : 8; /**< MAX2 (per Spi4.2 spec) */
uint64_t max1 : 8; /**< MAX1 (per Spi4.2 spec)
@@ -7881,12 +10425,10 @@ typedef union cvmx_gmxx_tx_spi_max cvmx_gmxx_tx_spi_max_t;
* GMX_TX_SPI_ROUND = Controls SPI4 TX Arbitration
*
*/
-union cvmx_gmxx_tx_spi_roundx
-{
+union cvmx_gmxx_tx_spi_roundx {
uint64_t u64;
- struct cvmx_gmxx_tx_spi_roundx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_spi_roundx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t round : 16; /**< Which Spi ports participate in each arbitration
round. Each bit corresponds to a spi port
@@ -7918,12 +10460,10 @@ typedef union cvmx_gmxx_tx_spi_roundx cvmx_gmxx_tx_spi_roundx_t;
* Octeon will never violate the Spi4.2 spec and send a non-EOP burst that is
* not a multiple of 16B.
*/
-union cvmx_gmxx_tx_spi_thresh
-{
+union cvmx_gmxx_tx_spi_thresh {
uint64_t u64;
- struct cvmx_gmxx_tx_spi_thresh_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_spi_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t thresh : 6; /**< Transmit threshold in 16B blocks - cannot be zero
THRESH <= TX_FIFO size (in non-passthrough mode)
@@ -7949,12 +10489,10 @@ typedef union cvmx_gmxx_tx_spi_thresh cvmx_gmxx_tx_spi_thresh_t;
/**
* cvmx_gmx#_tx_xaui_ctl
*/
-union cvmx_gmxx_tx_xaui_ctl
-{
+union cvmx_gmxx_tx_xaui_ctl {
uint64_t u64;
- struct cvmx_gmxx_tx_xaui_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_tx_xaui_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63 : 53;
uint64_t hg_pause_hgi : 2; /**< HGI Field for HW generated HiGig pause packets
(XAUI mode only) */
@@ -8014,20 +10552,23 @@ union cvmx_gmxx_tx_xaui_ctl
struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
+ struct cvmx_gmxx_tx_xaui_ctl_s cn61xx;
struct cvmx_gmxx_tx_xaui_ctl_s cn63xx;
struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1;
+ struct cvmx_gmxx_tx_xaui_ctl_s cn66xx;
+ struct cvmx_gmxx_tx_xaui_ctl_s cn68xx;
+ struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1;
+ struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx;
};
typedef union cvmx_gmxx_tx_xaui_ctl cvmx_gmxx_tx_xaui_ctl_t;
/**
* cvmx_gmx#_xaui_ext_loopback
*/
-union cvmx_gmxx_xaui_ext_loopback
-{
+union cvmx_gmxx_xaui_ext_loopback {
uint64_t u64;
- struct cvmx_gmxx_xaui_ext_loopback_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_gmxx_xaui_ext_loopback_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t en : 1; /**< Loopback enable
Puts the packet interface in external loopback
@@ -8049,8 +10590,13 @@ union cvmx_gmxx_xaui_ext_loopback
struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
+ struct cvmx_gmxx_xaui_ext_loopback_s cn61xx;
struct cvmx_gmxx_xaui_ext_loopback_s cn63xx;
struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1;
+ struct cvmx_gmxx_xaui_ext_loopback_s cn66xx;
+ struct cvmx_gmxx_xaui_ext_loopback_s cn68xx;
+ struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1;
+ struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx;
};
typedef union cvmx_gmxx_xaui_ext_loopback cvmx_gmxx_xaui_ext_loopback_t;