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-rw-r--r--MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c247
-rw-r--r--MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf61
-rw-r--r--MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.uni23
-rw-r--r--MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c231
-rw-r--r--MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c242
-rw-r--r--MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c278
-rw-r--r--MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S38
-rw-r--r--MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S39
-rw-r--r--MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S36
-rw-r--r--MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm37
-rw-r--r--MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S43
-rw-r--r--MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm44
-rw-r--r--MdePkg/Library/BaseCpuLib/BaseCpuLib.inf82
-rw-r--r--MdePkg/Library/BaseCpuLib/BaseCpuLib.uni24
-rw-r--r--MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c46
-rw-r--r--MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.asm40
-rw-r--r--MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c34
-rw-r--r--MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm37
-rw-r--r--MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c32
-rw-r--r--MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.asm39
-rw-r--r--MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c34
-rw-r--r--MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm36
-rw-r--r--MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c33
-rw-r--r--MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s58
-rw-r--r--MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c66
-rw-r--r--MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.S35
-rw-r--r--MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.asm38
-rw-r--r--MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.nasm38
-rw-r--r--MdePkg/Library/BaseCpuLib/X64/CpuSleep.S34
-rw-r--r--MdePkg/Library/BaseCpuLib/X64/CpuSleep.asm37
-rw-r--r--MdePkg/Library/BaseCpuLib/X64/CpuSleep.nasm37
-rw-r--r--MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf36
-rw-r--r--MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.uni21
-rw-r--r--MdePkg/Library/BaseDebugLibNull/DebugLib.c198
-rw-r--r--MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf49
-rw-r--r--MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.uni21
-rw-r--r--MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c284
-rw-r--r--MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.c59
-rw-r--r--MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf40
-rw-r--r--MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.uni21
-rw-r--r--MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.c484
-rw-r--r--MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf54
-rw-r--r--MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.uni27
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf82
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.uni24
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicInternal.h26
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.asm141
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm137
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoHighLevel.c2356
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoLib.c317
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c599
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoLibEbc.c342
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c196
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoLibIcc.c214
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c736
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoLibMmioBuffer.c411
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c228
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifo.asm127
-rw-r--r--MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifo.nasm126
-rw-r--r--MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S37
-rw-r--r--MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S36
-rw-r--r--MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S36
-rw-r--r--MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S45
-rw-r--r--MdePkg/Library/BaseLib/AArch64/MemoryFence.S39
-rw-r--r--MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S97
-rw-r--r--MdePkg/Library/BaseLib/AArch64/SwitchStack.S69
-rw-r--r--MdePkg/Library/BaseLib/ARShiftU64.c41
-rw-r--r--MdePkg/Library/BaseLib/Arm/CpuBreakpoint.S36
-rw-r--r--MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm38
-rw-r--r--MdePkg/Library/BaseLib/Arm/CpuPause.asm41
-rw-r--r--MdePkg/Library/BaseLib/Arm/DisableInterrupts.S35
-rw-r--r--MdePkg/Library/BaseLib/Arm/DisableInterrupts.asm37
-rw-r--r--MdePkg/Library/BaseLib/Arm/EnableInterrupts.S36
-rw-r--r--MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm37
-rw-r--r--MdePkg/Library/BaseLib/Arm/GetInterruptsState.S43
-rw-r--r--MdePkg/Library/BaseLib/Arm/GetInterruptsState.asm45
-rw-r--r--MdePkg/Library/BaseLib/Arm/InternalSwitchStack.c79
-rwxr-xr-xMdePkg/Library/BaseLib/Arm/Math64.S269
-rw-r--r--MdePkg/Library/BaseLib/Arm/MemoryFence.S39
-rw-r--r--MdePkg/Library/BaseLib/Arm/MemoryFence.asm39
-rw-r--r--MdePkg/Library/BaseLib/Arm/SetJumpLongJump.S70
-rw-r--r--MdePkg/Library/BaseLib/Arm/SetJumpLongJump.asm70
-rw-r--r--MdePkg/Library/BaseLib/Arm/SwitchStack.S68
-rw-r--r--MdePkg/Library/BaseLib/Arm/SwitchStack.asm45
-rw-r--r--MdePkg/Library/BaseLib/Arm/Unaligned.c252
-rw-r--r--MdePkg/Library/BaseLib/BaseLib.inf872
-rw-r--r--MdePkg/Library/BaseLib/BaseLib.uni23
-rw-r--r--MdePkg/Library/BaseLib/BaseLibInternals.h1865
-rw-r--r--MdePkg/Library/BaseLib/BitField.c922
-rw-r--r--MdePkg/Library/BaseLib/CheckSum.c337
-rw-r--r--MdePkg/Library/BaseLib/ChkStkGcc.c24
-rw-r--r--MdePkg/Library/BaseLib/Cpu.c65
-rw-r--r--MdePkg/Library/BaseLib/CpuDeadLoop.c38
-rw-r--r--MdePkg/Library/BaseLib/DivS64x64Remainder.c53
-rw-r--r--MdePkg/Library/BaseLib/DivU64x32.c45
-rw-r--r--MdePkg/Library/BaseLib/DivU64x32Remainder.c49
-rw-r--r--MdePkg/Library/BaseLib/DivU64x64Remainder.c49
-rw-r--r--MdePkg/Library/BaseLib/Ebc/CpuBreakpoint.c129
-rw-r--r--MdePkg/Library/BaseLib/Ebc/SetJumpLongJump.c67
-rw-r--r--MdePkg/Library/BaseLib/Ebc/SwitchStack.c58
-rw-r--r--MdePkg/Library/BaseLib/FilePaths.c118
-rw-r--r--MdePkg/Library/BaseLib/GetPowerOfTwo32.c44
-rw-r--r--MdePkg/Library/BaseLib/GetPowerOfTwo64.c44
-rw-r--r--MdePkg/Library/BaseLib/HighBitSet32.c47
-rw-r--r--MdePkg/Library/BaseLib/HighBitSet64.c55
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ARShiftU64.S43
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ARShiftU64.asm48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ARShiftU64.c51
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ARShiftU64.nasm45
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.c41
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuBreakpoint.nasm36
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuId.S63
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuId.asm66
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuId.c74
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuId.nasm65
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuIdEx.S67
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuIdEx.asm68
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuIdEx.c82
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuIdEx.nasm67
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuPause.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuPause.c35
-rw-r--r--MdePkg/Library/BaseLib/Ia32/CpuPause.nasm36
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisableCache.S39
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisableCache.asm45
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisableCache.c36
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisableCache.nasm42
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisableInterrupts.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisableInterrupts.c32
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisableInterrupts.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisablePaging32.S52
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisablePaging32.asm57
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisablePaging32.c77
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DisablePaging32.nasm54
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivS64x64Remainder.c53
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x32.S41
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x32.asm46
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x32.c50
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x32.nasm43
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.S46
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.asm51
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.c55
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x32Remainder.nasm48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.S89
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.asm92
-rw-r--r--MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.nasm94
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableCache.S39
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableCache.asm45
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableCache.c36
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableCache.nasm42
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.S36
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.asm41
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.c36
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableDisableInterrupts.nasm38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableInterrupts.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableInterrupts.c32
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnableInterrupts.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnablePaging32.S52
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnablePaging32.asm57
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnablePaging32.c81
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnablePaging32.nasm54
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnablePaging64.S63
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnablePaging64.asm68
-rw-r--r--MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm65
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm55
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c58
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FlushCacheLine.nasm51
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FxRestore.asm42
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FxRestore.c40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FxRestore.nasm38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FxSave.asm42
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FxSave.c40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/FxSave.nasm38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/GccInline.c1771
-rw-r--r--MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.S48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.c60
-rw-r--r--MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.nasm47
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Invd.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Invd.c35
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Invd.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LRotU64.S48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LRotU64.asm51
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LRotU64.c55
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LRotU64.nasm50
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LShiftU64.S43
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LShiftU64.asm48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LShiftU64.c51
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm45
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LongJump.S41
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LongJump.asm46
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LongJump.c50
-rw-r--r--MdePkg/Library/BaseLib/Ia32/LongJump.nasm43
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ModU64x32.S40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ModU64x32.asm45
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ModU64x32.c48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ModU64x32.nasm42
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Monitor.S40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Monitor.asm45
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Monitor.c48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Monitor.nasm42
-rw-r--r--MdePkg/Library/BaseLib/Ia32/MultU64x32.S41
-rw-r--r--MdePkg/Library/BaseLib/Ia32/MultU64x32.asm43
-rw-r--r--MdePkg/Library/BaseLib/Ia32/MultU64x32.c47
-rw-r--r--MdePkg/Library/BaseLib/Ia32/MultU64x32.nasm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/MultU64x64.S44
-rw-r--r--MdePkg/Library/BaseLib/Ia32/MultU64x64.asm47
-rw-r--r--MdePkg/Library/BaseLib/Ia32/MultU64x64.c51
-rw-r--r--MdePkg/Library/BaseLib/Ia32/MultU64x64.nasm46
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Mwait.S38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Mwait.asm43
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Mwait.c44
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Mwait.nasm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/Non-existing.c57
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RRotU64.S48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RRotU64.asm51
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RRotU64.c55
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RRotU64.nasm50
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RShiftU64.S46
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RShiftU64.asm48
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RShiftU64.c51
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RShiftU64.nasm45
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RdRand.S80
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RdRand.asm94
-rw-r--r--MdePkg/Library/BaseLib/Ia32/RdRand.nasm90
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr0.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr0.c37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr0.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr2.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr2.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr2.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr3.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr3.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr3.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr4.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr4.c40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCr4.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCs.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCs.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadCs.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr0.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr0.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr0.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr1.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr1.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr1.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr2.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr2.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr2.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr3.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr3.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr3.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr4.asm47
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr4.c40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm44
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr5.asm47
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr5.c40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm44
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr6.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr6.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr6.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr7.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr7.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDr7.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDs.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDs.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadDs.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadEflags.asm41
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadEflags.c39
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadEflags.nasm38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadEs.asm40
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadEs.c38
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadEs.nasm37
-rw-r--r--MdePkg/Library/BaseLib/Ia32/ReadFs.asm40
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-rw-r--r--MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.c72
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-rw-r--r--MdePkg/Library/UefiMemoryLib/CompareMemWrapper.c66
-rw-r--r--MdePkg/Library/UefiMemoryLib/CopyMemWrapper.c63
-rw-r--r--MdePkg/Library/UefiMemoryLib/IsZeroBufferWrapper.c54
-rw-r--r--MdePkg/Library/UefiMemoryLib/MemLib.c63
-rw-r--r--MdePkg/Library/UefiMemoryLib/MemLibGeneric.c289
-rw-r--r--MdePkg/Library/UefiMemoryLib/MemLibGuid.c171
-rw-r--r--MdePkg/Library/UefiMemoryLib/MemLibInternals.h249
-rw-r--r--MdePkg/Library/UefiMemoryLib/ScanMem16Wrapper.c67
-rw-r--r--MdePkg/Library/UefiMemoryLib/ScanMem32Wrapper.c66
-rw-r--r--MdePkg/Library/UefiMemoryLib/ScanMem64Wrapper.c67
-rw-r--r--MdePkg/Library/UefiMemoryLib/ScanMem8Wrapper.c99
-rw-r--r--MdePkg/Library/UefiMemoryLib/SetMem16Wrapper.c64
-rw-r--r--MdePkg/Library/UefiMemoryLib/SetMem32Wrapper.c64
-rw-r--r--MdePkg/Library/UefiMemoryLib/SetMem64Wrapper.c64
-rw-r--r--MdePkg/Library/UefiMemoryLib/SetMemWrapper.c91
-rw-r--r--MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf60
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-rw-r--r--MdePkg/Library/UefiMemoryLib/ZeroMemWrapper.c56
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1512 files changed, 191519 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c
new file mode 100644
index 000000000000..67a412e91fd3
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c
@@ -0,0 +1,247 @@
+/** @file
+ Cache Maintenance Functions. These functions vary by ARM architecture so the MdePkg
+ versions are null functions used to make sure things will compile.
+
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// Include common header file for this module.
+//
+#include <Base.h>
+#include <Library/DebugLib.h>
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+}
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, then no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+ ASSERT(FALSE);
+ return Address;
+}
+
+/**
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+}
+
+/**
+ Writes back and invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes back and invalidates the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, then no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+ ASSERT(FALSE);
+ return Address;
+}
+
+/**
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+}
+
+/**
+ Writes back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, then no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+ ASSERT(FALSE);
+ return Address;
+}
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+ ASSERT(FALSE);
+}
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, then no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+ ASSERT(FALSE);
+ return Address;
+}
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
new file mode 100644
index 000000000000..69418110f945
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -0,0 +1,61 @@
+## @file
+# Instance of Cache Maintenance Library using Base Library services.
+#
+# Cache Maintenance Library that uses Base Library services to maintain caches.
+# This library assumes there are no chipset dependencies required to maintain caches.
+#
+# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseCacheMaintenanceLib
+ MODULE_UNI_FILE = BaseCacheMaintenanceLib.uni
+ FILE_GUID = 123dd843-57c9-4158-8418-ce68b3944ce7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = CacheMaintenanceLib
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+#
+
+[Sources.IA32]
+ X86Cache.c
+
+[Sources.X64]
+ X86Cache.c
+
+[Sources.IPF]
+ IpfCache.c
+
+[Sources.EBC]
+ EbcCache.c
+
+[Sources.ARM]
+ ArmCache.c
+
+[Sources.AARCH64]
+ ArmCache.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+
+[LibraryClasses.Ipf]
+ PalLib
+
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.uni b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.uni
new file mode 100644
index 000000000000..9df91beec3fe
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.uni
@@ -0,0 +1,23 @@
+// /** @file
+// Instance of Cache Maintenance Library using Base Library services.
+//
+// Cache Maintenance Library that uses Base Library services to maintain caches.
+// This library assumes there are no chipset dependencies required to maintain caches.
+//
+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of Cache Maintenance Library using Base Library services"
+
+#string STR_MODULE_DESCRIPTION #language en-US "The Cache Maintenance Library that uses Base Library services to maintain caches. This library assumes there are no chipset dependencies required to maintain caches."
+
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c
new file mode 100644
index 000000000000..efbb03aa5cc6
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c
@@ -0,0 +1,231 @@
+/** @file
+ Cache Maintenance Functions.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+}
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, then no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+ return Address;
+}
+
+/**
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+}
+
+/**
+ Writes back and invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes Back and Invalidate the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, then no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address of cache invalidation.
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+ return Address;
+}
+
+/**
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+}
+
+/**
+ Writes back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, then no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address of cache written in main memory.
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+ return Address;
+}
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+}
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, then no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
+ return Address;
+}
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
new file mode 100644
index 000000000000..47153ac9a65f
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -0,0 +1,242 @@
+/** @file
+ Cache Maintenance Functions.
+
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PalLib.h>
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+ PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
+}
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, then no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ return AsmFlushCacheRange (Address, Length);
+}
+
+/**
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+ PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
+}
+
+/**
+ Writes back and invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes back and invalidates the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, then no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address of cache invalidation.
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ return AsmFlushCacheRange (Address, Length);
+}
+
+/**
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+ PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
+}
+
+/**
+ Writes Back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes Back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, then no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address of cache written in main memory.
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ return AsmFlushCacheRange (Address, Length);
+}
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+ //
+ // Invalidation of the entire data cache without writing back is not supported
+ // on IPF architecture, so a write back and invalidate operation is performed.
+ //
+ WriteBackInvalidateDataCache ();
+}
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, then no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ //
+ // Invalidation of a data cache range without writing back is not supported on
+ // IPF architecture, so write back and invalidate operation is performed.
+ //
+ return AsmFlushCacheRange (Address, Length);
+}
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c b/MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c
new file mode 100644
index 000000000000..66b839e72489
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c
@@ -0,0 +1,278 @@
+/** @file
+ Cache Maintenance Functions.
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+}
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, then no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ if (Length == 0) {
+ return Address;
+ }
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
+ return Address;
+}
+
+/**
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+ AsmWbinvd ();
+}
+
+/**
+ Writes back and invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes back and invalidates the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, then no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address of cache invalidation.
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ UINT32 RegEbx;
+ UINT32 RegEdx;
+ UINTN CacheLineSize;
+ UINTN Start;
+ UINTN End;
+
+ if (Length == 0) {
+ return Address;
+ }
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
+
+ //
+ // If the CPU does not support CLFLUSH instruction,
+ // then promote flush range to flush entire cache.
+ //
+ AsmCpuid (0x01, NULL, &RegEbx, NULL, &RegEdx);
+ if ((RegEdx & BIT19) == 0) {
+ AsmWbinvd ();
+ return Address;
+ }
+
+ //
+ // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H
+ //
+ CacheLineSize = (RegEbx & 0xff00) >> 5;
+
+ Start = (UINTN)Address;
+ //
+ // Calculate the cache line alignment
+ //
+ End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
+ Start &= ~((UINTN)CacheLineSize - 1);
+
+ do {
+ Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CacheLineSize;
+ } while (Start != End);
+ return Address;
+}
+
+/**
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+ WriteBackInvalidateDataCache ();
+}
+
+/**
+ Writes back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, then no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address of cache written in main memory.
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ return WriteBackInvalidateDataCacheRange (Address, Length);
+}
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+ AsmInvd ();
+}
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, then no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ //
+ // Invalidation of a data cache range without writing back is not supported on
+ // x86 architecture, so write back and invalidate operation is performed.
+ //
+ return WriteBackInvalidateDataCacheRange (Address, Length);
+}
diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S
new file mode 100644
index 000000000000..4b9a326f608f
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------
+#
+# CpuFlushTlb() for ARM
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuFlushTlb)
+
+#/**
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuFlushTlb (
+# VOID
+# )#
+#
+ASM_PFX(CpuFlushTlb):
+ tlbi vmalle1 // Invalidate Inst TLB and Data TLB
+ dsb sy
+ isb
+ ret
diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S
new file mode 100644
index 000000000000..b08bdfb8f39d
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# CpuSleep() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 3
+GCC_ASM_EXPORT(CpuSleep)
+
+#/**
+# Places the CPU in a sleep state until an interrupt is received.
+#
+# Places the CPU in a sleep state until an interrupt is received. If interrupts
+# are disabled prior to calling this function, then the CPU will be placed in a
+# sleep state indefinitely.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuSleep (
+# VOID
+# );
+#
+
+ASM_PFX(CpuSleep):
+ wfi
+ ret
diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S
new file mode 100644
index 000000000000..738f73356a3f
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# CpuFlushTlb() for ARM
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuFlushTlb)
+
+#/**
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuFlushTlb (
+# VOID
+# )#
+#
+ASM_PFX(CpuFlushTlb):
+ mov r0,#0
+ mcr p15,0,r0,c8,c5,0 // Invalidate all the unlocked entried in TLB
+ bx LR
diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm
new file mode 100644
index 000000000000..037d221a794d
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------
+;
+; CpuFlushTlb() for ARM
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuFlushTlb
+ AREA cpu_flush_tlb, CODE, READONLY
+
+;/**
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuFlushTlb (
+; VOID
+; );
+;
+CpuFlushTlb
+ MOV r0,#0
+ MCR p15,0,r0,c8,c5,0 ;Invalidate all the unlocked entried in TLB
+ BX LR
+
+ END
diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S
new file mode 100644
index 000000000000..b84c80862350
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------
+#
+# CpuSleep() for ARMv7
+#
+# ARMv6 versions was:
+# MOV r0,#0
+# MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
+#
+# But this is a no-op on ARMv7
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuSleep)
+
+#/**
+# Places the CPU in a sleep state until an interrupt is received.
+#
+# Places the CPU in a sleep state until an interrupt is received. If interrupts
+# are disabled prior to calling this function, then the CPU will be placed in a
+# sleep state indefinitely.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuSleep (
+# VOID
+# );
+#
+ASM_PFX(CpuSleep):
+ wfi
+ bx lr
diff --git a/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm
new file mode 100644
index 000000000000..399b80f720fb
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm
@@ -0,0 +1,44 @@
+;------------------------------------------------------------------------------
+;
+; CpuSleep() for ARMv7
+;
+; ARMv6 versions was:
+; MOV r0,#0
+; MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
+;
+; But this is a no-op on ARMv7
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2011, Apple Inc. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuSleep
+ AREA cpu_sleep, CODE, READONLY
+
+;/**
+; Places the CPU in a sleep state until an interrupt is received.
+;
+; Places the CPU in a sleep state until an interrupt is received. If interrupts
+; are disabled prior to calling this function, then the CPU will be placed in a
+; sleep state indefinitely.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuSleep (
+; VOID
+; );
+;
+CpuSleep
+ WFI
+ BX LR
+
+ END
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
new file mode 100644
index 000000000000..7237b8ff118e
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -0,0 +1,82 @@
+## @file
+# Instance of CPU Library for various architecture.
+#
+# CPU Library implemented using ASM functions for IA-32 and X64,
+# PAL CALLs for IPF, and empty functions for EBC.
+#
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseCpuLib
+ MODULE_UNI_FILE = BaseCpuLib.uni
+ FILE_GUID = 4FBD2538-249C-4b50-8F4A-A9E66609CBF6
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CpuLib
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+#
+
+[Sources.IA32]
+ Ia32/CpuSleep.c | MSFT
+ Ia32/CpuFlushTlb.c | MSFT
+
+ Ia32/CpuSleep.nasm| INTEL
+ Ia32/CpuSleep.asm | INTEL
+ Ia32/CpuFlushTlb.nasm| INTEL
+ Ia32/CpuFlushTlb.asm | INTEL
+
+ Ia32/CpuSleepGcc.c | GCC
+ Ia32/CpuFlushTlbGcc.c | GCC
+
+[Sources.X64]
+ X64/CpuFlushTlb.nasm
+ X64/CpuFlushTlb.asm
+ X64/CpuSleep.nasm
+ X64/CpuSleep.asm
+
+ X64/CpuSleep.nasm| GCC
+ X64/CpuSleep.S | GCC
+ X64/CpuFlushTlb.nasm| GCC
+ X64/CpuFlushTlb.S | GCC
+
+[Sources.IPF]
+ Ipf/CpuFlushTlb.s
+ Ipf/CpuSleep.c
+
+[Sources.EBC]
+ Ebc/CpuSleepFlushTlb.c
+
+[Sources.ARM]
+ Arm/CpuFlushTlb.asm | RVCT
+ Arm/CpuSleep.asm | RVCT
+ Arm/CpuFlushTlb.S | GCC
+ Arm/CpuSleep.S | GCC
+
+[Sources.AARCH64]
+ AArch64/CpuFlushTlb.S | GCC
+ AArch64/CpuSleep.S | GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+
+[LibraryClasses.IPF]
+ PalLib
+ BaseLib
+
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
new file mode 100644
index 000000000000..19510f427583
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
@@ -0,0 +1,24 @@
+// /** @file
+// Instance of CPU Library for various architecture.
+//
+// CPU Library implemented using ASM functions for IA-32 and X64,
+// PAL CALLs for IPF, and empty functions for EBC.
+//
+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
+
+#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty functions for EBC."
+
diff --git a/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c b/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c
new file mode 100644
index 000000000000..81ae029c59e4
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c
@@ -0,0 +1,46 @@
+/** @file
+ Base Library CPU Functions for EBC
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+}
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.asm b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.asm
new file mode 100644
index 000000000000..2b54d35a6ffc
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.asm
@@ -0,0 +1,40 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuFlushTlb.Asm
+;
+; Abstract:
+;
+; CpuFlushTlb function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ .386p
+ .model flat,C
+ .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuFlushTlb (
+; VOID
+; );
+;------------------------------------------------------------------------------
+CpuFlushTlb PROC
+ mov eax, cr3
+ mov cr3, eax ; moving to CR3 flushes TLB
+ ret
+CpuFlushTlb ENDP
+
+ END
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c
new file mode 100644
index 000000000000..25b16c52f632
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c
@@ -0,0 +1,34 @@
+/** @file
+ CpuFlushTlb function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ )
+{
+ _asm {
+ mov eax, cr3
+ mov cr3, eax
+ }
+}
+
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm
new file mode 100644
index 000000000000..aa343459f3f2
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuFlushTlb.Asm
+;
+; Abstract:
+;
+; CpuFlushTlb function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuFlushTlb (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuFlushTlb)
+ASM_PFX(CpuFlushTlb):
+ mov eax, cr3
+ mov cr3, eax ; moving to CR3 flushes TLB
+ ret
+
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c
new file mode 100644
index 000000000000..4cff85122f9c
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c
@@ -0,0 +1,32 @@
+/** @file
+ CpuFlushTlb function for Ia32/X64 GCC.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseLib.h>
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ )
+{
+ AsmWriteCr3 (AsmReadCr3 ());
+}
+
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.asm b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.asm
new file mode 100644
index 000000000000..592d36d377e4
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.asm
@@ -0,0 +1,39 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuSleep.Asm
+;
+; Abstract:
+;
+; CpuSleep function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ .386
+ .model flat,C
+ .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuSleep (
+; VOID
+; );
+;------------------------------------------------------------------------------
+CpuSleep PROC
+ hlt
+ ret
+CpuSleep ENDP
+
+ END
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c
new file mode 100644
index 000000000000..40b0453967d6
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c
@@ -0,0 +1,34 @@
+/** @file
+ CpuSleep function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+ _asm {
+ hlt
+ }
+}
+
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm
new file mode 100644
index 000000000000..c808f9630170
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm
@@ -0,0 +1,36 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuSleep.Asm
+;
+; Abstract:
+;
+; CpuSleep function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuSleep (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuSleep)
+ASM_PFX(CpuSleep):
+ hlt
+ ret
+
diff --git a/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c
new file mode 100644
index 000000000000..b61a61fcc9ae
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c
@@ -0,0 +1,33 @@
+/** @file
+ CpuSleep function for Ia32/X64 GCC.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("hlt"::: "memory");
+}
+
diff --git a/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s b/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
new file mode 100644
index 000000000000..e0d40163181e
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
@@ -0,0 +1,58 @@
+/// @file
+/// CpuFlushTlb() function for Itanium-based architecture.
+///
+/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+/// This program and the accompanying materials
+/// are licensed and made available under the terms and conditions of the BSD License
+/// which accompanies this distribution. The full text of the license may be found at
+/// http://opensource.org/licenses/bsd-license.php.
+///
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+///
+/// Module Name: CpuFlushTlb.s
+///
+///
+
+.auto
+.text
+
+ASM_GLOBAL PalCall
+.type PalCall, @function
+
+.proc CpuFlushTlb
+.type CpuFlushTlb, @function
+CpuFlushTlb::
+ alloc loc0 = ar.pfs, 0, 3, 5, 0
+ mov out0 = 0
+ mov out1 = 6
+ mov out2 = 0
+ mov out3 = 0
+ mov loc1 = b0
+ mov out4 = 0
+ brl.call.sptk b0 = PalCall
+ mov loc2 = psr // save PSR
+ mov ar.pfs = loc0
+ extr.u r14 = r10, 32, 32 // r14 <- count1
+ rsm 1 << 14 // Disable interrupts
+ extr.u r15 = r11, 32, 32 // r15 <- stride1
+ extr.u r10 = r10, 0, 32 // r10 <- count2
+ add r10 = -1, r10
+ extr.u r11 = r11, 0, 32 // r11 <- stride2
+ br.cond.sptk LoopPredicate
+LoopOuter:
+ mov ar.lc = r10 // LC <- count2
+ mov ar.ec = r0 // EC <- 0
+Loop:
+ ptc.e r9
+ add r9 = r11, r9 // r9 += stride2
+ br.ctop.sptk Loop
+ add r9 = r15, r9 // r9 += stride1
+LoopPredicate:
+ cmp.ne p6 = r0, r14 // count1 == 0?
+ add r14 = -1, r14
+(p6) br.cond.sptk LoopOuter
+ mov psr.l = loc2
+ mov b0 = loc1
+ br.ret.sptk.many b0
+.endp
diff --git a/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c b/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
new file mode 100644
index 000000000000..86d2c184772b
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
@@ -0,0 +1,66 @@
+/** @file
+ Base Library CPU functions for Itanium
+
+ Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PalLib.h>
+#include <Library/BaseLib.h>
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+ UINT64 Tpr;
+
+ //
+ // It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state
+ // back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.
+ // So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts.
+ // If interrupts are enabled, then just use current TRP setting.
+ //
+ if (GetInterruptState ()) {
+ //
+ // If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting.
+ //
+ PalCall (PAL_HALT_LIGHT, 0, 0, 0);
+ } else {
+ //
+ // If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT.
+ //
+
+ //
+ // Save TPR
+ //
+ Tpr = AsmReadTpr();
+ //
+ // Set TPR.mmi to mask all external interrupts
+ //
+ AsmWriteTpr (BIT16 | Tpr);
+
+ PalCall (PAL_HALT_LIGHT, 0, 0, 0);
+
+ //
+ // Restore TPR
+ //
+ AsmWriteTpr (Tpr);
+ }
+}
diff --git a/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.S b/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.S
new file mode 100644
index 000000000000..7820f5a0e334
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.S
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+# CpuFlushTlb.Asm
+#
+# Abstract:
+#
+# CpuFlushTlb function
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(CpuFlushTlb)
+
+#------------------------------------------------------------------------------
+# VOID
+# EFIAPI
+# CpuFlushTlb (
+# VOID
+# );
+#------------------------------------------------------------------------------
+ASM_PFX(CpuFlushTlb):
+ mov %cr3, %rax
+ mov %rax, %cr3
+ ret
diff --git a/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.asm b/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.asm
new file mode 100644
index 000000000000..9df888210381
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.asm
@@ -0,0 +1,38 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuFlushTlb.Asm
+;
+; Abstract:
+;
+; CpuFlushTlb function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuFlushTlb (
+; VOID
+; );
+;------------------------------------------------------------------------------
+CpuFlushTlb PROC
+ mov rax, cr3
+ mov cr3, rax
+ ret
+CpuFlushTlb ENDP
+
+ END
diff --git a/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.nasm b/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.nasm
new file mode 100644
index 000000000000..cdcbbca4ddb1
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.nasm
@@ -0,0 +1,38 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuFlushTlb.Asm
+;
+; Abstract:
+;
+; CpuFlushTlb function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuFlushTlb (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuFlushTlb)
+ASM_PFX(CpuFlushTlb):
+ mov rax, cr3
+ mov cr3, rax
+ ret
+
diff --git a/MdePkg/Library/BaseCpuLib/X64/CpuSleep.S b/MdePkg/Library/BaseCpuLib/X64/CpuSleep.S
new file mode 100644
index 000000000000..44d58e912cc5
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/X64/CpuSleep.S
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------ ;
+# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+# CpuSleep.S
+#
+# Abstract:
+#
+# CpuSleep function
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+
+#------------------------------------------------------------------------------
+# VOID
+# EFIAPI
+# CpuSleep (
+# VOID
+# );
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(CpuSleep)
+ASM_PFX(CpuSleep):
+ hlt
+ ret
diff --git a/MdePkg/Library/BaseCpuLib/X64/CpuSleep.asm b/MdePkg/Library/BaseCpuLib/X64/CpuSleep.asm
new file mode 100644
index 000000000000..a0448b776641
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/X64/CpuSleep.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuSleep.Asm
+;
+; Abstract:
+;
+; CpuSleep function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuSleep (
+; VOID
+; );
+;------------------------------------------------------------------------------
+CpuSleep PROC
+ hlt
+ ret
+CpuSleep ENDP
+
+ END
diff --git a/MdePkg/Library/BaseCpuLib/X64/CpuSleep.nasm b/MdePkg/Library/BaseCpuLib/X64/CpuSleep.nasm
new file mode 100644
index 000000000000..0deed7f224e1
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/X64/CpuSleep.nasm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuSleep.Asm
+;
+; Abstract:
+;
+; CpuSleep function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuSleep (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuSleep)
+ASM_PFX(CpuSleep):
+ hlt
+ ret
+
diff --git a/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf b/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
new file mode 100644
index 000000000000..5bb0a7808652
--- /dev/null
+++ b/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
@@ -0,0 +1,36 @@
+## @file
+# Debug Library with empty functions.
+#
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseDebugLibNull
+ MODULE_UNI_FILE = BaseDebugLibNull.uni
+ FILE_GUID = 9ba1d976-0624-41a3-8650-28165e8d9ae8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = DebugLib
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ DebugLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+
diff --git a/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.uni b/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.uni
new file mode 100644
index 000000000000..3cf6a75b3161
--- /dev/null
+++ b/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.uni
@@ -0,0 +1,21 @@
+// /** @file
+// Debug Library with empty functions.
+//
+// Debug Library with empty functions.
+//
+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Debug Library with empty functions"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Debug Library with empty functions."
+
diff --git a/MdePkg/Library/BaseDebugLibNull/DebugLib.c b/MdePkg/Library/BaseDebugLibNull/DebugLib.c
new file mode 100644
index 000000000000..f3fa4aa84fc4
--- /dev/null
+++ b/MdePkg/Library/BaseDebugLibNull/DebugLib.c
@@ -0,0 +1,198 @@
+/** @file
+ Null Base Debug Library instance with empty functions.
+
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+
+/**
+ Prints a debug message to the debug output device if the specified error level is enabled.
+
+ If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
+ GetDebugPrintErrorLevel (), then print the message specified by Format and the
+ associated variable argument list to the debug output device.
+
+ If Format is NULL, then ASSERT().
+
+ @param ErrorLevel The error level of the debug message.
+ @param Format Format string for the debug message to print.
+ @param ... Variable argument list whose contents are accessed
+ based on the format string specified by Format.
+
+**/
+VOID
+EFIAPI
+DebugPrint (
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ ...
+ )
+{
+}
+
+
+/**
+ Prints an assert message containing a filename, line number, and description.
+ This may be followed by a breakpoint or a dead loop.
+
+ Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
+ to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
+ PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
+ CpuDeadLoop() is called. If neither of these bits are set, then this function
+ returns immediately after the message is printed to the debug output device.
+ DebugAssert() must actively prevent recursion. If DebugAssert() is called while
+ processing another DebugAssert(), then DebugAssert() must return immediately.
+
+ If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.
+ If Description is NULL, then a <Description> string of "(NULL) Description" is printed.
+
+ @param FileName The pointer to the name of the source file that generated the assert condition.
+ @param LineNumber The line number in the source file that generated the assert condition
+ @param Description The pointer to the description of the assert condition.
+
+**/
+VOID
+EFIAPI
+DebugAssert (
+ IN CONST CHAR8 *FileName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *Description
+ )
+{
+}
+
+
+/**
+ Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with the value specified by
+ PcdDebugClearMemoryValue, and returns Buffer.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to be filled with PcdDebugClearMemoryValue.
+ @param Length The number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
+
+ @return Buffer The pointer to the target buffer filled with PcdDebugClearMemoryValue.
+
+**/
+VOID *
+EFIAPI
+DebugClearMemory (
+ OUT VOID *Buffer,
+ IN UINTN Length
+ )
+{
+ return Buffer;
+}
+
+
+/**
+ Returns TRUE if ASSERT() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugAssertEnabled (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+
+/**
+ Returns TRUE if DEBUG() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugPrintEnabled (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+
+/**
+ Returns TRUE if DEBUG_CODE() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugCodeEnabled (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+
+/**
+ Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugClearMemoryEnabled (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Returns TRUE if any one of the bit is set both in ErrorLevel and PcdFixedDebugPrintErrorLevel.
+
+ This function compares the bit mask of ErrorLevel and PcdFixedDebugPrintErrorLevel.
+
+ @retval TRUE Current ErrorLevel is supported.
+ @retval FALSE Current ErrorLevel is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+DebugPrintLevelEnabled (
+ IN CONST UINTN ErrorLevel
+ )
+{
+ return FALSE;
+}
+
diff --git a/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf b/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
new file mode 100644
index 000000000000..7d588a0da870
--- /dev/null
+++ b/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
@@ -0,0 +1,49 @@
+## @file
+# Instance of Debug Library based on Serial Port Library.
+# It uses Print Library to produce formatted output strings to seiral port device.
+#
+# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseDebugLibSerialPort
+ MODULE_UNI_FILE = BaseDebugLibSerialPort.uni
+ FILE_GUID = BB83F95F-EDBC-4884-A520-CD42AF388FAE
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = DebugLib
+ CONSTRUCTOR = BaseDebugLibSerialPortConstructor
+
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ DebugLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ SerialPortLib
+ BaseMemoryLib
+ PcdLib
+ PrintLib
+ BaseLib
+ DebugPrintErrorLevelLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue ## SOMETIMES_CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel ## CONSUMES
+
diff --git a/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.uni b/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.uni
new file mode 100644
index 000000000000..4b902078ca2f
--- /dev/null
+++ b/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.uni
@@ -0,0 +1,21 @@
+// /** @file
+// Instance of Debug Library based on Serial Port Library.
+//
+// It uses Print Library to produce formatted output strings to seiral port device.
+//
+// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of Debug Library based on Serial Port Library"
+
+#string STR_MODULE_DESCRIPTION #language en-US "It uses Print Library to produce formatted output strings to a serial port device."
+
diff --git a/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c b/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
new file mode 100644
index 000000000000..1bef983c908d
--- /dev/null
+++ b/MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
@@ -0,0 +1,284 @@
+/** @file
+ Base Debug library instance base on Serial Port library.
+ It uses PrintLib to send debug messages to serial port device.
+
+ NOTE: If the Serial Port library enables hardware flow control, then a call
+ to DebugPrint() or DebugAssert() may hang if writes to the serial port are
+ being blocked. This may occur if a key(s) are pressed in a terminal emulator
+ used to monitor the DEBUG() and ASSERT() messages.
+
+ Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+
+//
+// Define the maximum debug and assert message length that this library supports
+//
+#define MAX_DEBUG_MESSAGE_LENGTH 0x100
+
+/**
+ The constructor function initialize the Serial Port Library
+
+ @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
+
+**/
+RETURN_STATUS
+EFIAPI
+BaseDebugLibSerialPortConstructor (
+ VOID
+ )
+{
+ return SerialPortInitialize ();
+}
+
+/**
+ Prints a debug message to the debug output device if the specified error level is enabled.
+
+ If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
+ GetDebugPrintErrorLevel (), then print the message specified by Format and the
+ associated variable argument list to the debug output device.
+
+ If Format is NULL, then ASSERT().
+
+ @param ErrorLevel The error level of the debug message.
+ @param Format Format string for the debug message to print.
+ @param ... Variable argument list whose contents are accessed
+ based on the format string specified by Format.
+
+**/
+VOID
+EFIAPI
+DebugPrint (
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ ...
+ )
+{
+ CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
+ VA_LIST Marker;
+
+ //
+ // If Format is NULL, then ASSERT().
+ //
+ ASSERT (Format != NULL);
+
+ //
+ // Check driver debug mask value and global mask
+ //
+ if ((ErrorLevel & GetDebugPrintErrorLevel ()) == 0) {
+ return;
+ }
+
+ //
+ // Convert the DEBUG() message to an ASCII String
+ //
+ VA_START (Marker, Format);
+ AsciiVSPrint (Buffer, sizeof (Buffer), Format, Marker);
+ VA_END (Marker);
+
+ //
+ // Send the print string to a Serial Port
+ //
+ SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));
+}
+
+
+/**
+ Prints an assert message containing a filename, line number, and description.
+ This may be followed by a breakpoint or a dead loop.
+
+ Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
+ to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
+ PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
+ CpuDeadLoop() is called. If neither of these bits are set, then this function
+ returns immediately after the message is printed to the debug output device.
+ DebugAssert() must actively prevent recursion. If DebugAssert() is called while
+ processing another DebugAssert(), then DebugAssert() must return immediately.
+
+ If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.
+ If Description is NULL, then a <Description> string of "(NULL) Description" is printed.
+
+ @param FileName The pointer to the name of the source file that generated the assert condition.
+ @param LineNumber The line number in the source file that generated the assert condition
+ @param Description The pointer to the description of the assert condition.
+
+**/
+VOID
+EFIAPI
+DebugAssert (
+ IN CONST CHAR8 *FileName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *Description
+ )
+{
+ CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
+
+ //
+ // Generate the ASSERT() message in Ascii format
+ //
+ AsciiSPrint (Buffer, sizeof (Buffer), "ASSERT [%a] %a(%d): %a\n", gEfiCallerBaseName, FileName, LineNumber, Description);
+
+ //
+ // Send the print string to the Console Output device
+ //
+ SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));
+
+ //
+ // Generate a Breakpoint, DeadLoop, or NOP based on PCD settings
+ //
+ if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
+ CpuBreakpoint ();
+ } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
+ CpuDeadLoop ();
+ }
+}
+
+
+/**
+ Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with the value specified by
+ PcdDebugClearMemoryValue, and returns Buffer.
+
+ If Buffer is NULL, then ASSERT().
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+ @param Buffer The pointer to the target buffer to be filled with PcdDebugClearMemoryValue.
+ @param Length The number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
+
+ @return Buffer The pointer to the target buffer filled with PcdDebugClearMemoryValue.
+
+**/
+VOID *
+EFIAPI
+DebugClearMemory (
+ OUT VOID *Buffer,
+ IN UINTN Length
+ )
+{
+ //
+ // If Buffer is NULL, then ASSERT().
+ //
+ ASSERT (Buffer != NULL);
+
+ //
+ // SetMem() checks for the the ASSERT() condition on Length and returns Buffer
+ //
+ return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));
+}
+
+
+/**
+ Returns TRUE if ASSERT() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugAssertEnabled (
+ VOID
+ )
+{
+ return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
+}
+
+
+/**
+ Returns TRUE if DEBUG() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugPrintEnabled (
+ VOID
+ )
+{
+ return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
+}
+
+
+/**
+ Returns TRUE if DEBUG_CODE() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugCodeEnabled (
+ VOID
+ )
+{
+ return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
+}
+
+
+/**
+ Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugClearMemoryEnabled (
+ VOID
+ )
+{
+ return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
+}
+
+/**
+ Returns TRUE if any one of the bit is set both in ErrorLevel and PcdFixedDebugPrintErrorLevel.
+
+ This function compares the bit mask of ErrorLevel and PcdFixedDebugPrintErrorLevel.
+
+ @retval TRUE Current ErrorLevel is supported.
+ @retval FALSE Current ErrorLevel is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+DebugPrintLevelEnabled (
+ IN CONST UINTN ErrorLevel
+ )
+{
+ return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);
+}
+
diff --git a/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.c b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.c
new file mode 100644
index 000000000000..3e159e5caf4f
--- /dev/null
+++ b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.c
@@ -0,0 +1,59 @@
+/** @file
+ Debug Print Error Level library instance that retrieves the current error
+ level from PcdDebugPrintErrorLevel. This generic library instance does not
+ support the setting of the global debug print error level mask for the platform.
+
+ Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PcdLib.h>
+
+/**
+ Returns the debug print error level mask for the current module.
+
+ @return Debug print error level mask for the current module.
+
+**/
+UINT32
+EFIAPI
+GetDebugPrintErrorLevel (
+ VOID
+ )
+{
+ //
+ // Retrieve the current debug print error level mask from PcdDebugPrintErrorLevel.
+ //
+ return PcdGet32 (PcdDebugPrintErrorLevel);
+}
+
+/**
+ Sets the global debug print error level mask fpr the entire platform.
+
+ @param ErrorLevel Global debug print error level.
+
+ @retval TRUE The debug print error level mask was sucessfully set.
+ @retval FALSE The debug print error level mask could not be set.
+
+**/
+BOOLEAN
+EFIAPI
+SetDebugPrintErrorLevel (
+ UINT32 ErrorLevel
+ )
+{
+ //
+ // This library uinstance does not support setting the global debug print error
+ // level mask.
+ //
+ return FALSE;
+}
diff --git a/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
new file mode 100644
index 000000000000..f92edc20ee8a
--- /dev/null
+++ b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
@@ -0,0 +1,40 @@
+## @file
+# Debug Print Error Level library instance based on PcdDebugPrintErrorLevel.
+# It retrieves the current error level from PcdDebugPrintErrorLevel.
+#
+# Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseDebugPrintErrorLevelLib
+ MODULE_UNI_FILE = BaseDebugPrintErrorLevelLib.uni
+ FILE_GUID = A2C09E18-E4D2-407e-AFCC-628B79113F72
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = DebugPrintErrorLevelLib
+
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ BaseDebugPrintErrorLevelLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PcdLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel ## CONSUMES
+
diff --git a/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.uni b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.uni
new file mode 100644
index 000000000000..2b306d377f47
--- /dev/null
+++ b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.uni
@@ -0,0 +1,21 @@
+// /** @file
+// Debug Print Error Level library instance based on PcdDebugPrintErrorLevel.
+//
+// It retrieves the current error level from PcdDebugPrintErrorLevel.
+//
+// Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Debug Print Error Level library instance based on PcdDebugPrintErrorLevel"
+
+#string STR_MODULE_DESCRIPTION #language en-US "It retrieves the current error level from PcdDebugPrintErrorLevel."
+
diff --git a/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.c b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.c
new file mode 100644
index 000000000000..ddd464532046
--- /dev/null
+++ b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.c
@@ -0,0 +1,484 @@
+/** @file
+ Provide generic extract guided section functions.
+
+ Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ExtractGuidedSectionLib.h>
+
+#define EXTRACT_HANDLER_INFO_SIGNATURE SIGNATURE_32 ('E', 'G', 'S', 'I')
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 NumberOfExtractHandler;
+ GUID *ExtractHandlerGuidTable;
+ EXTRACT_GUIDED_SECTION_DECODE_HANDLER *ExtractDecodeHandlerTable;
+ EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *ExtractGetInfoHandlerTable;
+} EXTRACT_GUIDED_SECTION_HANDLER_INFO;
+
+/**
+ HandlerInfo table address is set by PcdGuidedExtractHandlerTableAddress, which is used to store
+ the registered guid and Handler list. When it is initialized, it will be directly returned.
+ Or, HandlerInfo table will be initialized in this function.
+
+ @param[in, out] InfoPointer The pointer to the handler information structure.
+
+ @retval RETURN_SUCCESS HandlerInfo table can be used to store guid and function tables.
+ @retval RETURN_OUT_OF_RESOURCES HandlerInfo table address is not writable.
+**/
+RETURN_STATUS
+GetExtractGuidedSectionHandlerInfo (
+ IN OUT EXTRACT_GUIDED_SECTION_HANDLER_INFO **InfoPointer
+ )
+{
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;
+
+ //
+ // Set the available memory address to handler info.
+ //
+ HandlerInfo = (EXTRACT_GUIDED_SECTION_HANDLER_INFO*)(VOID*)(UINTN) PcdGet64 (PcdGuidedExtractHandlerTableAddress);
+ if (HandlerInfo == NULL) {
+ *InfoPointer = NULL;
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // First check whether the handler information structure is initialized.
+ //
+ if (HandlerInfo->Signature == EXTRACT_HANDLER_INFO_SIGNATURE) {
+ //
+ // The handler information has been initialized and is returned.
+ //
+ *InfoPointer = HandlerInfo;
+ return RETURN_SUCCESS;
+ }
+
+ //
+ // Try to initialize the handler information structure
+ //
+ HandlerInfo->Signature = EXTRACT_HANDLER_INFO_SIGNATURE;
+ if (HandlerInfo->Signature != EXTRACT_HANDLER_INFO_SIGNATURE) {
+ //
+ // The handler information structure was not writeable because the memory is not ready.
+ //
+ *InfoPointer = NULL;
+ return RETURN_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Init HandlerInfo structure
+ //
+ HandlerInfo->NumberOfExtractHandler = 0;
+ HandlerInfo->ExtractHandlerGuidTable = (GUID *) (HandlerInfo + 1);
+ HandlerInfo->ExtractDecodeHandlerTable = (EXTRACT_GUIDED_SECTION_DECODE_HANDLER *) (
+ (UINT8 *)HandlerInfo->ExtractHandlerGuidTable +
+ PcdGet32 (PcdMaximumGuidedExtractHandler) * sizeof (GUID)
+ );
+ HandlerInfo->ExtractGetInfoHandlerTable = (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *) (
+ (UINT8 *)HandlerInfo->ExtractDecodeHandlerTable +
+ PcdGet32 (PcdMaximumGuidedExtractHandler) *
+ sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER)
+ );
+ *InfoPointer = HandlerInfo;
+ return RETURN_SUCCESS;
+}
+
+/**
+ Retrieve the list GUIDs that have been registered through ExtractGuidedSectionRegisterHandlers().
+
+ Sets ExtractHandlerGuidTable so it points at a callee allocated array of registered GUIDs.
+ The total number of GUIDs in the array are returned. Since the array of GUIDs is callee allocated
+ and caller must treat this array of GUIDs as read-only data.
+ If ExtractHandlerGuidTable is NULL, then ASSERT().
+
+ @param[out] ExtractHandlerGuidTable A pointer to the array of GUIDs that have been registered through
+ ExtractGuidedSectionRegisterHandlers().
+
+ @return The number of the supported extract guided Handler.
+
+**/
+UINTN
+EFIAPI
+ExtractGuidedSectionGetGuidList (
+ OUT GUID **ExtractHandlerGuidTable
+ )
+{
+ RETURN_STATUS Status;
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;
+
+ ASSERT (ExtractHandlerGuidTable != NULL);
+
+ //
+ // Get all registered handler information
+ //
+ Status = GetExtractGuidedSectionHandlerInfo (&HandlerInfo);
+ if (RETURN_ERROR (Status)) {
+ *ExtractHandlerGuidTable = NULL;
+ return 0;
+ }
+
+ //
+ // Get GuidTable and Table Number
+ //
+ ASSERT (HandlerInfo != NULL);
+ *ExtractHandlerGuidTable = HandlerInfo->ExtractHandlerGuidTable;
+ return HandlerInfo->NumberOfExtractHandler;
+}
+
+/**
+ Registers handlers of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER and EXTRACT_GUIDED_SECTION_DECODE_HANDLER
+ for a specific GUID section type.
+
+ Registers the handlers specified by GetInfoHandler and DecodeHandler with the GUID specified by SectionGuid.
+ If the GUID value specified by SectionGuid has already been registered, then return RETURN_ALREADY_STARTED.
+ If there are not enough resources available to register the handlers then RETURN_OUT_OF_RESOURCES is returned.
+
+ If SectionGuid is NULL, then ASSERT().
+ If GetInfoHandler is NULL, then ASSERT().
+ If DecodeHandler is NULL, then ASSERT().
+
+ @param[in] SectionGuid A pointer to the GUID associated with the the handlers
+ of the GUIDed section type being registered.
+ @param[in] GetInfoHandler The pointer to a function that examines a GUIDed section and returns the
+ size of the decoded buffer and the size of an optional scratch buffer
+ required to actually decode the data in a GUIDed section.
+ @param[in] DecodeHandler The pointer to a function that decodes a GUIDed section into a caller
+ allocated output buffer.
+
+ @retval RETURN_SUCCESS The handlers were registered.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to register the handlers.
+
+**/
+RETURN_STATUS
+EFIAPI
+ExtractGuidedSectionRegisterHandlers (
+ IN CONST GUID *SectionGuid,
+ IN EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER GetInfoHandler,
+ IN EXTRACT_GUIDED_SECTION_DECODE_HANDLER DecodeHandler
+ )
+{
+ UINT32 Index;
+ RETURN_STATUS Status;
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;
+
+ //
+ // Check input parameter
+ //
+ ASSERT (SectionGuid != NULL);
+ ASSERT (GetInfoHandler != NULL);
+ ASSERT (DecodeHandler != NULL);
+
+ //
+ // Get the registered handler information
+ //
+ Status = GetExtractGuidedSectionHandlerInfo (&HandlerInfo);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Search the match registered GetInfo handler for the input guided section.
+ //
+ ASSERT (HandlerInfo != NULL);
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {
+ if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionGuid)) {
+ //
+ // If the guided handler has been registered before, only update its handler.
+ //
+ HandlerInfo->ExtractDecodeHandlerTable [Index] = DecodeHandler;
+ HandlerInfo->ExtractGetInfoHandlerTable [Index] = GetInfoHandler;
+ return RETURN_SUCCESS;
+ }
+ }
+
+ //
+ // Check the global table is enough to contain new Handler.
+ //
+ if (HandlerInfo->NumberOfExtractHandler >= PcdGet32 (PcdMaximumGuidedExtractHandler)) {
+ return RETURN_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Register new Handler and guid value.
+ //
+ CopyGuid (HandlerInfo->ExtractHandlerGuidTable + HandlerInfo->NumberOfExtractHandler, SectionGuid);
+ HandlerInfo->ExtractDecodeHandlerTable [HandlerInfo->NumberOfExtractHandler] = DecodeHandler;
+ HandlerInfo->ExtractGetInfoHandlerTable [HandlerInfo->NumberOfExtractHandler++] = GetInfoHandler;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Retrieves a GUID from a GUIDed section and uses that GUID to select an associated handler of type
+ EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers().
+ The selected handler is used to retrieve and return the size of the decoded buffer and the size of an
+ optional scratch buffer required to actually decode the data in a GUIDed section.
+
+ Examines a GUIDed section specified by InputSection.
+ If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(),
+ then RETURN_UNSUPPORTED is returned.
+ If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler
+ of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers()
+ is used to retrieve the OututBufferSize, ScratchSize, and Attributes values. The return status from the handler of
+ type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER is returned.
+
+ If InputSection is NULL, then ASSERT().
+ If OutputBufferSize is NULL, then ASSERT().
+ If ScratchBufferSize is NULL, then ASSERT().
+ If SectionAttribute is NULL, then ASSERT().
+
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.
+ @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required if the buffer
+ specified by InputSection were decoded.
+ @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space if the buffer specified by
+ InputSection were decoded.
+ @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes field of
+ EFI_GUID_DEFINED_SECTION in the PI Specification.
+
+ @retval RETURN_SUCCESS Successfully retrieved the required information.
+ @retval RETURN_UNSUPPORTED The GUID from the section specified by InputSection does not match any of
+ the GUIDs registered with ExtractGuidedSectionRegisterHandlers().
+ @retval Others The return status from the handler associated with the GUID retrieved from
+ the section specified by InputSection.
+
+**/
+RETURN_STATUS
+EFIAPI
+ExtractGuidedSectionGetInfo (
+ IN CONST VOID *InputSection,
+ OUT UINT32 *OutputBufferSize,
+ OUT UINT32 *ScratchBufferSize,
+ OUT UINT16 *SectionAttribute
+ )
+{
+ UINT32 Index;
+ RETURN_STATUS Status;
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;
+ EFI_GUID *SectionDefinitionGuid;
+
+ //
+ // Check input parameter
+ //
+ ASSERT (InputSection != NULL);
+ ASSERT (OutputBufferSize != NULL);
+ ASSERT (ScratchBufferSize != NULL);
+ ASSERT (SectionAttribute != NULL);
+
+ //
+ // Get all registered handler information.
+ //
+ Status = GetExtractGuidedSectionHandlerInfo (&HandlerInfo);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ if (IS_SECTION2 (InputSection)) {
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid);
+ } else {
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid);
+ }
+
+ //
+ // Search the match registered GetInfo handler for the input guided section.
+ //
+ ASSERT (HandlerInfo != NULL);
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {
+ if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionDefinitionGuid)) {
+ //
+ // Call the match handler to get information for the input section data.
+ //
+ return HandlerInfo->ExtractGetInfoHandlerTable [Index] (
+ InputSection,
+ OutputBufferSize,
+ ScratchBufferSize,
+ SectionAttribute
+ );
+ }
+ }
+
+ //
+ // Not found, the input guided section is not supported.
+ //
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Retrieves the GUID from a GUIDed section and uses that GUID to select an associated handler of type
+ EXTRACT_GUIDED_SECTION_DECODE_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers().
+ The selected handler is used to decode the data in a GUIDed section and return the result in a caller
+ allocated output buffer.
+
+ Decodes the GUIDed section specified by InputSection.
+ If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(),
+ then RETURN_UNSUPPORTED is returned.
+ If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler
+ of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers()
+ is used to decode InputSection into the buffer specified by OutputBuffer and the authentication status of this
+ decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the data in InputSection,
+ then OutputBuffer is set to point at the data in InputSection. Otherwise, the decoded data will be placed in a caller
+ allocated buffer specified by OutputBuffer. This function is responsible for computing the EFI_AUTH_STATUS_PLATFORM_OVERRIDE
+ bit of in AuthenticationStatus. The return status from the handler of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER is returned.
+
+ If InputSection is NULL, then ASSERT().
+ If OutputBuffer is NULL, then ASSERT().
+ If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().
+ If AuthenticationStatus is NULL, then ASSERT().
+
+ @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file.
+ @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation.
+ @param[in] ScratchBuffer A caller allocated buffer that may be required by this function as a scratch buffer to perform the decode operation.
+ @param[out] AuthenticationStatus
+ A pointer to the authentication status of the decoded output buffer. See the definition
+ of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI section of the PI
+ Specification.
+
+ @retval RETURN_SUCCESS The buffer specified by InputSection was decoded.
+ @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports.
+ @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded.
+
+**/
+RETURN_STATUS
+EFIAPI
+ExtractGuidedSectionDecode (
+ IN CONST VOID *InputSection,
+ OUT VOID **OutputBuffer,
+ IN VOID *ScratchBuffer, OPTIONAL
+ OUT UINT32 *AuthenticationStatus
+ )
+{
+ UINT32 Index;
+ RETURN_STATUS Status;
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;
+ EFI_GUID *SectionDefinitionGuid;
+
+ //
+ // Check input parameter
+ //
+ ASSERT (InputSection != NULL);
+ ASSERT (OutputBuffer != NULL);
+ ASSERT (AuthenticationStatus != NULL);
+
+ //
+ // Get all registered handler information.
+ //
+ Status = GetExtractGuidedSectionHandlerInfo (&HandlerInfo);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ if (IS_SECTION2 (InputSection)) {
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid);
+ } else {
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid);
+ }
+
+ //
+ // Search the match registered Extract handler for the input guided section.
+ //
+ ASSERT (HandlerInfo != NULL);
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {
+ if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionDefinitionGuid)) {
+ //
+ // Call the match handler to extract raw data for the input guided section.
+ //
+ return HandlerInfo->ExtractDecodeHandlerTable [Index] (
+ InputSection,
+ OutputBuffer,
+ ScratchBuffer,
+ AuthenticationStatus
+ );
+ }
+ }
+
+ //
+ // Not found, the input guided section is not supported.
+ //
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Retrieves handlers of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER and
+ EXTRACT_GUIDED_SECTION_DECODE_HANDLER for a specific GUID section type.
+
+ Retrieves the handlers associated with SectionGuid and returns them in
+ GetInfoHandler and DecodeHandler.
+
+ If the GUID value specified by SectionGuid has not been registered, then
+ return RETURN_NOT_FOUND.
+
+ If SectionGuid is NULL, then ASSERT().
+
+ @param[in] SectionGuid A pointer to the GUID associated with the handlersof the GUIDed
+ section type being retrieved.
+ @param[out] GetInfoHandler Pointer to a function that examines a GUIDed section and returns
+ the size of the decoded buffer and the size of an optional scratch
+ buffer required to actually decode the data in a GUIDed section.
+ This is an optional parameter that may be NULL. If it is NULL, then
+ the previously registered handler is not returned.
+ @param[out] DecodeHandler Pointer to a function that decodes a GUIDed section into a caller
+ allocated output buffer. This is an optional parameter that may be NULL.
+ If it is NULL, then the previously registered handler is not returned.
+
+ @retval RETURN_SUCCESS The handlers were retrieved.
+ @retval RETURN_NOT_FOUND No handlers have been registered with the specified GUID.
+
+**/
+RETURN_STATUS
+EFIAPI
+ExtractGuidedSectionGetHandlers (
+ IN CONST GUID *SectionGuid,
+ OUT EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *GetInfoHandler, OPTIONAL
+ OUT EXTRACT_GUIDED_SECTION_DECODE_HANDLER *DecodeHandler OPTIONAL
+ )
+{
+ UINT32 Index;
+ RETURN_STATUS Status;
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;
+
+ //
+ // Check input parameter
+ //
+ ASSERT (SectionGuid != NULL);
+
+ //
+ // Get the registered handler information
+ //
+ Status = GetExtractGuidedSectionHandlerInfo (&HandlerInfo);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Search the match registered GetInfo handler for the input guided section.
+ //
+ ASSERT (HandlerInfo != NULL);
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {
+ if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionGuid)) {
+
+ //
+ // If the guided handler has been registered before, then return the registered handlers.
+ //
+ if (GetInfoHandler != NULL) {
+ *GetInfoHandler = HandlerInfo->ExtractGetInfoHandlerTable[Index];
+ }
+ if (DecodeHandler != NULL) {
+ *DecodeHandler = HandlerInfo->ExtractDecodeHandlerTable[Index];
+ }
+ return RETURN_SUCCESS;
+ }
+ }
+ return RETURN_NOT_FOUND;
+}
diff --git a/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
new file mode 100644
index 000000000000..e82d7f085cfb
--- /dev/null
+++ b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
@@ -0,0 +1,54 @@
+## @file
+# Base ExtractGuidedSection Library.
+# This instance can also be used in SEC phase only when the memory is ready in SEC phase.
+# PCD PcdGuidedExtractHandlerTableAddress points to the available pysical memory space
+# that is used to store Guided Extract Handlers.
+# Note: A driver of type DXE_RUNTIME_DRIVER can use this ExtractGuidedSectionLib
+# in their initialization without any issues. They only have to be careful in
+# the implementation of runtime services, because this BASE library instance doesn't
+# convert the address pointed by PcdGuidedExtractHandlerTableAddress to the virtual address.
+# And a driver should use this ExtractGuidedSectionLib to do implementation internally, also
+# this ExtractGuidedSectionLib couldn't be used for guided section extraction that is required
+# by PEI and DXE core for recovery or capsule image processing, etc.
+#
+# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseExtractGuidedSectionLib
+ MODULE_UNI_FILE = BaseExtractGuidedSectionLib.uni
+ FILE_GUID = 4e3236e9-d1c8-4c04-a89f-26f1c44b2592
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ExtractGuidedSectionLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+#
+
+[Sources]
+ BaseExtractGuidedSectionLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress ## CONSUMES
+
diff --git a/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.uni b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.uni
new file mode 100644
index 000000000000..fcb7d658a711
--- /dev/null
+++ b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.uni
@@ -0,0 +1,27 @@
+// /** @file
+// Base ExtractGuidedSection Library.
+//
+// This instance can also be used in SEC phase only when the memory is ready in SEC phase.
+// PCD PcdGuidedExtractHandlerTableAddress points to the available pysical memory space
+// that is used to store Guided Extract Handlers.
+// Note: A driver of type DXE_RUNTIME_DRIVER can use this ExtractGuidedSectionLib
+// in their initialization without any issues. They only have to be careful in
+// the implementation of runtime services, because this BASE library instance doesn't
+// convert the address pointed by PcdGuidedExtractHandlerTableAddress to the virtual address.
+//
+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Base ExtractGuidedSection Library"
+
+#string STR_MODULE_DESCRIPTION #language en-US "This instance can also be used in the SEC phase only when the memory is ready in the SEC phase. PCD PcdGuidedExtractHandlerTableAddress points to the available physical memory space that is used to store Guided Extract Handlers. Note: A driver of type DXE_RUNTIME_DRIVER can use this ExtractGuidedSectionLib in its initialization without any issues. Be careful in the implementation of runtime services, because this BASE library instance doesn't convert the address pointed by PcdGuidedExtractHandlerTableAddress to the virtual address."
+
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
new file mode 100644
index 000000000000..f41c4a4c715f
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -0,0 +1,82 @@
+## @file
+# Instance of I/O Library using compiler intrinsics.
+#
+# I/O Library that uses compiler intrinsics to perform IN and OUT instructions
+# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
+# MMIO requests are forwarded directly to memory. For EBC, I/O port requests
+# ASSERT().
+#
+# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseIoLibIntrinsic
+ MODULE_UNI_FILE = BaseIoLibIntrinsic.uni
+ FILE_GUID = 926c9cd0-4bb8-479b-9ac4-8a2a23f85307
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IoLib
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC IPF ARM AARCH64
+#
+
+[Sources]
+ IoLibMmioBuffer.c
+ BaseIoLibIntrinsicInternal.h
+ IoHighLevel.c
+
+[Sources.IA32]
+ IoLibGcc.c | GCC
+ IoLibMsc.c | MSFT
+ IoLibIcc.c | INTEL
+ IoLib.c
+ Ia32/IoFifo.nasm
+ Ia32/IoFifo.asm
+
+[Sources.X64]
+ IoLibGcc.c | GCC
+ IoLibMsc.c | MSFT
+ IoLibIcc.c | INTEL
+ IoLib.c
+ X64/IoFifo.nasm
+ X64/IoFifo.asm
+
+[Sources.EBC]
+ IoLibEbc.c
+ IoLib.c
+
+[Sources.IPF]
+ IoLibIpf.c
+
+[Sources.ARM]
+ IoLibArm.c
+
+[Sources.AARCH64]
+ IoLibArm.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ DebugLib
+ BaseLib
+
+[LibraryClasses.IPF]
+ PcdLib
+
+[Pcd.IPF]
+ gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf ## SOMETIMES_CONSUMES
+
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.uni b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.uni
new file mode 100644
index 000000000000..3696eda9b6af
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.uni
@@ -0,0 +1,24 @@
+// /** @file
+// Instance of I/O Library using compiler intrinsics.
+//
+// I/O Library that uses compiler intrinsics to perform IN and OUT instructions
+// for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
+// MMIO requests are forwarded directly to memory.
+//
+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of I/O Library using compiler intrinsics"
+
+#string STR_MODULE_DESCRIPTION #language en-US "I/O Library that uses compiler intrinsics to perform IN and OUT instructions for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests. MMIO requests are forwarded directly to memory."
+
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicInternal.h b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicInternal.h
new file mode 100644
index 000000000000..9b20df0b6926
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicInternal.h
@@ -0,0 +1,26 @@
+/** @file
+ Common header file shared by all source files.
+
+ This file includes package header files, dependent library classes.
+
+ Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef __BASEIOLIB_INTRINSIC_INTERNAL_H_
+#define __BASEIOLIB_INTRINSIC_INTERNAL_H_
+
+
+
+#include <Base.h>
+
+#include <Library/IoLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+#endif
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.asm b/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.asm
new file mode 100644
index 000000000000..729880d62914
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.asm
@@ -0,0 +1,141 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
+; This program and the accompanying materials are licensed and made available
+; under the terms and conditions of the BSD License which accompanies this
+; distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+ .586P
+ .model flat,C
+ .code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo8 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+IoReadFifo8 PROC
+ push edi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+rep insb
+ pop edi
+ ret
+IoReadFifo8 ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo16 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+IoReadFifo16 PROC
+ push edi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+rep insw
+ pop edi
+ ret
+IoReadFifo16 ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo32 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+IoReadFifo32 PROC
+ push edi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+rep insd
+ pop edi
+ ret
+IoReadFifo32 ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo8 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+IoWriteFifo8 PROC
+ push esi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+rep outsb
+ pop esi
+ ret
+IoWriteFifo8 ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo16 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+IoWriteFifo16 PROC
+ push esi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+rep outsw
+ pop esi
+ ret
+IoWriteFifo16 ENDP
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo32 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+IoWriteFifo32 PROC
+ push esi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+rep outsd
+ pop esi
+ ret
+IoWriteFifo32 ENDP
+
+ END
+
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm b/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm
new file mode 100644
index 000000000000..102bbb865448
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm
@@ -0,0 +1,137 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
+; This program and the accompanying materials are licensed and made available
+; under the terms and conditions of the BSD License which accompanies this
+; distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo8 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoReadFifo8)
+ASM_PFX(IoReadFifo8):
+ push edi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+rep insb
+ pop edi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo16 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoReadFifo16)
+ASM_PFX(IoReadFifo16):
+ push edi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+rep insw
+ pop edi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoReadFifo32 (
+; IN UINTN Port,
+; IN UINTN Size,
+; OUT VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoReadFifo32)
+ASM_PFX(IoReadFifo32):
+ push edi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov edi, [esp + 16]
+rep insd
+ pop edi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo8 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoWriteFifo8)
+ASM_PFX(IoWriteFifo8):
+ push esi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+rep outsb
+ pop esi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo16 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoWriteFifo16)
+ASM_PFX(IoWriteFifo16):
+ push esi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+rep outsw
+ pop esi
+ ret
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; IoWriteFifo32 (
+; IN UINTN Port,
+; IN UINTN Size,
+; IN VOID *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(IoWriteFifo32)
+ASM_PFX(IoWriteFifo32):
+ push esi
+ cld
+ mov dx, [esp + 8]
+ mov ecx, [esp + 12]
+ mov esi, [esp + 16]
+rep outsd
+ pop esi
+ ret
+
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoHighLevel.c b/MdePkg/Library/BaseIoLibIntrinsic/IoHighLevel.c
new file mode 100644
index 000000000000..8a03e33934fe
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoHighLevel.c
@@ -0,0 +1,2356 @@
+/** @file
+ High-level Io/Mmio functions.
+
+ All assertions for bit field operations are handled bit field functions in the
+ Base Library.
+
+ Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ The following IoLib instances contain the same copy of this file:
+
+ BaseIoLibIntrinsic
+ DxeIoLibCpuIo
+ PeiIoLibCpuIo
+
+**/
+
+#include "BaseIoLibIntrinsicInternal.h"
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 8-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoOr8 (
+ IN UINTN Port,
+ IN UINT8 OrData
+ )
+{
+ return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));
+}
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 8-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoAnd8 (
+ IN UINTN Port,
+ IN UINT8 AndData
+ )
+{
+ return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));
+}
+
+/**
+ Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoAndThenOr8 (
+ IN UINTN Port,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in an 8-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldRead8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldWrite8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return IoWrite8 (
+ Port,
+ BitFieldWrite8 (IoRead8 (Port), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 8-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra bits left in OrData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldOr8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return IoWrite8 (
+ Port,
+ BitFieldOr8 (IoRead8 (Port), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 8-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra bits left in AndData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldAnd8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return IoWrite8 (
+ Port,
+ BitFieldAnd8 (IoRead8 (Port), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 8-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra bits left in both
+ AndData and OrData are stripped.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoBitFieldAndThenOr8 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return IoWrite8 (
+ Port,
+ BitFieldAndThenOr8 (IoRead8 (Port), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 16-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoOr16 (
+ IN UINTN Port,
+ IN UINT16 OrData
+ )
+{
+ return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));
+}
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 16-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoAnd16 (
+ IN UINTN Port,
+ IN UINT16 AndData
+ )
+{
+ return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));
+}
+
+/**
+ Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoAndThenOr16 (
+ IN UINTN Port,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 16-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldRead16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ bits left in Value are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldWrite16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return IoWrite16 (
+ Port,
+ BitFieldWrite16 (IoRead16 (Port), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 16-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra bits left in OrData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldOr16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return IoWrite16 (
+ Port,
+ BitFieldOr16 (IoRead16 (Port), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 16-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra bits left in AndData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldAnd16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return IoWrite16 (
+ Port,
+ BitFieldAnd16 (IoRead16 (Port), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 16-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra bits left in both
+ AndData and OrData are stripped.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoBitFieldAndThenOr16 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return IoWrite16 (
+ Port,
+ BitFieldAndThenOr16 (IoRead16 (Port), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 32-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoOr32 (
+ IN UINTN Port,
+ IN UINT32 OrData
+ )
+{
+ return IoWrite32 (Port, IoRead32 (Port) | OrData);
+}
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 32-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoAnd32 (
+ IN UINTN Port,
+ IN UINT32 AndData
+ )
+{
+ return IoWrite32 (Port, IoRead32 (Port) & AndData);
+}
+
+/**
+ Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoAndThenOr32 (
+ IN UINTN Port,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 32-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldRead32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ bits left in Value are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldWrite32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return IoWrite32 (
+ Port,
+ BitFieldWrite32 (IoRead32 (Port), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 32-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra bits left in OrData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldOr32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return IoWrite32 (
+ Port,
+ BitFieldOr32 (IoRead32 (Port), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 32-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra bits left in AndData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldAnd32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return IoWrite32 (
+ Port,
+ BitFieldAnd32 (IoRead32 (Port), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 32-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra bits left in both
+ AndData and OrData are stripped.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoBitFieldAndThenOr32 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return IoWrite32 (
+ Port,
+ BitFieldAndThenOr32 (IoRead32 (Port), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise OR, and writes the
+ result back to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoOr64 (
+ IN UINTN Port,
+ IN UINT64 OrData
+ )
+{
+ return IoWrite64 (Port, IoRead64 (Port) | OrData);
+}
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back
+ to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 64-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoAnd64 (
+ IN UINTN Port,
+ IN UINT64 AndData
+ )
+{
+ return IoWrite64 (Port, IoRead64 (Port) & AndData);
+}
+
+/**
+ Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, performs a bitwise OR
+ between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 64-bit I/O port specified by Port. The value
+ written to the I/O port is returned. This function must guarantee that all
+ I/O read and write operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoAndThenOr64 (
+ IN UINTN Port,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of an I/O register.
+
+ Reads the bit field in a 64-bit I/O register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldRead64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to an I/O register.
+
+ Writes Value to the bit field of the I/O register. The bit field is specified
+ by the StartBit and the EndBit. All other bits in the destination I/O
+ register are preserved. The value written to the I/O port is returned. Extra
+ bits left in Value are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldWrite64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 Value
+ )
+{
+ return IoWrite64 (
+ Port,
+ BitFieldWrite64 (IoRead64 (Port), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the
+ result back to the bit field in the 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise OR
+ between the read result and the value specified by OrData, and writes the
+ result to the 64-bit I/O port specified by Port. The value written to the I/O
+ port is returned. This function must guarantee that all I/O read and write
+ operations are serialized. Extra bits left in OrData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param OrData The value to OR with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldOr64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 OrData
+ )
+{
+ return IoWrite64 (
+ Port,
+ BitFieldOr64 (IoRead64 (Port), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the
+ result back to the bit field in the 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
+ the read result and the value specified by AndData, and writes the result to
+ the 64-bit I/O port specified by Port. The value written to the I/O port is
+ returned. This function must guarantee that all I/O read and write operations
+ are serialized. Extra bits left in AndData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the I/O port.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldAnd64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData
+ )
+{
+ return IoWrite64 (
+ Port,
+ BitFieldAnd64 (IoRead64 (Port), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 64-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 64-bit port.
+
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed
+ by a bitwise OR between the read result and the value specified by
+ AndData, and writes the result to the 64-bit I/O port specified by Port. The
+ value written to the I/O port is returned. This function must guarantee that
+ all I/O read and write operations are serialized. Extra bits left in both
+ AndData and OrData are stripped.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+ If StartBit is greater than 63, then ASSERT().
+ If EndBit is greater than 63, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..63.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..63.
+ @param AndData The value to AND with the read value from the I/O port.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoBitFieldAndThenOr64 (
+ IN UINTN Port,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ return IoWrite64 (
+ Port,
+ BitFieldAndThenOr64 (IoRead64 (Port), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise OR, and writes the
+ result back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 8-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ )
+{
+ return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));
+}
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result
+ back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, and writes the
+ result to the 8-bit MMIO register specified by Address. The value written to
+ the MMIO register is returned. This function must guarantee that all MMIO
+ read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ )
+{
+ return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));
+}
+
+/**
+ Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise
+ OR, and writes the result back to the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
+ between the read result and the value specified by AndData, performs a
+ bitwise OR between the result of the AND operation and the value specified by
+ OrData, and writes the result to the 8-bit MMIO register specified by
+ Address. The value written to the MMIO register is returned. This function
+ must guarantee that all MMIO read and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a MMIO register.
+
+ Reads the bit field in an 8-bit MMIO register. The bit field is specified by
+ the StartBit and the EndBit. The value of the bit field is returned.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The MMIO register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a MMIO register.
+
+ Writes Value to the bit field of the MMIO register. The bit field is
+ specified by the StartBit and the EndBit. All other bits in the destination
+ MMIO register are preserved. The new value of the 8-bit register is returned.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return MmioWrite8 (
+ Address,
+ BitFieldWrite8 (MmioRead8 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise
+ OR between the read result and the value specified by OrData, and
+ writes the result to the 8-bit MMIO register specified by Address. The value
+ written to the MMIO register is returned. This function must guarantee that
+ all MMIO read and write operations are serialized. Extra bits left in OrData
+ are stripped.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return MmioWrite8 (
+ Address,
+ BitFieldOr8 (MmioRead8 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and
+ writes the result back to the bit field in the 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND<