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-rw-r--r--MdePkg/Include/Protocol/CpuIo2.h62
1 files changed, 28 insertions, 34 deletions
diff --git a/MdePkg/Include/Protocol/CpuIo2.h b/MdePkg/Include/Protocol/CpuIo2.h
index 49fb470713e7..173b00d5c3a4 100644
--- a/MdePkg/Include/Protocol/CpuIo2.h
+++ b/MdePkg/Include/Protocol/CpuIo2.h
@@ -1,28 +1,22 @@
/** @file
This files describes the CPU I/O 2 Protocol.
-
+
This protocol provides an I/O abstraction for a system processor. This protocol
is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions.
The I/O or memory primitives can be used by the consumer of the protocol to materialize
bus-specific configuration cycles, such as the transitional configuration address and data
- ports for PCI. Only drivers that require direct access to the entire system should use this
- protocol.
-
+ ports for PCI. Only drivers that require direct access to the entire system should use this
+ protocol.
+
Note: This is a boot-services only protocol and it may not be used by runtime drivers after
ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime
protocol and can be used by runtime drivers after ExitBootServices().
- Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- This Protocol is defined in UEFI Platform Initialization Specification 1.2
+ This Protocol is defined in UEFI Platform Initialization Specification 1.2
Volume 5: Standards
**/
@@ -57,35 +51,35 @@ typedef enum {
} EFI_CPU_IO_PROTOCOL_WIDTH;
/**
- Enables a driver to access registers in the PI CPU I/O space.
+ Enables a driver to access registers in the PI CPU I/O space.
- The Io.Read() and Io.Write() functions enable a driver to access PCI controller
- registers in the PI CPU I/O space.
+ The Io.Read() and Io.Write() functions enable a driver to access PCI controller
+ registers in the PI CPU I/O space.
- The I/O operations are carried out exactly as requested. The caller is responsible
- for satisfying any alignment and I/O width restrictions that a PI System on a
- platform might require. For example on some platforms, width requests of
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
be handled by the driver.
-
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
each of the Count operations that is performed.
-
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
- incremented for each of the Count operations that is performed. The read or
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
write operation is performed Count times on the same Address.
-
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
- incremented for each of the Count operations that is performed. The read or
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
write operation is performed Count times from the first element of Buffer.
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
@param[in] Width Signifies the width of the I/O or Memory operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Count The number of I/O operations to perform. The number
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number
of bytes moved is Width size * Count, starting at Address.
@param[in, out] Buffer For read operations, the destination buffer to store the results.
For write operations, the source buffer from which to write data.
@@ -94,7 +88,7 @@ typedef enum {
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
and Count is not valid for this PI system.
**/