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-rw-r--r--MdePkg/Include/IndustryStandard/Acpi.h13
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi10.h20
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi20.h20
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi30.h22
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi40.h20
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi50.h30
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi51.h30
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi60.h78
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi61.h80
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi62.h2960
-rw-r--r--MdePkg/Include/IndustryStandard/Acpi63.h2960
-rw-r--r--MdePkg/Include/IndustryStandard/AcpiAml.h18
-rw-r--r--MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h16
-rw-r--r--MdePkg/Include/IndustryStandard/Atapi.h372
-rw-r--r--MdePkg/Include/IndustryStandard/Bluetooth.h25
-rw-r--r--MdePkg/Include/IndustryStandard/Bmp.h8
-rw-r--r--MdePkg/Include/IndustryStandard/DebugPort2Table.h14
-rw-r--r--MdePkg/Include/IndustryStandard/DebugPortTable.h14
-rw-r--r--MdePkg/Include/IndustryStandard/Dhcp.h15
-rw-r--r--MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h28
-rw-r--r--MdePkg/Include/IndustryStandard/ElTorito.h50
-rw-r--r--MdePkg/Include/IndustryStandard/Emmc.h10
-rw-r--r--MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h28
-rw-r--r--MdePkg/Include/IndustryStandard/Hsti.h18
-rw-r--r--MdePkg/Include/IndustryStandard/Http11.h138
-rw-r--r--MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h20
-rw-r--r--MdePkg/Include/IndustryStandard/IoRemappingTable.h203
-rw-r--r--MdePkg/Include/IndustryStandard/Ipmi.h42
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h86
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiNetFnApp.h536
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h12
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h335
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h8
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h8
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h8
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h587
-rw-r--r--MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h611
-rw-r--r--MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h14
-rw-r--r--MdePkg/Include/IndustryStandard/LowPowerIdleTable.h8
-rw-r--r--MdePkg/Include/IndustryStandard/Mbr.h10
-rw-r--r--MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h16
-rw-r--r--MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h12
-rw-r--r--MdePkg/Include/IndustryStandard/Nvme.h24
-rw-r--r--MdePkg/Include/IndustryStandard/Pal.h3302
-rw-r--r--MdePkg/Include/IndustryStandard/Pci.h10
-rw-r--r--MdePkg/Include/IndustryStandard/Pci22.h125
-rw-r--r--MdePkg/Include/IndustryStandard/Pci23.h24
-rw-r--r--MdePkg/Include/IndustryStandard/Pci30.h10
-rw-r--r--MdePkg/Include/IndustryStandard/PciCodeId.h10
-rw-r--r--MdePkg/Include/IndustryStandard/PciExpress21.h94
-rw-r--r--MdePkg/Include/IndustryStandard/PciExpress30.h10
-rw-r--r--MdePkg/Include/IndustryStandard/PciExpress31.h8
-rw-r--r--MdePkg/Include/IndustryStandard/PciExpress40.h111
-rw-r--r--MdePkg/Include/IndustryStandard/PciExpress50.h136
-rw-r--r--MdePkg/Include/IndustryStandard/PeImage.h50
-rw-r--r--MdePkg/Include/IndustryStandard/Sal.h915
-rw-r--r--MdePkg/Include/IndustryStandard/Scsi.h68
-rw-r--r--MdePkg/Include/IndustryStandard/Sd.h8
-rw-r--r--MdePkg/Include/IndustryStandard/SdramSpd.h8
-rw-r--r--MdePkg/Include/IndustryStandard/SdramSpdDdr3.h8
-rw-r--r--MdePkg/Include/IndustryStandard/SdramSpdDdr4.h8
-rw-r--r--MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h8
-rw-r--r--MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h22
-rw-r--r--MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h98
-rw-r--r--MdePkg/Include/IndustryStandard/SmBios.h563
-rw-r--r--MdePkg/Include/IndustryStandard/SmBus.h12
-rw-r--r--MdePkg/Include/IndustryStandard/Spdm.h320
-rw-r--r--MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h12
-rw-r--r--MdePkg/Include/IndustryStandard/TcgStorageCore.h15
-rw-r--r--MdePkg/Include/IndustryStandard/TcgStorageOpal.h76
-rw-r--r--MdePkg/Include/IndustryStandard/TcpaAcpi.h8
-rw-r--r--MdePkg/Include/IndustryStandard/Tls1.h30
-rw-r--r--MdePkg/Include/IndustryStandard/Tpm12.h24
-rw-r--r--MdePkg/Include/IndustryStandard/Tpm20.h8
-rw-r--r--MdePkg/Include/IndustryStandard/Tpm2Acpi.h15
-rw-r--r--MdePkg/Include/IndustryStandard/TpmPtp.h15
-rw-r--r--MdePkg/Include/IndustryStandard/TpmTis.h16
-rw-r--r--MdePkg/Include/IndustryStandard/Udf.h141
-rw-r--r--MdePkg/Include/IndustryStandard/UefiTcgPlatform.h203
-rw-r--r--MdePkg/Include/IndustryStandard/Usb.h8
-rw-r--r--MdePkg/Include/IndustryStandard/WatchdogActionTable.h16
-rw-r--r--MdePkg/Include/IndustryStandard/WatchdogResourceTable.h12
-rw-r--r--MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h10
-rw-r--r--MdePkg/Include/IndustryStandard/WindowsUxCapsule.h10
84 files changed, 10158 insertions, 5916 deletions
diff --git a/MdePkg/Include/IndustryStandard/Acpi.h b/MdePkg/Include/IndustryStandard/Acpi.h
index 3d35f599b4e6..a362d0f68f98 100644
--- a/MdePkg/Include/IndustryStandard/Acpi.h
+++ b/MdePkg/Include/IndustryStandard/Acpi.h
@@ -2,20 +2,15 @@
This file contains the latest ACPI definitions that are
consumed by drivers that do not care about ACPI versions.
- Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2019, ARM Ltd. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_H_
#define _ACPI_H_
-#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/Acpi63.h>
#endif
diff --git a/MdePkg/Include/IndustryStandard/Acpi10.h b/MdePkg/Include/IndustryStandard/Acpi10.h
index 5a17db6ac570..d1398018aef9 100644
--- a/MdePkg/Include/IndustryStandard/Acpi10.h
+++ b/MdePkg/Include/IndustryStandard/Acpi10.h
@@ -1,14 +1,8 @@
-/** @file
+/** @file
ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_1_0_H_
@@ -43,7 +37,7 @@ typedef struct {
#pragma pack()
//
-// Define for Desriptor
+// Define for Descriptor
//
#define ACPI_SMALL_ITEM_FLAG 0x00
#define ACPI_LARGE_ITEM_FLAG 0x01
@@ -115,7 +109,7 @@ typedef struct {
#pragma pack(1)
///
-/// The commond definition of QWORD, DWORD, and WORD
+/// The common definition of QWORD, DWORD, and WORD
/// Address Space Descriptors.
///
typedef PACKED struct {
@@ -357,7 +351,7 @@ typedef struct {
#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20
#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40
#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60
-
+
#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04
#define EFI_ACPI_DMA_BUS_MASTER 0x04
@@ -403,7 +397,7 @@ typedef struct {
//
// Root System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
diff --git a/MdePkg/Include/IndustryStandard/Acpi20.h b/MdePkg/Include/IndustryStandard/Acpi20.h
index d84b7db7b7da..b4e19ae56ea6 100644
--- a/MdePkg/Include/IndustryStandard/Acpi20.h
+++ b/MdePkg/Include/IndustryStandard/Acpi20.h
@@ -1,14 +1,8 @@
-/** @file
+/** @file
ACPI 2.0 definitions from the ACPI Specification, revision 2.0
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_2_0_H_
@@ -17,7 +11,7 @@
#include <IndustryStandard/Acpi10.h>
//
-// Define for Desriptor
+// Define for Descriptor
//
#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02
@@ -103,7 +97,7 @@ typedef struct {
//
// Root System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
@@ -114,7 +108,7 @@ typedef struct {
//
// Extended System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
@@ -511,7 +505,7 @@ typedef struct {
#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
diff --git a/MdePkg/Include/IndustryStandard/Acpi30.h b/MdePkg/Include/IndustryStandard/Acpi30.h
index d510d8b93469..4ef7bec7a5b4 100644
--- a/MdePkg/Include/IndustryStandard/Acpi30.h
+++ b/MdePkg/Include/IndustryStandard/Acpi30.h
@@ -1,14 +1,8 @@
-/** @file
+/** @file
ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_3_0_H_
@@ -17,7 +11,7 @@
#include <IndustryStandard/Acpi20.h>
//
-// Define for Desriptor
+// Define for Descriptor
//
#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B
@@ -128,7 +122,7 @@ typedef struct {
//
// Root System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
@@ -139,7 +133,7 @@ typedef struct {
//
// Extended System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
@@ -597,7 +591,7 @@ typedef struct {
///
/// "RSD PTR " Root System Description Pointer
///
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table
@@ -690,7 +684,7 @@ typedef struct {
#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
diff --git a/MdePkg/Include/IndustryStandard/Acpi40.h b/MdePkg/Include/IndustryStandard/Acpi40.h
index 94ae5fc56727..cfd491d45de5 100644
--- a/MdePkg/Include/IndustryStandard/Acpi40.h
+++ b/MdePkg/Include/IndustryStandard/Acpi40.h
@@ -1,14 +1,8 @@
-/** @file
+/** @file
ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010
- Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_4_0_H_
@@ -86,7 +80,7 @@ typedef struct {
//
// Root System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
@@ -97,7 +91,7 @@ typedef struct {
//
// Extended System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
@@ -1132,7 +1126,7 @@ typedef struct {
///
/// "RSD PTR " Root System Description Pointer
///
-#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table
@@ -1270,7 +1264,7 @@ typedef struct {
#define EFI_ACPI_4_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_4_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
diff --git a/MdePkg/Include/IndustryStandard/Acpi50.h b/MdePkg/Include/IndustryStandard/Acpi50.h
index a371c9ade1b1..a9f0912e2d6a 100644
--- a/MdePkg/Include/IndustryStandard/Acpi50.h
+++ b/MdePkg/Include/IndustryStandard/Acpi50.h
@@ -1,15 +1,10 @@
-/** @file
+/** @file
ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.
Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
- Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_5_0_H_
@@ -18,7 +13,7 @@
#include <IndustryStandard/Acpi40.h>
//
-// Define for Desriptor
+// Define for Descriptor
//
#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A
#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C
@@ -208,7 +203,7 @@ typedef struct {
//
// Root System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
@@ -219,7 +214,7 @@ typedef struct {
//
// Extended System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
@@ -1207,7 +1202,7 @@ typedef struct {
///
UINT64 ExitBootServicesEntry;
///
- /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
@@ -1876,7 +1871,7 @@ typedef struct {
///
/// "RSD PTR " Root System Description Pointer
///
-#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table
@@ -2064,12 +2059,17 @@ typedef struct {
#define EFI_ACPI_5_0_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
/// "SLIC" MS Software Licensing Table Specification
///
#define EFI_ACPI_5_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
diff --git a/MdePkg/Include/IndustryStandard/Acpi51.h b/MdePkg/Include/IndustryStandard/Acpi51.h
index 457706befd82..2c027859b9a3 100644
--- a/MdePkg/Include/IndustryStandard/Acpi51.h
+++ b/MdePkg/Include/IndustryStandard/Acpi51.h
@@ -1,16 +1,11 @@
-/** @file
+/** @file
ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016.
Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
- Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_5_1_H_
@@ -89,7 +84,7 @@ typedef struct {
//
// Root System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
@@ -100,7 +95,7 @@ typedef struct {
//
// Extended System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
@@ -1160,7 +1155,7 @@ typedef struct {
///
UINT64 ExitBootServicesEntry;
///
- /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
@@ -1874,7 +1869,7 @@ typedef struct {
UINT8 CommandComplete:1;
UINT8 SciDoorbell:1;
UINT8 Error:1;
- UINT8 PlatformNotification:1;
+ UINT8 PlatformNotification:1;
UINT8 Reserved:4;
UINT8 Reserved1;
} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -1892,7 +1887,7 @@ typedef struct {
///
/// "RSD PTR " Root System Description Pointer
///
-#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table
@@ -2085,12 +2080,17 @@ typedef struct {
#define EFI_ACPI_5_1_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
/// "SLIC" MS Software Licensing Table Specification
///
#define EFI_ACPI_5_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
diff --git a/MdePkg/Include/IndustryStandard/Acpi60.h b/MdePkg/Include/IndustryStandard/Acpi60.h
index 478697cceb48..35417fb39b11 100644
--- a/MdePkg/Include/IndustryStandard/Acpi60.h
+++ b/MdePkg/Include/IndustryStandard/Acpi60.h
@@ -1,15 +1,10 @@
-/** @file
+/** @file
ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016.
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_6_0_H_
@@ -88,7 +83,7 @@ typedef struct {
//
// Root System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
@@ -99,7 +94,7 @@ typedef struct {
//
// Extended System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
@@ -1175,7 +1170,7 @@ typedef struct {
///
UINT64 ExitBootServicesEntry;
///
- /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
@@ -2020,7 +2015,9 @@ typedef struct {
//
// PCCT Subspace type
//
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
///
/// PCC Subspace Structure Header
@@ -2061,7 +2058,7 @@ typedef struct {
UINT8 CommandComplete:1;
UINT8 SciDoorbell:1;
UINT8 Error:1;
- UINT8 PlatformNotification:1;
+ UINT8 PlatformNotification:1;
UINT8 Reserved:4;
UINT8 Reserved1;
} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -2072,6 +2069,50 @@ typedef struct {
EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;
+ UINT64 DoorbellAckPreserve;
+ UINT64 DoorbellAckWrite;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
//
// Known table signatures
//
@@ -2079,7 +2120,7 @@ typedef struct {
///
/// "RSD PTR " Root System Description Pointer
///
-#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table
@@ -2282,12 +2323,17 @@ typedef struct {
#define EFI_ACPI_6_0_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
/// "SLIC" MS Software Licensing Table Specification
///
#define EFI_ACPI_6_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
diff --git a/MdePkg/Include/IndustryStandard/Acpi61.h b/MdePkg/Include/IndustryStandard/Acpi61.h
index 954e61d2a19f..35351db8b072 100644
--- a/MdePkg/Include/IndustryStandard/Acpi61.h
+++ b/MdePkg/Include/IndustryStandard/Acpi61.h
@@ -1,15 +1,10 @@
-/** @file
+/** @file
ACPI 6.1 definitions from the ACPI Specification Revision 6.1 January, 2016.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ACPI_6_1_H_
@@ -88,7 +83,7 @@ typedef struct {
//
// Root System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
//
@@ -99,7 +94,7 @@ typedef struct {
//
// Extended System Description Table
-// No definition needed as it is a common description table header, the same with
+// No definition needed as it is a common description table header, the same with
// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
//
@@ -1175,7 +1170,7 @@ typedef struct {
///
UINT64 ExitBootServicesEntry;
///
- /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// Timer value logged at the point just prior to when the OS loader gaining
/// control back from calls the ExitBootServices function for UEFI compatible firmware.
/// For non-UEFI compatible boots, this field must be zero.
///
@@ -1400,7 +1395,7 @@ typedef struct {
#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D ]}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
typedef struct {
UINT16 Type;
UINT16 Length;
@@ -2052,7 +2047,9 @@ typedef struct {
//
// PCCT Subspace type
//
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
///
/// PCC Subspace Structure Header
@@ -2093,7 +2090,7 @@ typedef struct {
UINT8 CommandComplete:1;
UINT8 SciDoorbell:1;
UINT8 Error:1;
- UINT8 PlatformNotification:1;
+ UINT8 PlatformNotification:1;
UINT8 Reserved:4;
UINT8 Reserved1;
} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -2104,6 +2101,50 @@ typedef struct {
EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 DoorbellInterrupt;
+ UINT8 DoorbellInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;
+ UINT64 DoorbellAckPreserve;
+ UINT64 DoorbellAckWrite;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
//
// Known table signatures
//
@@ -2111,7 +2152,7 @@ typedef struct {
///
/// "RSD PTR " Root System Description Pointer
///
-#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
///
/// "APIC" Multiple APIC Description Table
@@ -2314,12 +2355,17 @@ typedef struct {
#define EFI_ACPI_6_1_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
/// "SLIC" MS Software Licensing Table Specification
///
#define EFI_ACPI_6_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
///
#define EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
diff --git a/MdePkg/Include/IndustryStandard/Acpi62.h b/MdePkg/Include/IndustryStandard/Acpi62.h
new file mode 100644
index 000000000000..7d71ac142f90
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Acpi62.h
@@ -0,0 +1,2960 @@
+/** @file
+ ACPI 6.2 definitions from the ACPI Specification Revision 6.2 May, 2017.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_6_2_H_
+#define _ACPI_6_2_H_
+
+#include <IndustryStandard/Acpi61.h>
+
+//
+// Large Item Descriptor Name
+//
+#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D
+#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F
+#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10
+#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11
+#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12
+
+//
+// Large Item Descriptor Value
+//
+#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D
+#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F
+#define ACPI_PIN_GROUP_DESCRIPTOR 0x90
+#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91
+#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92
+
+#pragma pack(1)
+
+///
+/// Pin Function Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT8 PinPullConfiguration;
+ UINT16 FunctionNumber;
+ UINT16 PinTableOffset;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_FUNCTION_DESCRIPTOR;
+
+///
+/// Pin Configuration Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT8 PinConfigurationType;
+ UINT32 PinConfigurationValue;
+ UINT16 PinTableOffset;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_CONFIGURATION_DESCRIPTOR;
+
+///
+/// Pin Group Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT16 PinTableOffset;
+ UINT16 ResourceLabelOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_GROUP_DESCRIPTOR;
+
+///
+/// Pin Group Function Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT16 FunctionNumber;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 ResourceSourceLabelOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR;
+
+///
+/// Pin Group Configuration Descriptor
+///
+typedef PACKED struct {
+ ACPI_LARGE_RESOURCE_HEADER Header;
+ UINT8 RevisionId;
+ UINT16 Flags;
+ UINT8 PinConfigurationType;
+ UINT32 PinConfigurationValue;
+ UINT8 ResourceSourceIndex;
+ UINT16 ResourceSourceNameOffset;
+ UINT16 ResourceSourceLabelOffset;
+ UINT16 VendorDataOffset;
+ UINT16 VendorDataLength;
+} EFI_ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.2 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_2_SYSTEM_MEMORY 0
+#define EFI_ACPI_6_2_SYSTEM_IO 1
+#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3
+#define EFI_ACPI_6_2_SMBUS 4
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_2_UNDEFINED 0
+#define EFI_ACPI_6_2_BYTE 1
+#define EFI_ACPI_6_2_WORD 2
+#define EFI_ACPI_6_2_DWORD 3
+#define EFI_ACPI_6_2_QWORD 4
+
+//
+// ACPI 6.2 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_2_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x02
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_2_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_2_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_2_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_2_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_2_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_2_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_2_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_2_8042 BIT1
+#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_WBINVD BIT0
+#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_2_PROC_C1 BIT2
+#define EFI_ACPI_6_2_P_LVL2_UP BIT3
+#define EFI_ACPI_6_2_PWR_BUTTON BIT4
+#define EFI_ACPI_6_2_SLP_BUTTON BIT5
+#define EFI_ACPI_6_2_FIX_RTC BIT6
+#define EFI_ACPI_6_2_RTC_S4 BIT7
+#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_2_DCK_CAP BIT9
+#define EFI_ACPI_6_2_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_2_SEALED_CASE BIT11
+#define EFI_ACPI_6_2_HEADLESS BIT12
+#define EFI_ACPI_6_2_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_S4BIOS_F BIT0
+#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_2_IO_APIC 0x01
+#define EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_2_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_2_IO_SAPIC 0x06
+#define EFI_ACPI_6_2_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_2_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_2_GIC 0x0B
+#define EFI_ACPI_6_2_GICD 0x0C
+#define EFI_ACPI_6_2_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_2_GICR 0x0E
+#define EFI_ACPI_6_2_GIC_ITS 0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_2_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_POLARITY (3 << 0)
+#define EFI_ACPI_6_2_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_2_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GIC_ENABLED BIT0
+#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_2_GIC_V1 0x01
+#define EFI_ACPI_6_2_GIC_V2 0x02
+#define EFI_ACPI_6_2_GIC_V3 0x03
+#define EFI_ACPI_6_2_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_2_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_2_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x05 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_2_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_2_GICC_AFFINITY 0x03
+#define EFI_ACPI_6_2_GIC_ITS_AFFINITY 0x04
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
+} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE;
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_2_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_2_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_2_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+//EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x1
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+//EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+//UINT32 ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:1] = Reserved (must be zero)
+ /// Bit [0] = Valid. A one indicates the boot image graphic is valid.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_2_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_2_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior to when the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_2_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.2 spec.)
+//
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber:4;
+ UINT32 MemoryChannelNumber:4;
+ UINT32 MemoryControllerID:4;
+ UINT32 SocketID:4;
+ UINT32 NodeControllerID:12;
+ UINT32 Reserved_28:4;
+} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex ;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+//UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+//UINT8 Data[];
+} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01
+
+///
+/// Secure Device types
+///
+#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+
+///
+/// Secure Device flags
+///
+#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid:1;
+ UINT32 CorrectableErrorValid:1;
+ UINT32 MultipleUncorrectableErrors:1;
+ UINT32 MultipleCorrectableErrors:1;
+ UINT32 ErrorDataEntryCount:10;
+ UINT32 Reserved:18;
+} EFI_ACPI_6_2_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_6_2_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_2_ERROR_SEVERITY_NONE 0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
+} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR 0x09
+#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type:1;
+ UINT16 PollInterval:1;
+ UINT16 SwitchToPollingThresholdValue:1;
+ UINT16 SwitchToPollingThresholdWindow:1;
+ UINT16 ErrorThresholdValue:1;
+ UINT16 ErrorThresholdWindow:1;
+ UINT16 Reserved:10;
+} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
+} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00
+#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Subsystem Address Range Structure flags
+///
+typedef struct {
+ UINT16 ProcessorProximityDomainValid:1;
+ UINT16 MemoryProximityDomainValid:1;
+ UINT16 ReservationHint:1;
+ UINT16 Reserved:13;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS;
+
+///
+/// Memory Subsystem Address Range Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 ProcessorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[4];
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+ UINT8 MemoryHierarchy:5;
+ UINT8 Reserved:3;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 Reserved1[2];
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+ UINT32 TotalCacheLevels:4;
+ UINT32 CacheLevel:4;
+ UINT32 CacheAssociativity:4;
+ UINT32 WritePolicy:4;
+ UINT32 CacheLineSize:16;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_2_ERST_NOOP 0x04
+#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_2_ERST_ADD 0x08
+#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_2_ERST_STALL 0x0C
+#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_2_ERST_GOTO 0x0F
+#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_2_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_2_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved:7;
+ UINT8 NotifyOnCompletion:1;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete:1;
+ UINT8 PlatformInterrupt:1;
+ UINT8 Error:1;
+ UINT8 PlatformNotification:1;
+ UINT8 Reserved:4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
+} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+ UINT16 SubChannelIdentifer:8;
+ UINT16 Runtime:1;
+ UINT16 WaitForCompletion:1;
+ UINT16 Reserved:6;
+} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+
+///
+/// PPTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_2_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01
+#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+ UINT32 PhysicalPackage:1;
+ UINT32 AcpiProcessorIdValid:1;
+ UINT32 Reserved:30;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+ UINT32 SizePropertyValid:1;
+ UINT32 NumberOfSetsValid:1;
+ UINT32 AssociativityValid:1;
+ UINT32 AllocationTypeValid:1;
+ UINT32 CacheTypeValid:1;
+ UINT32 WritePolicyValid:1;
+ UINT32 LineSizeValid:1;
+ UINT32 Reserved:25;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+ UINT8 AllocationType:2;
+ UINT8 CacheType:2;
+ UINT8 WritePolicy:1;
+ UINT8 Reserved:3;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE;
+
+///
+/// ID structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 VendorId;
+ UINT64 Level1Id;
+ UINT64 Level2Id;
+ UINT16 MajorRev;
+ UINT16 MinorRev;
+ UINT16 SpinRev;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_ID;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_2_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_2_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_2_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_2_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_2_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_2_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_2_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_2_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DPPT" DMA Protection Policy Table
+///
+#define EFI_ACPI_6_2_DMA_PROTECTION_POLICY_TABLE_SIGNATURE SIGNATURE_32('D', 'P', 'P', 'T')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_2_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_2_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_2_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_2_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_2_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_2_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_2_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_2_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_2_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_2_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_2_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_2_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_2_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_2_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_2_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_2_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_2_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_2_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Acpi63.h b/MdePkg/Include/IndustryStandard/Acpi63.h
new file mode 100644
index 000000000000..b365cd0cd4de
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Acpi63.h
@@ -0,0 +1,2960 @@
+/** @file
+ ACPI 6.3 definitions from the ACPI Specification Revision 6.3 Jan, 2019.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2019 - 2020, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_6_3_H_
+#define _ACPI_6_3_H_
+
+#include <IndustryStandard/Acpi62.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.3 Generic Address Space definition
+///
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_3_SYSTEM_MEMORY 0x00
+#define EFI_ACPI_6_3_SYSTEM_IO 0x01
+#define EFI_ACPI_6_3_PCI_CONFIGURATION_SPACE 0x02
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER 0x03
+#define EFI_ACPI_6_3_SMBUS 0x04
+#define EFI_ACPI_6_3_SYSTEM_CMOS 0x05
+#define EFI_ACPI_6_3_PCI_BAR_TARGET 0x06
+#define EFI_ACPI_6_3_IPMI 0x07
+#define EFI_ACPI_6_3_GENERAL_PURPOSE_IO 0x08
+#define EFI_ACPI_6_3_GENERIC_SERIAL_BUS 0x09
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL 0x0A
+#define EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE 0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_3_UNDEFINED 0
+#define EFI_ACPI_6_3_BYTE 1
+#define EFI_ACPI_6_3_WORD 2
+#define EFI_ACPI_6_3_DWORD 3
+#define EFI_ACPI_6_3_QWORD 4
+
+//
+// ACPI 6.3 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OemId[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.3) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_3_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 FirmwareCtrl;
+ UINT32 Dsdt;
+ UINT8 Reserved0;
+ UINT8 PreferredPmProfile;
+ UINT16 SciInt;
+ UINT32 SmiCmd;
+ UINT8 AcpiEnable;
+ UINT8 AcpiDisable;
+ UINT8 S4BiosReq;
+ UINT8 PstateCnt;
+ UINT32 Pm1aEvtBlk;
+ UINT32 Pm1bEvtBlk;
+ UINT32 Pm1aCntBlk;
+ UINT32 Pm1bCntBlk;
+ UINT32 Pm2CntBlk;
+ UINT32 PmTmrBlk;
+ UINT32 Gpe0Blk;
+ UINT32 Gpe1Blk;
+ UINT8 Pm1EvtLen;
+ UINT8 Pm1CntLen;
+ UINT8 Pm2CntLen;
+ UINT8 PmTmrLen;
+ UINT8 Gpe0BlkLen;
+ UINT8 Gpe1BlkLen;
+ UINT8 Gpe1Base;
+ UINT8 CstCnt;
+ UINT16 PLvl2Lat;
+ UINT16 PLvl3Lat;
+ UINT16 FlushSize;
+ UINT16 FlushStride;
+ UINT8 DutyOffset;
+ UINT8 DutyWidth;
+ UINT8 DayAlrm;
+ UINT8 MonAlrm;
+ UINT8 Century;
+ UINT16 IaPcBootArch;
+ UINT8 Reserved1;
+ UINT32 Flags;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg;
+ UINT8 ResetValue;
+ UINT16 ArmBootArch;
+ UINT8 MinorVersion;
+ UINT64 XFirmwareCtrl;
+ UINT64 XDsdt;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;
+ UINT64 HypervisorVendorIdentity;
+} EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x03
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_3_PM_PROFILE_UNSPECIFIED 0
+#define EFI_ACPI_6_3_PM_PROFILE_DESKTOP 1
+#define EFI_ACPI_6_3_PM_PROFILE_MOBILE 2
+#define EFI_ACPI_6_3_PM_PROFILE_WORKSTATION 3
+#define EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER 4
+#define EFI_ACPI_6_3_PM_PROFILE_SOHO_SERVER 5
+#define EFI_ACPI_6_3_PM_PROFILE_APPLIANCE_PC 6
+#define EFI_ACPI_6_3_PM_PROFILE_PERFORMANCE_SERVER 7
+#define EFI_ACPI_6_3_PM_PROFILE_TABLET 8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_LEGACY_DEVICES BIT0
+#define EFI_ACPI_6_3_8042 BIT1
+#define EFI_ACPI_6_3_VGA_NOT_PRESENT BIT2
+#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED BIT3
+#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS BIT4
+#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT BIT0
+#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_WBINVD BIT0
+#define EFI_ACPI_6_3_WBINVD_FLUSH BIT1
+#define EFI_ACPI_6_3_PROC_C1 BIT2
+#define EFI_ACPI_6_3_P_LVL2_UP BIT3
+#define EFI_ACPI_6_3_PWR_BUTTON BIT4
+#define EFI_ACPI_6_3_SLP_BUTTON BIT5
+#define EFI_ACPI_6_3_FIX_RTC BIT6
+#define EFI_ACPI_6_3_RTC_S4 BIT7
+#define EFI_ACPI_6_3_TMR_VAL_EXT BIT8
+#define EFI_ACPI_6_3_DCK_CAP BIT9
+#define EFI_ACPI_6_3_RESET_REG_SUP BIT10
+#define EFI_ACPI_6_3_SEALED_CASE BIT11
+#define EFI_ACPI_6_3_HEADLESS BIT12
+#define EFI_ACPI_6_3_CPU_SW_SLP BIT13
+#define EFI_ACPI_6_3_PCI_EXP_WAK BIT14
+#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15
+#define EFI_ACPI_6_3_S4_RTC_STS_VALID BIT16
+#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE BIT17
+#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18
+#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+#define EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20
+#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+ UINT32 HardwareSignature;
+ UINT32 FirmwareWakingVector;
+ UINT32 GlobalLock;
+ UINT32 Flags;
+ UINT64 XFirmwareWakingVector;
+ UINT8 Version;
+ UINT8 Reserved0[3];
+ UINT32 OspmFlags;
+ UINT8 Reserved1[24];
+} EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_S4BIOS_F BIT0
+#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Multiple APIC Description Table header definition. The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 LocalApicAddress;
+ UINT32 Flags;
+} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_PCAT_COMPAT BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC 0x00
+#define EFI_ACPI_6_3_IO_APIC 0x01
+#define EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE 0x02
+#define EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE 0x03
+#define EFI_ACPI_6_3_LOCAL_APIC_NMI 0x04
+#define EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE 0x05
+#define EFI_ACPI_6_3_IO_SAPIC 0x06
+#define EFI_ACPI_6_3_LOCAL_SAPIC 0x07
+#define EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES 0x08
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC 0x09
+#define EFI_ACPI_6_3_LOCAL_X2APIC_NMI 0x0A
+#define EFI_ACPI_6_3_GIC 0x0B
+#define EFI_ACPI_6_3_GICD 0x0C
+#define EFI_ACPI_6_3_GIC_MSI_FRAME 0x0D
+#define EFI_ACPI_6_3_GICR 0x0E
+#define EFI_ACPI_6_3_GIC_ITS 0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT8 ApicId;
+ UINT32 Flags;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_LOCAL_APIC_ENABLED BIT0
+#define EFI_ACPI_6_3_LOCAL_APIC_ONLINE_CAPABLE BIT1
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 IoApicAddress;
+ UINT32 GlobalSystemInterruptBase;
+} EFI_ACPI_6_3_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Bus;
+ UINT8 Source;
+ UINT32 GlobalSystemInterrupt;
+ UINT16 Flags;
+} EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+ UINT8 CpeiProcessorOverride;
+ UINT8 Reserved[31];
+} EFI_ACPI_6_3_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_POLARITY (3 << 0)
+#define EFI_ACPI_6_3_TRIGGER_MODE (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 GlobalSystemInterrupt;
+} EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorUid;
+ UINT16 Flags;
+ UINT8 LocalApicLint;
+} EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 LocalApicAddress;
+} EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 IoApicId;
+ UINT8 Reserved;
+ UINT32 GlobalSystemInterruptBase;
+ UINT64 IoSapicAddress;
+} EFI_ACPI_6_3_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 AcpiProcessorId;
+ UINT8 LocalSapicId;
+ UINT8 LocalSapicEid;
+ UINT8 Reserved[3];
+ UINT32 Flags;
+ UINT32 ACPIProcessorUIDValue;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT8 InterruptType;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT8 IoSapicVector;
+ UINT32 GlobalSystemInterrupt;
+ UINT32 PlatformInterruptSourceFlags;
+} EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 AcpiProcessorUid;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Flags;
+ UINT32 AcpiProcessorUid;
+ UINT8 LocalX2ApicLint;
+ UINT8 Reserved[3];
+} EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 CPUInterfaceNumber;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ParkingProtocolVersion;
+ UINT32 PerformanceInterruptGsiv;
+ UINT64 ParkedAddress;
+ UINT64 PhysicalBaseAddress;
+ UINT64 GICV;
+ UINT64 GICH;
+ UINT32 VGICMaintenanceInterrupt;
+ UINT64 GICRBaseAddress;
+ UINT64 MPIDR;
+ UINT8 ProcessorPowerEfficiencyClass;
+ UINT8 Reserved2;
+ UINT16 SpeOverflowInterrupt;
+} EFI_ACPI_6_3_GIC_STRUCTURE;
+
+///
+/// GIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GIC_ENABLED BIT0
+#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL BIT1
+#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 SystemVectorBase;
+ UINT8 GicVersion;
+ UINT8 Reserved2[3];
+} EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_3_GIC_V1 0x01
+#define EFI_ACPI_6_3_GIC_V2 0x02
+#define EFI_ACPI_6_3_GIC_V3 0x03
+#define EFI_ACPI_6_3_GIC_V4 0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved1;
+ UINT32 GicMsiFrameId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Flags;
+ UINT16 SPICount;
+ UINT16 SPIBase;
+} EFI_ACPI_6_3_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT64 DiscoveryRangeBaseAddress;
+ UINT32 DiscoveryRangeLength;
+} EFI_ACPI_6_3_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT32 GicItsId;
+ UINT64 PhysicalBaseAddress;
+ UINT32 Reserved2;
+} EFI_ACPI_6_3_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 WarningEnergyLevel;
+ UINT32 LowEnergyLevel;
+ UINT32 CriticalEnergyLevel;
+} EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcControl;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcData;
+ UINT32 Uid;
+ UINT8 GpeBit;
+} EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01
+
+///
+/// System Resource Affinity Table (SRAT). The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved1; ///< Must be set to 1
+ UINT64 Reserved2;
+} EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03
+
+//
+// SRAT structure types.
+// All other values between 0x06 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00
+#define EFI_ACPI_6_3_MEMORY_AFFINITY 0x01
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02
+#define EFI_ACPI_6_3_GICC_AFFINITY 0x03
+#define EFI_ACPI_6_3_GIC_ITS_AFFINITY 0x04
+#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY 0x05
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProximityDomain7To0;
+ UINT8 ApicId;
+ UINT32 Flags;
+ UINT8 LocalSapicEid;
+ UINT8 ProximityDomain31To8[3];
+ UINT32 ClockDomain;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT16 Reserved1;
+ UINT32 AddressBaseLow;
+ UINT32 AddressBaseHigh;
+ UINT32 LengthLow;
+ UINT32 LengthHigh;
+ UINT32 Reserved2;
+ UINT32 Flags;
+ UINT64 Reserved3;
+} EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags. All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_3_MEMORY_ENABLED (1 << 0)
+#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_3_MEMORY_NONVOLATILE (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1[2];
+ UINT32 ProximityDomain;
+ UINT32 X2ApicId;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT32 AcpiProcessorUid;
+ UINT32 Flags;
+ UINT32 ClockDomain;
+} EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 ProximityDomain;
+ UINT8 Reserved[2];
+ UINT32 ItsId;
+} EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE;
+
+//
+// Generic Initiator Affinity Structure Device Handle Types
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE 0x00
+#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE 0x01
+
+///
+/// Device Handle - ACPI
+///
+typedef struct {
+ UINT64 AcpiHid;
+ UINT32 AcpiUid;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_3_DEVICE_HANDLE_ACPI;
+
+///
+/// Device Handle - PCI
+///
+typedef struct {
+ UINT16 PciSegment;
+ UINT16 PciBdfNumber;
+ UINT8 Reserved[12];
+} EFI_ACPI_6_3_DEVICE_HANDLE_PCI;
+
+///
+/// Generic Initiator Affinity Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1;
+ UINT8 DeviceHandleType;
+ UINT32 ProximityDomain;
+
+ union {
+ EFI_ACPI_6_3_DEVICE_HANDLE_ACPI Acpi;
+ EFI_ACPI_6_3_DEVICE_HANDLE_PCI Pci;
+ } DeviceHandle;
+
+ UINT32 Flags;
+ UINT8 Reserved2[4];
+} EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE;
+
+///
+/// Generic Initiator Affinity Structure Flags. All other bits are reserved
+/// and must be 0.
+///
+#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 NumberOfSystemLocalities;
+} EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[8];
+} EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC 0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 ProcessorId;
+ UINT8 ProcessorEid;
+ UINT32 PollingInterval;
+} EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaximumNumberOfProximityDomains;
+ UINT32 MaximumNumberOfClockDomains;
+ UINT64 MaximumPhysicalAddress;
+} EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProximityDomainRangeLow;
+ UINT32 ProximityDomainRangeHigh;
+ UINT32 MaximumProcessorCapacity;
+ UINT64 MaximumMemoryCapacity;
+} EFI_ACPI_6_3_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_3_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT16 Version;
+ UINT8 RASCapabilities[16];
+ UINT8 SetRASCapabilities[16];
+ UINT16 NumberOfRASFParameterBlocks;
+ UINT32 SetRASCapabilitiesStatus;
+} EFI_ACPI_6_3_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_3_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 Version;
+ UINT16 Length;
+ UINT16 PatrolScrubCommand;
+ UINT64 RequestedAddressRange[2];
+ UINT64 ActualAddressRange[2];
+ UINT16 Flags;
+ UINT8 RequestedSpeed;
+} EFI_ACPI_6_3_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 PlatformCommunicationChannelIdentifier;
+ UINT8 Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_6_3_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+ UINT32 Signature;
+ UINT16 Command;
+ UINT16 Status;
+ UINT32 MemoryPowerCommandRegister;
+ UINT32 MemoryPowerStatusRegister;
+ UINT32 PowerStateId;
+ UINT32 MemoryPowerNodeId;
+ UINT64 MemoryEnergyConsumed;
+ UINT64 ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_3_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_3_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+ UINT8 PowerStateValue;
+ UINT8 PowerStateInformationIndex;
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+ UINT8 Flag;
+ UINT8 Reserved;
+ UINT16 MemoryPowerNodeId;
+ UINT32 Length;
+ UINT64 AddressBase;
+ UINT64 AddressLength;
+ UINT32 NumberOfPowerStates;
+ UINT32 NumberOfPhysicalComponents;
+//EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];
+//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04
+
+typedef struct {
+ UINT16 MemoryPowerNodeCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+ UINT8 PowerStateStructureID;
+ UINT8 Flag;
+ UINT16 Reserved;
+ UINT32 AveragePowerConsumedInMPS0;
+ UINT32 RelativePowerSavingToMPS0;
+ UINT64 ExitLatencyToMPS0;
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04
+
+typedef struct {
+ UINT16 MemoryPowerStateCharacteristicsCount;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+ UINT16 Flags;
+ UINT16 Reserved1;
+} EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x1
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 SocketIdentifier;
+ UINT16 Reserved;
+//EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];
+} EFI_ACPI_6_3_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT32 ReadLatency;
+ UINT32 WriteLatency;
+ UINT32 ReadBandwidth;
+ UINT32 WriteBandwidth;
+ UINT16 OptimalAccessUnit;
+ UINT16 OptimalAccessAlignment;
+ UINT16 Reserved;
+ UINT16 NumberOfProximityDomains;
+//UINT32 ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];
+} EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;
+ UINT16 PhysicalComponentIdentifier;
+ UINT16 Reserved;
+ UINT32 SizeOfDimm;
+ UINT32 SmbiosHandle;
+} EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ ///
+ /// 2-bytes (16 bit) version ID. This value must be 1.
+ ///
+ UINT16 Version;
+ ///
+ /// 1-byte status field indicating current status about the table.
+ /// Bits[7:1] = Reserved (must be zero)
+ /// Bit [0] = Valid. A one indicates the boot image graphic is valid.
+ ///
+ UINT8 Status;
+ ///
+ /// 1-byte enumerated type field indicating format of the image.
+ /// 0 = Bitmap
+ /// 1 - 255 Reserved (for future use)
+ ///
+ UINT8 ImageType;
+ ///
+ /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+ /// of the image bitmap.
+ ///
+ UINT64 ImageAddress;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetX;
+ ///
+ /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+ /// (X, Y) display offset of the top left corner of the boot image.
+ /// The top left corner of the display is at offset (0, 0).
+ ///
+ UINT32 ImageOffsetY;
+} EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_3_BGRT_VERSION 0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED 0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_3_BGRT_IMAGE_TYPE_BMP 0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Length;
+ UINT8 Revision;
+} EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+ ///
+ UINT64 BootPerformanceTablePointer;
+} EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// 64-bit processor-relative physical address of the S3 Performance Table.
+ ///
+ UINT64 S3PerformanceTablePointer;
+} EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ UINT32 Reserved;
+ ///
+ /// Timer value logged at the beginning of firmware image execution.
+ /// This may not always be zero or near zero.
+ ///
+ UINT64 ResetEnd;
+ ///
+ /// Timer value logged just prior to loading the OS boot loader into memory.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 OsLoaderLoadImageStart;
+ ///
+ /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+ /// For non-UEFI compatible boots, the timer value logged will be just prior
+ /// to the INT 19h handler invocation.
+ ///
+ UINT64 OsLoaderStartImageStart;
+ ///
+ /// Timer value logged at the point when the OS loader calls the
+ /// ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesEntry;
+ ///
+ /// Timer value logged at the point just prior towhen the OS loader gaining
+ /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+ /// For non-UEFI compatible boots, this field must be zero.
+ ///
+ UINT64 ExitBootServicesExit;
+} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;
+ //
+ // one or more Performance Records.
+ //
+} EFI_ACPI_6_3_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// A count of the number of S3 resume cycles since the last full boot sequence.
+ ///
+ UINT32 ResumeCount;
+ ///
+ /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+ /// OS waking vector. Only the most recent resume cycle's time is retained.
+ ///
+ UINT64 FullResume;
+ ///
+ /// Average timer value of all resume cycles logged since the last full boot
+ /// sequence, including the most recent resume. Note that the entire log of
+ /// timer values does not need to be retained in order to calculate this average.
+ ///
+ UINT64 AverageResume;
+} EFI_ACPI_6_3_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;
+ ///
+ /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendStart;
+ ///
+ /// Timer value recorded at the final firmware write to SLP_TYP (or other
+ /// mechanism) used to trigger hardware entry to S3.
+ /// Only the most recent suspend cycle's timer value is retained.
+ ///
+ UINT64 SuspendEnd;
+} EFI_ACPI_6_3_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 CntControlBasePhysicalAddress;
+ UINT32 Reserved;
+ UINT32 SecurePL1TimerGSIV;
+ UINT32 SecurePL1TimerFlags;
+ UINT32 NonSecurePL1TimerGSIV;
+ UINT32 NonSecurePL1TimerFlags;
+ UINT32 VirtualTimerGSIV;
+ UINT32 VirtualTimerFlags;
+ UINT32 NonSecurePL2TimerGSIV;
+ UINT32 NonSecurePL2TimerFlags;
+ UINT64 CntReadBasePhysicalAddress;
+ UINT32 PlatformTimerCount;
+ UINT32 PlatformTimerOffset;
+ UINT32 VirtualPL2TimerGSIV;
+ UINT32 VirtualPL2TimerFlags;
+} EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK 0
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG 1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 CntCtlBase;
+ UINT32 GTBlockTimerCount;
+ UINT32 GTBlockTimerOffset;
+} EFI_ACPI_6_3_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+ UINT8 GTFrameNumber;
+ UINT8 Reserved[3];
+ UINT64 CntBaseX;
+ UINT64 CntEL0BaseX;
+ UINT32 GTxPhysicalTimerGSIV;
+ UINT32 GTxPhysicalTimerFlags;
+ UINT32 GTxVirtualTimerGSIV;
+ UINT32 GTxVirtualTimerFlags;
+ UINT32 GTxCommonFlags;
+} EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+
+///
+/// Common Flags Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Reserved;
+ UINT64 RefreshFramePhysicalAddress;
+ UINT64 WatchdogControlFramePhysicalAddress;
+ UINT32 WatchdogTimerGSIV;
+ UINT32 WatchdogTimerFlags;
+} EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved;
+} EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.3 spec.)
+//
+#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1
+#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE 2
+#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4
+#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5
+#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+} EFI_ACPI_6_3_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1
+#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 SPARangeStructureIndex;
+ UINT16 Flags;
+ UINT32 Reserved_8;
+ UINT32 ProximityDomain;
+ GUID AddressRangeTypeGUID;
+ UINT64 SystemPhysicalAddressRangeBase;
+ UINT64 SystemPhysicalAddressRangeLength;
+ UINT64 AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+ UINT32 DIMMNumber:4;
+ UINT32 MemoryChannelNumber:4;
+ UINT32 MemoryControllerID:4;
+ UINT32 SocketID:4;
+ UINT32 NodeControllerID:12;
+ UINT32 Reserved_28:4;
+} EFI_ACPI_6_3_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NVDIMMPhysicalID;
+ UINT16 NVDIMMRegionID;
+ UINT16 SPARangeStructureIndex ;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT64 NVDIMMRegionSize;
+ UINT64 RegionOffset;
+ UINT64 NVDIMMPhysicalAddressRegionBase;
+ UINT16 InterleaveStructureIndex;
+ UINT16 InterleaveWays;
+ UINT16 NVDIMMStateFlags;
+ UINT16 Reserved_46;
+} EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 InterleaveStructureIndex;
+ UINT16 Reserved_6;
+ UINT32 NumberOfLines;
+ UINT32 LineSize;
+//UINT32 LineOffset[NumberOfLines];
+} EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT32 Reserved_4;
+//UINT8 Data[];
+} EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0
+
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT8 ValidFields;
+ UINT8 ManufacturingLocation;
+ UINT16 ManufacturingDate;
+ UINT8 Reserved_22[2];
+ UINT32 SerialNumber;
+ UINT16 RegionFormatInterfaceCode;
+ UINT16 NumberOfBlockControlWindows;
+ UINT64 SizeOfBlockControlWindow;
+ UINT64 CommandRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;
+ UINT64 StatusRegisterOffsetInBlockControlWindow;
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;
+ UINT16 NVDIMMControlRegionFlag;
+ UINT8 Reserved_74[6];
+} EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 NVDIMMControlRegionStructureIndex;
+ UINT16 NumberOfBlockDataWindows;
+ UINT64 BlockDataWindowStartOffset;
+ UINT64 SizeOfBlockDataWindow;
+ UINT64 BlockAccessibleMemoryCapacity;
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;
+ UINT16 NumberOfFlushHintAddresses;
+ UINT8 Reserved_10[6];
+//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_3_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION 0x01
+
+///
+/// Secure Devcice types
+///
+#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01
+#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00
+
+///
+/// Secure Devcice flags
+///
+#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF BIT0
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_HEADER;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 PciSegmentNumber;
+ UINT16 StartBusNumber;
+ UINT16 PciPathOffset;
+ UINT16 PciPathLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Flags;
+ UINT16 Length;
+ UINT16 DeviceIdentifierOffset;
+ UINT16 DeviceIdentifierLength;
+ UINT16 VendorSpecificDataOffset;
+ UINT16 VendorSpecificDataLength;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 BootErrorRegionLength;
+ UINT64 BootErrorRegion;
+} EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+ UINT32 UncorrectableErrorValid:1;
+ UINT32 CorrectableErrorValid:1;
+ UINT32 MultipleUncorrectableErrors:1;
+ UINT32 MultipleCorrectableErrors:1;
+ UINT32 ErrorDataEntryCount:10;
+ UINT32 Reserved:18;
+} EFI_ACPI_6_3_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+ EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_3_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTABLE 0x00
+#define EFI_ACPI_6_3_ERROR_SEVERITY_FATAL 0x01
+#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTED 0x02
+#define EFI_ACPI_6_3_ERROR_SEVERITY_NONE 0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+ UINT8 SectionType[16];
+ UINT32 ErrorSeverity;
+ UINT16 Revision;
+ UINT8 ValidationBits;
+ UINT8 Flags;
+ UINT32 ErrorDataLength;
+ UINT8 FruId[16];
+ UINT8 FruText[20];
+ UINT8 Timestamp[8];
+} EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 ErrorSourceCount;
+} EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR 0x02
+#define EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER 0x06
+#define EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER 0x07
+#define EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER 0x08
+#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR 0x09
+#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT64 GlobalCapabilityInitData;
+ UINT64 GlobalControlInitData;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[7];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+ UINT8 BankNumber;
+ UINT8 ClearStatusOnInitialization;
+ UINT8 StatusDataFormat;
+ UINT8 Reserved0;
+ UINT32 ControlRegisterMsrAddress;
+ UINT64 ControlInitData;
+ UINT32 StatusRegisterMsrAddress;
+ UINT32 AddressRegisterMsrAddress;
+ UINT32 MiscRegisterMsrAddress;
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI 0x03
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI 0x04
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE 0x06
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+ UINT16 Type:1;
+ UINT16 PollInterval:1;
+ UINT16 SwitchToPollingThresholdValue:1;
+ UINT16 SwitchToPollingThresholdWindow:1;
+ UINT16 ErrorThresholdValue:1;
+ UINT16 ErrorThresholdWindow:1;
+ UINT16 Reserved:10;
+} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;
+ UINT32 PollInterval;
+ UINT32 Vector;
+ UINT32 SwitchToPollingThresholdValue;
+ UINT32 SwitchToPollingThresholdWindow;
+ UINT32 ErrorThresholdValue;
+ UINT32 ErrorThresholdWindow;
+} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 RootErrorCommand;
+} EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 Bus;
+ UINT16 Device;
+ UINT16 Function;
+ UINT16 DeviceControl;
+ UINT8 Reserved1[2];
+ UINT32 UncorrectableErrorMask;
+ UINT32 UncorrectableErrorSeverity;
+ UINT32 CorrectableErrorMask;
+ UINT32 AdvancedErrorCapabilitiesAndControl;
+ UINT32 SecondaryUncorrectableErrorMask;
+ UINT32 SecondaryUncorrectableErrorSeverity;
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT16 RelatedSourceId;
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ UINT32 MaxRawDataLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT32 ErrorStatusBlockLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;
+ UINT64 ReadAckPreserve;
+ UINT64 ReadAckWrite;
+} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+ EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;
+ UINT32 RawDataOffset;
+ UINT32 RawDataLength;
+ UINT32 DataLength;
+ UINT32 ErrorSeverity;
+} EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+ UINT16 Type;
+ UINT16 SourceId;
+ UINT8 Reserved0[2];
+ UINT8 Flags;
+ UINT8 Enabled;
+ UINT32 NumberOfRecordsToPreAllocate;
+ UINT32 MaxSectionsPerRecord;
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;
+ UINT8 NumberOfHardwareBanks;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 Reserved[4];
+} EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00
+#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Proximity Domain Attributes Structure flags
+///
+typedef struct {
+ UINT16 InitiatorProximityDomainValid:1;
+ UINT16 Reserved:15;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;
+
+///
+/// Memory Proximity Domain Attributes Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;
+ UINT8 Reserved1[2];
+ UINT32 InitiatorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved2[20];
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+ UINT8 MemoryHierarchy:4;
+ UINT8 Reserved:4;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
+ UINT8 DataType;
+ UINT8 Reserved1[2];
+ UINT32 NumberOfInitiatorProximityDomains;
+ UINT32 NumberOfTargetProximityDomains;
+ UINT8 Reserved2[4];
+ UINT64 EntryBaseUnit;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+ UINT32 TotalCacheLevels:4;
+ UINT32 CacheLevel:4;
+ UINT32 CacheAssociativity:4;
+ UINT32 WritePolicy:4;
+ UINT32 CacheLineSize:16;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+ UINT16 Type;
+ UINT8 Reserved[2];
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT8 Reserved1[4];
+ UINT64 MemorySideCacheSize;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;
+ UINT8 Reserved2[2];
+ UINT16 NumberOfSmbiosHandles;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 SerializationHeaderSize;
+ UINT8 Reserved0[4];
+ UINT32 InstructionEntryCount;
+} EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION 0x00
+#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION 0x01
+#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION 0x02
+#define EFI_ACPI_6_3_ERST_END_OPERATION 0x03
+#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET 0x04
+#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER 0x08
+#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER 0x09
+#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT 0x0A
+#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F
+#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE 0x01
+#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02
+#define EFI_ACPI_6_3_ERST_STATUS_FAILED 0x03
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY 0x04
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND 0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_3_ERST_READ_REGISTER 0x00
+#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_3_ERST_NOOP 0x04
+#define EFI_ACPI_6_3_ERST_LOAD_VAR1 0x05
+#define EFI_ACPI_6_3_ERST_LOAD_VAR2 0x06
+#define EFI_ACPI_6_3_ERST_STORE_VAR1 0x07
+#define EFI_ACPI_6_3_ERST_ADD 0x08
+#define EFI_ACPI_6_3_ERST_SUBTRACT 0x09
+#define EFI_ACPI_6_3_ERST_ADD_VALUE 0x0A
+#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE 0x0B
+#define EFI_ACPI_6_3_ERST_STALL 0x0C
+#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE 0x0D
+#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E
+#define EFI_ACPI_6_3_ERST_GOTO 0x0F
+#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE 0x10
+#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE 0x11
+#define EFI_ACPI_6_3_ERST_MOVE_DATA 0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER 0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+ UINT8 SerializationAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_3_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 InjectionHeaderSize;
+ UINT8 InjectionFlags;
+ UINT8 Reserved0[3];
+ UINT32 InjectionEntryCount;
+} EFI_ACPI_6_3_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION 0x00
+#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01
+#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE 0x02
+#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE 0x03
+#define EFI_ACPI_6_3_EINJ_END_OPERATION 0x04
+#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05
+#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06
+#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS 0x00
+#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE 0x01
+#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS 0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER 0x00
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE 0x01
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER 0x02
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE 0x03
+#define EFI_ACPI_6_3_EINJ_NOOP 0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER 0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+ UINT8 InjectionAction;
+ UINT8 Instruction;
+ UINT8 Flags;
+ UINT8 Reserved0;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
+ UINT64 Value;
+ UINT64 Mask;
+} EFI_ACPI_6_3_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+ UINT32 HeaderSize;
+ UINT32 Revision;
+ UINT32 TableSize;
+ UINT32 EntryCount;
+} EFI_ACPI_6_3_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Flags;
+ UINT64 Reserved;
+} EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_3_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC 0x00
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[6];
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+ UINT8 Command;
+ UINT8 Reserved:7;
+ UINT8 NotifyOnCompletion:1;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+ UINT8 CommandComplete:1;
+ UINT8 PlatformInterrupt:1;
+ UINT8 Error:1;
+ UINT8 PlatformNotification:1;
+ UINT8 Reserved:4;
+ UINT8 Reserved1;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;
+ EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT64 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT16 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckWrite;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT32 PlatformInterrupt;
+ UINT8 PlatformInterruptFlags;
+ UINT8 Reserved;
+ UINT64 BaseAddress;
+ UINT32 AddressLength;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;
+ UINT64 DoorbellPreserve;
+ UINT64 DoorbellWrite;
+ UINT32 NominalLatency;
+ UINT32 MaximumPeriodicAccessRate;
+ UINT32 MinimumRequestTurnaroundTime;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;
+ UINT64 PlatformInterruptAckPreserve;
+ UINT64 PlatformInterruptAckSet;
+ UINT8 Reserved1[8];
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;
+ UINT64 CommandCompleteCheckMask;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;
+ UINT64 CommandCompleteUpdatePreserve;
+ UINT64 CommandCompleteUpdateSet;
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;
+ UINT64 ErrorStatusMask;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_3_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 Command;
+} EFI_ACPI_6_3_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 TriggerCount;
+ UINT8 Reserved[3];
+ UINT32 TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+ UINT16 SubChannelIdentifer:8;
+ UINT16 Runtime:1;
+ UINT16 WaitForCompletion:1;
+ UINT16 TriggerOrder:1;
+ UINT16 Reserved:5;
+} EFI_ACPI_6_3_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01
+
+///
+/// PPTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_3_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR 0x00
+#define EFI_ACPI_6_3_PPTT_TYPE_CACHE 0x01
+#define EFI_ACPI_6_3_PPTT_TYPE_ID 0x02
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+} EFI_ACPI_6_3_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL 0x0
+#define EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL 0x1
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD 0x0
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD 0x1
+#define EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF 0x0
+#define EFI_ACPI_6_3_PPTT_NODE_IS_LEAF 0x1
+#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0
+#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL 0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+ UINT32 PhysicalPackage:1;
+ UINT32 AcpiProcessorIdValid:1;
+ UINT32 ProcessorIsAThread:1;
+ UINT32 NodeIsALeaf:1;
+ UINT32 IdenticalImplementation:1;
+ UINT32 Reserved:27;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;
+ UINT32 Parent;
+ UINT32 AcpiProcessorId;
+ UINT32 NumberOfPrivateResources;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// For PPTT struct cache flags
+///
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID 0x1
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID 0x0
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID 0x1
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+ UINT32 SizePropertyValid:1;
+ UINT32 NumberOfSetsValid:1;
+ UINT32 AssociativityValid:1;
+ UINT32 AllocationTypeValid:1;
+ UINT32 CacheTypeValid:1;
+ UINT32 WritePolicyValid:1;
+ UINT32 LineSizeValid:1;
+ UINT32 Reserved:25;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+ UINT8 AllocationType:2;
+ UINT8 CacheType:2;
+ UINT8 WritePolicy:1;
+ UINT8 Reserved:3;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS Flags;
+ UINT32 NextLevelOfCache;
+ UINT32 Size;
+ UINT32 NumberOfSets;
+ UINT8 Associativity;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
+ UINT16 LineSize;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE;
+
+///
+/// ID structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved[2];
+ UINT32 VendorId;
+ UINT64 Level1Id;
+ UINT64 Level2Id;
+ UINT16 MajorRev;
+ UINT16 MinorRev;
+ UINT16 SpinRev;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_ID;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CDIT" Component Distance Information Table
+///
+#define EFI_ACPI_6_3_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "CRAT" Component Resource Attribute Table
+///
+#define EFI_ACPI_6_3_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_3_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_3_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_3_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_3_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_3_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_3_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_3_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_3_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_3_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DPPT" DMA Protection Policy Table
+///
+#define EFI_ACPI_6_3_DMA_PROTECTION_POLICY_TABLE_SIGNATURE SIGNATURE_32('D', 'P', 'P', 'T')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_3_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_3_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_3_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_3_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_3_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_3_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_3_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_3_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_3_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_3_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_3_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_3_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_3_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_3_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_3_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_3_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_3_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_3_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_3_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/AcpiAml.h b/MdePkg/Include/IndustryStandard/AcpiAml.h
index 19d9684943eb..cba5848cb400 100644
--- a/MdePkg/Include/IndustryStandard/AcpiAml.h
+++ b/MdePkg/Include/IndustryStandard/AcpiAml.h
@@ -2,13 +2,8 @@
This file contains AML code definition in the latest ACPI spec.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2019, ARM Limited. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -36,6 +31,7 @@
#define AML_PACKAGE_OP 0x12
#define AML_VAR_PACKAGE_OP 0x13
#define AML_METHOD_OP 0x14
+#define AML_EXTERNAL_OP 0x15
#define AML_DUAL_NAME_PREFIX 0x2e
#define AML_MULTI_NAME_PREFIX 0x2f
#define AML_NAME_CHAR_A 0x41
@@ -172,4 +168,12 @@
#define AML_EXT_BANK_FIELD_OP 0x87
#define AML_EXT_DATA_REGION_OP 0x88
+//
+// FieldElement OpCode
+//
+#define AML_FIELD_RESERVED_OP 0x00
+#define AML_FIELD_ACCESS_OP 0x01
+#define AML_FIELD_CONNECTION_OP 0x02
+#define AML_FIELD_EXT_ACCESS_OP 0x03
+
#endif
diff --git a/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h b/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
index e7658541a3e4..8bb3ca66504b 100644
--- a/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
+++ b/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
@@ -1,14 +1,8 @@
-/** @file
+/** @file
ACPI Alert Standard Format Description Table ASF! as described in the ASF2.0 Specification
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _ALERT_STANDARD_FORMAT_TABLE_H_
@@ -31,7 +25,7 @@ typedef struct {
} EFI_ACPI_ASF_RECORD_HEADER;
///
-/// This structure contains information that identifies the system's type
+/// This structure contains information that identifies the system's type
/// and configuration
///
typedef struct {
@@ -84,7 +78,7 @@ typedef struct {
UINT8 DeviceAddress;
UINT8 Command;
UINT8 DataValue;
-} EFI_ACPI_ASF_CONTROLDATA;
+} EFI_ACPI_ASF_CONTROLDATA;
///
/// Alert Remote Control System Actions
diff --git a/MdePkg/Include/IndustryStandard/Atapi.h b/MdePkg/Include/IndustryStandard/Atapi.h
index cb1fae429f09..a886f59e3cb5 100644
--- a/MdePkg/Include/IndustryStandard/Atapi.h
+++ b/MdePkg/Include/IndustryStandard/Atapi.h
@@ -2,14 +2,8 @@
This file contains just some basic definitions that are needed by drivers
that dealing with ATA/ATAPI interface.
-Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -21,59 +15,59 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// ATA5_IDENTIFY_DATA is defined in ATA-5.
/// (This structure is provided mainly for backward-compatibility support.
-/// Old drivers may reference fields that are marked "obsolete" in
-/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)
+/// Old drivers may reference fields that are marked "obsolete" in
+/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)
///
-typedef struct {
+typedef struct {
UINT16 config; ///< General Configuration.
UINT16 cylinders; ///< Number of Cylinders.
- UINT16 reserved_2;
- UINT16 heads; ///< Number of logical heads.
- UINT16 vendor_data1;
- UINT16 vendor_data2;
- UINT16 sectors_per_track;
- UINT16 vendor_specific_7_9[3];
- CHAR8 SerialNo[20]; ///< ASCII
- UINT16 vendor_specific_20_21[2];
- UINT16 ecc_bytes_available;
- CHAR8 FirmwareVer[8]; ///< ASCII
- CHAR8 ModelName[40]; ///< ASCII
- UINT16 multi_sector_cmd_max_sct_cnt;
- UINT16 reserved_48;
- UINT16 capabilities;
- UINT16 reserved_50;
- UINT16 pio_cycle_timing;
- UINT16 reserved_52;
- UINT16 field_validity;
- UINT16 current_cylinders;
- UINT16 current_heads;
- UINT16 current_sectors;
- UINT16 CurrentCapacityLsb;
- UINT16 CurrentCapacityMsb;
- UINT16 reserved_59;
- UINT16 user_addressable_sectors_lo;
- UINT16 user_addressable_sectors_hi;
- UINT16 reserved_62;
- UINT16 multi_word_dma_mode;
- UINT16 advanced_pio_modes;
- UINT16 min_multi_word_dma_cycle_time;
- UINT16 rec_multi_word_dma_cycle_time;
- UINT16 min_pio_cycle_time_without_flow_control;
- UINT16 min_pio_cycle_time_with_flow_control;
- UINT16 reserved_69_79[11];
- UINT16 major_version_no;
- UINT16 minor_version_no;
- UINT16 command_set_supported_82; ///< word 82
- UINT16 command_set_supported_83; ///< word 83
- UINT16 command_set_feature_extn; ///< word 84
- UINT16 command_set_feature_enb_85; ///< word 85
- UINT16 command_set_feature_enb_86; ///< word 86
- UINT16 command_set_feature_default; ///< word 87
- UINT16 ultra_dma_mode; ///< word 88
- UINT16 reserved_89_127[39];
- UINT16 security_status;
- UINT16 vendor_data_129_159[31];
- UINT16 reserved_160_255[96];
+ UINT16 reserved_2;
+ UINT16 heads; ///< Number of logical heads.
+ UINT16 vendor_data1;
+ UINT16 vendor_data2;
+ UINT16 sectors_per_track;
+ UINT16 vendor_specific_7_9[3];
+ CHAR8 SerialNo[20]; ///< ASCII
+ UINT16 vendor_specific_20_21[2];
+ UINT16 ecc_bytes_available;
+ CHAR8 FirmwareVer[8]; ///< ASCII
+ CHAR8 ModelName[40]; ///< ASCII
+ UINT16 multi_sector_cmd_max_sct_cnt;
+ UINT16 reserved_48;
+ UINT16 capabilities;
+ UINT16 reserved_50;
+ UINT16 pio_cycle_timing;
+ UINT16 reserved_52;
+ UINT16 field_validity;
+ UINT16 current_cylinders;
+ UINT16 current_heads;
+ UINT16 current_sectors;
+ UINT16 CurrentCapacityLsb;
+ UINT16 CurrentCapacityMsb;
+ UINT16 reserved_59;
+ UINT16 user_addressable_sectors_lo;
+ UINT16 user_addressable_sectors_hi;
+ UINT16 reserved_62;
+ UINT16 multi_word_dma_mode;
+ UINT16 advanced_pio_modes;
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 reserved_69_79[11];
+ UINT16 major_version_no;
+ UINT16 minor_version_no;
+ UINT16 command_set_supported_82; ///< word 82
+ UINT16 command_set_supported_83; ///< word 83
+ UINT16 command_set_feature_extn; ///< word 84
+ UINT16 command_set_feature_enb_85; ///< word 85
+ UINT16 command_set_feature_enb_86; ///< word 86
+ UINT16 command_set_feature_default; ///< word 87
+ UINT16 ultra_dma_mode; ///< word 88
+ UINT16 reserved_89_127[39];
+ UINT16 security_status;
+ UINT16 vendor_data_129_159[31];
+ UINT16 reserved_160_255[96];
} ATA5_IDENTIFY_DATA;
///
@@ -86,50 +80,50 @@ typedef struct {
UINT16 obsolete_1;
UINT16 specific_config; ///< Specific Configuration.
UINT16 obsolete_3;
- UINT16 retired_4_5[2];
+ UINT16 retired_4_5[2];
UINT16 obsolete_6;
UINT16 cfa_reserved_7_8[2];
- UINT16 retired_9;
+ UINT16 retired_9;
CHAR8 SerialNo[20]; ///< word 10~19
- UINT16 retired_20_21[2];
- UINT16 obsolete_22;
+ UINT16 retired_20_21[2];
+ UINT16 obsolete_22;
CHAR8 FirmwareVer[8]; ///< word 23~26
CHAR8 ModelName[40]; ///< word 27~46
UINT16 multi_sector_cmd_max_sct_cnt;
- UINT16 trusted_computing_support;
+ UINT16 trusted_computing_support;
UINT16 capabilities_49;
UINT16 capabilities_50;
- UINT16 obsolete_51_52[2];
- UINT16 field_validity;
- UINT16 obsolete_54_58[5];
+ UINT16 obsolete_51_52[2];
+ UINT16 field_validity;
+ UINT16 obsolete_54_58[5];
UINT16 multi_sector_setting;
- UINT16 user_addressable_sectors_lo;
- UINT16 user_addressable_sectors_hi;
- UINT16 obsolete_62;
- UINT16 multi_word_dma_mode;
- UINT16 advanced_pio_modes;
- UINT16 min_multi_word_dma_cycle_time;
- UINT16 rec_multi_word_dma_cycle_time;
- UINT16 min_pio_cycle_time_without_flow_control;
- UINT16 min_pio_cycle_time_with_flow_control;
+ UINT16 user_addressable_sectors_lo;
+ UINT16 user_addressable_sectors_hi;
+ UINT16 obsolete_62;
+ UINT16 multi_word_dma_mode;
+ UINT16 advanced_pio_modes;
+ UINT16 min_multi_word_dma_cycle_time;
+ UINT16 rec_multi_word_dma_cycle_time;
+ UINT16 min_pio_cycle_time_without_flow_control;
+ UINT16 min_pio_cycle_time_with_flow_control;
UINT16 additional_supported; ///< word 69
UINT16 reserved_70;
UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd.
- UINT16 queue_depth;
+ UINT16 queue_depth;
UINT16 serial_ata_capabilities;
UINT16 reserved_77; ///< Reserved for Serial ATA
UINT16 serial_ata_features_supported;
UINT16 serial_ata_features_enabled;
- UINT16 major_version_no;
- UINT16 minor_version_no;
+ UINT16 major_version_no;
+ UINT16 minor_version_no;
UINT16 command_set_supported_82; ///< word 82
UINT16 command_set_supported_83; ///< word 83
UINT16 command_set_feature_extn; ///< word 84
UINT16 command_set_feature_enb_85; ///< word 85
UINT16 command_set_feature_enb_86; ///< word 86
UINT16 command_set_feature_default; ///< word 87
- UINT16 ultra_dma_mode; ///< word 88
- UINT16 time_for_security_erase_unit;
+ UINT16 ultra_dma_mode; ///< word 88
+ UINT16 time_for_security_erase_unit;
UINT16 time_for_enhanced_security_erase_unit;
UINT16 advanced_power_management_level;
UINT16 master_password_identifier;
@@ -154,7 +148,7 @@ typedef struct {
UINT16 reserved_121_126[6];
UINT16 obsolete_127;
UINT16 security_status; ///< word 128
- UINT16 vendor_specific_129_159[31];
+ UINT16 vendor_specific_129_159[31];
UINT16 cfa_power_mode; ///< word 160
UINT16 reserved_for_compactflash_161_167[7];
UINT16 device_nominal_form_factor;
@@ -239,7 +233,7 @@ typedef struct {
UINT16 reserved_95_107[13];
UINT16 world_wide_name[4]; ///< word 108~111
UINT16 reserved_for_128bit_wwn_112_115[4];
- UINT16 reserved_116_118[3];
+ UINT16 reserved_116_118[3];
UINT16 command_and_feature_sets_supported; ///< word 119
UINT16 command_and_feature_sets_supported_enabled;
UINT16 reserved_121_124[4];
@@ -458,7 +452,7 @@ typedef struct {
///
/// ATAPI_PACKET_COMMAND is not defined in the ATA specification.
-/// We add it here for the convenience of ATA/ATAPI module writers.
+/// We add it here for the convenience of ATA/ATAPI module writers.
///
typedef union {
UINT16 Data16[6];
@@ -477,7 +471,7 @@ typedef union {
#define ATAPI_MAX_DMA_CMD_SECTORS 0x100
// ATA/ATAPI Signature equates
-#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3
+#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3
#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3
#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3
@@ -490,42 +484,42 @@ typedef union {
//
// ATA Packet Command Code
//
-#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3
#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3
#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3
#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3
#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1
#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4
-#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devcies
-
-#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devcies
- #define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devcies
- #define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devcies
- #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devcies
- #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devcies
- #define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices
+
+#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices
+ #define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices
+ #define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices
+ #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices
+ #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices
+ #define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices
#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices
#define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices
- #define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices
- #define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices
-
+ #define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices
+ #define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices
+
#define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices
- #define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices
+ #define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices
#define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices
@@ -549,33 +543,33 @@ typedef union {
//
#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3
#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1
-#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1
+#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1
#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6
-#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3
-#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3
-#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3
+#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3
+#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3
+#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3
//
// Class 2: PIO Data-Out Commands
//
#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1
+#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1
#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1
#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6
-#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3
-#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3
+#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3
+#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3
//
// Class 3 No Data Command
//
-#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5
+#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5
#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3
#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3
#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4
@@ -599,39 +593,39 @@ typedef union {
#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1
#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4
#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1
-#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6
+#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6
//
// Set Features Sub Command
//
-#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3
-#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3
-#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3
-#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3
-#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3
-#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3
-#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3
+#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3
+#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3
+#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3
+#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3
+#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3
+#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3
//
// S.M.A.R.T
@@ -640,13 +634,13 @@ typedef union {
#define ATA_CONSTANT_C2 0xc2 ///< reserved
#define ATA_CONSTANT_4F 0x4f ///< reserved
-#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3
+#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3
-#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3
+#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3
#define ATA_AUTOSAVE_DISABLE_ATTR 0x00
#define ATA_AUTOSAVE_ENABLE_ATTR 0xf1
-#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3
+#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3
@@ -658,25 +652,25 @@ typedef union {
#define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3
#define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3
-#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3
-#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3
+#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3
+#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3
#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved
-#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3
+#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3
#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3
-#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3
-#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3
+#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3
+#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3
// SMART Log Definitions
-#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3
-#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3
-#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3
-#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3
-#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3
-#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3
-#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3
-#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3
-#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3
+#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3
+#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3
+#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3
+#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3
+#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3
+#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3
+#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3
+#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3
+#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3
//
// Class 4: DMA Command
@@ -687,18 +681,18 @@ typedef union {
#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1
#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA-
#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6
-
+
//
// ATA Security commands
//
-#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3
-#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3
+#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3
-#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3
+#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3
//
// ATA Device Config Overlay
@@ -712,19 +706,19 @@ typedef union {
//
// ATA Trusted Computing Feature Set Commands
//
-#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3
//
// ATA Trusted Receive Fields
//
-#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3
+#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3
//
// Equates used for Acoustic Flags
@@ -732,18 +726,18 @@ typedef union {
#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6
#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6
#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6
-
+
//
// Equates used for DiPM Support
//
-#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions
- #define ATA_DIPM_ENABLE 0x10 // defined in ACS-3
- #define ATA_DIPM_DISABLE 0x90 // defined in ACS-3
+#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions
+ #define ATA_DIPM_ENABLE 0x10 // defined in ACS-3
+ #define ATA_DIPM_DISABLE 0x90 // defined in ACS-3
//
// Equates used for DevSleep Support
//
-#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep
+#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep
#define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec
#define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec
@@ -765,7 +759,7 @@ typedef union {
/// Default content of device control register, disable INT,
/// Bit3 is set to 1 according ATA-1
///
-#define ATA_DEFAULT_CTL (0x0a)
+#define ATA_DEFAULT_CTL (0x0a)
///
/// Default context of Device/Head Register,
/// Bit7 and Bit5 are set to 1 for back-compatibilities.
@@ -778,9 +772,9 @@ typedef union {
//
// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier
-// defined in MultiMedia Commands (MMC, MMC-2)
+// defined in MultiMedia Commands (MMC, MMC-2)
//
-// Sense Key
+// Sense Key
//
#define ATA_SK_NO_SENSE (0x0)
#define ATA_SK_RECOVERY_ERROR (0x1)
@@ -825,7 +819,7 @@ typedef union {
//
// Error Register
-//
+//
#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2
#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4
#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4
diff --git a/MdePkg/Include/IndustryStandard/Bluetooth.h b/MdePkg/Include/IndustryStandard/Bluetooth.h
index f4b7372d5482..96940129ff7c 100644
--- a/MdePkg/Include/IndustryStandard/Bluetooth.h
+++ b/MdePkg/Include/IndustryStandard/Bluetooth.h
@@ -2,14 +2,8 @@
This file contains the Bluetooth definitions that are consumed by drivers.
These definitions are from Bluetooth Core Specification Version 4.0 June, 2010
- Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -38,6 +32,21 @@ typedef struct {
UINT16 MajorServiceClass:11;
} BLUETOOTH_CLASS_OF_DEVICE;
+///
+/// BLUETOOTH_LE_ADDRESS
+///
+typedef struct {
+ ///
+ /// 48-bit Bluetooth device address
+ ///
+ UINT8 Address[6];
+ ///
+ /// 0x00 - Public Device Address
+ /// 0x01 - Random Device Address
+ ///
+ UINT8 Type;
+} BLUETOOTH_LE_ADDRESS;
+
#pragma pack()
#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248
diff --git a/MdePkg/Include/IndustryStandard/Bmp.h b/MdePkg/Include/IndustryStandard/Bmp.h
index 25393911c42c..36f719403662 100644
--- a/MdePkg/Include/IndustryStandard/Bmp.h
+++ b/MdePkg/Include/IndustryStandard/Bmp.h
@@ -2,13 +2,7 @@
This file defines BMP file header data structures.
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/DebugPort2Table.h b/MdePkg/Include/IndustryStandard/DebugPort2Table.h
index 03331069fc29..5f8fc82b69b8 100644
--- a/MdePkg/Include/IndustryStandard/DebugPort2Table.h
+++ b/MdePkg/Include/IndustryStandard/DebugPort2Table.h
@@ -1,16 +1,10 @@
-/** @file
- ACPI debug port 2 table definition, defined at
+/** @file
+ ACPI debug port 2 table definition, defined at
Microsoft DebugPort2Specification.
- Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/DebugPortTable.h b/MdePkg/Include/IndustryStandard/DebugPortTable.h
index 99791c513311..1aaea8ec5264 100644
--- a/MdePkg/Include/IndustryStandard/DebugPortTable.h
+++ b/MdePkg/Include/IndustryStandard/DebugPortTable.h
@@ -1,15 +1,9 @@
-/** @file
- ACPI debug port table definition, defined at
+/** @file
+ ACPI debug port table definition, defined at
Microsoft DebugPortSpecification.
- Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/IndustryStandard/Dhcp.h
index 9f09753624e4..f51bb93c3178 100644
--- a/MdePkg/Include/IndustryStandard/Dhcp.h
+++ b/MdePkg/Include/IndustryStandard/Dhcp.h
@@ -3,13 +3,8 @@
They are used to carry additional information and parameters in DHCP messages.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _DHCP_H_
@@ -272,11 +267,17 @@ typedef enum {
#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
+#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
#endif
diff --git a/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h b/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
index 9c9afb358c4f..3e5aadc4a831 100644
--- a/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
+++ b/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
@@ -2,18 +2,12 @@
DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)
Virtualization Technology for Directed I/O (VT-D) Architecture Specification.
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture
- Specification v2.4, Dated June 2016.
+ Specification v2.5, Dated November 2017.
http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
@par Glossary:
@@ -23,15 +17,18 @@
#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_
#define _DMA_REMAPPING_REPORTING_TABLE_H_
+#include <IndustryStandard/Acpi.h>
+
#pragma pack(1)
///
/// DMA-Remapping Reporting Structure definitions from section 8.1
///@{
-#define EFI_ACPI_DMAR_REVISION 0x01
+#define EFI_ACPI_DMAR_REVISION 0x01
-#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0
-#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1
+#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0
+#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1
+#define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG BIT2
///@}
///
@@ -250,7 +247,12 @@ typedef struct {
firmware may Set this field to request system software to opt
out of enabling Extended xAPIC (X2APIC) mode. This field is
valid only when the INTR_REMAP field (bit 0) is Set.
- - Bits[7:2] Reserved.
+ - Bit[2]: DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is
+ recommended to Set this field to report any platform initiated
+ DMA is restricted to only reserved memory regions (reported in
+ RMRR structures) when transferring control to system software
+ such as on ExitBootServices().
+ - Bits[7:3] Reserved.
**/
UINT8 Flags;
UINT8 Reserved[10];
diff --git a/MdePkg/Include/IndustryStandard/ElTorito.h b/MdePkg/Include/IndustryStandard/ElTorito.h
index 3a3d018ac7d3..e9b870f77801 100644
--- a/MdePkg/Include/IndustryStandard/ElTorito.h
+++ b/MdePkg/Include/IndustryStandard/ElTorito.h
@@ -1,18 +1,12 @@
/** @file
- ElTorito Partitions Format Definition.
- This file includes some defintions from
+ ElTorito Partitions Format Definition.
+ This file includes some definitions from
1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0.
- 2. Volume and File Structure of CDROM for Information Interchange,
+ 2. Volume and File Structure of CDROM for Information Interchange,
Standard ECMA-119. (IS0 9660)
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -57,13 +51,13 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#pragma pack(1)
-///
+///
/// CD-ROM Volume Descriptor
-///
-typedef union {
+///
+typedef union {
struct {
- UINT8 Type;
- CHAR8 Id[5]; ///< "CD001"
+ UINT8 Type;
+ CHAR8 Id[5]; ///< "CD001"
CHAR8 Reserved[82];
} Unknown;
@@ -72,29 +66,29 @@ typedef union {
///
struct {
UINT8 Type; ///< Must be 0
- CHAR8 Id[5]; ///< "CD001"
- UINT8 Version; ///< Must be 1
- CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"
- CHAR8 Unused[32]; ///< Must be 0
+ CHAR8 Id[5]; ///< "CD001"
+ UINT8 Version; ///< Must be 1
+ CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"
+ CHAR8 Unused[32]; ///< Must be 0
UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog
CHAR8 Unused2[13]; ///< Must be 0
} BootRecordVolume;
-
+
///
- /// Primary Volumn Descriptor, defined in ISO 9660.
+ /// Primary Volume Descriptor, defined in ISO 9660.
///
struct {
- UINT8 Type;
+ UINT8 Type;
CHAR8 Id[5]; ///< "CD001"
- UINT8 Version;
+ UINT8 Version;
UINT8 Unused; ///< Must be 0
- CHAR8 SystemId[32];
- CHAR8 VolumeId[32];
- UINT8 Unused2[8]; ///< Must be 0
+ CHAR8 SystemId[32];
+ CHAR8 VolumeId[32];
+ UINT8 Unused2[8]; ///< Must be 0
UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks
} PrimaryVolume;
-} CDROM_VOLUME_DESCRIPTOR;
+} CDROM_VOLUME_DESCRIPTOR;
///
/// Catalog Entry
diff --git a/MdePkg/Include/IndustryStandard/Emmc.h b/MdePkg/Include/IndustryStandard/Emmc.h
index ad0ca55d7783..0987f6c4985c 100644
--- a/MdePkg/Include/IndustryStandard/Emmc.h
+++ b/MdePkg/Include/IndustryStandard/Emmc.h
@@ -4,13 +4,7 @@
This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -230,7 +224,7 @@ typedef struct {
UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]
UINT8 Reserved17; // Reserved [211]
UINT8 SecCount[4]; // Sector Count [215:212]
- UINT8 SleepNotificationTime; // Sleep Notification Timout [216]
+ UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]
UINT8 SATimeout; // Sleep/awake timeout [217]
UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]
UINT8 SCVccq; // Sleep current (VCCQ) [219]
diff --git a/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h b/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
index 97b1c45edfc9..d2bc6d57c401 100644
--- a/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
+++ b/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
@@ -1,15 +1,9 @@
/** @file
ACPI high precision event timer table definition, at www.intel.com
Specification name is IA-PC HPET (High Precision Event Timers) Specification.
-
- Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
@@ -23,6 +17,22 @@
#pragma pack(1)
///
+/// HPET Event Timer Block ID described in IA-PC HPET Specification, 3.2.4.
+///
+typedef union {
+ struct {
+ UINT32 Revision : 8;
+ UINT32 NumberOfTimers : 5;
+ UINT32 CounterSize : 1;
+ UINT32 Reserved : 1;
+ UINT32 LegacyRoute : 1;
+ UINT32 VendorId : 16;
+ } Bits;
+ UINT32 Uint32;
+} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID;
+
+
+///
/// High Precision Event Timer Table header definition.
///
typedef struct {
diff --git a/MdePkg/Include/IndustryStandard/Hsti.h b/MdePkg/Include/IndustryStandard/Hsti.h
index 2d9994ecb7fa..6b403ccbe8af 100644
--- a/MdePkg/Include/IndustryStandard/Hsti.h
+++ b/MdePkg/Include/IndustryStandard/Hsti.h
@@ -1,15 +1,9 @@
/** @file
- Support for HSTI 1.0 specification, defined at
+ Support for HSTI 1.1a specification, defined at
Microsoft Hardware Security Testability Specification.
- Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -25,8 +19,8 @@
#define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001 // IHV
#define PLATFORM_SECURITY_ROLE_PLATFORM_IBV 0x00000002
-#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM 0x00000003
-#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM 0x00000004
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM 0x00000003
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM 0x00000004
typedef struct {
//
@@ -72,7 +66,7 @@ typedef struct {
// which will describe the steps to remediate the failure - a URL to the
// documentation is recommended.
//
-//CHAR16 ErrorString[];
+//CHAR16 ErrorString[];
} ADAPTER_INFO_PLATFORM_SECURITY;
#pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/Http11.h b/MdePkg/Include/IndustryStandard/Http11.h
index 797e74e4d4b9..50a182634d04 100644
--- a/MdePkg/Include/IndustryStandard/Http11.h
+++ b/MdePkg/Include/IndustryStandard/Http11.h
@@ -1,16 +1,10 @@
/** @file
- Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616
+ Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616
- This file contains common HTTP 1.1 definitions from RFC 2616
-
- (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
+ This file contains common HTTP 1.1 definitions from RFC 2616
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __HTTP_11_H__
@@ -20,7 +14,7 @@
///
/// HTTP Version (currently HTTP 1.1)
-///
+///
/// The version of an HTTP message is indicated by an HTTP-Version field
/// in the first line of the message.
///
@@ -28,7 +22,7 @@
///
/// HTTP Request Method definitions
-///
+///
/// The Method token indicates the method to be performed on the
/// resource identified by the Request-URI. The method is case-sensitive.
///
@@ -50,27 +44,27 @@
///
/// Accept Request Header
-/// The Accept request-header field can be used to specify certain media types which are
-/// acceptable for the response. Accept headers can be used to indicate that the request
-/// is specifically limited to a small set of desired types, as in the case of a request
+/// The Accept request-header field can be used to specify certain media types which are
+/// acceptable for the response. Accept headers can be used to indicate that the request
+/// is specifically limited to a small set of desired types, as in the case of a request
/// for an in-line image.
///
#define HTTP_HEADER_ACCEPT "Accept"
-///
+///
/// Accept-Charset Request Header
-/// The Accept-Charset request-header field can be used to indicate what character sets
-/// are acceptable for the response. This field allows clients capable of understanding
-/// more comprehensive or special-purpose character sets to signal that capability to a
+/// The Accept-Charset request-header field can be used to indicate what character sets
+/// are acceptable for the response. This field allows clients capable of understanding
+/// more comprehensive or special-purpose character sets to signal that capability to a
/// server which is capable of representing documents in those character sets.
///
#define HTTP_HEADER_ACCEPT_CHARSET "Accept-Charset"
-///
+///
/// Accept-Language Request Header
-/// The Accept-Language request-header field is similar to Accept,
-/// but restricts the set of natural languages that are preferred
+/// The Accept-Language request-header field is similar to Accept,
+/// but restricts the set of natural languages that are preferred
/// as a response to the request.
///
#define HTTP_HEADER_ACCEPT_LANGUAGE "Accept-Language"
@@ -83,39 +77,39 @@
#define HTTP_HEADER_ACCEPT_RANGES "Accept-Ranges"
-///
+///
/// Accept-Encoding Request Header
-/// The Accept-Encoding request-header field is similar to Accept,
+/// The Accept-Encoding request-header field is similar to Accept,
/// but restricts the content-codings that are acceptable in the response.
///
#define HTTP_HEADER_ACCEPT_ENCODING "Accept-Encoding"
///
/// Content-Encoding Header
-/// The Content-Encoding entity-header field is used as a modifier to the media-type.
-/// When present, its value indicates what additional content codings have been applied
-/// to the entity-body, and thus what decoding mechanisms must be applied in order to
-/// obtain the media-type referenced by the Content-Type header field. Content-Encoding
-/// is primarily used to allow a document to be compressed without losing the identity
+/// The Content-Encoding entity-header field is used as a modifier to the media-type.
+/// When present, its value indicates what additional content codings have been applied
+/// to the entity-body, and thus what decoding mechanisms must be applied in order to
+/// obtain the media-type referenced by the Content-Type header field. Content-Encoding
+/// is primarily used to allow a document to be compressed without losing the identity
/// of its underlying media type.
///
#define HTTP_HEADER_CONTENT_ENCODING "Content-Encoding"
-///
+///
/// HTTP Content-Encoding Compression types
///
#define HTTP_CONTENT_ENCODING_IDENTITY "identity" /// No transformation is used. This is the default value for content coding.
#define HTTP_CONTENT_ENCODING_GZIP "gzip" /// Content-Encoding: GNU zip format (described in RFC 1952).
-#define HTTP_CONTENT_ENCODING_COMPRESS "compress" /// encoding format produced by the common UNIX file compression program "compress".
-#define HTTP_CONTENT_ENCODING_DEFLATE "deflate" /// The "zlib" format defined in RFC 1950 in combination with the "deflate"
+#define HTTP_CONTENT_ENCODING_COMPRESS "compress" /// encoding format produced by the common UNIX file compression program "compress".
+#define HTTP_CONTENT_ENCODING_DEFLATE "deflate" /// The "zlib" format defined in RFC 1950 in combination with the "deflate"
/// compression mechanism described in RFC 1951.
///
/// Content-Type Header
-/// The Content-Type entity-header field indicates the media type of the entity-body sent to
-/// the recipient or, in the case of the HEAD method, the media type that would have been sent
+/// The Content-Type entity-header field indicates the media type of the entity-body sent to
+/// the recipient or, in the case of the HEAD method, the media type that would have been sent
/// had the request been a GET.
///
#define HTTP_HEADER_CONTENT_TYPE "Content-Type"
@@ -124,12 +118,12 @@
//
#define HTTP_CONTENT_TYPE_APP_JSON "application/json"
#define HTTP_CONTENT_TYPE_APP_OCTET_STREAM "application/octet-stream"
-
+
#define HTTP_CONTENT_TYPE_TEXT_HTML "text/html"
#define HTTP_CONTENT_TYPE_TEXT_PLAIN "text/plain"
#define HTTP_CONTENT_TYPE_TEXT_CSS "text/css"
#define HTTP_CONTENT_TYPE_TEXT_XML "text/xml"
-
+
#define HTTP_CONTENT_TYPE_IMAGE_GIF "image/gif"
#define HTTP_CONTENT_TYPE_IMAGE_JPEG "image/jpeg"
#define HTTP_CONTENT_TYPE_IMAGE_PNG "image/png"
@@ -138,17 +132,17 @@
///
/// Content-Length Header
-/// The Content-Length entity-header field indicates the size of the entity-body,
-/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD
+/// The Content-Length entity-header field indicates the size of the entity-body,
+/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD
/// method, the size of the entity-body that would have been sent had the request been a GET.
///
#define HTTP_HEADER_CONTENT_LENGTH "Content-Length"
-
+
///
/// Transfer-Encoding Header
-/// The Transfer-Encoding general-header field indicates what (if any) type of transformation
-/// has been applied to the message body in order to safely transfer it between the sender
-/// and the recipient. This differs from the content-coding in that the transfer-coding
+/// The Transfer-Encoding general-header field indicates what (if any) type of transformation
+/// has been applied to the message body in order to safely transfer it between the sender
+/// and the recipient. This differs from the content-coding in that the transfer-coding
/// is a property of the message, not of the entity.
///
#define HTTP_HEADER_TRANSFER_ENCODING "Transfer-Encoding"
@@ -156,14 +150,14 @@
///
/// User Agent Request Header
-///
-/// The User-Agent request-header field contains information about the user agent originating
-/// the request. This is for statistical purposes, the tracing of protocol violations, and
-/// automated recognition of user agents for the sake of tailoring responses to avoid
-/// particular user agent limitations. User agents SHOULD include this field with requests.
-/// The field can contain multiple product tokens and comments identifying the agent and any
-/// subproducts which form a significant part of the user agent.
-/// By convention, the product tokens are listed in order of their significance for
+///
+/// The User-Agent request-header field contains information about the user agent originating
+/// the request. This is for statistical purposes, the tracing of protocol violations, and
+/// automated recognition of user agents for the sake of tailoring responses to avoid
+/// particular user agent limitations. User agents SHOULD include this field with requests.
+/// The field can contain multiple product tokens and comments identifying the agent and any
+/// subproducts which form a significant part of the user agent.
+/// By convention, the product tokens are listed in order of their significance for
/// identifying the application.
///
#define HTTP_HEADER_USER_AGENT "User-Agent"
@@ -171,49 +165,49 @@
///
/// Host Request Header
///
-/// The Host request-header field specifies the Internet host and port number of the resource
-/// being requested, as obtained from the original URI given by the user or referring resource
+/// The Host request-header field specifies the Internet host and port number of the resource
+/// being requested, as obtained from the original URI given by the user or referring resource
///
#define HTTP_HEADER_HOST "Host"
///
/// Location Response Header
-///
-/// The Location response-header field is used to redirect the recipient to a location other than
-/// the Request-URI for completion of the request or identification of a new resource.
-/// For 201 (Created) responses, the Location is that of the new resource which was created by
-/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for
+///
+/// The Location response-header field is used to redirect the recipient to a location other than
+/// the Request-URI for completion of the request or identification of a new resource.
+/// For 201 (Created) responses, the Location is that of the new resource which was created by
+/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for
/// automatic redirection to the resource. The field value consists of a single absolute URI.
///
#define HTTP_HEADER_LOCATION "Location"
///
/// The If-Match request-header field is used with a method to make it conditional.
-/// A client that has one or more entities previously obtained from the resource
-/// can verify that one of those entities is current by including a list of their
-/// associated entity tags in the If-Match header field.
-/// The purpose of this feature is to allow efficient updates of cached information
-/// with a minimum amount of transaction overhead. It is also used, on updating requests,
-/// to prevent inadvertent modification of the wrong version of a resource.
+/// A client that has one or more entities previously obtained from the resource
+/// can verify that one of those entities is current by including a list of their
+/// associated entity tags in the If-Match header field.
+/// The purpose of this feature is to allow efficient updates of cached information
+/// with a minimum amount of transaction overhead. It is also used, on updating requests,
+/// to prevent inadvertent modification of the wrong version of a resource.
/// As a special case, the value "*" matches any current entity of the resource.
///
#define HTTP_HEADER_IF_MATCH "If-Match"
///
-/// The If-None-Match request-header field is used with a method to make it conditional.
-/// A client that has one or more entities previously obtained from the resource can verify
-/// that none of those entities is current by including a list of their associated entity
-/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient
-/// updates of cached information with a minimum amount of transaction overhead. It is also used
-/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the
+/// The If-None-Match request-header field is used with a method to make it conditional.
+/// A client that has one or more entities previously obtained from the resource can verify
+/// that none of those entities is current by including a list of their associated entity
+/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient
+/// updates of cached information with a minimum amount of transaction overhead. It is also used
+/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the
/// client believes that the resource does not exist.
///
#define HTTP_HEADER_IF_NONE_MATCH "If-None-Match"
-///
+///
/// Authorization Request Header
/// The Authorization field value consists of credentials
/// containing the authentication information of the user agent for
@@ -223,8 +217,8 @@
///
/// ETAG Response Header
-/// The ETag response-header field provides the current value of the entity tag
-/// for the requested variant.
+/// The ETag response-header field provides the current value of the entity tag
+/// for the requested variant.
///
#define HTTP_HEADER_ETAG "ETag"
diff --git a/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h b/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
index d542b2c41291..547f2cc02f42 100644
--- a/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
+++ b/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
@@ -1,15 +1,9 @@
/** @file
The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's
- iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification.
-
- Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
+ iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification.
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -58,7 +52,7 @@ typedef struct {
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER;
///
-/// Common Header of Boot Firmware Table Structure
+/// Common Header of Boot Firmware Table Structure
///
typedef struct {
UINT8 StructureId;
@@ -78,7 +72,7 @@ typedef struct {
UINT16 NIC0Offset;
UINT16 Target0Offset;
UINT16 NIC1Offset;
- UINT16 Target1Offset;
+ UINT16 Target1Offset;
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1
@@ -100,8 +94,8 @@ typedef struct {
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID BIT0
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID BIT0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1
///
/// NIC Structure
diff --git a/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/MdePkg/Include/IndustryStandard/IoRemappingTable.h
new file mode 100644
index 000000000000..5ecf46097def
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IoRemappingTable.h
@@ -0,0 +1,203 @@
+/** @file
+ ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049D
+
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0049d/DEN0049D_IO_Remapping_Table.pdf
+
+ Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
+ Copyright (c) 2018, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __IO_REMAPPING_TABLE_H__
+#define __IO_REMAPPING_TABLE_H__
+
+#include <IndustryStandard/Acpi.h>
+
+#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION 0x0
+
+#define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0
+#define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1
+#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2
+#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3
+#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4
+#define EFI_ACPI_IORT_TYPE_PMCG 0x5
+
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0
+
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3
+
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
+
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5
+
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1
+
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1
+
+#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1
+#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3
+
+#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0
+#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1
+#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2
+
+#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0
+#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED 0x1
+
+#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0
+
+#pragma pack(1)
+
+///
+/// Table header
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 NumNodes;
+ UINT32 NodeOffset;
+ UINT32 Reserved;
+} EFI_ACPI_6_0_IO_REMAPPING_TABLE;
+
+///
+/// Definition for ID mapping table shared by all node types
+///
+typedef struct {
+ UINT32 InputBase;
+ UINT32 NumIds;
+ UINT32 OutputBase;
+ UINT32 OutputReference;
+ UINT32 Flags;
+} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;
+
+///
+/// Node header definition shared by all node types
+///
+typedef struct {
+ UINT8 Type;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT32 Reserved;
+ UINT32 NumIdMappings;
+ UINT32 IdReference;
+} EFI_ACPI_6_0_IO_REMAPPING_NODE;
+
+///
+/// Node type 0: ITS node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT32 NumItsIdentifiers;
+//UINT32 ItsIdentifiers[NumItsIdentifiers];
+} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
+
+///
+/// Node type 1: root complex node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT32 CacheCoherent;
+ UINT8 AllocationHints;
+ UINT16 Reserved;
+ UINT8 MemoryAccessFlags;
+
+ UINT32 AtsAttribute;
+ UINT32 PciSegmentNumber;
+ UINT8 MemoryAddressSize;
+ UINT8 Reserved1[3];
+} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
+
+///
+/// Node type 2: named component node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT32 Flags;
+ UINT32 CacheCoherent;
+ UINT8 AllocationHints;
+ UINT16 Reserved;
+ UINT8 MemoryAccessFlags;
+ UINT8 AddressSizeLimit;
+//UINT8 ObjectName[];
+} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;
+
+///
+/// Node type 3: SMMUv1 or SMMUv2 node
+///
+typedef struct {
+ UINT32 Interrupt;
+ UINT32 InterruptFlags;
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT64 Base;
+ UINT64 Span;
+ UINT32 Model;
+ UINT32 Flags;
+ UINT32 GlobalInterruptArrayRef;
+ UINT32 NumContextInterrupts;
+ UINT32 ContextInterruptArrayRef;
+ UINT32 NumPmuInterrupts;
+ UINT32 PmuInterruptArrayRef;
+
+ UINT32 SMMU_NSgIrpt;
+ UINT32 SMMU_NSgIrptFlags;
+ UINT32 SMMU_NSgCfgIrpt;
+ UINT32 SMMU_NSgCfgIrptFlags;
+
+//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];
+//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;
+
+///
+/// Node type 4: SMMUv3 node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT64 Base;
+ UINT32 Flags;
+ UINT32 Reserved;
+ UINT64 VatosAddress;
+ UINT32 Model;
+ UINT32 Event;
+ UINT32 Pri;
+ UINT32 Gerr;
+ UINT32 Sync;
+ UINT32 ProximityDomain;
+ UINT32 DeviceIdMappingIndex;
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
+
+///
+/// Node type 5: PMCG node
+///
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;
+
+ UINT64 Base;
+ UINT32 OverflowInterruptGsiv;
+ UINT32 NodeReference;
+ UINT64 Page1Base;
+//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];
+} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Ipmi.h b/MdePkg/Include/IndustryStandard/Ipmi.h
index 4cb7494d7bca..0be12b659020 100644
--- a/MdePkg/Include/IndustryStandard/Ipmi.h
+++ b/MdePkg/Include/IndustryStandard/Ipmi.h
@@ -1,17 +1,12 @@
/** @file
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+ IPMI Platform Management FRU Information Storage Definition v1.0 Revision 1.3.
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
- Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_H_
@@ -26,4 +21,35 @@
#include <IndustryStandard/IpmiNetFnTransport.h>
#include <IndustryStandard/IpmiNetFnGroupExtension.h>
+#include <IndustryStandard/IpmiFruInformationStorage.h>
+
+//
+// Generic Completion Codes definitions
+//
+#define IPMI_COMP_CODE_NORMAL 0x00
+#define IPMI_COMP_CODE_NODE_BUSY 0xC0
+#define IPMI_COMP_CODE_INVALID_COMMAND 0xC1
+#define IPMI_COMP_CODE_INVALID_FOR_GIVEN_LUN 0xC2
+#define IPMI_COMP_CODE_TIMEOUT 0xC3
+#define IPMI_COMP_CODE_OUT_OF_SPACE 0xC4
+#define IPMI_COMP_CODE_RESERVATION_CANCELED_OR_INVALID 0xC5
+#define IPMI_COMP_CODE_REQUEST_DATA_TRUNCATED 0xC6
+#define IPMI_COMP_CODE_INVALID_REQUEST_DATA_LENGTH 0xC7
+#define IPMI_COMP_CODE_REQUEST_EXCEED_LIMIT 0xC8
+#define IPMI_COMP_CODE_OUT_OF_RANGE 0xC9
+#define IPMI_COMP_CODE_CANNOT_RETURN 0xCA
+#define IPMI_COMP_CODE_NOT_PRESENT 0xCB
+#define IPMI_COMP_CODE_INVALID_DATA_FIELD 0xCC
+#define IPMI_COMP_CODE_COMMAND_ILLEGAL 0xCD
+#define IPMI_COMP_CODE_CMD_RESP_NOT_PROVIDED 0xCE
+#define IPMI_COMP_CODE_FAIL_DUP_REQUEST 0xCF
+#define IPMI_COMP_CODE_SDR_REP_IN_UPDATE_MODE 0xD0
+#define IPMI_COMP_CODE_DEV_IN_FW_UPDATE_MODE 0xD1
+#define IPMI_COMP_CODE_BMC_INIT_IN_PROGRESS 0xD2
+#define IPMI_COMP_CODE_DEST_UNAVAILABLE 0xD3
+#define IPMI_COMP_CODE_INSUFFICIENT_PRIVILEGE 0xD4
+#define IPMI_COMP_CODE_UNSUPPORTED_IN_PRESENT_STATE 0xD5
+#define IPMI_COMP_CODE_SUBFUNCTION_DISABLED 0xD6
+#define IPMI_COMP_CODE_UNSPECIFIED 0xFF
+
#endif
diff --git a/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h b/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h
new file mode 100644
index 000000000000..402b586ef109
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h
@@ -0,0 +1,86 @@
+/** @file
+ IPMI Platform Management FRU Information Storage Definitions
+
+ This file contains the definitions for:
+ Common Header Format (Chapter 8)
+ MultiRecord Header (Section 16.1)
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Revision Reference:
+ - IPMI Platform Management FRU Information Storage Definition v1.0 Revision
+ 1.3, Dated March 24, 2015.
+ https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-platform-mgt-fru-info-storage-def-v1-0-rev-1-3-spec-update.pdf
+**/
+
+#ifndef _IPMI_FRU_INFORMATION_STORAGE_H_
+#define _IPMI_FRU_INFORMATION_STORAGE_H_
+
+#pragma pack(1)
+
+//
+// Structure definitions for FRU Common Header
+//
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT8 FormatVersionNumber:4;
+ UINT8 Reserved:4;
+ } Bits;
+ ///
+ /// All bit fields as a 8-bit value
+ ///
+ UINT8 Uint8;
+} IPMI_FRU_COMMON_HEADER_FORMAT_VERSION;
+
+typedef struct {
+ IPMI_FRU_COMMON_HEADER_FORMAT_VERSION FormatVersion;
+ UINT8 InternalUseStartingOffset;
+ UINT8 ChassisInfoStartingOffset;
+ UINT8 BoardAreaStartingOffset;
+ UINT8 ProductInfoStartingOffset;
+ UINT8 MultiRecInfoStartingOffset;
+ UINT8 Pad;
+ UINT8 Checksum;
+} IPMI_FRU_COMMON_HEADER;
+
+//
+// Structure definition for FRU MultiRecord Header
+//
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT8 RecordFormatVersion:4;
+ UINT8 Reserved:3;
+ UINT8 EndofList:1;
+ } Bits;
+ ///
+ /// All bit fields as a 8-bit value
+ ///
+ UINT8 Uint8;
+} IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION;
+
+typedef struct {
+ UINT8 RecordTypeId;
+ IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION FormatVersion;
+ UINT8 RecordLength;
+ UINT8 RecordChecksum;
+ UINT8 HeaderChecksum;
+} IPMI_FRU_MULTI_RECORD_HEADER;
+
+//
+// Structure definition for System UUID Subrecord with checksum.
+//
+typedef struct {
+ UINT8 RecordCheckSum;
+ UINT8 SubRecordId;
+ EFI_GUID Uuid;
+} IPMI_SYSTEM_UUID_SUB_RECORD_WITH_CHECKSUM;
+
+#pragma pack()
+#endif
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h b/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
index 2d2d8e7c3681..499175f1c430 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
@@ -11,14 +11,8 @@
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
- Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_APP_H_
@@ -42,27 +36,48 @@
//
// Constants and Structure definitions for "Get Device ID" command to follow here
//
+typedef union {
+ struct {
+ UINT8 DeviceRevision : 4;
+ UINT8 Reserved : 3;
+ UINT8 DeviceSdr : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_DEVICE_ID_DEVICE_REV;
+
+typedef union {
+ struct {
+ UINT8 MajorFirmwareRev : 7;
+ UINT8 UpdateMode : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_DEVICE_ID_FIRMWARE_REV_1;
+
+typedef union {
+ struct {
+ UINT8 SensorDeviceSupport : 1;
+ UINT8 SdrRepositorySupport : 1;
+ UINT8 SelDeviceSupport : 1;
+ UINT8 FruInventorySupport : 1;
+ UINT8 IpmbMessageReceiver : 1;
+ UINT8 IpmbMessageGenerator : 1;
+ UINT8 BridgeSupport : 1;
+ UINT8 ChassisSupport : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_DEVICE_ID_DEVICE_SUPPORT;
+
typedef struct {
- UINT8 CompletionCode;
- UINT8 DeviceId;
- UINT8 DeviceRevision : 4;
- UINT8 Reserved : 3;
- UINT8 DeviceSdr : 1;
- UINT8 MajorFirmwareRev : 7;
- UINT8 UpdateMode : 1;
- UINT8 MinorFirmwareRev;
- UINT8 SpecificationVersion;
- UINT8 SensorDeviceSupport : 1;
- UINT8 SdrRepositorySupport : 1;
- UINT8 SelDeviceSupport : 1;
- UINT8 FruInventorySupport : 1;
- UINT8 IpmbMessageReceiver : 1;
- UINT8 IpmbMessageGenerator : 1;
- UINT8 BridgeSupport : 1;
- UINT8 ChassisSupport : 1;
- UINT8 ManufacturerId[3];
- UINT16 ProductId;
- UINT32 AuxFirmwareRevInfo;
+ UINT8 CompletionCode;
+ UINT8 DeviceId;
+ IPMI_GET_DEVICE_ID_DEVICE_REV DeviceRevision;
+ IPMI_GET_DEVICE_ID_FIRMWARE_REV_1 FirmwareRev1;
+ UINT8 MinorFirmwareRev;
+ UINT8 SpecificationVersion;
+ IPMI_GET_DEVICE_ID_DEVICE_SUPPORT DeviceSupport;
+ UINT8 ManufacturerId[3];
+ UINT16 ProductId;
+ UINT32 AuxFirmwareRevInfo;
} IPMI_GET_DEVICE_ID_RESPONSE;
@@ -128,11 +143,54 @@ typedef struct {
//
// Constants and Structure definitions for "Set ACPI Power State" command to follow here
//
+
+//
+// Definitions for System Power State
+//
+// Working
+#define IPMI_SYSTEM_POWER_STATE_S0_G0 0x0
+#define IPMI_SYSTEM_POWER_STATE_S1 0x1
+#define IPMI_SYSTEM_POWER_STATE_S2 0x2
+#define IPMI_SYSTEM_POWER_STATE_S3 0x3
+#define IPMI_SYSTEM_POWER_STATE_S4 0x4
+// Soft off
+#define IPMI_SYSTEM_POWER_STATE_S5_G2 0x5
+// Sent when message source cannot differentiate between S4 and S5
+#define IPMI_SYSTEM_POWER_STATE_S4_S5 0x6
+// Mechanical off
+#define IPMI_SYSTEM_POWER_STATE_G3 0x7
+// Sleeping - cannot differentiate between S1-S3
+#define IPMI_SYSTEM_POWER_STATE_SLEEPING 0x8
+// Sleeping - cannot differentiate between S1-S4
+#define IPMI_SYSTEM_POWER_STATE_G1_SLEEPING 0x9
+// S5 entered by override
+#define IPMI_SYSTEM_POWER_STATE_OVERRIDE 0xA
+#define IPMI_SYSTEM_POWER_STATE_LEGACY_ON 0x20
+#define IPMI_SYSTEM_POWER_STATE_LEGACY_OFF 0x21
+#define IPMI_SYSTEM_POWER_STATE_UNKNOWN 0x2A
+#define IPMI_SYSTEM_POWER_STATE_NO_CHANGE 0x7F
+
+//
+// Definitions for Device Power State
+//
+#define IPMI_DEVICE_POWER_STATE_D0 0x0
+#define IPMI_DEVICE_POWER_STATE_D1 0x1
+#define IPMI_DEVICE_POWER_STATE_D2 0x2
+#define IPMI_DEVICE_POWER_STATE_D3 0x3
+#define IPMI_DEVICE_POWER_STATE_UNKNOWN 0x2A
+#define IPMI_DEVICE_POWER_STATE_NO_CHANGE 0x7F
+
+typedef union {
+ struct {
+ UINT8 PowerState : 7;
+ UINT8 StateChange : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_ACPI_POWER_STATE;
+
typedef struct {
- UINT8 AcpiSystemPowerState : 7;
- UINT8 AcpiSystemStateChange : 1;
- UINT8 AcpiDevicePowerState : 7;
- UINT8 AcpiDeviceStateChange : 1;
+ IPMI_ACPI_POWER_STATE SystemPowerState;
+ IPMI_ACPI_POWER_STATE DevicePowerState;
} IPMI_SET_ACPI_POWER_STATE_REQUEST;
//
@@ -170,26 +228,77 @@ typedef struct {
#define IPMI_APP_RESET_WATCHDOG_TIMER 0x22
//
-// Constants and Structure definitions for "Reset WatchDog Timer" command to follow here
+// Definitions for Set WatchDog Timer command
//
-typedef struct {
- UINT8 TimerUse : 3;
- UINT8 Reserved : 3;
- UINT8 TimerRunning : 1;
- UINT8 TimerUseExpirationFlagLog : 1;
+#define IPMI_APP_SET_WATCHDOG_TIMER 0x24
+
+//
+// Constants and Structure definitions for "Set WatchDog Timer" command to follow here
+//
+
+//
+// Definitions for watchdog timer use
+//
+#define IPMI_WATCHDOG_TIMER_BIOS_FRB2 0x1
+#define IPMI_WATCHDOG_TIMER_BIOS_POST 0x2
+#define IPMI_WATCHDOG_TIMER_OS_LOADER 0x3
+#define IPMI_WATCHDOG_TIMER_SMS 0x4
+#define IPMI_WATCHDOG_TIMER_OEM 0x5
+
+//
+// Structure definition for timer Use
+//
+typedef union {
+ struct {
+ UINT8 TimerUse : 3;
+ UINT8 Reserved : 3;
+ UINT8 TimerRunning : 1;
+ UINT8 TimerUseExpirationFlagLog : 1;
+ } Bits;
+ UINT8 Uint8;
} IPMI_WATCHDOG_TIMER_USE;
//
-// Definitions for Set WatchDog Timer command
+// Definitions for watchdog timeout action
//
-#define IPMI_APP_SET_WATCHDOG_TIMER 0x24
+#define IPMI_WATCHDOG_TIMER_ACTION_NO_ACTION 0x0
+#define IPMI_WATCHDOG_TIMER_ACTION_HARD_RESET 0x1
+#define IPMI_WATCHDOG_TIMER_ACTION_POWER_DONW 0x2
+#define IPMI_WATCHDOG_TIMER_ACTION_POWER_CYCLE 0x3
//
-// Constants and Structure definitions for "Set WatchDog Timer" command to follow here
+// Definitions for watchdog pre-timeout interrupt
+//
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_NONE 0x0
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_SMI 0x1
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_NMI 0x2
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_MESSAGING 0x3
+
+//
+// Structure definitions for Timer Actions
+//
+typedef union {
+ struct {
+ UINT8 TimeoutAction : 3;
+ UINT8 Reserved1 : 1;
+ UINT8 PreTimeoutInterrupt : 3;
+ UINT8 Reserved2 : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_WATCHDOG_TIMER_ACTIONS;
+
+//
+// Bit definitions for Timer use expiration flags
//
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_BIOS_FRB2 BIT1
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_BIOS_POST BIT2
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OS_LOAD BIT3
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_SMS_OS BIT4
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OEM BIT5
+
typedef struct {
IPMI_WATCHDOG_TIMER_USE TimerUse;
- UINT8 TimerActions;
+ IPMI_WATCHDOG_TIMER_ACTIONS TimerActions;
UINT8 PretimeoutInterval;
UINT8 TimerUseExpirationFlagsClear;
UINT16 InitialCountdownValue;
@@ -206,7 +315,7 @@ typedef struct {
typedef struct {
UINT8 CompletionCode;
IPMI_WATCHDOG_TIMER_USE TimerUse;
- UINT8 TimerActions;
+ IPMI_WATCHDOG_TIMER_ACTIONS TimerActions;
UINT8 PretimeoutInterval;
UINT8 TimerUseExpirationFlagsClear;
UINT16 InitialCountdownValue;
@@ -225,6 +334,23 @@ typedef struct {
//
// Constants and Structure definitions for "Set BMC Global Enables " command to follow here
//
+typedef union {
+ struct {
+ UINT8 ReceiveMessageQueueInterrupt : 1;
+ UINT8 EventMessageBufferFullInterrupt : 1;
+ UINT8 EventMessageBuffer : 1;
+ UINT8 SystemEventLogging : 1;
+ UINT8 Reserved : 1;
+ UINT8 Oem0Enable : 1;
+ UINT8 Oem1Enable : 1;
+ UINT8 Oem2Enable : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BMC_GLOBAL_ENABLES;
+
+typedef struct {
+ IPMI_BMC_GLOBAL_ENABLES SetEnables;
+} IPMI_SET_BMC_GLOBAL_ENABLES_REQUEST;
//
// Definitions for Get BMC Global Enables command
@@ -234,6 +360,10 @@ typedef struct {
//
// Constants and Structure definitions for "Get BMC Global Enables " command to follow here
//
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_BMC_GLOBAL_ENABLES GetEnables;
+} IPMI_GET_BMC_GLOBAL_ENABLES_RESPONSE;
//
// Definitions for Clear Message Flags command
@@ -243,6 +373,23 @@ typedef struct {
//
// Constants and Structure definitions for "Clear Message Flags" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ReceiveMessageQueue : 1;
+ UINT8 EventMessageBuffer : 1;
+ UINT8 Reserved1 : 1;
+ UINT8 WatchdogPerTimeoutInterrupt : 1;
+ UINT8 Reserved2 : 1;
+ UINT8 Oem0 : 1;
+ UINT8 Oem1 : 1;
+ UINT8 Oem2 : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_MESSAGE_FLAGS;
+
+typedef struct {
+ IPMI_MESSAGE_FLAGS ClearFlags;
+} IPMI_CLEAR_MESSAGE_FLAGS_REQUEST;
//
// Definitions for Get Message Flags command
@@ -252,6 +399,10 @@ typedef struct {
//
// Constants and Structure definitions for "Get Message Flags" command to follow here
//
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_MESSAGE_FLAGS GetFlags;
+} IPMI_GET_MESSAGE_FLAGS_RESPONSE;
//
// Definitions for Enable Message Channel Receive command
@@ -270,6 +421,19 @@ typedef struct {
//
// Constants and Structure definitions for "Get Message" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 InferredPrivilegeLevel : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_MESSAGE_CHANNEL_NUMBER;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_GET_MESSAGE_CHANNEL_NUMBER ChannelNumber;
+ UINT8 MessageData[0];
+} IPMI_GET_MESSAGE_RESPONSE;
//
// Definitions for Send Message command
@@ -279,6 +443,26 @@ typedef struct {
//
// Constants and Structure definitions for "Send Message" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 Authentication : 1;
+ UINT8 Encryption : 1;
+ UINT8 Tracking : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SEND_MESSAGE_CHANNEL_NUMBER;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_SEND_MESSAGE_CHANNEL_NUMBER ChannelNumber;
+ UINT8 MessageData[0];
+} IPMI_SEND_MESSAGE_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ResponseData[0];
+} IPMI_SEND_MESSAGE_RESPONSE;
//
// Definitions for Read Event Message Buffer command
@@ -387,22 +571,65 @@ typedef struct {
//
// Constants and Structure definitions for "Get Channel Access" command to follow here
//
+
+//
+// Definitions for channel access memory type in Get Channel Access command request
+//
+#define IPMI_CHANNEL_ACCESS_MEMORY_TYPE_NON_VOLATILE 0x1
+#define IPMI_CHANNEL_ACCESS_MEMORY_TYPE_PRESENT_VOLATILE_SETTING 0x2
+
+//
+// Definitions for channel access modes in Get Channel Access command response
+//
+#define IPMI_CHANNEL_ACCESS_MODES_DISABLED 0x0
+#define IPMI_CHANNEL_ACCESS_MODES_PRE_BOOT_ONLY 0x1
+#define IPMI_CHANNEL_ACCESS_MODES_ALWAYS_AVAILABLE 0x2
+#define IPMI_CHANNEL_ACCESS_MODES_SHARED 0x3
+
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 6;
+ UINT8 MemoryType : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_CHANNEL_ACCESS_TYPE;
+
typedef struct {
- UINT8 ChannelNo : 4;
- UINT8 Reserve1 : 4;
- UINT8 Reserve2 : 6;
- UINT8 MemoryType : 2;
+ IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER ChannelNumber;
+ IPMI_GET_CHANNEL_ACCESS_TYPE AccessType;
} IPMI_GET_CHANNEL_ACCESS_REQUEST;
+typedef union {
+ struct {
+ UINT8 AccessMode : 3;
+ UINT8 UserLevelAuthEnabled : 1;
+ UINT8 MessageAuthEnable : 1;
+ UINT8 Alert : 1;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS;
+
+typedef union {
+ struct {
+ UINT8 ChannelPriviledgeLimit : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT;
+
typedef struct {
- UINT8 CompletionCode;
- UINT8 AccessMode : 3;
- UINT8 UserLevelAuthEnabled : 1;
- UINT8 MessageAuthEnable : 1;
- UINT8 Alert : 1;
- UINT8 Reserve1 : 2;
- UINT8 ChannelPriviledgeLimit : 4;
- UINT8 Reserve2 : 4;
+ UINT8 CompletionCode;
+ IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS ChannelAccess;
+ IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT PrivilegeLimit;
} IPMI_GET_CHANNEL_ACCESS_RESPONSE;
//
@@ -413,18 +640,78 @@ typedef struct {
//
// Constants and Structure definitions for "Get Channel Info" command to follow here
//
+
+//
+// Definitions for channel media type
+//
+// IPMB (I2C)
+#define IPMI_CHANNEL_MEDIA_TYPE_IPMB 0x1
+// ICMB v1.0
+#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_1_0 0x2
+// ICMB v0.9
+#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_0_9 0x3
+// 802.3 LAN
+#define IPMI_CHANNEL_MEDIA_TYPE_802_3_LAN 0x4
+// Asynch. Serial/Modem (RS-232)
+#define IPMI_CHANNEL_MEDIA_TYPE_RS_232 0x5
+// Other LAN
+#define IPMI_CHANNEL_MEDIA_TYPE_OTHER_LAN 0x6
+// PCI SMBus
+#define IPMI_CHANNEL_MEDIA_TYPE_PCI_SM_BUS 0x7
+// SMBus v1.0/1.1
+#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V1 0x8
+// SMBus v2.0
+#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V2 0x9
+// USB 1.x
+#define IPMI_CHANNEL_MEDIA_TYPE_USB1 0xA
+// USB 2.x
+#define IPMI_CHANNEL_MEDIA_TYPE_USB2 0xB
+// System Interface (KCS, SMIC, or BT)
+#define IPMI_CHANNEL_MEDIA_TYPE_SYSTEM_INTERFACE 0xC
+// OEM
+#define IPMI_CHANNEL_MEDIA_TYPE_OEM_START 0x60
+#define IPMI_CHANNEL_MEDIA_TYPE_OEM_END 0x7F
+
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_INFO_CHANNEL_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 ChannelMediumType : 7;
+ UINT8 Reserved : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_INFO_MEDIUM_TYPE;
+
+typedef union {
+ struct {
+ UINT8 ChannelProtocolType : 5;
+ UINT8 Reserved : 3;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_INFO_PROTOCOL_TYPE;
+
+typedef union {
+ struct {
+ UINT8 ActiveSessionCount : 6;
+ UINT8 SessionSupport : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_INFO_SESSION_SUPPORT;
+
typedef struct {
UINT8 CompletionCode;
- UINT8 ChannelNo : 4;
- UINT8 Reserve1 : 4;
- UINT8 ChannelMediumType : 7;
- UINT8 Reserve2 : 1;
- UINT8 ChannelProtocolType : 5;
- UINT8 Reserve3 : 3;
- UINT8 ActiveSessionCount : 6;
- UINT8 SessionSupport : 2;
- UINT8 VendorId[3];
- UINT16 AuxChannelInfo;
+ IPMI_CHANNEL_INFO_CHANNEL_NUMBER ChannelNumber;
+ IPMI_CHANNEL_INFO_MEDIUM_TYPE MediumType;
+ IPMI_CHANNEL_INFO_PROTOCOL_TYPE ProtocolType;
+ IPMI_CHANNEL_INFO_SESSION_SUPPORT SessionSupport;
+ UINT8 VendorId[3];
+ UINT16 AuxChannelInfo;
} IPMI_GET_CHANNEL_INFO_RESPONSE;
//
@@ -453,6 +740,69 @@ typedef struct {
//
// Constants and Structure definitions for "Get User Access" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_CHANNEL_NUMBER;
+
+typedef union {
+ struct {
+ UINT8 UserId : 6;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_USER_ID;
+
+typedef struct {
+ IPMI_GET_USER_ACCESS_CHANNEL_NUMBER ChannelNumber;
+ IPMI_USER_ID UserId;
+} IPMI_GET_USER_ACCESS_REQUEST;
+
+typedef union {
+ struct {
+ UINT8 MaxUserId : 6;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_MAX_USER_ID;
+
+typedef union {
+ struct {
+ UINT8 CurrentUserId : 6;
+ UINT8 UserIdEnableStatus : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_CURRENT_USER;
+
+typedef union {
+ struct {
+ UINT8 FixedUserId : 6;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_FIXED_NAME_USER;
+
+typedef union {
+ struct {
+ UINT8 UserPrivilegeLimit : 4;
+ UINT8 EnableIpmiMessaging : 1;
+ UINT8 EnableUserLinkAuthetication : 1;
+ UINT8 UserAccessAvailable : 1;
+ UINT8 Reserved : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_USER_ACCESS_CHANNEL_ACCESS;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_GET_USER_ACCESS_MAX_USER_ID MaxUserId;
+ IPMI_GET_USER_ACCESS_CURRENT_USER CurrentUser;
+ IPMI_GET_USER_ACCESS_FIXED_NAME_USER FixedNameUser;
+ IPMI_GET_USER_ACCESS_CHANNEL_ACCESS ChannelAccess;
+} IPMI_GET_USER_ACCESS_RESPONSE;
//
// Definitions for Set User Name command
@@ -462,6 +812,10 @@ typedef struct {
//
// Constants and Structure definitions for "Set User Name" command to follow here
//
+typedef struct {
+ IPMI_USER_ID UserId;
+ UINT8 UserName[16];
+} IPMI_SET_USER_NAME_REQUEST;
//
// Definitions for Get User Name command
@@ -471,6 +825,14 @@ typedef struct {
//
// Constants and Structure definitions for "Get User Name" command to follow here
//
+typedef struct {
+ IPMI_USER_ID UserId;
+} IPMI_GET_USER_NAME_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 UserName[16];
+} IPMI_GET_USER_NAME_RESPONSE;
//
// Definitions for Set User Password command
@@ -482,6 +844,43 @@ typedef struct {
//
//
+// Definitions for Set User password command operation type
+//
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_DISABLE_USER 0x0
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_ENABLE_USER 0x1
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_SET_PASSWORD 0x2
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_TEST_PASSWORD 0x3
+
+//
+// Definitions for Set user password command password size
+//
+#define IPMI_SET_USER_PASSWORD_PASSWORD_SIZE_16 0x0
+#define IPMI_SET_USER_PASSWORD_PASSWORD_SIZE_20 0x1
+
+typedef union {
+ struct {
+ UINT8 UserId : 6;
+ UINT8 Reserved : 1;
+ UINT8 PasswordSize : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_USER_PASSWORD_USER_ID;
+
+typedef union {
+ struct {
+ UINT8 Operation : 2;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_USER_PASSWORD_OPERATION;
+
+typedef struct {
+ IPMI_SET_USER_PASSWORD_USER_ID UserId;
+ IPMI_SET_USER_PASSWORD_OPERATION Operation;
+ UINT8 PasswordData[0]; // 16 or 20 bytes, depending on the 'PasswordSize' field
+} IPMI_SET_USER_PASSWORD_REQUEST;
+
+//
// Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24)
//
@@ -619,5 +1018,12 @@ typedef struct {
// Constants and Structure definitions for "Get System Interface Capabilities" command to follow here
//
+//
+// Definitions for Get System Interface Capabilities command SSIF transaction support
+//
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_SINGLE_PARTITION_RW 0x0
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_MULTI_PARTITION_RW 0x1
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_MULTI_PARTITION_RW_WITH_MIDDLE 0x2
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h b/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
index 7f174fdc6975..640a5402e305 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
@@ -7,13 +7,7 @@
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_BRIDGE_H_
@@ -133,12 +127,12 @@
//
//
-// Definitions for Prepare for Discoveery command
+// Definitions for Prepare for Discovery command
//
#define IPMI_BRIDGE_PREPARE_FOR_DISCOVERY 0x10
//
-// Constants and Structure definitions for "Prepare for Discoveery" command to follow here
+// Constants and Structure definitions for "Prepare for Discovery" command to follow here
//
//
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
index 833feeb9dd87..c20091fedcf2 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
@@ -7,14 +7,8 @@
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
- Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_CHASSIS_H_
@@ -38,6 +32,15 @@
//
// Constants and Structure definitions for "Get Chassis Capabilities" command to follow here
//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 CapabilitiesFlags;
+ UINT8 ChassisFruInfoDeviceAddress;
+ UINT8 ChassisSDRDeviceAddress;
+ UINT8 ChassisSELDeviceAddress;
+ UINT8 ChassisSystemManagementDeviceAddress;
+ UINT8 ChassisBridgeDeviceAddress;
+} IPMI_GET_CHASSIS_CAPABILITIES_RESPONSE;
//
// Definitions for Get Chassis Status command
@@ -47,6 +50,13 @@
//
// Constants and Structure definitions for "Get Chassis Status" command to follow here
//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 CurrentPowerState;
+ UINT8 LastPowerEvent;
+ UINT8 MiscChassisState;
+ UINT8 FrontPanelButtonCapabilities;
+} IPMI_GET_CHASSIS_STATUS_RESPONSE;
//
// Definitions for Chassis Control command
@@ -56,6 +66,17 @@
//
// Constants and Structure definitions for "Chassis Control" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ChassisControl:4;
+ UINT8 Reserved:4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL;
+
+typedef struct {
+ IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL ChassisControl;
+} IPMI_CHASSIS_CONTROL_REQUEST;
//
// Definitions for Chassis Reset command
@@ -92,6 +113,22 @@
//
// Constants and Structure definitions for "Set Power Restore Policy" command to follow here
//
+typedef union {
+ struct {
+ UINT8 PowerRestorePolicy : 3;
+ UINT8 Reserved : 5;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_POWER_RESTORE_POLICY;
+
+typedef struct {
+ IPMI_POWER_RESTORE_POLICY PowerRestorePolicy;
+} IPMI_SET_POWER_RESTORE_POLICY_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 PowerRestorePolicySupport;
+} IPMI_SET_POWER_RESTORE_POLICY_RESPONSE;
//
// Definitions for Get System Restart Cause command
@@ -101,26 +138,31 @@
//
// Constants and Structure definitions for "Get System Restart Cause" command to follow here
//
-typedef enum {
- Unknown,
- ChassisControlCommand,
- ResetViaPushButton,
- PowerupViaPowerButton,
- WatchdogExpiration,
- Oem,
- AutoPowerOnAlwaysRestore,
- AutoPowerOnRestorePrevious,
- ResetViaPef,
- PowerCycleViaPef,
- SoftReset,
- PowerUpViaRtc
+#define IPMI_SYSTEM_RESTART_CAUSE_UNKNOWN 0x0
+#define IPMI_SYSTEM_RESTART_CAUSE_CHASSIS_CONTROL_COMMAND 0x1
+#define IPMI_SYSTEM_RESTART_CAUSE_PUSHBUTTON_RESET 0x2
+#define IPMI_SYSTEM_RESTART_CAUSE_PUSHBUTTON_POWERUP 0x3
+#define IPMI_SYSTEM_RESTART_CAUSE_WATCHDOG_EXPIRE 0x4
+#define IPMI_SYSTEM_RESTART_CAUSE_OEM 0x5
+#define IPMI_SYSTEM_RESTART_CAUSE_AUTO_POWER_ALWAYS_RESTORE 0x6
+#define IPMI_SYSTEM_RESTART_CAUSE_AUTO_POWER_RESTORE_PREV 0x7
+#define IPMI_SYSTEM_RESTART_CAUSE_PEF_RESET 0x8
+#define IPMI_SYSTEM_RESTART_CAUSE_PEF_POWERCYCLE 0x9
+#define IPMI_SYSTEM_RESTART_CAUSE_SOFT_RESET 0xA
+#define IPMI_SYSTEM_RESTART_CAUSE_RTC_POWERUP 0xB
+
+typedef union {
+ struct {
+ UINT8 Cause:4;
+ UINT8 Reserved:4;
+ } Bits;
+ UINT8 Uint8;
} IPMI_SYSTEM_RESTART_CAUSE;
typedef struct {
- UINT8 CompletionCode;
- UINT8 Cause:4;
- UINT8 Reserved:4;
- UINT8 ChannelNumber;
+ UINT8 CompletionCode;
+ IPMI_SYSTEM_RESTART_CAUSE RestartCause;
+ UINT8 ChannelNumber;
} IPMI_GET_SYSTEM_RESTART_CAUSE_RESPONSE;
//
@@ -131,25 +173,39 @@ typedef struct {
//
// Constants and Structure definitions for "Set System boot options" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ParameterSelector:7;
+ UINT8 MarkParameterInvalid:1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID;
+
typedef struct {
- UINT8 ParameterSelector:7;
- UINT8 MarkParameterInvalid:1;
- UINT8 ParameterData[1];
+ IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid;
+ UINT8 ParameterData[0];
} IPMI_SET_BOOT_OPTIONS_REQUEST;
//
-// Definitions for Get System BOOT options command
+// Definitions for Get System Boot options command
//
#define IPMI_CHASSIS_GET_SYSTEM_BOOT_OPTIONS 0x09
//
// Constants and Structure definitions for "Get System boot options" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ParameterSelector:7;
+ UINT8 Reserved:1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR;
+
typedef struct {
- UINT8 ParameterSelector:7;
- UINT8 Reserved:1;
- UINT8 SetSelector;
- UINT8 BlockSelector;
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR ParameterSelector;
+ UINT8 SetSelector;
+ UINT8 BlockSelector;
} IPMI_GET_BOOT_OPTIONS_REQUEST;
typedef struct {
@@ -172,26 +228,49 @@ typedef struct {
} IPMI_BOOT_INITIATOR;
//
+// Definitions for boot option parameter selector
+//
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SET_IN_PROGRESS 0x0
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SERVICE_PARTITION_SELECTOR 0x1
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SERVICE_PARTITION_SCAN 0x2
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_BMC_BOOT_FLAG 0x3
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INFO_ACK 0x4
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_FLAGS 0x5
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INITIATOR_INFO 0x6
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INITIATOR_MAILBOX 0x7
+#define IPMI_BOOT_OPTIONS_PARAMETER_OEM_BEGIN 0x60
+#define IPMI_BOOT_OPTIONS_PARAMETER_OEM_END 0x7F
+
+//
// Response Parameters for IPMI Get Boot Options
//
-typedef struct {
- UINT8 SetInProgress: 2;
- UINT8 Reserved: 6;
+typedef union {
+ struct {
+ UINT8 SetInProgress : 2;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0;
typedef struct {
UINT8 ServicePartitionSelector;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1;
-typedef struct {
- UINT8 ServicePartitionDiscovered:1;
- UINT8 ServicePartitionScanRequest:1;
- UINT8 Reserved: 5;
+typedef union {
+ struct {
+ UINT8 ServicePartitionDiscovered : 1;
+ UINT8 ServicePartitionScanRequest : 1;
+ UINT8 Reserved: 6;
+ } Bits;
+ UINT8 Uint8;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2;
-typedef struct {
- UINT8 BmcBootFlagValid: 5;
- UINT8 Reserved: 3;
+typedef union {
+ struct {
+ UINT8 BmcBootFlagValid : 5;
+ UINT8 Reserved : 3;
+ } Bits;
+ UINT8 Uint8;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3;
typedef struct {
@@ -199,45 +278,101 @@ typedef struct {
UINT8 BootInitiatorAcknowledgeData;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4;
+//
+// Definitions for the 'Boot device selector' field of Boot Option Parameters #5
+//
+#define IPMI_BOOT_DEVICE_SELECTOR_NO_OVERRIDE 0x0
+#define IPMI_BOOT_DEVICE_SELECTOR_PXE 0x1
+#define IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE 0x2
+#define IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE_SAFE_MODE 0x3
+#define IPMI_BOOT_DEVICE_SELECTOR_DIAGNOSTIC_PARTITION 0x4
+#define IPMI_BOOT_DEVICE_SELECTOR_CD_DVD 0x5
+#define IPMI_BOOT_DEVICE_SELECTOR_BIOS_SETUP 0x6
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_FLOPPY 0x7
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_CD_DVD 0x8
+#define IPMI_BOOT_DEVICE_SELECTOR_PRIMARY_REMOTE_MEDIA 0x9
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_HARDDRIVE 0xB
+#define IPMI_BOOT_DEVICE_SELECTOR_FLOPPY 0xF
+
#define BOOT_OPTION_HANDLED_BY_BIOS 0x01
+//
+// Constant definitions for the 'BIOS Mux Control Override' field of Boot Option Parameters #5
+//
+#define BIOS_MUX_CONTROL_OVERRIDE_RECOMMEND_SETTING 0x00
+#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_BMC 0x01
+#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_SYSTEM 0x02
+
+typedef union {
+ struct {
+ UINT8 Reserved:5;
+ UINT8 BiosBootType:1;
+ UINT8 PersistentOptions:1;
+ UINT8 BootFlagValid:1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1;
+
+typedef union {
+ struct {
+ UINT8 LockReset:1;
+ UINT8 ScreenBlank:1;
+ UINT8 BootDeviceSelector:4;
+ UINT8 LockKeyboard:1;
+ UINT8 CmosClear:1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2;
+
+typedef union {
+ struct {
+ UINT8 ConsoleRedirection:2;
+ UINT8 LockSleep:1;
+ UINT8 UserPasswordBypass:1;
+ UINT8 ForceProgressEventTrap:1;
+ UINT8 BiosVerbosity:2;
+ UINT8 LockPower:1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3;
+
+typedef union {
+ struct {
+ UINT8 BiosMuxControlOverride:3;
+ UINT8 BiosSharedModeOverride:1;
+ UINT8 Reserved:4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4;
+
+typedef union {
+ struct {
+ UINT8 DeviceInstanceSelector:5;
+ UINT8 Reserved:3;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5;
+
typedef struct {
- //
- // Data 1
- //
- UINT8 Reserved0:6;
- UINT8 PersistentOptions:1;
- UINT8 BootFlagValid:1;
- //
- // Data 2
- //
- UINT8 LockReset:1;
- UINT8 ScreenBlank:1;
- UINT8 BootDeviceSelector:4;
- UINT8 LockKeyboard:1;
- UINT8 CmosClear:1;
- //
- //
- // Data 3
- UINT8 ConsoleRedirection:2;
- UINT8 LockSleep:1;
- UINT8 UserPasswordBypass:1;
- UINT8 ForceProgressEventTrap:1;
- UINT8 BiosVerbosity:2;
- UINT8 LockPower:1;
- //
- // Data 4
- //
- UINT8 BiosMuxControlOverride:2;
- UINT8 BiosSharedModeOverride:1;
- UINT8 Reserved1:4;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1 Data1;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2 Data2;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3 Data3;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4 Data4;
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5 Data5;
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5;
+typedef union {
+ struct {
+ UINT8 ChannelNumber:4;
+ UINT8 Reserved:4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_BOOT_OPTIONS_CHANNEL_NUMBER;
+
typedef struct {
- UINT8 ChannelNumber:4;
- UINT8 Reserved:4;
- UINT8 SessionId[4];
- UINT8 BootInfoTimeStamp[4];
+ IPMI_BOOT_OPTIONS_CHANNEL_NUMBER ChannelNumber;
+ UINT8 SessionId[4];
+ UINT8 BootInfoTimeStamp[4];
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6;
typedef struct {
@@ -256,13 +391,27 @@ typedef union {
IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7 Parm7;
} IPMI_BOOT_OPTIONS_PARAMETERS;
+typedef union {
+ struct {
+ UINT8 ParameterVersion:4;
+ UINT8 Reserved:4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION;
+
+typedef union {
+ struct {
+ UINT8 ParameterSelector:7;
+ UINT8 ParameterValid:1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID;
+
typedef struct {
- UINT8 CompletionCode;
- UINT8 ParameterVersion:4;
- UINT8 Reserved:4;
- UINT8 ParameterSelector:7;
- UINT8 ParameterValid:1;
- UINT8 ParameterData[1];
+ UINT8 CompletionCode;
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION ParameterVersion;
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid;
+ UINT8 ParameterData[0];
} IPMI_GET_BOOT_OPTIONS_RESPONSE;
//
@@ -270,17 +419,23 @@ typedef struct {
//
#define IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES 0x0A
-typedef struct {
- UINT8 DisablePoweroffButton:1;
- UINT8 DisableResetButton:1;
- UINT8 DisableDiagnosticInterruptButton:1;
- UINT8 DisableStandbyButton:1;
- UINT8 Reserved:4;
-} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST;
-
//
// Constants and Structure definitions for "Set front panel button enables" command to follow here
//
+typedef union {
+ struct {
+ UINT8 DisablePoweroffButton:1;
+ UINT8 DisableResetButton:1;
+ UINT8 DisableDiagnosticInterruptButton:1;
+ UINT8 DisableStandbyButton:1;
+ UINT8 Reserved:4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_FRONT_PANEL_BUTTON_ENABLES;
+
+typedef struct {
+ IPMI_FRONT_PANEL_BUTTON_ENABLES FrontPanelButtonEnables;
+} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST;
//
// Definitions for Set Power Cycle Interval command
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
index aba3c41d06c3..55886b16dcd6 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
@@ -2,13 +2,7 @@
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_FIRMWARE_H_
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h b/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
index 2a8ec6956703..fbadfcd7f0a6 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
@@ -2,13 +2,7 @@
IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_GROUP_EXTENSION_H_
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h b/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
index f9d851e6ca1c..dd090004921f 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
@@ -10,13 +10,7 @@
and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_SENSOR_EVENT_H_
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h b/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
index 210db1e7e933..c69df8f303fe 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
@@ -10,14 +10,8 @@
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
- Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_STORAGE_H_
@@ -45,14 +39,23 @@
//
// Constants and Structure definitions for "Get Fru Inventory Area Info" command to follow here
//
+typedef struct {
+ UINT8 DeviceId;
+} IPMI_GET_FRU_INVENTORY_AREA_INFO_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 InventoryAreaSize;
+ UINT8 AccessType;
+} IPMI_GET_FRU_INVENTORY_AREA_INFO_RESPONSE;
//
-// Definitions for Get Fru Data command
+// Definitions for Read Fru Data command
//
#define IPMI_STORAGE_READ_FRU_DATA 0x11
//
-// Constants and Structure definitions for "Get Fru Data" command to follow here
+// Constants and Structure definitions for "Read Fru Data" command to follow here
//
typedef struct {
UINT8 FruDeviceId;
@@ -64,6 +67,18 @@ typedef struct {
UINT8 Count;
} IPMI_FRU_READ_COMMAND;
+typedef struct {
+ UINT8 DeviceId;
+ UINT16 InventoryOffset;
+ UINT8 CountToRead;
+} IPMI_READ_FRU_DATA_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 CountReturned;
+ UINT8 Data[0];
+} IPMI_READ_FRU_DATA_RESPONSE;
+
//
// Definitions for Write Fru Data command
//
@@ -77,6 +92,17 @@ typedef struct {
UINT8 FruData[16];
} IPMI_FRU_WRITE_COMMAND;
+typedef struct {
+ UINT8 DeviceId;
+ UINT16 InventoryOffset;
+ UINT8 Data[0];
+} IPMI_WRITE_FRU_DATA_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 CountWritten;
+} IPMI_WRITE_FRU_DATA_RESPONSE;
+
//
// Below is Definitions for SDR Repository (Chapter 33)
//
@@ -89,21 +115,28 @@ typedef struct {
//
// Constants and Structure definitions for "Get SDR Repository Info" command to follow here
//
+typedef union {
+ struct {
+ UINT8 SdrRepAllocInfoCmd : 1;
+ UINT8 SdrRepReserveCmd : 1;
+ UINT8 PartialAddSdrCmd : 1;
+ UINT8 DeleteSdrRepCmd : 1;
+ UINT8 Reserved : 1;
+ UINT8 SdrRepUpdateOp : 2;
+ UINT8 Overflow : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_OPERATION_SUPPORT;
+
typedef struct {
- UINT8 CompletionCode;
- UINT8 Version;
- UINT16 RecordCount;
- UINT16 FreeSpace;
- UINT32 RecentAdditionTimeStamp;
- UINT32 RecentEraseTimeStamp;
- UINT8 SdrRepAllocInfoCmd : 1;
- UINT8 SdrRepReserveCmd : 1;
- UINT8 PartialAddSdrCmd : 1;
- UINT8 DeleteSdrRepCmd : 1;
- UINT8 Reserved : 1;
- UINT8 SdrRepUpdateOp : 2;
- UINT8 Overflow : 1;
-} IPMI_GET_SDR_REPOSITORY_INFO;
+ UINT8 CompletionCode;
+ UINT8 Version;
+ UINT16 RecordCount;
+ UINT16 FreeSpace;
+ UINT32 RecentAdditionTimeStamp;
+ UINT32 RecentEraseTimeStamp;
+ IPMI_SDR_OPERATION_SUPPORT OperationSupport;
+} IPMI_GET_SDR_REPOSITORY_INFO_RESPONSE;
//
// Definitions for Get SDR Repository Allocateion Info command
@@ -122,6 +155,10 @@ typedef struct {
//
// Constants and Structure definitions for "Reserve SDR Repository" command to follow here
//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ReservationId[2]; // Reservation ID. LS byte first.
+} IPMI_RESERVE_SDR_REPOSITORY_RESPONSE;
//
// Definitions for Get SDR command
@@ -131,149 +168,201 @@ typedef struct {
//
// Constants and Structure definitions for "Get SDR" command to follow here
//
+typedef union {
+ struct {
+ UINT8 EventScanningEnabled : 1;
+ UINT8 EventScanningDisabled : 1;
+ UINT8 InitSensorType : 1;
+ UINT8 InitHysteresis : 1;
+ UINT8 InitThresholds : 1;
+ UINT8 InitEvent : 1;
+ UINT8 InitScanning : 1;
+ UINT8 SettableSensor : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_SENSOR_INIT;
+
+typedef union {
+ struct {
+ UINT8 EventMessageControl : 2;
+ UINT8 ThresholdAccessSupport : 2;
+ UINT8 HysteresisSupport : 2;
+ UINT8 ReArmSupport : 1;
+ UINT8 IgnoreSensor : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_SENSOR_CAP;
+
+typedef union {
+ struct {
+ UINT8 Linearization : 7;
+ UINT8 Reserved : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_LINEARIZATION;
+
+typedef union {
+ struct {
+ UINT8 Toleremce : 6;
+ UINT8 MHi : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_M_TOLERANCE;
+
+typedef union {
+ struct {
+ UINT8 AccuracyLow : 6;
+ UINT8 BHi : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_B_ACCURACY;
+
+typedef union {
+ struct {
+ UINT8 Reserved : 2;
+ UINT8 AccuracyExp : 2;
+ UINT8 AccuracyHi : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR;
+
+typedef union {
+ struct {
+ UINT8 BExp : 4;
+ UINT8 RExp : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_R_EXP_B_EXP;
+
+typedef union {
+ struct {
+ UINT8 NominalReadingSpscified : 1;
+ UINT8 NominalMaxSpscified : 1;
+ UINT8 NominalMinSpscified : 1;
+ UINT8 Reserved : 5;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_ANALOG_FLAGS;
typedef struct {
- UINT16 RecordId; // 1
- UINT8 Version; // 3
- UINT8 RecordType; // 4
- UINT8 RecordLength; // 5
- UINT8 OwnerId; // 6
- UINT8 OwnerLun; // 7
- UINT8 SensorNumber; // 8
- UINT8 EntityId; // 9
- UINT8 EntityInstance; // 10
- UINT8 EventScanningEnabled : 1; // 11
- UINT8 EventScanningDisabled : 1; // 11
- UINT8 InitSensorType : 1; // 11
- UINT8 InitHysteresis : 1; // 11
- UINT8 InitThresholds : 1; // 11
- UINT8 InitEvent : 1; // 11
- UINT8 InitScanning : 1; // 11
- UINT8 Reserved : 1; // 11
- UINT8 EventMessageControl : 2; // 12
- UINT8 ThresholdAccessSupport : 2; // 12
- UINT8 HysteresisSupport : 2; // 12
- UINT8 ReArmSupport : 1; // 12
- UINT8 IgnoreSensor : 1; // 12
- UINT8 SensorType; // 13
- UINT8 EventType; // 14
- UINT8 Reserved1[7]; // 15
- UINT8 UnitType; // 22
- UINT8 Reserved2; // 23
- UINT8 Linearization : 7; // 24
- UINT8 Reserved3 : 1; // 24
- UINT8 MLo; // 25
- UINT8 Toleremce : 6; // 26
- UINT8 MHi : 2; // 26
- UINT8 BLo; // 27
- UINT8 AccuracyLow : 6; // 28
- UINT8 BHi : 2; // 28
- UINT8 Reserved4 : 2; // 29
- UINT8 AccuracyExp : 2; // 29
- UINT8 AccuracyHi : 4; // 29
- UINT8 BExp : 4; // 30
- UINT8 RExp : 4; // 30
- UINT8 NominalReadingSpscified : 1; // 31
- UINT8 NominalMaxSpscified : 1; // 31
- UINT8 NominalMinSpscified : 1; // 31
- UINT8 Reserved5 : 5; // 31
- UINT8 NominalReading; // 32
- UINT8 Reserved6[4]; // 33
- UINT8 UpperNonRecoverThreshold; // 37
- UINT8 UpperCriticalThreshold; // 38
- UINT8 UpperNonCriticalThreshold; // 39
- UINT8 LowerNonRecoverThreshold; // 40
- UINT8 LowerCriticalThreshold; // 41
- UINT8 LowerNonCriticalThreshold; // 42
- UINT8 Reserved7[5]; // 43
- UINT8 IdStringLength; // 48
- UINT8 AsciiIdString[16]; // 49 - 64
+ UINT16 RecordId; // 1
+ UINT8 Version; // 3
+ UINT8 RecordType; // 4
+ UINT8 RecordLength; // 5
+ UINT8 OwnerId; // 6
+ UINT8 OwnerLun; // 7
+ UINT8 SensorNumber; // 8
+ UINT8 EntityId; // 9
+ UINT8 EntityInstance; // 10
+ IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11
+ IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12
+ UINT8 SensorType; // 13
+ UINT8 EventType; // 14
+ UINT8 Reserved1[7]; // 15
+ UINT8 UnitType; // 22
+ UINT8 Reserved2; // 23
+ IPMI_SDR_RECORD_LINEARIZATION Linearization; // 24
+ UINT8 MLo; // 25
+ IPMI_SDR_RECORD_M_TOLERANCE MHiTolerance; // 26
+ UINT8 BLo; // 27
+ IPMI_SDR_RECORD_B_ACCURACY BHiAccuracyLo; // 28
+ IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR AccuracySensorDirection; // 29
+ IPMI_SDR_RECORD_R_EXP_B_EXP RExpBExp; // 30
+ IPMI_SDR_RECORD_ANALOG_FLAGS AnalogFlags; // 31
+ UINT8 NominalReading; // 32
+ UINT8 Reserved3[4]; // 33
+ UINT8 UpperNonRecoverThreshold; // 37
+ UINT8 UpperCriticalThreshold; // 38
+ UINT8 UpperNonCriticalThreshold; // 39
+ UINT8 LowerNonRecoverThreshold; // 40
+ UINT8 LowerCriticalThreshold; // 41
+ UINT8 LowerNonCriticalThreshold; // 42
+ UINT8 Reserved4[5]; // 43
+ UINT8 IdStringLength; // 48
+ UINT8 AsciiIdString[16]; // 49 - 64
} IPMI_SDR_RECORD_STRUCT_1;
typedef struct {
- UINT16 RecordId; // 1
- UINT8 Version; // 3
- UINT8 RecordType; // 4
- UINT8 RecordLength; // 5
- UINT8 OwnerId; // 6
- UINT8 OwnerLun; // 7
- UINT8 SensorNumber; // 8
- UINT8 EntityId; // 9
- UINT8 EntityInstance; // 10
- UINT8 SensorScanning : 1; // 11
- UINT8 EventScanning : 1; // 11
- UINT8 InitSensorType : 1; // 11
- UINT8 InitHysteresis : 1; // 11
- UINT8 InitThresholds : 1; // 11
- UINT8 InitEvent : 1; // 11
- UINT8 InitScanning : 1; // 11
- UINT8 Reserved : 1; // 11
- UINT8 EventMessageControl : 2; // 12
- UINT8 ThresholdAccessSupport : 2; // 12
- UINT8 HysteresisSupport : 2; // 12
- UINT8 ReArmSupport : 1; // 12
- UINT8 IgnoreSensor : 1; // 12
- UINT8 SensorType; // 13
- UINT8 EventType; // 14
- UINT8 Reserved1[7]; // 15
- UINT8 UnitType; // 22
- UINT8 Reserved2[9]; // 23
- UINT8 IdStringLength; // 32
- UINT8 AsciiIdString[16]; // 33 - 48
+ UINT16 RecordId; // 1
+ UINT8 Version; // 3
+ UINT8 RecordType; // 4
+ UINT8 RecordLength; // 5
+ UINT8 OwnerId; // 6
+ UINT8 OwnerLun; // 7
+ UINT8 SensorNumber; // 8
+ UINT8 EntityId; // 9
+ UINT8 EntityInstance; // 10
+ IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11
+ IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12
+ UINT8 SensorType; // 13
+ UINT8 EventType; // 14
+ UINT8 Reserved1[7]; // 15
+ UINT8 UnitType; // 22
+ UINT8 Reserved2[9]; // 23
+ UINT8 IdStringLength; // 32
+ UINT8 AsciiIdString[16]; // 33 - 48
} IPMI_SDR_RECORD_STRUCT_2;
-typedef struct {
- UINT8 Reserved1 : 1;
- UINT8 ControllerSlaveAddress : 7;
- UINT8 FruDeviceId;
- UINT8 BusId : 3;
- UINT8 Lun : 2;
- UINT8 Reserved : 2;
- UINT8 LogicalFruDevice : 1;
- UINT8 Reserved3 : 4;
- UINT8 ChannelNumber : 4;
+typedef union {
+ struct {
+ UINT8 Reserved1 : 1;
+ UINT8 ControllerSlaveAddress : 7;
+ UINT8 FruDeviceId;
+ UINT8 BusId : 3;
+ UINT8 Lun : 2;
+ UINT8 Reserved2 : 2;
+ UINT8 LogicalFruDevice : 1;
+ UINT8 Reserved3 : 4;
+ UINT8 ChannelNumber : 4;
+ } Bits;
+ UINT32 Uint32;
} IPMI_FRU_DATA_INFO;
+typedef union {
+ struct {
+ UINT8 Length : 4;
+ UINT8 Reserved : 1;
+ UINT8 StringType : 3;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH;
+
typedef struct {
- UINT16 RecordId; // 1
- UINT8 Version; // 3
- UINT8 RecordType; // 4
- UINT8 RecordLength; // 5
- IPMI_FRU_DATA_INFO FruDeviceData; // 6
- UINT8 Reserved1; // 10
- UINT8 DeviceType; // 11
- UINT8 DeviceTypeModifier; // 12
- UINT8 FruEntityId; // 13
- UINT8 FruEntityInstance; // 14
- UINT8 OemReserved; // 15
- UINT8 Length : 4; // 16
- UINT8 Reserved2 : 1; // 16
- UINT8 StringType : 3; // 16
- UINT8 String[16]; // 17
+ UINT16 RecordId; // 1
+ UINT8 Version; // 3
+ UINT8 RecordType; // 4
+ UINT8 RecordLength; // 5
+ IPMI_FRU_DATA_INFO FruDeviceData; // 6
+ UINT8 Reserved; // 10
+ UINT8 DeviceType; // 11
+ UINT8 DeviceTypeModifier; // 12
+ UINT8 FruEntityId; // 13
+ UINT8 FruEntityInstance; // 14
+ UINT8 OemReserved; // 15
+ IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH StringTypeLength; // 16
+ UINT8 String[16]; // 17
} IPMI_SDR_RECORD_STRUCT_11;
typedef struct {
- UINT16 NextRecordId; //1
- UINT16 RecordId; //3
- UINT8 Version; //5
- UINT8 RecordType; //6
- UINT8 RecordLength; //7
- UINT8 ManufacturerId[3]; //8
+ UINT16 RecordId; //1
+ UINT8 Version; //3
+ UINT8 RecordType; //4
+ UINT8 RecordLength; //5
+ UINT8 ManufacturerId[3]; //6
UINT8 StringChars[20];
} IPMI_SDR_RECORD_STRUCT_C0;
typedef struct {
- UINT16 NextRecordId; //1
- UINT16 RecordId; //3
- UINT8 Version; //5
- UINT8 RecordType; //6
- UINT8 RecordLength; //7
+ UINT16 RecordId; //1
+ UINT8 Version; //3
+ UINT8 RecordType; //4
+ UINT8 RecordLength; //5
} IPMI_SDR_RECORD_STRUCT_HEADER;
typedef union {
- IPMI_SDR_RECORD_STRUCT_1 SensorType1;
- IPMI_SDR_RECORD_STRUCT_2 SensorType2;
- IPMI_SDR_RECORD_STRUCT_11 SensorType11;
+ IPMI_SDR_RECORD_STRUCT_1 SensorType1;
+ IPMI_SDR_RECORD_STRUCT_2 SensorType2;
+ IPMI_SDR_RECORD_STRUCT_11 SensorType11;
IPMI_SDR_RECORD_STRUCT_C0 SensorTypeC0;
IPMI_SDR_RECORD_STRUCT_HEADER SensorHeader;
} IPMI_SENSOR_RECORD_STRUCT;
@@ -285,6 +374,12 @@ typedef struct {
UINT8 BytesToRead;
} IPMI_GET_SDR_REQUEST;
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 NextRecordId;
+ IPMI_SENSOR_RECORD_STRUCT RecordData;
+} IPMI_GET_SDR_RESPONSE;
+
//
// Definitions for Add SDR command
//
@@ -378,6 +473,12 @@ typedef struct {
//
// Constants and Structure definitions for "Get SEL Info" command to follow here
//
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_GET_SEL_ALLOCATION_INFO_CMD BIT0
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_RESERVE_SEL_CMD BIT1
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_PARTIAL_ADD_SEL_ENTRY_CMD BIT2
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_DELETE_SEL_CMD BIT3
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_OVERFLOW_FLAG BIT7
+
typedef struct {
UINT8 CompletionCode;
UINT8 Version; // Version of SEL
@@ -405,6 +506,10 @@ typedef struct {
//
// Constants and Structure definitions for "Reserve SEL" command to follow here
//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ReservationId[2]; // Reservation ID. LS byte first.
+} IPMI_RESERVE_SEL_RESPONSE;
//
// Definitions for Get SEL Entry command
@@ -414,6 +519,38 @@ typedef struct {
//
// Constants and Structure definitions for "Get SEL Entry" command to follow here
//
+
+//
+// Below is Definitions for SEL Record Formats (Chapter 32)
+//
+typedef struct {
+ UINT16 RecordId;
+ UINT8 RecordType;
+ UINT32 TimeStamp;
+ UINT16 GeneratorId;
+ UINT8 EvMRevision;
+ UINT8 SensorType;
+ UINT8 SensorNumber;
+ UINT8 EventDirType;
+ UINT8 OEMEvData1;
+ UINT8 OEMEvData2;
+ UINT8 OEMEvData3;
+} IPMI_SEL_EVENT_RECORD_DATA;
+
+typedef struct {
+ UINT16 RecordId;
+ UINT8 RecordType; // C0h-DFh = OEM system event record
+ UINT32 TimeStamp;
+ UINT8 ManufacturerId[3];
+ UINT8 OEMDefined[6];
+} IPMI_TIMESTAMPED_OEM_SEL_RECORD_DATA;
+
+typedef struct {
+ UINT16 RecordId;
+ UINT8 RecordType; // E0h-FFh = OEM system event record
+ UINT8 OEMDefined[13];
+} IPMI_NON_TIMESTAMPED_OEM_SEL_RECORD_DATA;
+
typedef struct {
UINT8 ReserveId[2]; // Reservation ID, LS Byte First
UINT8 SelRecID[2]; // Sel Record ID, LS Byte First
@@ -421,6 +558,12 @@ typedef struct {
UINT8 BytesToRead; // Bytes to be Read, 0xFF for entire record
} IPMI_GET_SEL_ENTRY_REQUEST;
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 NextSelRecordId; // Next SEL Record ID, LS Byte first
+ IPMI_SEL_EVENT_RECORD_DATA RecordData;
+} IPMI_GET_SEL_ENTRY_RESPONSE;
+
//
// Definitions for Add SEL Entry command
//
@@ -429,6 +572,14 @@ typedef struct {
//
// Constants and Structure definitions for "Add SEL Entry" command to follow here
//
+typedef struct {
+ IPMI_SEL_EVENT_RECORD_DATA RecordData;
+} IPMI_ADD_SEL_ENTRY_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 RecordId; // Record ID for added record, LS Byte first
+} IPMI_ADD_SEL_ENTRY_RESPONSE;
//
// Definitions for Partial Add SEL Entry command
@@ -438,6 +589,18 @@ typedef struct {
//
// Constants and Structure definitions for "Partial Add SEL Entry" command to follow here
//
+typedef struct {
+ UINT16 ReservationId;
+ UINT16 RecordId;
+ UINT8 OffsetIntoRecord;
+ UINT8 InProgress;
+ UINT8 RecordData[0];
+} IPMI_PARTIAL_ADD_SEL_ENTRY_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 RecordId;
+} IPMI_PARTIAL_ADD_SEL_ENTRY_RESPONSE;
//
// Definitions for Delete SEL Entry command
@@ -450,7 +613,15 @@ typedef struct {
typedef struct {
UINT8 ReserveId[2]; // Reservation ID, LS byte first
UINT8 RecordToDelete[2]; // Record to Delete, LS Byte First
-} IPMI_DELETE_SEL_REQUEST;
+} IPMI_DELETE_SEL_ENTRY_REQUEST;
+
+#define IPMI_DELETE_SEL_ENTRY_RESPONSE_TYPE_UNSUPPORTED 0x80
+#define IPMI_DELETE_SEL_ENTRY_RESPONSE_ERASE_IN_PROGRESS 0x81
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT16 RecordId; // Record ID added. LS byte first
+} IPMI_DELETE_SEL_ENTRY_RESPONSE;
//
// Definitions for Clear SEL command
@@ -460,6 +631,12 @@ typedef struct {
//
// Constants and Structure definitions for "Clear SEL" command to follow here
//
+#define IPMI_CLEAR_SEL_REQUEST_C_CHAR_ASCII 0x43
+#define IPMI_CLEAR_SEL_REQUEST_L_CHAR_ASCII 0x4C
+#define IPMI_CLEAR_SEL_REQUEST_R_CHAR_ASCII 0x52
+#define IPMI_CLEAR_SEL_REQUEST_INITIALIZE_ERASE 0xAA
+#define IPMI_CLEAR_SEL_REQUEST_GET_ERASE_STATUS 0x00
+
typedef struct {
UINT8 Reserve[2]; // Reserve ID, LSB first
UINT8 AscC; // Ascii for 'C' (0x43)
@@ -468,6 +645,14 @@ typedef struct {
UINT8 Erase; // 0xAA, Initiate Erase, 0x00 Get Erase Status
} IPMI_CLEAR_SEL_REQUEST;
+#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_IN_PROGRESS 0x00
+#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_COMPLETED 0x01
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ErasureProgress;
+} IPMI_CLEAR_SEL_RESPONSE;
+
//
// Definitions for Get SEL Time command
//
@@ -476,6 +661,10 @@ typedef struct {
//
// Constants and Structure definitions for "Get SEL Time" command to follow here
//
+typedef struct {
+ UINT8 CompletionCode;
+ UINT32 Timestamp; // Present Timestamp clock reading. LS byte first.
+} IPMI_GET_SEL_TIME_RESPONSE;
//
// Definitions for Set SEL Time command
@@ -485,6 +674,9 @@ typedef struct {
//
// Constants and Structure definitions for "Set SEL Time" command to follow here
//
+typedef struct {
+ UINT32 Timestamp;
+} IPMI_SET_SEL_TIME_REQUEST;
//
// Definitions for Get Auxillary Log Status command
@@ -504,39 +696,88 @@ typedef struct {
// Constants and Structure definitions for "Set Auxillary Log Status" command to follow here
//
-#define IPMI_COMPLETE_SEL_RECORD 0xFF
+//
+// Definitions for Get SEL Time UTC Offset command
+//
+#define IPMI_STORAGE_GET_SEL_TIME_UTC_OFFSET 0x5C
//
-// Below is Definitions for SEL Record Formats (Chapter 32)
+// Constants and Structure definitions for "Get SEL Time UTC Offset" command to follow here
//
typedef struct {
- UINT16 RecordId;
- UINT8 RecordType;
- UINT32 TimeStamp;
- UINT16 GeneratorId;
- UINT8 EvMRevision;
- UINT8 SensorType;
- UINT8 SensorNumber;
- UINT8 EventDirType;
- UINT8 OEMEvData1;
- UINT8 OEMEvData2;
- UINT8 OEMEvData3;
-} IPMI_SEL_EVENT_RECORD_DATA;
+ UINT8 CompletionCode;
+ //
+ // 16-bit, 2s-complement signed integer for the offset in minutes from UTC to SEL Time.
+ // LS-byte first. (ranges from -1440 to 1440)
+ //
+ INT16 UtcOffset;
+} IPMI_GET_SEL_TIME_UTC_OFFSET_RESPONSE;
-#define IPMI_SEL_SYSTEM_RECORD 0x02
+//
+// Definitions for Set SEL Time UTC Offset command
+//
+#define IPMI_STORAGE_SET_SEL_TIME_UTC_OFFSET 0x5D
-#define IPMI_EVM_REVISION 0x04
-#define IPMI_BIOS_ID 0x18
-#define IPMI_FORMAT_REV 0x00
-#define IPMI_FORMAT_REV1 0x01
-#define IPMI_SOFTWARE_ID 0x01
-#define IPMI_PLATFORM_VAL_ID 0x01
-#define IPMI_GENERATOR_ID(i,f) ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)
+//
+// Constants and Structure definitions for "Set SEL Time UTC Offset" command to follow here
+//
-#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE 0x6F
+#define IPMI_COMPLETE_SEL_RECORD 0xFF
-#define IPMI_OEM_SPECIFIC_DATA 0x02
-#define IPMI_SENSOR_SPECIFIC_DATA 0x03
+#define IPMI_SEL_SYSTEM_RECORD 0x02
+#define IPMI_SEL_OEM_TIME_STAMP_RECORD_START 0xC0
+#define IPMI_SEL_OEM_TIME_STAMP_RECORD_END 0xDF
+#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_START 0xE0
+#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_END 0xFF
+
+#define IPMI_SEL_EVENT_DIR(EventDirType) (EventDirType >> 7)
+#define IPMI_SEL_EVENT_DIR_ASSERTION_EVENT 0x00
+#define IPMI_SEL_EVENT_DIR_DEASSERTION_EVENT 0x01
+
+#define IPMI_SEL_EVENT_TYPE(EventDirType) (EventDirType & 0x7F)
+//
+// Event/Reading Type Code Ranges (Chapter 42)
+//
+#define IPMI_SEL_EVENT_TYPE_UNSPECIFIED 0x00
+#define IPMI_SEL_EVENT_TYPE_THRESHOLD 0x01
+#define IPMI_SEL_EVENT_TYPE_GENERIC_START 0x02
+#define IPMI_SEL_EVENT_TYPE_GENERIC_END 0x0C
+#define IPMI_SEL_EVENT_TYPE_SENSOR_SPECIFIC 0x6F
+#define IPMI_SEL_EVENT_TYPE_OEM_START 0x70
+#define IPMI_SEL_EVENT_TYPE_OEM_END 0x7F
+
+#define SOFTWARE_ID_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1)
+//
+// System Software IDs definitions (Section 5.5)
+//
+#define IPMI_SWID_BIOS_RANGE_START 0x00
+#define IPMI_SWID_BIOS_RANGE_END 0x0F
+#define IPMI_SWID_SMI_HANDLER_RANGE_START 0x10
+#define IPMI_SWID_SMI_HANDLER_RANGE_END 0x1F
+#define IPMI_SWID_SMS_RANGE_START 0x20
+#define IPMI_SWID_SMS_RANGE_END 0x2F
+#define IPMI_SWID_OEM_RANGE_START 0x30
+#define IPMI_SWID_OEM_RANGE_END 0x3F
+#define IPMI_SWID_REMOTE_CONSOLE_RANGE_START 0x40
+#define IPMI_SWID_REMOTE_CONSOLE_RANGE_END 0x46
+#define IPMI_SWID_TERMINAL_REMOTE_CONSOLE_ID 0x47
+
+#define SLAVE_ADDRESS_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1)
+#define LUN_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 8) & 0x03)
+#define CHANNEL_NUMBER_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 12) & 0x0F)
+
+#define IPMI_EVM_REVISION 0x04
+#define IPMI_BIOS_ID 0x18
+#define IPMI_FORMAT_REV 0x00
+#define IPMI_FORMAT_REV1 0x01
+#define IPMI_SOFTWARE_ID 0x01
+#define IPMI_PLATFORM_VAL_ID 0x01
+#define IPMI_GENERATOR_ID(i,f) ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)
+
+#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE 0x6F
+
+#define IPMI_OEM_SPECIFIC_DATA 0x02
+#define IPMI_SENSOR_SPECIFIC_DATA 0x03
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h b/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
index ad1a9aad707a..6ede54cbeaf3 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
@@ -10,14 +10,8 @@
See IPMI specification, Appendix G, Command Assignments
and Appendix H, Sub-function Assignments.
- Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IPMI_NET_FN_TRANSPORT_H_
@@ -65,7 +59,22 @@ typedef enum {
IpmiLanCommunityString,
IpmiLanReserved3,
IpmiLanDestinationType,
- IpmiLanDestinationAddress
+ IpmiLanDestinationAddress,
+ IpmiIpv4OrIpv6Support = 0x32,
+ IpmiIpv4OrIpv6AddressEnable,
+ IpmiIpv6HdrStatTrafficClass,
+ IpmiIpv6HdrStatHopLimit,
+ IpmiIpv6HdrFlowLabel,
+ IpmiIpv6Status,
+ IpmiIpv6StaticAddress,
+ IpmiIpv6DhcpStaticDuidLen,
+ IpmiIpv6DhcpStaticDuid,
+ IpmiIpv6DhcpAddress,
+ IpmiIpv6DhcpDynamicDuidLen,
+ IpmiIpv6DhcpDynamicDuid,
+ IpmiIpv6RouterConfig = 0x40,
+ IpmiIpv6StaticRouter1IpAddr,
+ IpmiIpv6DynamicRouterIpAddr = 0x4a
} IPMI_LAN_OPTION_TYPE;
//
@@ -94,23 +103,29 @@ typedef enum {
IpmiOem2
} IPMI_LAN_DEST_TYPE_DEST_TYPE;
-typedef struct {
- UINT8 NoAuth : 1;
- UINT8 MD2Auth : 1;
- UINT8 MD5Auth : 1;
- UINT8 Reserved1 : 1;
- UINT8 StraightPswd : 1;
- UINT8 OemType : 1;
- UINT8 Reserved2 : 2;
+typedef union {
+ struct {
+ UINT8 NoAuth : 1;
+ UINT8 MD2Auth : 1;
+ UINT8 MD5Auth : 1;
+ UINT8 Reserved1 : 1;
+ UINT8 StraightPswd : 1;
+ UINT8 OemType : 1;
+ UINT8 Reserved2 : 2;
+ } Bits;
+ UINT8 Uint8;
} IPMI_LAN_AUTH_TYPE;
typedef struct {
UINT8 IpAddress[4];
} IPMI_LAN_IP_ADDRESS;
-typedef struct {
- UINT8 AddressSrc : 4;
- UINT8 Reserved : 4;
+typedef union {
+ struct {
+ UINT8 AddressSrc : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
} IPMI_LAN_IP_ADDRESS_SRC;
typedef struct {
@@ -121,13 +136,27 @@ typedef struct {
UINT8 IpAddress[4];
} IPMI_LAN_SUBNET_MASK;
-typedef struct {
- UINT8 TimeToLive;
- UINT8 IpFlag : 3;
- UINT8 Reserved1 : 5;
- UINT8 Precedence : 3;
- UINT8 Reserved2 : 1;
- UINT8 ServiceType : 4;
+typedef union {
+ struct {
+ UINT8 IpFlag : 3;
+ UINT8 Reserved : 5;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_IPV4_HDR_PARAM_DATA_2;
+
+typedef union {
+ struct {
+ UINT8 Precedence : 3;
+ UINT8 Reserved : 1;
+ UINT8 ServiceType : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_IPV4_HDR_PARAM_DATA_3;
+
+typedef struct {
+ UINT8 TimeToLive;
+ IPMI_LAN_IPV4_HDR_PARAM_DATA_2 Data2;
+ IPMI_LAN_IPV4_HDR_PARAM_DATA_3 Data3;
} IPMI_LAN_IPV4_HDR_PARAM;
typedef struct {
@@ -135,10 +164,13 @@ typedef struct {
UINT8 RcmpPortLsb;
} IPMI_LAN_RCMP_PORT;
-typedef struct {
- UINT8 EnableBmcArpResponse : 1;
- UINT8 EnableBmcGratuitousArp : 1;
- UINT8 Reserved : 6;
+typedef union {
+ struct {
+ UINT8 EnableBmcArpResponse : 1;
+ UINT8 EnableBmcGratuitousArp : 1;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
} IPMI_LAN_BMC_GENERATED_ARP_CONTROL;
typedef struct {
@@ -149,23 +181,50 @@ typedef struct {
UINT8 Data[18];
} IPMI_LAN_COMMUNITY_STRING;
+typedef union {
+ struct {
+ UINT8 DestinationSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_SET_SELECTOR;
+
+typedef union {
+ struct {
+ UINT8 DestinationType : 3;
+ UINT8 Reserved : 4;
+ UINT8 AlertAcknowledged : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_DEST_TYPE_DESTINATION_TYPE;
+
typedef struct {
- UINT8 DestinationSelector : 4;
- UINT8 Reserved2 : 4;
- UINT8 DestinationType : 3;
- UINT8 Reserved1 : 4;
- UINT8 AlertAcknowledged : 1;
+ IPMI_LAN_SET_SELECTOR SetSelector;
+ IPMI_LAN_DEST_TYPE_DESTINATION_TYPE DestinationType;
} IPMI_LAN_DEST_TYPE;
-typedef struct {
- UINT8 DestinationSelector : 4;
- UINT8 Reserved1 : 4;
- UINT8 AlertingIpAddressSelector : 4;
- UINT8 AddressFormat : 4;
- UINT8 UseDefaultGateway : 1;
- UINT8 Reserved2 : 7;
- IPMI_LAN_IP_ADDRESS AlertingIpAddress;
- IPMI_LAN_MAC_ADDRESS AlertingMacAddress;
+typedef union {
+ struct {
+ UINT8 AlertingIpAddressSelector : 4;
+ UINT8 AddressFormat : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_ADDRESS_FORMAT;
+
+typedef union {
+ struct {
+ UINT8 UseDefaultGateway : 1;
+ UINT8 Reserved2 : 7;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_GATEWAY_SELECTOR;
+
+typedef struct {
+ IPMI_LAN_SET_SELECTOR SetSelector;
+ IPMI_LAN_ADDRESS_FORMAT AddressFormat;
+ IPMI_LAN_GATEWAY_SELECTOR GatewaySelector;
+ IPMI_LAN_IP_ADDRESS AlertingIpAddress;
+ IPMI_LAN_MAC_ADDRESS AlertingMacAddress;
} IPMI_LAN_DEST_ADDRESS;
typedef union {
@@ -183,6 +242,48 @@ typedef union {
IPMI_LAN_DEST_ADDRESS IpmiLanDestAddress;
} IPMI_LAN_OPTIONS;
+typedef union {
+ struct {
+ UINT8 AddressSourceType : 4;
+ UINT8 Reserved : 3;
+ UINT8 EnableStatus : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE;
+
+typedef struct {
+ UINT8 SetSelector;
+ IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE AddressSourceType;
+ UINT8 Ipv6Address[16];
+ UINT8 AddressPrefixLen;
+ UINT8 AddressStatus;
+} IPMI_LAN_IPV6_STATIC_ADDRESS;
+
+//
+// Set in progress parameter
+//
+typedef union {
+ struct {
+ UINT8 SetInProgress:2;
+ UINT8 Reserved:6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_LAN_SET_IN_PROGRESS;
+
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_LAN_CONFIG_CHANNEL_NUM;
+
+typedef struct {
+ IPMI_SET_LAN_CONFIG_CHANNEL_NUM ChannelNumber;
+ UINT8 ParameterSelector;
+ UINT8 ParameterData[0];
+} IPMI_SET_LAN_CONFIGURATION_PARAMETERS_COMMAND_REQUEST;
+
//
// Definitions for Get Lan Configuration Parameters command
//
@@ -191,6 +292,27 @@ typedef union {
//
// Constants and Structure definitions for "Get Lan Configuration Parameters" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 3;
+ UINT8 GetParameter : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_LAN_CONFIG_CHANNEL_NUM;
+
+typedef struct {
+ IPMI_GET_LAN_CONFIG_CHANNEL_NUM ChannelNumber;
+ UINT8 ParameterSelector;
+ UINT8 SetSelector;
+ UINT8 BlockSelector;
+} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ParameterRevision;
+ UINT8 ParameterData[0];
+} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_RESPONSE;
//
// Definitions for Suspend BMC ARPs command
@@ -226,67 +348,100 @@ typedef union {
//
// EMP OPTION DATA
//
-typedef struct {
- UINT8 NoAuthentication : 1;
- UINT8 MD2Authentication : 1;
- UINT8 MD5Authentication : 1;
- UINT8 Reserved1 : 1;
- UINT8 StraightPassword : 1;
- UINT8 OemProprietary : 1;
- UINT8 Reservd2 : 2;
+typedef union {
+ struct {
+ UINT8 NoAuthentication : 1;
+ UINT8 MD2Authentication : 1;
+ UINT8 MD5Authentication : 1;
+ UINT8 Reserved1 : 1;
+ UINT8 StraightPassword : 1;
+ UINT8 OemProprietary : 1;
+ UINT8 Reservd2 : 2;
+ } Bits;
+ UINT8 Uint8;
} IPMI_EMP_AUTH_TYPE;
-typedef struct {
- UINT8 EnableBasicMode : 1;
- UINT8 EnablePPPMode : 1;
- UINT8 EnableTerminalMode : 1;
- UINT8 Reserved1 : 2;
- UINT8 SnoopOsPPPNegotiation : 1;
- UINT8 Reserved2 : 1;
- UINT8 DirectConnect : 1;
+typedef union {
+ struct {
+ UINT8 EnableBasicMode : 1;
+ UINT8 EnablePPPMode : 1;
+ UINT8 EnableTerminalMode : 1;
+ UINT8 Reserved1 : 2;
+ UINT8 SnoopOsPPPNegotiation : 1;
+ UINT8 Reserved2 : 1;
+ UINT8 DirectConnect : 1;
+ } Bits;
+ UINT8 Uint8;
} IPMI_EMP_CONNECTION_TYPE;
-typedef struct {
- UINT8 InactivityTimeout : 4;
- UINT8 Reserved : 4;
+typedef union {
+ struct {
+ UINT8 InactivityTimeout : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
} IPMI_EMP_INACTIVITY_TIMEOUT;
-typedef struct {
- UINT8 IpmiCallback : 1;
- UINT8 CBCPCallback : 1;
- UINT8 Reserved1 : 6;
- UINT8 CbcpEnableNoCallback : 1;
- UINT8 CbcpEnablePreSpecifiedNumber : 1;
- UINT8 CbcpEnableUserSpecifiedNumber : 1;
- UINT8 CbcpEnableCallbackFromList : 1;
- UINT8 Reserved : 4;
- UINT8 CallbackDestination1;
- UINT8 CallbackDestination2;
- UINT8 CallbackDestination3;
+typedef union {
+ struct {
+ UINT8 IpmiCallback : 1;
+ UINT8 CBCPCallback : 1;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE;
+
+typedef union {
+ struct {
+ UINT8 CbcpEnableNoCallback : 1;
+ UINT8 CbcpEnablePreSpecifiedNumber : 1;
+ UINT8 CbcpEnableUserSpecifiedNumber : 1;
+ UINT8 CbcpEnableCallbackFromList : 1;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_CHANNEL_CALLBACK_CONTROL_CBCP;
+
+typedef struct {
+ IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE CallbackEnable;
+ IPMI_CHANNEL_CALLBACK_CONTROL_CBCP CBCPNegotiation;
+ UINT8 CallbackDestination1;
+ UINT8 CallbackDestination2;
+ UINT8 CallbackDestination3;
} IPMI_EMP_CHANNEL_CALLBACK_CONTROL;
-typedef struct {
- UINT8 CloseSessionOnDCDLoss : 1;
- UINT8 EnableSessionInactivityTimeout : 1;
- UINT8 Reserved : 6;
+typedef union {
+ struct {
+ UINT8 CloseSessionOnDCDLoss : 1;
+ UINT8 EnableSessionInactivityTimeout : 1;
+ UINT8 Reserved : 6;
+ } Bits;
+ UINT8 Uint8;
} IPMI_EMP_SESSION_TERMINATION;
-typedef struct {
- UINT8 Reserved1 : 5;
- UINT8 EnableDtrHangup : 1;
- UINT8 FlowControl : 2;
- UINT8 BitRate : 4;
- UINT8 Reserved2 : 4;
- UINT8 SaveSetting : 1;
- UINT8 SetComPort : 1;
- UINT8 Reserved3 : 6;
+typedef union {
+ struct {
+ UINT8 Reserved1 : 5;
+ UINT8 EnableDtrHangup : 1;
+ UINT8 FlowControl : 2;
+ UINT8 BitRate : 4;
+ UINT8 Reserved2 : 4;
+ UINT8 SaveSetting : 1;
+ UINT8 SetComPort : 1;
+ UINT8 Reserved3 : 6;
+ } Bits;
+ UINT8 Uint8;
+ UINT16 Uint16;
} IPMI_EMP_MESSAGING_COM_SETTING;
-typedef struct {
- UINT8 RingDurationInterval : 6;
- UINT8 Reserved1 : 2;
- UINT8 RingDeadTime : 4;
- UINT8 Reserved : 4;
+typedef union {
+ struct {
+ UINT8 RingDurationInterval : 6;
+ UINT8 Reserved1 : 2;
+ UINT8 RingDeadTime : 4;
+ UINT8 Reserved2 : 4;
+ } Bits;
+ UINT8 Uint8;
} IPMI_EMP_MODEM_RING_TIME;
typedef struct {
@@ -314,14 +469,20 @@ typedef struct {
UINT8 CommunityString[18];
} IPMI_EMP_COMMUNITY_STRING;
-typedef struct {
- UINT8 Reserved5 : 4;
- UINT8 DialStringSelector : 4;
+typedef union {
+ struct {
+ UINT8 Reserved : 4;
+ UINT8 DialStringSelector : 4;
+ } Bits;
+ UINT8 Uint8;
} IPMI_DIAL_PAGE_DESTINATION;
-typedef struct {
- UINT8 TapAccountSelector : 4;
- UINT8 Reserved : 4;
+typedef union {
+ struct {
+ UINT8 TapAccountSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
} IPMI_TAP_PAGE_DESTINATION;
typedef struct {
@@ -335,40 +496,78 @@ typedef union {
IPMI_PPP_ALERT_DESTINATION PppAlertDestination;
} IPMI_DEST_TYPE_SPECIFIC;
-typedef struct {
- UINT8 DestinationSelector : 4;
- UINT8 Reserved1 : 4;
- UINT8 DestinationType : 4;
- UINT8 Reserved2 : 3;
- UINT8 AlertAckRequired : 1;
- UINT8 AlertAckTimeoutSeconds;
- UINT8 NumRetriesCall : 3;
- UINT8 Reserved3 : 1;
- UINT8 NumRetryAlert : 3;
- UINT8 Reserved4 : 1;
- IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific;
+typedef union {
+ struct {
+ UINT8 DestinationSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_DESTINATION_SELECTOR;
+
+typedef union {
+ struct {
+ UINT8 DestinationType : 4;
+ UINT8 Reserved : 3;
+ UINT8 AlertAckRequired : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_DESTINATION_TYPE;
+
+typedef union {
+ struct {
+ UINT8 NumRetriesCall : 3;
+ UINT8 Reserved1 : 1;
+ UINT8 NumRetryAlert : 3;
+ UINT8 Reserved2 : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_RETRIES;
+
+typedef struct {
+ IPMI_EMP_DESTINATION_SELECTOR DestinationSelector;
+ IPMI_EMP_DESTINATION_TYPE DestinationType;
+ UINT8 AlertAckTimeoutSeconds;
+ IPMI_EMP_RETRIES Retries;
+ IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific;
} IPMI_EMP_DESTINATION_INFO;
+typedef union {
+ struct {
+ UINT8 Parity : 3;
+ UINT8 CharacterSize : 1;
+ UINT8 StopBit : 1;
+ UINT8 DtrHangup : 1;
+ UINT8 FlowControl : 2;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_DESTINATION_COM_SETTING_DATA_2;
+
+typedef union {
+ struct {
+ UINT8 BitRate : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_EMP_BIT_RATE;
+
typedef struct {
- UINT8 DestinationSelector : 4;
- UINT8 Reserved1 : 4;
- UINT8 Parity : 3;
- UINT8 CharacterSize : 1;
- UINT8 StopBit : 1;
- UINT8 DtrHangup : 1;
- UINT8 FlowControl : 2;
- UINT8 BitRate : 4;
- UINT8 Reserved2 : 4;
- UINT8 SaveSetting : 1;
- UINT8 SetComPort : 1;
- UINT8 Reserved3 : 6;
+ IPMI_EMP_DESTINATION_SELECTOR DestinationSelector;
+ IPMI_EMP_DESTINATION_COM_SETTING_DATA_2 Data2;
+ IPMI_EMP_BIT_RATE BitRate;
} IPMI_EMP_DESTINATION_COM_SETTING;
+typedef union {
+ struct {
+ UINT8 DialStringSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_DIAL_STRING_SELECTOR;
+
typedef struct {
- UINT8 DialStringSelector : 4;
- UINT8 Reserved1 : 4;
- UINT8 Reserved2;
- UINT8 DialString[48];
+ IPMI_DIAL_STRING_SELECTOR DestinationSelector;
+ UINT8 Reserved;
+ UINT8 DialString[48];
} IPMI_DESTINATION_DIAL_STRING;
typedef union {
@@ -376,16 +575,31 @@ typedef union {
UINT8 IpAddress[4];
} IPMI_PPP_IP_ADDRESS;
+typedef union {
+ struct {
+ UINT8 IpAddressSelector : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_DESTINATION_IP_ADDRESS_SELECTOR;
+
typedef struct {
- UINT8 IpAddressSelector : 4;
- UINT8 Reserved1 : 4;
- IPMI_PPP_IP_ADDRESS PppIpAddress;
+ IPMI_DESTINATION_IP_ADDRESS_SELECTOR DestinationSelector;
+ IPMI_PPP_IP_ADDRESS PppIpAddress;
} IPMI_DESTINATION_IP_ADDRESS;
+typedef union {
+ struct {
+ UINT8 TapServiceSelector : 4;
+ UINT8 TapDialStringSelector : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR;
+
+
typedef struct {
- UINT8 TapSelector;
- UINT8 TapServiceSelector : 4;
- UINT8 TapDialStringSelector : 4;
+ UINT8 TapSelector;
+ IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR TapDialStringServiceSelector;
} IPMI_DESTINATION_TAP_ACCOUNT;
typedef struct {
@@ -434,21 +648,63 @@ typedef union {
//
// Constants and Structure definitions for "Set Serial/Modem Mux" command to follow here
//
+
+//
+// Set Serial/Modem Mux command request return status
+//
+#define IPMI_MUX_SETTING_REQUEST_REJECTED 0x00
+#define IPMI_MUX_SETTING_REQUEST_ACCEPTED 0x01
+
+//
+// Definitions for serial multiplex settings
+//
+#define IPMI_MUX_SETTING_GET_MUX_SETTING 0x0
+#define IPMI_MUX_SETTING_REQUEST_MUX_TO_SYSTEM 0x1
+#define IPMI_MUX_SETTING_REQUEST_MUX_TO_BMC 0x2
+#define IPMI_MUX_SETTING_FORCE_MUX_TO_SYSTEM 0x3
+#define IPMI_MUX_SETTING_FORCE_MUX_TO_BMC 0x4
+#define IPMI_MUX_SETTING_BLOCK_REQUEST_MUX_TO_SYSTEM 0x5
+#define IPMI_MUX_SETTING_ALLOW_REQUEST_MUX_TO_SYSTEM 0x6
+#define IPMI_MUX_SETTING_BLOCK_REQUEST_MUX_TO_BMC 0x7
+#define IPMI_MUX_SETTING_ALLOW_REQUEST_MUX_TO_BMC 0x8
+
+typedef union {
+ struct {
+ UINT8 ChannelNo : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_MUX_CHANNEL_NUM;
+
+typedef union {
+ struct {
+ UINT8 MuxSetting : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_MUX_SETTING_REQUEST;
+
typedef struct {
- UINT8 ChannelNo : 4;
- UINT8 Reserved1 : 4;
- UINT8 MuxSetting : 4;
- UINT8 Reserved2 : 4;
+ IPMI_MUX_CHANNEL_NUM ChannelNumber;
+ IPMI_MUX_SETTING_REQUEST MuxSetting;
} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_REQUEST;
-typedef struct {
- UINT8 MuxSetToBmc : 1;
- UINT8 CommandStatus : 1;
- UINT8 MessagingSessionActive : 1;
- UINT8 AlertInProgress : 1;
- UINT8 Reserved2 : 2;
- UINT8 MuxToBmcAllowed : 1;
- UINT8 MuxToSystemBlocked : 1;
+typedef union {
+ struct {
+ UINT8 MuxSetToBmc : 1;
+ UINT8 CommandStatus : 1;
+ UINT8 MessagingSessionActive : 1;
+ UINT8 AlertInProgress : 1;
+ UINT8 Reserved : 2;
+ UINT8 MuxToBmcAllowed : 1;
+ UINT8 MuxToSystemBlocked : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_MUX_SETTING_PRESENT_STATE;
+
+typedef struct {
+ UINT8 CompletionCode;
+ IPMI_MUX_SETTING_PRESENT_STATE MuxSetting;
} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_RESPONSE;
//
@@ -544,6 +800,20 @@ typedef struct {
//
// Constants and Structure definitions for "SOL activating" command to follow here
//
+typedef union {
+ struct {
+ UINT8 SessionState : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SOL_SESSION_STATE;
+
+typedef struct {
+ IPMI_SOL_SESSION_STATE SessionState;
+ UINT8 PayloadInstance;
+ UINT8 FormatVersionMajor; // 1
+ UINT8 FormatVersionMinor; // 0
+} IPMI_SOL_ACTIVATING_REQUEST;
//
// Definitions for Set SOL Configuration Parameters command
@@ -555,6 +825,33 @@ typedef struct {
//
//
+// SOL Configuration Parameters selector
+//
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SET_IN_PROGRESS 0
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_ENABLE 1
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_AUTHENTICATION 2
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_CHARACTER_PARAM 3
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_RETRY 4
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_NV_BIT_RATE 5
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_VOLATILE_BIT_RATE 6
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_CHANNEL 7
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_PORT 8
+
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 Reserved : 4;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM;
+
+typedef struct {
+ IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber;
+ UINT8 ParameterSelector;
+ UINT8 ParameterData[0];
+} IPMI_SET_SOL_CONFIGURATION_PARAMETERS_REQUEST;
+
+//
// Definitions for Get SOL Configuration Parameters command
//
#define IPMI_TRANSPORT_GET_SOL_CONFIG_PARAM 0x22
@@ -562,5 +859,27 @@ typedef struct {
//
// Constants and Structure definitions for "Get SOL Configuration Parameters" command to follow here
//
+typedef union {
+ struct {
+ UINT8 ChannelNumber : 4;
+ UINT8 Reserved : 3;
+ UINT8 GetParameter : 1;
+ } Bits;
+ UINT8 Uint8;
+} IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM;
+
+typedef struct {
+ IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber;
+ UINT8 ParameterSelector;
+ UINT8 SetSelector;
+ UINT8 BlockSelector;
+} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_REQUEST;
+
+typedef struct {
+ UINT8 CompletionCode;
+ UINT8 ParameterRevision;
+ UINT8 ParameterData[0];
+} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_RESPONSE;
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h b/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
index 41045bd9765e..5c1f6ecfba0e 100644
--- a/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
+++ b/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
@@ -1,17 +1,11 @@
/** @file
Defives data structures per MultiProcessor Specification Ver 1.4.
-
- The MultiProcessor Specification defines an enhancement to the standard
+
+ The MultiProcessor Specification defines an enhancement to the standard
to which PC manufacturers design DOS-compatible systems.
-Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h b/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
index 2b361ed390a5..8de0cbf61283 100644
--- a/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
+++ b/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
@@ -2,13 +2,7 @@
ACPI Low Power Idle Table (LPIT) definitions
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- ACPI Low Power Idle Table (LPIT) Revision 001, dated July 2014
diff --git a/MdePkg/Include/IndustryStandard/Mbr.h b/MdePkg/Include/IndustryStandard/Mbr.h
index 302e44d77301..2d8c1f1e198f 100644
--- a/MdePkg/Include/IndustryStandard/Mbr.h
+++ b/MdePkg/Include/IndustryStandard/Mbr.h
@@ -1,14 +1,8 @@
/** @file
Legacy Master Boot Record Format Definition.
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
index d855d9b271d7..408971c019b1 100644
--- a/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
+++ b/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
@@ -1,16 +1,10 @@
/** @file
- ACPI memory mapped configuration space access table definition, defined at
+ ACPI memory mapped configuration space access table definition, defined at
in the PCI Firmware Specification, version 3.0.
Specification is available at http://www.pcisig.com.
-
- Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
@@ -35,7 +29,7 @@ typedef struct {
} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
///
-/// MCFG Table header definition. The rest of the table
+/// MCFG Table header definition. The rest of the table
/// must be defined in a platform specific manner.
///
typedef struct {
diff --git a/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h b/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
index 415c134779ae..3d5aaabf2764 100644
--- a/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
+++ b/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
@@ -1,16 +1,10 @@
/** @file
- Support for Microsoft Secure MOR implementation, defined at
+ Support for Microsoft Secure MOR implementation, defined at
Microsoft Secure MOR implementation.
https://msdn.microsoft.com/en-us/library/windows/hardware/mt270973(v=vs.85).aspx
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/IndustryStandard/Nvme.h
index 5914b58cfdd4..1c5d4980edbf 100644
--- a/MdePkg/Include/IndustryStandard/Nvme.h
+++ b/MdePkg/Include/IndustryStandard/Nvme.h
@@ -2,13 +2,8 @@
Definitions based on NVMe spec. version 1.1.
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
NVMe Specification 1.1
@@ -86,6 +81,8 @@ typedef struct {
UINT8 Iocqes:4; // I/O Completion Queue Entry Size
UINT8 Rsvd2;
} NVME_CC;
+#define NVME_CC_SHN_NORMAL_SHUTDOWN 1
+#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2
//
// 3.1.6 Offset 1Ch: CSTS - Controller Status
@@ -97,7 +94,8 @@ typedef struct {
UINT32 Nssro:1; // NVM Subsystem Reset Occurred
UINT32 Rsvd1:27;
} NVME_CSTS;
-
+#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
+#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
//
// 3.1.8 Offset 24h: AQA - Admin Queue Attributes
//
@@ -311,11 +309,11 @@ typedef struct {
UINT32 Exlat; /* Exit Latency */
UINT8 Rrt:5; /* Relative Read Throughput */
UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT8 Rrl:5; /* Relative Read Leatency */
+ UINT8 Rrl:5; /* Relative Read Latency */
UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 Rwt:5; /* Relative Write Throughput */
UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */
- UINT8 Rwl:5; /* Relative Write Leatency */
+ UINT8 Rwl:5; /* Relative Write Latency */
UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
} NVME_PSDESCRIPTOR;
@@ -331,7 +329,7 @@ typedef struct {
UINT16 Ssvid; /* PCI sub-system vendor ID */
UINT8 Sn[20]; /* Product serial number */
- UINT8 Mn[40]; /* Proeduct model number */
+ UINT8 Mn[40]; /* Product model number */
UINT8 Fr[8]; /* Firmware Revision */
UINT8 Rab; /* Recommended Arbitration Burst */
UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
@@ -659,7 +657,7 @@ typedef union {
//
typedef struct {
//
- // CDW 0, Common to all comnmands
+ // CDW 0, Common to all commands
//
UINT8 Opc; // Opcode
UINT8 Fuse:2; // Fused Operation
@@ -871,7 +869,7 @@ typedef struct {
//
UINT8 AvailableSpareThreshold;
//
- // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
+ // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
//
UINT8 PercentageUsed;
UINT8 Reserved1[26];
diff --git a/MdePkg/Include/IndustryStandard/Pal.h b/MdePkg/Include/IndustryStandard/Pal.h
deleted file mode 100644
index 5dc26a2f7b10..000000000000
--- a/MdePkg/Include/IndustryStandard/Pal.h
+++ /dev/null
@@ -1,3302 +0,0 @@
-/** @file
- Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.
-
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __PAL_API_H__
-#define __PAL_API_H__
-
-#define PAL_SUCCESS 0x0
-
-///
-/// CacheType of PAL_CACHE_FLUSH.
-///
-#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1
-#define PAL_CACHE_FLUSH_DATA_ALL 2
-#define PAL_CACHE_FLUSH_ALL 3
-#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4
-
-
-///
-/// Bitmask of Opearation of PAL_CACHE_FLUSH.
-///
-#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0
-#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0
-#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1
-#define PAL_CACHE_FLUSH_NO_INTERRUPT 0
-
-/**
- PAL Procedure - PAL_CACHE_FLUSH.
-
- Flush the instruction or data caches. It is required by Itanium processors.
- The PAL procedure supports the Static Registers calling
- convention. It could be called at virtual mode and physical
- mode.
-
- @param Index Index of PAL_CACHE_FLUSH within the
- list of PAL procedures.
- @param CacheType Unsigned 64-bit integer indicating
- which cache to flush.
- @param Operation Formatted bit vector indicating the
- operation of this call.
- @param ProgressIndicator Unsigned 64-bit integer specifying
- the starting position of the flush
- operation.
-
- @retval 2 Call completed without error, but a PMI
- was taken during the execution of this
- procedure.
- @retval 1 Call has not completed flushing due to
- a pending interrupt.
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error
-
- @return R9 Unsigned 64-bit integer specifying the vector
- number of the pending interrupt.
- @return R10 Unsigned 64-bit integer specifying the
- starting position of the flush operation.
- @return R11 Unsigned 64-bit integer specifying the vector
- number of the pending interrupt.
-
-**/
-#define PAL_CACHE_FLUSH 1
-
-
-///
-/// Attributes of PAL_CACHE_CONFIG_INFO1
-///
-#define PAL_CACHE_ATTR_WT 0
-#define PAL_CACHE_ATTR_WB 1
-
-///
-/// PAL_CACHE_CONFIG_INFO1.StoreHint
-///
-#define PAL_CACHE_STORE_TEMPORAL 0
-#define PAL_CACHE_STORE_NONE_TEMPORAL 3
-
-///
-/// PAL_CACHE_CONFIG_INFO1.StoreHint
-///
-#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0
-#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
-
-///
-/// PAL_CACHE_CONFIG_INFO1.StoreHint
-///
-#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0
-#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1
-#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3
-
-///
-/// Detail the characteristics of a given processor controlled
-/// cache in the cache hierarchy.
-///
-typedef struct {
- UINT64 IsUnified : 1;
- UINT64 Attributes : 2;
- UINT64 Associativity:8;
- UINT64 LineSize:8;
- UINT64 Stride:8;
- UINT64 StoreLatency:8;
- UINT64 StoreHint:8;
- UINT64 LoadHint:8;
-} PAL_CACHE_INFO_RETURN1;
-
-///
-/// Detail the characteristics of a given processor controlled
-/// cache in the cache hierarchy.
-///
-typedef struct {
- UINT64 CacheSize:32;
- UINT64 AliasBoundary:8;
- UINT64 TagLsBits:8;
- UINT64 TagMsBits:8;
-} PAL_CACHE_INFO_RETURN2;
-
-/**
- PAL Procedure - PAL_CACHE_INFO.
-
- Return detailed instruction or data cache information. It is
- required by Itanium processors. The PAL procedure supports the Static
- Registers calling convention. It could be called at virtual
- mode and physical mode.
-
- @param Index Index of PAL_CACHE_INFO within the list of
- PAL procedures.
- @param CacheLevel Unsigned 64-bit integer specifying the
- level in the cache hierarchy for which
- information is requested. This value must
- be between 0 and one less than the value
- returned in the cache_levels return value
- from PAL_CACHE_SUMMARY.
- @param CacheType Unsigned 64-bit integer with a value of 1
- for instruction cache and 2 for data or
- unified cache. All other values are
- reserved.
- @param Reserved Should be 0.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error
-
- @return R9 Detail the characteristics of a given
- processor controlled cache in the cache
- hierarchy. See PAL_CACHE_INFO_RETURN1.
- @return R10 Detail the characteristics of a given
- processor controlled cache in the cache
- hierarchy. See PAL_CACHE_INFO_RETURN2.
- @return R11 Reserved with 0.
-
-**/
-#define PAL_CACHE_INFO 2
-
-
-
-///
-/// Level of PAL_CACHE_INIT.
-///
-#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL
-
-///
-/// CacheType
-///
-#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1
-#define PAL_CACHE_INIT_TYPE_DATA 0x2
-#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3
-
-///
-/// Restrict of PAL_CACHE_INIT.
-///
-#define PAL_CACHE_INIT_NO_RESTRICT 0
-#define PAL_CACHE_INIT_RESTRICTED 1
-
-/**
- PAL Procedure - PAL_CACHE_INIT.
-
- Initialize the instruction or data caches. It is required by
- Itanium processors. The PAL procedure supports the Static Registers calling
- convention. It could be called at physical mode.
-
- @param Index Index of PAL_CACHE_INIT within the list of PAL
- procedures.
- @param Level Unsigned 64-bit integer containing the level of
- cache to initialize. If the cache level can be
- initialized independently, only that level will
- be initialized. Otherwise
- implementation-dependent side-effects will
- occur.
- @param CacheType Unsigned 64-bit integer with a value of 1 to
- initialize the instruction cache, 2 to
- initialize the data cache, or 3 to
- initialize both. All other values are
- reserved.
- @param Restrict Unsigned 64-bit integer with a value of 0 or
- 1. All other values are reserved. If
- restrict is 1 and initializing the specified
- level and cache_type of the cache would
- cause side-effects, PAL_CACHE_INIT will
- return -4 instead of initializing the cache.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -4 Call could not initialize the specified
- level and cache_type of the cache without
- side-effects and restrict was 1.
-
-**/
-#define PAL_CACHE_INIT 3
-
-
-///
-/// PAL_CACHE_PROTECTION.Method.
-///
-#define PAL_CACHE_PROTECTION_NONE_PROTECT 0
-#define PAL_CACHE_PROTECTION_ODD_PROTECT 1
-#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2
-#define PAL_CACHE_PROTECTION_ECC_PROTECT 3
-
-
-
-///
-/// PAL_CACHE_PROTECTION.TagOrData.
-///
-#define PAL_CACHE_PROTECTION_PROTECT_DATA 0
-#define PAL_CACHE_PROTECTION_PROTECT_TAG 1
-#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2
-#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3
-
-///
-/// 32-bit protection information structures.
-///
-typedef struct {
- UINT32 DataBits:8;
- UINT32 TagProtLsb:6;
- UINT32 TagProtMsb:6;
- UINT32 ProtBits:6;
- UINT32 Method:4;
- UINT32 TagOrData:2;
-} PAL_CACHE_PROTECTION;
-
-/**
- PAL Procedure - PAL_CACHE_PROT_INFO.
-
- Return instruction or data cache protection information. It is
- required by Itanium processors. The PAL procedure supports the Static
- Registers calling convention. It could be called at physical
- mode and Virtual mode.
-
- @param Index Index of PAL_CACHE_PROT_INFO within the list of
- PAL procedures.
- @param CacheLevel Unsigned 64-bit integer specifying the level
- in the cache hierarchy for which information
- is requested. This value must be between 0
- and one less than the value returned in the
- cache_levels return value from
- PAL_CACHE_SUMMARY.
- @param CacheType Unsigned 64-bit integer with a value of 1
- for instruction cache and 2 for data or
- unified cache. All other values are
- reserved.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Detail the characteristics of a given
- processor controlled cache in the cache
- hierarchy. See PAL_CACHE_PROTECTION[0..1].
- @return R10 Detail the characteristics of a given
- processor controlled cache in the cache
- hierarchy. See PAL_CACHE_PROTECTION[2..3].
- @return R11 Detail the characteristics of a given
- processor controlled cache in the cache
- hierarchy. See PAL_CACHE_PROTECTION[4..5].
-
-**/
-#define PAL_CACHE_PROT_INFO 38
-
-typedef struct {
- UINT64 ThreadId : 16; ///< The thread identifier of the logical
- ///< processor for which information is being
- ///< returned. This value will be unique on a per core basis.
- UINT64 Reserved1: 16;
- UINT64 CoreId: 16; ///< The core identifier of the logical processor
- ///< for which information is being returned.
- ///< This value will be unique on a per physical
- ///< processor package basis.
- UINT64 Reserved2: 16;
-} PAL_PCOC_N_CACHE_INFO1;
-
-
-typedef struct {
- UINT64 LogicalAddress : 16; ///< Logical address: geographical address
- ///< of the logical processor for which
- ///< information is being returned. This is
- ///< the same value that is returned by the
- ///< PAL_FIXED_ADDR procedure when it is
- ///< called on the logical processor.
- UINT64 Reserved1: 16;
- UINT64 Reserved2: 32;
-} PAL_PCOC_N_CACHE_INFO2;
-
-/**
- PAL Procedure - PAL_CACHE_SHARED_INFO.
-
- Returns information on which logical processors share caches.
- It is optional. The PAL procedure supports the Static
- Registers calling convention. It could be called at physical
- mode and Virtual mode.
-
- @param Index Index of PAL_CACHE_SHARED_INFO within the list
- of PAL procedures.
- @param CacheLevel Unsigned 64-bit integer specifying the
- level in the cache hierarchy for which
- information is requested. This value must
- be between 0 and one less than the value
- returned in the cache_levels return value
- from PAL_CACHE_SUMMARY.
- @param CacheType Unsigned 64-bit integer with a value of 1
- for instruction cache and 2 for data or
- unified cache. All other values are
- reserved.
- @param ProcNumber Unsigned 64-bit integer that specifies for
- which logical processor information is
- being requested. This input argument must
- be zero for the first call to this
- procedure and can be a maximum value of
- one less than the number of logical
- processors sharing this cache, which is
- returned by the num_shared return value.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned integer that returns the number of
- logical processors that share the processor
- cache level and type, for which information was
- requested.
- @return R10 The format of PAL_PCOC_N_CACHE_INFO1.
- @return R11 The format of PAL_PCOC_N_CACHE_INFO2.
-
-**/
-#define PAL_CACHE_SHARED_INFO 43
-
-
-/**
- PAL Procedure - PAL_CACHE_SUMMARY.
-
- Return a summary of the cache hierarchy. It is required by
- Itanium processors. The PAL procedure supports the Static Registers calling
- convention. It could be called at physical mode and Virtual
- mode.
-
- @param Index Index of PAL_CACHE_SUMMARY within the list of
- PAL procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 CacheLevels Unsigned 64-bit integer denoting the
- number of levels of cache
- implemented by the processor.
- Strictly, this is the number of
- levels for which the cache
- controller is integrated into the
- processor (the cache SRAMs may be
- external to the processor).
- @return R10 UniqueCaches Unsigned 64-bit integer denoting the
- number of unique caches implemented
- by the processor. This has a maximum
- of 2*cache_levels, but may be less
- if any of the levels in the cache
- hierarchy are unified caches or do
- not have both instruction and data
- caches.
-
-**/
-#define PAL_CACHE_SUMMARY 4
-
-
-//
-// Virtual Memory Attributes implemented by processor.
-//
-#define PAL_MEMORY_ATTR_WB 0
-#define PAL_MEMORY_ATTR_WC 6
-#define PAL_MEMORY_ATTR_UC 4
-#define PAL_MEMORY_ATTR_UCE 5
-#define PAL_MEMORY_ATTR_NATPAGE 7
-
-/**
- PAL Procedure - PAL_MEM_ATTRIB.
-
- Return a list of supported memory attributes.. It is required
- by Itanium processors. The PAL procedure supports the Static Registers calling
- convention. It could be called at physical mode and Virtual
- mode.
-
- @param Index Index of PAL_MEM_ATTRIB within the list of PAL
- procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Attributes 8-bit vector of memory attributes
- implemented by processor. See Virtual
- Memory Attributes above.
-
-**/
-
-#define PAL_MEM_ATTRIB 5
-
-/**
- PAL Procedure - PAL_PREFETCH_VISIBILITY.
-
- Used in architected sequence to transition pages from a
- cacheable, speculative attribute to an uncacheable attribute.
- It is required by Itanium processors. The PAL procedure supports the Static
- Registers calling convention. It could be called at physical
- mode and Virtual mode.
-
- @param Index Index of PAL_PREFETCH_VISIBILITY within the list
- of PAL procedures.
- @param TransitionType Unsigned integer specifying the type
- of memory attribute transition that is
- being performed.
-
- @retval 1 Call completed without error; this
- call is not necessary on remote
- processors.
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_PREFETCH_VISIBILITY 41
-
-/**
- PAL Procedure - PAL_PTCE_INFO.
-
- Return information needed for ptc.e instruction to purge
- entire TC. It is required by Itanium processors. The PAL procedure supports
- the Static Registers calling convention. It could be called at
- physical mode and Virtual mode.
-
- @param Index Index of PAL_PTCE_INFO within the list
- of PAL procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned 64-bit integer denoting the beginning
- address to be used by the first PTCE instruction
- in the purge loop.
- @return R10 Two unsigned 32-bit integers denoting the loop
- counts of the outer (loop 1) and inner (loop 2)
- purge loops. count1 (loop 1) is contained in bits
- 63:32 of the parameter, and count2 (loop 2) is
- contained in bits 31:0 of the parameter.
- @return R11 Two unsigned 32-bit integers denoting the loop
- strides of the outer (loop 1) and inner (loop 2)
- purge loops. stride1 (loop 1) is contained in bits
- 63:32 of the parameter, and stride2 (loop 2) is
- contained in bits 31:0 of the parameter.
-
-**/
-#define PAL_PTCE_INFO 6
-
-typedef struct {
- UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting the number
- ///< of hash sets for the specified level
- ///< (1=fully associative)
- UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting the
- ///< associativity of the specified level
- ///< (1=direct).
- UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting the
- ///< number of entries in the specified TC.
- UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the
- ///< specified level is optimized for
- ///< the region's preferred page size
- ///< (1=optimized) tc_pages indicates
- ///< which page sizes are usable by
- ///< this translation cache.
- UINT64 TcIsUnified:1; ///< Flag denoting whether the specified TC is
- ///< unified (1=unified).
- UINT64 EntriesReduction:1; ///< Flag denoting whether installed
- ///< translation registers will reduce
- ///< the number of entries within the
- ///< specified TC.
-} PAL_TC_INFO;
-
-/**
- PAL Procedure - PAL_VM_INFO.
-
- Return detailed information about virtual memory features
- supported in the processor. It is required by Itanium processors. The PAL
- procedure supports the Static Registers calling convention. It
- could be called at physical mode and Virtual mode.
-
- @param Index Index of PAL_VM_INFO within the list
- of PAL procedures.
- @param TcLevel Unsigned 64-bit integer specifying the level
- in the TLB hierarchy for which information is
- required. This value must be between 0 and one
- less than the value returned in the
- vm_info_1.num_tc_levels return value from
- PAL_VM_SUMMARY.
- @param TcType Unsigned 64-bit integer with a value of 1 for
- instruction translation cache and 2 for data
- or unified translation cache. All other values
- are reserved.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 8-byte formatted value returning information
- about the specified TC. See PAL_TC_INFO above.
- @return R10 64-bit vector containing a bit for each page
- size supported in the specified TC, where bit
- position n indicates a page size of 2**n.
-
-**/
-#define PAL_VM_INFO 7
-
-
-/**
- PAL Procedure - PAL_VM_PAGE_SIZE.
-
- Return virtual memory TC and hardware walker page sizes
- supported in the processor. It is required by Itanium processors. The PAL
- procedure supports the Static Registers calling convention. It
- could be called at physical mode and Virtual mode.
-
- @param Index Index of PAL_VM_PAGE_SIZE within the list
- of PAL procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 64-bit vector containing a bit for each
- architected page size that is supported for
- TLB insertions and region registers.
- @return R10 64-bit vector containing a bit for each
- architected page size supported for TLB purge
- operations.
-
-**/
-#define PAL_VM_PAGE_SIZE 34
-
-typedef struct {
- UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether a hardware
- ///< TLB walker is implemented (1 = walker
- ///< present).
- UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer
- ///< denoting the number of bits of
- ///< physical address implemented.
- UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoting the number
- ///< of bits mplemented in the PKR.key field.
- UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoting the
- ///< maximum PKR index (number of PKRs-1).
- UINT64 HashTagId:8; ///< Unsigned 8-bit integer which uniquely
- ///< identifies the processor hash and tag
- ///< algorithm.
- UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoting the
- ///< maximum data translation register index
- ///< (number of dtr entries - 1).
- UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoting the
- ///< maximum instruction translation register
- ///< index (number of itr entries - 1).
- UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoting the
- ///< number of unique TCs implemented.
- ///< This is a maximum of
- ///< 2*num_tc_levels.
- UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoting the
- ///< number of TC levels.
-} PAL_VM_INFO1;
-
-typedef struct {
- UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting
- ///< is the total number of virtual
- ///< address bits - 1.
- UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting the number
- ///< of bits implemented in the RR.rid field.
- UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting the
- ///< maximum number of concurrent outstanding
- ///< TLB purges allowed by the processor. A
- ///< value of 0 indicates one outstanding
- ///< purge allowed. A value of 216-1
- ///< indicates no limit on outstanding
- ///< purges. All other values indicate the
- ///< actual number of concurrent outstanding
- ///< purges allowed.
- UINT64 Reserved:32;
-} PAL_VM_INFO2;
-
-/**
- PAL Procedure - PAL_VM_SUMMARY.
-
- Return summary information about virtual memory features
- supported in the processor. It is required by Itanium processors. The PAL
- procedure supports the Static Registers calling convention. It
- could be called at physical mode and Virtual mode.
-
- @param Index Index of PAL_VM_SUMMARY within the list
- of PAL procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 8-byte formatted value returning global virtual
- memory information. See PAL_VM_INFO1 above.
- @return R10 8-byte formatted value returning global virtual
- memory information. See PAL_VM_INFO2 above.
-
-**/
-#define PAL_VM_SUMMARY 8
-
-
-//
-// Bit mask of TR_valid flag.
-//
-#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0
-#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1
-#define PAL_TR_DIRTY_IS_VALID BIT2
-#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3
-
-
-/**
- PAL Procedure - PAL_VM_TR_READ.
-
- Read contents of a translation register. It is required by
- Itanium processors. The PAL procedure supports the Stacked Register calling
- convention. It could be called at physical mode.
-
- @param Index Index of PAL_VM_TR_READ within the list
- of PAL procedures.
- @param RegNumber Unsigned 64-bit number denoting which TR to
- read.
- @param TrType Unsigned 64-bit number denoting whether to
- read an ITR (0) or DTR (1). All other values
- are reserved.
- @param TrBuffer 64-bit pointer to the 32-byte memory buffer in
- which translation data is returned.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Formatted bit vector denoting which fields are
- valid. See TR_valid above.
-
-**/
-#define PAL_VM_TR_READ 261
-
-
-
-
-//
-// Bit Mask of Processor Bus Fesatures .
-//
-
-/**
-
- When 0, bus data errors are detected and single bit errors are
- corrected. When 1, no error detection or correction is done.
-
-**/
-#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63
-
-
-/**
-
- When 0, bus address errors are signalled on the bus. When 1,
- no bus errors are signalled on the bus. If Disable Bus Address
- Error Checking is 1, this bit is ignored.
-
-**/
-#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62
-
-
-
-
-/**
-
- When 0, bus errors are detected, single bit errors are
- corrected., and a CMCI or MCA is generated internally to the
- processor. When 1, no bus address errors are detected or
- corrected.
-
-**/
-#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61
-
-
-/**
-
- When 0, bus protocol errors (BINIT#) are signaled by the
- processor on the bus. When 1, bus protocol errors (BINIT#) are
- not signaled on the bus. If Disable Bus Initialization Event
- Checking is 1, this bit is ignored.
-
-**/
-#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60
-
-
-/**
-
- When 0, bus protocol errors (BINIT#) are detected and sampled
- and an MCA is generated internally to the processor. When 1,
- the processor will ignore bus protocol error conditions
- (BINIT#).
-
-**/
-#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59
-
-
-
-/**
-
- When 0, BERR# is signalled if a bus error is detected. When 1,
- bus errors are not signalled on the bus.
-
-**/
-#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58
-
-
-
-
-/**
-
- When 0, BERR# is signalled when internal processor requestor
- initiated bus errors are detected. When 1, internal requester
- bus errors are not signalled on the bus.
-
-**/
-#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57
-
-
-/**
-
- When 0, the processor takes an MCA if BERR# is asserted. When
- 1, the processor ignores the BERR# signal.
-
-**/
-#define PAL_BUS_DISABLE_ERROR_CHECK BIT56
-
-
-/**
-
- When 0, the processor asserts BINIT# if it detects a parity
- error on the signals which identify the transactions to which
- this is a response. When 1, the processor ignores parity on
- these signals.
-
-**/
-#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55
-
-
-/**
-
- When 0, the in-order transaction queue is limited only by the
- number of hardware entries. When 1, the processor's in-order
- transactions queue is limited to one entry.
-
-**/
-#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54
-
-/**
-
- Enable a bus cache line replacement transaction when a cache
- line in the exclusive state is replaced from the highest level
- processor cache and is not present in the lower level processor
- caches. When 0, no bus cache line replacement transaction will
- be seen on the bus. When 1, bus cache line replacement
- transactions will be seen on the bus when the above condition is
- detected.
-
-**/
-#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53
-
-
-/**
-
- Enable a bus cache line replacement transaction when a cache
- line in the shared or exclusive state is replaced from the
- highest level processor cache and is not present in the lower
- level processor caches.
- When 0, no bus cache line replacement transaction will be seen
- on the bus. When 1, bus cache line replacement transactions
- will be seen on the bus when the above condition is detected.
-
-**/
-#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52
-
-
-
-/**
-
- When 0, the data bus is configured at the 2x data transfer
- rate.When 1, the data bus is configured at the 1x data
- transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
- processor executes locked transactions atomically. When 1, the
- processor masks the bus lock signal and executes locked
- transactions as a non-atomic series of transactions.
-
-**/
-#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
-
-/**
-
- When 0, the processor will deassert bus request when finished
- with each transaction. When 1, the processor will continue to
- assert bus request after it has finished, if it was the last
- agent to own the bus and if there are no other pending
- requests.
-
-**/
-#define PAL_BUS_REQUEST_BUS_PARKING BIT29
-
-
-/**
- PAL Procedure - PAL_BUS_GET_FEATURES.
-
- Return configurable processor bus interface features and their
- current settings. It is required by Itanium processors. The PAL procedure
- supports the Stacked Register calling convention. It could be
- called at physical mode.
-
- @param Index Index of PAL_BUS_GET_FEATURES within the list
- of PAL procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 64-bit vector of features implemented.
- (1=implemented, 0=not implemented)
- @return R10 64-bit vector of current feature settings.
- @return R11 64-bit vector of features controllable by
- software. (1=controllable, 0= not controllable)
-
-**/
-#define PAL_BUS_GET_FEATURES 9
-
-/**
- PAL Procedure - PAL_BUS_SET_FEATURES.
-
- Enable or disable configurable features in processor bus
- interface. It is required by Itanium processors. The PAL procedure
- supports the Static Registers calling convention. It could be
- called at physical mode.
-
- @param Index Index of PAL_BUS_SET_FEATURES within the list
- of PAL procedures.
- @param FeatureSelect 64-bit vector denoting desired state of
- each feature (1=select, 0=non-select).
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_BUS_SET_FEATURES 10
-
-
-/**
- PAL Procedure - PAL_DEBUG_INFO.
-
- Return the number of instruction and data breakpoint
- registers. It is required by Itanium processors. The
- PAL procedure supports the Static Registers calling
- convention. It could be called at physical mode and virtual
- mode.
-
- @param Index Index of PAL_DEBUG_INFO within the list of PAL
- procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned 64-bit integer denoting the number of
- pairs of instruction debug registers implemented
- by the processor.
- @return R10 Unsigned 64-bit integer denoting the number of
- pairs of data debug registers implemented by the
- processor.
-
-**/
-#define PAL_DEBUG_INFO 11
-
-/**
- PAL Procedure - PAL_FIXED_ADDR.
-
- Return the fixed component of a processor's directed address.
- It is required by Itanium processors. The PAL
- procedure supports the Static Registers calling convention. It
- could be called at physical mode and virtual mode.
-
- @param Index Index of PAL_FIXED_ADDR within the list of PAL
- procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Fixed geographical address of this processor.
-
-**/
-#define PAL_FIXED_ADDR 12
-
-/**
- PAL Procedure - PAL_FREQ_BASE.
-
- Return the frequency of the output clock for use by the
- platform, if generated by the processor. It is optinal. The
- PAL procedure supports the Static Registers calling
- convention. It could be called at physical mode and virtual
- mode.
-
- @param Index Index of PAL_FREQ_BASE within the list of PAL
- procedures.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Base frequency of the platform if generated by the
- processor chip.
-
-**/
-#define PAL_FREQ_BASE 13
-
-
-/**
- PAL Procedure - PAL_FREQ_RATIOS.
-
- Return ratio of processor, bus, and interval time counter to
- processor input clock or output clock for platform use, if
- generated by the processor. It is required by Itanium processors. The PAL
- procedure supports the Static Registers calling convention. It
- could be called at physical mode and virtual mode.
-
- @param Index Index of PAL_FREQ_RATIOS within the list of PAL
- procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Ratio of the processor frequency to the input
- clock of the processor, if the platform clock is
- generated externally or to the output clock to the
- platform, if the platform clock is generated by
- the processor.
- @return R10 Ratio of the bus frequency to the input clock of
- the processor, if the platform clock is generated
- externally or to the output clock to the platform,
- if the platform clock is generated by the
- processor.
- @return R11 Ratio of the interval timer counter rate to input
- clock of the processor, if the platform clock is
- generated externally or to the output clock to the
- platform, if the platform clock is generated by
- the processor.
-
-**/
-#define PAL_FREQ_RATIOS 14
-
-typedef struct {
- UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical
- ///< processors on this physical
- ///< processor package that are
- ///< enabled.
- UINT64 ThreadsPerCore:8; ///< Number of threads per core.
- UINT64 Reserved1:8;
- UINT64 CoresPerProcessor:8; ///< Total number of cores on this
- ///< physical processor package.
- UINT64 Reserved2:8;
- UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package
- ///< identifier which was
- ///< assigned at reset by the
- ///< platform or bus
- ///< controller. This value may
- ///< or may not be unique
- ///< across the entire platform
- ///< since it depends on the
- ///< platform vendor's policy.
- UINT64 Reserved3:8;
-} PAL_LOGICAL_PROCESSPR_OVERVIEW;
-
-typedef struct {
- UINT64 ThreadId:16; ///< The thread identifier of the logical
- ///< processor for which information is being
- ///< returned. This value will be unique on a per
- ///< core basis.
- UINT64 Reserved1:16;
- UINT64 CoreId:16; ///< The core identifier of the logical processor
- ///< for which information is being returned.
- ///< This value will be unique on a per physical
- ///< processor package basis.
- UINT64 Reserved2:16;
-} PAL_LOGICAL_PROCESSORN_INFO1;
-
-typedef struct {
- UINT64 LogicalAddress:16; ///< Geographical address of the logical
- ///< processor for which information is being
- ///< returned. This is the same value that is
- ///< returned by the PAL_FIXED_ADDR procedure
- ///< when it is called on the logical processor.
- UINT64 Reserved:48;
-} PAL_LOGICAL_PROCESSORN_INFO2;
-
-/**
- PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
-
- Return information on which logical processors map to a
- physical processor die. It is optinal. The PAL procedure
- supports the Static Registers calling convention. It could be
- called at physical mode and virtual mode.
-
- @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
- procedures.
- @param ProcessorNumber Signed 64-bit integer that specifies
- for which logical processor
- information is being requested. When
- this input argument is -1, information
- is returned about the logical
- processor on which the procedure call
- is made. This input argument must be
- in the range of 1 up to one less than
- the number of logical processors
- returned by num_log in the
- log_overview return value.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
- @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.
- @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.
-
-**/
-#define PAL_LOGICAL_TO_PHYSICAL 42
-
-typedef struct {
- UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number defining the
- ///< number of generic PMC/PMD pairs.
- UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in the range
- ///< 0:60 defining the number of
- ///< implemented counter bits.
- UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number defining the
- ///< event type for counting processor cycles.
- UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit
- ///< number defining the
- ///< event type for retired
- ///< instruction bundles.
- UINT64 Reserved:32;
-} PAL_PERFORMANCE_INFO;
-
-/**
- PAL Procedure - PAL_PERF_MON_INFO.
-
- Return the number and type of performance monitors. It is
- required by Itanium processors. The PAL procedure supports the Static
- Registers calling convention. It could be called at physical
- mode and virtual mode.
-
- @param Index Index of PAL_PERF_MON_INFO within the list of
- PAL procedures.
- @param PerformanceBuffer An address to an 8-byte aligned
- 128-byte memory buffer.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Information about the performance monitors
- implemented. See PAL_PERFORMANCE_INFO;
-
-**/
-#define PAL_PERF_MON_INFO 15
-
-#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0
-#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1
-
-/**
- PAL Procedure - PAL_PLATFORM_ADDR.
-
- Specify processor interrupt block address and I/O port space
- address. It is required by Itanium processors. The PAL procedure supports the
- Static Registers calling convention. It could be called at
- physical mode and virtual mode.
-
- @param Index Index of PAL_PLATFORM_ADDR within the list of
- PAL procedures.
- @param Type Unsigned 64-bit integer specifying the type of
- block. 0 indicates that the processor interrupt
- block pointer should be initialized. 1 indicates
- that the processor I/O block pointer should be
- initialized.
- @param Address Unsigned 64-bit integer specifying the address
- to which the processor I/O block or interrupt
- block shall be set. The address must specify
- an implemented physical address on the
- processor model, bit 63 is ignored.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure.
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_PLATFORM_ADDR 16
-
-typedef struct {
- UINT64 Reserved1:36;
- UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplemented
- ///< instruction address reported as
- ///< fault. Denotes how the processor
- ///< reports the detection of
- ///< unimplemented instruction
- ///< addresses. When 1, the processor
- ///< reports an Unimplemented
- ///< Instruction Address fault on the
- ///< unimplemented address; when 0, it
- ///< reports an Unimplemented
- ///< Instruction Address trap on the
- ///< previous instruction in program
- ///< order. This feature may only be
- ///< interrogated by
- ///< PAL_PROC_GET_FEATURES. It may not
- ///< be enabled or disabled by
- ///< PAL_PROC_SET_FEATURES. The
- ///< corresponding argument is ignored.
-
- UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins
- ///< present. Denotes the absence of INIT,
- ///< PMI, LINT0 and LINT1 pins on the
- ///< processor. When 1, the pins are absent.
- ///< When 0, the pins are present. This
- ///< feature may only be interrogated by
- ///< PAL_PROC_GET_FEATURES. It may not be
- ///< enabled or disabled by
- ///< PAL_PROC_SET_FEATURES. The corresponding
- ///< argument is ignored.
-
- UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple
- ///< implementation of
- ///< unimplemented instruction
- ///< addresses. Denotes how an
- ///< unimplemented instruction
- ///< address is recorded in IIP
- ///< on an Unimplemented
- ///< Instruction Address trap or
- ///< fault. When 1, the full
- ///< unimplemented address is
- ///< recorded in IIP; when 0, the
- ///< address is sign extended
- ///< (virtual addresses) or zero
- ///< extended (physical
- ///< addresses). This feature may
- ///< only be interrogated by
- ///< PAL_PROC_GET_FEATURES. It
- ///< may not be enabled or
- ///< disabled by
- ///< PAL_PROC_SET_FEATURES. The
- ///< corresponding argument is
- ///< ignored.
-
- UINT64 NoVariablePState:1; ///< Bit39, No Variable P-state
- ///< performance: A value of 1, indicates
- ///< that a processor implements
- ///< techniques to optimize performance
- ///< for the given P-state power budget
- ///< by dynamically varying the
- ///< frequency, such that maximum
- ///< performance is achieved for the
- ///< power budget. A value of 0,
- ///< indicates that P-states have no
- ///< frequency variation or very small
- ///< frequency variations for their given
- ///< power budget. This feature may only
- ///< be interrogated by
- ///< PAL_PROC_GET_FEATURES. it may not be
- ///< enabled or disabled by
- ///< PAL_PROC_SET_FEATURES. The
- ///< corresponding argument is ignored.
-
- UINT64 NoVM:1; ///< Bit40, No Virtual Machine features implemented.
- ///< Denotes whether PSR.vm is implemented. This
- ///< feature may only be interrogated by
- ///< PAL_PROC_GET_FEATURES. It may not be enabled or
- ///< disabled by PAL_PROC_SET_FEATURES. The
- ///< corresponding argument is ignored.
-
- UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, and XFS
- ///< implemented. Denotes whether XIP, XPSR,
- ///< and XFS are implemented for machine
- ///< check recovery. This feature may only be
- ///< interrogated by PAL_PROC_GET_FEATURES.
- ///< It may not be enabled or disabled by
- ///< PAL_PROC_SET_FEATURES. The corresponding
- ///< argument is ignored.
-
- UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through XR3 implemented.
- ///< Denotes whether XR1 XR3 are
- ///< implemented for machine check
- ///< recovery. This feature may only be
- ///< interrogated by PAL_PROC_GET_FEATURES.
- ///< It may not be enabled or disabled by
- ///< PAL_PROC_SET_FEATURES. The
- ///< corresponding argument is ignored.
-
- UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic
- ///< Predicate Prediction. When
- ///< 0, the processor may predict
- ///< predicate results and
- ///< execute speculatively, but
- ///< may not commit results until
- ///< the actual predicates are
- ///< known. When 1, the processor
- ///< shall not execute predicated
- ///< instructions until the
- ///< actual predicates are known.
-
- UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Spontaneous
- ///< Deferral. When 1, the
- ///< processor may optionally
- ///< defer speculative loads
- ///< that do not encounter any
- ///< exception conditions, but
- ///< that trigger other
- ///< implementation-dependent
- ///< conditions (e.g., cache
- ///< miss). When 0, spontaneous
- ///< deferral is disabled.
-
- UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic
- ///< Data Cache Prefetch.
- ///< When 0, the processor
- ///< may prefetch into the
- ///< caches any data which
- ///< has not been accessed
- ///< by instruction
- ///< execution, but which
- ///< is likely to be
- ///< accessed. When 1, no
- ///< data may be fetched
- ///< until it is needed for
- ///< instruction execution
- ///< or is fetched by an
- ///< lfetch instruction.
-
- UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable
- ///< DynamicInstruction Cache
- ///< Prefetch. When 0, the
- ///< processor may prefetch
- ///< into the caches any
- ///< instruction which has
- ///< not been executed, but
- ///< whose execution is
- ///< likely. When 1,
- ///< instructions may not be
- ///< fetched until needed or
- ///< hinted for execution.
- ///< (Prefetch for a hinted
- ///< branch is allowed even
- ///< when dynamic instruction
- ///< cache prefetch is
- ///< disabled.)
-
- UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynamic branch
- ///< prediction. When 0, the
- ///< processor may predict branch
- ///< targets and speculatively
- ///< execute, but may not commit
- ///< results. When 1, the processor
- ///< must wait until branch targets
- ///< are known to execute.
- UINT64 Reserved2:4;
- UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL
- ///< P-state procedures (PAL_PSTATE_INFO,
- ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will
- ///< return with a status of -1
- ///< (Unimplemented procedure).
-
- UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling
- ///< on data-poisoning event
- ///< detection. When 0, a CMCI
- ///< will be signaled on error
- ///< detection. When 1, an MCA
- ///< will be signaled on error
- ///< detection. If this feature
- ///< is not supported, then the
- ///< corresponding argument is
- ///< ignored when calling
- ///< PAL_PROC_SET_FEATURES. Note
- ///< that the functionality of
- ///< this bit is independent of
- ///< the setting in bit 60
- ///< (Enable CMCI promotion), and
- ///< that the bit 60 setting does
- ///< not affect CMCI signaling
- ///< for data-poisoning related
- ///< events. Volume 2: Processor
- ///< Abstraction Layer 2:431
- ///< PAL_PROC_GET_FEATURES
-
- UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw
- ///< instruction. When 0, the vmsw instruction
- ///< causes a Virtualization fault when
- ///< executed at the most privileged level.
- ///< When 1, this bit will enable normal
- ///< operation of the vmsw instruction.
-
- UINT64 EnableEnvNotification:1; ///< Bit55, Enable external
- ///< notification when the processor
- ///< detects hardware errors caused
- ///< by environmental factors that
- ///< could cause loss of
- ///< deterministic behavior of the
- ///< processor. When 1, this bit will
- ///< enable external notification,
- ///< when 0 external notification is
- ///< not provided. The type of
- ///< external notification of these
- ///< errors is processor-dependent. A
- ///< loss of processor deterministic
- ///< behavior is considered to have
- ///< occurred if these
- ///< environmentally induced errors
- ///< cause the processor to deviate
- ///< from its normal execution and
- ///< eventually causes different
- ///< behavior which can be observed
- ///< at the processor bus pins.
- ///< Processor errors that do not
- ///< have this effects (i.e.,
- ///< software induced machine checks)
- ///< may or may not be promoted
- ///< depending on the processor
- ///< implementation.
-
- UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on
- ///< internal processor time-out.
- ///< When 0, the processor may
- ///< generate a BINIT on an
- ///< internal processor time-out.
- ///< When 1, the processor will not
- ///< generate a BINIT on an
- ///< internal processor time-out.
- ///< The event is silently ignored.
-
- UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management
- ///< (DPM). When 0, the hardware may reduce
- ///< power consumption by removing the clock
- ///< input from idle functional units. When 1,
- ///< all functional units will receive clock
- ///< input, even when idle.
-
- UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0,
- ///< the processor uses normal coherency
- ///< requests and responses. When 1, the
- ///< processor answers all requests as if
- ///< the line were not present.
-
- UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the
- ///< processor performs cast outs on
- ///< cacheable pages and issues and responds
- ///< to coherency requests normally. When 1,
- ///< the processor performs a memory access
- ///< for each reference regardless of cache
- ///< contents and issues no coherence
- ///< requests and responds as if the line
- ///< were not present. Cache contents cannot
- ///< be relied upon when the cache is
- ///< disabled. WARNING: Semaphore
- ///< instructions may not be atomic or may
- ///< cause Unsupported Data Reference faults
- ///< if caches are disabled.
-
- UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When
- ///< 1, Corrected Machine Check
- ///< Interrupts (CMCI) are promoted to
- ///< MCAs. They are also further
- ///< promoted to BERR if bit 39, Enable
- ///< MCA promotion, is also set and
- ///< they are promoted to BINIT if bit
- ///< 38, Enable MCA to BINIT promotion,
- ///< is also set. This bit has no
- ///< effect if MCA signalling is
- ///< disabled (see
- ///< PAL_BUS_GET/SET_FEATURES)
-
- UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT
- ///< promotion. When 1, machine
- ///< check aborts (MCAs) are
- ///< promoted to the Bus
- ///< Initialization signal, and
- ///< the BINIT pin is assert on
- ///< each occurrence of an MCA.
- ///< Setting this bit has no
- ///< effect if BINIT signalling
- ///< is disabled. (See
- ///< PAL_BUS_GET/SET_FEATURES)
-
- UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When
- ///< 1, machine check aborts (MCAs) are
- ///< promoted to the Bus Error signal,
- ///< and the BERR pin is assert on each
- ///< occurrence of an MCA. Setting this
- ///< bit has no effect if BERR
- ///< signalling is disabled. (See
- ///< PAL_BUS_GET/SET_FEATURES)
-
- UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When
- ///< 1, the Bus Error (BERR) signal is
- ///< promoted to the Bus Initialization
- ///< (BINIT) signal, and the BINIT pin
- ///< is asserted on the occurrence of
- ///< each Bus Error. Setting this bit
- ///< has no effect if BINIT signalling
- ///< is disabled. (See
- ///< PAL_BUS_GET/SET_FEATURES)
-} PAL_PROCESSOR_FEATURES;
-
-/**
- PAL Procedure - PAL_PROC_GET_FEATURES.
-
- Return configurable processor features and their current
- setting. It is required by Itanium processors. The PAL procedure supports the
- Static Registers calling convention. It could be called at
- physical mode and virtual mode.
-
- @param Index Index of PAL_PROC_GET_FEATURES within the list of
- PAL procedures.
- @param Reserved Reserved parameter.
- @param FeatureSet Feature set information is being requested
- for.
-
- @retval 1 Call completed without error; The
- feature_set passed is not supported but a
- feature_set of a larger value is supported.
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -8 feature_set passed is beyond the maximum
- feature_set supported
-
- @return R9 64-bit vector of features implemented. See
- PAL_PROCESSOR_FEATURES.
- @return R10 64-bit vector of current feature settings. See
- PAL_PROCESSOR_FEATURES.
- @return R11 64-bit vector of features controllable by
- software.
-
-**/
-#define PAL_PROC_GET_FEATURES 17
-
-
-/**
- PAL Procedure - PAL_PROC_SET_FEATURES.
-
- Enable or disable configurable processor features. It is
- required by Itanium processors. The PAL procedure supports the Static
- Registers calling convention. It could be called at physical
- mode.
-
- @param Index Index of PAL_PROC_SET_FEATURES within the list of
- PAL procedures.
- @param FeatureSelect 64-bit vector denoting desired state of
- each feature (1=select, 0=non-select).
- @param FeatureSet Feature set to apply changes to. See
- PAL_PROC_GET_FEATURES for more information
- on feature sets.
-
- @retval 1 Call completed without error; The
- feature_set passed is not supported but a
- feature_set of a larger value is supported
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -8 feature_set passed is beyond the maximum
- feature_set supported
-
-**/
-#define PAL_PROC_SET_FEATURES 18
-
-
-//
-// Value of PAL_REGISTER_INFO.InfoRequest.
-//
-#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0
-#define PAL_APPLICATION_REGISTER_READABLE 1
-#define PAL_CONTROL_REGISTER_IMPLEMENTED 2
-#define PAL_CONTROL_REGISTER_READABLE 3
-
-
-/**
- PAL Procedure - PAL_REGISTER_INFO.
-
- Return AR and CR register information. It is required by Itanium processors.
- The PAL procedure supports the Static Registers calling
- convention. It could be called at physical mode and virtual
- mode.
-
- @param Index Index of PAL_REGISTER_INFO within the list of
- PAL procedures.
- @param InfoRequest Unsigned 64-bit integer denoting what
- register information is requested. See
- PAL_REGISTER_INFO.InfoRequest above.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 64-bit vector denoting information for registers
- 0-63. Bit 0 is register 0, bit 63 is register 63.
- @return R10 64-bit vector denoting information for registers
- 64-127. Bit 0 is register 64, bit 63 is register
- 127.
-
-**/
-#define PAL_REGISTER_INFO 39
-
-/**
- PAL Procedure - PAL_RSE_INFO.
-
- Return RSE information. It is required by Itanium processors. The PAL
- procedure supports the Static Registers calling convention. It
- could be called at physical mode and virtual mode.
-
- @param Index Index of PAL_RSE_INFO within the list of
- PAL procedures.
- @param InfoRequest Unsigned 64-bit integer denoting what
- register information is requested. See
- PAL_REGISTER_INFO.InfoRequest above.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Number of physical stacked general registers.
- @return R10 RSE hints supported by processor.
-
-**/
-#define PAL_RSE_INFO 19
-
-typedef struct {
- UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD)
- ///< number that provides identification
- ///< information about the PAL_B firmware.
- UINT64 Reserved1:8;
- UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicating the
- ///< vendor of the PAL code.
- UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD)
- ///< number that provides identification
- ///< information about the PAL_A firmware. In
- ///< the split PAL_A model, this return value
- ///< is the version number of the
- ///< processor-specific PAL_A. The generic
- ///< PAL_A version is not returned by this
- ///< procedure in the split PAL_A model.
- UINT64 Reserved2:16;
-} PAL_VERSION_INFO;
-
-/**
- PAL Procedure - PAL_VERSION.
-
- Return version of PAL code. It is required by Itanium processors. The PAL
- procedure supports the Static Registers calling convention. It
- could be called at physical mode and virtual mode.
-
- @param Index Index of PAL_VERSION within the list of
- PAL procedures.
- @param InfoRequest Unsigned 64-bit integer denoting what
- register information is requested. See
- PAL_REGISTER_INFO.InfoRequest above.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 8-byte formatted value returning the minimum PAL
- version needed for proper operation of the
- processor. See PAL_VERSION_INFO above.
- @return R10 8-byte formatted value returning the current PAL
- version running on the processor. See
- PAL_VERSION_INFO above.
-
-**/
-#define PAL_VERSION 20
-
-
-
-//
-// Vectors of PAL_MC_CLEAR_LOG.pending
-//
-#define PAL_MC_PENDING BIT0
-#define PAL_INIT_PENDING BIT1
-
-/**
- PAL Procedure - PAL_MC_CLEAR_LOG.
-
- Clear all error information from processor error logging
- registers. It is required by Itanium processors. The PAL procedure supports
- the Static Registers calling convention. It could be called at
- physical mode and virtual mode.
-
- @param Index Index of PAL_MC_CLEAR_LOG within the list of
- PAL procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 64-bit vector denoting whether an event is
- pending. See PAL_MC_CLEAR_LOG.pending above.
-
-**/
-#define PAL_MC_CLEAR_LOG 21
-
-/**
- PAL Procedure - PAL_MC_DRAIN.
-
- Ensure that all operations that could cause an MCA have
- completed. It is required by Itanium processors. The PAL procedure supports
- the Static Registers calling convention. It could be called at
- physical mode and virtual mode.
-
- @param Index Index of PAL_MC_DRAIN within the list of PAL
- procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_MC_DRAIN 22
-
-
-/**
- PAL Procedure - PAL_MC_DYNAMIC_STATE.
-
- Return Processor Dynamic State for logging by SAL. It is
- optional. The PAL procedure supports the Static Registers
- calling convention. It could be called at physical mode.
-
- @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL
- procedures.
- @param Offset Offset of the next 8 bytes of Dynamic Processor
- State to return. (multiple of 8).
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure.
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned 64-bit integer denoting bytes of Dynamic
- Processor State returned.
- @return R10 Next 8 bytes of Dynamic Processor State.
-
-**/
-#define PAL_MC_DYNAMIC_STATE 24
-
-
-
-//
-// Values of PAL_MC_ERROR_INFO.InfoIndex.
-//
-#define PAL_PROCESSOR_ERROR_MAP 0
-#define PAL_PROCESSOR_STATE_PARAM 1
-#define PAL_STRUCTURE_SPECIFIC_ERROR 2
-
-typedef struct {
- UINT64 CoreId:4; ///< Bit3:0, Processor core ID (default is 0 for
- ///< processors with a single core)
-
- UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (default is 0 for
- ///< processors that execute a single thread)
-
- UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is
- ///< available for 1st, 2nd, 3rd, and 4th
- ///< level instruction caches.
-
- UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is
- ///< available for 1st, 2nd, 3rd, and 4th
- ///< level data/unified caches.
-
- UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is available
- ///< for 1st, 2nd, 3rd, and 4th level
- ///< instruction TLB.
-
- UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is available
- ///< for 1st, 2nd, 3rd, and 4th level
- ///< data/unified TLB
-
- UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is
- ///< available for the 1st, 2nd, 3rd,
- ///< and 4th level processor bus
- ///< hierarchy.
- UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is
- ///< available on register file
- ///< structures.
- UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is
- ///< available on micro-architectural
- ///< structures.
- UINT64 Reserved:16;
-} PAL_MC_ERROR_INFO_LEVEL_INDEX;
-
-//
-// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
-//
-#define PAL_ERR_INFO_BY_LEVEL_INDEX 0
-#define PAL_ERR_INFO_TARGET_ADDRESS 1
-#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2
-#define PAL_ERR_INFO_REPONSER_INDENTIFIER 3
-#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4
-
-typedef struct {
- UINT64 Operation:4; ///< Bit3:0, Type of cache operation that caused
- ///< the machine check: 0 - unknown or internal
- ///< error 1 - load 2 - store 3 - instruction
- ///< fetch or instruction prefetch 4 - data
- ///< prefetch (both hardware and software) 5 -
- ///< snoop (coherency check) 6 - cast out
- ///< (explicit or implicit write-back of a cache
- ///< line) 7 - move in (cache line fill)
-
- UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where the
- ///< error occurred. A value of 0
- ///< indicates the first level of cache.
- UINT64 Reserved1:2;
- UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the data part of the cache line.
- UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the tag part of the cache line.
- UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the data cache
-
- UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the
- ///< instruction cache.
-
- UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache
- ///< line is held shared. 2 - cache line is held
- ///< exclusive. 3 - cache line is modified. All other
- ///< values are reserved.
-
- UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check
- ///< parameter is valid.
-
- UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of
- ///< the cache indicated by this value.
-
- UINT64 WayIndexIsValid:1; ///< Bit21, The way and index field in the
- ///< cache_check parameter is valid.
-
- UINT64 Reserved2:1;
- UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error was
- ///< detected, and data was poisoned for
- ///< the corresponding cache line during
- ///< castout.
- UINT64 Reserved3:8;
- UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache
- ///< line where the error occurred.
- UINT64 Reserved4:2;
-
- UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value
- ///< is set to zero, the instruction that
- ///< generated the machine check was an
- ///< Intel Itanium instruction. If this bit
- ///< is set to one, the instruction that
- ///< generated the machine check was IA-32
- ///< instruction.
-
- UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the
- ///< cache_check parameter is valid.
-
- UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The
- ///< privilege level of the instruction
- ///< bundle responsible for generating the
- ///< machine check.
-
- UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the
- ///< cache_check parameter is
- ///< valid.
-
- UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit
- ///< is set to one to indicate that the machine
- ///< check has been corrected.
-
- UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:
- ///< This bit is set to one to
- ///< indicate that a valid target
- ///< address has been logged.
-
- UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: This
- ///< bit is set to one to indicate that
- ///< a valid requester identifier has
- ///< been logged.
-
- UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This
- ///< bit is set to one to indicate that
- ///< a valid responder identifier has
- ///< been logged.
-
- UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction pointer.
- ///< This bit is set to one to indicate
- ///< that a valid precise instruction
- ///< pointer has been logged.
-
-} PAL_CACHE_CHECK_INFO;
-
-
-typedef struct {
- UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the translation
- ///< register where the failure occurred.
- UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the
- ///< TLB_check parameter is valid.
- UINT64 Reserved1 :1;
- UINT64 TlbLevel:2; ///< Bit11:10, The level of the TLB where the
- ///< error occurred. A value of 0 indicates the
- ///< first level of TLB
- UINT64 Reserved2 :4;
-
- UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the data
- ///< translation registers.
-
- UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the instruction
- ///< translation registers
-
- UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data
- ///< translation cache.
-
- UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the instruction
- ///< translation cache.
-
- UINT64 FailedOperation:4; ///< Bit23:20, Type of cache operation that
- ///< caused the machine check: 0 - unknown
- ///< 1 - TLB access due to load instruction
- ///< 2 - TLB access due to store
- ///< instruction 3 - TLB access due to
- ///< instruction fetch or instruction
- ///< prefetch 4 - TLB access due to data
- ///< prefetch (both hardware and software)
- ///< 5 - TLB shoot down access 6 - TLB
- ///< probe instruction (probe, tpa) 7 -
- ///< move in (VHPT fill) 8 - purge (insert
- ///< operation that purges entries or a TLB
- ///< purge instruction) All other values
- ///< are reserved.
-
- UINT64 Reserved3:30;
- UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value
- ///< is set to zero, the instruction that
- ///< generated the machine check was an
- ///< Intel Itanium instruction. If this bit
- ///< is set to one, the instruction that
- ///< generated the machine check was IA-32
- ///< instruction.
-
- UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the
- ///< TLB_check parameter is valid.
-
- UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The
- ///< privilege level of the instruction
- ///< bundle responsible for generating the
- ///< machine check.
-
- UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the
- ///< TLB_check parameter is valid.
-
- UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit
- ///< is set to one to indicate that the machine
- ///< check has been corrected.
-
- UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:
- ///< This bit is set to one to
- ///< indicate that a valid target
- ///< address has been logged.
-
- UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: This
- ///< bit is set to one to indicate that
- ///< a valid requester identifier has
- ///< been logged.
-
- UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This
- ///< bit is set to one to indicate that
- ///< a valid responder identifier has
- ///< been logged.
-
- UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction pointer.
- ///< This bit is set to one to indicate
- ///< that a valid precise instruction
- ///< pointer has been logged.
-} PAL_TLB_CHECK_INFO;
-
-/**
- PAL Procedure - PAL_MC_ERROR_INFO.
-
- Return Processor Machine Check Information and Processor
- Static State for logging by SAL. It is required by Itanium processors. The
- PAL procedure supports the Static Registers calling
- convention. It could be called at physical and virtual mode.
-
- @param Index Index of PAL_MC_ERROR_INFO within the list of PAL
- procedures.
- @param InfoIndex Unsigned 64-bit integer identifying the
- error information that is being requested.
- See PAL_MC_ERROR_INFO.InfoIndex.
- @param LevelIndex 8-byte formatted value identifying the
- structure to return error information
- on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
- @param ErrorTypeIndex Unsigned 64-bit integer denoting the
- type of error information that is
- being requested for the structure
- identified in LevelIndex.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -6 Argument was valid, but no error
- information was available
-
- @return R9 Error information returned. The format of this
- value is dependant on the input values passed.
- @return R10 If this value is zero, all the error information
- specified by err_type_index has been returned. If
- this value is one, more structure-specific error
- information is available and the caller needs to
- make this procedure call again with level_index
- unchanged and err_type_index, incremented.
-
-**/
-#define PAL_MC_ERROR_INFO 25
-
-/**
- PAL Procedure - PAL_MC_EXPECTED.
-
- Set/Reset Expected Machine Check Indicator. It is required by
- Itanium processors. The PAL procedure supports the Static Registers calling
- convention. It could be called at physical mode.
-
- @param Index Index of PAL_MC_EXPECTED within the list of PAL
- procedures.
- @param Expected Unsigned integer with a value of 0 or 1 to
- set or reset the hardware resource
- PALE_CHECK examines for expected machine
- checks.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned integer denoting whether a machine check
- was previously expected.
-
-**/
-#define PAL_MC_EXPECTED 23
-
-/**
- PAL Procedure - PAL_MC_REGISTER_MEM.
-
- Register min-state save area with PAL for machine checks and
- inits. It is required by Itanium processors. The PAL procedure supports the
- Static Registers calling convention. It could be called at
- physical mode.
-
- @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL
- procedures.
- @param Address Physical address of the buffer to be
- registered with PAL.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_MC_REGISTER_MEM 27
-
-/**
- PAL Procedure - PAL_MC_RESUME.
-
- Restore minimal architected state and return to interrupted
- process. It is required by Itanium processors. The PAL procedure supports the
- Static Registers calling convention. It could be called at
- physical mode.
-
- @param Index Index of PAL_MC_RESUME within the list of PAL
- procedures.
- @param SetCmci Unsigned 64 bit integer denoting whether to
- set the CMC interrupt. A value of 0 indicates
- not to set the interrupt, a value of 1
- indicated to set the interrupt, and all other
- values are reserved.
- @param SavePtr Physical address of min-state save area used
- to used to restore processor state.
- @param NewContext Unsigned 64-bit integer denoting whether
- the caller is returning to a new context.
- A value of 0 indicates the caller is
- returning to the interrupted context, a
- value of 1 indicates that the caller is
- returning to a new context.
-
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_MC_RESUME 26
-
-/**
- PAL Procedure - PAL_HALT.
-
- Enter the low-power HALT state or an implementation-dependent
- low-power state. It is optinal. The PAL procedure supports the
- Static Registers calling convention. It could be called at
- physical mode.
-
- @param Index Index of PAL_HALT within the list of PAL
- procedures.
- @param HaltState Unsigned 64-bit integer denoting low power
- state requested.
- @param IoDetailPtr 8-byte aligned physical address pointer to
- information on the type of I/O
- (load/store) requested.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Value returned if a load instruction is requested
- in the io_detail_ptr
-
-**/
-#define PAL_HALT 28
-
-
-/**
- PAL Procedure - PAL_HALT_INFO.
-
- Return the low power capabilities of the processor. It is
- required by Itanium processors. The PAL procedure supports the
- Stacked Registers calling convention. It could be called at
- physical and virtual mode.
-
- @param Index Index of PAL_HALT_INFO within the list of PAL
- procedures.
- @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned
- on an 8-byte boundary.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_HALT_INFO 257
-
-
-/**
- PAL Procedure - PAL_HALT_LIGHT.
-
- Enter the low power LIGHT HALT state. It is required by
- Itanium processors. The PAL procedure supports the Static Registers calling
- convention. It could be called at physical and virtual mode.
-
- @param Index Index of PAL_HALT_LIGHT within the list of PAL
- procedures.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_HALT_LIGHT 29
-
-/**
- PAL Procedure - PAL_CACHE_LINE_INIT.
-
- Initialize tags and data of a cache line for processor
- testing. It is required by Itanium processors. The PAL procedure supports the
- Static Registers calling convention. It could be called at
- physical and virtual mode.
-
- @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL
- procedures.
- @param Address Unsigned 64-bit integer value denoting the
- physical address from which the physical page
- number is to be generated. The address must be
- an implemented physical address, bit 63 must
- be zero.
- @param DataValue 64-bit data value which is used to
- initialize the cache line.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_CACHE_LINE_INIT 31
-
-/**
- PAL Procedure - PAL_CACHE_READ.
-
- Read tag and data of a cache line for diagnostic testing. It
- is optional. The PAL procedure supports the
- Satcked Registers calling convention. It could be called at
- physical mode.
-
- @param Index Index of PAL_CACHE_READ within the list of PAL
- procedures.
- @param LineId 8-byte formatted value describing where in the
- cache to read the data.
- @param Address 64-bit 8-byte aligned physical address from
- which to read the data. The address must be an
- implemented physical address on the processor
- model with bit 63 set to zero.
-
- @retval 1 The word at address was found in the
- cache, but the line was invalid.
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -5 The word at address was not found in the
- cache.
- @retval -7 The operation requested is not supported
- for this cache_type and level.
-
- @return R9 Right-justified value returned from the cache
- line.
- @return R10 The number of bits returned in data.
- @return R11 The status of the cache line.
-
-**/
-#define PAL_CACHE_READ 259
-
-
-/**
- PAL Procedure - PAL_CACHE_WRITE.
-
- Write tag and data of a cache for diagnostic testing. It is
- optional. The PAL procedure supports the Satcked Registers
- calling convention. It could be called at physical mode.
-
- @param Index Index of PAL_CACHE_WRITE within the list of PAL
- procedures.
- @param LineId 8-byte formatted value describing where in the
- cache to write the data.
- @param Address 64-bit 8-byte aligned physical address at
- which the data should be written. The address
- must be an implemented physical address on the
- processor model with bit 63 set to 0.
- @param Data Unsigned 64-bit integer value to write into
- the specified part of the cache.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -7 The operation requested is not supported
- for this cache_type and level.
-
-**/
-#define PAL_CACHE_WRITE 260
-
-/**
- PAL Procedure - PAL_TEST_INFO.
-
- Returns alignment and size requirements needed for the memory
- buffer passed to the PAL_TEST_PROC procedure as well as
- information on self-test control words for the processor self
- tests. It is required by Itanium processors. The PAL procedure supports the
- Static Registers calling convention. It could be called at
- physical mode.
-
- @param Index Index of PAL_TEST_INFO within the list of PAL
- procedures.
- @param TestPhase Unsigned integer that specifies which phase
- of the processor self-test information is
- being requested on. A value of 0 indicates
- the phase two of the processor self-test and
- a value of 1 indicates phase one of the
- processor self-test. All other values are
- reserved.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned 64-bit integer denoting the number of
- bytes of main memory needed to perform the second
- phase of processor self-test.
- @return R10 Unsigned 64-bit integer denoting the alignment
- required for the memory buffer.
- @return R11 48-bit wide bit-field indicating if control of
- the processor self-tests is supported and which
- bits of the test_control field are defined for
- use.
-
-**/
-#define PAL_TEST_INFO 37
-
-typedef struct {
- UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory
- ///< buffer that is passed to this procedure.
- ///< BufferSize must be greater than or equal in
- ///< size to the bytes_needed return value from
- ///< PAL_TEST_INFO, otherwise this procedure will
- ///< return with an invalid argument return
- ///< value.
-
- UINT64 TestPhase:8; ///< Defines which phase of the processor
- ///< self-tests are requested to be run. A value
- ///< of zero indicates to run phase two of the
- ///< processor self-tests. Phase two of the
- ///< processor self-tests are ones that require
- ///< external memory to execute correctly. A
- ///< value of one indicates to run phase one of
- ///< the processor self-tests. Phase one of the
- ///< processor self-tests are tests run during
- ///< PALE_RESET and do not depend on external
- ///< memory to run correctly. When the caller
- ///< requests to have phase one of the processor
- ///< self-test run via this procedure call, a
- ///< memory buffer may be needed to save and
- ///< restore state as required by the PAL calling
- ///< conventions. The procedure PAL_TEST_INFO
- ///< informs the caller about the requirements of
- ///< the memory buffer.
-} PAL_TEST_INFO_INFO;
-
-typedef struct {
- UINT64 TestControl:47; ///< This is an ordered implementation-specific
- ///< control word that allows the user control
- ///< over the length and runtime of the
- ///< processor self-tests. This control word is
- ///< ordered from the longest running tests up
- ///< to the shortest running tests with bit 0
- ///< controlling the longest running test. PAL
- ///< may not implement all 47-bits of the
- ///< test_control word. PAL communicates if a
- ///< bit provides control by placing a zero in
- ///< that bit. If a bit provides no control,
- ///< PAL will place a one in it. PAL will have
- ///< two sets of test_control bits for the two
- ///< phases of the processor self-test. PAL
- ///< provides information about implemented
- ///< test_control bits at the hand-off from PAL
- ///< to SAL for the firmware recovery check.
- ///< These test_control bits provide control
- ///< for phase one of processor self-test. It
- ///< also provides this information via the PAL
- ///< procedure call PAL_TEST_INFO for both the
- ///< phase one and phase two processor tests
- ///< depending on which information the caller
- ///< is requesting. PAL interprets these bits
- ///< as input parameters on two occasions. The
- ///< first time is when SAL passes control back
- ///< to PAL after the firmware recovery check.
- ///< The second time is when a call to
- ///< PAL_TEST_PROC is made. When PAL interprets
- ///< these bits it will only interpret
- ///< implemented test_control bits and will
- ///< ignore the values located in the
- ///< unimplemented test_control bits. PAL
- ///< interprets the implemented bits such that
- ///< if a bit contains a zero, this indicates
- ///< to run the test. If a bit contains a one,
- ///< this indicates to PAL to skip the test. If
- ///< the cs bit indicates that control is not
- ///< available, the test_control bits will be
- ///< ignored or generate an illegal argument in
- ///< procedure calls if the caller sets these
- ///< bits.
-
- UINT64 ControlSupport:1; ///< This bit defines if an implementation
- ///< supports control of the PAL self-tests
- ///< via the self-test control word. If
- ///< this bit is 0, the implementation does
- ///< not support control of the processor
- ///< self-tests via the self-test control
- ///< word. If this bit is 1, the
- ///< implementation does support control of
- ///< the processor self-tests via the
- ///< self-test control word. If control is
- ///< not supported, GR37 will be ignored at
- ///< the hand-off between SAL and PAL after
- ///< the firmware recovery check and the
- ///< PAL procedures related to the
- ///< processor self-tests may return
- ///< illegal arguments if a user tries to
- ///< use the self-test control features.
- UINT64 Reserved:16;
-} PAL_SELF_TEST_CONTROL;
-
-typedef struct {
- UINT64 Attributes:8; ///< Specifies the memory attributes that are
- ///< allowed to be used with the memory buffer
- ///< passed to this procedure. The attributes
- ///< parameter is a vector where each bit
- ///< represents one of the virtual memory
- ///< attributes defined by the architecture.See
- ///< MEMORY_AATRIBUTES. The caller is required
- ///< to support the cacheable attribute for the
- ///< memory buffer, otherwise an invalid
- ///< argument will be returned.
- UINT64 Reserved:8;
- UINT64 TestControl:48; ///< Is the self-test control word
- ///< corresponding to the test_phase passed.
- ///< This test_control directs the coverage and
- ///< runtime of the processor self-tests
- ///< specified by the test_phase input
- ///< argument. Information on if this
- ///< feature is implemented and the number of
- ///< bits supported can be obtained by the
- ///< PAL_TEST_INFO procedure call. If this
- ///< feature is implemented by the processor,
- ///< the caller can selectively skip parts of
- ///< the processor self-test by setting
- ///< test_control bits to a one. If a bit has a
- ///< zero, this test will be run. The values in
- ///< the unimplemented bits are ignored. If
- ///< PAL_TEST_INFO indicated that the self-test
- ///< control word is not implemented, this
- ///< procedure will return with an invalid
- ///< argument status if the caller sets any of
- ///< the test_control bits. See
- ///< PAL_SELF_TEST_CONTROL.
-} PAL_TEST_CONTROL;
-
-/**
- PAL Procedure - PAL_TEST_PROC.
-
- Perform late processor self test. It is required by Itanium processors. The
- PAL procedure supports the Static Registers calling
- convention. It could be called at physical mode.
-
- @param Index Index of PAL_TEST_PROC within the list of PAL
- procedures.
- @param TestAddress 64-bit physical address of main memory
- area to be used by processor self-test.
- The memory region passed must be
- cacheable, bit 63 must be zero.
- @param TestInfo Input argument specifying the size of the
- memory buffer passed and the phase of the
- processor self-test that should be run. See
- PAL_TEST_INFO.
- @param TestParam Input argument specifying the self-test
- control word and the allowable memory
- attributes that can be used with the memory
- buffer. See PAL_TEST_CONTROL.
-
- @retval 1 Call completed without error, but hardware
- failures occurred during self-test.
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Formatted 8-byte value denoting the state of the
- processor after self-test
-
-**/
-#define PAL_TEST_PROC 258
-
-typedef struct {
- UINT32 NumberOfInterruptControllers; ///< Number of interrupt
- ///< controllers currently
- ///< enabled on the system.
-
- UINT32 NumberOfProcessors; ///< Number of processors currently
- ///< enabled on the system.
-} PAL_PLATFORM_INFO;
-
-/**
- PAL Procedure - PAL_COPY_INFO.
-
- Return information needed to relocate PAL procedures and PAL
- PMI code to memory. It is required by Itanium processors. The PAL procedure
- supports the Static Registers calling convention. It could be
- called at physical mode.
-
- @param Index Index of PAL_COPY_INFO within the list of PAL
- procedures.
- @param CopyType Unsigned integer denoting type of procedures
- for which copy information is requested.
- @param PlatformInfo 8-byte formatted value describing the
- number of processors and the number of
- interrupt controllers currently enabled
- on the system. See PAL_PLATFORM_INFO.
- @param McaProcStateInfo Unsigned integer denoting the number
- of bytes that SAL needs for the
- min-state save area for each
- processor.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned integer denoting the number of bytes of
- PAL information that must be copied to main
- memory.
- @return R10 Unsigned integer denoting the starting alignment
- of the data to be copied.
-
-**/
-#define PAL_COPY_INFO 30
-
-/**
- PAL Procedure - PAL_COPY_PAL.
-
- Relocate PAL procedures and PAL PMI code to memory. It is
- required by Itanium processors. The PAL procedure supports the Stacked
- Registers calling convention. It could be called at physical
- mode.
-
- @param Index Index of PAL_COPY_PAL within the list of PAL
- procedures.
- @param TargetAddress Physical address of a memory buffer to
- copy relocatable PAL procedures and PAL
- PMI code.
- @param AllocSize Unsigned integer denoting the size of the
- buffer passed by SAL for the copy operation.
- @param CopyOption Unsigned integer indicating whether
- relocatable PAL code and PAL PMI code
- should be copied from firmware address
- space to main memory.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned integer denoting the offset of PAL_PROC
- in the relocatable segment copied.
-
-**/
-#define PAL_COPY_PAL 256
-
-/**
- PAL Procedure - PAL_ENTER_IA_32_ENV.
-
- Enter IA-32 System environment. It is optional. The PAL
- procedure supports the Static Registers calling convention.
- It could be called at physical mode.
-
- Note: Since this is a special call, it does not follow the PAL
- static register calling convention. GR28 contains the index of
- PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
- input arguments including GR29-GR31 are setup by SAL to values
- as required by the IA-32 operating system defined in Table
- 11-67. The registers that are designated as preserved, scratch,
- input arguments and procedure return values by the static
- procedure calling convention are not followed by this call. For
- instance, GR5 and GR6 need not be preserved since these are
- regarded as scratch by the IA-32 operating system. Note: In an
- MP system, this call must be COMPLETED on the first CPU to enter
- the IA-32 System Environment (may or may not be the BSP) prior
- to being called on the remaining processors in the MP system.
-
- @param Index GR28 contains the index of the
- PAL_ENTER_IA_32_ENV call within the list of PAL
- procedures.
-
-
- @retval The status is returned in GR4.
- -1 - Un-implemented procedure 0 JMPE detected
- at privilege level
-
- 0 - 1 SAL allocated buffer for IA-32 System
- Environment operation is too small
-
- 2 - IA-32 Firmware Checksum Error
-
- 3 - SAL allocated buffer for IA-32 System
- Environment operation is not properly aligned
-
- 4 - Error in SAL MP Info Table
-
- 5 - Error in SAL Memory Descriptor Table
-
- 6 - Error in SAL System Table
-
- 7 - Inconsistent IA-32 state
-
- 8 - IA-32 Firmware Internal Error
-
- 9 - IA-32 Soft Reset (Note: remaining register
- state is undefined for this termination
- reason)
-
- 10 - Machine Check Error
-
- 11 - Error in SAL I/O Intercept Table
-
- 12 - Processor exit due to other processor in
- MP system terminating the IA32 system
- environment. (Note: remaining register state
- is undefined for this termination reason.)
-
- 13 - Itanium architecture-based state
- corruption by either SAL PMI handler or I/O
- Intercept callback function.
-
-
-**/
-#define PAL_ENTER_IA_32_ENV 33
-
-/**
- PAL Procedure - PAL_PMI_ENTRYPOINT.
-
- Register PMI memory entrypoints with processor. It is required
- by Itanium processors. The PAL procedure supports the Stacked Registers
- calling convention. It could be called at physical mode.
-
- @param Index Index of PAL_PMI_ENTRYPOINT within the list of
- PAL procedures.
- @param SalPmiEntry 256-byte aligned physical address of SAL
- PMI entrypoint in memory.
-
- @retval 0 Call completed without error
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
-**/
-#define PAL_PMI_ENTRYPOINT 32
-
-
-/**
-
- The ASCII brand identification string will be copied to the
- address specified in the address input argument. The processor
- brand identification string is defined to be a maximum of 128
- characters long; 127 bytes will contain characters and the 128th
- byte is defined to be NULL (0). A processor may return less than
- the 127 ASCII characters as long as the string is null
- terminated. The string length will be placed in the brand_info
- return argument.
-
-**/
-#define PAL_BRAND_INFO_ID_REQUEST 0
-
-/**
- PAL Procedure - PAL_BRAND_INFO.
-
- Provides processor branding information. It is optional by
- Itanium processors. The PAL procedure supports the Stacked Registers calling
- convention. It could be called at physical and Virtual mode.
-
- @param Index Index of PAL_BRAND_INFO within the list of PAL
- procedures.
- @param InfoRequest Unsigned 64-bit integer specifying the
- information that is being requested. (See
- PAL_BRAND_INFO_ID_REQUEST)
- @param Address Unsigned 64-bit integer specifying the
- address of the 128-byte block to which the
- processor brand string shall be written.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -6 Input argument is not implemented.
-
- @return R9 Brand information returned. The format of this
- value is dependent on the input values passed.
-
-**/
-#define PAL_BRAND_INFO 274
-
-/**
- PAL Procedure - PAL_GET_HW_POLICY.
-
- Returns the current hardware resource sharing policy of the
- processor. It is optional by Itanium processors. The PAL procedure supports
- the Static Registers calling convention. It could be called at
- physical and Virtual mode.
-
-
- @param Index Index of PAL_GET_HW_POLICY within the list of PAL
- procedures.
- @param ProcessorNumber Unsigned 64-bit integer that specifies
- for which logical processor
- information is being requested. This
- input argument must be zero for the
- first call to this procedure and can
- be a maximum value of one less than
- the number of logical processors
- impacted by the hardware resource
- sharing policy, which is returned by
- the R10 return value.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
- @return R9 Unsigned 64-bit integer representing the current
- hardware resource sharing policy.
- @return R10 Unsigned 64-bit integer that returns the number
- of logical processors impacted by the policy
- input argument.
- @return R11 Unsigned 64-bit integer containing the logical
- address of one of the logical processors
- impacted by policy modification.
-
-**/
-#define PAL_GET_HW_POLICY 48
-
-
-//
-// Value of PAL_SET_HW_POLICY.Policy
-//
-#define PAL_SET_HW_POLICY_PERFORMANCE 0
-#define PAL_SET_HW_POLICY_FAIRNESS 1
-#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2
-#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3
-
-/**
- PAL Procedure - PAL_SET_HW_POLICY.
-
- Sets the current hardware resource sharing policy of the
- processor. It is optional by Itanium processors. The PAL procedure supports
- the Static Registers calling convention. It could be called at
- physical and Virtual mode.
-
- @param Index Index of PAL_SET_HW_POLICY within the list of PAL
- procedures.
- @param Policy Unsigned 64-bit integer specifying the hardware
- resource sharing policy the caller is setting.
- See Value of PAL_SET_HW_POLICY.Policy above.
-
- @retval 1 Call completed successfully but could not
- change the hardware policy since a
- competing logical processor is set in
- exclusive high priority.
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_SET_HW_POLICY 49
-
-typedef struct {
- UINT64 Mode:3; ///< Bit2:0, Indicates the mode of operation for this
- ///< procedure: 0 - Query mode 1 - Error inject mode
- ///< (err_inj should also be specified) 2 - Cancel
- ///< outstanding trigger. All other fields in
- ///< PAL_MC_ERROR_TYPE_INFO,
- ///< PAL_MC_ERROR_STRUCTURE_INFO and
- ///< PAL_MC_ERROR_DATA_BUFFER are ignored. All other
- ///< values are reserved.
-
- UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of error
- ///< injection: 0 - Error inject only (no
- ///< error consumption) 1 - Error inject
- ///< and consume All other values are
- ///< reserved.
-
- UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity desired
- ///< for error injection/query. Definitions
- ///< of the different error severity types
- ///< 0 - Corrected error 1 - Recoverable
- ///< error 2 - Fatal error 3 - Reserved
-
- UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure
- ///< identification for error
- ///< injection/query: 0 - Any structure
- ///< (cannot be used during query mode).
- ///< When selected, the structure type used
- ///< for error injection is determined by
- ///< PAL. 1 - Cache 2 - TLB 3 - Register
- ///< file 4 - Bus/System interconnect 5-15
- ///< - Reserved 16-31 - Processor
- ///< specific error injection
- ///< capabilities.ErrorDataBuffer is used
- ///< to specify error types. Please refer
- ///< to the processor specific
- ///< documentation for additional details.
-
- UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure
- ///< hierarchy for error
- ///< injection/query: 0 - Any level of
- ///< hierarchy (cannot be used during
- ///< query mode). When selected, the
- ///< structure hierarchy used for error
- ///< injection is determined by PAL. 1
- ///< - Error structure hierarchy
- ///< level-1 2 - Error structure
- ///< hierarchy level-2 3 - Error
- ///< structure hierarchy level-3 4 -
- ///< Error structure hierarchy level-4
- ///< All other values are reserved.
-
- UINT64 Reserved:32; ///< Reserved 47:16 Reserved
-
- UINT64 ImplSpec:16; ///< Bit63:48, Processor specific error injection capabilities.
-} PAL_MC_ERROR_TYPE_INFO;
-
-typedef struct {
- UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates that the
- ///< structure information fields
- ///< (c_t,cl_p,cl_id) are valid and
- ///< should be used for error injection.
- ///< When 0, the structure information
- ///< fields are ignored, and the values
- ///< of these fields used for error
- ///< injection are
- ///< implementation-specific.
-
- UINT64 CacheType:2; ///< Bit2:1 Indicates which cache should be used
- ///< for error injection: 0 - Reserved 1 -
- ///< Instruction cache 2 - Data or unified cache
- ///< 3 - Reserved
-
- UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the portion of the
- ///< cache line where the error should
- ///< be injected: 0 - Reserved 1 - Tag
- ///< 2 - Data 3 - mesi All other
- ///< values are reserved.
-
- UINT64 Mechanism:3; ///< Bit8:6 Indicates which mechanism is used to
- ///< identify the cache line to be used for error
- ///< injection: 0 - Reserved 1 - Virtual address
- ///< provided in the inj_addr field of the buffer
- ///< pointed to by err_data_buffer should be used
- ///< to identify the cache line for error
- ///< injection. 2 - Physical address provided in
- ///< the inj_addr field of the buffer pointed to
- ///< by err_data_buffershould be used to identify
- ///< the cache line for error injection. 3 - way
- ///< and index fields provided in err_data_buffer
- ///< should be used to identify the cache line
- ///< for error injection. All other values are
- ///< reserved.
-
- UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates that a
- ///< multiple bit, non-correctable
- ///< error should be injected in the
- ///< cache line specified by cl_id.
- ///< If this injected error is not
- ///< consumed, it may eventually
- ///< cause a data-poisoning event
- ///< resulting in a corrected error
- ///< signal, when the associated
- ///< cache line is cast out (implicit
- ///< or explicit write-back of the
- ///< cache line). The error severity
- ///< specified by err_sev in
- ///< err_type_info must be set to 0
- ///< (corrected error) when this bit
- ///< is set.
-
- UINT64 Reserved1:22;
-
- UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates that the
- ///< trigger information fields (trigger,
- ///< trigger_pl) are valid and should be
- ///< used for error injection. When 0,
- ///< the trigger information fields are
- ///< ignored and error injection is
- ///< performed immediately.
-
- UINT64 Triger:4; ///< Bit36:33 Indicates the operation type to be
- ///< used as the error trigger condition. The
- ///< address corresponding to the trigger is
- ///< specified in the trigger_addr field of the
- ///< buffer pointed to by err_data_buffer: 0 -
- ///< Instruction memory access. The trigger match
- ///< conditions for this operation type are similar
- ///< to the IBR address breakpoint match conditions
- ///< 1 - Data memory access. The trigger match
- ///< conditions for this operation type are similar
- ///< to the DBR address breakpoint match conditions
- ///< All other values are reserved.
-
- UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the privilege
- ///< level of the context during which
- ///< the error should be injected: 0 -
- ///< privilege level 0 1 - privilege
- ///< level 1 2 - privilege level 2 3 -
- ///< privilege level 3 All other values
- ///< are reserved. If the implementation
- ///< does not support privilege level
- ///< qualifier for triggers (i.e. if
- ///< trigger_pl is 0 in the capabilities
- ///< vector), this field is ignored and
- ///< triggers can be taken at any
- ///< privilege level.
-
- UINT64 Reserved2:24;
-} PAL_MC_ERROR_STRUCT_INFO;
-
-/**
-
- Buffer Pointed to by err_data_buffer - TLB
-
-**/
-typedef struct {
- UINT64 TrigerAddress;
- UINT64 VirtualPageNumber:52;
- UINT64 Reserved1:8;
- UINT64 RegionId:24;
- UINT64 Reserved2:40;
-} PAL_MC_ERROR_DATA_BUFFER_TLB;
-
-/**
- PAL Procedure - PAL_MC_ERROR_INJECT.
-
- Injects the requested processor error or returns information
- on the supported injection capabilities for this particular
- processor implementation. It is optional by Itanium processors. The PAL
- procedure supports the Stacked Registers calling convention.
- It could be called at physical and Virtual mode.
-
- @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL
- procedures.
- @param ErrorTypeInfo Unsigned 64-bit integer specifying the
- first level error information which
- identifies the error structure and
- corresponding structure hierarchy, and
- the error severity.
- @param ErrorStructInfo Unsigned 64-bit integer identifying
- the optional structure specific
- information that provides the second
- level details for the requested error.
- @param ErrorDataBuffer 64-bit physical address of a buffer
- providing additional parameters for
- the requested error. The address of
- this buffer must be 8-byte aligned.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -4 Call completed with error; the requested
- error could not be injected due to failure in
- locating the target location in the specified
- structure.
- @retval -5 Argument was valid, but requested error
- injection capability is not supported.
- @retval -9 Call requires PAL memory buffer.
-
- @return R9 64-bit vector specifying the supported error
- injection capabilities for the input argument
- combination of struct_hier, err_struct and
- err_sev fields in ErrorTypeInfo.
- @return R10 64-bit vector specifying the architectural
- resources that are used by the procedure.
-
-**/
-#define PAL_MC_ERROR_INJECT 276
-
-
-//
-// Types of PAL_GET_PSTATE.Type
-//
-#define PAL_GET_PSTATE_RECENT 0
-#define PAL_GET_PSTATE_AVERAGE_NEW_START 1
-#define PAL_GET_PSTATE_AVERAGE 2
-#define PAL_GET_PSTATE_NOW 3
-
-/**
- PAL Procedure - PAL_GET_PSTATE.
-
- Returns the performance index of the processor. It is optional
- by Itanium processors. The PAL procedure supports the Stacked Registers
- calling convention. It could be called at physical and Virtual
- mode.
-
- @param Index Index of PAL_GET_PSTATE within the list of PAL
- procedures.
- @param Type Type of performance_index value to be returned
- by this procedure.See PAL_GET_PSTATE.Type above.
-
- @retval 1 Call completed without error, but accuracy
- of performance index has been impacted by a
- thermal throttling event, or a
- hardware-initiated event.
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
- @return R9 Unsigned integer denoting the processor
- performance for the time duration since the last
- PAL_GET_PSTATE procedure call was made. The
- value returned is between 0 and 100, and is
- relative to the performance index of the highest
- available P-state.
-
-**/
-#define PAL_GET_PSTATE 262
-
-/**
-
- Layout of PAL_PSTATE_INFO.PStateBuffer
-
-**/
-typedef struct {
- UINT32 PerformanceIndex:7;
- UINT32 Reserved1:5;
- UINT32 TypicalPowerDissipation:20;
- UINT32 TransitionLatency1;
- UINT32 TransitionLatency2;
- UINT32 Reserved2;
-} PAL_PSTATE_INFO_BUFFER;
-
-
-/**
- PAL Procedure - PAL_PSTATE_INFO.
-
- Returns information about the P-states supported by the
- processor. It is optional by Itanium processors. The PAL procedure supports
- the Static Registers calling convention. It could be called
- at physical and Virtual mode.
-
- @param Index Index of PAL_PSTATE_INFO within the list of PAL
- procedures.
- @param PStateBuffer 64-bit pointer to a 256-byte buffer
- aligned on an 8-byte boundary. See
- PAL_PSTATE_INFO_BUFFER above.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
-
- @return R9 Unsigned integer denoting the number of P-states
- supported. The maximum value of this field is 16.
- @return R10 Dependency domain information
-
-**/
-#define PAL_PSTATE_INFO 44
-
-
-/**
- PAL Procedure - PAL_SET_PSTATE.
-
- To request a processor transition to a given P-state. It is
- optional by Itanium processors. The PAL procedure supports the Stacked
- Registers calling convention. It could be called at physical
- and Virtual mode.
-
- @param Index Index of PAL_SET_PSTATE within the list of PAL
- procedures.
- @param PState Unsigned integer denoting the processor
- P-state being requested.
- @param ForcePState Unsigned integer denoting whether the
- P-state change should be forced for the
- logical processor.
-
- @retval 1 Call completed without error, but
- transition request was not accepted
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_SET_PSTATE 263
-
-/**
- PAL Procedure - PAL_SHUTDOWN.
-
- Put the logical processor into a low power state which can be
- exited only by a reset event. It is optional by Itanium processors. The PAL
- procedure supports the Static Registers calling convention. It
- could be called at physical mode.
-
- @param Index Index of PAL_SHUTDOWN within the list of PAL
- procedures.
- @param NotifyPlatform 8-byte aligned physical address
- pointer providing details on how to
- optionally notify the platform that
- the processor is entering a shutdown
- state.
-
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_SHUTDOWN 45
-
-/**
-
- Layout of PAL_MEMORY_BUFFER.ControlWord
-
-**/
-typedef struct {
- UINT64 Registration:1;
- UINT64 ProbeInterrupt:1;
- UINT64 Reserved:62;
-} PAL_MEMORY_CONTROL_WORD;
-
-/**
- PAL Procedure - PAL_MEMORY_BUFFER.
-
- Provides cacheable memory to PAL for exclusive use during
- runtime. It is optional by Itanium processors. The PAL procedure supports the
- Static Registers calling convention. It could be called at
- physical mode.
-
- @param Index Index of PAL_MEMORY_BUFFER within the list of PAL
- procedures.
- @param BaseAddress Physical address of the memory buffer
- allocated for PAL use.
- @param AllocSize Unsigned integer denoting the size of the
- memory buffer.
- @param ControlWord Formatted bit vector that provides control
- options for this procedure. See
- PAL_MEMORY_CONTROL_WORD above.
-
- @retval 1 Call has not completed a buffer relocation
- due to a pending interrupt
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
- @return R9 Returns the minimum size of the memory buffer
- required if the alloc_size input argument was
- not large enough.
-
-**/
-#define PAL_MEMORY_BUFFER 277
-
-
-/**
- PAL Procedure - PAL_VP_CREATE.
-
- Initializes a new vpd for the operation of a new virtual
- processor in the virtual environment. It is optional by Itanium processors.
- The PAL procedure supports the Stacked Registers calling
- convention. It could be called at Virtual mode.
-
- @param Index Index of PAL_VP_CREATE within the list of PAL
- procedures.
- @param Vpd 64-bit host virtual pointer to the Virtual
- Processor Descriptor (VPD).
- @param HostIva 64-bit host virtual pointer to the host IVT
- for the virtual processor
- @param OptionalHandler 64-bit non-zero host-virtual pointer
- to an optional handler for
- virtualization intercepts.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_CREATE 265
-
-/**
-
- Virtual Environment Information Parameter
-
-**/
-typedef struct {
- UINT64 Reserved1:8;
- UINT64 Opcode:1;
- UINT64 Reserved:53;
-} PAL_VP_ENV_INFO_RETURN;
-
-/**
- PAL Procedure - PAL_VP_ENV_INFO.
-
- Returns the parameters needed to enter a virtual environment.
- It is optional by Itanium processors. The PAL procedure supports the Stacked
- Registers calling convention. It could be called at Virtual
- mode.
-
- @param Index Index of PAL_VP_ENV_INFO within the list of PAL
- procedures.
- @param Vpd 64-bit host virtual pointer to the Virtual
- Processor Descriptor (VPD).
- @param HostIva 64-bit host virtual pointer to the host IVT
- for the virtual processor
- @param OptionalHandler 64-bit non-zero host-virtual pointer
- to an optional handler for
- virtualization intercepts.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
- @return R9 Unsigned integer denoting the number of bytes
- required by the PAL virtual environment buffer
- during PAL_VP_INIT_ENV
- @return R10 64-bit vector of virtual environment
- information. See PAL_VP_ENV_INFO_RETURN.
-
-
-**/
-#define PAL_VP_ENV_INFO 266
-
-/**
- PAL Procedure - PAL_VP_EXIT_ENV.
-
- Allows a logical processor to exit a virtual environment.
- It is optional by Itanium processors. The PAL procedure supports the Stacked
- Registers calling convention. It could be called at Virtual
- mode.
-
- @param Index Index of PAL_VP_EXIT_ENV within the list of PAL
- procedures.
- @param Iva Optional 64-bit host virtual pointer to the IVT
- when this procedure is done
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_EXIT_ENV 267
-
-
-
-/**
- PAL Procedure - PAL_VP_INIT_ENV.
-
- Allows a logical processor to enter a virtual environment. It
- is optional by Itanium processors. The PAL procedure supports the Stacked
- Registers calling convention. It could be called at Virtual
- mode.
-
- @param Index Index of PAL_VP_INIT_ENV within the list of PAL
- procedures.
- @param ConfigOptions 64-bit vector of global configuration
- settings.
- @param PhysicalBase Host physical base address of a block of
- contiguous physical memory for the PAL
- virtual environment buffer 1) This
- memory area must be allocated by the VMM
- and be 4K aligned. The first logical
- processor to enter the environment will
- initialize the physical block for
- virtualization operations.
- @param VirtualBase Host virtual base address of the
- corresponding physical memory block for
- the PAL virtual environment buffer : The
- VMM must maintain the host virtual to host
- physical data and instruction translations
- in TRs for addresses within the allocated
- address space. Logical processors in this
- virtual environment will use this address
- when transitioning to virtual mode
- operations.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
- @return R9 Virtualization Service Address - VSA specifies
- the virtual base address of the PAL
- virtualization services in this virtual
- environment.
-
-
-**/
-#define PAL_VP_INIT_ENV 268
-
-
-/**
- PAL Procedure - PAL_VP_REGISTER.
-
- Register a different host IVT and/or a different optional
- virtualization intercept handler for the virtual processor
- specified by vpd. It is optional by Itanium processors. The PAL procedure
- supports the Stacked Registers calling convention. It could be
- called at Virtual mode.
-
- @param Index Index of PAL_VP_REGISTER within the list of PAL
- procedures.
- @param Vpd 64-bit host virtual pointer to the Virtual
- Processor Descriptor (VPD) host_iva 64-bit host
- virtual pointer to the host IVT for the virtual
- processor
- @param OptionalHandler 64-bit non-zero host-virtual pointer
- to an optional handler for
- virtualization intercepts.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_REGISTER 269
-
-
-/**
- PAL Procedure - PAL_VP_RESTORE.
-
- Restores virtual processor state for the specified vpd on the
- logical processor. It is optional by Itanium processors. The PAL procedure
- supports the Stacked Registers calling convention. It could be
- called at Virtual mode.
-
- @param Index Index of PAL_VP_RESTORE within the list of PAL
- procedures.
- @param Vpd 64-bit host virtual pointer to the Virtual
- Processor Descriptor (VPD) host_iva 64-bit host
- virtual pointer to the host IVT for the virtual
- processor
- @param PalVector Vector specifies PAL procedure
- implementation-specific state to be
- restored.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_RESTORE 270
-
-/**
- PAL Procedure - PAL_VP_SAVE.
-
- Saves virtual processor state for the specified vpd on the
- logical processor. It is optional by Itanium processors. The PAL procedure
- supports the Stacked Registers calling convention. It could be
- called at Virtual mode.
-
- @param Index Index of PAL_VP_SAVE within the list of PAL
- procedures.
- @param Vpd 64-bit host virtual pointer to the Virtual
- Processor Descriptor (VPD) host_iva 64-bit host
- virtual pointer to the host IVT for the virtual
- processor
- @param PalVector Vector specifies PAL procedure
- implementation-specific state to be
- restored.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_SAVE 271
-
-
-/**
- PAL Procedure - PAL_VP_TERMINATE.
-
- Terminates operation for the specified virtual processor. It
- is optional by Itanium processors. The PAL procedure supports the Stacked
- Registers calling convention. It could be called at Virtual
- mode.
-
- @param Index Index of PAL_VP_TERMINATE within the list of PAL
- procedures.
- @param Vpd 64-bit host virtual pointer to the Virtual
- Processor Descriptor (VPD)
- @param Iva Optional 64-bit host virtual pointer to the IVT
- when this procedure is done.
-
- @retval 0 Call completed without error
- @retval -1 Unimplemented procedure
- @retval -2 Invalid argument
- @retval -3 Call completed with error.
- @retval -9 Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_TERMINATE 272
-
-#endif
diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h
index e5954dbce7a5..ef5791ef568f 100644
--- a/MdePkg/Include/IndustryStandard/Pci.h
+++ b/MdePkg/Include/IndustryStandard/Pci.h
@@ -1,14 +1,8 @@
/** @file
Support for the latest PCI standard.
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 97f70e1d324f..69e15f7aa9d9 100644
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -5,17 +5,11 @@
PCI Local Bus Specification, 2.2
PCI-to-PCI Bridge Architecture Specification, Revision 1.2
PC Card Standard, 8.0
- PCI Power Management Interface Specifiction, Revision 1.2
+ PCI Power Management Interface Specification, Revision 1.2
- Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -116,12 +110,12 @@ typedef union {
PCI_TYPE01 Bridge;
} PCI_TYPE_GENERIC;
-///
-/// CardBus Conroller Configuration Space,
+///
+/// CardBus Controller Configuration Space,
/// Section 4.5.1, PC Card Standard. 8.0
///
typedef struct {
- UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base
+ UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base
UINT8 Cap_Ptr;
UINT8 Reserved;
UINT16 SecondaryStatus; ///< Secondary Status
@@ -158,7 +152,7 @@ typedef struct {
#define PCI_CLASS_MASS_STORAGE_OTHER 0x80
#define PCI_CLASS_NETWORK 0x02
-#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
#define PCI_CLASS_NETWORK_TOKENRING 0x01
#define PCI_CLASS_NETWORK_FDDI 0x02
#define PCI_CLASS_NETWORK_ATM 0x03
@@ -171,7 +165,7 @@ typedef struct {
#define PCI_IF_VGA_8514 0x01
#define PCI_CLASS_DISPLAY_XGA 0x01
#define PCI_CLASS_DISPLAY_3D 0x02
-#define PCI_CLASS_DISPLAY_OTHER 0x80
+#define PCI_CLASS_DISPLAY_OTHER 0x80
#define PCI_CLASS_MEDIA 0x04
#define PCI_CLASS_MEDIA_VIDEO 0x00
@@ -199,7 +193,7 @@ typedef struct {
#define PCI_CLASS_BRIDGE_OTHER 0x80
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
-#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
+#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
#define PCI_SUBCLASS_SERIAL 0x00
#define PCI_IF_GENERIC_XT 0x00
#define PCI_IF_16450 0x01
@@ -228,8 +222,8 @@ typedef struct {
#define PCI_IF_8259_PIC 0x00
#define PCI_IF_ISA_PIC 0x01
#define PCI_IF_EISA_PIC 0x02
-#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
-#define PCI_IF_APIC_CONTROLLER2 0x20
+#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.
+#define PCI_IF_APIC_CONTROLLER2 0x20
#define PCI_SUBCLASS_DMA 0x01
#define PCI_IF_8237_DMA 0x00
#define PCI_IF_ISA_DMA 0x01
@@ -297,25 +291,25 @@ typedef struct {
#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
#define PCI_SUBCLASS_NET_COMPUT 0x00
-#define PCI_SUBCLASS_ENTERTAINMENT 0x10
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10
#define PCI_SUBCLASS_SECURITY_OTHER 0x80
#define PCI_CLASS_DPIO 0x11
#define PCI_SUBCLASS_DPIO 0x00
#define PCI_SUBCLASS_DPIO_OTHER 0x80
-/**
+/**
Macro that checks whether the Base Class code of device matched.
@param _p Specified device.
@param c Base Class code needs matching.
@retval TRUE Base Class code matches the specified device.
- @retval FALSE Base Class code doesn't match the specified device.
+ @retval FALSE Base Class code doesn't match the specified device.
**/
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
-/**
+/**
Macro that checks whether the Base Class code and Sub-Class code of device matched.
@param _p Specified device.
@@ -323,11 +317,11 @@ typedef struct {
@param s Sub-Class code needs matching.
@retval TRUE Base Class code and Sub-Class code match the specified device.
- @retval FALSE Base Class code and Sub-Class code don't match the specified device.
+ @retval FALSE Base Class code and Sub-Class code don't match the specified device.
**/
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
-/**
+/**
Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
@param _p Specified device.
@@ -336,12 +330,12 @@ typedef struct {
@param p Interface code needs matching.
@retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
- @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
+ @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
**/
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
-/**
+/**
Macro that checks whether device is a display controller.
@param _p Specified device.
@@ -351,7 +345,7 @@ typedef struct {
**/
#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
-/**
+/**
Macro that checks whether device is a VGA-compatible controller.
@param _p Specified device.
@@ -361,7 +355,7 @@ typedef struct {
**/
#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
-/**
+/**
Macro that checks whether device is an 8514-compatible controller.
@param _p Specified device.
@@ -371,7 +365,7 @@ typedef struct {
**/
#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
-/**
+/**
Macro that checks whether device is built before the Class Code field was defined.
@param _p Specified device.
@@ -381,7 +375,7 @@ typedef struct {
**/
#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
-/**
+/**
Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
@param _p Specified device.
@@ -391,7 +385,7 @@ typedef struct {
**/
#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
-/**
+/**
Macro that checks whether device is an IDE controller.
@param _p Specified device.
@@ -401,7 +395,7 @@ typedef struct {
**/
#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
-/**
+/**
Macro that checks whether device is a SCSI bus controller.
@param _p Specified device.
@@ -411,7 +405,7 @@ typedef struct {
**/
#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
-/**
+/**
Macro that checks whether device is a RAID controller.
@param _p Specified device.
@@ -421,7 +415,7 @@ typedef struct {
**/
#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
-/**
+/**
Macro that checks whether device is an ISA bridge.
@param _p Specified device.
@@ -431,7 +425,7 @@ typedef struct {
**/
#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
-/**
+/**
Macro that checks whether device is a PCI-to-PCI bridge.
@param _p Specified device.
@@ -441,7 +435,7 @@ typedef struct {
**/
#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
-/**
+/**
Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
@param _p Specified device.
@@ -451,7 +445,7 @@ typedef struct {
**/
#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
-/**
+/**
Macro that checks whether device is a 16550-compatible serial controller.
@param _p Specified device.
@@ -461,7 +455,7 @@ typedef struct {
**/
#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
-/**
+/**
Macro that checks whether device is a Universal Serial Bus controller.
@param _p Specified device.
@@ -473,7 +467,7 @@ typedef struct {
#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
//
-// the definition of Header Type
+// the definition of Header Type
//
#define HEADER_TYPE_DEVICE 0x00
#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
@@ -483,7 +477,7 @@ typedef struct {
// Mask of Header type
//
#define HEADER_LAYOUT_CODE 0x7f
-/**
+/**
Macro that checks whether device is a PCI-PCI bridge.
@param _p Specified device.
@@ -493,7 +487,7 @@ typedef struct {
**/
#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
-/**
+/**
Macro that checks whether device is a CardBus bridge.
@param _p Specified device.
@@ -503,7 +497,7 @@ typedef struct {
**/
#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
-/**
+/**
Macro that checks whether device is a multiple functions device.
@param _p Specified device.
@@ -515,7 +509,7 @@ typedef struct {
#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
///
-/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
+/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,
///
#define PCI_BRIDGE_ROMBAR 0x38
@@ -548,17 +542,17 @@ typedef struct {
//
// defined in PCI-to-PCI Bridge Architecture Specification
//
-#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
-#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
-#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
-#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
-#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
///
/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
///
-#define PCI_INT_LINE_UNKNOWN 0xFF
+#define PCI_INT_LINE_UNKNOWN 0xFF
///
/// PCI Access Data Format
@@ -648,7 +642,7 @@ typedef struct {
///
/// PMC - Power Management Capabilities
-/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
+/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2
///
typedef union {
struct {
@@ -668,7 +662,7 @@ typedef union {
///
/// PMCSR - Power Management Control/Status
-/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2
+/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2
///
typedef union {
struct {
@@ -691,7 +685,7 @@ typedef union {
///
/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
-/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
+/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2
///
typedef union {
struct {
@@ -704,7 +698,7 @@ typedef union {
///
/// Power Management Register Block Definition
-/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
+/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
@@ -738,7 +732,7 @@ typedef struct {
///
/// Slot Numbering Capabilities Register
-/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
+/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2
///
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
@@ -770,7 +764,7 @@ typedef struct {
} EFI_PCI_CAPABILITY_MSI64;
///
-/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
///
typedef struct {
@@ -780,25 +774,6 @@ typedef struct {
///
} EFI_PCI_CAPABILITY_HOTPLUG;
-///
-/// Below macros (till PCI_BAR_NOCHANGE) were used by EfiIncompatiblePciDeviceSupport Protocol.
-///
-#ifndef DISABLE_NEW_DEPRECATED_INTERFACES
-
-///
-/// [ATTENTION] These macros are deprecated because they don't match Spec or not defined in Spec.
-///
-#define DEVICE_ID_NOCARE 0xFFFF ///< Deprecated. Value doesn't match Spec.
-#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL ///< Deprecated. Value isn't defined in Spec.
-#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL ///< Deprecated. Value isn't defined in Spec.
-#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL ///< Deprecated. Value isn't defined in Spec.
-#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL ///< Deprecated. Value isn't defined in Spec.
-#define PCI_BAR_ALL 0xFF ///< Deprecated. Value doesn't match Spec.
-#define PCI_ACPI_UNUSED 0 ///< Deprecated. Macro name is too general.
-#define PCI_BAR_NOCHANGE 0 ///< Deprecated. Macro name is too general.
-
-#endif
-
#define PCI_BAR_IDX0 0x00
#define PCI_BAR_IDX1 0x01
#define PCI_BAR_IDX2 0x02
@@ -808,8 +783,8 @@ typedef struct {
///
/// EFI PCI Option ROM definitions
-///
-#define EFI_ROOT_BRIDGE_LIST 'eprb'
+///
+#define EFI_ROOT_BRIDGE_LIST 'eprb'
#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
diff --git a/MdePkg/Include/IndustryStandard/Pci23.h b/MdePkg/Include/IndustryStandard/Pci23.h
index b4698ac2fbfa..0ce38eb867d9 100644
--- a/MdePkg/Include/IndustryStandard/Pci23.h
+++ b/MdePkg/Include/IndustryStandard/Pci23.h
@@ -1,14 +1,8 @@
/** @file
Support for PCI 2.3 standard.
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -92,10 +86,11 @@
/// PCI Capability List IDs and records.
///
#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
+#define EFI_PCI_CAPABILITY_ID_VENDOR 0x09
#pragma pack(1)
///
-/// PCI-X Capabilities List,
+/// PCI-X Capabilities List,
/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
///
typedef struct {
@@ -105,7 +100,7 @@ typedef struct {
} EFI_PCI_CAPABILITY_PCIX;
///
-/// PCI-X Bridge Capabilities List,
+/// PCI-X Bridge Capabilities List,
/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
///
typedef struct {
@@ -116,6 +111,15 @@ typedef struct {
UINT32 SplitTransCtrlRegDn;
} EFI_PCI_CAPABILITY_PCIX_BRDG;
+///
+/// Vendor Specific Capability Header
+/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ UINT8 Length;
+} EFI_PCI_CAPABILITY_VENDOR_HDR;
+
#pragma pack()
#define PCI_CODE_TYPE_EFI_IMAGE 0x03
diff --git a/MdePkg/Include/IndustryStandard/Pci30.h b/MdePkg/Include/IndustryStandard/Pci30.h
index 57bd5a4179d2..beefb1aeb438 100644
--- a/MdePkg/Include/IndustryStandard/Pci30.h
+++ b/MdePkg/Include/IndustryStandard/Pci30.h
@@ -1,14 +1,8 @@
/** @file
Support for PCI 3.0 standard.
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/PciCodeId.h b/MdePkg/Include/IndustryStandard/PciCodeId.h
index 31b6b8ec5d3a..e5b63c3f42d4 100644
--- a/MdePkg/Include/IndustryStandard/PciCodeId.h
+++ b/MdePkg/Include/IndustryStandard/PciCodeId.h
@@ -2,14 +2,8 @@
The file lists the PCI class codes only defined in PCI code and ID assignment specification
revision 1.3.
- Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index 61ec5542072f..4f1322310bea 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -1,15 +1,9 @@
/** @file
Support for the latest PCI standard.
- Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
- (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -18,6 +12,23 @@
#include <IndustryStandard/Pci30.h>
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
+ of Bus, Device, Function and Register are stripped prior to the generation of
+ the address.
+
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..4095.
+
+ @return The encode ECAM address.
+
+**/
+#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
+ (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
#pragma pack(1)
///
/// PCI Express Capability Structure
@@ -80,6 +91,24 @@ typedef union {
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL;
+#define PCIE_MAX_PAYLOAD_SIZE_128B 0
+#define PCIE_MAX_PAYLOAD_SIZE_256B 1
+#define PCIE_MAX_PAYLOAD_SIZE_512B 2
+#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
+#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
+#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
+
+#define PCIE_MAX_READ_REQ_SIZE_128B 0
+#define PCIE_MAX_READ_REQ_SIZE_256B 1
+#define PCIE_MAX_READ_REQ_SIZE_512B 2
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
+
typedef union {
struct {
UINT16 CorrectableError : 1;
@@ -165,18 +194,18 @@ typedef union {
typedef union {
struct {
- UINT32 AttentionButtonPressed : 1;
- UINT32 PowerFaultDetected : 1;
- UINT32 MrlSensorChanged : 1;
- UINT32 PresenceDetectChanged : 1;
- UINT32 CommandCompletedInterrupt : 1;
- UINT32 HotPlugInterrupt : 1;
- UINT32 AttentionIndicator : 2;
- UINT32 PowerIndicator : 2;
- UINT32 PowerController : 1;
- UINT32 ElectromechanicalInterlock : 1;
- UINT32 DataLinkLayerStateChanged : 1;
- UINT32 Reserved : 3;
+ UINT16 AttentionButtonPressed : 1;
+ UINT16 PowerFaultDetected : 1;
+ UINT16 MrlSensorChanged : 1;
+ UINT16 PresenceDetectChanged : 1;
+ UINT16 CommandCompletedInterrupt : 1;
+ UINT16 HotPlugInterrupt : 1;
+ UINT16 AttentionIndicator : 2;
+ UINT16 PowerIndicator : 2;
+ UINT16 PowerController : 1;
+ UINT16 ElectromechanicalInterlock : 1;
+ UINT16 DataLinkLayerStateChanged : 1;
+ UINT16 Reserved : 3;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
@@ -239,16 +268,30 @@ typedef union {
UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
- UINT32 Reserved : 4;
+ UINT32 LnSystemCLS : 2;
+ UINT32 TenBitTagCompleterSupported : 1;
+ UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
UINT32 ExtendedFmtField : 1;
UINT32 EndEndTlpPrefix : 1;
UINT32 MaxEndEndTlpPrefixes : 2;
- UINT32 Reserved2 : 8;
+ UINT32 EmergencyPowerReductionSupported : 2;
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY2;
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
+
#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
@@ -261,8 +304,9 @@ typedef union {
UINT16 AtomicOpEgressBlocking : 1;
UINT16 IdoRequest : 1;
UINT16 IdoCompletion : 1;
- UINT16 LtrMechanism : 2;
- UINT16 Reserved : 2;
+ UINT16 LtrMechanism : 1;
+ UINT16 EmergencyPowerReductionRequest : 1;
+ UINT16 TenBitTagRequesterEnable : 1;
UINT16 Obff : 2;
UINT16 EndEndTlpPrefixBlocking : 1;
} Bits;
diff --git a/MdePkg/Include/IndustryStandard/PciExpress30.h b/MdePkg/Include/IndustryStandard/PciExpress30.h
index 5ab7feb8d64f..2e52e0782af6 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress30.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress30.h
@@ -3,14 +3,8 @@
This header file may not define all structures. Please extend as required.
- Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/PciExpress31.h b/MdePkg/Include/IndustryStandard/PciExpress31.h
index 72a3ccda81ee..2e5e097be9db 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress31.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress31.h
@@ -4,13 +4,7 @@ Support for the PCI Express 3.1 standard.
This header file may not define all structures. Please extend as required.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
new file mode 100644
index 000000000000..a76f1bd5ae81
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -0,0 +1,111 @@
+/** @file
+Support for the PCI Express 4.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS40_H_
+#define _PCIEXPRESS40_H_
+
+#include <IndustryStandard/PciExpress31.h>
+
+#pragma pack(1)
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.5 of PCI Express Base Specification 4.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 Reserved : 27; // Reserved bit 5:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;
+ UINT32 LocalDataParityMismatchStatus;
+ UINT32 FirstRetimerDataParityMismatchStatus;
+ UINT32 SecondRetimerDataParityMismatchStatus;
+ UINT32 Reserved;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
+///@}
+
+/// The Designated Vendor Specific Capability definitions
+/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
+///@{
+typedef union {
+ struct {
+ UINT32 DvsecVendorId : 16; //bit 0..15
+ UINT32 DvsecRevision : 4; //bit 16..19
+ UINT32 DvsecLength : 12; //bit 20..31
+ }Bits;
+ UINT32 Uint32;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+
+typedef union {
+ struct {
+ UINT16 DvsecId : 16; //bit 0..15
+ }Bits;
+ UINT16 Uint16;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;
+ UINT8 DesignatedVendorSpecific[1];
+}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
+///@}
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Include/IndustryStandard/PciExpress50.h
new file mode 100644
index 000000000000..3765875869eb
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress50.h
@@ -0,0 +1,136 @@
+/** @file
+Support for the PCI Express 5.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS50_H_
+#define _PCIEXPRESS50_H_
+
+#include <IndustryStandard/PciExpress40.h>
+
+#pragma pack(1)
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.6 of PCI Express Base Specification 5.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
+
+typedef union {
+ struct {
+ UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0
+ UINT32 NoEqualizationNeededSupport : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageMode0Support : 1; // bit 8
+ UINT32 ModifiedTSUsageMode1Support : 1; // bit 9
+ UINT32 ModifiedTSUsageMode2Support : 1; // bit 10
+ UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15
+ UINT32 Reserved2 : 16; // Reserved bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0
+ UINT32 NoEqualizationNeededDisable : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10
+ UINT32 Reserved2 : 21; // Reserved bit 11:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 ModifiedTSRcvd : 1; // bit 5
+ UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7
+ UINT32 TransmitterPrecodingOn : 1; // bit 8
+ UINT32 TransmitterPrecodeRequest : 1; // bit 9
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 10
+ UINT32 Reserved : 21; // Reserved bit 11:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;
+
+typedef union {
+ struct {
+ UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;
+
+typedef union {
+ struct {
+ UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;
+
+typedef union {
+ struct {
+ UINT32 TransModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 TransModifiedTSVendorId : 16; // bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;
+
+typedef union {
+ struct {
+ UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;
+///@}
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
index 3af3edbd8ec2..15a713ea06e7 100644
--- a/MdePkg/Include/IndustryStandard/PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
@@ -1,21 +1,17 @@
/** @file
- EFI image format for PE32, PE32+ and TE. Please note some data structures are
- different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and
- EFI_IMAGE_NT_HEADERS64 is for PE32+.
+ EFI image format for PE32, PE32+ and TE. Please note some data structures are
+ different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and
+ EFI_IMAGE_NT_HEADERS64 is for PE32+.
- This file is coded to the Visual Studio, Microsoft Portable Executable and
+ This file is coded to the Visual Studio, Microsoft Portable Executable and
Common Object File Format Specification, Revision 8.3 - February 6, 2013.
This file also includes some definitions in PI Specification, Revision 1.0.
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
+Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -40,6 +36,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define IMAGE_FILE_MACHINE_X64 0x8664
#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2
#define IMAGE_FILE_MACHINE_ARM64 0xAA64
+#define IMAGE_FILE_MACHINE_RISCV32 0x5032
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064
+#define IMAGE_FILE_MACHINE_RISCV128 0x5128
//
// EXE file formats
@@ -98,7 +97,7 @@ typedef struct {
//
#define EFI_IMAGE_FILE_RELOCS_STRIPPED BIT0 ///< 0x0001 Relocation info stripped from file.
#define EFI_IMAGE_FILE_