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-rw-r--r--README.txt43
-rw-r--r--cvmip.h10
-rw-r--r--cvmx-abi.h30
-rw-r--r--cvmx-access-native.h17
-rw-r--r--cvmx-access.h6
-rw-r--r--cvmx-address.h19
-rw-r--r--cvmx-agl-defs.h1386
-rw-r--r--cvmx-app-hotplug.c639
-rw-r--r--cvmx-app-hotplug.h78
-rw-r--r--cvmx-app-init-linux.c22
-rw-r--r--cvmx-app-init.c127
-rw-r--r--cvmx-app-init.h102
-rw-r--r--cvmx-asm.h23
-rw-r--r--cvmx-asx0-defs.h31
-rw-r--r--cvmx-asxx-defs.h278
-rw-r--r--cvmx-atomic.h32
-rw-r--r--cvmx-bootloader.h15
-rw-r--r--cvmx-bootmem.c90
-rw-r--r--cvmx-bootmem.h65
-rw-r--r--cvmx-ciu-defs.h9174
-rw-r--r--cvmx-ciu2-defs.h10670
-rw-r--r--cvmx-clock.c11
-rw-r--r--cvmx-clock.h8
-rw-r--r--cvmx-cmd-queue.c13
-rw-r--r--cvmx-cmd-queue.h11
-rw-r--r--cvmx-cn3010-evb-hs5.c8
-rw-r--r--cvmx-cn3010-evb-hs5.h8
-rw-r--r--cvmx-compactflash.c6
-rw-r--r--cvmx-compactflash.h6
-rw-r--r--cvmx-core.c8
-rw-r--r--cvmx-core.h14
-rw-r--r--cvmx-coremask.c8
-rw-r--r--cvmx-coremask.h168
-rw-r--r--cvmx-crypto.c6
-rw-r--r--cvmx-crypto.h6
-rw-r--r--cvmx-csr-db-support.c28
-rw-r--r--cvmx-csr-db.c146488
-rw-r--r--cvmx-csr-db.h8
-rw-r--r--cvmx-csr-enums.h8
-rw-r--r--cvmx-csr-typedefs.h16
-rw-r--r--cvmx-csr.h8
-rw-r--r--cvmx-dbg-defs.h33
-rw-r--r--cvmx-debug-handler.S29
-rw-r--r--cvmx-debug-remote.c9
-rw-r--r--cvmx-debug-uart.c68
-rw-r--r--cvmx-debug.c534
-rw-r--r--cvmx-debug.h13
-rw-r--r--cvmx-dfa-defs.h1406
-rw-r--r--cvmx-dfa.c8
-rw-r--r--cvmx-dfa.h12
-rw-r--r--cvmx-dfm-defs.h490
-rw-r--r--cvmx-dma-engine.c50
-rw-r--r--cvmx-dma-engine.h56
-rw-r--r--cvmx-dpi-defs.h1160
-rw-r--r--cvmx-ebt3000.c8
-rw-r--r--cvmx-ebt3000.h8
-rw-r--r--cvmx-endor-defs.h7826
-rw-r--r--cvmx-eoi-defs.h689
-rw-r--r--cvmx-error-custom.c297
-rw-r--r--cvmx-error-custom.h7
-rw-r--r--cvmx-error-init-cn30xx.c6
-rw-r--r--cvmx-error-init-cn31xx.c6
-rw-r--r--cvmx-error-init-cn38xx.c6
-rw-r--r--cvmx-error-init-cn38xxp2.c6
-rw-r--r--cvmx-error-init-cn50xx.c6
-rw-r--r--cvmx-error-init-cn52xx.c58
-rw-r--r--cvmx-error-init-cn52xxp1.c58
-rw-r--r--cvmx-error-init-cn56xx.c42
-rw-r--r--cvmx-error-init-cn56xxp1.c42
-rw-r--r--cvmx-error-init-cn58xx.c6
-rw-r--r--cvmx-error-init-cn58xxp1.c6
-rw-r--r--cvmx-error-init-cn61xx.c9130
-rw-r--r--cvmx-error-init-cn63xx.c204
-rw-r--r--cvmx-error-init-cn63xxp1.c28
-rw-r--r--cvmx-error-init-cn66xx.c9164
-rw-r--r--cvmx-error-init-cn68xx.c14043
-rw-r--r--cvmx-error-init-cn68xxp1.c14005
-rw-r--r--cvmx-error-init-cnf71xx.c5782
-rw-r--r--cvmx-error.c144
-rw-r--r--cvmx-error.h18
-rw-r--r--cvmx-fau.h8
-rw-r--r--cvmx-flash.c8
-rw-r--r--cvmx-flash.h8
-rw-r--r--cvmx-fpa-defs.h1500
-rw-r--r--cvmx-fpa.c8
-rw-r--r--cvmx-fpa.h30
-rw-r--r--cvmx-gmx.h8
-rw-r--r--cvmx-gmxx-defs.h6600
-rw-r--r--cvmx-gpio-defs.h466
-rw-r--r--cvmx-gpio.h71
-rw-r--r--cvmx-helper-board.c833
-rw-r--r--cvmx-helper-board.h13
-rw-r--r--cvmx-helper-cfg.c715
-rw-r--r--cvmx-helper-cfg.h282
-rw-r--r--cvmx-helper-check-defines.h8
-rw-r--r--cvmx-helper-errata.c16
-rw-r--r--cvmx-helper-errata.h8
-rw-r--r--cvmx-helper-fpa.c8
-rw-r--r--cvmx-helper-fpa.h8
-rw-r--r--cvmx-helper-ilk.c440
-rw-r--r--cvmx-helper-ilk.h110
-rw-r--r--cvmx-helper-jtag.c23
-rw-r--r--cvmx-helper-jtag.h6
-rw-r--r--cvmx-helper-loop.c68
-rw-r--r--cvmx-helper-loop.h9
-rw-r--r--cvmx-helper-npi.c64
-rw-r--r--cvmx-helper-npi.h12
-rw-r--r--cvmx-helper-rgmii.c9
-rw-r--r--cvmx-helper-rgmii.h12
-rw-r--r--cvmx-helper-sgmii.c197
-rw-r--r--cvmx-helper-sgmii.h9
-rw-r--r--cvmx-helper-spi.c52
-rw-r--r--cvmx-helper-spi.h9
-rw-r--r--cvmx-helper-srio.c65
-rw-r--r--cvmx-helper-srio.h10
-rw-r--r--cvmx-helper-util.c529
-rw-r--r--cvmx-helper-util.h137
-rw-r--r--cvmx-helper-xaui.c202
-rw-r--r--cvmx-helper-xaui.h9
-rw-r--r--cvmx-helper.c818
-rw-r--r--cvmx-helper.h111
-rw-r--r--cvmx-hfa.c174
-rw-r--r--cvmx-hfa.h437
-rw-r--r--cvmx-higig.h122
-rw-r--r--cvmx-ilk-defs.h3529
-rw-r--r--cvmx-ilk.c1396
-rw-r--r--cvmx-ilk.h183
-rw-r--r--cvmx-interrupt-handler.S15
-rw-r--r--cvmx-interrupt.c983
-rw-r--r--cvmx-interrupt.h293
-rw-r--r--cvmx-iob-defs.h1016
-rw-r--r--cvmx-iob1-defs.h184
-rw-r--r--cvmx-ipd-defs.h1682
-rw-r--r--cvmx-ipd.c314
-rw-r--r--cvmx-ipd.h147
-rw-r--r--cvmx-ixf18201.c6
-rw-r--r--cvmx-ixf18201.h6
-rw-r--r--cvmx-key-defs.h70
-rw-r--r--cvmx-key.h8
-rw-r--r--cvmx-l2c-defs.h1952
-rw-r--r--cvmx-l2c.c1654
-rw-r--r--cvmx-l2c.h362
-rw-r--r--cvmx-l2d-defs.h166
-rw-r--r--cvmx-l2t-defs.h43
-rw-r--r--cvmx-led-defs.h114
-rw-r--r--cvmx-llm.c33
-rw-r--r--cvmx-llm.h8
-rw-r--r--cvmx-lmcx-defs.h2744
-rw-r--r--cvmx-log-arc.S6
-rw-r--r--cvmx-log.c8
-rw-r--r--cvmx-log.h14
-rw-r--r--cvmx-malloc.h8
-rw-r--r--cvmx-malloc/README-malloc12
-rw-r--r--cvmx-malloc/arena.c293
-rw-r--r--cvmx-malloc/malloc.c4106
-rw-r--r--cvmx-malloc/malloc.h213
-rw-r--r--cvmx-malloc/thread-m.h73
-rw-r--r--cvmx-mdio.h14
-rw-r--r--cvmx-mgmt-port.c15
-rw-r--r--cvmx-mgmt-port.h8
-rw-r--r--cvmx-mio-defs.h4509
-rw-r--r--cvmx-mixx-defs.h357
-rw-r--r--cvmx-mpi-defs.h345
-rw-r--r--cvmx-nand.c81
-rw-r--r--cvmx-nand.h7
-rw-r--r--cvmx-ndf-defs.h119
-rw-r--r--cvmx-npei-defs.h983
-rw-r--r--cvmx-npi-defs.h414
-rw-r--r--cvmx-npi.h16
-rw-r--r--cvmx-packet.h8
-rw-r--r--cvmx-pci-defs.h537
-rw-r--r--cvmx-pci.h8
-rw-r--r--cvmx-pcie.c145
-rw-r--r--cvmx-pcie.h8
-rw-r--r--cvmx-pcieepx-defs.h2891
-rw-r--r--cvmx-pciercx-defs.h2538
-rw-r--r--cvmx-pcm-defs.h80
-rw-r--r--cvmx-pcmx-defs.h494
-rw-r--r--cvmx-pcsx-defs.h802
-rw-r--r--cvmx-pcsxx-defs.h645
-rw-r--r--cvmx-pemx-defs.h504
-rw-r--r--cvmx-pescx-defs.h163
-rw-r--r--cvmx-pexp-defs.h317
-rw-r--r--cvmx-pip-defs.h3075
-rw-r--r--cvmx-pip.h454
-rw-r--r--cvmx-pko-defs.h2265
-rw-r--r--cvmx-pko.c776
-rw-r--r--cvmx-pko.h385
-rw-r--r--cvmx-platform.h11
-rw-r--r--cvmx-pow-defs.h598
-rw-r--r--cvmx-pow.c383
-rw-r--r--cvmx-pow.h843
-rw-r--r--cvmx-power-throttle.c236
-rw-r--r--cvmx-power-throttle.h121
-rw-r--r--cvmx-profiler.c237
-rw-r--r--cvmx-profiler.h103
-rw-r--r--cvmx-qlm-tables.c440
-rw-r--r--cvmx-qlm.c732
-rw-r--r--cvmx-qlm.h165
-rw-r--r--cvmx-rad-defs.h355
-rw-r--r--cvmx-raid.c28
-rw-r--r--cvmx-raid.h12
-rw-r--r--cvmx-resources.config197
-rw-r--r--cvmx-rng.h9
-rw-r--r--cvmx-rnm-defs.h124
-rw-r--r--cvmx-rtc.h8
-rw-r--r--cvmx-rwlock.h8
-rw-r--r--cvmx-scratch.h8
-rw-r--r--cvmx-shared-linux-n32.ld307
-rw-r--r--cvmx-shared-linux-o32.ld279
-rw-r--r--cvmx-shared-linux.ld306
-rw-r--r--cvmx-shmem.c6
-rw-r--r--cvmx-shmem.h6
-rw-r--r--cvmx-sim-magic.h10
-rw-r--r--cvmx-sli-defs.h3323
-rw-r--r--cvmx-smi-defs.h25
-rw-r--r--cvmx-smix-defs.h275
-rw-r--r--cvmx-spi.c8
-rw-r--r--cvmx-spi.h8
-rw-r--r--cvmx-spi4000.c8
-rw-r--r--cvmx-spinlock.h8
-rw-r--r--cvmx-spx0-defs.h26
-rw-r--r--cvmx-spxx-defs.h160
-rw-r--r--cvmx-srio.c907
-rw-r--r--cvmx-srio.h42
-rw-r--r--cvmx-sriomaintx-defs.h1329
-rw-r--r--cvmx-sriox-defs.h1307
-rw-r--r--cvmx-srxx-defs.h58
-rw-r--r--cvmx-sso-defs.h2194
-rw-r--r--cvmx-stxx-defs.h138
-rw-r--r--cvmx-swap.h8
-rw-r--r--cvmx-sysinfo.c38
-rw-r--r--cvmx-sysinfo.h22
-rw-r--r--cvmx-thunder.c8
-rw-r--r--cvmx-thunder.h8
-rw-r--r--cvmx-tim-defs.h1002
-rw-r--r--cvmx-tim.c116
-rw-r--r--cvmx-tim.h13
-rw-r--r--cvmx-tlb.c98
-rw-r--r--cvmx-tlb.h101
-rw-r--r--cvmx-tra-defs.h3174
-rw-r--r--cvmx-tra.c386
-rw-r--r--cvmx-tra.h146
-rw-r--r--cvmx-trax-defs.h3590
-rw-r--r--cvmx-twsi.c87
-rw-r--r--cvmx-twsi.h8
-rw-r--r--cvmx-uahcx-defs.h791
-rw-r--r--cvmx-uart.c11
-rw-r--r--cvmx-uart.h8
-rw-r--r--cvmx-uctlx-defs.h297
-rw-r--r--cvmx-usb.c8
-rw-r--r--cvmx-usb.h6
-rw-r--r--cvmx-usbcx-defs.h431
-rw-r--r--cvmx-usbd.c6
-rw-r--r--cvmx-usbd.h6
-rw-r--r--cvmx-usbnx-defs.h234
-rw-r--r--cvmx-utils.h86
-rw-r--r--cvmx-version.h10
-rw-r--r--cvmx-warn.c14
-rw-r--r--cvmx-warn.h10
-rw-r--r--cvmx-wqe.h513
-rw-r--r--cvmx-zip-defs.h901
-rw-r--r--cvmx-zip.c113
-rw-r--r--cvmx-zip.h60
-rw-r--r--cvmx-zone.c8
-rw-r--r--cvmx.h10
-rw-r--r--cvmx.mk187
-rw-r--r--executive-config.h.template184
-rw-r--r--libfdt/fdt.c201
-rw-r--r--libfdt/fdt.h60
-rw-r--r--libfdt/fdt_ro.c469
-rw-r--r--libfdt/fdt_rw.c463
-rw-r--r--libfdt/fdt_strerror.c96
-rw-r--r--libfdt/fdt_sw.c257
-rw-r--r--libfdt/fdt_wip.c145
-rw-r--r--libfdt/libfdt.h1076
-rw-r--r--libfdt/libfdt.mk88
-rw-r--r--libfdt/libfdt_env.h23
-rw-r--r--libfdt/libfdt_internal.h95
-rw-r--r--octeon-boot-info.h95
-rw-r--r--octeon-feature.c146
-rw-r--r--octeon-feature.h165
-rw-r--r--octeon-model.c119
-rw-r--r--octeon-model.h68
-rw-r--r--octeon-pci-console.c34
-rw-r--r--octeon-pci-console.h6
286 files changed, 293873 insertions, 31773 deletions
diff --git a/README.txt b/README.txt
new file mode 100644
index 000000000000..fc83b72784c6
--- /dev/null
+++ b/README.txt
@@ -0,0 +1,43 @@
+Readme for the OCTEON Executive Library
+
+
+The OCTEON Executive Library provides runtime support and hardware
+abstraction for the OCTEON processor. The executive is composed of the
+libcvmx.a library as well as header files that provide
+functionality with inline functions.
+
+
+Usage:
+
+The libcvmx.a library is built for every application as part of the
+application build. (Please refer to the 'related pages' section of the
+HTML documentation for more information on the build system.)
+Applications using the executive should include the header files from
+$OCTEON_ROOT/target/include and link against the library that is built in
+the local obj directory. Each file using the executive
+should include the following two header files in order:
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+
+The cvmx-config.h file contains configuration information for the
+executive and is generated by the cvmx-config script from an
+'executive-config.h' file. A sample version of this file is provided
+in the executive directory as 'executive-config.h.template'.
+
+Copy this file to 'executive-config.h' into the 'config' subdirectory
+of the application directory and customize as required by the application.
+Applications that don't use any simple executive functionality can omit
+the cvmx-config.h header file. Please refer to the examples for a
+demonstration of where to put the executive-config.h file and for an
+example of generated cvmx-config.h.
+
+For file specific information please see the documentation within the
+source files or the HTML documentation provided in docs/html/index.html.
+The HTML documentation is automatically generated by Doxygen from the
+source files.
+
+
+
+==========================================================================
+Please see the release notes for version specific information.
diff --git a/cvmip.h b/cvmip.h
index b3aa6b0ef97a..4bcaaa66aa8f 100644
--- a/cvmip.h
+++ b/cvmip.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,11 +46,11 @@
/**
* @file
*
- * Cavium Networks Internet Protocol (IP)
+ * Cavium Inc. Internet Protocol (IP)
*
* Definitions for the Internet Protocol (IP) support.
*
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*
*/
diff --git a/cvmx-abi.h b/cvmx-abi.h
index 93d71b3b6303..f3ca4a2a80bf 100644
--- a/cvmx-abi.h
+++ b/cvmx-abi.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -39,21 +39,21 @@
-
-
-
-
/**
* @file
*
* This file defines macros for use in determining the current calling ABI.
*
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*/
#ifndef __CVMX_ABI_H__
#define __CVMX_ABI_H__
+#ifndef __U_BOOT__
+#include <endian.h>
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -87,6 +87,20 @@ extern "C" {
#endif
#endif
+/* For compatibility with Linux definitions... */
+#if __BYTE_ORDER == __BIG_ENDIAN
+# ifndef __BIG_ENDIAN_BITFIELD
+# define __BIG_ENDIAN_BITFIELD
+# endif
+#else
+# ifndef __LITTLE_ENDIAN_BITFIELD
+# define __LITTLE_ENDIAN_BITFIELD
+# endif
+#endif
+#if defined(__BIG_ENDIAN_BITFIELD) && defined(__LITTLE_ENDIAN_BITFIELD)
+# error Cannot define both __BIG_ENDIAN_BITFIELD and __LITTLE_ENDIAN_BITFIELD
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/cvmx-access-native.h b/cvmx-access-native.h
index 212b7c7af441..d137378309d8 100644
--- a/cvmx-access-native.h
+++ b/cvmx-access-native.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -181,12 +181,6 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
#ifdef CVMX_BUILD_FOR_UBOOT
-#if !CONFIG_OCTEON_UBOOT_TLB
- if (physical_address >= 0x80000000)
- return NULL;
- else
- return CASTPTR(void, (physical_address & 0x7FFFFFFF));
-#endif
/* U-boot is a special case, as it is running in 32 bit mode, using the TLB to map code/data
** which can have a physical address above the 32 bit address space. 1-1 mappings are used
@@ -249,8 +243,9 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
- else if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && (physical_address >= 0x410000000ull) &&
- (physical_address < 0x420000000ull))
+ else if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
+ && (physical_address >= 0x410000000ull)
+ && (physical_address < 0x420000000ull))
return CASTPTR(void, physical_address - 0x400000000ull);
else
return CASTPTR(void, physical_address);
diff --git a/cvmx-access.h b/cvmx-access.h
index c1206ddd39c1..43190f695d1c 100644
--- a/cvmx-access.h
+++ b/cvmx-access.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
diff --git a/cvmx-address.h b/cvmx-address.h
index daaf6a4cc5c0..d59c41dbf6ec 100644
--- a/cvmx-address.h
+++ b/cvmx-address.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,6 +47,10 @@
#ifndef __CVMX_ADDRESS_H__
#define __CVMX_ADDRESS_H__
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#include "cvmx-abi.h"
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -233,6 +237,7 @@ typedef union {
#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
+#define CVMX_OCT_DID_TAG_TAG5 CVMX_FULL_DID(CVMX_OCT_DID_TAG,5ULL)
#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
@@ -245,6 +250,14 @@ typedef union {
#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+#ifdef CVMX_ABI_N32
+#define UNMAPPED_PTR(x) ( (1U << 31) | x )
+#else
+#define UNMAPPED_PTR(x) ( (1ULL << 63) | x )
+#endif
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/cvmx-agl-defs.h b/cvmx-agl-defs.h
index 2138f90a19fd..13afef3fc963 100644
--- a/cvmx-agl-defs.h
+++ b/cvmx-agl-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,14 +49,14 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_AGL_TYPEDEFS_H__
-#define __CVMX_AGL_TYPEDEFS_H__
+#ifndef __CVMX_AGL_DEFS_H__
+#define __CVMX_AGL_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
}
@@ -67,7 +67,7 @@ static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
#define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
}
@@ -102,7 +102,10 @@ static inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048;
}
@@ -115,7 +118,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048;
}
@@ -128,7 +134,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048;
}
@@ -141,7 +150,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048;
}
@@ -154,7 +166,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048;
}
@@ -167,7 +182,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048;
}
@@ -180,7 +198,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048;
}
@@ -193,7 +214,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048;
}
@@ -206,7 +230,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048;
}
@@ -219,7 +246,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048;
}
@@ -232,7 +262,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048;
}
@@ -245,7 +278,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048;
}
@@ -258,7 +294,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048;
}
@@ -271,7 +310,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048;
}
@@ -284,7 +326,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048;
}
@@ -297,7 +342,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048;
}
@@ -310,7 +358,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048;
}
@@ -323,7 +374,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048;
}
@@ -336,7 +390,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048;
}
@@ -347,7 +404,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
static inline uint64_t CVMX_AGL_GMX_RXX_RX_INBND(unsigned long offset)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_RX_INBND(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048;
}
@@ -360,7 +420,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048;
}
@@ -373,7 +436,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048;
}
@@ -386,7 +452,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048;
}
@@ -399,7 +468,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048;
}
@@ -412,7 +484,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048;
}
@@ -425,7 +500,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048;
}
@@ -438,7 +516,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048;
}
@@ -451,7 +532,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048;
}
@@ -464,7 +548,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048;
}
@@ -477,7 +564,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048;
}
@@ -490,7 +580,10 @@ static inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048;
}
@@ -503,7 +596,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8;
}
@@ -516,7 +612,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8;
}
@@ -529,7 +628,10 @@ static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8;
}
@@ -540,7 +642,7 @@ static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
#define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
}
@@ -551,7 +653,7 @@ static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
#define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
}
@@ -564,7 +666,10 @@ static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048;
}
@@ -575,7 +680,7 @@ static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
#define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
}
@@ -588,7 +693,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048;
}
@@ -599,7 +707,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
static inline uint64_t CVMX_AGL_GMX_TXX_CLK(unsigned long offset)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_CLK(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048;
}
@@ -612,7 +723,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048;
}
@@ -625,7 +739,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048;
}
@@ -638,7 +755,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048;
}
@@ -651,7 +771,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048;
}
@@ -664,7 +787,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048;
}
@@ -677,7 +803,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048;
}
@@ -690,7 +819,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048;
}
@@ -703,7 +835,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048;
}
@@ -716,7 +851,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048;
}
@@ -729,7 +867,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048;
}
@@ -742,7 +883,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048;
}
@@ -755,7 +899,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048;
}
@@ -768,7 +915,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048;
}
@@ -781,7 +931,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048;
}
@@ -794,7 +947,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048;
}
@@ -807,7 +963,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048;
}
@@ -820,7 +979,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048;
}
@@ -833,7 +995,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048;
}
@@ -846,7 +1011,10 @@ static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
if (!(
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048;
}
@@ -857,7 +1025,7 @@ static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
#define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00004D0ull);
}
@@ -868,7 +1036,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
#define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000498ull);
}
@@ -879,7 +1047,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
#define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000488ull);
}
@@ -890,7 +1058,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
#define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000508ull);
}
@@ -901,7 +1069,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
#define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000500ull);
}
@@ -912,7 +1080,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
#define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E0000490ull);
}
@@ -923,7 +1091,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
#define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00004F8ull);
}
@@ -934,7 +1102,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
#define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00004C8ull);
}
@@ -945,7 +1113,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00004A0ull);
}
@@ -956,7 +1124,7 @@ static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC()
static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00011800E00004A8ull);
}
@@ -967,7 +1135,10 @@ static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
static inline uint64_t CVMX_AGL_PRTX_CTL(unsigned long offset)
{
if (!(
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
cvmx_warn("CVMX_AGL_PRTX_CTL(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8;
}
@@ -986,12 +1157,10 @@ static inline uint64_t CVMX_AGL_PRTX_CTL(unsigned long offset)
* OUT_OVR[1], LOSTSTAT[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1.
* STATOVR will be reset when both MIX0/1_CTL[RESET] are set to 1.
*/
-union cvmx_agl_gmx_bad_reg
-{
+union cvmx_agl_gmx_bad_reg {
uint64_t u64;
- struct cvmx_agl_gmx_bad_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_bad_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_38_63 : 26;
uint64_t txpsh1 : 1; /**< TX FIFO overflow (MII1) */
uint64_t txpop1 : 1; /**< TX FIFO underflow (MII1) */
@@ -1025,9 +1194,8 @@ union cvmx_agl_gmx_bad_reg
uint64_t reserved_38_63 : 26;
#endif
} s;
- struct cvmx_agl_gmx_bad_reg_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_bad_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_38_63 : 26;
uint64_t txpsh1 : 1; /**< TX FIFO overflow (MII1) */
uint64_t txpop1 : 1; /**< TX FIFO underflow (MII1) */
@@ -1061,9 +1229,8 @@ union cvmx_agl_gmx_bad_reg
#endif
} cn52xx;
struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_bad_reg_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_bad_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_35_63 : 29;
uint64_t txpsh : 1; /**< TX FIFO overflow */
uint64_t txpop : 1; /**< TX FIFO underflow */
@@ -1091,8 +1258,12 @@ union cvmx_agl_gmx_bad_reg
#endif
} cn56xx;
struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_bad_reg_s cn61xx;
struct cvmx_agl_gmx_bad_reg_s cn63xx;
struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
+ struct cvmx_agl_gmx_bad_reg_s cn66xx;
+ struct cvmx_agl_gmx_bad_reg_s cn68xx;
+ struct cvmx_agl_gmx_bad_reg_s cn68xxp1;
};
typedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t;
@@ -1106,12 +1277,10 @@ typedef union cvmx_agl_gmx_bad_reg cvmx_agl_gmx_bad_reg_t;
* Not reset when MIX*_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_bist
-{
+union cvmx_agl_gmx_bist {
uint64_t u64;
- struct cvmx_agl_gmx_bist_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63 : 39;
uint64_t status : 25; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -1131,8 +1300,8 @@ union cvmx_agl_gmx_bist
- 13: gmx#.outb.fif.fif_bnk_ext1
- 14: RAZ
- 15: RAZ
- - 16: gmx#.csr.gmi0.srf8x64m1_bist
- - 17: gmx#.csr.gmi1.srf8x64m1_bist
+ - 16: RAZ
+ - 17: RAZ
- 18: RAZ
- 19: RAZ
- 20: gmx#.csr.drf20x32m2_bist
@@ -1145,9 +1314,8 @@ union cvmx_agl_gmx_bist
uint64_t reserved_25_63 : 39;
#endif
} s;
- struct cvmx_agl_gmx_bist_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t status : 10; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -1169,8 +1337,12 @@ union cvmx_agl_gmx_bist
struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
struct cvmx_agl_gmx_bist_cn52xx cn56xx;
struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_bist_s cn61xx;
struct cvmx_agl_gmx_bist_s cn63xx;
struct cvmx_agl_gmx_bist_s cn63xxp1;
+ struct cvmx_agl_gmx_bist_s cn66xx;
+ struct cvmx_agl_gmx_bist_s cn68xx;
+ struct cvmx_agl_gmx_bist_s cn68xxp1;
};
typedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t;
@@ -1184,12 +1356,10 @@ typedef union cvmx_agl_gmx_bist cvmx_agl_gmx_bist_t;
* NCTL, PCTL, BYP_EN will be reset when MIX0_CTL[RESET] is set to 1.
* NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_drv_ctl
-{
+union cvmx_agl_gmx_drv_ctl {
uint64_t u64;
- struct cvmx_agl_gmx_drv_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_drv_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_49_63 : 15;
uint64_t byp_en1 : 1; /**< Compensation Controller Bypass Enable (MII1) */
uint64_t reserved_45_47 : 3;
@@ -1219,9 +1389,8 @@ union cvmx_agl_gmx_drv_ctl
} s;
struct cvmx_agl_gmx_drv_ctl_s cn52xx;
struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_drv_ctl_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_drv_ctl_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63 : 47;
uint64_t byp_en : 1; /**< Compensation Controller Bypass Enable */
uint64_t reserved_13_15 : 3;
@@ -1251,12 +1420,10 @@ typedef union cvmx_agl_gmx_drv_ctl cvmx_agl_gmx_drv_ctl_t;
* Not reset when MIX*_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_inf_mode
-{
+union cvmx_agl_gmx_inf_mode {
uint64_t u64;
- struct cvmx_agl_gmx_inf_mode_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_inf_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t en : 1; /**< Interface Enable */
uint64_t reserved_0_0 : 1;
@@ -1283,12 +1450,10 @@ typedef union cvmx_agl_gmx_inf_mode cvmx_agl_gmx_inf_mode_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_prtx_cfg
-{
+union cvmx_agl_gmx_prtx_cfg {
uint64_t u64;
- struct cvmx_agl_gmx_prtx_cfg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_prtx_cfg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63 : 50;
uint64_t tx_idle : 1; /**< TX Machine is idle */
uint64_t rx_idle : 1; /**< RX Machine is idle */
@@ -1346,9 +1511,8 @@ union cvmx_agl_gmx_prtx_cfg
uint64_t reserved_14_63 : 50;
#endif
} s;
- struct cvmx_agl_gmx_prtx_cfg_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t tx_en : 1; /**< Port enable. Must be set for Octane to send
RMGII traffic. When this bit clear on a given
@@ -1388,8 +1552,12 @@ union cvmx_agl_gmx_prtx_cfg
struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_s cn61xx;
struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_s cn66xx;
+ struct cvmx_agl_gmx_prtx_cfg_s cn68xx;
+ struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1;
};
typedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t;
@@ -1403,16 +1571,12 @@ typedef union cvmx_agl_gmx_prtx_cfg cvmx_agl_gmx_prtx_cfg_t;
* Not reset when MIX*_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_adr_cam0
-{
+union cvmx_agl_gmx_rxx_adr_cam0 {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_adr_cam0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_adr_cam0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to AGL_GMX_RX_ADR_CAM will not
- change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses. */
#else
@@ -1423,8 +1587,12 @@ union cvmx_agl_gmx_rxx_adr_cam0
struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx;
struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t;
@@ -1438,16 +1606,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam0 cvmx_agl_gmx_rxx_adr_cam0_t;
* Not reset when MIX*_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_adr_cam1
-{
+union cvmx_agl_gmx_rxx_adr_cam1 {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_adr_cam1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_adr_cam1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to AGL_GMX_RX_ADR_CAM will not
- change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses. */
#else
@@ -1458,8 +1622,12 @@ union cvmx_agl_gmx_rxx_adr_cam1
struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx;
struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t;
@@ -1473,16 +1641,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam1 cvmx_agl_gmx_rxx_adr_cam1_t;
* Not reset when MIX*_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_adr_cam2
-{
+union cvmx_agl_gmx_rxx_adr_cam2 {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_adr_cam2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_adr_cam2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to AGL_GMX_RX_ADR_CAM will not
- change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses. */
#else
@@ -1493,8 +1657,12 @@ union cvmx_agl_gmx_rxx_adr_cam2
struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx;
struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t;
@@ -1508,16 +1676,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam2 cvmx_agl_gmx_rxx_adr_cam2_t;
* Not reset when MIX*_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_adr_cam3
-{
+union cvmx_agl_gmx_rxx_adr_cam3 {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_adr_cam3_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_adr_cam3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to AGL_GMX_RX_ADR_CAM will not
- change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses. */
#else
@@ -1528,8 +1692,12 @@ union cvmx_agl_gmx_rxx_adr_cam3
struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx;
struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t;
@@ -1543,16 +1711,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam3 cvmx_agl_gmx_rxx_adr_cam3_t;
* Not reset when MIX*_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_adr_cam4
-{
+union cvmx_agl_gmx_rxx_adr_cam4 {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_adr_cam4_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_adr_cam4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to AGL_GMX_RX_ADR_CAM will not
- change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses. */
#else
@@ -1563,8 +1727,12 @@ union cvmx_agl_gmx_rxx_adr_cam4
struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx;
struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t;
@@ -1578,16 +1746,12 @@ typedef union cvmx_agl_gmx_rxx_adr_cam4 cvmx_agl_gmx_rxx_adr_cam4_t;
* Not reset when MIX*_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_adr_cam5
-{
+union cvmx_agl_gmx_rxx_adr_cam5 {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_adr_cam5_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_adr_cam5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t adr : 64; /**< The DMAC address to match on
- Each entry contributes 8bits to one of 8 matchers
- Write transactions to AGL_GMX_RX_ADR_CAM will not
- change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+ Each entry contributes 8bits to one of 8 matchers.
The CAM matches against unicst or multicst DMAC
addresses. */
#else
@@ -1598,8 +1762,12 @@ union cvmx_agl_gmx_rxx_adr_cam5
struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx;
struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t;
@@ -1613,12 +1781,10 @@ typedef union cvmx_agl_gmx_rxx_adr_cam5 cvmx_agl_gmx_rxx_adr_cam5_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_adr_cam_en
-{
+union cvmx_agl_gmx_rxx_adr_cam_en {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t en : 8; /**< CAM Entry Enables */
#else
@@ -1630,8 +1796,12 @@ union cvmx_agl_gmx_rxx_adr_cam_en
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx;
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t;
@@ -1679,12 +1849,10 @@ typedef union cvmx_agl_gmx_rxx_adr_cam_en cvmx_agl_gmx_rxx_adr_cam_en_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_adr_ctl
-{
+union cvmx_agl_gmx_rxx_adr_ctl {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_adr_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_adr_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t cam_mode : 1; /**< Allow or deny DMAC address filter
0 = reject the packet on DMAC address match
@@ -1706,8 +1874,12 @@ union cvmx_agl_gmx_rxx_adr_ctl
struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx;
struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t;
@@ -1740,12 +1912,10 @@ typedef union cvmx_agl_gmx_rxx_adr_ctl cvmx_agl_gmx_rxx_adr_ctl_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_decision
-{
+union cvmx_agl_gmx_rxx_decision {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_decision_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_decision_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t cnt : 5; /**< The byte count to decide when to accept or filter
a packet. */
@@ -1758,8 +1928,12 @@ union cvmx_agl_gmx_rxx_decision
struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
struct cvmx_agl_gmx_rxx_decision_s cn56xx;
struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_decision_s cn61xx;
struct cvmx_agl_gmx_rxx_decision_s cn63xx;
struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_decision_s cn66xx;
+ struct cvmx_agl_gmx_rxx_decision_s cn68xx;
+ struct cvmx_agl_gmx_rxx_decision_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t;
@@ -1774,12 +1948,10 @@ typedef union cvmx_agl_gmx_rxx_decision cvmx_agl_gmx_rxx_decision_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_frm_chk
-{
+union cvmx_agl_gmx_rxx_frm_chk {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_frm_chk_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_frm_chk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t niberr : 1; /**< Nibble error */
uint64_t skperr : 1; /**< Skipper error */
@@ -1805,9 +1977,8 @@ union cvmx_agl_gmx_rxx_frm_chk
uint64_t reserved_10_63 : 54;
#endif
} s;
- struct cvmx_agl_gmx_rxx_frm_chk_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t skperr : 1; /**< Skipper error */
uint64_t rcverr : 1; /**< Frame was received with MII Data reception error */
@@ -1834,8 +2005,12 @@ union cvmx_agl_gmx_rxx_frm_chk
struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx;
struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t;
@@ -1870,12 +2045,10 @@ typedef union cvmx_agl_gmx_rxx_frm_chk cvmx_agl_gmx_rxx_frm_chk_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_frm_ctl
-{
+union cvmx_agl_gmx_rxx_frm_ctl {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_frm_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_frm_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63 : 51;
uint64_t ptp_mode : 1; /**< Timestamp mode
When PTP_MODE is set, a 64-bit timestamp will be
@@ -1940,9 +2113,8 @@ union cvmx_agl_gmx_rxx_frm_ctl
uint64_t reserved_13_63 : 51;
#endif
} s;
- struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t pre_align : 1; /**< When set, PREAMBLE parser aligns the the SFD byte
regardless of the number of previous PREAMBLE
@@ -1990,8 +2162,12 @@ union cvmx_agl_gmx_rxx_frm_ctl
struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx;
struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t;
@@ -2011,12 +2187,10 @@ typedef union cvmx_agl_gmx_rxx_frm_ctl cvmx_agl_gmx_rxx_frm_ctl_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_frm_max
-{
+union cvmx_agl_gmx_rxx_frm_max {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_frm_max_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_frm_max_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t len : 16; /**< Byte count for Max-sized frame check
AGL_GMX_RXn_FRM_CHK[MAXERR] enables the check
@@ -2035,8 +2209,12 @@ union cvmx_agl_gmx_rxx_frm_max
struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn61xx;
struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn66xx;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn68xx;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t;
@@ -2050,12 +2228,10 @@ typedef union cvmx_agl_gmx_rxx_frm_max cvmx_agl_gmx_rxx_frm_max_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_frm_min
-{
+union cvmx_agl_gmx_rxx_frm_min {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_frm_min_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_frm_min_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t len : 16; /**< Byte count for Min-sized frame check
AGL_GMX_RXn_FRM_CHK[MINERR] enables the check
@@ -2073,8 +2249,12 @@ union cvmx_agl_gmx_rxx_frm_min
struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn61xx;
struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn66xx;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn68xx;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t;
@@ -2088,12 +2268,10 @@ typedef union cvmx_agl_gmx_rxx_frm_min cvmx_agl_gmx_rxx_frm_min_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_ifg
-{
+union cvmx_agl_gmx_rxx_ifg {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_ifg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t ifg : 4; /**< Min IFG (in IFG*8 bits) between packets used to
determine IFGERR. Normally IFG is 96 bits.
@@ -2111,8 +2289,12 @@ union cvmx_agl_gmx_rxx_ifg
struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_ifg_s cn61xx;
struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_ifg_s cn66xx;
+ struct cvmx_agl_gmx_rxx_ifg_s cn68xx;
+ struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t;
@@ -2126,12 +2308,10 @@ typedef union cvmx_agl_gmx_rxx_ifg cvmx_agl_gmx_rxx_ifg_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_int_en
-{
+union cvmx_agl_gmx_rxx_int_en {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_int_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */
uint64_t phy_dupx : 1; /**< Change in the RMGII inbound LinkDuplex | NS */
@@ -2177,9 +2357,8 @@ union cvmx_agl_gmx_rxx_int_en
uint64_t reserved_20_63 : 44;
#endif
} s;
- struct cvmx_agl_gmx_rxx_int_en_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */
uint64_t reserved_16_18 : 3;
@@ -2224,8 +2403,12 @@ union cvmx_agl_gmx_rxx_int_en
struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_int_en_s cn61xx;
struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_int_en_s cn66xx;
+ struct cvmx_agl_gmx_rxx_int_en_s cn68xx;
+ struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t;
@@ -2274,7 +2457,7 @@ typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t;
* (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.
* Does not check the number of PREAMBLE cycles.
*
- * (C) OVRERR - Not to be included in the HRM
+ * (C) OVRERR -
*
* OVRERR is an architectural assertion check internal to GMX to
* make sure no assumption was violated. In a correctly operating
@@ -2291,12 +2474,10 @@ typedef union cvmx_agl_gmx_rxx_int_en cvmx_agl_gmx_rxx_int_en_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_int_reg
-{
+union cvmx_agl_gmx_rxx_int_reg {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_int_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */
uint64_t phy_dupx : 1; /**< Change in the RGMII inbound LinkDuplex | NS */
@@ -2344,9 +2525,8 @@ union cvmx_agl_gmx_rxx_int_reg
uint64_t reserved_20_63 : 44;
#endif
} s;
- struct cvmx_agl_gmx_rxx_int_reg_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t pause_drp : 1; /**< Pause packet was dropped due to full GMX RX FIFO */
uint64_t reserved_16_18 : 3;
@@ -2393,8 +2573,12 @@ union cvmx_agl_gmx_rxx_int_reg
struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn61xx;
struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn66xx;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn68xx;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t;
@@ -2421,12 +2605,10 @@ typedef union cvmx_agl_gmx_rxx_int_reg cvmx_agl_gmx_rxx_int_reg_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_jabber
-{
+union cvmx_agl_gmx_rxx_jabber {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_jabber_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_jabber_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t cnt : 16; /**< Byte count for jabber check
Failing packets set the JABBER interrupt and are
@@ -2442,8 +2624,12 @@ union cvmx_agl_gmx_rxx_jabber
struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_jabber_s cn61xx;
struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_jabber_s cn66xx;
+ struct cvmx_agl_gmx_rxx_jabber_s cn68xx;
+ struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t;
@@ -2457,12 +2643,10 @@ typedef union cvmx_agl_gmx_rxx_jabber cvmx_agl_gmx_rxx_jabber_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_pause_drop_time
-{
+union cvmx_agl_gmx_rxx_pause_drop_time {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t status : 16; /**< Time extracted from the dropped PAUSE packet */
#else
@@ -2474,8 +2658,12 @@ union cvmx_agl_gmx_rxx_pause_drop_time
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx;
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_t;
@@ -2492,12 +2680,10 @@ typedef union cvmx_agl_gmx_rxx_pause_drop_time cvmx_agl_gmx_rxx_pause_drop_time_
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_rx_inbnd
-{
+union cvmx_agl_gmx_rxx_rx_inbnd {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_rx_inbnd_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t duplex : 1; /**< RGMII Inbound LinkDuplex | NS
0=half-duplex
@@ -2517,8 +2703,12 @@ union cvmx_agl_gmx_rxx_rx_inbnd
uint64_t reserved_4_63 : 60;
#endif
} s;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx;
struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t;
@@ -2532,12 +2722,10 @@ typedef union cvmx_agl_gmx_rxx_rx_inbnd cvmx_agl_gmx_rxx_rx_inbnd_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rxx_stats_ctl
-{
+union cvmx_agl_gmx_rxx_stats_ctl {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t rd_clr : 1; /**< RX Stats registers will clear on reads */
#else
@@ -2549,8 +2737,12 @@ union cvmx_agl_gmx_rxx_stats_ctl
struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t;
@@ -2562,12 +2754,10 @@ typedef union cvmx_agl_gmx_rxx_stats_ctl cvmx_agl_gmx_rxx_stats_ctl_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_octs
-{
+union cvmx_agl_gmx_rxx_stats_octs {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_octs_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_octs_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t cnt : 48; /**< Octet count of received good packets */
#else
@@ -2579,8 +2769,12 @@ union cvmx_agl_gmx_rxx_stats_octs
struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t;
@@ -2592,12 +2786,10 @@ typedef union cvmx_agl_gmx_rxx_stats_octs cvmx_agl_gmx_rxx_stats_octs_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_octs_ctl
-{
+union cvmx_agl_gmx_rxx_stats_octs_ctl {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t cnt : 48; /**< Octet count of received pause packets */
#else
@@ -2609,8 +2801,12 @@ union cvmx_agl_gmx_rxx_stats_octs_ctl
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t;
@@ -2622,12 +2818,10 @@ typedef union cvmx_agl_gmx_rxx_stats_octs_ctl cvmx_agl_gmx_rxx_stats_octs_ctl_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_octs_dmac
-{
+union cvmx_agl_gmx_rxx_stats_octs_dmac {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t cnt : 48; /**< Octet count of filtered dmac packets */
#else
@@ -2639,8 +2833,12 @@ union cvmx_agl_gmx_rxx_stats_octs_dmac
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_t;
@@ -2652,12 +2850,10 @@ typedef union cvmx_agl_gmx_rxx_stats_octs_dmac cvmx_agl_gmx_rxx_stats_octs_dmac_
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_octs_drp
-{
+union cvmx_agl_gmx_rxx_stats_octs_drp {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t cnt : 48; /**< Octet count of dropped packets */
#else
@@ -2669,8 +2865,12 @@ union cvmx_agl_gmx_rxx_stats_octs_drp
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t;
@@ -2688,12 +2888,10 @@ typedef union cvmx_agl_gmx_rxx_stats_octs_drp cvmx_agl_gmx_rxx_stats_octs_drp_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_pkts
-{
+union cvmx_agl_gmx_rxx_stats_pkts {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_pkts_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_pkts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of received good packets */
#else
@@ -2705,8 +2903,12 @@ union cvmx_agl_gmx_rxx_stats_pkts
struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t;
@@ -2723,12 +2925,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts cvmx_agl_gmx_rxx_stats_pkts_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_pkts_bad
-{
+union cvmx_agl_gmx_rxx_stats_pkts_bad {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of bad packets */
#else
@@ -2740,8 +2940,12 @@ union cvmx_agl_gmx_rxx_stats_pkts_bad
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t;
@@ -2763,12 +2967,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts_bad cvmx_agl_gmx_rxx_stats_pkts_bad_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_pkts_ctl
-{
+union cvmx_agl_gmx_rxx_stats_pkts_ctl {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of received pause packets */
#else
@@ -2780,8 +2982,12 @@ union cvmx_agl_gmx_rxx_stats_pkts_ctl
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t;
@@ -2804,12 +3010,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts_ctl cvmx_agl_gmx_rxx_stats_pkts_ctl_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_pkts_dmac
-{
+union cvmx_agl_gmx_rxx_stats_pkts_dmac {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of filtered dmac packets */
#else
@@ -2821,8 +3025,12 @@ union cvmx_agl_gmx_rxx_stats_pkts_dmac
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_t;
@@ -2841,12 +3049,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts_dmac cvmx_agl_gmx_rxx_stats_pkts_dmac_
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_stats_pkts_drp
-{
+union cvmx_agl_gmx_rxx_stats_pkts_drp {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t cnt : 32; /**< Count of dropped packets */
#else
@@ -2858,8 +3064,12 @@ union cvmx_agl_gmx_rxx_stats_pkts_drp
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx;
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t;
@@ -2896,12 +3106,10 @@ typedef union cvmx_agl_gmx_rxx_stats_pkts_drp cvmx_agl_gmx_rxx_stats_pkts_drp_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rxx_udd_skp
-{
+union cvmx_agl_gmx_rxx_udd_skp {
uint64_t u64;
- struct cvmx_agl_gmx_rxx_udd_skp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rxx_udd_skp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t fcssel : 1; /**< Include the skip bytes in the FCS calculation
0 = all skip bytes are included in FCS
@@ -2921,8 +3129,12 @@ union cvmx_agl_gmx_rxx_udd_skp
struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx;
struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t;
@@ -2936,12 +3148,10 @@ typedef union cvmx_agl_gmx_rxx_udd_skp cvmx_agl_gmx_rxx_udd_skp_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rx_bp_dropx
-{
+union cvmx_agl_gmx_rx_bp_dropx {
uint64_t u64;
- struct cvmx_agl_gmx_rx_bp_dropx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rx_bp_dropx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t mark : 6; /**< Number of 8B ticks to reserve in the RX FIFO.
When the FIFO exceeds this count, packets will
@@ -2958,8 +3168,12 @@ union cvmx_agl_gmx_rx_bp_dropx
struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx;
struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t;
@@ -2973,12 +3187,10 @@ typedef union cvmx_agl_gmx_rx_bp_dropx cvmx_agl_gmx_rx_bp_dropx_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rx_bp_offx
-{
+union cvmx_agl_gmx_rx_bp_offx {
uint64_t u64;
- struct cvmx_agl_gmx_rx_bp_offx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rx_bp_offx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t mark : 6; /**< Water mark (8B ticks) to deassert backpressure */
#else
@@ -2990,8 +3202,12 @@ union cvmx_agl_gmx_rx_bp_offx
struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn61xx;
struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn66xx;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn68xx;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t;
@@ -3005,12 +3221,10 @@ typedef union cvmx_agl_gmx_rx_bp_offx cvmx_agl_gmx_rx_bp_offx_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_rx_bp_onx
-{
+union cvmx_agl_gmx_rx_bp_onx {
uint64_t u64;
- struct cvmx_agl_gmx_rx_bp_onx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rx_bp_onx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t mark : 9; /**< Hiwater mark (8B ticks) for backpressure. */
#else
@@ -3022,8 +3236,12 @@ union cvmx_agl_gmx_rx_bp_onx
struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn61xx;
struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn66xx;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn68xx;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t;
@@ -3037,12 +3255,10 @@ typedef union cvmx_agl_gmx_rx_bp_onx cvmx_agl_gmx_rx_bp_onx_t;
* COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1.
* COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rx_prt_info
-{
+union cvmx_agl_gmx_rx_prt_info {
uint64_t u64;
- struct cvmx_agl_gmx_rx_prt_info_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rx_prt_info_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63 : 46;
uint64_t drop : 2; /**< Port indication that data was dropped */
uint64_t reserved_2_15 : 14;
@@ -3056,9 +3272,8 @@ union cvmx_agl_gmx_rx_prt_info
} s;
struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
- struct cvmx_agl_gmx_rx_prt_info_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rx_prt_info_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63 : 47;
uint64_t drop : 1; /**< Port indication that data was dropped */
uint64_t reserved_1_15 : 15;
@@ -3071,8 +3286,12 @@ union cvmx_agl_gmx_rx_prt_info
#endif
} cn56xx;
struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_rx_prt_info_s cn61xx;
struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
+ struct cvmx_agl_gmx_rx_prt_info_s cn66xx;
+ struct cvmx_agl_gmx_rx_prt_info_s cn68xx;
+ struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t;
@@ -3086,12 +3305,10 @@ typedef union cvmx_agl_gmx_rx_prt_info cvmx_agl_gmx_rx_prt_info_t;
* RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1.
* RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_rx_tx_status
-{
+union cvmx_agl_gmx_rx_tx_status {
uint64_t u64;
- struct cvmx_agl_gmx_rx_tx_status_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rx_tx_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t tx : 2; /**< Transmit data since last read */
uint64_t reserved_2_3 : 2;
@@ -3105,9 +3322,8 @@ union cvmx_agl_gmx_rx_tx_status
} s;
struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
- struct cvmx_agl_gmx_rx_tx_status_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_rx_tx_status_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t tx : 1; /**< Transmit data since last read */
uint64_t reserved_1_3 : 3;
@@ -3120,8 +3336,12 @@ union cvmx_agl_gmx_rx_tx_status
#endif
} cn56xx;
struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_rx_tx_status_s cn61xx;
struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
+ struct cvmx_agl_gmx_rx_tx_status_s cn66xx;
+ struct cvmx_agl_gmx_rx_tx_status_s cn68xx;
+ struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1;
};
typedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t;
@@ -3135,12 +3355,10 @@ typedef union cvmx_agl_gmx_rx_tx_status cvmx_agl_gmx_rx_tx_status_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_smacx
-{
+union cvmx_agl_gmx_smacx {
uint64_t u64;
- struct cvmx_agl_gmx_smacx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_smacx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t smac : 48; /**< The SMAC field is used for generating and
accepting Control Pause packets */
@@ -3153,8 +3371,12 @@ union cvmx_agl_gmx_smacx
struct cvmx_agl_gmx_smacx_s cn52xxp1;
struct cvmx_agl_gmx_smacx_s cn56xx;
struct cvmx_agl_gmx_smacx_s cn56xxp1;
+ struct cvmx_agl_gmx_smacx_s cn61xx;
struct cvmx_agl_gmx_smacx_s cn63xx;
struct cvmx_agl_gmx_smacx_s cn63xxp1;
+ struct cvmx_agl_gmx_smacx_s cn66xx;
+ struct cvmx_agl_gmx_smacx_s cn68xx;
+ struct cvmx_agl_gmx_smacx_s cn68xxp1;
};
typedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t;
@@ -3167,15 +3389,34 @@ typedef union cvmx_agl_gmx_smacx cvmx_agl_gmx_smacx_t;
* Notes:
* Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
*
+ *
+ *
+ * It has no relationship with the TX FIFO per se. The TX engine sends packets
+ * from PKO and upon completion, sends a command to the TX stats block for an
+ * update based on the packet size. The stats operation can take a few cycles -
+ * normally not enough to be visible considering the 64B min packet size that is
+ * ethernet convention.
+ *
+ * In the rare case in which SW attempted to schedule really, really, small packets
+ * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in
+ * real time and can back up the TX engine.
+ *
+ * This counter is the number of cycles in which the TX engine was stalled. In
+ * normal operation, it should always be zeros.
*/
-union cvmx_agl_gmx_stat_bp
-{
+union cvmx_agl_gmx_stat_bp {
uint64_t u64;
- struct cvmx_agl_gmx_stat_bp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_stat_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63 : 47;
- uint64_t bp : 1; /**< Current BP state */
+ uint64_t bp : 1; /**< Current TX stats BP state
+ When the TX stats machine cannot update the stats
+ registers quickly enough, the machine has the
+ ability to BP TX datapath. This is a rare event
+ and will not occur in normal operation.
+ 0 = no backpressure is applied
+ 1 = backpressure is applied to TX datapath to
+ allow stat update operations to complete */
uint64_t cnt : 16; /**< Number of cycles that BP has been asserted
Saturating counter */
#else
@@ -3188,8 +3429,12 @@ union cvmx_agl_gmx_stat_bp
struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
struct cvmx_agl_gmx_stat_bp_s cn56xx;
struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+ struct cvmx_agl_gmx_stat_bp_s cn61xx;
struct cvmx_agl_gmx_stat_bp_s cn63xx;
struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
+ struct cvmx_agl_gmx_stat_bp_s cn66xx;
+ struct cvmx_agl_gmx_stat_bp_s cn68xx;
+ struct cvmx_agl_gmx_stat_bp_s cn68xxp1;
};
typedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t;
@@ -3203,12 +3448,10 @@ typedef union cvmx_agl_gmx_stat_bp cvmx_agl_gmx_stat_bp_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_txx_append
-{
+union cvmx_agl_gmx_txx_append {
uint64_t u64;
- struct cvmx_agl_gmx_txx_append_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_append_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t force_fcs : 1; /**< Append the Ethernet FCS on each pause packet
when FCS is clear. Pause packets are normally
@@ -3230,8 +3473,12 @@ union cvmx_agl_gmx_txx_append
struct cvmx_agl_gmx_txx_append_s cn52xxp1;
struct cvmx_agl_gmx_txx_append_s cn56xx;
struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_append_s cn61xx;
struct cvmx_agl_gmx_txx_append_s cn63xx;
struct cvmx_agl_gmx_txx_append_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_append_s cn66xx;
+ struct cvmx_agl_gmx_txx_append_s cn68xx;
+ struct cvmx_agl_gmx_txx_append_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t;
@@ -3255,12 +3502,10 @@ typedef union cvmx_agl_gmx_txx_append cvmx_agl_gmx_txx_append_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_clk
-{
+union cvmx_agl_gmx_txx_clk {
uint64_t u64;
- struct cvmx_agl_gmx_txx_clk_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_clk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t clk_cnt : 6; /**< Controls the RGMII TXC frequency | NS
TXC(period) =
@@ -3270,8 +3515,12 @@ union cvmx_agl_gmx_txx_clk
uint64_t reserved_6_63 : 58;
#endif
} s;
+ struct cvmx_agl_gmx_txx_clk_s cn61xx;
struct cvmx_agl_gmx_txx_clk_s cn63xx;
struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_clk_s cn66xx;
+ struct cvmx_agl_gmx_txx_clk_s cn68xx;
+ struct cvmx_agl_gmx_txx_clk_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t;
@@ -3285,12 +3534,10 @@ typedef union cvmx_agl_gmx_txx_clk cvmx_agl_gmx_txx_clk_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_txx_ctl
-{
+union cvmx_agl_gmx_txx_ctl {
uint64_t u64;
- struct cvmx_agl_gmx_txx_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t xsdef_en : 1; /**< Enables the excessive deferral check for stats
and interrupts */
@@ -3306,8 +3553,12 @@ union cvmx_agl_gmx_txx_ctl
struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
struct cvmx_agl_gmx_txx_ctl_s cn56xx;
struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_ctl_s cn61xx;
struct cvmx_agl_gmx_txx_ctl_s cn63xx;
struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_ctl_s cn66xx;
+ struct cvmx_agl_gmx_txx_ctl_s cn68xx;
+ struct cvmx_agl_gmx_txx_ctl_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t;
@@ -3321,12 +3572,10 @@ typedef union cvmx_agl_gmx_txx_ctl cvmx_agl_gmx_txx_ctl_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_txx_min_pkt
-{
+union cvmx_agl_gmx_txx_min_pkt {
uint64_t u64;
- struct cvmx_agl_gmx_txx_min_pkt_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_min_pkt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t min_size : 8; /**< Min frame in bytes before the FCS is applied
Padding is only appened when
@@ -3342,8 +3591,12 @@ union cvmx_agl_gmx_txx_min_pkt
struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn61xx;
struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn66xx;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn68xx;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t;
@@ -3374,12 +3627,10 @@ typedef union cvmx_agl_gmx_txx_min_pkt cvmx_agl_gmx_txx_min_pkt_t;
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_pause_pkt_interval
-{
+union cvmx_agl_gmx_txx_pause_pkt_interval {
uint64_t u64;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t interval : 16; /**< Arbitrate for a pause packet every (INTERVAL*512)
bit-times.
@@ -3395,8 +3646,12 @@ union cvmx_agl_gmx_txx_pause_pkt_interval
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx;
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_interval_t;
@@ -3427,12 +3682,10 @@ typedef union cvmx_agl_gmx_txx_pause_pkt_interval cvmx_agl_gmx_txx_pause_pkt_int
*
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_pause_pkt_time
-{
+union cvmx_agl_gmx_txx_pause_pkt_time {
uint64_t u64;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t time : 16; /**< The pause_time field placed is outbnd pause pkts
pause_time is in 512 bit-times
@@ -3446,8 +3699,12 @@ union cvmx_agl_gmx_txx_pause_pkt_time
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx;
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t;
@@ -3461,12 +3718,10 @@ typedef union cvmx_agl_gmx_txx_pause_pkt_time cvmx_agl_gmx_txx_pause_pkt_time_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_txx_pause_togo
-{
+union cvmx_agl_gmx_txx_pause_togo {
uint64_t u64;
- struct cvmx_agl_gmx_txx_pause_togo_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_pause_togo_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t time : 16; /**< Amount of time remaining to backpressure */
#else
@@ -3478,8 +3733,12 @@ union cvmx_agl_gmx_txx_pause_togo
struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn61xx;
struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn66xx;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn68xx;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t;
@@ -3493,12 +3752,10 @@ typedef union cvmx_agl_gmx_txx_pause_togo cvmx_agl_gmx_txx_pause_togo_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_txx_pause_zero
-{
+union cvmx_agl_gmx_txx_pause_zero {
uint64_t u64;
- struct cvmx_agl_gmx_txx_pause_zero_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_pause_zero_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t send : 1; /**< When backpressure condition clear, send PAUSE
packet with pause_time of zero to enable the
@@ -3512,8 +3769,12 @@ union cvmx_agl_gmx_txx_pause_zero
struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn61xx;
struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn66xx;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn68xx;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t;
@@ -3527,12 +3788,10 @@ typedef union cvmx_agl_gmx_txx_pause_zero cvmx_agl_gmx_txx_pause_zero_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_txx_soft_pause
-{
+union cvmx_agl_gmx_txx_soft_pause {
uint64_t u64;
- struct cvmx_agl_gmx_txx_soft_pause_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_soft_pause_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t time : 16; /**< Back off the TX bus for (TIME*512) bit-times
for full-duplex operation only */
@@ -3545,8 +3804,12 @@ union cvmx_agl_gmx_txx_soft_pause
struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn61xx;
struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn66xx;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn68xx;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t;
@@ -3561,12 +3824,10 @@ typedef union cvmx_agl_gmx_txx_soft_pause cvmx_agl_gmx_txx_soft_pause_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat0
-{
+union cvmx_agl_gmx_txx_stat0 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t xsdef : 32; /**< Number of packets dropped (never successfully
sent) due to excessive deferal */
uint64_t xscol : 32; /**< Number of packets dropped (never successfully
@@ -3581,8 +3842,12 @@ union cvmx_agl_gmx_txx_stat0
struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat0_s cn56xx;
struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat0_s cn61xx;
struct cvmx_agl_gmx_txx_stat0_s cn63xx;
struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat0_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat0_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat0_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t;
@@ -3597,12 +3862,10 @@ typedef union cvmx_agl_gmx_txx_stat0 cvmx_agl_gmx_txx_stat0_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat1
-{
+union cvmx_agl_gmx_txx_stat1 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t scol : 32; /**< Number of packets sent with a single collision */
uint64_t mcol : 32; /**< Number of packets sent with multiple collisions
but < AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */
@@ -3615,8 +3878,12 @@ union cvmx_agl_gmx_txx_stat1
struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat1_s cn56xx;
struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat1_s cn61xx;
struct cvmx_agl_gmx_txx_stat1_s cn63xx;
struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat1_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat1_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat1_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t;
@@ -3634,12 +3901,10 @@ typedef union cvmx_agl_gmx_txx_stat1 cvmx_agl_gmx_txx_stat1_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat2
-{
+union cvmx_agl_gmx_txx_stat2 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat2_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t octs : 48; /**< Number of total octets sent on the interface.
Does not count octets from frames that were
@@ -3653,8 +3918,12 @@ union cvmx_agl_gmx_txx_stat2
struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat2_s cn56xx;
struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat2_s cn61xx;
struct cvmx_agl_gmx_txx_stat2_s cn63xx;
struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat2_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat2_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat2_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t;
@@ -3669,12 +3938,10 @@ typedef union cvmx_agl_gmx_txx_stat2 cvmx_agl_gmx_txx_stat2_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat3
-{
+union cvmx_agl_gmx_txx_stat3 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat3_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t pkts : 32; /**< Number of total frames sent on the interface.
Does not count frames that were truncated due to
@@ -3688,8 +3955,12 @@ union cvmx_agl_gmx_txx_stat3
struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat3_s cn56xx;
struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat3_s cn61xx;
struct cvmx_agl_gmx_txx_stat3_s cn63xx;
struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat3_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat3_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat3_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t;
@@ -3707,12 +3978,10 @@ typedef union cvmx_agl_gmx_txx_stat3 cvmx_agl_gmx_txx_stat3_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat4
-{
+union cvmx_agl_gmx_txx_stat4 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat4_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t hist1 : 32; /**< Number of packets sent with an octet count of 64. */
uint64_t hist0 : 32; /**< Number of packets sent with an octet count
of < 64. */
@@ -3725,8 +3994,12 @@ union cvmx_agl_gmx_txx_stat4
struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat4_s cn56xx;
struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat4_s cn61xx;
struct cvmx_agl_gmx_txx_stat4_s cn63xx;
struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat4_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat4_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat4_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t;
@@ -3744,12 +4017,10 @@ typedef union cvmx_agl_gmx_txx_stat4 cvmx_agl_gmx_txx_stat4_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat5
-{
+union cvmx_agl_gmx_txx_stat5 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat5_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat5_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t hist3 : 32; /**< Number of packets sent with an octet count of
128 - 255. */
uint64_t hist2 : 32; /**< Number of packets sent with an octet count of
@@ -3763,8 +4034,12 @@ union cvmx_agl_gmx_txx_stat5
struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat5_s cn56xx;
struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat5_s cn61xx;
struct cvmx_agl_gmx_txx_stat5_s cn63xx;
struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat5_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat5_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat5_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t;
@@ -3782,12 +4057,10 @@ typedef union cvmx_agl_gmx_txx_stat5 cvmx_agl_gmx_txx_stat5_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat6
-{
+union cvmx_agl_gmx_txx_stat6 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat6_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat6_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t hist5 : 32; /**< Number of packets sent with an octet count of
512 - 1023. */
uint64_t hist4 : 32; /**< Number of packets sent with an octet count of
@@ -3801,8 +4074,12 @@ union cvmx_agl_gmx_txx_stat6
struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat6_s cn56xx;
struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat6_s cn61xx;
struct cvmx_agl_gmx_txx_stat6_s cn63xx;
struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat6_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat6_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat6_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t;
@@ -3820,12 +4097,10 @@ typedef union cvmx_agl_gmx_txx_stat6 cvmx_agl_gmx_txx_stat6_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat7
-{
+union cvmx_agl_gmx_txx_stat7 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat7_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat7_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t hist7 : 32; /**< Number of packets sent with an octet count
of > 1518. */
uint64_t hist6 : 32; /**< Number of packets sent with an octet count of
@@ -3839,8 +4114,12 @@ union cvmx_agl_gmx_txx_stat7
struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat7_s cn56xx;
struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat7_s cn61xx;
struct cvmx_agl_gmx_txx_stat7_s cn63xx;
struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat7_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat7_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat7_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t;
@@ -3860,12 +4139,10 @@ typedef union cvmx_agl_gmx_txx_stat7 cvmx_agl_gmx_txx_stat7_t;
* reality and should be ignored by software.
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat8
-{
+union cvmx_agl_gmx_txx_stat8 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat8_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat8_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t mcst : 32; /**< Number of packets sent to multicast DMAC.
Does not include BCST packets. */
uint64_t bcst : 32; /**< Number of packets sent to broadcast DMAC.
@@ -3879,8 +4156,12 @@ union cvmx_agl_gmx_txx_stat8
struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat8_s cn56xx;
struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat8_s cn61xx;
struct cvmx_agl_gmx_txx_stat8_s cn63xx;
struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat8_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat8_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat8_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t;
@@ -3895,12 +4176,10 @@ typedef union cvmx_agl_gmx_txx_stat8 cvmx_agl_gmx_txx_stat8_t;
* - Counters will wrap
* - Not reset when MIX*_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_txx_stat9
-{
+union cvmx_agl_gmx_txx_stat9 {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stat9_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stat9_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t undflw : 32; /**< Number of underflow packets */
uint64_t ctl : 32; /**< Number of Control packets (PAUSE flow control)
generated by GMX. It does not include control
@@ -3914,8 +4193,12 @@ union cvmx_agl_gmx_txx_stat9
struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat9_s cn56xx;
struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat9_s cn61xx;
struct cvmx_agl_gmx_txx_stat9_s cn63xx;
struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stat9_s cn66xx;
+ struct cvmx_agl_gmx_txx_stat9_s cn68xx;
+ struct cvmx_agl_gmx_txx_stat9_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t;
@@ -3929,12 +4212,10 @@ typedef union cvmx_agl_gmx_txx_stat9 cvmx_agl_gmx_txx_stat9_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_txx_stats_ctl
-{
+union cvmx_agl_gmx_txx_stats_ctl {
uint64_t u64;
- struct cvmx_agl_gmx_txx_stats_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_stats_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t rd_clr : 1; /**< Stats registers will clear on reads */
#else
@@ -3946,8 +4227,12 @@ union cvmx_agl_gmx_txx_stats_ctl
struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx;
struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t;
@@ -3961,12 +4246,10 @@ typedef union cvmx_agl_gmx_txx_stats_ctl cvmx_agl_gmx_txx_stats_ctl_t;
* Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
*
*/
-union cvmx_agl_gmx_txx_thresh
-{
+union cvmx_agl_gmx_txx_thresh {
uint64_t u64;
- struct cvmx_agl_gmx_txx_thresh_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_txx_thresh_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t cnt : 6; /**< Number of 16B ticks to accumulate in the TX FIFO
before sending on the packet interface
@@ -3983,8 +4266,12 @@ union cvmx_agl_gmx_txx_thresh
struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
struct cvmx_agl_gmx_txx_thresh_s cn56xx;
struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_thresh_s cn61xx;
struct cvmx_agl_gmx_txx_thresh_s cn63xx;
struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
+ struct cvmx_agl_gmx_txx_thresh_s cn66xx;
+ struct cvmx_agl_gmx_txx_thresh_s cn68xx;
+ struct cvmx_agl_gmx_txx_thresh_s cn68xxp1;
};
typedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t;
@@ -3998,12 +4285,10 @@ typedef union cvmx_agl_gmx_txx_thresh cvmx_agl_gmx_txx_thresh_t;
* BP[0] will be reset when MIX0_CTL[RESET] is set to 1.
* BP[1] will be reset when MIX1_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_tx_bp
-{
+union cvmx_agl_gmx_tx_bp {
uint64_t u64;
- struct cvmx_agl_gmx_tx_bp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t bp : 2; /**< Port BackPressure status
0=Port is available
@@ -4015,9 +4300,8 @@ union cvmx_agl_gmx_tx_bp
} s;
struct cvmx_agl_gmx_tx_bp_s cn52xx;
struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
- struct cvmx_agl_gmx_tx_bp_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_bp_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t bp : 1; /**< Port BackPressure status
0=Port is available
@@ -4028,8 +4312,12 @@ union cvmx_agl_gmx_tx_bp
#endif
} cn56xx;
struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_bp_s cn61xx;
struct cvmx_agl_gmx_tx_bp_s cn63xx;
struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_bp_s cn66xx;
+ struct cvmx_agl_gmx_tx_bp_s cn68xx;
+ struct cvmx_agl_gmx_tx_bp_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t;
@@ -4043,12 +4331,10 @@ typedef union cvmx_agl_gmx_tx_bp cvmx_agl_gmx_tx_bp_t;
* Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
*
*/
-union cvmx_agl_gmx_tx_col_attempt
-{
+union cvmx_agl_gmx_tx_col_attempt {
uint64_t u64;
- struct cvmx_agl_gmx_tx_col_attempt_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_col_attempt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t limit : 5; /**< Collision Attempts */
#else
@@ -4060,8 +4346,12 @@ union cvmx_agl_gmx_tx_col_attempt
struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn61xx;
struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn66xx;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn68xx;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t;
@@ -4090,12 +4380,10 @@ typedef union cvmx_agl_gmx_tx_col_attempt cvmx_agl_gmx_tx_col_attempt_t;
*
* Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
*/
-union cvmx_agl_gmx_tx_ifg
-{
+union cvmx_agl_gmx_tx_ifg {
uint64_t u64;
- struct cvmx_agl_gmx_tx_ifg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_ifg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t ifg2 : 4; /**< 1/3 of the interframe gap timing
If CRS is detected during IFG2, then the
@@ -4115,8 +4403,12 @@ union cvmx_agl_gmx_tx_ifg
struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
struct cvmx_agl_gmx_tx_ifg_s cn56xx;
struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_ifg_s cn61xx;
struct cvmx_agl_gmx_tx_ifg_s cn63xx;
struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_ifg_s cn66xx;
+ struct cvmx_agl_gmx_tx_ifg_s cn68xx;
+ struct cvmx_agl_gmx_tx_ifg_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t;
@@ -4131,12 +4423,10 @@ typedef union cvmx_agl_gmx_tx_ifg cvmx_agl_gmx_tx_ifg_t;
* UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1.
* PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
*/
-union cvmx_agl_gmx_tx_int_en
-{
+union cvmx_agl_gmx_tx_int_en {
uint64_t u64;
- struct cvmx_agl_gmx_tx_int_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_22_63 : 42;
uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be
sent due to XSCOL */
@@ -4165,9 +4455,8 @@ union cvmx_agl_gmx_tx_int_en
uint64_t reserved_22_63 : 42;
#endif
} s;
- struct cvmx_agl_gmx_tx_int_en_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_int_en_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63 : 46;
uint64_t late_col : 2; /**< TX Late Collision */
uint64_t reserved_14_15 : 2;
@@ -4192,9 +4481,8 @@ union cvmx_agl_gmx_tx_int_en
#endif
} cn52xx;
struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_tx_int_en_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_int_en_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63 : 47;
uint64_t late_col : 1; /**< TX Late Collision */
uint64_t reserved_13_15 : 3;
@@ -4219,8 +4507,12 @@ union cvmx_agl_gmx_tx_int_en
#endif
} cn56xx;
struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_int_en_s cn61xx;
struct cvmx_agl_gmx_tx_int_en_s cn63xx;
struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_int_en_s cn66xx;
+ struct cvmx_agl_gmx_tx_int_en_s cn68xx;
+ struct cvmx_agl_gmx_tx_int_en_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t;
@@ -4235,12 +4527,10 @@ typedef union cvmx_agl_gmx_tx_int_en cvmx_agl_gmx_tx_int_en_t;
* UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1], PTP_LOST[1] will be reset when MIX1_CTL[RESET] is set to 1.
* PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
*/
-union cvmx_agl_gmx_tx_int_reg
-{
+union cvmx_agl_gmx_tx_int_reg {
uint64_t u64;
- struct cvmx_agl_gmx_tx_int_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_22_63 : 42;
uint64_t ptp_lost : 2; /**< A packet with a PTP request was not able to be
sent due to XSCOL */
@@ -4269,9 +4559,8 @@ union cvmx_agl_gmx_tx_int_reg
uint64_t reserved_22_63 : 42;
#endif
} s;
- struct cvmx_agl_gmx_tx_int_reg_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_int_reg_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63 : 46;
uint64_t late_col : 2; /**< TX Late Collision */
uint64_t reserved_14_15 : 2;
@@ -4296,9 +4585,8 @@ union cvmx_agl_gmx_tx_int_reg
#endif
} cn52xx;
struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_tx_int_reg_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_int_reg_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63 : 47;
uint64_t late_col : 1; /**< TX Late Collision */
uint64_t reserved_13_15 : 3;
@@ -4323,8 +4611,12 @@ union cvmx_agl_gmx_tx_int_reg
#endif
} cn56xx;
struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_int_reg_s cn61xx;
struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_int_reg_s cn66xx;
+ struct cvmx_agl_gmx_tx_int_reg_s cn68xx;
+ struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t;
@@ -4338,12 +4630,10 @@ typedef union cvmx_agl_gmx_tx_int_reg cvmx_agl_gmx_tx_int_reg_t;
* Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
*
*/
-union cvmx_agl_gmx_tx_jam
-{
+union cvmx_agl_gmx_tx_jam {
uint64_t u64;
- struct cvmx_agl_gmx_tx_jam_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_jam_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t jam : 8; /**< Jam pattern */
#else
@@ -4355,8 +4645,12 @@ union cvmx_agl_gmx_tx_jam
struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
struct cvmx_agl_gmx_tx_jam_s cn56xx;
struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_jam_s cn61xx;
struct cvmx_agl_gmx_tx_jam_s cn63xx;
struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_jam_s cn66xx;
+ struct cvmx_agl_gmx_tx_jam_s cn68xx;
+ struct cvmx_agl_gmx_tx_jam_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t;
@@ -4370,12 +4664,10 @@ typedef union cvmx_agl_gmx_tx_jam cvmx_agl_gmx_tx_jam_t;
* Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
*
*/
-union cvmx_agl_gmx_tx_lfsr
-{
+union cvmx_agl_gmx_tx_lfsr {
uint64_t u64;
- struct cvmx_agl_gmx_tx_lfsr_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_lfsr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t lfsr : 16; /**< The current state of the LFSR used to feed random
numbers to compute truncated binary exponential
@@ -4389,8 +4681,12 @@ union cvmx_agl_gmx_tx_lfsr
struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_lfsr_s cn61xx;
struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_lfsr_s cn66xx;
+ struct cvmx_agl_gmx_tx_lfsr_s cn68xx;
+ struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t;
@@ -4404,12 +4700,10 @@ typedef union cvmx_agl_gmx_tx_lfsr cvmx_agl_gmx_tx_lfsr_t;
* IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1.
* IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1.
*/
-union cvmx_agl_gmx_tx_ovr_bp
-{
+union cvmx_agl_gmx_tx_ovr_bp {
uint64_t u64;
- struct cvmx_agl_gmx_tx_ovr_bp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_ovr_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63 : 54;
uint64_t en : 2; /**< Per port Enable back pressure override */
uint64_t reserved_6_7 : 2;
@@ -4429,9 +4723,8 @@ union cvmx_agl_gmx_tx_ovr_bp
} s;
struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
- struct cvmx_agl_gmx_tx_ovr_bp_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t en : 1; /**< Per port Enable back pressure override */
uint64_t reserved_5_7 : 3;
@@ -4450,8 +4743,12 @@ union cvmx_agl_gmx_tx_ovr_bp
#endif
} cn56xx;
struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx;
struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t;
@@ -4465,12 +4762,10 @@ typedef union cvmx_agl_gmx_tx_ovr_bp cvmx_agl_gmx_tx_ovr_bp_t;
* Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
*
*/
-union cvmx_agl_gmx_tx_pause_pkt_dmac
-{
+union cvmx_agl_gmx_tx_pause_pkt_dmac {
uint64_t u64;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63 : 16;
uint64_t dmac : 48; /**< The DMAC field placed is outbnd pause pkts */
#else
@@ -4482,8 +4777,12 @@ union cvmx_agl_gmx_tx_pause_pkt_dmac
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx;
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t;
@@ -4497,12 +4796,10 @@ typedef union cvmx_agl_gmx_tx_pause_pkt_dmac cvmx_agl_gmx_tx_pause_pkt_dmac_t;
* Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
*
*/
-union cvmx_agl_gmx_tx_pause_pkt_type
-{
+union cvmx_agl_gmx_tx_pause_pkt_type {
uint64_t u64;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t type : 16; /**< The TYPE field placed is outbnd pause pkts */
#else
@@ -4514,8 +4811,12 @@ union cvmx_agl_gmx_tx_pause_pkt_type
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx;
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1;
};
typedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t;
@@ -4526,19 +4827,49 @@ typedef union cvmx_agl_gmx_tx_pause_pkt_type cvmx_agl_gmx_tx_pause_pkt_type_t;
*
*
* Notes:
+ * The RGMII timing specification requires that devices transmit clock and
+ * data synchronously. The specification requires external sources (namely
+ * the PC board trace routes) to introduce the appropriate 1.5 to 2.0 ns of
+ * delay.
+ *
+ * To eliminate the need for the PC board delays, the MIX RGMII interface
+ * has optional onboard DLL's for both transmit and receive. For correct
+ * operation, at most one of the transmitter, board, or receiver involved
+ * in an RGMII link should introduce delay. By default/reset,
+ * the MIX RGMII receivers delay the received clock, and the MIX
+ * RGMII transmitters do not delay the transmitted clock. Whether this
+ * default works as-is with a given link partner depends on the behavior
+ * of the link partner and the PC board.
+ *
+ * These are the possible modes of MIX RGMII receive operation:
+ * o AGL_PRTx_CTL[CLKRX_BYP] = 0 (reset value) - The OCTEON MIX RGMII
+ * receive interface introduces clock delay using its internal DLL.
+ * This mode is appropriate if neither the remote
+ * transmitter nor the PC board delays the clock.
+ * o AGL_PRTx_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The OCTEON MIX
+ * RGMII receive interface introduces no clock delay. This mode
+ * is appropriate if either the remote transmitter or the PC board
+ * delays the clock.
+ *
+ * These are the possible modes of MIX RGMII transmit operation:
+ * o AGL_PRTx_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) -
+ * The OCTEON MIX RGMII transmit interface introduces no clock
+ * delay. This mode is appropriate is either the remote receiver
+ * or the PC board delays the clock.
+ * o AGL_PRTx_CTL[CLKTX_BYP] = 0 - The OCTEON MIX RGMII transmit
+ * interface introduces clock delay using its internal DLL.
+ * This mode is appropriate if neither the remote receiver
+ * nor the PC board delays the clock.
+ *
* AGL_PRT0_CTL will be reset when MIX0_CTL[RESET] is set to 1.
* AGL_PRT1_CTL will be reset when MIX1_CTL[RESET] is set to 1.
*/
-union cvmx_agl_prtx_ctl
-{
+union cvmx_agl_prtx_ctl {
uint64_t u64;
- struct cvmx_agl_prtx_ctl_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_agl_prtx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t drv_byp : 1; /**< Bypass the compensation controller and use
- DRV_NCTL and DRV_PCTL
- Note: the reset value was changed from pass1
- to pass2. */
+ DRV_NCTL and DRV_PCTL */
uint64_t reserved_62_62 : 1;
uint64_t cmp_pctl : 6; /**< PCTL drive strength from the compensation ctl */
uint64_t reserved_54_55 : 2;
@@ -4562,7 +4893,6 @@ union cvmx_agl_prtx_ctl
Skews RXC from RXD in RGMII mode */
uint64_t clktx_byp : 1; /**< Bypass the TX clock delay setting
Skews TXC from TXD,TXCTL in RGMII mode
- Skews RXC from RXD,RXCTL in RGMII mode
By default, clock and data and sourced
synchronously.
In MII mode, the CLKRX_BYP is forced to 1. */
@@ -4572,9 +4902,7 @@ union cvmx_agl_prtx_ctl
uint64_t reserved_5_7 : 3;
uint64_t dllrst : 1; /**< DLL Reset */
uint64_t comp : 1; /**< Compensation Enable */
- uint64_t enable : 1; /**< Port Enable
- Note: the reset value was changed from pass1
- to pass2. */
+ uint64_t enable : 1; /**< Port Enable */
uint64_t clkrst : 1; /**< Clock Tree Reset */
uint64_t mode : 1; /**< Port Mode
MODE must be set the same for all ports in which
@@ -4607,8 +4935,12 @@ union cvmx_agl_prtx_ctl
uint64_t drv_byp : 1;
#endif
} s;
+ struct cvmx_agl_prtx_ctl_s cn61xx;
struct cvmx_agl_prtx_ctl_s cn63xx;
struct cvmx_agl_prtx_ctl_s cn63xxp1;
+ struct cvmx_agl_prtx_ctl_s cn66xx;
+ struct cvmx_agl_prtx_ctl_s cn68xx;
+ struct cvmx_agl_prtx_ctl_s cn68xxp1;
};
typedef union cvmx_agl_prtx_ctl cvmx_agl_prtx_ctl_t;
diff --git a/cvmx-app-hotplug.c b/cvmx-app-hotplug.c
index 6145134b86bc..a2c54d28172d 100644
--- a/cvmx-app-hotplug.c
+++ b/cvmx-app-hotplug.c
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,9 +48,12 @@
#include "cvmx-app-hotplug.h"
#include "cvmx-spinlock.h"
+#include "cvmx-debug.h"
//#define DEBUG 1
+static cvmx_app_hotplug_global_t *hotplug_global_ptr = 0;
+
#ifndef CVMX_BUILD_FOR_LINUX_USER
static CVMX_SHARED cvmx_spinlock_t cvmx_app_hotplug_sync_lock = { CVMX_SPINLOCK_UNLOCKED_VAL };
@@ -61,6 +64,11 @@ static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32],
static void __cvmx_app_hotplug_sync(void);
static void __cvmx_app_hotplug_reset(void);
+/* Declaring this array here is a compile time check to ensure that the
+ size of cvmx_app_hotplug_info_t is 1024. If the size is not 1024
+ the size of the array will be -1 and this results in a compilation
+ error */
+char __hotplug_info_check[(sizeof(cvmx_app_hotplug_info_t) == 1024) ? 1 : -1];
/**
* This routine registers an application for hotplug. It installs a handler for
* any incoming shutdown request. It also registers a callback routine from the
@@ -90,7 +98,7 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
cvmx_app_hotplug_info_ptr->shutdown_callback = CAST64(fn);
#ifdef DEBUG
- cvmx_dprintf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n",
+ printf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n",
cvmx_app_hotplug_info_ptr->coremask, cvmx_app_hotplug_info_ptr->valid);
#endif
@@ -100,7 +108,82 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
}
/**
- * Activate the current application core for receiving hotplug shutdown requests.
+ * This routine deprecates the the cvmx_app_hotplug_register method. This
+ * registers application for hotplug and the application will have CPU
+ * hotplug callbacks. Various callbacks are specified in cb.
+ * cvmx_app_hotplug_callbacks_t documents the callbacks
+ *
+ * This routine only needs to be called once per application.
+ *
+ * @param cb Callback routine from the application.
+ * @param arg Argument to the application callback routins
+ * @param app_shutdown When set to 1 the application will invoke core_shutdown
+ on each core. When set to 0 core shutdown will be
+ called invoked automatically after invoking the
+ application callback.
+ * @return Return index of app on success, -1 on failure
+ *
+ */
+int cvmx_app_hotplug_register_cb(cvmx_app_hotplug_callbacks_t *cb, void* arg,
+ int app_shutdown)
+{
+ cvmx_app_hotplug_info_t *app_info;
+
+ /* Find the list of applications launched by bootoct utility. */
+ app_info = cvmx_app_hotplug_get_info(cvmx_sysinfo_get()->core_mask);
+ cvmx_app_hotplug_info_ptr = app_info;
+ if (!app_info)
+ {
+ /* Application not launched by bootoct? */
+ printf("ERROR: cmvx_app_hotplug_register() failed\n");
+ return -1;
+ }
+ /* Register the callback */
+ app_info->data = CAST64(arg);
+ app_info->shutdown_callback = CAST64(cb->shutdown_callback);
+ app_info->cores_added_callback = CAST64(cb->cores_added_callback);
+ app_info->cores_removed_callback = CAST64(cb->cores_removed_callback);
+ app_info->unplug_callback = CAST64(cb->unplug_core_callback);
+ app_info->hotplug_start = CAST64(cb->hotplug_start);
+ app_info->app_shutdown = app_shutdown;
+#ifdef DEBUG
+ printf("cvmx_app_hotplug_register(): coremask 0x%x valid %d\n",
+ app_info->coremask, app_info->valid);
+#endif
+
+ cvmx_interrupt_register(CVMX_IRQ_MBOX0, __cvmx_app_hotplug_shutdown, NULL);
+ return 0;
+
+}
+
+void cvmx_app_hotplug_remove_self_from_core_mask(void)
+{
+ int core = cvmx_get_core_num();
+ uint32_t core_mask = 1ull << core;
+
+ cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
+ cvmx_app_hotplug_info_ptr->coremask = cvmx_app_hotplug_info_ptr->coremask & ~core_mask ;
+ cvmx_app_hotplug_info_ptr->hotplug_activated_coremask =
+ cvmx_app_hotplug_info_ptr->hotplug_activated_coremask & ~core_mask ;
+ cvmx_spinlock_unlock(&cvmx_app_hotplug_lock);
+}
+
+
+
+/**
+* Returns 1 if the running core is being unplugged, else it returns 0.
+*/
+int is_core_being_unplugged(void)
+{
+ if (cvmx_app_hotplug_info_ptr->unplug_cores &
+ (1ull << cvmx_get_core_num()))
+ return 1;
+ return 0;
+}
+
+
+/**
+ * Activate the current application core for receiving hotplug shutdown requests.
*
* This routine makes sure that each core belonging to the application is enabled
* to receive the shutdown notification and also provides a barrier sync to make
@@ -108,25 +191,41 @@ int cvmx_app_hotplug_register(void(*fn)(void*), void* arg)
*/
int cvmx_app_hotplug_activate(void)
{
- /* Make sure all application cores are activating */
- __cvmx_app_hotplug_sync();
+ uint64_t cnt = 0;
+ uint64_t cnt_interval = 10000000;
- cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
+ while (!cvmx_app_hotplug_info_ptr)
+ {
+ cnt++;
+ if ((cnt % cnt_interval) == 0)
+ printf("waiting for cnt=%lld\n", (unsigned long long)cnt);
+ }
+ if (cvmx_app_hotplug_info_ptr->hplugged_cores & (1ull << cvmx_get_core_num()))
+ {
+#ifdef DEBUG
+ printf("core=%d : is being hotplugged \n", cvmx_get_core_num());
+#endif
+ cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+ sys_info_ptr->core_mask |= 1ull << cvmx_get_core_num();
+ }
+ else
+ {
+ __cvmx_app_hotplug_sync();
+ }
+ cvmx_spinlock_lock(&cvmx_app_hotplug_lock);
if (!cvmx_app_hotplug_info_ptr)
{
cvmx_spinlock_unlock(&cvmx_app_hotplug_lock);
printf("ERROR: This application is not registered for hotplug\n");
- return -1;
+ return -1;
}
-
/* Enable the interrupt before we mark the core as activated */
cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
-
- cvmx_app_hotplug_info_ptr->hotplug_activated_coremask |= (1<<cvmx_get_core_num());
+ cvmx_app_hotplug_info_ptr->hotplug_activated_coremask |= (1ull<<cvmx_get_core_num());
#ifdef DEBUG
- cvmx_dprintf("cvmx_app_hotplug_activate(): coremask 0x%x valid %d sizeof %d\n",
+ printf("cvmx_app_hotplug_activate(): coremask 0x%x valid %d sizeof %d\n",
cvmx_app_hotplug_info_ptr->coremask, cvmx_app_hotplug_info_ptr->valid,
sizeof(*cvmx_app_hotplug_info_ptr));
#endif
@@ -180,75 +279,196 @@ void cvmx_app_hotplug_shutdown_enable(void)
cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
}
+/**
+* Request shutdown of the currently running core. Should be
+* called by the application when it has been registered with
+* app_shutdown option set to 1.
+*/
+void cvmx_app_hotplug_core_shutdown(void)
+{
+ uint32_t flags;
+ if (cvmx_app_hotplug_info_ptr->shutdown_cores)
+ {
+ cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+ __cvmx_app_hotplug_sync();
+ if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+ {
+ bzero(cvmx_app_hotplug_info_ptr,
+ sizeof(*cvmx_app_hotplug_info_ptr));
+ #ifdef DEBUG
+ printf("__cvmx_app_hotplug_shutdown(): setting shutdown done! \n");
+ #endif
+ cvmx_app_hotplug_info_ptr->shutdown_done = 1;
+ }
+ /* Tell the debugger that this application is finishing. */
+ cvmx_debug_finish ();
+ flags = cvmx_interrupt_disable_save();
+ __cvmx_app_hotplug_sync();
+ /* Reset the core */
+ __cvmx_app_hotplug_reset();
+ }
+ else
+ {
+ cvmx_sysinfo_remove_self_from_core_mask();
+ cvmx_app_hotplug_remove_self_from_core_mask();
+ flags = cvmx_interrupt_disable_save();
+ __cvmx_app_hotplug_reset();
+ }
+}
+
/*
- * ISR for the incoming shutdown request interrupt.
+ * ISR for the incoming shutdown request interrupt.
*/
-static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32], void *user_arg)
+static void __cvmx_app_hotplug_shutdown(int irq_number, uint64_t registers[32],
+ void *user_arg)
{
cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
- uint32_t flags;
+ uint64_t mbox;
+ cvmx_app_hotplug_info_t *ai = cvmx_app_hotplug_info_ptr;
+ int dbg = 0;
+#ifdef DEBUG
+ dbg = 1;
+#endif
cvmx_interrupt_mask_irq(CVMX_IRQ_MBOX0);
+ mbox = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()));
/* Clear the interrupt */
- cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 1);
+ cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), mbox);
/* Make sure the write above completes */
cvmx_read_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()));
+
if (!cvmx_app_hotplug_info_ptr)
{
printf("ERROR: Application is not registered for hotplug!\n");
return;
}
- if (cvmx_app_hotplug_info_ptr->hotplug_activated_coremask != sys_info_ptr->core_mask)
+ if (ai->hotplug_activated_coremask != sys_info_ptr->core_mask)
{
- printf("ERROR: Shutdown requested when not all app cores have activated hotplug\n"
- "Application coremask: 0x%x Hotplug coremask: 0x%x\n", (unsigned int)sys_info_ptr->core_mask,
- (unsigned int)cvmx_app_hotplug_info_ptr->hotplug_activated_coremask);
- return;
+ printf("ERROR: Shutdown requested when not all app cores have "
+ "activated hotplug\n" "Application coremask: 0x%x Hotplug "
+ "coremask: 0x%x\n", (unsigned int)sys_info_ptr->core_mask,
+ (unsigned int)ai->hotplug_activated_coremask);
+ return;
}
- /* Call the application's own callback function */
- ((void(*)(void*))(long)cvmx_app_hotplug_info_ptr->shutdown_callback)(CASTPTR(void *, cvmx_app_hotplug_info_ptr->data));
-
- __cvmx_app_hotplug_sync();
-
- if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+ if (mbox & 1ull)
{
- bzero(cvmx_app_hotplug_info_ptr, sizeof(*cvmx_app_hotplug_info_ptr));
-#ifdef DEBUG
- cvmx_dprintf("__cvmx_app_hotplug_shutdown(): setting shutdown done! \n");
-#endif
- cvmx_app_hotplug_info_ptr->shutdown_done = 1;
+ int core = cvmx_get_core_num();
+ if (dbg)
+ printf("Shutting down application .\n");
+ /* Call the application's own callback function */
+ if (ai->shutdown_callback)
+ {
+ ((void(*)(void*))(long)ai->shutdown_callback)(CASTPTR(void *, ai->data));
+ }
+ else
+ {
+ printf("ERROR : Shutdown callback has not been registered\n");
+ }
+ if (!ai->app_shutdown)
+ {
+ if (dbg)
+ printf("%s : core = %d Invoking app shutdown\n", __FUNCTION__, core);
+ cvmx_app_hotplug_core_shutdown();
+ }
}
+ else if (mbox & 2ull)
+ {
+ int core = cvmx_get_core_num();
+ int unplug = is_core_being_unplugged();
+ if (dbg) printf("%s : core=%d Unplug event \n", __FUNCTION__, core);
- flags = cvmx_interrupt_disable_save();
+ if (unplug)
+ {
+ /* Call the application's own callback function */
+ if (ai->unplug_callback)
+ {
+ if (dbg) printf("%s : core=%d Calling unplug callback\n",
+ __FUNCTION__, core);
+ ((void(*)(void*))(long)ai->unplug_callback)(CASTPTR(void *,
+ ai->data));
+ }
+ if (!ai->app_shutdown)
+ {
+ if (dbg) printf("%s : core = %d Invoking app shutdown\n",
+ __FUNCTION__, core);
+ cvmx_app_hotplug_core_shutdown();
+ }
+ }
+ else
+ {
+ if (ai->cores_removed_callback)
+ {
+ if (dbg) printf("%s : core=%d Calling cores removed callback\n",
+ __FUNCTION__, core);
+ ((void(*)(uint32_t, void*))(long)ai->cores_removed_callback)
+ (ai->unplug_cores, CASTPTR(void *, ai->data));
+ }
+ cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+ }
+ }
+ else if (mbox & 4ull)
+ {
+ int core = cvmx_get_core_num();
+ if (dbg) printf("%s : core=%d Add cores event \n", __FUNCTION__, core);
- __cvmx_app_hotplug_sync();
+ if (ai->cores_added_callback)
+ {
+ if (dbg) printf("%s : core=%d Calling cores added callback\n",
+ __FUNCTION__, core);
+ ((void(*)(uint32_t, void*))(long)ai->cores_added_callback)
+ (ai->hplugged_cores, CASTPTR(void *, ai->data));
+ }
+ cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+ }
+ else
+ {
+ printf("ERROR: unexpected mbox=%llx\n", (unsigned long long)mbox);
+ }
- /* Reset the core */
- __cvmx_app_hotplug_reset();
}
-/*
- * Reset the core. We just jump back to the reset vector for now.
- */
void __cvmx_app_hotplug_reset(void)
{
- /* Code from SecondaryCoreLoop from bootloader, sleep until we recieve
- a NMI. */
- __asm__ volatile (
- ".set noreorder \n"
- "\tsync \n"
- "\tnop \n"
- "1:\twait \n"
- "\tb 1b \n"
- "\tnop \n"
- ".set reorder \n"
- ::
- );
+#define IDLE_CORE_BLOCK_NAME "idle-core-loop"
+#define HPLUG_MAKE_XKPHYS(x) ((1ULL << 63) | (x))
+ uint64_t reset_addr;
+ const cvmx_bootmem_named_block_desc_t *block_desc;
+
+ block_desc = cvmx_bootmem_find_named_block(IDLE_CORE_BLOCK_NAME);
+ if (!block_desc) {
+ cvmx_dprintf("Named block(%s) is not created\n", IDLE_CORE_BLOCK_NAME);
+ /* loop here, should not happen */
+ __asm__ volatile (
+ ".set noreorder \n"
+ "\tsync \n"
+ "\tnop \n"
+ "1:\twait \n"
+ "\tb 1b \n"
+ "\tnop \n"
+ ".set reorder \n"
+ ::
+ );
+ }
+
+ reset_addr = HPLUG_MAKE_XKPHYS(block_desc->base_addr);
+ asm volatile (" .set push \n"
+ " .set mips64 \n"
+ " .set noreorder \n"
+ " move $2, %[addr] \n"
+ " jr $2 \n"
+ " nop \n"
+ " .set pop "
+ :: [addr] "r"(reset_addr)
+ : "$2");
+
+ /*Should never reach here*/
+ while (1) ;
+
}
/*
@@ -268,34 +488,47 @@ static void __cvmx_app_hotplug_sync(void)
cvmx_spinlock_unlock(&cvmx_app_hotplug_sync_lock);
while (sync_coremask != sys_info_ptr->core_mask);
+
+ cvmx_spinlock_lock(&cvmx_app_hotplug_sync_lock);
+ sync_coremask = 0;
+ cvmx_spinlock_unlock(&cvmx_app_hotplug_sync_lock);
+
+
}
#endif /* CVMX_BUILD_FOR_LINUX_USER */
/**
- * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the
- * application running on the given coremask.
- *
- * @param coremask Coremask of application.
- * @return Returns hotplug info struct on success, NULL on failure
- *
- */
-cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
+* Returns 1 if the running core is being hotplugged, else it returns 0.
+*/
+int is_core_being_hot_plugged(void)
+{
+
+#ifndef CVMX_BUILD_FOR_LINUX_USER
+ if (!cvmx_app_hotplug_info_ptr) return 0;
+ if (cvmx_app_hotplug_info_ptr->hplugged_cores &
+ (1ull << cvmx_get_core_num()))
+ return 1;
+ return 0;
+#else
+ return 0;
+#endif
+}
+
+static cvmx_app_hotplug_global_t *cvmx_app_get_hotplug_global_ptr(void)
{
const struct cvmx_bootmem_named_block_desc *block_desc;
- cvmx_app_hotplug_info_t *hip;
cvmx_app_hotplug_global_t *hgp;
- int i;
- block_desc = cvmx_bootmem_find_named_block(CVMX_APP_HOTPLUG_INFO_REGION_NAME);
+ if(hotplug_global_ptr != 0) return hotplug_global_ptr;
+ block_desc = cvmx_bootmem_find_named_block(CVMX_APP_HOTPLUG_INFO_REGION_NAME);
if (!block_desc)
{
printf("ERROR: Hotplug info region is not setup\n");
return NULL;
}
else
-
#ifdef CVMX_BUILD_FOR_LINUX_USER
{
size_t pg_sz = sysconf(_SC_PAGESIZE), size;
@@ -314,7 +547,8 @@ cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
*/
size = CVMX_APP_HOTPLUG_INFO_REGION_SIZE + pg_sz-1;
offset = block_desc->base_addr & ~(pg_sz-1);
- if ((vaddr = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset)) == MAP_FAILED)
+ if ((vaddr = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset))
+ == MAP_FAILED)
{
perror("mmap");
return NULL;
@@ -323,35 +557,143 @@ cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
hgp = (cvmx_app_hotplug_global_t *)(vaddr + ( block_desc->base_addr & (pg_sz-1)));
}
#else
- hgp = cvmx_phys_to_ptr(block_desc->base_addr);
+ hgp = CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, block_desc->base_addr));
#endif
+ hotplug_global_ptr = hgp;
+ return hgp;
- hip = hgp->hotplug_info_array;
+}
+
+/**
+ * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the
+ * application running on the given coremask.
+ *
+ * @param coremask Coremask of application.
+ * @return Returns hotplug info struct on success, NULL on failure
+ *
+ */
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t coremask)
+{
+ cvmx_app_hotplug_info_t *hip;
+ cvmx_app_hotplug_global_t *hgp;
+ int i;
+ int dbg = 0;
#ifdef DEBUG
- cvmx_dprintf("cvmx_app_hotplug_get_info(): hotplug_info phy addr 0x%llx ptr %p\n",
- block_desc->base_addr, hgp);
+ dbg = 1;
#endif
+ hgp = cvmx_app_get_hotplug_global_ptr();
+ if (!hgp) return NULL;
+ hip = hgp->hotplug_info_array;
/* Look for the current app's info */
-
for (i=0; i<CVMX_APP_HOTPLUG_MAX_APPS; i++)
{
if (hip[i].coremask == coremask)
- {
+ {
+ if (dbg)
+ printf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x, valid %d\n", i, (unsigned int)hip[i].coremask, (unsigned int)hip[i].valid);
+ return &hip[i];
+ }
+ }
+ return NULL;
+}
+
+/**
+ * Return the hotplug application index structure for the application running on the
+ * given coremask.
+ *
+ * @param coremask Coremask of application.
+ * @return Returns hotplug application index on success. -1 on failure
+ *
+ */
+int cvmx_app_hotplug_get_index(uint32_t coremask)
+{
+ cvmx_app_hotplug_info_t *hip;
+ cvmx_app_hotplug_global_t *hgp;
+ int i;
+ int dbg = 0;
+
#ifdef DEBUG
- cvmx_dprintf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x valid %d\n",
- i, hip[i].coremask, hip[i].valid);
+ dbg = 1;
#endif
+ hgp = cvmx_app_get_hotplug_global_ptr();
+ if (!hgp) return -1;
+ hip = hgp->hotplug_info_array;
- return &hip[i];
- }
+ /* Look for the current app's info */
+ for (i=0; i<CVMX_APP_HOTPLUG_MAX_APPS; i++)
+ {
+ if (hip[i].coremask == coremask)
+ {
+ if (dbg)
+ printf("cvmx_app_hotplug_get_info(): coremask match %d -- coremask 0x%x valid %d\n", i, (unsigned int)hip[i].coremask, (unsigned int)hip[i].valid);
+ return i;
+ }
}
+ return -1;
+}
+
+void print_hot_plug_info(cvmx_app_hotplug_info_t* hpinfo)
+{
+ printf("name=%s coremask=%08x hotplugged coremask=%08x valid=%d\n", hpinfo->app_name,
+ (unsigned int)hpinfo->coremask, (unsigned int)hpinfo->hotplug_activated_coremask, (unsigned int)hpinfo->valid);
+}
+/**
+ * Return the hotplug info structure (cvmx_app_hotplug_info_t) pointer for the
+ * application with the specified index.
+ *
+ * @param index index of application.
+ * @return Returns hotplug info struct on success, NULL on failure
+ *
+ */
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info_at_index(int index)
+{
+ cvmx_app_hotplug_info_t *hip;
+ cvmx_app_hotplug_global_t *hgp;
+
+ hgp = cvmx_app_get_hotplug_global_ptr();
+ if (!hgp) return NULL;
+ hip = hgp->hotplug_info_array;
+
+#ifdef DEBUG
+ printf("cvmx_app_hotplug_get_info(): hotplug_info phy addr 0x%llx ptr %p\n",
+ block_desc->base_addr, hgp);
+#endif
+ if (index < CVMX_APP_HOTPLUG_MAX_APPS)
+ {
+ if (hip[index].valid)
+ {
+ //print_hot_plug_info( &hip[index] );
+ return &hip[index];
+ }
+ }
return NULL;
}
/**
+ * Determines if SE application at the index specified is hotpluggable.
+ *
+ * @param index index of application.
+ * @return Returns -1 on error.
+ * 0 -> The application is not hotpluggable
+ * 1 -> The application is hotpluggable
+*/
+int is_app_hotpluggable(int index)
+{
+ cvmx_app_hotplug_info_t *ai;
+
+ if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+ {
+ printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+ return -1;
+ }
+ if (ai->hotplug_activated_coremask) return 1;
+ return 0;
+}
+
+/**
* This routine sends a shutdown request to a running target application.
*
* @param coremask Coremask the application is running on.
@@ -371,7 +713,7 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
printf("\nERROR: Failed to get hotplug info for coremask: 0x%x\n", (unsigned int)coremask);
return -1;
}
-
+ hotplug_info_ptr->shutdown_cores = coremask;
if (!hotplug_info_ptr->shutdown_callback)
{
printf("\nERROR: Target application has not registered for hotplug!\n");
@@ -386,8 +728,8 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
/* Send IPIs to all application cores to request shutdown */
for (i=0; i<CVMX_MAX_CORES; i++) {
- if (coremask & (1<<i))
- cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 1);
+ if (coremask & (1ull<<i))
+ cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 1);
}
if (wait)
@@ -400,3 +742,144 @@ int cvmx_app_hotplug_shutdown_request(uint32_t coremask, int wait)
return 0;
}
+
+
+
+/**
+ * This routine invokes the invoked the cores_added callbacks.
+ */
+int cvmx_app_hotplug_call_add_cores_callback(int index)
+{
+ cvmx_app_hotplug_info_t *ai;
+ int i;
+ if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+ {
+ printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+ return -1;
+ }
+ /* Send IPIs to all application cores to request add_cores callback*/
+ for (i=0; i<CVMX_MAX_CORES; i++) {
+ if (ai->coremask & (1ull<<i))
+ cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 4);
+ }
+ return 0;
+}
+
+/**
+ * This routine sends a request to a running target application
+ * to unplug a specified set cores
+ * @param index is the index of the target application
+ * @param coremask Coremask of the cores to be unplugged from the app.
+ * @param wait 1 - Wait for shutdown completion
+ * 0 - Do not wait
+ * @return 0 on success, -1 on error
+ *
+ */
+int cvmx_app_hotplug_unplug_cores(int index, uint32_t coremask, int wait)
+{
+ cvmx_app_hotplug_info_t *ai;
+ int i;
+
+ if (!(ai = cvmx_app_hotplug_get_info_at_index(index)))
+ {
+ printf("\nERROR: Failed to get hotplug info for app at index=%d\n", index);
+ return -1;
+ }
+ ai->unplug_cores = coremask;
+#if 0
+ if (!ai->shutdown_callback)
+ {
+ printf("\nERROR: Target application has not registered for hotplug!\n");
+ return -1;
+ }
+#endif
+ if ( (ai->coremask | coremask ) != ai->coremask)
+ {
+ printf("\nERROR: Not all cores requested are a part of the app "
+ "r=%08x:%08x\n", (unsigned int)coremask, (unsigned int)ai->coremask);
+ return -1;
+ }
+ if (ai->coremask == coremask)
+ {
+ printf("\nERROR: Trying to remove all cores in app. "
+ "r=%08x:%08x\n", (unsigned int)coremask, (unsigned int)ai->coremask);
+ return -1;
+ }
+ /* Send IPIs to all application cores to request unplug/remove_cores
+ callback */
+ for (i=0; i<CVMX_MAX_CORES; i++) {
+ if (ai->coremask & (1ull<<i))
+ cvmx_write_csr(CVMX_CIU_MBOX_SETX(i), 2);
+ }
+
+#if 0
+ if (wait)
+ {
+ while (!ai->shutdown_done);
+
+ /* Clean up the hotplug info region for this application */
+ bzero(ai, sizeof(*ai));
+ }
+#endif
+ return 0;
+}
+
+/**
+ * Returns 1 if any app is currently being currently booted , hotplugged or
+ * shutdown. Only one app can be under a boot, hotplug or shutdown condition.
+ * Before booting an app this methods should be used to check whether boot or
+ * shutdown activity is in progress and proceed with the boot or shutdown only
+ * when there is no other activity.
+ *
+ */
+int is_app_under_boot_or_shutdown(void)
+{
+ int ret=0;
+ cvmx_app_hotplug_global_t *hgp;
+
+ hgp = cvmx_app_get_hotplug_global_ptr();
+ cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+ if (hgp->app_under_boot || hgp->app_under_shutdown) ret=1;
+ cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+ return ret;
+
+}
+
+/**
+ * Sets or clear the app_under_boot value. This when set signifies that an app
+ * is being currently booted or hotplugged with a new core.
+ *
+ *
+ * @param val sets the app_under_boot to the specified value. This should be
+ * set to 1 while app any is being booted and cleared after the
+ * application has booted up.
+ *
+ */
+void set_app_unber_boot(int val)
+{
+ cvmx_app_hotplug_global_t *hgp;
+
+ hgp = cvmx_app_get_hotplug_global_ptr();
+ cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+ hgp->app_under_boot = val;
+ cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+}
+
+/**
+ * Sets or clear the app_under_shutdown value. This when set signifies that an
+ * app is being currently shutdown or some cores of an app are being shutdown.
+ *
+ * @param val sets the app_under_shutdown to the specified value. This
+ * should be set to 1 while any app is being shutdown and cleared
+ * after the shutdown of the app is complete.
+ *
+ */
+void set_app_under_shutdown(int val)
+{
+ cvmx_app_hotplug_global_t *hgp;
+
+ hgp = cvmx_app_get_hotplug_global_ptr();
+ cvmx_spinlock_lock(&hgp->hotplug_global_lock);
+ hgp->app_under_shutdown = val;
+ cvmx_spinlock_unlock(&hgp->hotplug_global_lock);
+}
diff --git a/cvmx-app-hotplug.h b/cvmx-app-hotplug.h
index bfa62f8c35a8..4e251bbc029f 100644
--- a/cvmx-app-hotplug.h
+++ b/cvmx-app-hotplug.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,47 +48,99 @@
#ifndef __CVMX_APP_HOTPLUG_H__
#define __CVMX_APP_HOTPLUG_H__
-#ifdef __cplusplus
+#ifdef __cplusplus
extern "C" {
#endif
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
#include <asm/octeon/cvmx.h>
#include <asm/octeon/cvmx-bootmem.h>
+#include <asm/octeon/cvmx-spinlock.h>
#else
#include "cvmx.h"
#include "cvmx-coremask.h"
#include "cvmx-interrupt.h"
#include "cvmx-bootmem.h"
+#include "cvmx-spinlock.h"
#endif
#define CVMX_APP_HOTPLUG_MAX_APPS 32
#define CVMX_APP_HOTPLUG_MAX_APPNAME_LEN 256
+/**
+* hotplug_start is the entry point for hot plugged cores.
+* cores_added_callback is callback which in invoked when new cores are added
+* to the application. This is invoked on all the old core
+* that existed before the current set of cores were
+* added.
+* cores_removed_callback is callback which in invoked when cores are removed
+* an application. This is invoked on all the cores that
+* exist after the set of cores being requesed are
+* removed.
+* shutdown_done_callback before the application is shutdown this callback is
+* invoked on all the cores that are part of the app.
+* unplug_callback before the cores are unplugged this callback is invoked
+* only on the cores that are being unlpuuged.
+*/
+typedef struct cvmx_app_hotplug_callbacks
+{
+ void (*hotplug_start)(void *ptr);
+ void (*cores_added_callback) (uint32_t ,void *ptr);
+ void (*cores_removed_callback) (uint32_t,void *ptr);
+ void (*shutdown_callback) (void *ptr);
+ void (*unplug_core_callback) (void *ptr);
+} cvmx_app_hotplug_callbacks_t;
+
+/* The size of this struct should be a fixed size of 1024 bytes.
+ Additional members should be added towards the end of the
+ strcuture by adjusting the size of padding */
typedef struct cvmx_app_hotplug_info
{
- char app_name[CVMX_APP_HOTPLUG_MAX_APPNAME_LEN];
- uint32_t coremask;
- uint32_t volatile hotplug_activated_coremask;
- int32_t valid;
- int32_t volatile shutdown_done;
- uint64_t shutdown_callback;
- uint64_t data;
+ char app_name[CVMX_APP_HOTPLUG_MAX_APPNAME_LEN];
+ uint32_t coremask;
+ uint32_t volatile hotplug_activated_coremask;
+ int32_t valid;
+ int32_t volatile shutdown_done;
+ uint64_t shutdown_callback;
+ uint64_t unplug_callback;
+ uint64_t cores_added_callback;
+ uint64_t cores_removed_callback;
+ uint64_t hotplug_start;
+ uint64_t data;
+ uint32_t volatile hplugged_cores;
+ uint32_t shutdown_cores;
+ uint32_t app_shutdown;
+ uint32_t unplug_cores;
+ uint32_t padding[172];
} cvmx_app_hotplug_info_t;
struct cvmx_app_hotplug_global
{
uint32_t avail_coremask;
cvmx_app_hotplug_info_t hotplug_info_array[CVMX_APP_HOTPLUG_MAX_APPS];
+ uint32_t version;
+ cvmx_spinlock_t hotplug_global_lock;
+ int app_under_boot;
+ int app_under_shutdown;
};
-
typedef struct cvmx_app_hotplug_global cvmx_app_hotplug_global_t;
+int is_core_being_hot_plugged(void);
+int is_app_being_booted_or_shutdown(void);
+void set_app_unber_boot(int val);
+void set_app_under_shutdown(int val);
int cvmx_app_hotplug_shutdown_request(uint32_t, int);
+int cvmx_app_hotplug_unplug_cores(int index, uint32_t coremask, int wait);
cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info(uint32_t);
+int cvmx_app_hotplug_get_index(uint32_t coremask);
+cvmx_app_hotplug_info_t* cvmx_app_hotplug_get_info_at_index(int index);
+int is_app_hotpluggable(int index);
+int cvmx_app_hotplug_call_add_cores_callback(int index);
#ifndef CVMX_BUILD_FOR_LINUX_USER
int cvmx_app_hotplug_register(void(*)(void*), void*);
+int cvmx_app_hotplug_register_cb(cvmx_app_hotplug_callbacks_t *, void*, int);
int cvmx_app_hotplug_activate(void);
+void cvmx_app_hotplug_core_shutdown(void);
void cvmx_app_hotplug_shutdown_disable(void);
void cvmx_app_hotplug_shutdown_enable(void);
#endif
@@ -96,7 +148,7 @@ void cvmx_app_hotplug_shutdown_enable(void);
#define CVMX_APP_HOTPLUG_INFO_REGION_SIZE sizeof(cvmx_app_hotplug_global_t)
#define CVMX_APP_HOTPLUG_INFO_REGION_NAME "cvmx-app-hotplug-block"
-#ifdef __cplusplus
+#ifdef __cplusplus
}
#endif
diff --git a/cvmx-app-init-linux.c b/cvmx-app-init-linux.c
index 73726df953e0..aeb42cb9bcd1 100644
--- a/cvmx-app-init-linux.c
+++ b/cvmx-app-init-linux.c
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -61,7 +61,7 @@
* -# Most hardware can only be initialized once. Unless you're very careful,
* this also means you Linux application can only run once.
*
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70129 $<hr>
*
*/
#define _GNU_SOURCE
@@ -88,6 +88,7 @@
#include "cvmx-coremask.h"
#include "cvmx-spinlock.h"
#include "cvmx-bootmem.h"
+#include "cvmx-helper-cfg.h"
int octeon_model_version_check(uint32_t chip_id);
@@ -326,7 +327,6 @@ int main(int argc, const char *argv[])
int firstcore = 0;
cvmx_linux_enable_xkphys_access(0);
-
cvmx_sysinfo_linux_userspace_initialize();
if (sizeof(void*) == 4)
@@ -349,6 +349,10 @@ int main(int argc, const char *argv[])
/* Check to make sure the Chip version matches the configured version */
octeon_model_version_check(cvmx_get_proc_id());
+ /* Initialize configuration to set bpid, pkind, pko_port for all the
+ available ports connected. */
+ __cvmx_helper_cfg_init();
+
/* Get the list of logical cpus we should run on */
if (sched_getaffinity(0, sizeof(cpumask), (cpu_set_t*)&cpumask))
{
@@ -362,7 +366,7 @@ int main(int argc, const char *argv[])
/* Get the lowest logical cpu */
firstcore = ffsl(cpumask) - 1;
- cpumask ^= (1<<(firstcore));
+ cpumask ^= (1ull<<(firstcore));
while (1)
{
if (cpumask == 0)
@@ -373,9 +377,9 @@ int main(int argc, const char *argv[])
}
cpu = ffsl(cpumask) - 1;
/* Turn off the bit for this CPU number. We've counted him */
- cpumask ^= (1<<cpu);
+ cpumask ^= (1ull<<cpu);
/* Increment the number of CPUs running this app */
- cvmx_atomic_add32(&pending_fork, 1);
+ cvmx_atomic_add32(&pending_fork, 1);
/* Flush all IO streams before the fork. Otherwise any buffered
data in the C library will be duplicated. This results in
duplicate output from a single print */
@@ -406,7 +410,9 @@ int main(int argc, const char *argv[])
system_info->core_mask |= 1<<cvmx_get_core_num();
cvmx_atomic_add32(&pending_fork, -1);
if (cvmx_atomic_get32(&pending_fork) == 0)
+ {
cvmx_dprintf("Active coremask = 0x%x\n", system_info->core_mask);
+ }
if (firstcpu)
system_info->init_core = cvmx_get_core_num();
cvmx_spinlock_unlock(&mask_lock);
diff --git a/cvmx-app-init.c b/cvmx-app-init.c
index 885e36ef8787..75e51561f49a 100644
--- a/cvmx-app-init.c
+++ b/cvmx-app-init.c
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,6 +47,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
+#include "executive-config.h"
#include "cvmx-config.h"
#include "cvmx.h"
#include "cvmx-spinlock.h"
@@ -60,8 +61,12 @@
#include "cvmx-ebt3000.h"
#include "cvmx-sim-magic.h"
#include "cvmx-debug.h"
-#include "../../bootloader/u-boot/include/octeon_mem_map.h"
-
+#include "cvmx-qlm.h"
+#include "cvmx-scratch.h"
+#include "cvmx-helper-cfg.h"
+#include "cvmx-helper-jtag.h"
+#include <octeon_mem_map.h>
+#include "libfdt.h"
int cvmx_debug_uart = -1;
/**
@@ -184,6 +189,20 @@ static void process_boot_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr, cvmx
(int)cvmx_bootinfo_ptr->major_version, (int)cvmx_bootinfo_ptr->minor_version);
exit(-1);
}
+ if ((cvmx_bootinfo_ptr->minor_version >= 3) && (cvmx_bootinfo_ptr->fdt_addr != 0))
+ {
+ sys_info_ptr->fdt_addr = UNMAPPED_PTR(cvmx_bootinfo_ptr->fdt_addr);
+ if (fdt_check_header((const void *)sys_info_ptr->fdt_addr))
+ {
+ printf("ERROR : Corrupt Device Tree.\n");
+ exit(-1);
+ }
+ printf("Using device tree\n");
+ }
+ else
+ {
+ sys_info_ptr->fdt_addr = 0;
+ }
}
@@ -211,18 +230,18 @@ static void process_break_interrupt(int irq_number, uint64_t registers[32], void
{
register uint64_t tmp;
- /* Wait for an another Control-C if right now we have no
- access to the console. After this point we hold the
- lock and use a different lock to synchronize between
- the memfile dumps from different cores. As a
- consequence regular printfs *don't* work after this
- point! */
- if (__octeon_uart_trylock () == 1)
- return;
+ /* Wait for an another Control-C if right now we have no
+ access to the console. After this point we hold the
+ lock and use a different lock to synchronize between
+ the memfile dumps from different cores. As a
+ consequence regular printfs *don't* work after this
+ point! */
+ if (__octeon_uart_trylock () == 1)
+ return;
/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also
- set the MCD0 to be not masked by this core so we know
- the signal is received by someone */
+ set the MCD0 to be not masked by this core so we know
+ the signal is received by someone */
asm volatile (
"dmfc0 %0, $22\n"
"ori %0, %0, 0x1110\n"
@@ -270,6 +289,7 @@ char octeon_rev_signature[] =
"Compiled for Octeon processor id: "OMS;
#endif
+#define OCTEON_BL_FLAG_HPLUG_CORES (1 << 6)
void __cvmx_app_init(uint64_t app_desc_addr)
{
/* App descriptor used by bootloader */
@@ -279,8 +299,16 @@ void __cvmx_app_init(uint64_t app_desc_addr)
cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
int breakflag = 0;
+ //printf("coremask=%08x flags=%08x \n", app_desc_ptr->core_mask, app_desc_ptr->flags);
if (cvmx_coremask_first_core(app_desc_ptr->core_mask))
{
+ /* Intialize the bootmem allocator with the descriptor that was provided by
+ * the bootloader
+ * IMPORTANT: All printfs must happen after this since PCI console uses named
+ * blocks.
+ */
+ cvmx_bootmem_init(CASTPTR(cvmx_bootinfo_t, app_desc_ptr->cvmx_desc_vaddr)->phy_mem_desc_addr);
+
/* do once per application setup */
if (app_desc_ptr->desc_version < 6)
{
@@ -297,8 +325,34 @@ void __cvmx_app_init(uint64_t app_desc_addr)
process_boot_desc_ver_6(app_desc_ptr,sys_info_ptr);
}
+
+ /*
+ * set up the feature map and config.
+ */
+ octeon_feature_init();
+
+ __cvmx_helper_cfg_init();
}
- cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+ /* The flags varibale get copied over at some places and tracing the origins
+ found that
+ ** In octeon_setup_boot_desc_block
+ . cvmx_bootinfo_array[core].flags is initialized and the various bits are set
+ . cvmx_bootinfo_array[core].flags gets copied to boot_desc[core].flags
+ . Then boot_desc then get copied over to the end of the application heap and
+ boot_info_block_array[core].boot_descr_addr is set to point to the boot_desc
+ in heap.
+ ** In start_app boot_vect->boot_info_addr->boot_desc_addr is referenced and passed on
+ to octeon_setup_crt0_tlb() and this puts it into r16
+ ** In ctr0.S of the toolchain r16 is picked up and passed on as a parameter to
+ __cvmx_app_init
+
+ Note : boot_vect->boot_info_addr points to boot_info_block_array[core] and this
+ pointer is setup in octeon_setup_boot_vector()
+ */
+
+ if (!(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+ cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+
breakflag = sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_BREAK;
@@ -311,20 +365,12 @@ void __cvmx_app_init(uint64_t app_desc_addr)
/* Make sure we can properly run on this chip */
octeon_model_version_check(chip_id);
}
-
cvmx_interrupt_initialize();
-
if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
{
int break_uart = 0;
unsigned int i;
- /* Intialize the bootmem allocator with the descriptor that was provided by
- * the bootloader
- * IMPORTANT: All printfs must happen after this since PCI console uses named
- * blocks.
- */
- cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_addr);
if (breakflag && cvmx_debug_booted())
{
printf("ERROR: Using debug and break together in not supported.\n");
@@ -350,8 +396,8 @@ void __cvmx_app_init(uint64_t app_desc_addr)
cvmx_uart_enable_intr(break_uart, process_break_interrupt);
}
}
-
- cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+ if ( !(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+ cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
/* Clear BEV now that we have installed exception handlers. */
uint64_t tmp;
@@ -375,13 +421,13 @@ void __cvmx_app_init(uint64_t app_desc_addr)
"dmtc0 %0, $22, 0\n" : "=r" (tmp));
CVMX_SYNC;
-
/* Now intialize the debug exception handler as BEV is cleared. */
- if (!breakflag)
+ if ((!breakflag) && (!(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES)))
cvmx_debug_init();
/* Synchronise all cores at this point */
- cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+ if ( !(app_desc_ptr->flags & OCTEON_BL_FLAG_HPLUG_CORES))
+ cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
}
@@ -396,11 +442,11 @@ int cvmx_user_app_init(void)
/* Put message on LED display */
if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
- ebt3000_str_write("CVMX ");
+ ebt3000_str_write("CVMX ");
/* Check BIST results for COP0 registers, some values only meaningful in pass 2 */
CVMX_MF_CACHE_ERR(bist_val);
- mask = (1ULL<<32) | (1ULL<<33) | (1ULL<<34) | (1ULL<<35) | (1ULL<<36);
+ mask = (0x3fULL<<32); // Icache;BHT;AES;HSH/GFM;LRU;register file
bist_val &= mask;
if (bist_val)
{
@@ -429,6 +475,17 @@ int cvmx_user_app_init(void)
}
CVMX_MT_CVM_MEM_CTL(tmp);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X))
+ {
+ /* Clear the lines of scratch memory configured, for
+ ** 63XX pass 2 errata Core-15169. */
+ uint64_t addr;
+ unsigned num_lines;
+ CVMX_MF_CVM_MEM_CTL(tmp);
+ num_lines = tmp & 0x3f;
+ for (addr = 0; addr < CVMX_CACHE_LINE_SIZE * num_lines; addr += 8)
+ cvmx_scratch_write64(addr, 0);
+ }
#if CVMX_USE_1_TO_1_TLB_MAPPINGS
@@ -475,7 +532,7 @@ int cvmx_user_app_init(void)
printf("ERROR adding 1-1 TLB mapping for address 0x%llx\n", (unsigned long long)base_addr);
/* Exit from here, as expected memory mappings aren't set
up if this fails */
- exit(-1);
+ exit(-1);
}
}
}
@@ -507,6 +564,10 @@ int cvmx_user_app_init(void)
cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_addr);
+ /* Initialize QLM and JTAG settings. Also apply any erratas. */
+ if (cvmx_coremask_first_core(cvmx_sysinfo_get()->core_mask))
+ cvmx_qlm_init();
+
return(0);
}
@@ -516,7 +577,7 @@ void __cvmx_app_exit(void)
if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
{
- CVMX_BREAK;
+ CVMX_BREAK;
}
/* Hang forever, until more appropriate stand alone simple executive
exit() is implemented */
diff --git a/cvmx-app-init.h b/cvmx-app-init.h
index f3f01fd957ce..c30bc9715aa9 100644
--- a/cvmx-app-init.h
+++ b/cvmx-app-init.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -46,7 +46,7 @@
* @file
* Header file for simple executive application initialization. This defines
* part of the ABI between the bootloader and the application.
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70327 $<hr>
*
*/
@@ -62,7 +62,7 @@ extern "C" {
** from the bootloader to the application. This is versioned so that applications
** can properly handle multiple bootloader versions. */
#define CVMX_BOOTINFO_MAJ_VER 1
-#define CVMX_BOOTINFO_MIN_VER 2
+#define CVMX_BOOTINFO_MIN_VER 3
#if (CVMX_BOOTINFO_MAJ_VER == 1)
@@ -76,6 +76,7 @@ extern "C" {
** to 0.
*/
struct cvmx_bootinfo {
+#ifdef __BIG_ENDIAN_BITFIELD
uint32_t major_version;
uint32_t minor_version;
@@ -120,8 +121,70 @@ struct cvmx_bootinfo {
uint32_t config_flags; /**< flags indicating various configuration options. These flags supercede
** the 'flags' variable and should be used instead if available */
#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+ uint64_t fdt_addr; /**< Address of the OF Flattened Device Tree structure describing the board. */
+#endif
+#else /* __BIG_ENDIAN */
+ /*
+ * Little-Endian: When the CPU mode is switched to
+ * little-endian, the view of the structure has some of the
+ * fields swapped.
+ */
+ uint32_t minor_version;
+ uint32_t major_version;
+
+ uint64_t stack_top;
+ uint64_t heap_base;
+ uint64_t heap_end;
+ uint64_t desc_vaddr;
+
+ uint32_t stack_size;
+ uint32_t exception_base_addr;
+
+ uint32_t core_mask;
+ uint32_t flags;
+
+ uint32_t phy_mem_desc_addr;
+ uint32_t dram_size;
+
+ uint32_t eclock_hz;
+ uint32_t debugger_flags_base_addr;
+
+ uint32_t reserved0;
+ uint32_t dclock_hz;
+
+ uint8_t reserved3;
+ uint8_t reserved2;
+ uint16_t reserved1;
+ uint8_t board_rev_minor;
+ uint8_t board_rev_major;
+ uint16_t board_type;
+
+ union cvmx_bootinfo_scramble {
+ /* Must byteswap these four words so that...*/
+ uint64_t s[4];
+ /* ... this strucure has the proper data arrangement. */
+ struct {
+ char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+ uint8_t mac_addr_base[6];
+ uint8_t mac_addr_count;
+ uint8_t pad[5];
+ } le;
+ } scramble1;
-
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+ uint64_t compact_flash_common_base_addr;
+ uint64_t compact_flash_attribute_base_addr;
+ uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+ uint32_t config_flags;
+ uint32_t dfa_ref_clock_hz;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+ uint64_t fdt_addr;
+#endif
+#endif
};
typedef struct cvmx_bootinfo cvmx_bootinfo_t;
@@ -145,7 +208,7 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_EBT3000 = 2,
CVMX_BOARD_TYPE_KODAMA = 3,
CVMX_BOARD_TYPE_NIAGARA = 4, /* Obsolete, no longer supported */
- CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
+ CVMX_BOARD_TYPE_NAC38 = 5, /* Obsolete, no longer supported */
CVMX_BOARD_TYPE_THUNDER = 6,
CVMX_BOARD_TYPE_TRANTOR = 7, /* Obsolete, no longer supported */
CVMX_BOARD_TYPE_EBH3000 = 8,
@@ -178,7 +241,18 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_LANAI2_G = 35,
CVMX_BOARD_TYPE_EBT5810 = 36,
CVMX_BOARD_TYPE_NIC10E = 37,
+ CVMX_BOARD_TYPE_EP6300C = 38,
+ CVMX_BOARD_TYPE_EBB6800 = 39,
+ CVMX_BOARD_TYPE_NIC4E = 40,
+ CVMX_BOARD_TYPE_NIC2E = 41,
+ CVMX_BOARD_TYPE_EBB6600 = 42,
+ CVMX_BOARD_TYPE_REDWING = 43,
+ CVMX_BOARD_TYPE_NIC68_4 = 44,
+ CVMX_BOARD_TYPE_NIC10E_66 = 45,
+ CVMX_BOARD_TYPE_EBB6100 = 46,
+ CVMX_BOARD_TYPE_EVB7100 = 47,
CVMX_BOARD_TYPE_MAX,
+ /* NOTE: 256-257 are being used by a customer. */
/* The range from CVMX_BOARD_TYPE_MAX to CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved
** for future SDK use. */
@@ -227,7 +301,7 @@ enum cvmx_board_types_enum {
CVMX_BOARD_TYPE_MODULE_EBB5600_QLM1 = 30008,
CVMX_BOARD_TYPE_MODULE_EBB5600_QLM2 = 30009,
CVMX_BOARD_TYPE_MODULE_EBB5600_QLM3 = 30010,
- CVMX_BOARD_TYPE_MODULE_MAX = 31000,
+ CVMX_BOARD_TYPE_MODULE_MAX = 31000
/* The remaining range is reserved for future use. */
};
@@ -235,7 +309,7 @@ enum cvmx_chip_types_enum {
CVMX_CHIP_TYPE_NULL = 0,
CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
- CVMX_CHIP_TYPE_MAX,
+ CVMX_CHIP_TYPE_MAX
};
/* Compatability alias for NAC38 name change, planned to be removed from SDK 1.7 */
@@ -285,6 +359,16 @@ static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum t
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6100)
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EVB7100)
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
/* Customer boards listed here */
diff --git a/cvmx-asm.h b/cvmx-asm.h
index 24c94a6bc9d0..a35ff4aeba63 100644
--- a/cvmx-asm.h
+++ b/cvmx-asm.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,13 +48,15 @@
*
* This is file defines ASM primitives for the executive.
- * <hr>$Revision: 52004 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*
*
*/
#ifndef __CVMX_ASM_H__
#define __CVMX_ASM_H__
+#define CVMX_MAX_CORES (32)
+
#define COP0_INDEX $0,0 /* TLB read/write index */
#define COP0_RANDOM $1,0 /* TLB random index */
#define COP0_ENTRYLO0 $2,0 /* TLB entryLo0 */
@@ -111,8 +113,6 @@
things under !__ASSEMBLER__. */
#ifndef __ASSEMBLER__
-#include "octeon-model.h"
-
#ifdef __cplusplus
extern "C" {
#endif
@@ -121,10 +121,9 @@ extern "C" {
#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
#define CVMX_TMP_STR2(x) #x
-#if !OCTEON_IS_COMMON_BINARY()
- #if CVMX_COMPILED_FOR(OCTEON_CN63XX)
- #define CVMX_CAVIUM_OCTEON2
- #endif
+/* Since sync is required for Octeon2. */
+#ifdef _MIPS_ARCH_OCTEON2
+#define CVMX_CAVIUM_OCTEON2 1
#endif
/* other useful stuff */
@@ -139,9 +138,7 @@ extern "C" {
#endif /* CVMX_CAVIUM_OCTEON2 */
#ifdef __OCTEON__
- #define CVMX_SYNCIO asm volatile ("nop") /* Deprecated, will be removed in future release */
#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : :"memory")
- #define CVMX_SYNCIOALL asm volatile ("nop") /* Deprecated, will be removed in future release */
/* We actually use two syncw instructions in a row when we need a write
memory barrier. This is because the CN3XXX series of Octeons have
errata Core-401. This can cause a single syncw to not enforce
@@ -187,9 +184,7 @@ extern "C" {
#endif
#else /* !__OCTEON__ */
/* Not using a Cavium compiler, always use the slower sync so the assembler stays happy */
- #define CVMX_SYNCIO asm volatile ("nop") /* Deprecated, will be removed in future release */
#define CVMX_SYNCIOBDMA asm volatile ("sync" : : :"memory")
- #define CVMX_SYNCIOALL asm volatile ("nop") /* Deprecated, will be removed in future release */
#define CVMX_SYNCW asm volatile ("sync" : : :"memory")
#define CVMX_SYNCWS CVMX_SYNCW
#define CVMX_SYNCS CVMX_SYNC
diff --git a/cvmx-asx0-defs.h b/cvmx-asx0-defs.h
index 42115db5980b..f87c2fd4e3e3 100644
--- a/cvmx-asx0-defs.h
+++ b/cvmx-asx0-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_ASX0_TYPEDEFS_H__
-#define __CVMX_ASX0_TYPEDEFS_H__
+#ifndef __CVMX_ASX0_DEFS_H__
+#define __CVMX_ASX0_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
@@ -81,12 +81,10 @@ static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
* ASX_DBG_DATA_DRV
*
*/
-union cvmx_asx0_dbg_data_drv
-{
+union cvmx_asx0_dbg_data_drv {
uint64_t u64;
- struct cvmx_asx0_dbg_data_drv_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asx0_dbg_data_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t pctl : 5; /**< These bits control the driving strength of the dbg
interface. */
@@ -98,9 +96,8 @@ union cvmx_asx0_dbg_data_drv
uint64_t reserved_9_63 : 55;
#endif
} s;
- struct cvmx_asx0_dbg_data_drv_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asx0_dbg_data_drv_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t pctl : 4; /**< These bits control the driving strength of the dbg
interface. */
@@ -124,12 +121,10 @@ typedef union cvmx_asx0_dbg_data_drv cvmx_asx0_dbg_data_drv_t;
* ASX_DBG_DATA_ENABLE
*
*/
-union cvmx_asx0_dbg_data_enable
-{
+union cvmx_asx0_dbg_data_enable {
uint64_t u64;
- struct cvmx_asx0_dbg_data_enable_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asx0_dbg_data_enable_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t en : 1; /**< A 1->0 transistion, turns the dbg interface OFF. */
#else
diff --git a/cvmx-asxx-defs.h b/cvmx-asxx-defs.h
index 0791d1b1d4da..29c0de3960b1 100644
--- a/cvmx-asxx-defs.h
+++ b/cvmx-asxx-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,8 +49,8 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_ASXX_TYPEDEFS_H__
-#define __CVMX_ASXX_TYPEDEFS_H__
+#ifndef __CVMX_ASXX_DEFS_H__
+#define __CVMX_ASXX_DEFS_H__
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
@@ -395,12 +395,10 @@ static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
* ASX_GMII_RX_CLK_SET = GMII Clock delay setting
*
*/
-union cvmx_asxx_gmii_rx_clk_set
-{
+union cvmx_asxx_gmii_rx_clk_set {
uint64_t u64;
- struct cvmx_asxx_gmii_rx_clk_set_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_gmii_rx_clk_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the RXCLK (GMII receive clk)
delay line. The intrinsic delay can range from
@@ -422,12 +420,10 @@ typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
* ASX_GMII_RX_DAT_SET = GMII Clock delay setting
*
*/
-union cvmx_asxx_gmii_rx_dat_set
-{
+union cvmx_asxx_gmii_rx_dat_set {
uint64_t u64;
- struct cvmx_asxx_gmii_rx_dat_set_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_gmii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the RXD (GMII receive data)
delay lines. The intrinsic delay can range from
@@ -449,12 +445,10 @@ typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
* ASX_INT_EN = Interrupt Enable
*
*/
-union cvmx_asxx_int_en
-{
+union cvmx_asxx_int_en {
uint64_t u64;
- struct cvmx_asxx_int_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_int_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */
uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */
@@ -466,9 +460,8 @@ union cvmx_asxx_int_en
uint64_t reserved_12_63 : 52;
#endif
} s;
- struct cvmx_asxx_int_en_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_int_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63 : 53;
uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */
uint64_t reserved_7_7 : 1;
@@ -499,12 +492,10 @@ typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;
* ASX_INT_REG = Interrupt Register
*
*/
-union cvmx_asxx_int_reg
-{
+union cvmx_asxx_int_reg {
uint64_t u64;
- struct cvmx_asxx_int_reg_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_int_reg_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */
uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */
@@ -516,9 +507,8 @@ union cvmx_asxx_int_reg
uint64_t reserved_12_63 : 52;
#endif
} s;
- struct cvmx_asxx_int_reg_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_int_reg_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63 : 53;
uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */
uint64_t reserved_7_7 : 1;
@@ -549,12 +539,10 @@ typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;
* ASX_MII_RX_DAT_SET = GMII Clock delay setting
*
*/
-union cvmx_asxx_mii_rx_dat_set
-{
+union cvmx_asxx_mii_rx_dat_set {
uint64_t u64;
- struct cvmx_asxx_mii_rx_dat_set_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_mii_rx_dat_set_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the RXD (MII receive data)
delay lines. The intrinsic delay can range from
@@ -575,12 +563,10 @@ typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;
* ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
*
*/
-union cvmx_asxx_prt_loop
-{
+union cvmx_asxx_prt_loop {
uint64_t u64;
- struct cvmx_asxx_prt_loop_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_prt_loop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t ext_loop : 4; /**< External Loopback Enable
0 = No Loopback (TX FIFO is filled by RMGII)
@@ -602,9 +588,8 @@ union cvmx_asxx_prt_loop
uint64_t reserved_8_63 : 56;
#endif
} s;
- struct cvmx_asxx_prt_loop_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_prt_loop_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63 : 57;
uint64_t ext_loop : 3; /**< External Loopback Enable
0 = No Loopback (TX FIFO is filled by RMGII)
@@ -646,12 +631,10 @@ typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;
* ASX_RLD_BYPASS
*
*/
-union cvmx_asxx_rld_bypass
-{
+union cvmx_asxx_rld_bypass {
uint64_t u64;
- struct cvmx_asxx_rld_bypass_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_bypass_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t bypass : 1; /**< When set, the rld_dll setting is bypassed with
ASX_RLD_BYPASS_SETTING */
@@ -673,12 +656,10 @@ typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;
* ASX_RLD_BYPASS_SETTING
*
*/
-union cvmx_asxx_rld_bypass_setting
-{
+union cvmx_asxx_rld_bypass_setting {
uint64_t u64;
- struct cvmx_asxx_rld_bypass_setting_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_bypass_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< The rld_dll setting bypass value */
#else
@@ -699,12 +680,10 @@ typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;
* ASX_RLD_COMP
*
*/
-union cvmx_asxx_rld_comp
-{
+union cvmx_asxx_rld_comp {
uint64_t u64;
- struct cvmx_asxx_rld_comp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_comp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t pctl : 5; /**< PCTL Compensation Value
These bits reflect the computed compensation
@@ -717,9 +696,8 @@ union cvmx_asxx_rld_comp
uint64_t reserved_9_63 : 55;
#endif
} s;
- struct cvmx_asxx_rld_comp_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_comp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t pctl : 4; /**< These bits reflect the computed compensation
values from the built-in compensation circuit. */
@@ -743,12 +721,10 @@ typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;
* ASX_RLD_DATA_DRV
*
*/
-union cvmx_asxx_rld_data_drv
-{
+union cvmx_asxx_rld_data_drv {
uint64_t u64;
- struct cvmx_asxx_rld_data_drv_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_data_drv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t pctl : 4; /**< These bits specify a driving strength (positive
integer) for the RLD I/Os when the built-in
@@ -775,12 +751,10 @@ typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;
* ASX_RLD_FCRAM_MODE
*
*/
-union cvmx_asxx_rld_fcram_mode
-{
+union cvmx_asxx_rld_fcram_mode {
uint64_t u64;
- struct cvmx_asxx_rld_fcram_mode_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_fcram_mode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t mode : 1; /**< Memory Mode
- 0: RLDRAM
@@ -801,12 +775,10 @@ typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;
* ASX_RLD_NCTL_STRONG
*
*/
-union cvmx_asxx_rld_nctl_strong
-{
+union cvmx_asxx_rld_nctl_strong {
uint64_t u64;
- struct cvmx_asxx_rld_nctl_strong_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_nctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t nctl : 5; /**< Duke's drive control */
#else
@@ -827,12 +799,10 @@ typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;
* ASX_RLD_NCTL_WEAK
*
*/
-union cvmx_asxx_rld_nctl_weak
-{
+union cvmx_asxx_rld_nctl_weak {
uint64_t u64;
- struct cvmx_asxx_rld_nctl_weak_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_nctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t nctl : 5; /**< UNUSED (not needed for CN58XX) */
#else
@@ -853,12 +823,10 @@ typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;
* ASX_RLD_PCTL_STRONG
*
*/
-union cvmx_asxx_rld_pctl_strong
-{
+union cvmx_asxx_rld_pctl_strong {
uint64_t u64;
- struct cvmx_asxx_rld_pctl_strong_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_pctl_strong_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t pctl : 5; /**< Duke's drive control */
#else
@@ -879,12 +847,10 @@ typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;
* ASX_RLD_PCTL_WEAK
*
*/
-union cvmx_asxx_rld_pctl_weak
-{
+union cvmx_asxx_rld_pctl_weak {
uint64_t u64;
- struct cvmx_asxx_rld_pctl_weak_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_pctl_weak_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t pctl : 5; /**< UNUSED (not needed for CN58XX) */
#else
@@ -905,12 +871,10 @@ typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;
* ASX_RLD_SETTING
*
*/
-union cvmx_asxx_rld_setting
-{
+union cvmx_asxx_rld_setting {
uint64_t u64;
- struct cvmx_asxx_rld_setting_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_setting_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63 : 51;
uint64_t dfaset : 5; /**< RLD ClkGen DLL Setting(debug) */
uint64_t dfalag : 1; /**< RLD ClkGen DLL Lag Error(debug) */
@@ -926,9 +890,8 @@ union cvmx_asxx_rld_setting
uint64_t reserved_13_63 : 51;
#endif
} s;
- struct cvmx_asxx_rld_setting_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rld_setting_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< This is the read-only true rld dll_setting. */
#else
@@ -982,12 +945,10 @@ typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;
* 1.25 24
* 1.3 25
*/
-union cvmx_asxx_rx_clk_setx
-{
+union cvmx_asxx_rx_clk_setx {
uint64_t u64;
- struct cvmx_asxx_rx_clk_setx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the open-loop RXC delay line */
#else
@@ -1011,12 +972,10 @@ typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;
* ASX_RX_PRT_EN = RGMII Port Enable
*
*/
-union cvmx_asxx_rx_prt_en
-{
+union cvmx_asxx_rx_prt_en {
uint64_t u64;
- struct cvmx_asxx_rx_prt_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to receive
RMGII traffic. When this bit clear on a given
@@ -1027,9 +986,8 @@ union cvmx_asxx_rx_prt_en
uint64_t reserved_4_63 : 60;
#endif
} s;
- struct cvmx_asxx_rx_prt_en_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63 : 61;
uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to receive
RMGII traffic. When this bit clear on a given
@@ -1055,12 +1013,10 @@ typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;
* ASX_RX_WOL = RGMII RX Wake on LAN status register
*
*/
-union cvmx_asxx_rx_wol
-{
+union cvmx_asxx_rx_wol {
uint64_t u64;
- struct cvmx_asxx_rx_wol_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rx_wol_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t status : 1; /**< Copy of PMCSR[15] - PME_status */
uint64_t enable : 1; /**< Copy of PMCSR[8] - PME_enable */
@@ -1081,12 +1037,10 @@ typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;
* ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
*
*/
-union cvmx_asxx_rx_wol_msk
-{
+union cvmx_asxx_rx_wol_msk {
uint64_t u64;
- struct cvmx_asxx_rx_wol_msk_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rx_wol_msk_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t msk : 64; /**< Bytes to include in the CRC signature */
#else
uint64_t msk : 64;
@@ -1103,12 +1057,10 @@ typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;
* ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
*
*/
-union cvmx_asxx_rx_wol_powok
-{
+union cvmx_asxx_rx_wol_powok {
uint64_t u64;
- struct cvmx_asxx_rx_wol_powok_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rx_wol_powok_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t powerok : 1; /**< Power OK */
#else
@@ -1127,12 +1079,10 @@ typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;
* ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
*
*/
-union cvmx_asxx_rx_wol_sig
-{
+union cvmx_asxx_rx_wol_sig {
uint64_t u64;
- struct cvmx_asxx_rx_wol_sig_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_rx_wol_sig_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t sig : 32; /**< CRC signature */
#else
@@ -1185,12 +1135,10 @@ typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;
* 1.25 24
* 1.3 25
*/
-union cvmx_asxx_tx_clk_setx
-{
+union cvmx_asxx_tx_clk_setx {
uint64_t u64;
- struct cvmx_asxx_tx_clk_setx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_clk_setx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63 : 59;
uint64_t setting : 5; /**< Setting to place on the open-loop TXC delay line */
#else
@@ -1214,20 +1162,17 @@ typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;
* ASX_TX_COMP_BYP = RGMII Clock delay setting
*
*/
-union cvmx_asxx_tx_comp_byp
-{
+union cvmx_asxx_tx_comp_byp {
uint64_t u64;
- struct cvmx_asxx_tx_comp_byp_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_comp_byp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_0_63 : 64;
#else
uint64_t reserved_0_63 : 64;
#endif
} s;
- struct cvmx_asxx_tx_comp_byp_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_comp_byp_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63 : 55;
uint64_t bypass : 1; /**< Compensation bypass */
uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */
@@ -1240,9 +1185,8 @@ union cvmx_asxx_tx_comp_byp
#endif
} cn30xx;
struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
- struct cvmx_asxx_tx_comp_byp_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_comp_byp_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63 : 56;
uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */
uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */
@@ -1253,9 +1197,8 @@ union cvmx_asxx_tx_comp_byp
#endif
} cn38xx;
struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
- struct cvmx_asxx_tx_comp_byp_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_comp_byp_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63 : 47;
uint64_t bypass : 1; /**< Compensation bypass */
uint64_t reserved_13_15 : 3;
@@ -1271,9 +1214,8 @@ union cvmx_asxx_tx_comp_byp
uint64_t reserved_17_63 : 47;
#endif
} cn50xx;
- struct cvmx_asxx_tx_comp_byp_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_comp_byp_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63 : 51;
uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */
uint64_t reserved_5_7 : 3;
@@ -1295,12 +1237,10 @@ typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;
* ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
*
*/
-union cvmx_asxx_tx_hi_waterx
-{
+union cvmx_asxx_tx_hi_waterx {
uint64_t u64;
- struct cvmx_asxx_tx_hi_waterx_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_hi_waterx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t mark : 4; /**< TX FIFO HiWatermark to stall GMX
Value of 0 maps to 16
@@ -1315,9 +1255,8 @@ union cvmx_asxx_tx_hi_waterx
uint64_t reserved_4_63 : 60;
#endif
} s;
- struct cvmx_asxx_tx_hi_waterx_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_hi_waterx_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63 : 61;
uint64_t mark : 3; /**< TX FIFO HiWatermark to stall GMX
Value 0 maps to 8. */
@@ -1341,12 +1280,10 @@ typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;
* ASX_TX_PRT_EN = RGMII Port Enable
*
*/
-union cvmx_asxx_tx_prt_en
-{
+union cvmx_asxx_tx_prt_en {
uint64_t u64;
- struct cvmx_asxx_tx_prt_en_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_prt_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to send
RMGII traffic. When this bit clear on a given
@@ -1357,9 +1294,8 @@ union cvmx_asxx_tx_prt_en
uint64_t reserved_4_63 : 60;
#endif
} s;
- struct cvmx_asxx_tx_prt_en_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_asxx_tx_prt_en_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63 : 61;
uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to send
RMGII traffic. When this bit clear on a given
diff --git a/cvmx-atomic.h b/cvmx-atomic.h
index ba1fafaa985c..35ee331fed32 100644
--- a/cvmx-atomic.h
+++ b/cvmx-atomic.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -48,7 +48,7 @@
*
* This file provides atomic operations
*
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*
*
*/
@@ -355,7 +355,7 @@ static inline int64_t cvmx_atomic_fetch_and_add64_nosync(int64_t *ptr, int64_t i
{
uint64_t tmp, ret;
- if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
{
CVMX_PUSH_OCTEON2;
if (__builtin_constant_p(incr) && incr == 1)
@@ -436,7 +436,7 @@ static inline int32_t cvmx_atomic_fetch_and_add32_nosync(int32_t *ptr, int32_t i
{
uint32_t tmp, ret;
- if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
{
CVMX_PUSH_OCTEON2;
if (__builtin_constant_p(incr) && incr == 1)
@@ -648,7 +648,7 @@ static inline uint64_t cvmx_atomic_swap64_nosync(uint64_t *ptr, uint64_t new_val
{
uint64_t tmp, ret;
- if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
{
CVMX_PUSH_OCTEON2;
if (__builtin_constant_p(new_val) && new_val == 0)
@@ -706,7 +706,7 @@ static inline uint32_t cvmx_atomic_swap32_nosync(uint32_t *ptr, uint32_t new_val
{
uint32_t tmp, ret;
- if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
{
CVMX_PUSH_OCTEON2;
if (__builtin_constant_p(new_val) && new_val == 0)
@@ -747,22 +747,6 @@ static inline uint32_t cvmx_atomic_swap32_nosync(uint32_t *ptr, uint32_t new_val
return (ret);
}
-/**
- * This atomic operation is now named cvmx_atomic_compare_and_store32_nosync
- * and the (deprecated) macro is provided for backward compatibility.
- * @deprecated
- */
-#define cvmx_atomic_compare_and_store_nosync32 cvmx_atomic_compare_and_store32_nosync
-
-/**
- * This atomic operation is now named cvmx_atomic_compare_and_store64_nosync
- * and the (deprecated) macro is provided for backward compatibility.
- * @deprecated
- */
-#define cvmx_atomic_compare_and_store_nosync64 cvmx_atomic_compare_and_store64_nosync
-
-
-
#ifdef __cplusplus
}
#endif
diff --git a/cvmx-bootloader.h b/cvmx-bootloader.h
index caf460974db5..6529df1d0f97 100644
--- a/cvmx-bootloader.h
+++ b/cvmx-bootloader.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -50,7 +50,7 @@
*
* Bootloader definitions that are shared with other programs
*
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*/
@@ -127,9 +127,9 @@ typedef enum
BL_HEADER_IMAGE_PCIBOOT, /* Binary bootloader for PCI boot */
BL_HEADER_IMAGE_UBOOT_ENV, /* Environment for u-boot */
BL_HEADER_IMAGE_MAX,
- /* Range for customer private use. Will not be used by Cavium Networks */
+ /* Range for customer private use. Will not be used by Cavium Inc. */
BL_HEADER_IMAGE_CUST_RESERVED_MIN = 0x1000,
- BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff,
+ BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff
} bootloader_image_t;
#endif /* __ASSEMBLY__ */
@@ -139,7 +139,7 @@ typedef enum
#define MAX_NAND_SEARCH_ADDR 0x400000
/* Maximum address to look for start of normal bootloader */
-#define MAX_NOR_SEARCH_ADDR 0x100000
+#define MAX_NOR_SEARCH_ADDR 0x200000
/* Defines for RAM based environment set by the host or the previous bootloader
** in a chain boot configuration. */
@@ -147,5 +147,6 @@ typedef enum
#define U_BOOT_RAM_ENV_ADDR (0x1000)
#define U_BOOT_RAM_ENV_SIZE (0x1000)
#define U_BOOT_RAM_ENV_CRC_SIZE (0x4)
+#define U_BOOT_RAM_ENV_ADDR_2 (U_BOOT_RAM_ENV_ADDR + U_BOOT_RAM_ENV_SIZE)
#endif /* __CVMX_BOOTLOADER__ */
diff --git a/cvmx-bootmem.c b/cvmx-bootmem.c
index bb373fbaa0ea..a5f4e0c786ae 100644
--- a/cvmx-bootmem.c
+++ b/cvmx-bootmem.c
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
* Simple allocate only memory allocator. Used to allocate memory at application
* start time.
*
- * <hr>$Revision: 52119 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*
*/
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
@@ -300,7 +300,7 @@ static int __cvmx_bootmem_check_version(int exact_match)
int major_version;
#ifdef CVMX_BUILD_FOR_LINUX_HOST
if (!cvmx_bootmem_desc_addr)
- cvmx_bootmem_desc_addr = cvmx_read64_uint64(0x24100);
+ cvmx_bootmem_desc_addr = cvmx_read64_uint64(0x48100);
#endif
major_version = CVMX_BOOTMEM_DESC_GET_FIELD(major_version);
if ((major_version > 3) || (exact_match && major_version != exact_match))
@@ -457,27 +457,70 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
EXPORT_SYMBOL(cvmx_bootmem_alloc);
#endif
-void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name)
+void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, void (*init)(void*))
{
int64_t addr;
+ void *ptr;
+ uint64_t named_block_desc_addr;
+
+ __cvmx_bootmem_lock(0);
__cvmx_validate_mem_range(&min_addr, &max_addr);
- addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, 0);
- if (addr >= 0)
+ named_block_desc_addr = cvmx_bootmem_phy_named_block_find(name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+ if (named_block_desc_addr)
+ {
+ addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_desc_addr, base_addr);
+ __cvmx_bootmem_unlock(0);
return cvmx_phys_to_ptr(addr);
- else
+ }
+
+ addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+ if (addr < 0)
+ {
+ __cvmx_bootmem_unlock(0);
return NULL;
+ }
+ ptr = cvmx_phys_to_ptr(addr);
+ init(ptr);
+ __cvmx_bootmem_unlock(0);
+ return ptr;
+}
+
+void *cvmx_bootmem_alloc_named_range_flags(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, uint32_t flags)
+{
+ int64_t addr;
+
+ __cvmx_validate_mem_range(&min_addr, &max_addr);
+ addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, flags);
+ if (addr >= 0)
+ return cvmx_phys_to_ptr(addr);
+ else
+ return NULL;
+
+}
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name)
+{
+ return cvmx_bootmem_alloc_named_range_flags(size, min_addr, max_addr, align, name, 0);
}
+
void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, const char *name)
{
return(cvmx_bootmem_alloc_named_range(size, address, address + size, 0, name));
}
+
void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, const char *name)
{
return(cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name));
}
+void *cvmx_bootmem_alloc_named_flags(uint64_t size, uint64_t alignment, const char *name, uint32_t flags)
+{
+ return cvmx_bootmem_alloc_named_range_flags(size, 0, 0, alignment, name, flags);
+}
+
int cvmx_bootmem_free_named(const char *name)
{
return(cvmx_bootmem_phy_named_block_free(name, 0));
@@ -569,16 +612,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
/* Round req_size up to mult of minimum alignment bytes */
req_size = (req_size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) & ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
- /* Convert !0 address_min and 0 address_max to special case of range that specifies an exact
- ** memory block to allocate. Do this before other checks and adjustments so that this tranformation will be validated */
- if (address_min && !address_max)
- address_max = address_min + req_size;
- else if (!address_min && !address_max)
- address_max = ~0ull; /* If no limits given, use max limits */
-
-
-
-
+
/* Enforce minimum alignment (this also keeps the minimum free block
** req_size the same as the alignment req_size */
if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE)
@@ -592,6 +626,12 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t
if (alignment)
address_min = (address_min + (alignment - 1)) & ~(alignment - 1);
+ /* Convert !0 address_min and 0 address_max to special case of range that specifies an exact
+ ** memory block to allocate. Do this before other checks and adjustments so that this tranformation will be validated */
+ if (address_min && !address_max)
+ address_max = address_min + req_size;
+ else if (!address_min && !address_max)
+ address_max = ~0ull; /* If no limits given, use max limits */
/* Reject inconsistent args. We have adjusted these, so this may fail due to our internal changes
** even if this check would pass for the values the user supplied. */
@@ -825,7 +865,7 @@ void cvmx_bootmem_phy_list_print(void)
}
while (addr)
{
- cvmx_dprintf("Block address: 0x%08qx, size: 0x%08qx, next: 0x%08qx\n",
+ cvmx_dprintf("Block address: 0x%08llx, size: 0x%08llx, next: 0x%08llx\n",
(ULL)addr,
(ULL)cvmx_bootmem_phy_get_size(addr),
(ULL)cvmx_bootmem_phy_get_next(addr));
@@ -1014,7 +1054,7 @@ void cvmx_bootmem_phy_named_block_print(void)
uint64_t named_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_addr, base_addr);
CVMX_BOOTMEM_NAMED_GET_NAME(named_block_addr, name_tmp, name_length);
printed++;
- cvmx_dprintf("Name: %s, address: 0x%08qx, size: 0x%08qx, index: %d\n",
+ cvmx_dprintf("Name: %s, address: 0x%08llx, size: 0x%08llx, index: %d\n",
name_tmp, (ULL)named_addr, (ULL)named_size, i);
}
named_block_addr += sizeof(cvmx_bootmem_named_block_desc_t);
@@ -1027,14 +1067,6 @@ void cvmx_bootmem_phy_named_block_print(void)
}
-/* Real physical addresses of memory regions */
-#define OCTEON_DDR0_BASE (0x0ULL)
-#define OCTEON_DDR0_SIZE (0x010000000ULL)
-#define OCTEON_DDR1_BASE (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x20000000ULL : 0x410000000ULL)
-#define OCTEON_DDR1_SIZE (0x010000000ULL)
-#define OCTEON_DDR2_BASE (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x30000000ULL : 0x20000000ULL)
-#define OCTEON_DDR2_SIZE (OCTEON_IS_MODEL(OCTEON_CN6XXX) ? 0x7d0000000ULL : 0x3e0000000ULL)
-#define OCTEON_MAX_PHY_MEM_SIZE (OCTEON_IS_MODEL(OCTEON_CN63XX) ? 32*1024*1024*1024ULL : 16*1024*1024*1024ULL)
int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size, uint32_t low_reserved_bytes, cvmx_bootmem_desc_t *desc_buffer)
{
uint64_t cur_block_addr;
diff --git a/cvmx-bootmem.h b/cvmx-bootmem.h
index 2f07990e5c12..319b2c9a401f 100644
--- a/cvmx-bootmem.h
+++ b/cvmx-bootmem.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -47,7 +47,7 @@
* Simple allocate only memory allocator. Used to allocate memory at application
* start time.
*
- * <hr>$Revision: 49448 $<hr>
+ * <hr>$Revision: 70030 $<hr>
*
*/
@@ -66,6 +66,14 @@ extern "C" {
#define CVMX_BOOTMEM_FLAG_END_ALLOC (1 << 0) /* Allocate from end of block instead of beginning */
#define CVMX_BOOTMEM_FLAG_NO_LOCKING (1 << 1) /* Don't do any locking. */
+/* Real physical addresses of memory regions */
+#define OCTEON_DDR0_BASE (0x0ULL)
+#define OCTEON_DDR0_SIZE (0x010000000ULL)
+#define OCTEON_DDR1_BASE ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x20000000ULL : 0x410000000ULL)
+#define OCTEON_DDR1_SIZE (0x010000000ULL)
+#define OCTEON_DDR2_BASE ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x30000000ULL : 0x20000000ULL)
+#define OCTEON_DDR2_SIZE ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 0x7d0000000ULL : 0x3e0000000ULL)
+#define OCTEON_MAX_PHY_MEM_SIZE ((OCTEON_IS_MODEL(OCTEON_CN68XX)) ? 128*1024*1024*1024ULL : (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) ? 32*1024*1024*1024ull : 16*1024*1024*1024ULL)
/* First bytes of each free physical block of memory contain this structure,
* which is used to maintain the free memory list. Since the bootloader is
@@ -162,6 +170,21 @@ extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
*/
extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, uint64_t alignment);
+/**
+ * Allocate a block of memory from the free list that was
+ * passed to the application by the bootloader within a specified
+ * address range. This is an allocate-only algorithm, so
+ * freeing memory is not possible. Allocation will fail if
+ * memory cannot be allocated in the requested range.
+ *
+ * @param size Size in bytes of block to allocate
+ * @param min_addr defines the minimum address of the range
+ * @param max_addr defines the maximum address of the range
+ * @param alignment Alignment required - must be power of 2
+ * @param flags Flags to control options for the allocation.
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_range_flags(uint64_t size, uint64_t alignment, uint64_t min_addr, uint64_t max_addr, uint32_t flags);
/**
@@ -194,6 +217,21 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, uint64_
*/
extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, const char *name);
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @param size Size in bytes of block to allocate
+ * @param alignment Alignment required - must be power of 2
+ * @param name name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ * @param flags Flags to control options for the allocation.
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_flags(uint64_t size, uint64_t alignment, const char *name, uint32_t flags);
+
/**
@@ -231,6 +269,25 @@ extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, c
extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name);
/**
+ * Allocate if needed a block of memory from a specific range of the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ * If the requested name block is already allocated, return the pointer to block of memory.
+ * If request cannot be satisfied within the address range specified, NULL is returned
+ *
+ * @param size Size in bytes of block to allocate
+ * @param min_addr minimum address of range
+ * @param max_addr maximum address of range
+ * @param align Alignment of memory to be allocated. (must be a power of 2)
+ * @param name name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ * @param init Initialization function
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, const char *name, void (*init)(void*));
+
+/**
* Frees a previously allocated named bootmem block.
*
* @param name name of block to free
diff --git a/cvmx-ciu-defs.h b/cvmx-ciu-defs.h
index 05c03ff4eef2..2411d13dd3c8 100644
--- a/cvmx-ciu-defs.h
+++ b/cvmx-ciu-defs.h
@@ -1,5 +1,5 @@
/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
+ * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
* reserved.
*
*
@@ -15,7 +15,7 @@
* disclaimer in the documentation and/or other materials provided
* with the distribution.
- * * Neither the name of Cavium Networks nor the names of
+ * * Neither the name of Cavium Inc. nor the names of
* its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
@@ -26,7 +26,7 @@
* countries.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
+ * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
@@ -49,15 +49,15 @@
* <hr>$Revision$<hr>
*
*/
-#ifndef __CVMX_CIU_TYPEDEFS_H__
-#define __CVMX_CIU_TYPEDEFS_H__
+#ifndef __CVMX_CIU_DEFS_H__
+#define __CVMX_CIU_DEFS_H__
#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_CIU_BLOCK_INT CVMX_CIU_BLOCK_INT_FUNC()
static inline uint64_t CVMX_CIU_BLOCK_INT_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_BLOCK_INT not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00010700000007C0ull);
}
@@ -65,13 +65,169 @@ static inline uint64_t CVMX_CIU_BLOCK_INT_FUNC(void)
#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
#endif
#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_IOX_INT(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_CIU_EN2_IOX_INT(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_IOX_INT_W1C(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_CIU_EN2_IOX_INT_W1C(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_IOX_INT_W1S(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_CIU_EN2_IOX_INT_W1S(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP2(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP2(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP2_W1C(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP2_W1C(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP2_W1S(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP2_W1S(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP3(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP3(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP3_W1C(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP3_W1C(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP3_W1S(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP3_W1S(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP4(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP4(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP4_W1C(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP4_W1C(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_EN2_PPX_IP4_W1S(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_EN2_PPX_IP4_W1S(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8)
+#endif
#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_CIU_INT33_SUM0 CVMX_CIU_INT33_SUM0_FUNC()
static inline uint64_t CVMX_CIU_INT33_SUM0_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_INT33_SUM0 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001070000000110ull);
}
@@ -89,7 +245,10 @@ static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16;
}
@@ -103,7 +262,10 @@ static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16;
}
@@ -117,7 +279,10 @@ static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16;
}
@@ -135,7 +300,10 @@ static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16;
}
@@ -149,7 +317,10 @@ static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16;
}
@@ -163,7 +334,10 @@ static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33))))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16;
}
@@ -178,7 +352,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16;
}
@@ -192,7 +369,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16;
}
@@ -206,7 +386,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16;
}
@@ -221,7 +404,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16;
}
@@ -235,7 +421,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16;
}
@@ -249,7 +438,10 @@ static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16;
}
@@ -267,7 +459,10 @@ static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || (offset == 32)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || (offset == 32))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || (offset == 32))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || (offset == 32))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || (offset == 32)))))
cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8;
}
@@ -282,7 +477,10 @@ static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset);
return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8;
}
@@ -293,77 +491,173 @@ static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
#define CVMX_CIU_INT_DBG_SEL CVMX_CIU_INT_DBG_SEL_FUNC()
static inline uint64_t CVMX_CIU_INT_DBG_SEL_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_INT_DBG_SEL not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x00010700000007D0ull);
}
#else
#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
#endif
-#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
+#define CVMX_CIU_INT_SUM1 CVMX_CIU_INT_SUM1_FUNC()
+static inline uint64_t CVMX_CIU_INT_SUM1_FUNC(void)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
- cvmx_warn("CVMX_CIU_MBOX_CLRX(%lu) is invalid on this chip\n", offset);
- return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+ if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+ cvmx_warn("CVMX_CIU_INT_SUM1 not supported on this chip\n");
+ return CVMX_ADD_IO_SEG(0x0001070000000108ull);
}
#else
-#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
#endif
-#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ if ((offset == 0))
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 0) * 8;
+ break;
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 3))
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 3) * 8;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 1))
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 1) * 8;
+ break;
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 15))
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 11))
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 9))
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 5))
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 7) * 8;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 31))
+ return CVMX_ADD_IO_SEG(0x0001070100100600ull) + ((offset) & 31) * 8;
+ break;
+ }
+ cvmx_warn("CVMX_CIU_MBOX_CLRX (offset = %lu) not supported on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 3) * 8;
+}
static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
- cvmx_warn("CVMX_CIU_MBOX_SETX(%lu) is invalid on this chip\n", offset);
- return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ if ((offset == 0))
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 0) * 8;
+ break;
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 3))
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 3) * 8;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 1))
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 1) * 8;
+ break;
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 15))
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 11))
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 9))
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 5))
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 7) * 8;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 31))
+ return CVMX_ADD_IO_SEG(0x0001070100100400ull) + ((offset) & 31) * 8;
+ break;
+ }
+ cvmx_warn("CVMX_CIU_MBOX_SETX (offset = %lu) not supported on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 3) * 8;
}
-#else
-#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
-#endif
#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
-#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
+#define CVMX_CIU_PP_BIST_STAT CVMX_CIU_PP_BIST_STAT_FUNC()
+static inline uint64_t CVMX_CIU_PP_BIST_STAT_FUNC(void)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
- cvmx_warn("CVMX_CIU_PP_POKEX(%lu) is invalid on this chip\n", offset);
- return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+ if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+ cvmx_warn("CVMX_CIU_PP_BIST_STAT not supported on this chip\n");
+ return CVMX_ADD_IO_SEG(0x00010700000007E0ull);
}
#else
-#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
#endif
+#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
+static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ if ((offset == 0))
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 0) * 8;
+ break;
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 3))
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 3) * 8;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 1))
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 1) * 8;
+ break;
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 15))
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 11))
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 9))
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 5))
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 7) * 8;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 31))
+ return CVMX_ADD_IO_SEG(0x0001070100100200ull) + ((offset) & 31) * 8;
+ break;
+ }
+ cvmx_warn("CVMX_CIU_PP_POKEX (offset = %lu) not supported on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 3) * 8;
+}
#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_CIU_QLM0 CVMX_CIU_QLM0_FUNC()
static inline uint64_t CVMX_CIU_QLM0_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_QLM0 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001070000000780ull);
}
@@ -374,7 +668,7 @@ static inline uint64_t CVMX_CIU_QLM0_FUNC(void)
#define CVMX_CIU_QLM1 CVMX_CIU_QLM1_FUNC()
static inline uint64_t CVMX_CIU_QLM1_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_QLM1 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001070000000788ull);
}
@@ -385,7 +679,7 @@ static inline uint64_t CVMX_CIU_QLM1_FUNC(void)
#define CVMX_CIU_QLM2 CVMX_CIU_QLM2_FUNC()
static inline uint64_t CVMX_CIU_QLM2_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_QLM2 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001070000000790ull);
}
@@ -393,6 +687,28 @@ static inline uint64_t CVMX_CIU_QLM2_FUNC(void)
#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM3 CVMX_CIU_QLM3_FUNC()
+static inline uint64_t CVMX_CIU_QLM3_FUNC(void)
+{
+ if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+ cvmx_warn("CVMX_CIU_QLM3 not supported on this chip\n");
+ return CVMX_ADD_IO_SEG(0x0001070000000798ull);
+}
+#else
+#define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_QLM4 CVMX_CIU_QLM4_FUNC()
+static inline uint64_t CVMX_CIU_QLM4_FUNC(void)
+{
+ if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
+ cvmx_warn("CVMX_CIU_QLM4 not supported on this chip\n");
+ return CVMX_ADD_IO_SEG(0x00010700000007A0ull);
+}
+#else
+#define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC()
static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
{
@@ -407,7 +723,7 @@ static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
#define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC()
static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001070000000768ull);
}
@@ -418,7 +734,7 @@ static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
#define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC()
static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001070000000770ull);
}
@@ -431,15 +747,141 @@ static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC()
static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void)
{
- if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)))
+ if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n");
return CVMX_ADD_IO_SEG(0x0001070000000758ull);
}
#else
#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_SOFT_PRST2 CVMX_CIU_SOFT_PRST2_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST2_FUNC(void)
+{
+ if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
+ cvmx_warn("CVMX_CIU_SOFT_PRST2 not supported on this chip\n");
+ return CVMX_ADD_IO_SEG(0x00010700000007D8ull);
+}
+#else
+#define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull))
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_CIU_SOFT_PRST3 CVMX_CIU_SOFT_PRST3_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST3_FUNC(void)
+{
+ if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
+ cvmx_warn("CVMX_CIU_SOFT_PRST3 not supported on this chip\n");
+ return CVMX_ADD_IO_SEG(0x00010700000007E0ull);
+}
+#else
+#define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
+#endif
#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM1_IOX_INT(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_CIU_SUM1_IOX_INT(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM1_PPX_IP2(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_SUM1_PPX_IP2(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM1_PPX_IP3(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_SUM1_PPX_IP3(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM1_PPX_IP4(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_SUM1_PPX_IP4(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM2_IOX_INT(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
+ cvmx_warn("CVMX_CIU_SUM2_IOX_INT(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8;
+}
+#else
+#define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM2_PPX_IP2(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_SUM2_PPX_IP2(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM2_PPX_IP3(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_SUM2_PPX_IP3(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+static inline uint64_t CVMX_CIU_SUM2_PPX_IP4(unsigned long offset)
+{
+ if (!(
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
+ cvmx_warn("CVMX_CIU_SUM2_PPX_IP4(%lu) is invalid on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8;
+}
+#else
+#define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8)
+#endif
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
{
if (!(
@@ -450,53 +892,90 @@ static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3)))))
+ (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
+ (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
+ (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 9)))))
cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset);
- return CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8;
+ return CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8;
}
#else
-#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8)
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
-static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
+#define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_TIM_MULTI_CAST_FUNC()
+static inline uint64_t CVMX_CIU_TIM_MULTI_CAST_FUNC(void)
{
- if (!(
- (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
- (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
- (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
- (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
- (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
- (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5)))))
- cvmx_warn("CVMX_CIU_WDOGX(%lu) is invalid on this chip\n", offset);
- return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+ if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
+ cvmx_warn("CVMX_CIU_TIM_MULTI_CAST not supported on this chip\n");
+ return CVMX_ADD_IO_SEG(0x000107000000C200ull);
}
#else
-#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull))
#endif
+static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
+{
+ switch(cvmx_get_octeon_family()) {
+ case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
+ if ((offset == 0))
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 0) * 8;
+ break;
+ case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 3))
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 3) * 8;
+ break;
+ case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 1))
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 1) * 8;
+ break;
+ case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 15))
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 11))
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 9))
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
+ break;
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 5))
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 7) * 8;
+ break;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ if ((offset <= 31))
+ return CVMX_ADD_IO_SEG(0x0001070100100000ull) + ((offset) & 31) * 8;
+ break;
+ }
+ cvmx_warn("CVMX_CIU_WDOGX (offset = %lu) not supported on this chip\n", offset);
+ return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 3) * 8;
+}
/**
* cvmx_ciu_bist
*/
-union cvmx_ciu_bist
-{
+union cvmx_ciu_bist {
uint64_t u64;
- struct cvmx_ciu_bist_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_5_63 : 59;
- uint64_t bist : 5; /**< BIST Results.
+ struct cvmx_ciu_bist_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_7_63 : 57;
+ uint64_t bist : 7; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
BIST. */
#else
- uint64_t bist : 5;
- uint64_t reserved_5_63 : 59;
+ uint64_t bist : 7;
+ uint64_t reserved_7_63 : 57;
#endif
} s;
- struct cvmx_ciu_bist_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_bist_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t bist : 4; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -509,9 +988,8 @@ union cvmx_ciu_bist
struct cvmx_ciu_bist_cn30xx cn31xx;
struct cvmx_ciu_bist_cn30xx cn38xx;
struct cvmx_ciu_bist_cn30xx cn38xxp2;
- struct cvmx_ciu_bist_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_bist_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t bist : 2; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -521,9 +999,8 @@ union cvmx_ciu_bist
uint64_t reserved_2_63 : 62;
#endif
} cn50xx;
- struct cvmx_ciu_bist_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_bist_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63 : 61;
uint64_t bist : 3; /**< BIST Results.
HW sets a bit in BIST for for memory that fails
@@ -538,8 +1015,33 @@ union cvmx_ciu_bist
struct cvmx_ciu_bist_cn30xx cn56xxp1;
struct cvmx_ciu_bist_cn30xx cn58xx;
struct cvmx_ciu_bist_cn30xx cn58xxp1;
- struct cvmx_ciu_bist_s cn63xx;
- struct cvmx_ciu_bist_s cn63xxp1;
+ struct cvmx_ciu_bist_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_6_63 : 58;
+ uint64_t bist : 6; /**< BIST Results.
+ HW sets a bit in BIST for for memory that fails
+ BIST. */
+#else
+ uint64_t bist : 6;
+ uint64_t reserved_6_63 : 58;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_bist_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_5_63 : 59;
+ uint64_t bist : 5; /**< BIST Results.
+ HW sets a bit in BIST for for memory that fails
+ BIST. */
+#else
+ uint64_t bist : 5;
+ uint64_t reserved_5_63 : 59;
+#endif
+ } cn63xx;
+ struct cvmx_ciu_bist_cn63xx cn63xxp1;
+ struct cvmx_ciu_bist_cn61xx cn66xx;
+ struct cvmx_ciu_bist_s cn68xx;
+ struct cvmx_ciu_bist_s cn68xxp1;
+ struct cvmx_ciu_bist_cn61xx cnf71xx;
};
typedef union cvmx_ciu_bist cvmx_ciu_bist_t;
@@ -550,13 +1052,16 @@ typedef union cvmx_ciu_bist cvmx_ciu_bist_t;
*
* The interrupt lines from the various chip blocks.
*/
-union cvmx_ciu_block_int
-{
+union cvmx_ciu_block_int {
uint64_t u64;
- struct cvmx_ciu_block_int_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_43_63 : 21;
+ struct cvmx_ciu_block_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_62_63 : 2;
+ uint64_t srio3 : 1; /**< SRIO3 interrupt
+ See SRIO3_INT_REG, SRIO3_INT2_REG */
+ uint64_t srio2 : 1; /**< SRIO2 interrupt
+ See SRIO2_INT_REG, SRIO2_INT2_REG */
+ uint64_t reserved_43_59 : 17;
uint64_t ptp : 1; /**< PTP interrupt
See CIU_INT_SUM1[PTP] */
uint64_t dpi : 1; /**< DPI interrupt
@@ -567,7 +1072,213 @@ union cvmx_ciu_block_int
uint64_t srio1 : 1; /**< SRIO1 interrupt
See SRIO1_INT_REG */
uint64_t srio0 : 1; /**< SRIO0 interrupt
- See SRIO0_INT_REG */
+ See SRIO0_INT_REG, SRIO0_INT2_REG */
+ uint64_t reserved_31_31 : 1;
+ uint64_t iob : 1; /**< IOB interrupt
+ See IOB_INT_SUM */
+ uint64_t reserved_29_29 : 1;
+ uint64_t agl : 1; /**< AGL interrupt
+ See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+ uint64_t reserved_27_27 : 1;
+ uint64_t pem1 : 1; /**< PEM1 interrupt
+ See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+ uint64_t pem0 : 1; /**< PEM0 interrupt
+ See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+ uint64_t reserved_24_24 : 1;
+ uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */
+ uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+ uint64_t reserved_21_21 : 1;
+ uint64_t pip : 1; /**< PIP interrupt
+ See PIP_INT_REG */
+ uint64_t reserved_18_19 : 2;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt
+ See LMC0_INT */
+ uint64_t l2c : 1; /**< L2C interrupt
+ See L2C_INT_REG */
+ uint64_t reserved_15_15 : 1;
+ uint64_t rad : 1; /**< RAD interrupt
+ See RAD_REG_ERROR */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt
+ See UCTL0_INT_REG */
+ uint64_t pow : 1; /**< POW err interrupt
+ See POW_ECC_ERR */
+ uint64_t tim : 1; /**< TIM interrupt
+ See TIM_REG_ERROR */
+ uint64_t pko : 1; /**< PKO interrupt
+ See PKO_REG_ERROR */
+ uint64_t ipd : 1; /**< IPD interrupt
+ See IPD_INT_SUM */
+ uint64_t reserved_8_8 : 1;
+ uint64_t zip : 1; /**< ZIP interrupt
+ See ZIP_ERROR */
+ uint64_t dfa : 1; /**< DFA interrupt
+ See DFA_ERROR */
+ uint64_t fpa : 1; /**< FPA interrupt
+ See FPA_INT_SUM */
+ uint64_t key : 1; /**< KEY interrupt
+ See KEY_INT_SUM */
+ uint64_t sli : 1; /**< SLI interrupt
+ See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+ uint64_t gmx1 : 1; /**< GMX1 interrupt
+ See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
+ uint64_t gmx0 : 1; /**< GMX0 interrupt
+ See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+ uint64_t mio : 1; /**< MIO boot interrupt
+ See MIO_BOOT_ERR */
+#else
+ uint64_t mio : 1;
+ uint64_t gmx0 : 1;
+ uint64_t gmx1 : 1;
+ uint64_t sli : 1;
+ uint64_t key : 1;
+ uint64_t fpa : 1;
+ uint64_t dfa : 1;
+ uint64_t zip : 1;
+ uint64_t reserved_8_8 : 1;
+ uint64_t ipd : 1;
+ uint64_t pko : 1;
+ uint64_t tim : 1;
+ uint64_t pow : 1;
+ uint64_t usb : 1;
+ uint64_t rad : 1;
+ uint64_t reserved_15_15 : 1;
+ uint64_t l2c : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_18_19 : 2;
+ uint64_t pip : 1;
+ uint64_t reserved_21_21 : 1;
+ uint64_t asxpcs0 : 1;
+ uint64_t asxpcs1 : 1;
+ uint64_t reserved_24_24 : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_27_27 : 1;
+ uint64_t agl : 1;
+ uint64_t reserved_29_29 : 1;
+ uint64_t iob : 1;
+ uint64_t reserved_31_31 : 1;
+ uint64_t srio0 : 1;
+ uint64_t srio1 : 1;
+ uint64_t reserved_34_39 : 6;
+ uint64_t dfm : 1;
+ uint64_t dpi : 1;
+ uint64_t ptp : 1;
+ uint64_t reserved_43_59 : 17;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_63 : 2;
+#endif
+ } s;
+ struct cvmx_ciu_block_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_43_63 : 21;
+ uint64_t ptp : 1; /**< PTP interrupt
+ See CIU_INT_SUM1[PTP] */
+ uint64_t dpi : 1; /**< DPI interrupt
+ See DPI_INT_REG */
+ uint64_t reserved_31_40 : 10;
+ uint64_t iob : 1; /**< IOB interrupt
+ See IOB_INT_SUM */
+ uint64_t reserved_29_29 : 1;
+ uint64_t agl : 1; /**< AGL interrupt
+ See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+ uint64_t reserved_27_27 : 1;
+ uint64_t pem1 : 1; /**< PEM1 interrupt
+ See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+ uint64_t pem0 : 1; /**< PEM0 interrupt
+ See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+ uint64_t reserved_24_24 : 1;
+ uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */
+ uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+ uint64_t reserved_21_21 : 1;
+ uint64_t pip : 1; /**< PIP interrupt
+ See PIP_INT_REG */
+ uint64_t reserved_18_19 : 2;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt
+ See LMC0_INT */
+ uint64_t l2c : 1; /**< L2C interrupt
+ See L2C_INT_REG */
+ uint64_t reserved_15_15 : 1;
+ uint64_t rad : 1; /**< RAD interrupt
+ See RAD_REG_ERROR */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt
+ See UCTL0_INT_REG */
+ uint64_t pow : 1; /**< POW err interrupt
+ See POW_ECC_ERR */
+ uint64_t tim : 1; /**< TIM interrupt
+ See TIM_REG_ERROR */
+ uint64_t pko : 1; /**< PKO interrupt
+ See PKO_REG_ERROR */
+ uint64_t ipd : 1; /**< IPD interrupt
+ See IPD_INT_SUM */
+ uint64_t reserved_8_8 : 1;
+ uint64_t zip : 1; /**< ZIP interrupt
+ See ZIP_ERROR */
+ uint64_t dfa : 1; /**< DFA interrupt
+ See DFA_ERROR */
+ uint64_t fpa : 1; /**< FPA interrupt
+ See FPA_INT_SUM */
+ uint64_t key : 1; /**< KEY interrupt
+ See KEY_INT_SUM */
+ uint64_t sli : 1; /**< SLI interrupt
+ See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+ uint64_t gmx1 : 1; /**< GMX1 interrupt
+ See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
+ uint64_t gmx0 : 1; /**< GMX0 interrupt
+ See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+ uint64_t mio : 1; /**< MIO boot interrupt
+ See MIO_BOOT_ERR */
+#else
+ uint64_t mio : 1;
+ uint64_t gmx0 : 1;
+ uint64_t gmx1 : 1;
+ uint64_t sli : 1;
+ uint64_t key : 1;
+ uint64_t fpa : 1;
+ uint64_t dfa : 1;
+ uint64_t zip : 1;
+ uint64_t reserved_8_8 : 1;
+ uint64_t ipd : 1;
+ uint64_t pko : 1;
+ uint64_t tim : 1;
+ uint64_t pow : 1;
+ uint64_t usb : 1;
+ uint64_t rad : 1;
+ uint64_t reserved_15_15 : 1;
+ uint64_t l2c : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_18_19 : 2;
+ uint64_t pip : 1;
+ uint64_t reserved_21_21 : 1;
+ uint64_t asxpcs0 : 1;
+ uint64_t asxpcs1 : 1;
+ uint64_t reserved_24_24 : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_27_27 : 1;
+ uint64_t agl : 1;
+ uint64_t reserved_29_29 : 1;
+ uint64_t iob : 1;
+ uint64_t reserved_31_40 : 10;
+ uint64_t dpi : 1;
+ uint64_t ptp : 1;
+ uint64_t reserved_43_63 : 21;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_block_int_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_43_63 : 21;
+ uint64_t ptp : 1; /**< PTP interrupt
+ See CIU_INT_SUM1[PTP] */
+ uint64_t dpi : 1; /**< DPI interrupt
+ See DPI_INT_REG */
+ uint64_t dfm : 1; /**< DFM interrupt
+ See DFM_FNT_STAT */
+ uint64_t reserved_34_39 : 6;
+ uint64_t srio1 : 1; /**< SRIO1 interrupt
+ See SRIO1_INT_REG, SRIO1_INT2_REG */
+ uint64_t srio0 : 1; /**< SRIO0 interrupt
+ See SRIO0_INT_REG, SRIO0_INT2_REG */
uint64_t reserved_31_31 : 1;
uint64_t iob : 1; /**< IOB interrupt
See IOB_INT_SUM */
@@ -657,31 +1368,221 @@ union cvmx_ciu_block_int
uint64_t ptp : 1;
uint64_t reserved_43_63 : 21;
#endif
- } s;
- struct cvmx_ciu_block_int_s cn63xx;
- struct cvmx_ciu_block_int_s cn63xxp1;
+ } cn63xx;
+ struct cvmx_ciu_block_int_cn63xx cn63xxp1;
+ struct cvmx_ciu_block_int_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_62_63 : 2;
+ uint64_t srio3 : 1; /**< SRIO3 interrupt
+ See SRIO3_INT_REG, SRIO3_INT2_REG */
+ uint64_t srio2 : 1; /**< SRIO2 interrupt
+ See SRIO2_INT_REG, SRIO2_INT2_REG */
+ uint64_t reserved_43_59 : 17;
+ uint64_t ptp : 1; /**< PTP interrupt
+ See CIU_INT_SUM1[PTP] */
+ uint64_t dpi : 1; /**< DPI interrupt
+ See DPI_INT_REG */
+ uint64_t dfm : 1; /**< DFM interrupt
+ See DFM_FNT_STAT */
+ uint64_t reserved_33_39 : 7;
+ uint64_t srio0 : 1; /**< SRIO0 interrupt
+ See SRIO0_INT_REG, SRIO0_INT2_REG */
+ uint64_t reserved_31_31 : 1;
+ uint64_t iob : 1; /**< IOB interrupt
+ See IOB_INT_SUM */
+ uint64_t reserved_29_29 : 1;
+ uint64_t agl : 1; /**< AGL interrupt
+ See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
+ uint64_t reserved_27_27 : 1;
+ uint64_t pem1 : 1; /**< PEM1 interrupt
+ See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+ uint64_t pem0 : 1; /**< PEM0 interrupt
+ See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+ uint64_t reserved_24_24 : 1;
+ uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */
+ uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+ uint64_t reserved_21_21 : 1;
+ uint64_t pip : 1; /**< PIP interrupt
+ See PIP_INT_REG */
+ uint64_t reserved_18_19 : 2;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt
+ See LMC0_INT */
+ uint64_t l2c : 1; /**< L2C interrupt
+ See L2C_INT_REG */
+ uint64_t reserved_15_15 : 1;
+ uint64_t rad : 1; /**< RAD interrupt
+ See RAD_REG_ERROR */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt
+ See UCTL0_INT_REG */
+ uint64_t pow : 1; /**< POW err interrupt
+ See POW_ECC_ERR */
+ uint64_t tim : 1; /**< TIM interrupt
+ See TIM_REG_ERROR */
+ uint64_t pko : 1; /**< PKO interrupt
+ See PKO_REG_ERROR */
+ uint64_t ipd : 1; /**< IPD interrupt
+ See IPD_INT_SUM */
+ uint64_t reserved_8_8 : 1;
+ uint64_t zip : 1; /**< ZIP interrupt
+ See ZIP_ERROR */
+ uint64_t dfa : 1; /**< DFA interrupt
+ See DFA_ERROR */
+ uint64_t fpa : 1; /**< FPA interrupt
+ See FPA_INT_SUM */
+ uint64_t key : 1; /**< KEY interrupt
+ See KEY_INT_SUM */
+ uint64_t sli : 1; /**< SLI interrupt
+ See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+ uint64_t gmx1 : 1; /**< GMX1 interrupt
+ See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
+ uint64_t gmx0 : 1; /**< GMX0 interrupt
+ See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+ uint64_t mio : 1; /**< MIO boot interrupt
+ See MIO_BOOT_ERR */
+#else
+ uint64_t mio : 1;
+ uint64_t gmx0 : 1;
+ uint64_t gmx1 : 1;
+ uint64_t sli : 1;
+ uint64_t key : 1;
+ uint64_t fpa : 1;
+ uint64_t dfa : 1;
+ uint64_t zip : 1;
+ uint64_t reserved_8_8 : 1;
+ uint64_t ipd : 1;
+ uint64_t pko : 1;
+ uint64_t tim : 1;
+ uint64_t pow : 1;
+ uint64_t usb : 1;
+ uint64_t rad : 1;
+ uint64_t reserved_15_15 : 1;
+ uint64_t l2c : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_18_19 : 2;
+ uint64_t pip : 1;
+ uint64_t reserved_21_21 : 1;
+ uint64_t asxpcs0 : 1;
+ uint64_t asxpcs1 : 1;
+ uint64_t reserved_24_24 : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_27_27 : 1;
+ uint64_t agl : 1;
+ uint64_t reserved_29_29 : 1;
+ uint64_t iob : 1;
+ uint64_t reserved_31_31 : 1;
+ uint64_t srio0 : 1;
+ uint64_t reserved_33_39 : 7;
+ uint64_t dfm : 1;
+ uint64_t dpi : 1;
+ uint64_t ptp : 1;
+ uint64_t reserved_43_59 : 17;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_63 : 2;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_block_int_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_43_63 : 21;
+ uint64_t ptp : 1; /**< PTP interrupt
+ See CIU_INT_SUM1[PTP] */
+ uint64_t dpi : 1; /**< DPI interrupt
+ See DPI_INT_REG */
+ uint64_t reserved_31_40 : 10;
+ uint64_t iob : 1; /**< IOB interrupt
+ See IOB_INT_SUM */
+ uint64_t reserved_27_29 : 3;
+ uint64_t pem1 : 1; /**< PEM1 interrupt
+ See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
+ uint64_t pem0 : 1; /**< PEM0 interrupt
+ See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
+ uint64_t reserved_23_24 : 2;
+ uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
+ uint64_t reserved_21_21 : 1;
+ uint64_t pip : 1; /**< PIP interrupt
+ See PIP_INT_REG */
+ uint64_t reserved_18_19 : 2;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt
+ See LMC0_INT */
+ uint64_t l2c : 1; /**< L2C interrupt
+ See L2C_INT_REG */
+ uint64_t reserved_15_15 : 1;
+ uint64_t rad : 1; /**< RAD interrupt
+ See RAD_REG_ERROR */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt
+ See UCTL0_INT_REG */
+ uint64_t pow : 1; /**< POW err interrupt
+ See POW_ECC_ERR */
+ uint64_t tim : 1; /**< TIM interrupt
+ See TIM_REG_ERROR */
+ uint64_t pko : 1; /**< PKO interrupt
+ See PKO_REG_ERROR */
+ uint64_t ipd : 1; /**< IPD interrupt
+ See IPD_INT_SUM */
+ uint64_t reserved_6_8 : 3;
+ uint64_t fpa : 1; /**< FPA interrupt
+ See FPA_INT_SUM */
+ uint64_t key : 1; /**< KEY interrupt
+ See KEY_INT_SUM */
+ uint64_t sli : 1; /**< SLI interrupt
+ See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
+ uint64_t reserved_2_2 : 1;
+ uint64_t gmx0 : 1; /**< GMX0 interrupt
+ See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
+ uint64_t mio : 1; /**< MIO boot interrupt
+ See MIO_BOOT_ERR */
+#else
+ uint64_t mio : 1;
+ uint64_t gmx0 : 1;
+ uint64_t reserved_2_2 : 1;
+ uint64_t sli : 1;
+ uint64_t key : 1;
+ uint64_t fpa : 1;
+ uint64_t reserved_6_8 : 3;
+ uint64_t ipd : 1;
+ uint64_t pko : 1;
+ uint64_t tim : 1;
+ uint64_t pow : 1;
+ uint64_t usb : 1;
+ uint64_t rad : 1;
+ uint64_t reserved_15_15 : 1;
+ uint64_t l2c : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_18_19 : 2;
+ uint64_t pip : 1;
+ uint64_t reserved_21_21 : 1;
+ uint64_t asxpcs0 : 1;
+ uint64_t reserved_23_24 : 2;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_27_29 : 3;
+ uint64_t iob : 1;
+ uint64_t reserved_31_40 : 10;
+ uint64_t dpi : 1;
+ uint64_t ptp : 1;
+ uint64_t reserved_43_63 : 21;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_block_int cvmx_ciu_block_int_t;
/**
* cvmx_ciu_dint
*/
-union cvmx_ciu_dint
-{
+union cvmx_ciu_dint {
uint64_t u64;
- struct cvmx_ciu_dint_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_16_63 : 48;
- uint64_t dint : 16; /**< Send DINT pulse to PP vector */
+ struct cvmx_ciu_dint_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_32_63 : 32;
+ uint64_t dint : 32; /**< Send DINT pulse to PP vector */
#else
- uint64_t dint : 16;
- uint64_t reserved_16_63 : 48;
+ uint64_t dint : 32;
+ uint64_t reserved_32_63 : 32;
#endif
} s;
- struct cvmx_ciu_dint_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_dint_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t dint : 1; /**< Send DINT pulse to PP vector */
#else
@@ -689,9 +1590,8 @@ union cvmx_ciu_dint
uint64_t reserved_1_63 : 63;
#endif
} cn30xx;
- struct cvmx_ciu_dint_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_dint_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t dint : 2; /**< Send DINT pulse to PP vector */
#else
@@ -699,12 +1599,19 @@ union cvmx_ciu_dint
uint64_t reserved_2_63 : 62;
#endif
} cn31xx;
- struct cvmx_ciu_dint_s cn38xx;
- struct cvmx_ciu_dint_s cn38xxp2;
+ struct cvmx_ciu_dint_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_16_63 : 48;
+ uint64_t dint : 16; /**< Send DINT pulse to PP vector */
+#else
+ uint64_t dint : 16;
+ uint64_t reserved_16_63 : 48;
+#endif
+ } cn38xx;
+ struct cvmx_ciu_dint_cn38xx cn38xxp2;
struct cvmx_ciu_dint_cn31xx cn50xx;
- struct cvmx_ciu_dint_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_dint_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t dint : 4; /**< Send DINT pulse to PP vector */
#else
@@ -713,9 +1620,8 @@ union cvmx_ciu_dint
#endif
} cn52xx;
struct cvmx_ciu_dint_cn52xx cn52xxp1;
- struct cvmx_ciu_dint_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_dint_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t dint : 12; /**< Send DINT pulse to PP vector */
#else
@@ -724,11 +1630,11 @@ union cvmx_ciu_dint
#endif
} cn56xx;
struct cvmx_ciu_dint_cn56xx cn56xxp1;
- struct cvmx_ciu_dint_s cn58xx;
- struct cvmx_ciu_dint_s cn58xxp1;
- struct cvmx_ciu_dint_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_dint_cn38xx cn58xx;
+ struct cvmx_ciu_dint_cn38xx cn58xxp1;
+ struct cvmx_ciu_dint_cn52xx cn61xx;
+ struct cvmx_ciu_dint_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t dint : 6; /**< Send DINT pulse to PP vector */
#else
@@ -737,28 +1643,541 @@ union cvmx_ciu_dint
#endif
} cn63xx;
struct cvmx_ciu_dint_cn63xx cn63xxp1;
+ struct cvmx_ciu_dint_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t dint : 10; /**< Send DINT pulse to PP vector */
+#else
+ uint64_t dint : 10;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_dint_s cn68xx;
+ struct cvmx_ciu_dint_s cn68xxp1;
+ struct cvmx_ciu_dint_cn52xx cnf71xx;
};
typedef union cvmx_ciu_dint cvmx_ciu_dint_t;
/**
+ * cvmx_ciu_en2_io#_int
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_en2_iox_int {
+ uint64_t u64;
+ struct cvmx_ciu_en2_iox_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_iox_int_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_iox_int_cn61xx cn66xx;
+ struct cvmx_ciu_en2_iox_int_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_iox_int cvmx_ciu_en2_iox_int_t;
+
+/**
+ * cvmx_ciu_en2_io#_int_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_iox_int_w1c {
+ uint64_t u64;
+ struct cvmx_ciu_en2_iox_int_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_iox_int_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx;
+ struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_iox_int_w1c cvmx_ciu_en2_iox_int_w1c_t;
+
+/**
+ * cvmx_ciu_en2_io#_int_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_iox_int_w1s {
+ uint64_t u64;
+ struct cvmx_ciu_en2_iox_int_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_iox_int_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx;
+ struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_iox_int_w1s cvmx_ciu_en2_iox_int_w1s_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip2
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_en2_ppx_ip2 {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip2_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip2_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip2 cvmx_ciu_en2_ppx_ip2_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip2_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip2_w1c {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip2_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip2_w1c cvmx_ciu_en2_ppx_ip2_w1c_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip2_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip2_w1s {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip2_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip2_w1s cvmx_ciu_en2_ppx_ip2_w1s_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip3
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_en2_ppx_ip3 {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip3_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip3_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip3 cvmx_ciu_en2_ppx_ip3_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip3_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip3_w1c {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip3_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip3_w1c cvmx_ciu_en2_ppx_ip3_w1c_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip3_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip3_w1s {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip3_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip3_w1s cvmx_ciu_en2_ppx_ip3_w1s_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip4
+ *
+ * Notes:
+ * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
+ *
+ */
+union cvmx_ciu_en2_ppx_ip4 {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip4_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip4_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip4_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip4 cvmx_ciu_en2_ppx_ip4_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip4_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip4_w1c {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip4_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip4_w1c cvmx_ciu_en2_ppx_ip4_w1c_t;
+
+/**
+ * cvmx_ciu_en2_pp#_ip4_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
+ * CIU_EN2_PP(IO)X_IPx(INT) value.
+ */
+union cvmx_ciu_en2_ppx_ip4_w1s {
+ uint64_t u64;
+ struct cvmx_ciu_en2_ppx_ip4_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_15_63 : 49;
+ uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */
+ uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */
+ uint64_t reserved_10_11 : 2;
+ uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_11 : 2;
+ uint64_t eoi : 1;
+ uint64_t endor : 2;
+ uint64_t reserved_15_63 : 49;
+#endif
+ } s;
+ struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
+ uint64_t reserved_0_3 : 4;
+#else
+ uint64_t reserved_0_3 : 4;
+ uint64_t timer : 6;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx;
+ struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx;
+};
+typedef union cvmx_ciu_en2_ppx_ip4_w1s cvmx_ciu_en2_ppx_ip4_w1s_t;
+
+/**
* cvmx_ciu_fuse
*/
-union cvmx_ciu_fuse
-{
+union cvmx_ciu_fuse {
uint64_t u64;
- struct cvmx_ciu_fuse_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
- uint64_t reserved_16_63 : 48;
- uint64_t fuse : 16; /**< Physical PP is present */
+ struct cvmx_ciu_fuse_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_32_63 : 32;
+ uint64_t fuse : 32; /**< Physical PP is present */
#else
- uint64_t fuse : 16;
- uint64_t reserved_16_63 : 48;
+ uint64_t fuse : 32;
+ uint64_t reserved_32_63 : 32;
#endif
} s;
- struct cvmx_ciu_fuse_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_fuse_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t fuse : 1; /**< Physical PP is present */
#else
@@ -766,9 +2185,8 @@ union cvmx_ciu_fuse
uint64_t reserved_1_63 : 63;
#endif
} cn30xx;
- struct cvmx_ciu_fuse_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_fuse_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t fuse : 2; /**< Physical PP is present */
#else
@@ -776,12 +2194,19 @@ union cvmx_ciu_fuse
uint64_t reserved_2_63 : 62;
#endif
} cn31xx;
- struct cvmx_ciu_fuse_s cn38xx;
- struct cvmx_ciu_fuse_s cn38xxp2;
+ struct cvmx_ciu_fuse_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_16_63 : 48;
+ uint64_t fuse : 16; /**< Physical PP is present */
+#else
+ uint64_t fuse : 16;
+ uint64_t reserved_16_63 : 48;
+#endif
+ } cn38xx;
+ struct cvmx_ciu_fuse_cn38xx cn38xxp2;
struct cvmx_ciu_fuse_cn31xx cn50xx;
- struct cvmx_ciu_fuse_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_fuse_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63 : 60;
uint64_t fuse : 4; /**< Physical PP is present */
#else
@@ -790,9 +2215,8 @@ union cvmx_ciu_fuse
#endif
} cn52xx;
struct cvmx_ciu_fuse_cn52xx cn52xxp1;
- struct cvmx_ciu_fuse_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_fuse_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t fuse : 12; /**< Physical PP is present */
#else
@@ -801,11 +2225,11 @@ union cvmx_ciu_fuse
#endif
} cn56xx;
struct cvmx_ciu_fuse_cn56xx cn56xxp1;
- struct cvmx_ciu_fuse_s cn58xx;
- struct cvmx_ciu_fuse_s cn58xxp1;
- struct cvmx_ciu_fuse_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_fuse_cn38xx cn58xx;
+ struct cvmx_ciu_fuse_cn38xx cn58xxp1;
+ struct cvmx_ciu_fuse_cn52xx cn61xx;
+ struct cvmx_ciu_fuse_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63 : 58;
uint64_t fuse : 6; /**< Physical PP is present */
#else
@@ -814,18 +2238,28 @@ union cvmx_ciu_fuse
#endif
} cn63xx;
struct cvmx_ciu_fuse_cn63xx cn63xxp1;
+ struct cvmx_ciu_fuse_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t reserved_10_63 : 54;
+ uint64_t fuse : 10; /**< Physical PP is present */
+#else
+ uint64_t fuse : 10;
+ uint64_t reserved_10_63 : 54;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_fuse_s cn68xx;
+ struct cvmx_ciu_fuse_s cn68xxp1;
+ struct cvmx_ciu_fuse_cn52xx cnf71xx;
};
typedef union cvmx_ciu_fuse cvmx_ciu_fuse_t;
/**
* cvmx_ciu_gstop
*/
-union cvmx_ciu_gstop
-{
+union cvmx_ciu_gstop {
uint64_t u64;
- struct cvmx_ciu_gstop_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_gstop_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t gstop : 1; /**< GSTOP bit */
#else
@@ -844,8 +2278,13 @@ union cvmx_ciu_gstop
struct cvmx_ciu_gstop_s cn56xxp1;
struct cvmx_ciu_gstop_s cn58xx;
struct cvmx_ciu_gstop_s cn58xxp1;
+ struct cvmx_ciu_gstop_s cn61xx;
struct cvmx_ciu_gstop_s cn63xx;
struct cvmx_ciu_gstop_s cn63xxp1;
+ struct cvmx_ciu_gstop_s cn66xx;
+ struct cvmx_ciu_gstop_s cn68xx;
+ struct cvmx_ciu_gstop_s cn68xxp1;
+ struct cvmx_ciu_gstop_s cnf71xx;
};
typedef union cvmx_ciu_gstop cvmx_ciu_gstop_t;
@@ -853,27 +2292,31 @@ typedef union cvmx_ciu_gstop cvmx_ciu_gstop_t;
* cvmx_ciu_int#_en0
*
* Notes:
- * CIU_INT0_EN0: PP0 /IP2
- * CIU_INT1_EN0: PP0 /IP3
- * ...
+ * CIU_INT0_EN0: PP0/IP2
+ * CIU_INT1_EN0: PP0/IP3
+ * CIU_INT2_EN0: PP1/IP2
+ * CIU_INT3_EN0: PP1/IP3
+ * CIU_INT4_EN0: PP2/IP2
+ * CIU_INT5_EN0: PP2/IP3
* CIU_INT6_EN0: PP3/IP2
* CIU_INT7_EN0: PP3/IP3
+ * .....
+ *
* (hole)
- * CIU_INT32_EN0: PCI /IP
+ * CIU_INT32_EN0: IO 0
+ * CIU_INT33_EN0: IO 1
*/
-union cvmx_ciu_intx_en0
-{
+union cvmx_ciu_intx_en0 {
uint64_t u64;
- struct cvmx_ciu_intx_en0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
uint64_t powiq : 1; /**< POW IQ interrupt enable */
uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
- uint64_t mpi : 1; /**< MPI/SPI interrupt */
- uint64_t pcm : 1; /**< PCM/TDM interrupt */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
uint64_t timer : 4; /**< General timer interrupt enables */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
@@ -883,10 +2326,10 @@ union cvmx_ciu_intx_en0
uint64_t rml : 1; /**< RML Interrupt enable */
uint64_t twsi : 1; /**< TWSI Interrupt enable */
uint64_t reserved_44_44 : 1;
- uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */
+ uint64_t pci_msi : 4; /**< PCIe MSI enables */
uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
uint64_t uart : 2; /**< Two UART interrupt enables */
- uint64_t mbox : 2; /**< Two mailbox/PCIe/sRIO interrupt enables */
+ uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
uint64_t workq : 16; /**< 16 work queue interrupt enables */
#else
@@ -914,9 +2357,8 @@ union cvmx_ciu_intx_en0
uint64_t bootdma : 1;
#endif
} s;
- struct cvmx_ciu_intx_en0_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63 : 5;
uint64_t mpi : 1; /**< MPI/SPI interrupt */
uint64_t pcm : 1; /**< PCM/TDM interrupt */
@@ -958,9 +2400,8 @@ union cvmx_ciu_intx_en0
uint64_t reserved_59_63 : 5;
#endif
} cn30xx;
- struct cvmx_ciu_intx_en0_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63 : 5;
uint64_t mpi : 1; /**< MPI/SPI interrupt */
uint64_t pcm : 1; /**< PCM/TDM interrupt */
@@ -1002,9 +2443,8 @@ union cvmx_ciu_intx_en0
uint64_t reserved_59_63 : 5;
#endif
} cn31xx;
- struct cvmx_ciu_intx_en0_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63 : 8;
uint64_t timer : 4; /**< General timer interrupts */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
@@ -1040,9 +2480,8 @@ union cvmx_ciu_intx_en0
} cn38xx;
struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
struct cvmx_ciu_intx_en0_cn30xx cn50xx;
- struct cvmx_ciu_intx_en0_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -1091,9 +2530,8 @@ union cvmx_ciu_intx_en0
#endif
} cn52xx;
struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
- struct cvmx_ciu_intx_en0_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -1142,8 +2580,157 @@ union cvmx_ciu_intx_en0
struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
struct cvmx_ciu_intx_en0_cn38xx cn58xx;
struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
+ struct cvmx_ciu_intx_en0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
+ uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt enable */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
+ uint64_t powiq : 1; /**< POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
+ uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< RML Interrupt enable */
+ uint64_t twsi : 1; /**< TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCIe MSI enables */
+ uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Two UART interrupt enables */
+ uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
+ uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
+ uint64_t workq : 16; /**< 16 work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn61xx;
struct cvmx_ciu_intx_en0_cn52xx cn63xx;
struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
+ struct cvmx_ciu_intx_en0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
+ uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
+ uint64_t powiq : 1; /**< POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
+ uint64_t reserved_57_57 : 1;
+ uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
+ uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< RML Interrupt enable */
+ uint64_t twsi : 1; /**< TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */
+ uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Two UART interrupt enables */
+ uint64_t mbox : 2; /**< Two mailbox/PCIe/sRIO interrupt enables */
+ uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
+ uint64_t workq : 16; /**< 16 work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_57 : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
+ uint64_t powiq : 1; /**< POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
+ uint64_t reserved_49_49 : 1;
+ uint64_t gmx_drp : 1; /**< GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< RML Interrupt enable */
+ uint64_t twsi : 1; /**< TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCIe MSI enables */
+ uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Two UART interrupt enables */
+ uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
+ uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
+ uint64_t workq : 16; /**< 16 work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 1;
+ uint64_t reserved_49_49 : 1;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en0 cvmx_ciu_intx_en0_t;
@@ -1151,26 +2738,25 @@ typedef union cvmx_ciu_intx_en0 cvmx_ciu_intx_en0_t;
* cvmx_ciu_int#_en0_w1c
*
* Notes:
- * Write-1-to-clear version of the CIU_INTx_EN0 register
+ * Write-1-to-clear version of the CIU_INTx_EN0 register, read back corresponding CIU_INTx_EN0 value.
*
*/
-union cvmx_ciu_intx_en0_w1c
-{
+union cvmx_ciu_intx_en0_w1c {
uint64_t u64;
- struct cvmx_ciu_intx_en0_w1c_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
enable */
uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
enable */
uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
interrupt enable */
- uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */
- uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */
- uint64_t reserved_57_58 : 2;
- uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */
- uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */
+ uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
enable */
@@ -1179,10 +2765,10 @@ union cvmx_ciu_intx_en0_w1c
uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
uint64_t reserved_44_44 : 1;
- uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */
+ uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
- uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe/sRIO interrupt
+ uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
enables */
uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
@@ -1202,7 +2788,8 @@ union cvmx_ciu_intx_en0_w1c
uint64_t key_zero : 1;
uint64_t timer : 4;
uint64_t usb : 1;
- uint64_t reserved_57_58 : 2;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
uint64_t twsi2 : 1;
uint64_t powiq : 1;
uint64_t ipdppthr : 1;
@@ -1210,9 +2797,8 @@ union cvmx_ciu_intx_en0_w1c
uint64_t bootdma : 1;
#endif
} s;
- struct cvmx_ciu_intx_en0_w1c_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -1260,10 +2846,55 @@ union cvmx_ciu_intx_en0_w1c
uint64_t bootdma : 1;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en0_w1c_s cn56xx;
- struct cvmx_ciu_intx_en0_w1c_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
+ uint64_t mii : 1; /**< MII Interface Interrupt */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
+ uint64_t powiq : 1; /**< POW IQ interrupt */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
+ uint64_t reserved_57_58 : 2;
+ uint64_t usb : 1; /**< USB Interrupt */
+ uint64_t timer : 4; /**< General timer interrupts */
+ uint64_t key_zero : 1; /**< Key Zeroization interrupt */
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
+ uint64_t gmx_drp : 2; /**< GMX packet drop */
+ uint64_t trace : 1; /**< L2C has the CMB trace buffer */
+ uint64_t rml : 1; /**< RML Interrupt */
+ uint64_t twsi : 1; /**< TWSI Interrupt */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCI MSI */
+ uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
+ uint64_t uart : 2; /**< Two UART interrupts */
+ uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
+ uint64_t gpio : 16; /**< 16 GPIO interrupts */
+ uint64_t workq : 16; /**< 16 work queue interrupts */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t key_zero : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_58 : 2;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en0_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63 : 8;
uint64_t timer : 4; /**< General timer interrupts */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
@@ -1297,8 +2928,171 @@ union cvmx_ciu_intx_en0_w1c
uint64_t reserved_56_63 : 8;
#endif
} cn58xx;
+ struct cvmx_ciu_intx_en0_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
+ enable */
+ uint64_t mii : 1; /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt
+ enable */
+ uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
+ enable */
+ uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
+ enables */
+ uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn61xx;
struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
+ struct cvmx_ciu_intx_en0_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
+ enable */
+ uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
+ enable */
+ uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */
+ uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */
+ uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt */
+ uint64_t reserved_57_57 : 1;
+ uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */
+ uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
+ enable */
+ uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe/sRIO interrupt
+ enables */
+ uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_57 : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en0_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
+ enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
+ enable */
+ uint64_t reserved_49_49 : 1;
+ uint64_t gmx_drp : 1; /**< Write 1 to clear GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
+ enables */
+ uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 1;
+ uint64_t reserved_49_49 : 1;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1c_t;
@@ -1306,26 +3100,25 @@ typedef union cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1c_t;
* cvmx_ciu_int#_en0_w1s
*
* Notes:
- * Write-1-to-set version of the CIU_INTx_EN0 register
+ * Write-1-to-set version of the CIU_INTx_EN0 register, read back corresponding CIU_INTx_EN0 value.
*
*/
-union cvmx_ciu_intx_en0_w1s
-{
+union cvmx_ciu_intx_en0_w1s {
uint64_t u64;
- struct cvmx_ciu_intx_en0_w1s_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
enable */
uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
enable */
uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
interrupt enable */
- uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */
- uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */
- uint64_t reserved_57_58 : 2;
- uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */
- uint64_t timer : 4; /**< Write 1 to set General timer interrupts */
+ uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
enable */
@@ -1334,10 +3127,10 @@ union cvmx_ciu_intx_en0_w1s
uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
uint64_t reserved_44_44 : 1;
- uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */
+ uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
- uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe/sRIO interrupt
+ uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
enables */
uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
@@ -1357,7 +3150,8 @@ union cvmx_ciu_intx_en0_w1s
uint64_t key_zero : 1;
uint64_t timer : 4;
uint64_t usb : 1;
- uint64_t reserved_57_58 : 2;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
uint64_t twsi2 : 1;
uint64_t powiq : 1;
uint64_t ipdppthr : 1;
@@ -1365,9 +3159,8 @@ union cvmx_ciu_intx_en0_w1s
uint64_t bootdma : 1;
#endif
} s;
- struct cvmx_ciu_intx_en0_w1s_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -1415,10 +3208,55 @@ union cvmx_ciu_intx_en0_w1s
uint64_t bootdma : 1;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en0_w1s_s cn56xx;
- struct cvmx_ciu_intx_en0_w1s_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en0_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
+ uint64_t mii : 1; /**< MII Interface Interrupt */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
+ uint64_t powiq : 1; /**< POW IQ interrupt */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
+ uint64_t reserved_57_58 : 2;
+ uint64_t usb : 1; /**< USB Interrupt */
+ uint64_t timer : 4; /**< General timer interrupts */
+ uint64_t key_zero : 1; /**< Key Zeroization interrupt */
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
+ uint64_t gmx_drp : 2; /**< GMX packet drop */
+ uint64_t trace : 1; /**< L2C has the CMB trace buffer */
+ uint64_t rml : 1; /**< RML Interrupt */
+ uint64_t twsi : 1; /**< TWSI Interrupt */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCI MSI */
+ uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
+ uint64_t uart : 2; /**< Two UART interrupts */
+ uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
+ uint64_t gpio : 16; /**< 16 GPIO interrupts */
+ uint64_t workq : 16; /**< 16 work queue interrupts */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t key_zero : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_58 : 2;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en0_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63 : 8;
uint64_t timer : 4; /**< General timer interrupts */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
@@ -1452,8 +3290,171 @@ union cvmx_ciu_intx_en0_w1s
uint64_t reserved_56_63 : 8;
#endif
} cn58xx;
+ struct cvmx_ciu_intx_en0_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
+ enable */
+ uint64_t mii : 1; /**< Write 1 to set RGMII/MIX Interface 0 Interrupt
+ enable */
+ uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
+ enable */
+ uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
+ enables */
+ uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn61xx;
struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
+ struct cvmx_ciu_intx_en0_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
+ enable */
+ uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
+ enable */
+ uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */
+ uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */
+ uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt */
+ uint64_t reserved_57_57 : 1;
+ uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */
+ uint64_t timer : 4; /**< Write 1 to set General timer interrupts */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
+ enable */
+ uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe/sRIO interrupt
+ enables */
+ uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_57 : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en0_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
+ enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
+ enable */
+ uint64_t reserved_49_49 : 1;
+ uint64_t gmx_drp : 1; /**< Write 1 to set GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
+ enables */
+ uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 1;
+ uint64_t reserved_49_49 : 1;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en0_w1s_t;
@@ -1461,30 +3462,47 @@ typedef union cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en0_w1s_t;
* cvmx_ciu_int#_en1
*
* Notes:
+ * Enables for CIU_SUM1_PPX_IPx or CIU_SUM1_IOX_INT
+ * CIU_INT0_EN1: PP0/IP2
+ * CIU_INT1_EN1: PP0/IP3
+ * CIU_INT2_EN1: PP1/IP2
+ * CIU_INT3_EN1: PP1/IP3
+ * CIU_INT4_EN1: PP2/IP2
+ * CIU_INT5_EN1: PP2/IP3
+ * CIU_INT6_EN1: PP3/IP2
+ * CIU_INT7_EN1: PP3/IP3
+ * .....
+ *
+ * (hole)
+ * CIU_INT32_EN1: IO0
+ * CIU_INT33_EN1: IO1
+ *
* @verbatim
* PPx/IP2 will be raised when...
*
* n = x*2
- * PPx/IP2 = |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
+ * PPx/IP2 = |([CIU_SUM2_PPx_IP2,CIU_SUM1_PPx_IP2, CIU_INTn_SUM0] & [CIU_EN2_PPx_IP2,CIU_INTn_EN1, CIU_INTn_EN0])
*
* PPx/IP3 will be raised when...
*
* n = x*2 + 1
- * PPx/IP3 = |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
+ * PPx/IP3 = |([CIU_SUM2_PPx_IP3,CIU_SUM1_PPx_IP3, CIU_INTn_SUM0] & [CIU_EN2_PPx_IP3,CIU_INTn_EN1, CIU_INTn_EN0])
*
* PCI/INT will be raised when...
*
- * PCI/INT = |([CIU_INT_SUM1, CIU_INT32_SUM0] & [CIU_INT32_EN1, CIU_INT32_EN0])
+ * PCI/INT = |([CIU_SUM2_IO0_INT,CIU_SUM1_IO0_INT, CIU_INT32_SUM0] & [CIU_EN2_IO0_INT,CIU_INT32_EN1, CIU_INT32_EN0])
+ * PCI/INT = |([CIU_SUM2_IO1_INT,CIU_SUM1_IO1_INT, CIU_INT33_SUM0] & [CIU_EN2_IO1_INT,CIU_INT33_EN1, CIU_INT33_EN0])
* @endverbatim
*/
-union cvmx_ciu_intx_en1
-{
+union cvmx_ciu_intx_en1 {
uint64_t u64;
- struct cvmx_ciu_intx_en1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< MIO RST interrupt enable */
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
uint64_t dfm : 1; /**< DFM interrupt enable */
uint64_t reserved_53_55 : 3;
uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
@@ -1494,7 +3512,10 @@ union cvmx_ciu_intx_en1
uint64_t pem0 : 1; /**< PEM0 interrupt enable */
uint64_t ptp : 1; /**< PTP interrupt enable */
uint64_t agl : 1; /**< AGL interrupt enable */
- uint64_t reserved_37_45 : 9;
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< GMX1 interrupt enable */
uint64_t agx0 : 1; /**< GMX0 interrupt enable */
uint64_t dpi : 1; /**< DPI interrupt enable */
uint64_t sli : 1; /**< SLI interrupt enable */
@@ -1512,7 +3533,7 @@ union cvmx_ciu_intx_en1
uint64_t fpa : 1; /**< FPA interrupt enable */
uint64_t iob : 1; /**< IOB interrupt enable */
uint64_t mio : 1; /**< MIO boot interrupt enable */
- uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */
+ uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
uint64_t usb1 : 1; /**< Second USB Interrupt */
uint64_t uart2 : 1; /**< Third UART interrupt */
@@ -1540,7 +3561,10 @@ union cvmx_ciu_intx_en1
uint64_t sli : 1;
uint64_t dpi : 1;
uint64_t agx0 : 1;
- uint64_t reserved_37_45 : 9;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
uint64_t agl : 1;
uint64_t ptp : 1;
uint64_t pem0 : 1;
@@ -1550,13 +3574,15 @@ union cvmx_ciu_intx_en1
uint64_t lmc0 : 1;
uint64_t reserved_53_55 : 3;
uint64_t dfm : 1;
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
uint64_t rst : 1;
#endif
} s;
- struct cvmx_ciu_intx_en1_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t wdog : 1; /**< Watchdog summary interrupt enable vector */
#else
@@ -1564,9 +3590,8 @@ union cvmx_ciu_intx_en1
uint64_t reserved_1_63 : 63;
#endif
} cn30xx;
- struct cvmx_ciu_intx_en1_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t wdog : 2; /**< Watchdog summary interrupt enable vectory */
#else
@@ -1574,9 +3599,8 @@ union cvmx_ciu_intx_en1
uint64_t reserved_2_63 : 62;
#endif
} cn31xx;
- struct cvmx_ciu_intx_en1_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
#else
@@ -1586,9 +3610,8 @@ union cvmx_ciu_intx_en1
} cn38xx;
struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
struct cvmx_ciu_intx_en1_cn31xx cn50xx;
- struct cvmx_ciu_intx_en1_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t nand : 1; /**< NAND Flash Controller */
uint64_t mii1 : 1; /**< Second MII Interrupt */
@@ -1606,9 +3629,8 @@ union cvmx_ciu_intx_en1
uint64_t reserved_20_63 : 44;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en1_cn52xxp1
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63 : 45;
uint64_t mii1 : 1; /**< Second MII Interrupt */
uint64_t usb1 : 1; /**< Second USB Interrupt */
@@ -1624,9 +3646,8 @@ union cvmx_ciu_intx_en1
uint64_t reserved_19_63 : 45;
#endif
} cn52xxp1;
- struct cvmx_ciu_intx_en1_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
#else
@@ -1637,9 +3658,79 @@ union cvmx_ciu_intx_en1
struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
struct cvmx_ciu_intx_en1_cn38xx cn58xx;
struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
- struct cvmx_ciu_intx_en1_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< PTP interrupt enable */
+ uint64_t agl : 1; /**< AGL interrupt enable */
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< DPI interrupt enable */
+ uint64_t sli : 1; /**< SLI interrupt enable */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< DFA interrupt enable */
+ uint64_t key : 1; /**< KEY interrupt enable */
+ uint64_t rad : 1; /**< RAD interrupt enable */
+ uint64_t tim : 1; /**< TIM interrupt enable */
+ uint64_t zip : 1; /**< ZIP interrupt enable */
+ uint64_t pko : 1; /**< PKO interrupt enable */
+ uint64_t pip : 1; /**< PIP interrupt enable */
+ uint64_t ipd : 1; /**< IPD interrupt enable */
+ uint64_t l2c : 1; /**< L2C interrupt enable */
+ uint64_t pow : 1; /**< POW err interrupt enable */
+ uint64_t fpa : 1; /**< FPA interrupt enable */
+ uint64_t iob : 1; /**< IOB interrupt enable */
+ uint64_t mio : 1; /**< MIO boot interrupt enable */
+ uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
+ uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt enable */
+ uint64_t reserved_4_17 : 14;
+ uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_17 : 14;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_intx_en1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< MIO RST interrupt enable */
uint64_t reserved_57_62 : 6;
uint64_t dfm : 1; /**< DFM interrupt enable */
@@ -1710,6 +3801,150 @@ union cvmx_ciu_intx_en1
#endif
} cn63xx;
struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
+ struct cvmx_ciu_intx_en1_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< MIO RST interrupt enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
+ uint64_t dfm : 1; /**< DFM interrupt enable */
+ uint64_t reserved_53_55 : 3;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
+ uint64_t reserved_51_51 : 1;
+ uint64_t srio0 : 1; /**< SRIO0 interrupt enable */
+ uint64_t pem1 : 1; /**< PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< PTP interrupt enable */
+ uint64_t agl : 1; /**< AGL interrupt enable */
+ uint64_t reserved_38_45 : 8;
+ uint64_t agx1 : 1; /**< GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< DPI interrupt enable */
+ uint64_t sli : 1; /**< SLI interrupt enable */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< DFA interrupt enable */
+ uint64_t key : 1; /**< KEY interrupt enable */
+ uint64_t rad : 1; /**< RAD interrupt enable */
+ uint64_t tim : 1; /**< TIM interrupt enable */
+ uint64_t zip : 1; /**< ZIP interrupt enable */
+ uint64_t pko : 1; /**< PKO interrupt enable */
+ uint64_t pip : 1; /**< PIP interrupt enable */
+ uint64_t ipd : 1; /**< IPD interrupt enable */
+ uint64_t l2c : 1; /**< L2C interrupt enable */
+ uint64_t pow : 1; /**< POW err interrupt enable */
+ uint64_t fpa : 1; /**< FPA interrupt enable */
+ uint64_t iob : 1; /**< IOB interrupt enable */
+ uint64_t mio : 1; /**< MIO boot interrupt enable */
+ uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */
+ uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
+ uint64_t reserved_10_17 : 8;
+ uint64_t wdog : 10; /**< Watchdog summary interrupt enable vector */
+#else
+ uint64_t wdog : 10;
+ uint64_t reserved_10_17 : 8;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_45 : 8;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t srio0 : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t dfm : 1;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t rst : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en1_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< PTP interrupt enable */
+ uint64_t reserved_41_46 : 6;
+ uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
+ uint64_t reserved_37_39 : 3;
+ uint64_t agx0 : 1; /**< GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< DPI interrupt enable */
+ uint64_t sli : 1; /**< SLI interrupt enable */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
+ uint64_t reserved_32_32 : 1;
+ uint64_t key : 1; /**< KEY interrupt enable */
+ uint64_t rad : 1; /**< RAD interrupt enable */
+ uint64_t tim : 1; /**< TIM interrupt enable */
+ uint64_t reserved_28_28 : 1;
+ uint64_t pko : 1; /**< PKO interrupt enable */
+ uint64_t pip : 1; /**< PIP interrupt enable */
+ uint64_t ipd : 1; /**< IPD interrupt enable */
+ uint64_t l2c : 1; /**< L2C interrupt enable */
+ uint64_t pow : 1; /**< POW err interrupt enable */
+ uint64_t fpa : 1; /**< FPA interrupt enable */
+ uint64_t iob : 1; /**< IOB interrupt enable */
+ uint64_t mio : 1; /**< MIO boot interrupt enable */
+ uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
+ uint64_t reserved_4_18 : 15;
+ uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_18 : 15;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t reserved_28_28 : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t reserved_32_32 : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t reserved_37_39 : 3;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_46 : 6;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en1 cvmx_ciu_intx_en1_t;
@@ -1717,17 +3952,18 @@ typedef union cvmx_ciu_intx_en1 cvmx_ciu_intx_en1_t;
* cvmx_ciu_int#_en1_w1c
*
* Notes:
- * Write-1-to-clear version of the CIU_INTx_EN1 register
+ * Write-1-to-clear version of the CIU_INTX_EN1 register, read back corresponding CIU_INTX_EN1 value.
*
*/
-union cvmx_ciu_intx_en1_w1c
-{
+union cvmx_ciu_intx_en1_w1c {
uint64_t u64;
- struct cvmx_ciu_intx_en1_w1c_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
uint64_t reserved_53_55 : 3;
uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
@@ -1737,7 +3973,10 @@ union cvmx_ciu_intx_en1_w1c
uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
- uint64_t reserved_37_45 : 9;
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
@@ -1755,7 +3994,7 @@ union cvmx_ciu_intx_en1_w1c
uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
- uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt
+ uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
enable */
uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
Interrupt enable */
@@ -1785,7 +4024,10 @@ union cvmx_ciu_intx_en1_w1c
uint64_t sli : 1;
uint64_t dpi : 1;
uint64_t agx0 : 1;
- uint64_t reserved_37_45 : 9;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
uint64_t agl : 1;
uint64_t ptp : 1;
uint64_t pem0 : 1;
@@ -1795,13 +4037,15 @@ union cvmx_ciu_intx_en1_w1c
uint64_t lmc0 : 1;
uint64_t reserved_53_55 : 3;
uint64_t dfm : 1;
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
uint64_t rst : 1;
#endif
} s;
- struct cvmx_ciu_intx_en1_w1c_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t nand : 1; /**< NAND Flash Controller */
uint64_t mii1 : 1; /**< Second MII Interrupt */
@@ -1819,9 +4063,8 @@ union cvmx_ciu_intx_en1_w1c
uint64_t reserved_20_63 : 44;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en1_w1c_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
#else
@@ -1829,9 +4072,8 @@ union cvmx_ciu_intx_en1_w1c
uint64_t reserved_12_63 : 52;
#endif
} cn56xx;
- struct cvmx_ciu_intx_en1_w1c_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
#else
@@ -1839,9 +4081,81 @@ union cvmx_ciu_intx_en1_w1c
uint64_t reserved_16_63 : 48;
#endif
} cn58xx;
- struct cvmx_ciu_intx_en1_w1c_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
+ uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
+ uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
+ uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
+ uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
+ enable */
+ uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MIX Interface 1
+ Interrupt enable */
+ uint64_t reserved_4_17 : 14;
+ uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_17 : 14;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_intx_en1_w1c_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
uint64_t reserved_57_62 : 6;
uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
@@ -1914,6 +4228,153 @@ union cvmx_ciu_intx_en1_w1c
#endif
} cn63xx;
struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
+ struct cvmx_ciu_intx_en1_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
+ uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
+ uint64_t reserved_53_55 : 3;
+ uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
+ uint64_t reserved_51_51 : 1;
+ uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */
+ uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
+ uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
+ uint64_t reserved_38_45 : 8;
+ uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
+ uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
+ uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
+ uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt
+ enable */
+ uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
+ Interrupt enable */
+ uint64_t reserved_10_17 : 8;
+ uint64_t wdog : 10; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 10;
+ uint64_t reserved_10_17 : 8;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_45 : 8;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t srio0 : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t dfm : 1;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t rst : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en1_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
+ uint64_t reserved_41_46 : 6;
+ uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
+ uint64_t reserved_37_39 : 3;
+ uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
+ uint64_t reserved_32_32 : 1;
+ uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
+ uint64_t reserved_28_28 : 1;
+ uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
+ enable */
+ uint64_t reserved_4_18 : 15;
+ uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_18 : 15;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t reserved_28_28 : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t reserved_32_32 : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t reserved_37_39 : 3;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_46 : 6;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1c_t;
@@ -1921,17 +4382,18 @@ typedef union cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1c_t;
* cvmx_ciu_int#_en1_w1s
*
* Notes:
- * Write-1-to-set version of the CIU_INTx_EN1 register
+ * Write-1-to-set version of the CIU_INTX_EN1 register, read back corresponding CIU_INTX_EN1 value.
*
*/
-union cvmx_ciu_intx_en1_w1s
-{
+union cvmx_ciu_intx_en1_w1s {
uint64_t u64;
- struct cvmx_ciu_intx_en1_w1s_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
uint64_t reserved_53_55 : 3;
uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
@@ -1941,7 +4403,10 @@ union cvmx_ciu_intx_en1_w1s
uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
- uint64_t reserved_37_45 : 9;
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
@@ -1959,7 +4424,7 @@ union cvmx_ciu_intx_en1_w1s
uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
- uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt
+ uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
enable */
uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
enable */
@@ -1989,7 +4454,10 @@ union cvmx_ciu_intx_en1_w1s
uint64_t sli : 1;
uint64_t dpi : 1;
uint64_t agx0 : 1;
- uint64_t reserved_37_45 : 9;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
uint64_t agl : 1;
uint64_t ptp : 1;
uint64_t pem0 : 1;
@@ -1999,13 +4467,15 @@ union cvmx_ciu_intx_en1_w1s
uint64_t lmc0 : 1;
uint64_t reserved_53_55 : 3;
uint64_t dfm : 1;
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
uint64_t rst : 1;
#endif
} s;
- struct cvmx_ciu_intx_en1_w1s_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t nand : 1; /**< NAND Flash Controller */
uint64_t mii1 : 1; /**< Second MII Interrupt */
@@ -2023,9 +4493,8 @@ union cvmx_ciu_intx_en1_w1s
uint64_t reserved_20_63 : 44;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en1_w1s_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
#else
@@ -2033,9 +4502,8 @@ union cvmx_ciu_intx_en1_w1s
uint64_t reserved_12_63 : 52;
#endif
} cn56xx;
- struct cvmx_ciu_intx_en1_w1s_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
#else
@@ -2043,9 +4511,81 @@ union cvmx_ciu_intx_en1_w1s
uint64_t reserved_16_63 : 48;
#endif
} cn58xx;
- struct cvmx_ciu_intx_en1_w1s_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en1_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
+ uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
+ uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
+ uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
+ uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
+ enable */
+ uint64_t mii1 : 1; /**< Write 1 to set RGMII/MIX Interface 1 Interrupt
+ enable */
+ uint64_t reserved_4_17 : 14;
+ uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_17 : 14;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_intx_en1_w1s_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
uint64_t reserved_57_62 : 6;
uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
@@ -2118,6 +4658,153 @@ union cvmx_ciu_intx_en1_w1s
#endif
} cn63xx;
struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
+ struct cvmx_ciu_intx_en1_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
+ uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
+ uint64_t reserved_53_55 : 3;
+ uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
+ uint64_t reserved_51_51 : 1;
+ uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */
+ uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
+ uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
+ uint64_t reserved_38_45 : 8;
+ uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
+ uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
+ uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
+ uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt
+ enable */
+ uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
+ enable */
+ uint64_t reserved_10_17 : 8;
+ uint64_t wdog : 10; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 10;
+ uint64_t reserved_10_17 : 8;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_45 : 8;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t srio0 : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t dfm : 1;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t rst : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en1_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
+ uint64_t reserved_41_46 : 6;
+ uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
+ uint64_t reserved_37_39 : 3;
+ uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
+ uint64_t reserved_32_32 : 1;
+ uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
+ uint64_t reserved_28_28 : 1;
+ uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
+ enable */
+ uint64_t reserved_4_18 : 15;
+ uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_18 : 15;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t reserved_28_28 : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t reserved_32_32 : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t reserved_37_39 : 3;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_46 : 6;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en1_w1s_t;
@@ -2128,21 +4815,19 @@ typedef union cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en1_w1s_t;
* CIU_INT0_EN4_0: PP0 /IP4
* CIU_INT1_EN4_0: PP1 /IP4
* ...
- * CIU_INT11_EN4_0: PP11 /IP4
+ * CIU_INT3_EN4_0: PP3 /IP4
*/
-union cvmx_ciu_intx_en4_0
-{
+union cvmx_ciu_intx_en4_0 {
uint64_t u64;
- struct cvmx_ciu_intx_en4_0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
uint64_t powiq : 1; /**< POW IQ interrupt enable */
uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
- uint64_t mpi : 1; /**< MPI/SPI interrupt */
- uint64_t pcm : 1; /**< PCM/TDM interrupt */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
uint64_t timer : 4; /**< General timer interrupt enables */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
@@ -2152,7 +4837,7 @@ union cvmx_ciu_intx_en4_0
uint64_t rml : 1; /**< RML Interrupt enable */
uint64_t twsi : 1; /**< TWSI Interrupt enable */
uint64_t reserved_44_44 : 1;
- uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */
+ uint64_t pci_msi : 4; /**< PCIe MSI enables */
uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
uint64_t uart : 2; /**< Two UART interrupt enables */
uint64_t mbox : 2; /**< Two mailbox interrupt enables */
@@ -2183,9 +4868,8 @@ union cvmx_ciu_intx_en4_0
uint64_t bootdma : 1;
#endif
} s;
- struct cvmx_ciu_intx_en4_0_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63 : 5;
uint64_t mpi : 1; /**< MPI/SPI interrupt */
uint64_t pcm : 1; /**< PCM/TDM interrupt */
@@ -2227,9 +4911,8 @@ union cvmx_ciu_intx_en4_0
uint64_t reserved_59_63 : 5;
#endif
} cn50xx;
- struct cvmx_ciu_intx_en4_0_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -2278,9 +4961,8 @@ union cvmx_ciu_intx_en4_0
#endif
} cn52xx;
struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
- struct cvmx_ciu_intx_en4_0_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -2327,9 +5009,8 @@ union cvmx_ciu_intx_en4_0
#endif
} cn56xx;
struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
- struct cvmx_ciu_intx_en4_0_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63 : 8;
uint64_t timer : 4; /**< General timer interrupts */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
@@ -2364,8 +5045,157 @@ union cvmx_ciu_intx_en4_0
#endif
} cn58xx;
struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
+ struct cvmx_ciu_intx_en4_0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
+ uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt enable */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
+ uint64_t powiq : 1; /**< POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
+ uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< RML Interrupt enable */
+ uint64_t twsi : 1; /**< TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCIe MSI enables */
+ uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Two UART interrupt enables */
+ uint64_t mbox : 2; /**< Two mailbox interrupt enables */
+ uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
+ uint64_t workq : 16; /**< 16 work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn61xx;
struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
+ struct cvmx_ciu_intx_en4_0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
+ uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
+ uint64_t powiq : 1; /**< POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
+ uint64_t reserved_57_57 : 1;
+ uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
+ uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< RML Interrupt enable */
+ uint64_t twsi : 1; /**< TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */
+ uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Two UART interrupt enables */
+ uint64_t mbox : 2; /**< Two mailbox interrupt enables */
+ uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
+ uint64_t workq : 16; /**< 16 work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_57 : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en4_0_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
+ uint64_t powiq : 1; /**< POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
+ uint64_t reserved_49_49 : 1;
+ uint64_t gmx_drp : 1; /**< GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< RML Interrupt enable */
+ uint64_t twsi : 1; /**< TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCIe MSI enables */
+ uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Two UART interrupt enables */
+ uint64_t mbox : 2; /**< Two mailbox interrupt enables */
+ uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
+ uint64_t workq : 16; /**< 16 work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 1;
+ uint64_t reserved_49_49 : 1;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en4_0 cvmx_ciu_intx_en4_0_t;
@@ -2373,26 +5203,25 @@ typedef union cvmx_ciu_intx_en4_0 cvmx_ciu_intx_en4_0_t;
* cvmx_ciu_int#_en4_0_w1c
*
* Notes:
- * Write-1-to-clear version of the CIU_INTx_EN4_0 register
+ * Write-1-to-clear version of the CIU_INTx_EN4_0 register, read back corresponding CIU_INTx_EN4_0 value.
*
*/
-union cvmx_ciu_intx_en4_0_w1c
-{
+union cvmx_ciu_intx_en4_0_w1c {
uint64_t u64;
- struct cvmx_ciu_intx_en4_0_w1c_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
enable */
uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
enable */
uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
interrupt enable */
- uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */
- uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */
- uint64_t reserved_57_58 : 2;
- uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */
- uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */
+ uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
enable */
@@ -2401,7 +5230,7 @@ union cvmx_ciu_intx_en4_0_w1c
uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
uint64_t reserved_44_44 : 1;
- uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */
+ uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
@@ -2423,7 +5252,8 @@ union cvmx_ciu_intx_en4_0_w1c
uint64_t key_zero : 1;
uint64_t timer : 4;
uint64_t usb : 1;
- uint64_t reserved_57_58 : 2;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
uint64_t twsi2 : 1;
uint64_t powiq : 1;
uint64_t ipdppthr : 1;
@@ -2431,9 +5261,8 @@ union cvmx_ciu_intx_en4_0_w1c
uint64_t bootdma : 1;
#endif
} s;
- struct cvmx_ciu_intx_en4_0_w1c_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -2481,10 +5310,55 @@ union cvmx_ciu_intx_en4_0_w1c
uint64_t bootdma : 1;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
- struct cvmx_ciu_intx_en4_0_w1c_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
+ uint64_t mii : 1; /**< MII Interface Interrupt */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
+ uint64_t powiq : 1; /**< POW IQ interrupt */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
+ uint64_t reserved_57_58 : 2;
+ uint64_t usb : 1; /**< USB Interrupt */
+ uint64_t timer : 4; /**< General timer interrupts */
+ uint64_t key_zero : 1; /**< Key Zeroization interrupt */
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
+ uint64_t gmx_drp : 2; /**< GMX packet drop */
+ uint64_t trace : 1; /**< L2C has the CMB trace buffer */
+ uint64_t rml : 1; /**< RML Interrupt */
+ uint64_t twsi : 1; /**< TWSI Interrupt */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCI MSI */
+ uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
+ uint64_t uart : 2; /**< Two UART interrupts */
+ uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
+ uint64_t gpio : 16; /**< 16 GPIO interrupts */
+ uint64_t workq : 16; /**< 16 work queue interrupts */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t key_zero : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_58 : 2;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63 : 8;
uint64_t timer : 4; /**< General timer interrupts */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
@@ -2518,8 +5392,168 @@ union cvmx_ciu_intx_en4_0_w1c
uint64_t reserved_56_63 : 8;
#endif
} cn58xx;
+ struct cvmx_ciu_intx_en4_0_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
+ enable */
+ uint64_t mii : 1; /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt
+ enable */
+ uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
+ enable */
+ uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
+ uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn61xx;
struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
+ struct cvmx_ciu_intx_en4_0_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
+ enable */
+ uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
+ enable */
+ uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */
+ uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */
+ uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt */
+ uint64_t reserved_57_57 : 1;
+ uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */
+ uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
+ enable */
+ uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
+ uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_57 : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en4_0_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
+ enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
+ enable */
+ uint64_t reserved_49_49 : 1;
+ uint64_t gmx_drp : 1; /**< Write 1 to clear GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
+ uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 1;
+ uint64_t reserved_49_49 : 1;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1c_t;
@@ -2527,26 +5561,25 @@ typedef union cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1c_t;
* cvmx_ciu_int#_en4_0_w1s
*
* Notes:
- * Write-1-to-set version of the CIU_INTx_EN4_0 register
+ * Write-1-to-set version of the CIU_INTX_EN4_0 register, read back corresponding CIU_INTX_EN4_0 value.
*
*/
-union cvmx_ciu_intx_en4_0_w1s
-{
+union cvmx_ciu_intx_en4_0_w1s {
uint64_t u64;
- struct cvmx_ciu_intx_en4_0_w1s_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
enable */
uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
enable */
uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
interrupt enable */
- uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */
- uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */
- uint64_t reserved_57_58 : 2;
- uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */
- uint64_t timer : 4; /**< Write 1 to set General timer interrupts */
+ uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
enable */
@@ -2555,7 +5588,7 @@ union cvmx_ciu_intx_en4_0_w1s
uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
uint64_t reserved_44_44 : 1;
- uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */
+ uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
@@ -2577,7 +5610,8 @@ union cvmx_ciu_intx_en4_0_w1s
uint64_t key_zero : 1;
uint64_t timer : 4;
uint64_t usb : 1;
- uint64_t reserved_57_58 : 2;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
uint64_t twsi2 : 1;
uint64_t powiq : 1;
uint64_t ipdppthr : 1;
@@ -2585,9 +5619,8 @@ union cvmx_ciu_intx_en4_0_w1s
uint64_t bootdma : 1;
#endif
} s;
- struct cvmx_ciu_intx_en4_0_w1s_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -2635,10 +5668,55 @@ union cvmx_ciu_intx_en4_0_w1s
uint64_t bootdma : 1;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
- struct cvmx_ciu_intx_en4_0_w1s_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_0_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
+ uint64_t mii : 1; /**< MII Interface Interrupt */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
+ uint64_t powiq : 1; /**< POW IQ interrupt */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
+ uint64_t reserved_57_58 : 2;
+ uint64_t usb : 1; /**< USB Interrupt */
+ uint64_t timer : 4; /**< General timer interrupts */
+ uint64_t key_zero : 1; /**< Key Zeroization interrupt */
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
+ uint64_t gmx_drp : 2; /**< GMX packet drop */
+ uint64_t trace : 1; /**< L2C has the CMB trace buffer */
+ uint64_t rml : 1; /**< RML Interrupt */
+ uint64_t twsi : 1; /**< TWSI Interrupt */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< PCI MSI */
+ uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
+ uint64_t uart : 2; /**< Two UART interrupts */
+ uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
+ uint64_t gpio : 16; /**< 16 GPIO interrupts */
+ uint64_t workq : 16; /**< 16 work queue interrupts */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t key_zero : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_58 : 2;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn56xx;
+ struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63 : 8;
uint64_t timer : 4; /**< General timer interrupts */
uint64_t key_zero : 1; /**< Key Zeroization interrupt */
@@ -2672,8 +5750,168 @@ union cvmx_ciu_intx_en4_0_w1s
uint64_t reserved_56_63 : 8;
#endif
} cn58xx;
+ struct cvmx_ciu_intx_en4_0_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
+ enable */
+ uint64_t mii : 1; /**< Write 1 to set RGMII/MIX Interface 0 Interrupt
+ enable */
+ uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
+ enable */
+ uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
+ uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn61xx;
struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
+ struct cvmx_ciu_intx_en4_0_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
+ enable */
+ uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
+ enable */
+ uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */
+ uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */
+ uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt */
+ uint64_t reserved_57_57 : 1;
+ uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */
+ uint64_t timer : 4; /**< Write 1 to set General timer interrupts */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
+ enable */
+ uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
+ uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t reserved_57_57 : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en4_0_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
+ enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
+ interrupt enable */
+ uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
+ uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
+ uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
+ uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
+ uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
+ uint64_t reserved_51_51 : 1;
+ uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
+ enable */
+ uint64_t reserved_49_49 : 1;
+ uint64_t gmx_drp : 1; /**< Write 1 to set GMX packet drop interrupt enable */
+ uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
+ uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
+ uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
+ uint64_t reserved_44_44 : 1;
+ uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
+ uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
+ uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
+ uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
+ uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
+ uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t reserved_44_44 : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 1;
+ uint64_t reserved_49_49 : 1;
+ uint64_t ipd_drp : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_0_w1s_t;
@@ -2682,16 +5920,17 @@ typedef union cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_0_w1s_t;
*
* Notes:
* PPx/IP4 will be raised when...
- * PPx/IP4 = |([CIU_INT_SUM1, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0])
+ * PPx/IP4 = |([CIU_SUM1_PPx_IP4, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0])
*/
-union cvmx_ciu_intx_en4_1
-{
+union cvmx_ciu_intx_en4_1 {
uint64_t u64;
- struct cvmx_ciu_intx_en4_1_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< MIO RST interrupt enable */
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
uint64_t dfm : 1; /**< DFM interrupt enable */
uint64_t reserved_53_55 : 3;
uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
@@ -2701,7 +5940,10 @@ union cvmx_ciu_intx_en4_1
uint64_t pem0 : 1; /**< PEM0 interrupt enable */
uint64_t ptp : 1; /**< PTP interrupt enable */
uint64_t agl : 1; /**< AGL interrupt enable */
- uint64_t reserved_37_45 : 9;
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< GMX1 interrupt enable */
uint64_t agx0 : 1; /**< GMX0 interrupt enable */
uint64_t dpi : 1; /**< DPI interrupt enable */
uint64_t sli : 1; /**< SLI interrupt enable */
@@ -2719,7 +5961,7 @@ union cvmx_ciu_intx_en4_1
uint64_t fpa : 1; /**< FPA interrupt enable */
uint64_t iob : 1; /**< IOB interrupt enable */
uint64_t mio : 1; /**< MIO boot interrupt enable */
- uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */
+ uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
uint64_t usb1 : 1; /**< Second USB Interrupt */
uint64_t uart2 : 1; /**< Third UART interrupt */
@@ -2747,7 +5989,10 @@ union cvmx_ciu_intx_en4_1
uint64_t sli : 1;
uint64_t dpi : 1;
uint64_t agx0 : 1;
- uint64_t reserved_37_45 : 9;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
uint64_t agl : 1;
uint64_t ptp : 1;
uint64_t pem0 : 1;
@@ -2757,13 +6002,15 @@ union cvmx_ciu_intx_en4_1
uint64_t lmc0 : 1;
uint64_t reserved_53_55 : 3;
uint64_t dfm : 1;
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
uint64_t rst : 1;
#endif
} s;
- struct cvmx_ciu_intx_en4_1_cn50xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63 : 62;
uint64_t wdog : 2; /**< Watchdog summary interrupt enable vectory */
#else
@@ -2771,9 +6018,8 @@ union cvmx_ciu_intx_en4_1
uint64_t reserved_2_63 : 62;
#endif
} cn50xx;
- struct cvmx_ciu_intx_en4_1_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t nand : 1; /**< NAND Flash Controller */
uint64_t mii1 : 1; /**< Second MII Interrupt */
@@ -2791,9 +6037,8 @@ union cvmx_ciu_intx_en4_1
uint64_t reserved_20_63 : 44;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en4_1_cn52xxp1
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_cn52xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63 : 45;
uint64_t mii1 : 1; /**< Second MII Interrupt */
uint64_t usb1 : 1; /**< Second USB Interrupt */
@@ -2809,9 +6054,8 @@ union cvmx_ciu_intx_en4_1
uint64_t reserved_19_63 : 45;
#endif
} cn52xxp1;
- struct cvmx_ciu_intx_en4_1_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
#else
@@ -2820,9 +6064,8 @@ union cvmx_ciu_intx_en4_1
#endif
} cn56xx;
struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
- struct cvmx_ciu_intx_en4_1_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
#else
@@ -2831,9 +6074,79 @@ union cvmx_ciu_intx_en4_1
#endif
} cn58xx;
struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
- struct cvmx_ciu_intx_en4_1_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< PTP interrupt enable */
+ uint64_t agl : 1; /**< AGL interrupt enable */
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< DPI interrupt enable */
+ uint64_t sli : 1; /**< SLI interrupt enable */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< DFA interrupt enable */
+ uint64_t key : 1; /**< KEY interrupt enable */
+ uint64_t rad : 1; /**< RAD interrupt enable */
+ uint64_t tim : 1; /**< TIM interrupt enable */
+ uint64_t zip : 1; /**< ZIP interrupt enable */
+ uint64_t pko : 1; /**< PKO interrupt enable */
+ uint64_t pip : 1; /**< PIP interrupt enable */
+ uint64_t ipd : 1; /**< IPD interrupt enable */
+ uint64_t l2c : 1; /**< L2C interrupt enable */
+ uint64_t pow : 1; /**< POW err interrupt enable */
+ uint64_t fpa : 1; /**< FPA interrupt enable */
+ uint64_t iob : 1; /**< IOB interrupt enable */
+ uint64_t mio : 1; /**< MIO boot interrupt enable */
+ uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
+ uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt enable */
+ uint64_t reserved_4_17 : 14;
+ uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_17 : 14;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_intx_en4_1_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< MIO RST interrupt enable */
uint64_t reserved_57_62 : 6;
uint64_t dfm : 1; /**< DFM interrupt enable */
@@ -2904,6 +6217,150 @@ union cvmx_ciu_intx_en4_1
#endif
} cn63xx;
struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
+ struct cvmx_ciu_intx_en4_1_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< MIO RST interrupt enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
+ uint64_t dfm : 1; /**< DFM interrupt enable */
+ uint64_t reserved_53_55 : 3;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
+ uint64_t reserved_51_51 : 1;
+ uint64_t srio0 : 1; /**< SRIO0 interrupt enable */
+ uint64_t pem1 : 1; /**< PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< PTP interrupt enable */
+ uint64_t agl : 1; /**< AGL interrupt enable */
+ uint64_t reserved_38_45 : 8;
+ uint64_t agx1 : 1; /**< GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< DPI interrupt enable */
+ uint64_t sli : 1; /**< SLI interrupt enable */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< DFA interrupt enable */
+ uint64_t key : 1; /**< KEY interrupt enable */
+ uint64_t rad : 1; /**< RAD interrupt enable */
+ uint64_t tim : 1; /**< TIM interrupt enable */
+ uint64_t zip : 1; /**< ZIP interrupt enable */
+ uint64_t pko : 1; /**< PKO interrupt enable */
+ uint64_t pip : 1; /**< PIP interrupt enable */
+ uint64_t ipd : 1; /**< IPD interrupt enable */
+ uint64_t l2c : 1; /**< L2C interrupt enable */
+ uint64_t pow : 1; /**< POW err interrupt enable */
+ uint64_t fpa : 1; /**< FPA interrupt enable */
+ uint64_t iob : 1; /**< IOB interrupt enable */
+ uint64_t mio : 1; /**< MIO boot interrupt enable */
+ uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */
+ uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
+ uint64_t reserved_10_17 : 8;
+ uint64_t wdog : 10; /**< Watchdog summary interrupt enable vector */
+#else
+ uint64_t wdog : 10;
+ uint64_t reserved_10_17 : 8;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_45 : 8;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t srio0 : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t dfm : 1;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t rst : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en4_1_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< PTP interrupt enable */
+ uint64_t reserved_41_46 : 6;
+ uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
+ uint64_t reserved_37_39 : 3;
+ uint64_t agx0 : 1; /**< GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< DPI interrupt enable */
+ uint64_t sli : 1; /**< SLI interrupt enable */
+ uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
+ uint64_t reserved_32_32 : 1;
+ uint64_t key : 1; /**< KEY interrupt enable */
+ uint64_t rad : 1; /**< RAD interrupt enable */
+ uint64_t tim : 1; /**< TIM interrupt enable */
+ uint64_t reserved_28_28 : 1;
+ uint64_t pko : 1; /**< PKO interrupt enable */
+ uint64_t pip : 1; /**< PIP interrupt enable */
+ uint64_t ipd : 1; /**< IPD interrupt enable */
+ uint64_t l2c : 1; /**< L2C interrupt enable */
+ uint64_t pow : 1; /**< POW err interrupt enable */
+ uint64_t fpa : 1; /**< FPA interrupt enable */
+ uint64_t iob : 1; /**< IOB interrupt enable */
+ uint64_t mio : 1; /**< MIO boot interrupt enable */
+ uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
+ uint64_t reserved_4_18 : 15;
+ uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_18 : 15;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t reserved_28_28 : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t reserved_32_32 : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t reserved_37_39 : 3;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_46 : 6;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en4_1 cvmx_ciu_intx_en4_1_t;
@@ -2911,17 +6368,18 @@ typedef union cvmx_ciu_intx_en4_1 cvmx_ciu_intx_en4_1_t;
* cvmx_ciu_int#_en4_1_w1c
*
* Notes:
- * Write-1-to-clear version of the CIU_INTx_EN4_1 register
+ * Write-1-to-clear version of the CIU_INTX_EN4_1 register, read back corresponding CIU_INTX_EN4_1 value.
*
*/
-union cvmx_ciu_intx_en4_1_w1c
-{
+union cvmx_ciu_intx_en4_1_w1c {
uint64_t u64;
- struct cvmx_ciu_intx_en4_1_w1c_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1c_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
uint64_t reserved_53_55 : 3;
uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
@@ -2931,7 +6389,10 @@ union cvmx_ciu_intx_en4_1_w1c
uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
- uint64_t reserved_37_45 : 9;
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
@@ -2949,7 +6410,7 @@ union cvmx_ciu_intx_en4_1_w1c
uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
- uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt
+ uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
enable */
uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
Interrupt enable */
@@ -2979,7 +6440,10 @@ union cvmx_ciu_intx_en4_1_w1c
uint64_t sli : 1;
uint64_t dpi : 1;
uint64_t agx0 : 1;
- uint64_t reserved_37_45 : 9;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
uint64_t agl : 1;
uint64_t ptp : 1;
uint64_t pem0 : 1;
@@ -2989,13 +6453,15 @@ union cvmx_ciu_intx_en4_1_w1c
uint64_t lmc0 : 1;
uint64_t reserved_53_55 : 3;
uint64_t dfm : 1;
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
uint64_t rst : 1;
#endif
} s;
- struct cvmx_ciu_intx_en4_1_w1c_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t nand : 1; /**< NAND Flash Controller */
uint64_t mii1 : 1; /**< Second MII Interrupt */
@@ -3013,9 +6479,8 @@ union cvmx_ciu_intx_en4_1_w1c
uint64_t reserved_20_63 : 44;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en4_1_w1c_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
#else
@@ -3023,9 +6488,8 @@ union cvmx_ciu_intx_en4_1_w1c
uint64_t reserved_12_63 : 52;
#endif
} cn56xx;
- struct cvmx_ciu_intx_en4_1_w1c_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
#else
@@ -3033,9 +6497,81 @@ union cvmx_ciu_intx_en4_1_w1c
uint64_t reserved_16_63 : 48;
#endif
} cn58xx;
- struct cvmx_ciu_intx_en4_1_w1c_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1c_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
+ uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
+ uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
+ uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
+ uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
+ enable */
+ uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MIX Interface 1
+ Interrupt enable */
+ uint64_t reserved_4_17 : 14;
+ uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_17 : 14;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
uint64_t reserved_57_62 : 6;
uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
@@ -3108,6 +6644,153 @@ union cvmx_ciu_intx_en4_1_w1c
#endif
} cn63xx;
struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
+ struct cvmx_ciu_intx_en4_1_w1c_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
+ uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
+ uint64_t reserved_53_55 : 3;
+ uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
+ uint64_t reserved_51_51 : 1;
+ uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */
+ uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
+ uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
+ uint64_t reserved_38_45 : 8;
+ uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
+ uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
+ uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
+ uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt
+ enable */
+ uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
+ Interrupt enable */
+ uint64_t reserved_10_17 : 8;
+ uint64_t wdog : 10; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 10;
+ uint64_t reserved_10_17 : 8;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_45 : 8;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t srio0 : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t dfm : 1;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t rst : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en4_1_w1c_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
+ uint64_t reserved_41_46 : 6;
+ uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
+ uint64_t reserved_37_39 : 3;
+ uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
+ uint64_t reserved_32_32 : 1;
+ uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
+ uint64_t reserved_28_28 : 1;
+ uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
+ enable */
+ uint64_t reserved_4_18 : 15;
+ uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_18 : 15;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t reserved_28_28 : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t reserved_32_32 : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t reserved_37_39 : 3;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_46 : 6;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1c_t;
@@ -3115,17 +6798,18 @@ typedef union cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1c_t;
* cvmx_ciu_int#_en4_1_w1s
*
* Notes:
- * Write-1-to-set version of the CIU_INTx_EN4_1 register
+ * Write-1-to-set version of the CIU_INTX_EN4_1 register, read back corresponding CIU_INTX_EN4_1 value.
*
*/
-union cvmx_ciu_intx_en4_1_w1s
-{
+union cvmx_ciu_intx_en4_1_w1s {
uint64_t u64;
- struct cvmx_ciu_intx_en4_1_w1s_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1s_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
uint64_t reserved_53_55 : 3;
uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
@@ -3135,7 +6819,10 @@ union cvmx_ciu_intx_en4_1_w1s
uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
- uint64_t reserved_37_45 : 9;
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
@@ -3153,7 +6840,7 @@ union cvmx_ciu_intx_en4_1_w1s
uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
- uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt
+ uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
enable */
uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
enable */
@@ -3183,7 +6870,10 @@ union cvmx_ciu_intx_en4_1_w1s
uint64_t sli : 1;
uint64_t dpi : 1;
uint64_t agx0 : 1;
- uint64_t reserved_37_45 : 9;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
uint64_t agl : 1;
uint64_t ptp : 1;
uint64_t pem0 : 1;
@@ -3193,13 +6883,15 @@ union cvmx_ciu_intx_en4_1_w1s
uint64_t lmc0 : 1;
uint64_t reserved_53_55 : 3;
uint64_t dfm : 1;
- uint64_t reserved_57_62 : 6;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
uint64_t rst : 1;
#endif
} s;
- struct cvmx_ciu_intx_en4_1_w1s_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63 : 44;
uint64_t nand : 1; /**< NAND Flash Controller */
uint64_t mii1 : 1; /**< Second MII Interrupt */
@@ -3217,9 +6909,8 @@ union cvmx_ciu_intx_en4_1_w1s
uint64_t reserved_20_63 : 44;
#endif
} cn52xx;
- struct cvmx_ciu_intx_en4_1_w1s_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
#else
@@ -3227,9 +6918,8 @@ union cvmx_ciu_intx_en4_1_w1s
uint64_t reserved_12_63 : 52;
#endif
} cn56xx;
- struct cvmx_ciu_intx_en4_1_w1s_cn58xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
#else
@@ -3237,9 +6927,81 @@ union cvmx_ciu_intx_en4_1_w1s
uint64_t reserved_16_63 : 48;
#endif
} cn58xx;
- struct cvmx_ciu_intx_en4_1_w1s_cn63xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_en4_1_w1s_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
+ uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
+ uint64_t reserved_41_45 : 5;
+ uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
+ uint64_t reserved_38_39 : 2;
+ uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
+ uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
+ uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
+ uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
+ enable */
+ uint64_t mii1 : 1; /**< Write 1 to set RGMII/MIX Interface 1 Interrupt
+ enable */
+ uint64_t reserved_4_17 : 14;
+ uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_17 : 14;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_39 : 2;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_45 : 5;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cn61xx;
+ struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
uint64_t reserved_57_62 : 6;
uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
@@ -3312,18 +7074,163 @@ union cvmx_ciu_intx_en4_1_w1s
#endif
} cn63xx;
struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
+ struct cvmx_ciu_intx_en4_1_w1s_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
+ uint64_t reserved_62_62 : 1;
+ uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */
+ uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */
+ uint64_t reserved_57_59 : 3;
+ uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
+ uint64_t reserved_53_55 : 3;
+ uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
+ uint64_t reserved_51_51 : 1;
+ uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */
+ uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
+ uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
+ uint64_t reserved_38_45 : 8;
+ uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
+ uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
+ uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
+ uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
+ uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
+ uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt
+ enable */
+ uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
+ enable */
+ uint64_t reserved_10_17 : 8;
+ uint64_t wdog : 10; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 10;
+ uint64_t reserved_10_17 : 8;
+ uint64_t mii1 : 1;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t zip : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t dfa : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t agx1 : 1;
+ uint64_t reserved_38_45 : 8;
+ uint64_t agl : 1;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t srio0 : 1;
+ uint64_t reserved_51_51 : 1;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_55 : 3;
+ uint64_t dfm : 1;
+ uint64_t reserved_57_59 : 3;
+ uint64_t srio2 : 1;
+ uint64_t srio3 : 1;
+ uint64_t reserved_62_62 : 1;
+ uint64_t rst : 1;
+#endif
+ } cn66xx;
+ struct cvmx_ciu_intx_en4_1_w1s_cnf71xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
+ uint64_t reserved_53_62 : 10;
+ uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
+ uint64_t reserved_50_51 : 2;
+ uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
+ uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
+ uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
+ uint64_t reserved_41_46 : 6;
+ uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
+ uint64_t reserved_37_39 : 3;
+ uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
+ uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
+ uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
+ uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
+ uint64_t reserved_32_32 : 1;
+ uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
+ uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
+ uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
+ uint64_t reserved_28_28 : 1;
+ uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
+ uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
+ uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
+ uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
+ uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
+ uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
+ uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
+ uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
+ uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
+ enable */
+ uint64_t reserved_4_18 : 15;
+ uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */
+#else
+ uint64_t wdog : 4;
+ uint64_t reserved_4_18 : 15;
+ uint64_t nand : 1;
+ uint64_t mio : 1;
+ uint64_t iob : 1;
+ uint64_t fpa : 1;
+ uint64_t pow : 1;
+ uint64_t l2c : 1;
+ uint64_t ipd : 1;
+ uint64_t pip : 1;
+ uint64_t pko : 1;
+ uint64_t reserved_28_28 : 1;
+ uint64_t tim : 1;
+ uint64_t rad : 1;
+ uint64_t key : 1;
+ uint64_t reserved_32_32 : 1;
+ uint64_t usb : 1;
+ uint64_t sli : 1;
+ uint64_t dpi : 1;
+ uint64_t agx0 : 1;
+ uint64_t reserved_37_39 : 3;
+ uint64_t dpi_dma : 1;
+ uint64_t reserved_41_46 : 6;
+ uint64_t ptp : 1;
+ uint64_t pem0 : 1;
+ uint64_t pem1 : 1;
+ uint64_t reserved_50_51 : 2;
+ uint64_t lmc0 : 1;
+ uint64_t reserved_53_62 : 10;
+ uint64_t rst : 1;
+#endif
+ } cnf71xx;
};
typedef union cvmx_ciu_intx_en4_1_w1s cvmx_ciu_intx_en4_1_w1s_t;
/**
* cvmx_ciu_int#_sum0
*/
-union cvmx_ciu_intx_sum0
-{
+union cvmx_ciu_intx_sum0 {
uint64_t u64;
- struct cvmx_ciu_intx_sum0_s
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_sum0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
@@ -3334,19 +7241,26 @@ union cvmx_ciu_intx_sum0
See POW_IQ_INT */
uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
See MIO_TWS1_INT */
- uint64_t mpi : 1; /**< MPI/SPI interrupt */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction
+ finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
uint64_t pcm : 1; /**< PCM/TDM interrupt */
uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
- uint64_t timer : 4; /**< General timer interrupts
- Set any time the corresponding CIU timer expires */
- uint64_t key_zero : 1; /**< Key Zeroization interrupt
- KEY_ZERO will be set when the external ZERO_KEYS
- pin is sampled high. KEY_ZERO is cleared by SW */
+ uint64_t timer : 4; /**< General timer 0-3 interrupts.
+ When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+ common for all PP/IRQs, writing '1' to any PP/IRQ
+ will clear all TIMERx(x=0..9) interrupts.
+ When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+ are set at the same time, but clearing are based on
+ per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+ The combination of this field and the
+ CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+ interrupts. */
+ uint64_t reserved_51_51 : 1;
uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
Set any time PIP/IPD drops a packet */
- uint64_t gmx_drp : 2; /**< GMX packet drop interrupt
- Set any time corresponding GMX drops a packet */
+ uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt
+ Set any time corresponding GMX0/1 drops a packet */
uint64_t trace : 1; /**< Trace buffer interrupt
See TRA_INT_STATUS */
uint64_t rml : 1; /**< RML Interrupt
@@ -3356,30 +7270,37 @@ union cvmx_ciu_intx_sum0
See MIO_TWS0_INT */
uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
This read-only bit reads as a one whenever any
- CIU_INT_SUM1 bit is set and corresponding
- enable bit in CIU_INTx_EN is set, where x
- is the same as x in this CIU_INTx_SUM0.
- PPs use CIU_INTx_SUM0 where x=0-11
- PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
- Even INTx registers report WDOG to IP2
- Odd INTx registers report WDOG to IP3
- Note that WDOG_SUM only summarizes the SUM/EN1
+ CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
+ and corresponding enable bit in CIU_INTx_EN is set
+ PPs use CIU_INTx_SUM0 where x=0-7
+ PCIe uses the CIU_INTx_SUM0 where x=32-33.
+ Note that WDOG_SUM only summarizes the SUM1/EN1
result and does not have a corresponding enable
bit, so does not directly contribute to
interrupts. */
- uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
+ uint64_t pci_msi : 4; /**< PCIe MSI
See SLI_MSI_RCVn for bit <40+n> */
uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
Refer to "Receiving Emulated INTA/INTB/
- INTC/INTD" in the SLI chapter of the spec */
+ INTC/INTD" in the SLI chapter of the spec
+ PCI_INT<3> = INTD
+ PCI_INT<2> = INTC
+ PCI_INT<1> = INTB
+ PCI_INT<0> = INTA */
uint64_t uart : 2; /**< Two UART interrupts
See MIO_UARTn_IIR[IID] for bit <34+n> */
uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
[33] is the or of <31:16>
[32] is the or of <15:0>
- Two PCIe/sRIO internal interrupts for entries 32-33
+ Two PCIe internal interrupts for entries 32-33
which equal CIU_PCI_INTA[INT] */
- uint64_t gpio : 16; /**< 16 GPIO interrupts */
+ uint64_t gpio : 16; /**< 16 GPIO interrupts
+ When GPIO_MULTI_CAST[EN] == 1
+ Write 1 to clear either the per PP or common GPIO
+ edge-triggered interrupts,depending on mode.
+ See GPIO_MULTI_CAST for all details.
+ When GPIO_MULTI_CAST[EN] == 0
+ Read Only, retain the same behavior as o63. */
uint64_t workq : 16; /**< 16 work queue interrupts
See POW_WQ_INT[WQ_INT]
1 bit/group. A copy of the R/W1C bit in the POW. */
@@ -3396,7 +7317,7 @@ union cvmx_ciu_intx_sum0
uint64_t trace : 1;
uint64_t gmx_drp : 2;
uint64_t ipd_drp : 1;
- uint64_t key_zero : 1;
+ uint64_t reserved_51_51 : 1;
uint64_t timer : 4;
uint64_t usb : 1;
uint64_t pcm : 1;
@@ -3408,9 +7329,8 @@ union cvmx_ciu_intx_sum0
uint64_t bootdma : 1;
#endif
} s;
- struct cvmx_ciu_intx_sum0_cn30xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_sum0_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63 : 5;
uint64_t mpi : 1; /**< MPI/SPI interrupt */
uint64_t pcm : 1; /**< PCM/TDM interrupt */
@@ -3465,9 +7385,8 @@ union cvmx_ciu_intx_sum0
uint64_t reserved_59_63 : 5;
#endif
} cn30xx;
- struct cvmx_ciu_intx_sum0_cn31xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_sum0_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63 : 5;
uint64_t mpi : 1; /**< MPI/SPI interrupt */
uint64_t pcm : 1; /**< PCM/TDM interrupt */
@@ -3522,9 +7441,8 @@ union cvmx_ciu_intx_sum0
uint64_t reserved_59_63 : 5;
#endif
} cn31xx;
- struct cvmx_ciu_intx_sum0_cn38xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_sum0_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63 : 8;
uint64_t timer : 4; /**< General timer interrupts */
uint64_t key_zero : 1; /**< Key Zeroization interrupt
@@ -3575,9 +7493,8 @@ union cvmx_ciu_intx_sum0
} cn38xx;
struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
- struct cvmx_ciu_intx_sum0_cn52xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_sum0_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -3647,9 +7564,8 @@ union cvmx_ciu_intx_sum0
#endif
} cn52xx;
struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
- struct cvmx_ciu_intx_sum0_cn56xx
- {
-#if __BYTE_ORDER == __BIG_ENDIAN
+ struct cvmx_ciu_intx_sum0_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
uint64_t mii : 1; /**< MII Interface Interrupt */
uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
@@ -3713,20 +7629,341 @@ union cvmx_ciu_intx_sum0
struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
+ struct cvmx_ciu_intx_sum0_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
+ See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+ uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt
+ See MIX0_ISR */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
+ See IPD_PORT_QOS_INT* */
+ uint64_t powiq : 1; /**< POW IQ interrupt
+ See POW_IQ_INT */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
+ See MIO_TWS1_INT */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction
+ finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
+ uint64_t pcm : 1; /**< PCM/TDM interrupt */
+ uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
+ See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+ uint64_t timer : 4; /**< General timer 0-3 interrupts.
+ When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
+ common for all PP/IRQs, writing '1' to any PP/IRQ
+ will clear all TIMERx(x=0..9) interrupts.
+ When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+ are set at the same time, but clearing are based on
+ per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+ The combination of this field and the
+ CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+ interrupts. */
+ uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
+ This read-only bit reads as a one whenever any
+ CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
+ and corresponding enable bit in CIU_EN2_PPX_IPx
+ (CIU_EN2_IOX_INT) is set.
+ Note that SUM2 only summarizes the SUM2/EN2
+ result and does not have a corresponding enable
+ bit, so does not directly contribute to
+ interrupts. */
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
+ Set any time PIP/IPD drops a packet */
+ uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt
+ Set any time corresponding GMX0/1 drops a packet */
+ uint64_t trace : 1; /**< Trace buffer interrupt
+ See TRA_INT_STATUS */
+ uint64_t rml : 1; /**< RML Interrupt
+ This interrupt will assert if any bit within
+ CIU_BLOCK_INT is asserted. */
+ uint64_t twsi : 1; /**< TWSI Interrupt
+ See MIO_TWS0_INT */
+ uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
+ This read-only bit reads as a one whenever any
+ CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
+ and corresponding enable bit in CIU_INTx_EN is set
+ PPs use CIU_INTx_SUM0 where x=0-7
+ PCIe uses the CIU_INTx_SUM0 where x=32-33.
+ Note that WDOG_SUM only summarizes the SUM1/EN1
+ result and does not have a corresponding enable
+ bit, so does not directly contribute to
+ interrupts. */
+ uint64_t pci_msi : 4; /**< PCIe MSI
+ See SLI_MSI_RCVn for bit <40+n> */
+ uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
+ Refer to "Receiving Emulated INTA/INTB/
+ INTC/INTD" in the SLI chapter of the spec
+ PCI_INT<3> = INTD
+ PCI_INT<2> = INTC
+ PCI_INT<1> = INTB
+ PCI_INT<0> = INTA */
+ uint64_t uart : 2; /**< Two UART interrupts
+ See MIO_UARTn_IIR[IID] for bit <34+n> */
+ uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
+ [33] is the or of <31:16>
+ [32] is the or of <15:0>
+ Two PCIe internal interrupts for entries 32-33
+ which equal CIU_PCI_INTA[INT] */
+ uint64_t gpio : 16; /**< 16 GPIO interrupts
+ When GPIO_MULTI_CAST[EN] == 1
+ Write 1 to clear either the per PP or common GPIO
+ edge-triggered interrupts,depending on mode.
+ See GPIO_MULTI_CAST for all details.
+ When GPIO_MULTI_CAST[EN] == 0
+ Read Only, retain the same behavior as o63. */
+ uint64_t workq : 16; /**< 16 work queue interrupts
+ See POW_WQ_INT[WQ_INT]
+ 1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t wdog_sum : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;
+ uint64_t ipd_drp : 1;
+ uint64_t sum2 : 1;
+ uint64_t timer : 4;
+ uint64_t usb : 1;
+ uint64_t pcm : 1;
+ uint64_t mpi : 1;
+ uint64_t twsi2 : 1;
+ uint64_t powiq : 1;
+ uint64_t ipdppthr : 1;
+ uint64_t mii : 1;
+ uint64_t bootdma : 1;
+#endif
+ } cn61xx;
struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
+ struct cvmx_ciu_intx_sum0_cn66xx {
+#ifdef __BIG_ENDIAN_BITFIELD
+ uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
+ See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
+ uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
+ See MIX0_ISR */
+ uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
+ See IPD_PORT_QOS_INT* */
+ uint64_t powiq : 1; /**< POW IQ interrupt
+ See POW_IQ_INT */
+ uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
+ See MIO_TWS1_INT */
+ uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction
+ finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
+ uint64_t reserved_57_57 : 1;
+ uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
+ See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
+ uint64_t timer : 4; /**< General timer 0-3 interrupts.
+ Prior to pass 1.2 or
+ when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is
+ common for all PP/IRQs, writing '1' to any PP/IRQ
+ will clear all TIMERx(x=0..9) interrupts.
+ When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
+ are set at the same time, but clearing is per
+ cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
+ The combination of this field and the
+ CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
+ interrupts. */
+ uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
+ In pass 1.2 and subsequent passes,
+ this read-only bit reads as a one whenever any
+ CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
+ and corresponding enable bit in CIU_EN2_PPX_IPx
+ (CIU_EN2_IOX_INT) is set.
+ Note that SUM2 only summarizes the SUM2/EN2
+ result and does not have a corresponding enable
+ bit, so does not directly contribute to
+ interrupts.
+ Prior to pass 1.2, SUM2 did not exist and this
+ bit reads as zero. */
+ uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
+ Set any time PIP/IPD drops a packet */
+ uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt
+ Set any time corresponding GMX0/1 drops a packet */
+ uint64_t trace : 1; /**< Trace buffer interrupt
+ See TRA_INT_STATUS */
+ uint64_t rml : 1; /**< RML Interrupt
+ This interrupt will assert if any bit within
+ CIU_BLOCK_INT is asserted. */
+ uint64_t twsi : 1; /**< TWSI Interrupt
+ See MIO_TWS0_INT */
+ uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
+ This read-only bit reads as a one whenever any
+ CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
+ and corresponding enable bit in CIU_INTx_EN is set
+ PPs use CIU_INTx_SUM0 where x=0-19
+ PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
+ Note that WDOG_SUM only summarizes the SUM1/EN1
+ result and does not have a corresponding enable
+ bit, so does not directly contribute to
+ interrupts. */
+ uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
+ See SLI_MSI_RCVn for bit <40+n> */
+ uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
+ Refer to "Receiving Emulated INTA/INTB/
+ INTC/INTD" in the SLI chapter of the spec
+ PCI_INT<3> = INTD
+ PCI_INT<2> = INTC
+ PCI_INT<1> = INTB
+ PCI_INT<0> = INTA */
+ uint64_t uart : 2; /**< Two UART interrupts
+ See MIO_UARTn_IIR[IID] for bit <34+n> */
+ uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
+ [33] is the or of <31:16>
+ [32] is the or of <15:0>
+ Two PCIe/sRIO internal interrupts for entries 32-33
+ which equal CIU_PCI_INTA[INT] */
+ uint64_t gpio : 16; /**< 16 GPIO interrupts */
+ uint64_t workq : 16; /**< 16 work queue interrupts
+ See POW_WQ_INT[WQ_INT]
+ 1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+ uint64_t workq : 16;
+ uint64_t gpio : 16;
+ uint64_t mbox : 2;
+ uint64_t uart : 2;
+ uint64_t pci_int : 4;
+ uint64_t pci_msi : 4;
+ uint64_t wdog_sum : 1;
+ uint64_t twsi : 1;
+ uint64_t rml : 1;
+ uint64_t trace : 1;
+ uint64_t gmx_drp : 2;