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authorDimitry Andric <dim@FreeBSD.org>2015-07-05 14:23:59 +0000
committerDimitry Andric <dim@FreeBSD.org>2015-07-05 14:23:59 +0000
commitc192b3dcffd5e672a2b2e1730e2440febb4fb192 (patch)
treeac719b5984165053bf83d71142e4d96b609b9784 /lib/Basic
parent2e645aa5697838f16ec570eb07c2bee7e13d0e0b (diff)
downloadsrc-c192b3dcffd5e672a2b2e1730e2440febb4fb192.tar.gz
src-c192b3dcffd5e672a2b2e1730e2440febb4fb192.zip
Vendor import of clang trunk r241361:vendor/clang/clang-trunk-r241361
Notes
Notes: svn path=/vendor/clang/dist/; revision=285165 svn path=/vendor/clang/clang-trunk-r241361/; revision=285166; tag=vendor/clang/clang-trunk-r241361
Diffstat (limited to 'lib/Basic')
-rw-r--r--lib/Basic/Diagnostic.cpp21
-rw-r--r--lib/Basic/IdentifierTable.cpp11
-rw-r--r--lib/Basic/Module.cpp2
-rw-r--r--lib/Basic/OpenMPKinds.cpp16
-rw-r--r--lib/Basic/TargetInfo.cpp1
-rw-r--r--lib/Basic/Targets.cpp265
-rw-r--r--lib/Basic/VirtualFileSystem.cpp14
7 files changed, 183 insertions, 147 deletions
diff --git a/lib/Basic/Diagnostic.cpp b/lib/Basic/Diagnostic.cpp
index 7f5a15dab6b2..f89caf7b248f 100644
--- a/lib/Basic/Diagnostic.cpp
+++ b/lib/Basic/Diagnostic.cpp
@@ -24,6 +24,27 @@
using namespace clang;
+const DiagnosticBuilder &clang::operator<<(const DiagnosticBuilder &DB,
+ DiagNullabilityKind nullability) {
+ StringRef string;
+ switch (nullability.first) {
+ case NullabilityKind::NonNull:
+ string = nullability.second ? "'nonnull'" : "'_Nonnull'";
+ break;
+
+ case NullabilityKind::Nullable:
+ string = nullability.second ? "'nullable'" : "'_Nullable'";
+ break;
+
+ case NullabilityKind::Unspecified:
+ string = nullability.second ? "'null_unspecified'" : "'_Null_unspecified'";
+ break;
+ }
+
+ DB.AddString(string);
+ return DB;
+}
+
static void DummyArgToStringFn(DiagnosticsEngine::ArgumentKind AK, intptr_t QT,
StringRef Modifier, StringRef Argument,
ArrayRef<DiagnosticsEngine::ArgumentValue> PrevArgs,
diff --git a/lib/Basic/IdentifierTable.cpp b/lib/Basic/IdentifierTable.cpp
index b29500810003..36fba994f1e7 100644
--- a/lib/Basic/IdentifierTable.cpp
+++ b/lib/Basic/IdentifierTable.cpp
@@ -71,8 +71,6 @@ IdentifierIterator *IdentifierInfoLookup::getIdentifiers() {
return new EmptyLookupIterator();
}
-ExternalIdentifierLookup::~ExternalIdentifierLookup() {}
-
IdentifierTable::IdentifierTable(const LangOptions &LangOpts,
IdentifierInfoLookup* externalLookup)
: HashTable(8192), // Start with space for 8K identifiers.
@@ -647,16 +645,17 @@ const char *clang::getOperatorSpelling(OverloadedOperatorKind Operator) {
llvm_unreachable("Invalid OverloadedOperatorKind!");
}
-StringRef clang::getNullabilitySpelling(NullabilityKind kind) {
+StringRef clang::getNullabilitySpelling(NullabilityKind kind,
+ bool isContextSensitive) {
switch (kind) {
case NullabilityKind::NonNull:
- return "__nonnull";
+ return isContextSensitive ? "nonnull" : "_Nonnull";
case NullabilityKind::Nullable:
- return "__nullable";
+ return isContextSensitive ? "nullable" : "_Nullable";
case NullabilityKind::Unspecified:
- return "__null_unspecified";
+ return isContextSensitive ? "null_unspecified" : "_Null_unspecified";
}
llvm_unreachable("Unknown nullability kind.");
}
diff --git a/lib/Basic/Module.cpp b/lib/Basic/Module.cpp
index 7308665bd2d8..1a48a6c6a8d1 100644
--- a/lib/Basic/Module.cpp
+++ b/lib/Basic/Module.cpp
@@ -27,7 +27,7 @@ using namespace clang;
Module::Module(StringRef Name, SourceLocation DefinitionLoc, Module *Parent,
bool IsFramework, bool IsExplicit, unsigned VisibilityID)
: Name(Name), DefinitionLoc(DefinitionLoc), Parent(Parent), Directory(),
- Umbrella(), ASTFile(nullptr), VisibilityID(VisibilityID),
+ Umbrella(), Signature(0), ASTFile(nullptr), VisibilityID(VisibilityID),
IsMissingRequirement(false), IsAvailable(true), IsFromModuleFile(false),
IsFramework(IsFramework), IsExplicit(IsExplicit), IsSystem(false),
IsExternC(false), IsInferred(false), InferSubmodules(false),
diff --git a/lib/Basic/OpenMPKinds.cpp b/lib/Basic/OpenMPKinds.cpp
index b2798b7f0fd3..b7407f60e6d1 100644
--- a/lib/Basic/OpenMPKinds.cpp
+++ b/lib/Basic/OpenMPKinds.cpp
@@ -91,6 +91,11 @@ unsigned clang::getOpenMPSimpleClauseType(OpenMPClauseKind Kind,
#define OPENMP_SCHEDULE_KIND(Name) .Case(#Name, OMPC_SCHEDULE_##Name)
#include "clang/Basic/OpenMPKinds.def"
.Default(OMPC_SCHEDULE_unknown);
+ case OMPC_depend:
+ return llvm::StringSwitch<OpenMPDependClauseKind>(Str)
+#define OPENMP_DEPEND_KIND(Name) .Case(#Name, OMPC_DEPEND_##Name)
+#include "clang/Basic/OpenMPKinds.def"
+ .Default(OMPC_DEPEND_unknown);
case OMPC_unknown:
case OMPC_threadprivate:
case OMPC_if:
@@ -154,6 +159,15 @@ const char *clang::getOpenMPSimpleClauseTypeName(OpenMPClauseKind Kind,
return #Name;
#include "clang/Basic/OpenMPKinds.def"
}
+ case OMPC_depend:
+ switch (Type) {
+ case OMPC_DEPEND_unknown:
+ return "unknown";
+#define OPENMP_DEPEND_KIND(Name) \
+ case OMPC_DEPEND_##Name: \
+ return #Name;
+#include "clang/Basic/OpenMPKinds.def"
+ }
llvm_unreachable("Invalid OpenMP 'schedule' clause type");
case OMPC_unknown:
case OMPC_threadprivate:
@@ -333,6 +347,8 @@ bool clang::isAllowedClauseForDirective(OpenMPDirectiveKind DKind,
case OMPD_barrier:
case OMPD_taskwait:
case OMPD_taskgroup:
+ case OMPD_cancellation_point:
+ case OMPD_cancel:
case OMPD_ordered:
break;
}
diff --git a/lib/Basic/TargetInfo.cpp b/lib/Basic/TargetInfo.cpp
index 330258b025b5..856ad50d3782 100644
--- a/lib/Basic/TargetInfo.cpp
+++ b/lib/Basic/TargetInfo.cpp
@@ -50,6 +50,7 @@ TargetInfo::TargetInfo(const llvm::Triple &T) : TargetOpts(), Triple(T) {
LargeArrayAlign = 0;
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0;
MaxVectorAlign = 0;
+ SimdDefaultAlign = 0;
SizeType = UnsignedLong;
PtrDiffType = SignedLong;
IntMaxType = SignedLongLong;
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 076b04bf342c..8f2bca051b67 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -759,6 +759,7 @@ public:
HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
HasBPERMD(false), HasExtDiv(false) {
BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
+ SimdDefaultAlign = 128;
LongDoubleWidth = LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
}
@@ -2215,6 +2216,7 @@ public:
Names = AddlRegNames;
NumNames = llvm::array_lengthof(AddlRegNames);
}
+ bool validateCpuSupports(StringRef Name) const override;
bool validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &info) const override;
@@ -2249,7 +2251,9 @@ public:
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override;
StringRef getABI() const override {
- if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
+ if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
+ return "avx512";
+ else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
return "avx";
else if (getTriple().getArch() == llvm::Triple::x86 &&
MMX3DNowLevel == NoMMX3DNow)
@@ -2725,7 +2729,11 @@ void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
StringRef Name, bool Enabled) {
- Features[Name] = Enabled;
+ // This is a bit of a hack to deal with the sse4 target feature when used
+ // as part of the target attribute. We handle sse4 correctly everywhere
+ // else. See below for more information on how we handle the sse4 options.
+ if (Name != "sse4")
+ Features[Name] = Enabled;
if (Name == "mmx") {
setMMXLevel(Features, MMX, Enabled);
@@ -2776,6 +2784,15 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
} else if (Name == "sha") {
if (Enabled)
setSSELevel(Features, SSE2, Enabled);
+ } else if (Name == "sse4") {
+ // We can get here via the __target__ attribute since that's not controlled
+ // via the -msse4/-mno-sse4 command line alias. Handle this the same way
+ // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
+ // disabled.
+ if (Enabled)
+ setSSELevel(Features, SSE42, Enabled);
+ else
+ setSSELevel(Features, SSE41, Enabled);
}
}
@@ -2972,6 +2989,9 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
Features.erase(it);
else if (SSELevel > NoSSE)
MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
+
+ SimdDefaultAlign =
+ (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128;
return true;
}
@@ -3336,6 +3356,33 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Default(false);
}
+// We can't use a generic validation scheme for the features accepted here
+// versus subtarget features accepted in the target attribute because the
+// bitfield structure that's initialized in the runtime only supports the
+// below currently rather than the full range of subtarget features. (See
+// X86TargetInfo::hasFeature for a somewhat comprehensive list).
+bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
+ return llvm::StringSwitch<bool>(FeatureStr)
+ .Case("cmov", true)
+ .Case("mmx", true)
+ .Case("popcnt", true)
+ .Case("sse", true)
+ .Case("sse2", true)
+ .Case("sse3", true)
+ .Case("sse4.1", true)
+ .Case("sse4.2", true)
+ .Case("avx", true)
+ .Case("avx2", true)
+ .Case("sse4a", true)
+ .Case("fma4", true)
+ .Case("xop", true)
+ .Case("fma", true)
+ .Case("avx512f", true)
+ .Case("bmi", true)
+ .Case("bmi2", true)
+ .Default(false);
+}
+
bool
X86TargetInfo::validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &Info) const {
@@ -3949,8 +3996,14 @@ class ARMTargetInfo : public TargetInfo {
FP_Neon
} FPMath;
+ unsigned ArchISA;
+ unsigned ArchKind;
+ unsigned ArchProfile;
+ unsigned ArchVersion;
+
unsigned FPU : 5;
+ unsigned ShouldUseInlineAtomic : 1;
unsigned IsAAPCS : 1;
unsigned IsThumb : 1;
unsigned HWDiv : 2;
@@ -3972,37 +4025,6 @@ class ARMTargetInfo : public TargetInfo {
static const Builtin::Info BuiltinInfo[];
- static bool shouldUseInlineAtomic(const llvm::Triple &T) {
- StringRef ArchName = T.getArchName();
- if (T.getArch() == llvm::Triple::arm ||
- T.getArch() == llvm::Triple::armeb) {
- StringRef VersionStr;
- if (ArchName.startswith("armv"))
- VersionStr = ArchName.substr(4, 1);
- else if (ArchName.startswith("armebv"))
- VersionStr = ArchName.substr(6, 1);
- else
- return false;
- unsigned Version;
- if (VersionStr.getAsInteger(10, Version))
- return false;
- return Version >= 6;
- }
- assert(T.getArch() == llvm::Triple::thumb ||
- T.getArch() == llvm::Triple::thumbeb);
- StringRef VersionStr;
- if (ArchName.startswith("thumbv"))
- VersionStr = ArchName.substr(6, 1);
- else if (ArchName.startswith("thumbebv"))
- VersionStr = ArchName.substr(8, 1);
- else
- return false;
- unsigned Version;
- if (VersionStr.getAsInteger(10, Version))
- return false;
- return Version >= 7;
- }
-
void setABIAAPCS() {
IsAAPCS = true;
@@ -4101,6 +4123,27 @@ class ARMTargetInfo : public TargetInfo {
// FIXME: Override "preferred align" for double and long long.
}
+ void setArchInfo(StringRef ArchName) {
+ ArchISA = llvm::ARMTargetParser::parseArchISA(ArchName);
+ ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
+ ArchProfile = llvm::ARMTargetParser::parseArchProfile(ArchName);
+ ArchVersion = llvm::ARMTargetParser::parseArchVersion(ArchName);
+ }
+
+ void setAtomic() {
+ // Cortex M does not support 8 byte atomics, while general Thumb2 does.
+ if (ArchProfile == llvm::ARM::PK_M) {
+ MaxAtomicPromoteWidth = 32;
+ if (ShouldUseInlineAtomic)
+ MaxAtomicInlineWidth = 32;
+ }
+ else {
+ MaxAtomicPromoteWidth = 64;
+ if (ShouldUseInlineAtomic)
+ MaxAtomicInlineWidth = 64;
+ }
+ }
+
public:
ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
: TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
@@ -4116,12 +4159,27 @@ public:
break;
}
+ // if subArch is not specified Arc Info is based on the default CPU
+ if (Triple.getSubArch() == llvm::Triple::SubArchType::NoSubArch) {
+ unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(CPU);
+ setArchInfo(llvm::ARMTargetParser::getArchName(ArchKind));
+ ShouldUseInlineAtomic = false;
+ }
+ else {
+ setArchInfo(Triple.getArchName());
+ // FIXME: Should't this be updated also when calling setCPU() ?
+ // Doing so currently causes regressions
+ ShouldUseInlineAtomic = (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
+ (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
+ }
+
// {} in inline assembly are neon specifiers, not assembly variant
// specifiers.
NoAsmVariants = true;
- // FIXME: Should we just treat this as a feature?
- IsThumb = getTriple().getArchName().startswith("thumb");
+ // FIXME: Should't this be updated also when calling setCPU() ?
+ // Doing so currently causes regressions
+ IsThumb = (ArchISA == llvm::ARM::IK_THUMB);
// FIXME: This duplicates code from the driver that sets the -target-abi
// option - this code is used if -target-abi isn't passed and should
@@ -4166,10 +4224,7 @@ public:
// ARM targets default to using the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::GenericARM);
- // ARM has atomics up to 8 bytes
- MaxAtomicPromoteWidth = 64;
- if (shouldUseInlineAtomic(getTriple()))
- MaxAtomicInlineWidth = 64;
+ setAtomic();
// Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member
@@ -4177,7 +4232,9 @@ public:
// zero length bitfield.
UseZeroLengthBitfieldAlignment = true;
}
+
StringRef getABI() const override { return ABI; }
+
bool setABI(const std::string &Name) override {
ABI = Name;
@@ -4198,11 +4255,6 @@ public:
// FIXME: This should be based on Arch attributes, not CPU names.
void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
- StringRef ArchName = getTriple().getArchName();
- unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
- bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A ||
- ArchKind == llvm::ARM::AK_ARMV8_1A);
-
if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
Features["vfp2"] = true;
else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
@@ -4227,7 +4279,7 @@ public:
Features["hwdiv-arm"] = true;
Features["crc"] = true;
Features["crypto"] = true;
- } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) {
+ } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || ArchVersion == 8) {
Features["hwdiv"] = true;
Features["hwdiv-arm"] = true;
} else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
@@ -4244,6 +4296,9 @@ public:
SoftFloat = SoftFloatABI = false;
HWDiv = 0;
+ // This does not diagnose illegal cases like having both
+ // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
+ uint32_t HW_FP_remove = 0;
for (const auto &Feature : Features) {
if (Feature == "+soft-float") {
SoftFloat = true;
@@ -4251,19 +4306,19 @@ public:
SoftFloatABI = true;
} else if (Feature == "+vfp2") {
FPU |= VFP2FPU;
- HW_FP = HW_FP_SP | HW_FP_DP;
+ HW_FP |= HW_FP_SP | HW_FP_DP;
} else if (Feature == "+vfp3") {
FPU |= VFP3FPU;
- HW_FP = HW_FP_SP | HW_FP_DP;
+ HW_FP |= HW_FP_SP | HW_FP_DP;
} else if (Feature == "+vfp4") {
FPU |= VFP4FPU;
- HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
+ HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
} else if (Feature == "+fp-armv8") {
FPU |= FPARMV8;
- HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
+ HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
} else if (Feature == "+neon") {
FPU |= NeonFPU;
- HW_FP = HW_FP_SP | HW_FP_DP;
+ HW_FP |= HW_FP_SP | HW_FP_DP;
} else if (Feature == "+hwdiv") {
HWDiv |= HWDivThumb;
} else if (Feature == "+hwdiv-arm") {
@@ -4273,9 +4328,10 @@ public:
} else if (Feature == "+crypto") {
Crypto = 1;
} else if (Feature == "+fp-only-sp") {
- HW_FP &= ~HW_FP_DP;
+ HW_FP_remove |= HW_FP_DP | HW_FP_HP;
}
}
+ HW_FP &= ~HW_FP_remove;
if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
@@ -4306,26 +4362,14 @@ public:
.Case("hwdiv-arm", HWDiv & HWDivARM)
.Default(false);
}
- const char *getCPUDefineSuffix(StringRef Name) const {
- if(Name == "generic") {
- auto subarch = getTriple().getSubArch();
- switch (subarch) {
- case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
- return "8_1A";
- default:
- break;
- }
- }
-
- unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
- if (ArchKind == llvm::ARM::AK_INVALID)
- return "";
-
+ const char *getCPUAttr() const {
+ const char *CPUAttr;
// For most sub-arches, the build attribute CPU name is enough.
// For Cortex variants, it's slightly different.
switch(ArchKind) {
default:
- return llvm::ARMTargetParser::getCPUAttr(ArchKind);
+ CPUAttr = llvm::ARMTargetParser::getCPUAttr(ArchKind);
+ return CPUAttr ? CPUAttr : "" ;
case llvm::ARM::AK_ARMV6M:
case llvm::ARM::AK_ARMV6SM:
return "6M";
@@ -4345,23 +4389,8 @@ public:
return "8_1A";
}
}
- const char *getCPUProfile(StringRef Name) const {
- if(Name == "generic") {
- auto subarch = getTriple().getSubArch();
- switch (subarch) {
- case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
- return "A";
- default:
- break;
- }
- }
-
- unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name);
- if (CPUArch == llvm::ARM::AK_INVALID)
- return "";
-
- StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch);
- switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) {
+ const char *getCPUProfile() const {
+ switch(ArchProfile) {
case llvm::ARM::PK_A:
return "A";
case llvm::ARM::PK_R:
@@ -4373,35 +4402,26 @@ public:
}
}
bool setCPU(const std::string &Name) override {
- if (!getCPUDefineSuffix(Name))
+ unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
+ if (ArchKind == llvm::ARM::AK_INVALID)
return false;
-
- // Cortex M does not support 8 byte atomics, while general Thumb2 does.
- StringRef Profile = getCPUProfile(Name);
- if (Profile == "M" && MaxAtomicInlineWidth) {
- MaxAtomicPromoteWidth = 32;
- MaxAtomicInlineWidth = 32;
- }
-
+ setArchInfo(llvm::ARMTargetParser::getArchName(ArchKind));
+ setAtomic();
CPU = Name;
return true;
}
bool setFPMath(StringRef Name) override;
- bool supportsThumb(StringRef ArchName, StringRef CPUArch,
- unsigned CPUArchVer) const {
- return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
- (CPUArch.find('M') != StringRef::npos);
- }
- bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
- unsigned CPUArchVer) const {
- // We check both CPUArchVer and ArchName because when only triple is
- // specified, the default CPU is arm1136j-s.
- return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
- ArchName.endswith("v8.1a") ||
- ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
+ bool supportsThumb(StringRef CPUAttr) const {
+ return CPUAttr.count('T') || ArchVersion >= 6;
+ }
+ bool supportsThumb2(StringRef CPUAttr) const {
+ return CPUAttr.equals("6T2") || ArchVersion >= 7;
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
+ StringRef CPUAttr = getCPUAttr();
+ StringRef CPUProfile = getCPUProfile();
+
// Target identification.
Builder.defineMacro("__arm");
Builder.defineMacro("__arm__");
@@ -4409,19 +4429,12 @@ public:
// Target properties.
Builder.defineMacro("__REGISTER_PREFIX__", "");
- StringRef CPUArch = getCPUDefineSuffix(CPU);
- unsigned int CPUArchVer;
- if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
- llvm_unreachable("Invalid char for architecture version number");
- Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
+ Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
// ACLE 6.4.1 ARM/Thumb instruction set architecture
- StringRef CPUProfile = getCPUProfile(CPU);
- StringRef ArchName = getTriple().getArchName();
-
// __ARM_ARCH is defined as an integer value indicating the current ARM ISA
- Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
- if (CPUArch[0] >= '8') {
+ Builder.defineMacro("__ARM_ARCH", std::to_string(ArchVersion));
+ if (ArchVersion >= 8) {
Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
}
@@ -4435,9 +4448,9 @@ public:
// __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
// Thumb ISA (including v6-M). It is set to 2 if the core supports the
// Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
- if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
+ if (supportsThumb2(CPUAttr))
Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
- else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
+ else if (supportsThumb(CPUAttr))
Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
// __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
@@ -4462,7 +4475,7 @@ public:
// FIXME: It's more complicated than this and we don't really support
// interworking.
// Windows on ARM does not "support" interworking
- if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
+ if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
Builder.defineMacro("__THUMB_INTERWORK__");
if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
@@ -4485,7 +4498,7 @@ public:
if (IsThumb) {
Builder.defineMacro("__THUMBEL__");
Builder.defineMacro("__thumb__");
- if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
+ if (supportsThumb2(CPUAttr))
Builder.defineMacro("__thumb2__");
}
if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
@@ -4508,7 +4521,7 @@ public:
// the VFP define, hence the soft float and arch check. This is subtly
// different from gcc, we follow the intent which was that it should be set
// when Neon instructions are actually available.
- if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
+ if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
Builder.defineMacro("__ARM_NEON");
Builder.defineMacro("__ARM_NEON__");
}
@@ -4525,18 +4538,18 @@ public:
if (Crypto)
Builder.defineMacro("__ARM_FEATURE_CRYPTO");
- if (CPUArchVer >= 6 && CPUArch != "6M") {
+ if (ArchVersion >= 6 && CPUAttr != "6M") {
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
}
- bool is5EOrAbove = (CPUArchVer >= 6 ||
- (CPUArchVer == 5 &&
- CPUArch.find('E') != StringRef::npos));
- bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
- if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
+ bool is5EOrAbove = (ArchVersion >= 6 ||
+ (ArchVersion == 5 && CPUAttr.count('E')));
+ // FIXME: We are not getting all 32-bit ARM architectures
+ bool is32Bit = (!IsThumb || supportsThumb2(CPUAttr));
+ if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr == "7EM"))
Builder.defineMacro("__ARM_FEATURE_DSP");
}
void getTargetBuiltins(const Builtin::Info *&Records,
diff --git a/lib/Basic/VirtualFileSystem.cpp b/lib/Basic/VirtualFileSystem.cpp
index 8a882e13f7a5..a36102cf0f5a 100644
--- a/lib/Basic/VirtualFileSystem.cpp
+++ b/lib/Basic/VirtualFileSystem.cpp
@@ -324,20 +324,6 @@ directory_iterator OverlayFileSystem::dir_begin(const Twine &Dir,
// VFSFromYAML implementation
//===-----------------------------------------------------------------------===/
-// Allow DenseMap<StringRef, ...>. This is useful below because we know all the
-// strings are literals and will outlive the map, and there is no reason to
-// store them.
-namespace llvm {
- template<>
- struct DenseMapInfo<StringRef> {
- // This assumes that "" will never be a valid key.
- static inline StringRef getEmptyKey() { return StringRef(""); }
- static inline StringRef getTombstoneKey() { return StringRef(); }
- static unsigned getHashValue(StringRef Val) { return HashString(Val); }
- static bool isEqual(StringRef LHS, StringRef RHS) { return LHS == RHS; }
- };
-}
-
namespace {
enum EntryKind {