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authorDimitry Andric <dim@FreeBSD.org>2019-08-20 20:50:49 +0000
committerDimitry Andric <dim@FreeBSD.org>2019-08-20 20:50:49 +0000
commit2298981669bf3bd63335a4be179bc0f96823a8f4 (patch)
tree1cbe2eb27f030d2d70b80ee5ca3c86bee7326a9f /lib/Basic/Targets
parent9a83721404652cea39e9f02ae3e3b5c964602a5c (diff)
downloadsrc-2298981669bf3bd63335a4be179bc0f96823a8f4.tar.gz
src-2298981669bf3bd63335a4be179bc0f96823a8f4.zip
Vendor import of stripped clang trunk r366426 (just before thevendor/clang/clang-trunk-r366426
Notes
Notes: svn path=/vendor/clang/dist/; revision=351280 svn path=/vendor/clang/clang-trunk-r366426/; revision=351281; tag=vendor/clang/clang-trunk-r366426
Diffstat (limited to 'lib/Basic/Targets')
-rw-r--r--lib/Basic/Targets/AArch64.cpp108
-rw-r--r--lib/Basic/Targets/AArch64.h31
-rw-r--r--lib/Basic/Targets/AMDGPU.cpp56
-rw-r--r--lib/Basic/Targets/AMDGPU.h10
-rw-r--r--lib/Basic/Targets/ARC.cpp9
-rw-r--r--lib/Basic/Targets/ARC.h7
-rw-r--r--lib/Basic/Targets/ARM.cpp157
-rw-r--r--lib/Basic/Targets/ARM.h21
-rw-r--r--lib/Basic/Targets/AVR.cpp7
-rw-r--r--lib/Basic/Targets/AVR.h7
-rw-r--r--lib/Basic/Targets/BPF.cpp11
-rw-r--r--lib/Basic/Targets/BPF.h7
-rw-r--r--lib/Basic/Targets/Hexagon.cpp7
-rw-r--r--lib/Basic/Targets/Hexagon.h7
-rw-r--r--lib/Basic/Targets/Lanai.cpp7
-rw-r--r--lib/Basic/Targets/Lanai.h7
-rw-r--r--lib/Basic/Targets/Le64.cpp7
-rw-r--r--lib/Basic/Targets/Le64.h7
-rw-r--r--lib/Basic/Targets/MSP430.cpp7
-rw-r--r--lib/Basic/Targets/MSP430.h13
-rw-r--r--lib/Basic/Targets/Mips.cpp15
-rw-r--r--lib/Basic/Targets/Mips.h9
-rw-r--r--lib/Basic/Targets/NVPTX.cpp15
-rw-r--r--lib/Basic/Targets/NVPTX.h31
-rw-r--r--lib/Basic/Targets/OSTargets.cpp86
-rw-r--r--lib/Basic/Targets/OSTargets.h194
-rw-r--r--lib/Basic/Targets/PNaCl.cpp7
-rw-r--r--lib/Basic/Targets/PNaCl.h7
-rw-r--r--lib/Basic/Targets/PPC.cpp36
-rw-r--r--lib/Basic/Targets/PPC.h87
-rw-r--r--lib/Basic/Targets/RISCV.cpp29
-rw-r--r--lib/Basic/Targets/RISCV.h21
-rw-r--r--lib/Basic/Targets/SPIR.cpp7
-rw-r--r--lib/Basic/Targets/SPIR.h8
-rw-r--r--lib/Basic/Targets/Sparc.cpp7
-rw-r--r--lib/Basic/Targets/Sparc.h9
-rw-r--r--lib/Basic/Targets/SystemZ.cpp13
-rw-r--r--lib/Basic/Targets/SystemZ.h11
-rw-r--r--lib/Basic/Targets/TCE.cpp7
-rw-r--r--lib/Basic/Targets/TCE.h7
-rw-r--r--lib/Basic/Targets/WebAssembly.cpp80
-rw-r--r--lib/Basic/Targets/WebAssembly.h21
-rw-r--r--lib/Basic/Targets/X86.cpp229
-rw-r--r--lib/Basic/Targets/X86.h33
-rw-r--r--lib/Basic/Targets/XCore.cpp7
-rw-r--r--lib/Basic/Targets/XCore.h7
46 files changed, 1032 insertions, 444 deletions
diff --git a/lib/Basic/Targets/AArch64.cpp b/lib/Basic/Targets/AArch64.cpp
index 62919a02dcb9..74ac69ab8946 100644
--- a/lib/Basic/Targets/AArch64.cpp
+++ b/lib/Basic/Targets/AArch64.cpp
@@ -1,9 +1,8 @@
//===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -50,6 +49,7 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
// All AArch64 implementations support ARMv8 FP, which makes half a legal type.
HasLegalHalfType = true;
+ HasFloat16 = true;
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
MaxVectorAlign = 128;
@@ -118,6 +118,28 @@ void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
getTargetDefinesARMV81A(Opts, Builder);
}
+void AArch64TargetInfo::getTargetDefinesARMV83A(const LangOptions &Opts,
+ MacroBuilder &Builder) const {
+ Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
+ // Also include the Armv8.2 defines
+ getTargetDefinesARMV82A(Opts, Builder);
+}
+
+void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
+ MacroBuilder &Builder) const {
+ // Also include the Armv8.3 defines
+ // FIXME: Armv8.4 makes some extensions mandatory. Handle them here.
+ getTargetDefinesARMV83A(Opts, Builder);
+}
+
+void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
+ MacroBuilder &Builder) const {
+ // Also include the Armv8.4 defines
+ // FIXME: Armv8.5 makes some extensions mandatory. Handle them here.
+ getTargetDefinesARMV84A(Opts, Builder);
+}
+
+
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
@@ -177,13 +199,13 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
if (FPU & SveMode)
Builder.defineMacro("__ARM_FEATURE_SVE", "1");
- if (CRC)
+ if (HasCRC)
Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
- if (Crypto)
+ if (HasCrypto)
Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
- if (Unaligned)
+ if (HasUnaligned)
Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
if ((FPU & NeonMode) && HasFullFP16)
@@ -194,6 +216,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasDotProd)
Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
+ if (HasMTE)
+ Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
+
if ((FPU & NeonMode) && HasFP16FML)
Builder.defineMacro("__ARM_FEATURE_FP16FML", "1");
@@ -206,6 +231,15 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
case llvm::AArch64::ArchKind::ARMV8_2A:
getTargetDefinesARMV82A(Opts, Builder);
break;
+ case llvm::AArch64::ArchKind::ARMV8_3A:
+ getTargetDefinesARMV83A(Opts, Builder);
+ break;
+ case llvm::AArch64::ArchKind::ARMV8_4A:
+ getTargetDefinesARMV84A(Opts, Builder);
+ break;
+ case llvm::AArch64::ArchKind::ARMV8_5A:
+ getTargetDefinesARMV85A(Opts, Builder);
+ break;
}
// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
@@ -229,12 +263,13 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) {
FPU = FPUMode;
- CRC = 0;
- Crypto = 0;
- Unaligned = 1;
- HasFullFP16 = 0;
- HasDotProd = 0;
- HasFP16FML = 0;
+ HasCRC = false;
+ HasCrypto = false;
+ HasUnaligned = true;
+ HasFullFP16 = false;
+ HasDotProd = false;
+ HasFP16FML = false;
+ HasMTE = false;
ArchKind = llvm::AArch64::ArchKind::ARMV8A;
for (const auto &Feature : Features) {
@@ -243,21 +278,29 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
if (Feature == "+sve")
FPU |= SveMode;
if (Feature == "+crc")
- CRC = 1;
+ HasCRC = true;
if (Feature == "+crypto")
- Crypto = 1;
+ HasCrypto = true;
if (Feature == "+strict-align")
- Unaligned = 0;
+ HasUnaligned = false;
if (Feature == "+v8.1a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_1A;
if (Feature == "+v8.2a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_2A;
+ if (Feature == "+v8.3a")
+ ArchKind = llvm::AArch64::ArchKind::ARMV8_3A;
+ if (Feature == "+v8.4a")
+ ArchKind = llvm::AArch64::ArchKind::ARMV8_4A;
+ if (Feature == "+v8.5a")
+ ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
if (Feature == "+fullfp16")
- HasFullFP16 = 1;
+ HasFullFP16 = true;
if (Feature == "+dotprod")
- HasDotProd = 1;
+ HasDotProd = true;
if (Feature == "+fp16fml")
- HasFP16FML = 1;
+ HasFP16FML = true;
+ if (Feature == "+mte")
+ HasMTE = true;
}
setDataLayout();
@@ -528,16 +571,10 @@ MicrosoftARM64TargetInfo::MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
TheCXXABI.set(TargetCXXABI::Microsoft);
}
-void MicrosoftARM64TargetInfo::getVisualStudioDefines(
- const LangOptions &Opts, MacroBuilder &Builder) const {
- WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, Builder);
- Builder.defineMacro("_M_ARM64", "1");
-}
-
void MicrosoftARM64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
- WindowsTargetInfo::getTargetDefines(Opts, Builder);
- getVisualStudioDefines(Opts, Builder);
+ WindowsARM64TargetInfo::getTargetDefines(Opts, Builder);
+ Builder.defineMacro("_M_ARM64", "1");
}
TargetInfo::CallingConvKind
@@ -545,6 +582,23 @@ MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const {
return CCK_MicrosoftWin64;
}
+unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const {
+ unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize);
+
+ // MSVC does size based alignment for arm64 based on alignment section in
+ // below document, replicate that to keep alignment consistent with object
+ // files compiled by MSVC.
+ // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions
+ if (TypeSize >= 512) { // TypeSize >= 64 bytes
+ Align = std::max(Align, 128u); // align type at least 16 bytes
+ } else if (TypeSize >= 64) { // TypeSize >= 8 bytes
+ Align = std::max(Align, 64u); // align type at least 8 butes
+ } else if (TypeSize >= 16) { // TypeSize >= 2 bytes
+ Align = std::max(Align, 32u); // align type at least 4 bytes
+ }
+ return Align;
+}
+
MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts)
: WindowsARM64TargetInfo(Triple, Opts) {
diff --git a/lib/Basic/Targets/AArch64.h b/lib/Basic/Targets/AArch64.h
index d7f767abd4d1..5833c146003b 100644
--- a/lib/Basic/Targets/AArch64.h
+++ b/lib/Basic/Targets/AArch64.h
@@ -1,9 +1,8 @@
//===--- AArch64.h - Declare AArch64 target feature support -----*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -29,12 +28,14 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
enum FPUModeEnum { FPUMode, NeonMode = (1 << 0), SveMode = (1 << 1) };
unsigned FPU;
- unsigned CRC;
- unsigned Crypto;
- unsigned Unaligned;
- unsigned HasFullFP16;
- unsigned HasDotProd;
- unsigned HasFP16FML;
+ bool HasCRC;
+ bool HasCrypto;
+ bool HasUnaligned;
+ bool HasFullFP16;
+ bool HasDotProd;
+ bool HasFP16FML;
+ bool HasMTE;
+
llvm::AArch64::ArchKind ArchKind;
static const Builtin::Info BuiltinInfo[];
@@ -59,6 +60,12 @@ public:
MacroBuilder &Builder) const;
void getTargetDefinesARMV82A(const LangOptions &Opts,
MacroBuilder &Builder) const;
+ void getTargetDefinesARMV83A(const LangOptions &Opts,
+ MacroBuilder &Builder) const;
+ void getTargetDefinesARMV84A(const LangOptions &Opts,
+ MacroBuilder &Builder) const;
+ void getTargetDefinesARMV85A(const LangOptions &Opts,
+ MacroBuilder &Builder) const;
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
@@ -123,12 +130,12 @@ public:
MicrosoftARM64TargetInfo(const llvm::Triple &Triple,
const TargetOptions &Opts);
- void getVisualStudioDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const;
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
TargetInfo::CallingConvKind
getCallingConvKind(bool ClangABICompat4) const override;
+
+ unsigned getMinGlobalAlign(uint64_t TypeSize) const override;
};
// ARM64 MinGW target
diff --git a/lib/Basic/Targets/AMDGPU.cpp b/lib/Basic/Targets/AMDGPU.cpp
index 7313a692f46b..b5c82e288570 100644
--- a/lib/Basic/Targets/AMDGPU.cpp
+++ b/lib/Basic/Targets/AMDGPU.cpp
@@ -1,9 +1,8 @@
//===--- AMDGPU.cpp - Implement AMDGPU target feature support -------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -35,7 +34,8 @@ static const char *const DataLayoutStringR600 =
static const char *const DataLayoutStringAMDGCN =
"e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
- "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
+ "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+ "-ni:7";
const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
Generic, // Default
@@ -135,9 +135,33 @@ bool AMDGPUTargetInfo::initFeatureMap(
CPU = "gfx600";
switch (llvm::AMDGPU::parseArchAMDGCN(CPU)) {
+ case GK_GFX1012:
+ case GK_GFX1011:
+ Features["dot1-insts"] = true;
+ Features["dot2-insts"] = true;
+ Features["dot5-insts"] = true;
+ Features["dot6-insts"] = true;
+ LLVM_FALLTHROUGH;
+ case GK_GFX1010:
+ Features["dl-insts"] = true;
+ Features["ci-insts"] = true;
+ Features["16-bit-insts"] = true;
+ Features["dpp"] = true;
+ Features["gfx8-insts"] = true;
+ Features["gfx9-insts"] = true;
+ Features["gfx10-insts"] = true;
+ Features["s-memrealtime"] = true;
+ break;
+ case GK_GFX908:
+ Features["dot3-insts"] = true;
+ Features["dot4-insts"] = true;
+ Features["dot5-insts"] = true;
+ Features["dot6-insts"] = true;
+ LLVM_FALLTHROUGH;
case GK_GFX906:
Features["dl-insts"] = true;
- Features["dot-insts"] = true;
+ Features["dot1-insts"] = true;
+ Features["dot2-insts"] = true;
LLVM_FALLTHROUGH;
case GK_GFX909:
case GK_GFX904:
@@ -149,7 +173,7 @@ bool AMDGPUTargetInfo::initFeatureMap(
case GK_GFX803:
case GK_GFX802:
case GK_GFX801:
- Features["vi-insts"] = true;
+ Features["gfx8-insts"] = true;
Features["16-bit-insts"] = true;
Features["dpp"] = true;
Features["s-memrealtime"] = true;
@@ -251,6 +275,9 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple,
!isAMDGCN(Triple));
UseAddrSpaceMapMangling = true;
+ HasLegalHalfType = true;
+ HasFloat16 = true;
+
// Set pointer width and alignment for target address space 0.
PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits();
if (getMaxPointerWidth() == 64) {
@@ -306,3 +333,18 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions &Opts,
if (hasFastFMA())
Builder.defineMacro("FP_FAST_FMA");
}
+
+void AMDGPUTargetInfo::setAuxTarget(const TargetInfo *Aux) {
+ assert(HalfFormat == Aux->HalfFormat);
+ assert(FloatFormat == Aux->FloatFormat);
+ assert(DoubleFormat == Aux->DoubleFormat);
+
+ // On x86_64 long double is 80-bit extended precision format, which is
+ // not supported by AMDGPU. 128-bit floating point format is also not
+ // supported by AMDGPU. Therefore keep its own format for these two types.
+ auto SaveLongDoubleFormat = LongDoubleFormat;
+ auto SaveFloat128Format = Float128Format;
+ copyAuxTarget(Aux);
+ LongDoubleFormat = SaveLongDoubleFormat;
+ Float128Format = SaveFloat128Format;
+}
diff --git a/lib/Basic/Targets/AMDGPU.h b/lib/Basic/Targets/AMDGPU.h
index 926772809aa7..456cb2ebb8b5 100644
--- a/lib/Basic/Targets/AMDGPU.h
+++ b/lib/Basic/Targets/AMDGPU.h
@@ -1,9 +1,8 @@
//===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -42,7 +41,6 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
llvm::AMDGPU::GPUKind GPUKind;
unsigned GPUFeatures;
-
bool hasFP64() const {
return getTriple().getArch() == llvm::Triple::amdgcn ||
!!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64);
@@ -352,6 +350,8 @@ public:
uint64_t getNullPointerValue(LangAS AS) const override {
return AS == LangAS::opencl_local ? ~0 : 0;
}
+
+ void setAuxTarget(const TargetInfo *Aux) override;
};
} // namespace targets
diff --git a/lib/Basic/Targets/ARC.cpp b/lib/Basic/Targets/ARC.cpp
index 2159ab8e2020..5cc13e2cf728 100644
--- a/lib/Basic/Targets/ARC.cpp
+++ b/lib/Basic/Targets/ARC.cpp
@@ -1,9 +1,8 @@
//===--- ARC.cpp - Implement ARC target feature support -------------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -22,4 +21,4 @@ using namespace clang::targets;
void ARCTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__arc__");
-}
+}
diff --git a/lib/Basic/Targets/ARC.h b/lib/Basic/Targets/ARC.h
index ee20568f3d5b..c43a39984edb 100644
--- a/lib/Basic/Targets/ARC.h
+++ b/lib/Basic/Targets/ARC.h
@@ -1,9 +1,8 @@
//===--- ARC.h - Declare ARC target feature support -------------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/ARM.cpp b/lib/Basic/Targets/ARM.cpp
index 16644ace108b..c6834b9fac15 100644
--- a/lib/Basic/Targets/ARM.cpp
+++ b/lib/Basic/Targets/ARM.cpp
@@ -1,9 +1,8 @@
//===--- ARM.cpp - Implement ARM target feature support -------------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -41,13 +40,14 @@ void ARMTargetInfo::setABIAAPCS() {
// so set preferred for small types to 32.
if (T.isOSBinFormatMachO()) {
resetDataLayout(BigEndian
- ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
- : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
+ ? "E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
} else if (T.isOSWindows()) {
assert(!BigEndian && "Windows on ARM does not support big endian");
resetDataLayout("e"
"-m:w"
"-p:32:32"
+ "-Fi8"
"-i64:64"
"-v128:64:128"
"-a:0:32"
@@ -55,11 +55,11 @@ void ARMTargetInfo::setABIAAPCS() {
"-S64");
} else if (T.isOSNaCl()) {
assert(!BigEndian && "NaCl on ARM does not support big endian");
- resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128");
+ resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");
} else {
resetDataLayout(BigEndian
- ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
- : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
+ ? "E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ : "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
}
// FIXME: Enumerated types are variable width in straight AAPCS.
@@ -88,17 +88,17 @@ void ARMTargetInfo::setABIAPCS(bool IsAAPCS16) {
if (T.isOSBinFormatMachO() && IsAAPCS16) {
assert(!BigEndian && "AAPCS16 does not support big-endian");
- resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128");
+ resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128");
} else if (T.isOSBinFormatMachO())
resetDataLayout(
BigEndian
- ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
- : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
+ ? "E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+ : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
else
resetDataLayout(
BigEndian
- ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
- : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
+ ? "E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+ : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32");
// FIXME: Override "preferred align" for double and long long.
}
@@ -146,6 +146,14 @@ void ARMTargetInfo::setAtomic() {
}
}
+bool ARMTargetInfo::hasMVE() const {
+ return ArchKind == llvm::ARM::ArchKind::ARMV8_1MMainline && MVE != 0;
+}
+
+bool ARMTargetInfo::hasMVEFloat() const {
+ return hasMVE() && (MVE & MVE_FP);
+}
+
bool ARMTargetInfo::isThumb() const {
return ArchISA == llvm::ARM::ISAKind::THUMB;
}
@@ -197,6 +205,8 @@ StringRef ARMTargetInfo::getCPUAttr() const {
return "8M_MAIN";
case llvm::ARM::ArchKind::ARMV8R:
return "8R";
+ case llvm::ARM::ArchKind::ARMV8_1MMainline:
+ return "8_1M_MAIN";
}
}
@@ -313,6 +323,8 @@ ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple,
this->MCountName = Opts.EABIVersion == llvm::EABI::GNU
? "\01__gnu_mcount_nc"
: "\01mcount";
+
+ SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi");
}
StringRef ARMTargetInfo::getABI() const { return ABI; }
@@ -375,12 +387,21 @@ bool ARMTargetInfo::initFeatureMap(
// Convert user-provided arm and thumb GNU target attributes to
// [-|+]thumb-mode target features respectively.
- std::vector<std::string> UpdatedFeaturesVec(FeaturesVec);
- for (auto &Feature : UpdatedFeaturesVec) {
- if (Feature.compare("+arm") == 0)
- Feature = "-thumb-mode";
- else if (Feature.compare("+thumb") == 0)
- Feature = "+thumb-mode";
+ std::vector<std::string> UpdatedFeaturesVec;
+ for (const auto &Feature : FeaturesVec) {
+ // Skip soft-float-abi; it's something we only use to initialize a bit of
+ // class state, and is otherwise unrecognized.
+ if (Feature == "+soft-float-abi")
+ continue;
+
+ StringRef FixedFeature;
+ if (Feature == "+arm")
+ FixedFeature = "-thumb-mode";
+ else if (Feature == "+thumb")
+ FixedFeature = "+thumb-mode";
+ else
+ FixedFeature = Feature;
+ UpdatedFeaturesVec.push_back(FixedFeature.str());
}
return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
@@ -390,37 +411,49 @@ bool ARMTargetInfo::initFeatureMap(
bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) {
FPU = 0;
+ MVE = 0;
CRC = 0;
Crypto = 0;
DSP = 0;
Unaligned = 1;
- SoftFloat = SoftFloatABI = false;
+ SoftFloat = false;
+ // Note that SoftFloatABI is initialized in our constructor.
HWDiv = 0;
DotProd = 0;
+ HasFloat16 = true;
// This does not diagnose illegal cases like having both
- // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
- uint32_t HW_FP_remove = 0;
+ // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
for (const auto &Feature : Features) {
if (Feature == "+soft-float") {
SoftFloat = true;
- } else if (Feature == "+soft-float-abi") {
- SoftFloatABI = true;
- } else if (Feature == "+vfp2") {
+ } else if (Feature == "+vfp2sp" || Feature == "+vfp2d16sp" ||
+ Feature == "+vfp2" || Feature == "+vfp2d16") {
FPU |= VFP2FPU;
- HW_FP |= HW_FP_SP | HW_FP_DP;
- } else if (Feature == "+vfp3") {
+ HW_FP |= HW_FP_SP;
+ if (Feature == "+vfp2" || Feature == "+vfp2d16")
+ HW_FP |= HW_FP_DP;
+ } else if (Feature == "+vfp3sp" || Feature == "+vfp3d16sp" ||
+ Feature == "+vfp3" || Feature == "+vfp3d16") {
FPU |= VFP3FPU;
- HW_FP |= HW_FP_SP | HW_FP_DP;
- } else if (Feature == "+vfp4") {
+ HW_FP |= HW_FP_SP;
+ if (Feature == "+vfp3" || Feature == "+vfp3d16")
+ HW_FP |= HW_FP_DP;
+ } else if (Feature == "+vfp4sp" || Feature == "+vfp4d16sp" ||
+ Feature == "+vfp4" || Feature == "+vfp4d16") {
FPU |= VFP4FPU;
- HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
- } else if (Feature == "+fp-armv8") {
+ HW_FP |= HW_FP_SP | HW_FP_HP;
+ if (Feature == "+vfp4" || Feature == "+vfp4d16")
+ HW_FP |= HW_FP_DP;
+ } else if (Feature == "+fp-armv8sp" || Feature == "+fp-armv8d16sp" ||
+ Feature == "+fp-armv8" || Feature == "+fp-armv8d16") {
FPU |= FPARMV8;
- HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
+ HW_FP |= HW_FP_SP | HW_FP_HP;
+ if (Feature == "+fp-armv8" || Feature == "+fp-armv8d16")
+ HW_FP |= HW_FP_DP;
} else if (Feature == "+neon") {
FPU |= NeonFPU;
- HW_FP |= HW_FP_SP | HW_FP_DP;
+ HW_FP |= HW_FP_SP;
} else if (Feature == "+hwdiv") {
HWDiv |= HWDivThumb;
} else if (Feature == "+hwdiv-arm") {
@@ -431,8 +464,13 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
Crypto = 1;
} else if (Feature == "+dsp") {
DSP = 1;
- } else if (Feature == "+fp-only-sp") {
- HW_FP_remove |= HW_FP_DP;
+ } else if (Feature == "+fp64") {
+ HW_FP |= HW_FP_DP;
+ } else if (Feature == "+8msecext") {
+ if (CPUProfile != "M" || ArchVersion != 8) {
+ Diags.Report(diag::err_target_unsupported_mcmse) << CPU;
+ return false;
+ }
} else if (Feature == "+strict-align") {
Unaligned = 0;
} else if (Feature == "+fp16") {
@@ -441,9 +479,17 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasLegalHalfType = true;
} else if (Feature == "+dotprod") {
DotProd = true;
+ } else if (Feature == "+mve") {
+ DSP = 1;
+ MVE |= MVE_INT;
+ } else if (Feature == "+mve.fp") {
+ DSP = 1;
+ HasLegalHalfType = true;
+ FPU |= FPARMV8;
+ MVE |= MVE_INT | MVE_FP;
+ HW_FP |= HW_FP_SP | HW_FP_HP;
}
}
- HW_FP &= ~HW_FP_remove;
switch (ArchVersion) {
case 6:
@@ -474,11 +520,6 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
else if (FPMath == FP_VFP)
Features.push_back("-neonfp");
- // Remove front-end specific options which the backend handles differently.
- auto Feature = std::find(Features.begin(), Features.end(), "+soft-float-abi");
- if (Feature != Features.end())
- Features.erase(Feature);
-
return true;
}
@@ -492,6 +533,7 @@ bool ARMTargetInfo::hasFeature(StringRef Feature) const {
.Case("vfp", FPU && !SoftFloat)
.Case("hwdiv", HWDiv & HWDivThumb)
.Case("hwdiv-arm", HWDiv & HWDivARM)
+ .Case("mve", hasMVE())
.Default(false);
}
@@ -652,6 +694,12 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
if (SoftFloat)
Builder.defineMacro("__SOFTFP__");
+ // ACLE position independent code macros.
+ if (Opts.ROPI)
+ Builder.defineMacro("__ARM_ROPI", "1");
+ if (Opts.RWPI)
+ Builder.defineMacro("__ARM_RWPI", "1");
+
if (ArchKind == llvm::ARM::ArchKind::XSCALE)
Builder.defineMacro("__XSCALE__");
@@ -701,11 +749,19 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
"0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
}
+ if (hasMVE()) {
+ Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? "3" : "1");
+ }
+
Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
Twine(Opts.WCharSize ? Opts.WCharSize : 4));
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
+ // CMSE
+ if (ArchVersion == 8 && ArchProfile == llvm::ARM::ProfileKind::M)
+ Builder.defineMacro("__ARM_FEATURE_CMSE", Opts.Cmse ? "3" : "1");
+
if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
@@ -844,6 +900,17 @@ bool ARMTargetInfo::validateAsmConstraint(
case 'Q': // A memory address that is a single base register.
Info.setAllowsMemory();
return true;
+ case 'T':
+ switch (Name[1]) {
+ default:
+ break;
+ case 'e': // Even general-purpose register
+ case 'o': // Odd general-purpose register
+ Info.setAllowsRegister();
+ Name++;
+ return true;
+ }
+ break;
case 'U': // a memory reference...
switch (Name[1]) {
case 'q': // ...ARMV4 ldrsb
@@ -859,6 +926,7 @@ bool ARMTargetInfo::validateAsmConstraint(
Name++;
return true;
}
+ break;
}
return false;
}
@@ -867,6 +935,7 @@ std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const {
std::string R;
switch (*Constraint) {
case 'U': // Two-character constraint; add "^" hint for later parsing.
+ case 'T':
R = std::string("^") + std::string(Constraint, 2);
Constraint++;
break;
@@ -961,8 +1030,6 @@ WindowsARMTargetInfo::WindowsARMTargetInfo(const llvm::Triple &Triple,
void WindowsARMTargetInfo::getVisualStudioDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
- WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
-
// FIXME: this is invalid for WindowsCE
Builder.defineMacro("_M_ARM_NT", "1");
Builder.defineMacro("_M_ARMT", "_M_ARM");
@@ -1049,7 +1116,7 @@ CygwinARMTargetInfo::CygwinARMTargetInfo(const llvm::Triple &Triple,
this->WCharType = TargetInfo::UnsignedShort;
TLSSupported = false;
DoubleAlign = LongLongAlign = 64;
- resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64");
+ resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
}
void CygwinARMTargetInfo::getTargetDefines(const LangOptions &Opts,
diff --git a/lib/Basic/Targets/ARM.h b/lib/Basic/Targets/ARM.h
index 9c72c3387f7a..ce87a6265934 100644
--- a/lib/Basic/Targets/ARM.h
+++ b/lib/Basic/Targets/ARM.h
@@ -1,9 +1,8 @@
//===--- ARM.h - Declare ARM target feature support -------------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -34,6 +33,11 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
FPARMV8 = (1 << 4)
};
+ enum MVEMode {
+ MVE_INT = (1 << 0),
+ MVE_FP = (1 << 1)
+ };
+
// Possible HWDiv features.
enum HWDivMode { HWDivThumb = (1 << 0), HWDivARM = (1 << 1) };
@@ -57,6 +61,7 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
unsigned ArchVersion;
unsigned FPU : 5;
+ unsigned MVE : 2;
unsigned IsAAPCS : 1;
unsigned HWDiv : 2;
@@ -101,6 +106,8 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
bool isThumb() const;
bool supportsThumb() const;
bool supportsThumb2() const;
+ bool hasMVE() const;
+ bool hasMVEFloat() const;
StringRef getCPUAttr() const;
StringRef getCPUProfile() const;
@@ -117,6 +124,12 @@ public:
StringRef CPU,
const std::vector<std::string> &FeaturesVec) const override;
+ bool isValidFeatureName(StringRef Feature) const override {
+ // We pass soft-float-abi in as a -target-feature, but the backend figures
+ // this out through other means.
+ return Feature != "soft-float-abi";
+ }
+
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override;
diff --git a/lib/Basic/Targets/AVR.cpp b/lib/Basic/Targets/AVR.cpp
index 9b66449cbca6..d865676700b5 100644
--- a/lib/Basic/Targets/AVR.cpp
+++ b/lib/Basic/Targets/AVR.cpp
@@ -1,9 +1,8 @@
//===--- AVR.cpp - Implement AVR target feature support -------------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/AVR.h b/lib/Basic/Targets/AVR.h
index d595f48e8ef7..94f006ee1b8a 100644
--- a/lib/Basic/Targets/AVR.h
+++ b/lib/Basic/Targets/AVR.h
@@ -1,9 +1,8 @@
//===--- AVR.h - Declare AVR target feature support -------------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/BPF.cpp b/lib/Basic/Targets/BPF.cpp
index cf41a09d76f5..0cf55a58a951 100644
--- a/lib/Basic/Targets/BPF.cpp
+++ b/lib/Basic/Targets/BPF.cpp
@@ -1,9 +1,8 @@
//===--- BPF.cpp - Implement BPF target feature support -------------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -21,12 +20,12 @@ using namespace clang::targets;
void BPFTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
- DefineStd(Builder, "bpf", Opts);
+ Builder.defineMacro("__bpf__");
Builder.defineMacro("__BPF__");
}
static constexpr llvm::StringLiteral ValidCPUNames[] = {"generic", "v1", "v2",
- "probe"};
+ "v3", "probe"};
bool BPFTargetInfo::isValidCPUName(StringRef Name) const {
return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
diff --git a/lib/Basic/Targets/BPF.h b/lib/Basic/Targets/BPF.h
index 7f97f8189145..79abd8828a2c 100644
--- a/lib/Basic/Targets/BPF.h
+++ b/lib/Basic/Targets/BPF.h
@@ -1,9 +1,8 @@
//===--- BPF.h - Declare BPF target feature support -------------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/Hexagon.cpp b/lib/Basic/Targets/Hexagon.cpp
index 94e1388e381e..be23fd2536e0 100644
--- a/lib/Basic/Targets/Hexagon.cpp
+++ b/lib/Basic/Targets/Hexagon.cpp
@@ -1,9 +1,8 @@
//===--- Hexagon.cpp - Implement Hexagon target feature support -----------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/Hexagon.h b/lib/Basic/Targets/Hexagon.h
index fb4956a9e53d..25a78c181580 100644
--- a/lib/Basic/Targets/Hexagon.h
+++ b/lib/Basic/Targets/Hexagon.h
@@ -1,9 +1,8 @@
//===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/Lanai.cpp b/lib/Basic/Targets/Lanai.cpp
index 0e8030c04e5c..bb1872083c09 100644
--- a/lib/Basic/Targets/Lanai.cpp
+++ b/lib/Basic/Targets/Lanai.cpp
@@ -1,9 +1,8 @@
//===--- Lanai.cpp - Implement Lanai target feature support ---------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/Lanai.h b/lib/Basic/Targets/Lanai.h
index b9e6dbe04433..e119606384c7 100644
--- a/lib/Basic/Targets/Lanai.h
+++ b/lib/Basic/Targets/Lanai.h
@@ -1,9 +1,8 @@
//===--- Lanai.h - Declare Lanai target feature support ---------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/Le64.cpp b/lib/Basic/Targets/Le64.cpp
index 5a1c1c88e7e3..cacd10dc8936 100644
--- a/lib/Basic/Targets/Le64.cpp
+++ b/lib/Basic/Targets/Le64.cpp
@@ -1,9 +1,8 @@
//===--- Le64.cpp - Implement Le64 target feature support -----------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/Le64.h b/lib/Basic/Targets/Le64.h
index 5e18d0498641..253d5681abc2 100644
--- a/lib/Basic/Targets/Le64.h
+++ b/lib/Basic/Targets/Le64.h
@@ -1,9 +1,8 @@
//===--- Le64.h - Declare Le64 target feature support -----------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/MSP430.cpp b/lib/Basic/Targets/MSP430.cpp
index 86f85a398f14..ef53ee352c32 100644
--- a/lib/Basic/Targets/MSP430.cpp
+++ b/lib/Basic/Targets/MSP430.cpp
@@ -1,9 +1,8 @@
//===--- MSP430.cpp - Implement MSP430 target feature support -------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/MSP430.h b/lib/Basic/Targets/MSP430.h
index 72aafb9459bd..620f12d2b8e3 100644
--- a/lib/Basic/Targets/MSP430.h
+++ b/lib/Basic/Targets/MSP430.h
@@ -1,9 +1,8 @@
//===--- MSP430.h - Declare MSP430 target feature support -------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -34,6 +33,10 @@ public:
LongWidth = 32;
LongLongWidth = 64;
LongAlign = LongLongAlign = 16;
+ FloatWidth = 32;
+ FloatAlign = 16;
+ DoubleWidth = LongDoubleWidth = 64;
+ DoubleAlign = LongDoubleAlign = 16;
PointerWidth = 16;
PointerAlign = 16;
SuitableAlign = 16;
@@ -52,6 +55,8 @@ public:
return None;
}
+ bool allowsLargerPreferedTypeAlignment() const override { return false; }
+
bool hasFeature(StringRef Feature) const override {
return Feature == "msp430";
}
diff --git a/lib/Basic/Targets/Mips.cpp b/lib/Basic/Targets/Mips.cpp
index d43edeae608f..2cafbe87a996 100644
--- a/lib/Basic/Targets/Mips.cpp
+++ b/lib/Basic/Targets/Mips.cpp
@@ -1,9 +1,8 @@
//===--- Mips.cpp - Implement Mips target feature support -----------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -216,6 +215,14 @@ ArrayRef<Builtin::Info> MipsTargetInfo::getTargetBuiltins() const {
Builtin::FirstTSBuiltin);
}
+unsigned MipsTargetInfo::getUnwindWordWidth() const {
+ return llvm::StringSwitch<unsigned>(ABI)
+ .Case("o32", 32)
+ .Case("n32", 64)
+ .Case("n64", 64)
+ .Default(getPointerWidth(0));
+}
+
bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
// microMIPS64R6 backend was removed.
if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
diff --git a/lib/Basic/Targets/Mips.h b/lib/Basic/Targets/Mips.h
index d49f49888b0c..474cda84a40e 100644
--- a/lib/Basic/Targets/Mips.h
+++ b/lib/Basic/Targets/Mips.h
@@ -1,9 +1,8 @@
//===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -402,6 +401,8 @@ public:
return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
}
+ unsigned getUnwindWordWidth() const override;
+
bool validateTarget(DiagnosticsEngine &Diags) const override;
};
} // namespace targets
diff --git a/lib/Basic/Targets/NVPTX.cpp b/lib/Basic/Targets/NVPTX.cpp
index ca41c4d14ca3..f69e9d84c701 100644
--- a/lib/Basic/Targets/NVPTX.cpp
+++ b/lib/Basic/Targets/NVPTX.cpp
@@ -1,9 +1,8 @@
//===--- NVPTX.cpp - Implement NVPTX target feature support ---------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -45,6 +44,8 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
if (!Feature.startswith("+ptx"))
continue;
PTXVersion = llvm::StringSwitch<unsigned>(Feature)
+ .Case("+ptx64", 64)
+ .Case("+ptx63", 63)
.Case("+ptx61", 61)
.Case("+ptx60", 60)
.Case("+ptx50", 50)
@@ -118,7 +119,7 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
LongAlign = HostTarget->getLongAlign();
LongLongWidth = HostTarget->getLongLongWidth();
LongLongAlign = HostTarget->getLongLongAlign();
- MinGlobalAlign = HostTarget->getMinGlobalAlign();
+ MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0);
NewAlign = HostTarget->getNewAlign();
DefaultAlignForAttributeAligned =
HostTarget->getDefaultAlignForAttributeAligned();
@@ -190,7 +191,11 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
case CudaArch::GFX902:
case CudaArch::GFX904:
case CudaArch::GFX906:
+ case CudaArch::GFX908:
case CudaArch::GFX909:
+ case CudaArch::GFX1010:
+ case CudaArch::GFX1011:
+ case CudaArch::GFX1012:
case CudaArch::LAST:
break;
case CudaArch::UNKNOWN:
diff --git a/lib/Basic/Targets/NVPTX.h b/lib/Basic/Targets/NVPTX.h
index 84d466d2f49f..2cdd37ca1b07 100644
--- a/lib/Basic/Targets/NVPTX.h
+++ b/lib/Basic/Targets/NVPTX.h
@@ -1,9 +1,8 @@
//===--- NVPTX.h - Declare NVPTX target feature support ---------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -36,6 +35,16 @@ static const unsigned NVPTXAddrSpaceMap[] = {
3, // cuda_shared
};
+/// The DWARF address class. Taken from
+/// https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf
+static const int NVPTXDWARFAddrSpaceMap[] = {
+ -1, // Default, opencl_private or opencl_generic - not defined
+ 5, // opencl_global
+ -1,
+ 8, // opencl_local or cuda_shared
+ 4, // opencl_constant or cuda_constant
+};
+
class LLVM_LIBRARY_VISIBILITY NVPTXTargetInfo : public TargetInfo {
static const char *const GCCRegNames[];
static const Builtin::Info BuiltinInfo[];
@@ -125,6 +134,20 @@ public:
Opts.support("cl_khr_local_int32_extended_atomics");
}
+ /// \returns If a target requires an address within a target specific address
+ /// space \p AddressSpace to be converted in order to be used, then return the
+ /// corresponding target specific DWARF address space.
+ ///
+ /// \returns Otherwise return None and no conversion will be emitted in the
+ /// DWARF.
+ Optional<unsigned>
+ getDWARFAddressSpace(unsigned AddressSpace) const override {
+ if (AddressSpace >= llvm::array_lengthof(NVPTXDWARFAddrSpaceMap) ||
+ NVPTXDWARFAddrSpaceMap[AddressSpace] < 0)
+ return llvm::None;
+ return NVPTXDWARFAddrSpaceMap[AddressSpace];
+ }
+
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
// CUDA compilations support all of the host's calling conventions.
//
diff --git a/lib/Basic/Targets/OSTargets.cpp b/lib/Basic/Targets/OSTargets.cpp
index 6252a51ef710..72fdb0e7dde8 100644
--- a/lib/Basic/Targets/OSTargets.cpp
+++ b/lib/Basic/Targets/OSTargets.cpp
@@ -1,9 +1,8 @@
//===--- OSTargets.cpp - Implement OS target feature support --------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -135,5 +134,84 @@ void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
PlatformMinVersion = VersionTuple(Maj, Min, Rev);
}
+
+static void addMinGWDefines(const llvm::Triple &Triple, const LangOptions &Opts,
+ MacroBuilder &Builder) {
+ DefineStd(Builder, "WIN32", Opts);
+ DefineStd(Builder, "WINNT", Opts);
+ if (Triple.isArch64Bit()) {
+ DefineStd(Builder, "WIN64", Opts);
+ Builder.defineMacro("__MINGW64__");
+ }
+ Builder.defineMacro("__MSVCRT__");
+ Builder.defineMacro("__MINGW32__");
+ addCygMingDefines(Opts, Builder);
+}
+
+static void addVisualCDefines(const LangOptions &Opts, MacroBuilder &Builder) {
+ if (Opts.CPlusPlus) {
+ if (Opts.RTTIData)
+ Builder.defineMacro("_CPPRTTI");
+
+ if (Opts.CXXExceptions)
+ Builder.defineMacro("_CPPUNWIND");
+ }
+
+ if (Opts.Bool)
+ Builder.defineMacro("__BOOL_DEFINED");
+
+ if (!Opts.CharIsSigned)
+ Builder.defineMacro("_CHAR_UNSIGNED");
+
+ // FIXME: POSIXThreads isn't exactly the option this should be defined for,
+ // but it works for now.
+ if (Opts.POSIXThreads)
+ Builder.defineMacro("_MT");
+
+ if (Opts.MSCompatibilityVersion) {
+ Builder.defineMacro("_MSC_VER",
+ Twine(Opts.MSCompatibilityVersion / 100000));
+ Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
+ // FIXME We cannot encode the revision information into 32-bits
+ Builder.defineMacro("_MSC_BUILD", Twine(1));
+
+ if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
+ Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
+
+ if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
+ if (Opts.CPlusPlus2a)
+ Builder.defineMacro("_MSVC_LANG", "201704L");
+ else if (Opts.CPlusPlus17)
+ Builder.defineMacro("_MSVC_LANG", "201703L");
+ else if (Opts.CPlusPlus14)
+ Builder.defineMacro("_MSVC_LANG", "201402L");
+ }
+ }
+
+ if (Opts.MicrosoftExt) {
+ Builder.defineMacro("_MSC_EXTENSIONS");
+
+ if (Opts.CPlusPlus11) {
+ Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
+ Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
+ Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
+ }
+ }
+
+ Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
+}
+
+void addWindowsDefines(const llvm::Triple &Triple, const LangOptions &Opts,
+ MacroBuilder &Builder) {
+ Builder.defineMacro("_WIN32");
+ if (Triple.isArch64Bit())
+ Builder.defineMacro("_WIN64");
+ if (Triple.isWindowsGNUEnvironment())
+ addMinGWDefines(Triple, Opts, Builder);
+ else if (Triple.isKnownWindowsMSVCEnvironment() ||
+ (Triple.isWindowsItaniumEnvironment() && Opts.MSVCCompat))
+ addVisualCDefines(Opts, Builder);
+}
+
} // namespace targets
} // namespace clang
diff --git a/lib/Basic/Targets/OSTargets.h b/lib/Basic/Targets/OSTargets.h
index 085efa02cc5f..8542311ffa41 100644
--- a/lib/Basic/Targets/OSTargets.h
+++ b/lib/Basic/Targets/OSTargets.h
@@ -1,9 +1,8 @@
//===--- OSTargets.h - Declare OS target feature support --------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -134,6 +133,37 @@ public:
/// attribute on declarations that can be dynamically replaced.
bool hasProtectedVisibility() const override { return false; }
+ unsigned getExnObjectAlignment() const override {
+ // Older versions of libc++abi guarantee an alignment of only 8-bytes for
+ // exception objects because of a bug in __cxa_exception that was
+ // eventually fixed in r319123.
+ llvm::VersionTuple MinVersion;
+ const llvm::Triple &T = this->getTriple();
+
+ // Compute the earliest OS versions that have the fix to libc++abi.
+ switch (T.getOS()) {
+ case llvm::Triple::Darwin:
+ case llvm::Triple::MacOSX: // Earliest supporting version is 10.14.
+ MinVersion = llvm::VersionTuple(10U, 14U);
+ break;
+ case llvm::Triple::IOS:
+ case llvm::Triple::TvOS: // Earliest supporting version is 12.0.0.
+ MinVersion = llvm::VersionTuple(12U);
+ break;
+ case llvm::Triple::WatchOS: // Earliest supporting version is 5.0.0.
+ MinVersion = llvm::VersionTuple(5U);
+ break;
+ default:
+ llvm_unreachable("Unexpected OS");
+ }
+
+ unsigned Major, Minor, Micro;
+ T.getOSVersion(Major, Minor, Micro);
+ if (llvm::VersionTuple(Major, Minor, Micro) < MinVersion)
+ return 64;
+ return OSTargetInfo<Target>::getExnObjectAlignment();
+ }
+
TargetInfo::IntType getLeastIntTypeByWidth(unsigned BitWidth,
bool IsSigned) const final {
// Darwin uses `long long` for `int_least64_t` and `int_fast64_t`.
@@ -602,7 +632,11 @@ protected:
public:
SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
: OSTargetInfo<Target>(Triple, Opts) {
- // FIXME: WIntType should be SignedLong
+ if (this->PointerWidth == 64) {
+ this->WCharType = this->WIntType = this->SignedInt;
+ } else {
+ this->WCharType = this->WIntType = this->SignedLong;
+ }
switch (Triple.getArch()) {
default:
break;
@@ -614,71 +648,79 @@ public:
}
};
-// Windows target
+// AIX Target
template <typename Target>
-class LLVM_LIBRARY_VISIBILITY WindowsTargetInfo : public OSTargetInfo<Target> {
+class AIXTargetInfo : public OSTargetInfo<Target> {
protected:
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
MacroBuilder &Builder) const override {
- Builder.defineMacro("_WIN32");
- if (Triple.isArch64Bit())
- Builder.defineMacro("_WIN64");
- if (Triple.isWindowsGNUEnvironment())
- addMinGWDefines(Triple, Opts, Builder);
-
- }
- void getVisualStudioDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const {
- if (Opts.CPlusPlus) {
- if (Opts.RTTIData)
- Builder.defineMacro("_CPPRTTI");
-
- if (Opts.CXXExceptions)
- Builder.defineMacro("_CPPUNWIND");
+ DefineStd(Builder, "unix", Opts);
+ Builder.defineMacro("_IBMR2");
+ Builder.defineMacro("_POWER");
+
+ Builder.defineMacro("_AIX");
+
+ unsigned Major, Minor, Micro;
+ Triple.getOSVersion(Major, Minor, Micro);
+
+ // Define AIX OS-Version Macros.
+ // Includes logic for legacy versions of AIX; no specific intent to support.
+ std::pair<int, int> OsVersion = {Major, Minor};
+ if (OsVersion >= std::make_pair(3, 2)) Builder.defineMacro("_AIX32");
+ if (OsVersion >= std::make_pair(4, 1)) Builder.defineMacro("_AIX41");
+ if (OsVersion >= std::make_pair(4, 3)) Builder.defineMacro("_AIX43");
+ if (OsVersion >= std::make_pair(5, 0)) Builder.defineMacro("_AIX50");
+ if (OsVersion >= std::make_pair(5, 1)) Builder.defineMacro("_AIX51");
+ if (OsVersion >= std::make_pair(5, 2)) Builder.defineMacro("_AIX52");
+ if (OsVersion >= std::make_pair(5, 3)) Builder.defineMacro("_AIX53");
+ if (OsVersion >= std::make_pair(6, 1)) Builder.defineMacro("_AIX61");
+ if (OsVersion >= std::make_pair(7, 1)) Builder.defineMacro("_AIX71");
+ if (OsVersion >= std::make_pair(7, 2)) Builder.defineMacro("_AIX72");
+
+ // FIXME: Do not define _LONG_LONG when -fno-long-long is specified.
+ Builder.defineMacro("_LONG_LONG");
+
+ if (Opts.POSIXThreads) {
+ Builder.defineMacro("_THREAD_SAFE");
}
- if (Opts.Bool)
- Builder.defineMacro("__BOOL_DEFINED");
+ if (this->PointerWidth == 64) {
+ Builder.defineMacro("__64BIT__");
+ }
- if (!Opts.CharIsSigned)
- Builder.defineMacro("_CHAR_UNSIGNED");
+ // Define _WCHAR_T when it is a fundamental type
+ // (i.e., for C++ without -fno-wchar).
+ if (Opts.CPlusPlus && Opts.WChar) {
+ Builder.defineMacro("_WCHAR_T");
+ }
+ }
- // FIXME: POSIXThreads isn't exactly the option this should be defined for,
- // but it works for now.
- if (Opts.POSIXThreads)
- Builder.defineMacro("_MT");
-
- if (Opts.MSCompatibilityVersion) {
- Builder.defineMacro("_MSC_VER",
- Twine(Opts.MSCompatibilityVersion / 100000));
- Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
- // FIXME We cannot encode the revision information into 32-bits
- Builder.defineMacro("_MSC_BUILD", Twine(1));
-
- if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
- Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
-
- if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) {
- if (Opts.CPlusPlus2a)
- Builder.defineMacro("_MSVC_LANG", "201704L");
- else if (Opts.CPlusPlus17)
- Builder.defineMacro("_MSVC_LANG", "201703L");
- else if (Opts.CPlusPlus14)
- Builder.defineMacro("_MSVC_LANG", "201402L");
- }
+public:
+ AIXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
+ : OSTargetInfo<Target>(Triple, Opts) {
+ if (this->PointerWidth == 64) {
+ this->WCharType = this->UnsignedInt;
+ } else {
+ this->WCharType = this->UnsignedShort;
}
+ this->UseZeroLengthBitfieldAlignment = true;
+ }
- if (Opts.MicrosoftExt) {
- Builder.defineMacro("_MSC_EXTENSIONS");
+ // AIX sets FLT_EVAL_METHOD to be 1.
+ unsigned getFloatEvalMethod() const override { return 1; }
+ bool hasInt128Type() const override { return false; }
+};
- if (Opts.CPlusPlus11) {
- Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
- Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
- Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
- }
- }
+void addWindowsDefines(const llvm::Triple &Triple, const LangOptions &Opts,
+ MacroBuilder &Builder);
- Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
+// Windows target
+template <typename Target>
+class LLVM_LIBRARY_VISIBILITY WindowsTargetInfo : public OSTargetInfo<Target> {
+protected:
+ void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
+ MacroBuilder &Builder) const override {
+ addWindowsDefines(Triple, Opts, Builder);
}
public:
@@ -764,14 +806,17 @@ public:
template <typename Target>
class LLVM_LIBRARY_VISIBILITY WebAssemblyOSTargetInfo
: public OSTargetInfo<Target> {
+protected:
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
- MacroBuilder &Builder) const final {
+ MacroBuilder &Builder) const {
// A common platform macro.
if (Opts.POSIXThreads)
Builder.defineMacro("_REENTRANT");
// Follow g++ convention and predefine _GNU_SOURCE for C++.
if (Opts.CPlusPlus)
Builder.defineMacro("_GNU_SOURCE");
+ // Indicate that we have __float128.
+ Builder.defineMacro("__FLOAT128__");
}
public:
@@ -780,7 +825,38 @@ public:
: OSTargetInfo<Target>(Triple, Opts) {
this->MCountName = "__mcount";
this->TheCXXABI.set(TargetCXXABI::WebAssembly);
+ this->HasFloat128 = true;
+ }
+};
+
+// WASI target
+template <typename Target>
+class LLVM_LIBRARY_VISIBILITY WASITargetInfo
+ : public WebAssemblyOSTargetInfo<Target> {
+ void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
+ MacroBuilder &Builder) const final {
+ WebAssemblyOSTargetInfo<Target>::getOSDefines(Opts, Triple, Builder);
+ Builder.defineMacro("__wasi__");
}
+
+public:
+ explicit WASITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
+ : WebAssemblyOSTargetInfo<Target>(Triple, Opts) {}
+};
+
+// Emscripten target
+template <typename Target>
+class LLVM_LIBRARY_VISIBILITY EmscriptenTargetInfo
+ : public WebAssemblyOSTargetInfo<Target> {
+ void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
+ MacroBuilder &Builder) const final {
+ WebAssemblyOSTargetInfo<Target>::getOSDefines(Opts, Triple, Builder);
+ Builder.defineMacro("__EMSCRIPTEN__");
+ }
+
+public:
+ explicit EmscriptenTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
+ : WebAssemblyOSTargetInfo<Target>(Triple, Opts) {}
};
} // namespace targets
diff --git a/lib/Basic/Targets/PNaCl.cpp b/lib/Basic/Targets/PNaCl.cpp
index b9128c2716e8..60e9467193a8 100644
--- a/lib/Basic/Targets/PNaCl.cpp
+++ b/lib/Basic/Targets/PNaCl.cpp
@@ -1,9 +1,8 @@
//===--- PNaCl.cpp - Implement PNaCl target feature support ---------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/PNaCl.h b/lib/Basic/Targets/PNaCl.h
index 922944e85ca2..ab4abf9fc567 100644
--- a/lib/Basic/Targets/PNaCl.h
+++ b/lib/Basic/Targets/PNaCl.h
@@ -1,9 +1,8 @@
//===--- PNaCl.h - Declare PNaCl target feature support ---------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/PPC.cpp b/lib/Basic/Targets/PPC.cpp
index 6cfbed1713e1..2a773d999286 100644
--- a/lib/Basic/Targets/PPC.cpp
+++ b/lib/Basic/Targets/PPC.cpp
@@ -1,9 +1,8 @@
//===--- PPC.cpp - Implement PPC target feature support -------------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -31,6 +30,7 @@ const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
/// configured set of features.
bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) {
+ FloatABI = HardFloat;
for (const auto &Feature : Features) {
if (Feature == "+altivec") {
HasAltivec = true;
@@ -54,6 +54,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasFloat128 = true;
} else if (Feature == "+power9-vector") {
HasP9Vector = true;
+ } else if (Feature == "-hard-float") {
+ FloatABI = SoftFloat;
}
// TODO: Finish this list and add an assert that we've handled them
// all.
@@ -101,7 +103,9 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("_CALL_LINUX", "1");
// Subtarget options.
- Builder.defineMacro("__NATURAL_ALIGNMENT__");
+ if (!getTriple().isOSAIX()){
+ Builder.defineMacro("__NATURAL_ALIGNMENT__");
+ }
Builder.defineMacro("__REGISTER_PREFIX__", "");
// FIXME: Should be controlled by command line option.
@@ -213,31 +217,26 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector<std::string> &FeaturesVec) {
- if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
- FeaturesVec.end()) {
- if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
- FeaturesVec.end()) {
+ if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
+ if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
<< "-mno-vsx";
return false;
}
- if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
- FeaturesVec.end()) {
+ if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
<< "-mno-vsx";
return false;
}
- if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
- FeaturesVec.end()) {
+ if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
<< "-mno-vsx";
return false;
}
- if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") !=
- FeaturesVec.end()) {
+ if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
<< "-mno-vsx";
return false;
@@ -310,8 +309,7 @@ bool PPCTargetInfo::initFeatureMap(
return false;
if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
- std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") !=
- FeaturesVec.end()) {
+ llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
// We have __float128 on PPC but not power 9 and above.
Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
return false;
@@ -467,6 +465,10 @@ void PPCTargetInfo::adjust(LangOptions &Opts) {
if (HasAltivec)
Opts.AltiVec = 1;
TargetInfo::adjust(Opts);
+ if (LongDoubleFormat != &llvm::APFloat::IEEEdouble())
+ LongDoubleFormat = Opts.PPCIEEELongDouble
+ ? &llvm::APFloat::IEEEquad()
+ : &llvm::APFloat::PPCDoubleDouble();
}
ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
diff --git a/lib/Basic/Targets/PPC.h b/lib/Basic/Targets/PPC.h
index 058970a0e098..6e5df097921b 100644
--- a/lib/Basic/Targets/PPC.h
+++ b/lib/Basic/Targets/PPC.h
@@ -1,9 +1,8 @@
//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -54,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
static const char *const GCCRegNames[];
static const TargetInfo::GCCRegAlias GCCRegAliases[];
std::string CPU;
+ enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
// Target cpu features.
bool HasAltivec = false;
@@ -132,19 +132,18 @@ public:
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
ArchDefinePpcsq)
.Cases("power7", "pwr7",
- ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 |
- ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
- ArchDefinePpcgr | ArchDefinePpcsq)
+ ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
+ ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
+ ArchDefinePpcsq)
// powerpc64le automatically defaults to at least power8.
.Cases("power8", "pwr8", "ppc64le",
- ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x |
- ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
- ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+ ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
+ ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
+ ArchDefinePpcgr | ArchDefinePpcsq)
.Cases("power9", "pwr9",
- ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
- ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
- ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
- ArchDefinePpcsq)
+ ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
+ ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
+ ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
.Default(ArchDefineNone);
}
return CPUKnown;
@@ -185,8 +184,12 @@ public:
return false;
case 'O': // Zero
break;
- case 'b': // Base register
case 'f': // Floating point register
+ // Don't use floating point registers on soft float ABI.
+ if (FloatABI == SoftFloat)
+ return false;
+ LLVM_FALLTHROUGH;
+ case 'b': // Base register
Info.setAllowsRegister();
break;
// FIXME: The following are added to allow parsing.
@@ -194,13 +197,18 @@ public:
// Also, is more specific checking needed? I.e. specific registers?
case 'd': // Floating point register (containing 64-bit value)
case 'v': // Altivec vector register
+ // Don't use floating point and altivec vector registers
+ // on soft float ABI
+ if (FloatABI == SoftFloat)
+ return false;
Info.setAllowsRegister();
break;
case 'w':
switch (Name[1]) {
case 'd': // VSX vector register to hold vector double data
case 'f': // VSX vector register to hold vector float data
- case 's': // VSX vector register to hold scalar float data
+ case 's': // VSX vector register to hold scalar double data
+ case 'w': // VSX vector register to hold scalar double data
case 'a': // Any VSX register
case 'c': // An individual CR bit
case 'i': // FP or VSX register to hold 64-bit integers data
@@ -306,11 +314,14 @@ public:
bool hasSjLjLowering() const override { return true; }
- bool useFloat128ManglingForLongDouble() const override {
- return LongDoubleWidth == 128 &&
- LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() &&
- getTriple().isOSBinFormatELF();
+ const char *getLongDoubleMangling() const override {
+ if (LongDoubleWidth == 64)
+ return "e";
+ return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
+ ? "g"
+ : "u9__ieee128";
}
+ const char *getFloat128Mangling() const override { return "u9__ieee128"; }
};
class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
@@ -327,11 +338,18 @@ public:
PtrDiffType = SignedInt;
IntPtrType = SignedInt;
break;
+ case llvm::Triple::AIX:
+ SizeType = UnsignedLong;
+ PtrDiffType = SignedLong;
+ IntPtrType = SignedLong;
+ SuitableAlign = 64;
+ break;
default:
break;
}
- if (getTriple().isOSFreeBSD()) {
+ if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
+ Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) {
LongDoubleWidth = LongDoubleAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
}
@@ -361,16 +379,16 @@ public:
ABI = "elfv2";
} else {
resetDataLayout("E-m:e-i64:64-n32:64");
- ABI = "elfv1";
+ ABI = Triple.getEnvironment() == llvm::Triple::ELFv2 ? "elfv2" : "elfv1";
}
- switch (getTriple().getOS()) {
- case llvm::Triple::FreeBSD:
+ if (Triple.getOS() == llvm::Triple::AIX)
+ SuitableAlign = 64;
+
+ if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX ||
+ Triple.isMusl()) {
LongDoubleWidth = LongDoubleAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
- break;
- default:
- break;
}
// PPC64 supports atomics up to 8 bytes.
@@ -427,6 +445,21 @@ public:
}
};
+class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
+ public AIXTargetInfo<PPC32TargetInfo> {
+public:
+ using AIXTargetInfo::AIXTargetInfo;
+ BuiltinVaListKind getBuiltinVaListKind() const override {
+ return TargetInfo::CharPtrBuiltinVaList;
+ }
+};
+
+class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
+ public AIXTargetInfo<PPC64TargetInfo> {
+public:
+ using AIXTargetInfo::AIXTargetInfo;
+};
+
} // namespace targets
} // namespace clang
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
diff --git a/lib/Basic/Targets/RISCV.cpp b/lib/Basic/Targets/RISCV.cpp
index 7eb5e6a686a9..f800bb0b25da 100644
--- a/lib/Basic/Targets/RISCV.cpp
+++ b/lib/Basic/Targets/RISCV.cpp
@@ -1,9 +1,8 @@
//===--- RISCV.cpp - Implement RISCV target feature support ---------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -32,7 +31,7 @@ ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
{{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"},
{{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"},
{{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
- {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x15"}, {{"a5"}, "x15"},
+ {{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
{{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
{{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
{{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
@@ -40,6 +39,26 @@ ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
return llvm::makeArrayRef(GCCRegAliases);
}
+bool RISCVTargetInfo::validateAsmConstraint(
+ const char *&Name, TargetInfo::ConstraintInfo &Info) const {
+ switch (*Name) {
+ default:
+ return false;
+ case 'I':
+ // A 12-bit signed immediate.
+ Info.setRequiresImmediate(-2048, 2047);
+ return true;
+ case 'J':
+ // Integer zero.
+ Info.setRequiresImmediate(0);
+ return true;
+ case 'K':
+ // A 5-bit unsigned immediate for CSR access instructions.
+ Info.setRequiresImmediate(0, 31);
+ return true;
+ }
+}
+
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ELF__");
diff --git a/lib/Basic/Targets/RISCV.h b/lib/Basic/Targets/RISCV.h
index f83aae539391..bc814b79ce51 100644
--- a/lib/Basic/Targets/RISCV.h
+++ b/lib/Basic/Targets/RISCV.h
@@ -1,9 +1,8 @@
//===--- RISCV.h - Declare RISCV target feature support ---------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -36,7 +35,6 @@ public:
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
HasD(false), HasC(false) {
- TLSSupported = false;
LongDoubleWidth = 128;
LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad();
@@ -59,12 +57,19 @@ public:
ArrayRef<const char *> getGCCRegNames() const override;
+ int getEHDataRegisterNumber(unsigned RegNo) const override {
+ if (RegNo == 0)
+ return 10;
+ else if (RegNo == 1)
+ return 11;
+ else
+ return -1;
+ }
+
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const override {
- return false;
- }
+ TargetInfo::ConstraintInfo &Info) const override;
bool hasFeature(StringRef Feature) const override;
diff --git a/lib/Basic/Targets/SPIR.cpp b/lib/Basic/Targets/SPIR.cpp
index 304d904368ca..a9b815d13bc1 100644
--- a/lib/Basic/Targets/SPIR.cpp
+++ b/lib/Basic/Targets/SPIR.cpp
@@ -1,9 +1,8 @@
//===--- SPIR.cpp - Implement SPIR target feature support -----------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/SPIR.h b/lib/Basic/Targets/SPIR.h
index 9815292fc276..6023c868dbdc 100644
--- a/lib/Basic/Targets/SPIR.h
+++ b/lib/Basic/Targets/SPIR.h
@@ -1,9 +1,8 @@
//===--- SPIR.h - Declare SPIR target feature support -----------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -48,6 +47,7 @@ public:
AddrSpaceMap = &SPIRAddrSpaceMap;
UseAddrSpaceMapMangling = true;
HasLegalHalfType = true;
+ HasFloat16 = true;
// Define available target features
// These must be defined in sorted order!
NoAsmVariants = true;
diff --git a/lib/Basic/Targets/Sparc.cpp b/lib/Basic/Targets/Sparc.cpp
index ee4f309363af..13aa964d4716 100644
--- a/lib/Basic/Targets/Sparc.cpp
+++ b/lib/Basic/Targets/Sparc.cpp
@@ -1,9 +1,8 @@
//===--- Sparc.cpp - Implement Sparc target feature support ---------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/Sparc.h b/lib/Basic/Targets/Sparc.h
index 5ae305bffb43..963192a4634f 100644
--- a/lib/Basic/Targets/Sparc.h
+++ b/lib/Basic/Targets/Sparc.h
@@ -1,9 +1,8 @@
//===--- Sparc.h - declare sparc target feature support ---------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -40,7 +39,7 @@ public:
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override {
// Check if software floating point is enabled
- auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
+ auto Feature = llvm::find(Features, "+soft-float");
if (Feature != Features.end()) {
SoftFloat = true;
}
diff --git a/lib/Basic/Targets/SystemZ.cpp b/lib/Basic/Targets/SystemZ.cpp
index 6f06f1fc760c..d86928a6333b 100644
--- a/lib/Basic/Targets/SystemZ.cpp
+++ b/lib/Basic/Targets/SystemZ.cpp
@@ -1,9 +1,8 @@
//===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -92,7 +91,8 @@ static constexpr ISANameRevision ISARevisions[] = {
{{"arch9"}, 9}, {{"z196"}, 9},
{{"arch10"}, 10}, {{"zEC12"}, 10},
{{"arch11"}, 11}, {{"z13"}, 11},
- {{"arch12"}, 12}, {{"z14"}, 12}
+ {{"arch12"}, 12}, {{"z14"}, 12},
+ {{"arch13"}, 13},
};
int SystemZTargetInfo::getISARevision(StringRef Name) const {
@@ -119,6 +119,7 @@ bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
.Case("arch10", ISARevision >= 10)
.Case("arch11", ISARevision >= 11)
.Case("arch12", ISARevision >= 12)
+ .Case("arch13", ISARevision >= 13)
.Case("htm", HasTransactionalExecution)
.Case("vx", HasVector)
.Default(false);
@@ -143,7 +144,7 @@ void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasVector)
Builder.defineMacro("__VX__");
if (Opts.ZVector)
- Builder.defineMacro("__VEC__", "10302");
+ Builder.defineMacro("__VEC__", "10303");
}
ArrayRef<Builtin::Info> SystemZTargetInfo::getTargetBuiltins() const {
diff --git a/lib/Basic/Targets/SystemZ.h b/lib/Basic/Targets/SystemZ.h
index 842316005ed9..e751806f4747 100644
--- a/lib/Basic/Targets/SystemZ.h
+++ b/lib/Basic/Targets/SystemZ.h
@@ -1,9 +1,8 @@
//===--- SystemZ.h - Declare SystemZ target feature support -----*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -101,6 +100,8 @@ public:
Features["vector"] = true;
if (ISARevision >= 12)
Features["vector-enhancements-1"] = true;
+ if (ISARevision >= 13)
+ Features["vector-enhancements-2"] = true;
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
@@ -142,7 +143,7 @@ public:
return "";
}
- bool useFloat128ManglingForLongDouble() const override { return true; }
+ const char *getLongDoubleMangling() const override { return "g"; }
};
} // namespace targets
} // namespace clang
diff --git a/lib/Basic/Targets/TCE.cpp b/lib/Basic/Targets/TCE.cpp
index bf89c1dc549e..91194b568a09 100644
--- a/lib/Basic/Targets/TCE.cpp
+++ b/lib/Basic/Targets/TCE.cpp
@@ -1,9 +1,8 @@
//===--- TCE.cpp - Implement TCE target feature support -------------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/TCE.h b/lib/Basic/Targets/TCE.h
index be43bed98d80..967ef5c59ee5 100644
--- a/lib/Basic/Targets/TCE.h
+++ b/lib/Basic/Targets/TCE.h
@@ -1,9 +1,8 @@
//===--- TCE.h - Declare TCE target feature support -------------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/WebAssembly.cpp b/lib/Basic/Targets/WebAssembly.cpp
index 2fdc84bb8cc8..b16442b99b62 100644
--- a/lib/Basic/Targets/WebAssembly.cpp
+++ b/lib/Basic/Targets/WebAssembly.cpp
@@ -1,9 +1,8 @@
//===--- WebAssembly.cpp - Implement WebAssembly target feature support ---===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -41,6 +40,11 @@ bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const {
.Case("nontrapping-fptoint", HasNontrappingFPToInt)
.Case("sign-ext", HasSignExt)
.Case("exception-handling", HasExceptionHandling)
+ .Case("bulk-memory", HasBulkMemory)
+ .Case("atomics", HasAtomics)
+ .Case("mutable-globals", HasMutableGlobals)
+ .Case("multivalue", HasMultivalue)
+ .Case("tail-call", HasTailCall)
.Default(false);
}
@@ -60,6 +64,22 @@ void WebAssemblyTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__wasm_simd128__");
if (SIMDLevel >= UnimplementedSIMD128)
Builder.defineMacro("__wasm_unimplemented_simd128__");
+ if (HasNontrappingFPToInt)
+ Builder.defineMacro("__wasm_nontrapping_fptoint__");
+ if (HasSignExt)
+ Builder.defineMacro("__wasm_sign_ext__");
+ if (HasExceptionHandling)
+ Builder.defineMacro("__wasm_exception_handling__");
+ if (HasBulkMemory)
+ Builder.defineMacro("__wasm_bulk_memory__");
+ if (HasAtomics)
+ Builder.defineMacro("__wasm_atomics__");
+ if (HasMutableGlobals)
+ Builder.defineMacro("__wasm_mutable_globals__");
+ if (HasMultivalue)
+ Builder.defineMacro("__wasm_multivalue__");
+ if (HasTailCall)
+ Builder.defineMacro("__wasm_tail_call__");
}
void WebAssemblyTargetInfo::setSIMDLevel(llvm::StringMap<bool> &Features,
@@ -82,6 +102,8 @@ bool WebAssemblyTargetInfo::initFeatureMap(
if (CPU == "bleeding-edge") {
Features["nontrapping-fptoint"] = true;
Features["sign-ext"] = true;
+ Features["atomics"] = true;
+ Features["mutable-globals"] = true;
setSIMDLevel(Features, SIMD128);
}
// Other targets do not consider user-configured features here, but while we
@@ -94,6 +116,16 @@ bool WebAssemblyTargetInfo::initFeatureMap(
Features["sign-ext"] = true;
if (HasExceptionHandling)
Features["exception-handling"] = true;
+ if (HasBulkMemory)
+ Features["bulk-memory"] = true;
+ if (HasAtomics)
+ Features["atomics"] = true;
+ if (HasMutableGlobals)
+ Features["mutable-globals"] = true;
+ if (HasMultivalue)
+ Features["multivalue"] = true;
+ if (HasTailCall)
+ Features["tail-call"] = true;
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
@@ -141,6 +173,46 @@ bool WebAssemblyTargetInfo::handleTargetFeatures(
HasExceptionHandling = false;
continue;
}
+ if (Feature == "+bulk-memory") {
+ HasBulkMemory = true;
+ continue;
+ }
+ if (Feature == "-bulk-memory") {
+ HasBulkMemory = false;
+ continue;
+ }
+ if (Feature == "+atomics") {
+ HasAtomics = true;
+ continue;
+ }
+ if (Feature == "-atomics") {
+ HasAtomics = false;
+ continue;
+ }
+ if (Feature == "+mutable-globals") {
+ HasMutableGlobals = true;
+ continue;
+ }
+ if (Feature == "-mutable-globals") {
+ HasMutableGlobals = false;
+ continue;
+ }
+ if (Feature == "+multivalue") {
+ HasMultivalue = true;
+ continue;
+ }
+ if (Feature == "-multivalue") {
+ HasMultivalue = false;
+ continue;
+ }
+ if (Feature == "+tail-call") {
+ HasTailCall = true;
+ continue;
+ }
+ if (Feature == "-tail-call") {
+ HasTailCall = false;
+ continue;
+ }
Diags.Report(diag::err_opt_not_valid_with_opt)
<< Feature << "-target-feature";
diff --git a/lib/Basic/Targets/WebAssembly.h b/lib/Basic/Targets/WebAssembly.h
index 3dea9a373cb4..9665156b143f 100644
--- a/lib/Basic/Targets/WebAssembly.h
+++ b/lib/Basic/Targets/WebAssembly.h
@@ -1,9 +1,8 @@
//=== WebAssembly.h - Declare WebAssembly target feature support *- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -31,14 +30,18 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public TargetInfo {
UnimplementedSIMD128,
} SIMDLevel = NoSIMD;
- bool HasNontrappingFPToInt;
- bool HasSignExt;
- bool HasExceptionHandling;
+ bool HasNontrappingFPToInt = false;
+ bool HasSignExt = false;
+ bool HasExceptionHandling = false;
+ bool HasBulkMemory = false;
+ bool HasAtomics = false;
+ bool HasMutableGlobals = false;
+ bool HasMultivalue = false;
+ bool HasTailCall = false;
public:
explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &)
- : TargetInfo(T), SIMDLevel(NoSIMD), HasNontrappingFPToInt(false),
- HasSignExt(false), HasExceptionHandling(false) {
+ : TargetInfo(T) {
NoAsmVariants = true;
SuitableAlign = 128;
LargeArrayMinWidth = 128;
diff --git a/lib/Basic/Targets/X86.cpp b/lib/Basic/Targets/X86.cpp
index 53b4c153e952..d618c90b05c0 100644
--- a/lib/Basic/Targets/X86.cpp
+++ b/lib/Basic/Targets/X86.cpp
@@ -1,9 +1,8 @@
//===--- X86.cpp - Implement X86 target feature support -------------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -116,6 +115,11 @@ bool X86TargetInfo::initFeatureMap(
if (Kind != CK_Lakemont)
setFeatureEnabledImpl(Features, "x87", true);
+ // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards
+ // compatibility.
+ if (Kind >= CK_i586 || Kind == CK_Generic)
+ setFeatureEnabledImpl(Features, "cx8", true);
+
switch (Kind) {
case CK_Generic:
case CK_i386:
@@ -123,6 +127,7 @@ bool X86TargetInfo::initFeatureMap(
case CK_i586:
case CK_Pentium:
case CK_PentiumPro:
+ case CK_i686:
case CK_Lakemont:
break;
@@ -133,6 +138,25 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "mmx", true);
break;
+ case CK_Cooperlake:
+ // CPX inherits all CLX features plus AVX512BF16
+ setFeatureEnabledImpl(Features, "avx512bf16", true);
+ LLVM_FALLTHROUGH;
+ case CK_Cascadelake:
+ // CLX inherits all SKX features plus AVX512VNNI
+ setFeatureEnabledImpl(Features, "avx512vnni", true);
+ LLVM_FALLTHROUGH;
+ case CK_SkylakeServer:
+ setFeatureEnabledImpl(Features, "avx512f", true);
+ setFeatureEnabledImpl(Features, "avx512cd", true);
+ setFeatureEnabledImpl(Features, "avx512dq", true);
+ setFeatureEnabledImpl(Features, "avx512bw", true);
+ setFeatureEnabledImpl(Features, "avx512vl", true);
+ setFeatureEnabledImpl(Features, "clwb", true);
+ setFeatureEnabledImpl(Features, "pku", true);
+ // SkylakeServer cores inherits all SKL features, except SGX
+ goto SkylakeCommon;
+
case CK_IcelakeServer:
setFeatureEnabledImpl(Features, "pconfig", true);
setFeatureEnabledImpl(Features, "wbnoinvd", true);
@@ -143,38 +167,29 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "vpclmulqdq", true);
setFeatureEnabledImpl(Features, "avx512bitalg", true);
setFeatureEnabledImpl(Features, "avx512vbmi2", true);
+ setFeatureEnabledImpl(Features, "avx512vnni", true);
setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
setFeatureEnabledImpl(Features, "rdpid", true);
+ setFeatureEnabledImpl(Features, "clwb", true);
LLVM_FALLTHROUGH;
case CK_Cannonlake:
- setFeatureEnabledImpl(Features, "avx512ifma", true);
- setFeatureEnabledImpl(Features, "avx512vbmi", true);
- setFeatureEnabledImpl(Features, "sha", true);
- LLVM_FALLTHROUGH;
- case CK_Cascadelake:
- //Cannonlake has no VNNI feature inside while Icelake has
- if (Kind != CK_Cannonlake)
- // CLK inherits all SKX features plus AVX512_VNNI
- setFeatureEnabledImpl(Features, "avx512vnni", true);
- LLVM_FALLTHROUGH;
- case CK_SkylakeServer:
setFeatureEnabledImpl(Features, "avx512f", true);
setFeatureEnabledImpl(Features, "avx512cd", true);
setFeatureEnabledImpl(Features, "avx512dq", true);
setFeatureEnabledImpl(Features, "avx512bw", true);
setFeatureEnabledImpl(Features, "avx512vl", true);
+ setFeatureEnabledImpl(Features, "avx512ifma", true);
+ setFeatureEnabledImpl(Features, "avx512vbmi", true);
setFeatureEnabledImpl(Features, "pku", true);
- if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
- setFeatureEnabledImpl(Features, "clwb", true);
+ setFeatureEnabledImpl(Features, "sha", true);
LLVM_FALLTHROUGH;
case CK_SkylakeClient:
+ setFeatureEnabledImpl(Features, "sgx", true);
+ // SkylakeServer cores inherits all SKL features, except SGX
+SkylakeCommon:
setFeatureEnabledImpl(Features, "xsavec", true);
setFeatureEnabledImpl(Features, "xsaves", true);
setFeatureEnabledImpl(Features, "mpx", true);
- if (Kind != CK_SkylakeServer
- && Kind != CK_Cascadelake)
- // SKX/CLX inherits all SKL features, except SGX
- setFeatureEnabledImpl(Features, "sgx", true);
setFeatureEnabledImpl(Features, "clflushopt", true);
setFeatureEnabledImpl(Features, "aes", true);
LLVM_FALLTHROUGH;
@@ -215,11 +230,12 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "ssse3", true);
setFeatureEnabledImpl(Features, "sahf", true);
LLVM_FALLTHROUGH;
+ case CK_Nocona:
+ setFeatureEnabledImpl(Features, "cx16", true);
+ LLVM_FALLTHROUGH;
case CK_Yonah:
case CK_Prescott:
- case CK_Nocona:
setFeatureEnabledImpl(Features, "sse3", true);
- setFeatureEnabledImpl(Features, "cx16", true);
LLVM_FALLTHROUGH;
case CK_PentiumM:
case CK_Pentium4:
@@ -348,6 +364,11 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "sahf", true);
break;
+ case CK_ZNVER2:
+ setFeatureEnabledImpl(Features, "clwb", true);
+ setFeatureEnabledImpl(Features, "rdpid", true);
+ setFeatureEnabledImpl(Features, "wbnoinvd", true);
+ LLVM_FALLTHROUGH;
case CK_ZNVER1:
setFeatureEnabledImpl(Features, "adx", true);
setFeatureEnabledImpl(Features, "aes", true);
@@ -416,23 +437,20 @@ bool X86TargetInfo::initFeatureMap(
// Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
auto I = Features.find("sse4.2");
if (I != Features.end() && I->getValue() &&
- std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
- FeaturesVec.end())
+ llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end())
Features["popcnt"] = true;
// Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
I = Features.find("3dnow");
if (I != Features.end() && I->getValue() &&
- std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
- FeaturesVec.end())
+ llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end())
Features["prfchw"] = true;
// Additionally, if SSE is enabled and mmx is not explicitly disabled,
// then enable MMX.
I = Features.find("sse");
if (I != Features.end() && I->getValue() &&
- std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
- FeaturesVec.end())
+ llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end())
Features["mmx"] = true;
return true;
@@ -443,7 +461,9 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
if (Enabled) {
switch (Level) {
case AVX512F:
- Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
+ Features["avx512f"] = true;
+ Features["fma"] = true;
+ Features["f16c"] = true;
LLVM_FALLTHROUGH;
case AVX2:
Features["avx2"] = true;
@@ -482,8 +502,8 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
Features["sse"] = false;
LLVM_FALLTHROUGH;
case SSE2:
- Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
- Features["gfni"] = false;
+ Features["sse2"] = Features["pclmul"] = Features["aes"] = false;
+ Features["sha"] = Features["gfni"] = false;
LLVM_FALLTHROUGH;
case SSE3:
Features["sse3"] = false;
@@ -499,20 +519,22 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
Features["sse4.2"] = false;
LLVM_FALLTHROUGH;
case AVX:
- Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
- Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
+ Features["fma"] = Features["avx"] = Features["f16c"] = false;
+ Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false;
+ Features["vpclmulqdq"] = false;
setXOPLevel(Features, FMA4, false);
LLVM_FALLTHROUGH;
case AVX2:
Features["avx2"] = false;
LLVM_FALLTHROUGH;
case AVX512F:
- Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
- Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
- Features["avx512vl"] = Features["avx512vbmi"] =
- Features["avx512ifma"] = Features["avx512vpopcntdq"] =
- Features["avx512bitalg"] = Features["avx512vnni"] =
- Features["avx512vbmi2"] = false;
+ Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false;
+ Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false;
+ Features["avx512vl"] = Features["avx512vbmi"] = false;
+ Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
+ Features["avx512bitalg"] = Features["avx512vnni"] = false;
+ Features["avx512vbmi2"] = Features["avx512bf16"] = false;
+ Features["avx512vp2intersect"] = false;
break;
}
}
@@ -640,20 +662,20 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
setSSELevel(Features, AVX2, Enabled);
} else if (Name == "avx512f") {
setSSELevel(Features, AVX512F, Enabled);
- } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
- Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
- Name == "avx512vbmi" || Name == "avx512ifma" ||
- Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
- Name == "avx512vnni" || Name == "avx512vbmi2") {
+ } else if (Name.startswith("avx512")) {
if (Enabled)
setSSELevel(Features, AVX512F, Enabled);
- // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
- if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
+ // Enable BWI instruction if certain features are being enabled.
+ if ((Name == "avx512vbmi" || Name == "avx512vbmi2" ||
+ Name == "avx512bitalg" || Name == "avx512bf16") && Enabled)
Features["avx512bw"] = true;
- // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
- if (Name == "avx512bw" && !Enabled)
- Features["avx512vbmi"] = Features["avx512vbmi2"] =
+ // Also disable some features if BWI is being disabled.
+ if (Name == "avx512bw" && !Enabled) {
+ Features["avx512vbmi"] = false;
+ Features["avx512vbmi2"] = false;
Features["avx512bitalg"] = false;
+ Features["avx512bf16"] = false;
+ }
} else if (Name == "fma") {
if (Enabled)
setSSELevel(Features, AVX, Enabled);
@@ -743,6 +765,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasAVX512VPOPCNTDQ = true;
} else if (Feature == "+avx512vnni") {
HasAVX512VNNI = true;
+ } else if (Feature == "+avx512bf16") {
+ HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
} else if (Feature == "+avx512pf") {
@@ -761,6 +785,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasAVX512VBMI2 = true;
} else if (Feature == "+avx512ifma") {
HasAVX512IFMA = true;
+ } else if (Feature == "+avx512vp2intersect") {
+ HasAVX512VP2INTERSECT = true;
} else if (Feature == "+sha") {
HasSHA = true;
} else if (Feature == "+mpx") {
@@ -771,6 +797,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasMOVBE = true;
} else if (Feature == "+sgx") {
HasSGX = true;
+ } else if (Feature == "+cx8") {
+ HasCX8 = true;
} else if (Feature == "+cx16") {
HasCX16 = true;
} else if (Feature == "+fxsr") {
@@ -817,6 +845,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasPTWRITE = true;
} else if (Feature == "+invpcid") {
HasINVPCID = true;
+ } else if (Feature == "+enqcmd") {
+ HasENQCMD = true;
}
X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
@@ -865,6 +895,9 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
/// definitions for this particular subtarget.
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
+ // Inline assembly supports X86 flag outputs.
+ Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
+
std::string CodeModel = getTargetOpts().CodeModel;
if (CodeModel == "default")
CodeModel = "small";
@@ -884,6 +917,11 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
DefineStd(Builder, "i386", Opts);
}
+ Builder.defineMacro("__SEG_GS");
+ Builder.defineMacro("__SEG_FS");
+ Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
+ Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
+
// Subtarget options.
// FIXME: We are hard-coding the tune parameters based on the CPU, but they
// truly should be based on -mtune options.
@@ -918,6 +956,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__tune_pentium2__");
LLVM_FALLTHROUGH;
case CK_PentiumPro:
+ case CK_i686:
defineCPUMacros(Builder, "i686");
defineCPUMacros(Builder, "pentiumpro");
break;
@@ -957,6 +996,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_SkylakeClient:
case CK_SkylakeServer:
case CK_Cascadelake:
+ case CK_Cooperlake:
case CK_Cannonlake:
case CK_IcelakeClient:
case CK_IcelakeServer:
@@ -1028,6 +1068,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_ZNVER1:
defineCPUMacros(Builder, "znver1");
break;
+ case CK_ZNVER2:
+ defineCPUMacros(Builder, "znver2");
+ break;
case CK_Geode:
defineCPUMacros(Builder, "geode");
break;
@@ -1124,6 +1167,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__AVX512VPOPCNTDQ__");
if (HasAVX512VNNI)
Builder.defineMacro("__AVX512VNNI__");
+ if (HasAVX512BF16)
+ Builder.defineMacro("__AVX512BF16__");
if (HasAVX512ER)
Builder.defineMacro("__AVX512ER__");
if (HasAVX512PF)
@@ -1142,7 +1187,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__AVX512VBMI2__");
if (HasAVX512IFMA)
Builder.defineMacro("__AVX512IFMA__");
-
+ if (HasAVX512VP2INTERSECT)
+ Builder.defineMacro("__AVX512VP2INTERSECT__");
if (HasSHA)
Builder.defineMacro("__SHA__");
@@ -1190,6 +1236,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__PTWRITE__");
if (HasINVPCID)
Builder.defineMacro("__INVPCID__");
+ if (HasENQCMD)
+ Builder.defineMacro("__ENQCMD__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1262,14 +1310,14 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
break;
}
- if (CPU >= CK_i486) {
+ if (CPU >= CK_i486 || CPU == CK_Generic) {
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
}
- if (CPU >= CK_i586)
+ if (HasCX8)
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
- if (HasCX16)
+ if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
if (HasFloat128)
@@ -1288,6 +1336,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("avx512cd", true)
.Case("avx512vpopcntdq", true)
.Case("avx512vnni", true)
+ .Case("avx512bf16", true)
.Case("avx512er", true)
.Case("avx512pf", true)
.Case("avx512dq", true)
@@ -1297,6 +1346,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("avx512vbmi", true)
.Case("avx512vbmi2", true)
.Case("avx512ifma", true)
+ .Case("avx512vp2intersect", true)
.Case("bmi", true)
.Case("bmi2", true)
.Case("cldemote", true)
@@ -1304,6 +1354,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("clwb", true)
.Case("clzero", true)
.Case("cx16", true)
+ .Case("enqcmd", true)
.Case("f16c", true)
.Case("fma", true)
.Case("fma4", true)
@@ -1366,6 +1417,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("avx512cd", HasAVX512CD)
.Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
.Case("avx512vnni", HasAVX512VNNI)
+ .Case("avx512bf16", HasAVX512BF16)
.Case("avx512er", HasAVX512ER)
.Case("avx512pf", HasAVX512PF)
.Case("avx512dq", HasAVX512DQ)
@@ -1375,13 +1427,16 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("avx512vbmi", HasAVX512VBMI)
.Case("avx512vbmi2", HasAVX512VBMI2)
.Case("avx512ifma", HasAVX512IFMA)
+ .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
.Case("bmi", HasBMI)
.Case("bmi2", HasBMI2)
.Case("cldemote", HasCLDEMOTE)
.Case("clflushopt", HasCLFLUSHOPT)
.Case("clwb", HasCLWB)
.Case("clzero", HasCLZERO)
+ .Case("cx8", HasCX8)
.Case("cx16", HasCX16)
+ .Case("enqcmd", HasENQCMD)
.Case("f16c", HasF16C)
.Case("fma", HasFMA)
.Case("fma4", XOPLevel >= FMA4)
@@ -1527,18 +1582,6 @@ void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
}
-std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const {
- switch (Kind) {
- case CK_Generic:
- return "";
-#define PROC(ENUM, STRING, IS64BIT) \
- case CK_##ENUM: \
- return STRING;
-#include "clang/Basic/X86Target.def"
- }
- llvm_unreachable("Invalid CPUKind");
-}
-
// We can't use a generic validation scheme for the cpus accepted here
// versus subtarget cpus accepted in the target attribute because the
// variables intitialized by the runtime only support the below currently
@@ -1554,6 +1597,40 @@ bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
.Default(false);
}
+static unsigned matchAsmCCConstraint(const char *&Name) {
+ auto RV = llvm::StringSwitch<unsigned>(Name)
+ .Case("@cca", 4)
+ .Case("@ccae", 5)
+ .Case("@ccb", 4)
+ .Case("@ccbe", 5)
+ .Case("@ccc", 4)
+ .Case("@cce", 4)
+ .Case("@ccz", 4)
+ .Case("@ccg", 4)
+ .Case("@ccge", 5)
+ .Case("@ccl", 4)
+ .Case("@ccle", 5)
+ .Case("@ccna", 5)
+ .Case("@ccnae", 6)
+ .Case("@ccnb", 5)
+ .Case("@ccnbe", 6)
+ .Case("@ccnc", 5)
+ .Case("@ccne", 5)
+ .Case("@ccnz", 5)
+ .Case("@ccng", 5)
+ .Case("@ccnge", 6)
+ .Case("@ccnl", 5)
+ .Case("@ccnle", 6)
+ .Case("@ccno", 5)
+ .Case("@ccnp", 5)
+ .Case("@ccns", 5)
+ .Case("@cco", 4)
+ .Case("@ccp", 4)
+ .Case("@ccs", 4)
+ .Default(0);
+ return RV;
+}
+
bool X86TargetInfo::validateAsmConstraint(
const char *&Name, TargetInfo::ConstraintInfo &Info) const {
switch (*Name) {
@@ -1636,6 +1713,14 @@ bool X86TargetInfo::validateAsmConstraint(
case 'C': // SSE floating point constant.
case 'G': // x87 floating point constant.
return true;
+ case '@':
+ // CC condition changes.
+ if (auto Len = matchAsmCCConstraint(Name)) {
+ Name += Len - 1;
+ Info.setAllowsRegister();
+ return true;
+ }
+ return false;
}
}
@@ -1707,6 +1792,13 @@ bool X86TargetInfo::validateOperandSize(StringRef Constraint,
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
switch (*Constraint) {
+ case '@':
+ if (auto Len = matchAsmCCConstraint(Constraint)) {
+ std::string Converted = "{" + std::string(Constraint, Len) + "}";
+ Constraint += Len - 1;
+ return Converted;
+ }
+ return std::string(1, *Constraint);
case 'a':
return std::string("{ax}");
case 'b':
@@ -1769,10 +1861,9 @@ void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
#define PROC(ENUM, STRING, IS64BIT) \
if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
Values.emplace_back(STRING);
- // Go through CPUKind checking to ensure that the alias is de-aliased and
- // 64 bit-ness is checked.
+ // For aliases we need to lookup the CPUKind to check get the 64-bit ness.
#define PROC_ALIAS(ENUM, ALIAS) \
- if (checkCPUKind(getCPUKind(ALIAS))) \
+ if (checkCPUKind(CK_##ENUM)) \
Values.emplace_back(ALIAS);
#include "clang/Basic/X86Target.def"
}
diff --git a/lib/Basic/Targets/X86.h b/lib/Basic/Targets/X86.h
index 05930ae9eec0..588b6d3da1d6 100644
--- a/lib/Basic/Targets/X86.h
+++ b/lib/Basic/Targets/X86.h
@@ -1,9 +1,8 @@
//===--- X86.h - Declare X86 target feature support -------------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@@ -69,6 +68,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasAVX512CD = false;
bool HasAVX512VPOPCNTDQ = false;
bool HasAVX512VNNI = false;
+ bool HasAVX512BF16 = false;
bool HasAVX512ER = false;
bool HasAVX512PF = false;
bool HasAVX512DQ = false;
@@ -78,10 +78,12 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasAVX512VBMI = false;
bool HasAVX512VBMI2 = false;
bool HasAVX512IFMA = false;
+ bool HasAVX512VP2INTERSECT = false;
bool HasSHA = false;
bool HasMPX = false;
bool HasSHSTK = false;
bool HasSGX = false;
+ bool HasCX8 = false;
bool HasCX16 = false;
bool HasFXSR = false;
bool HasXSAVE = false;
@@ -106,6 +108,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasMOVDIR64B = false;
bool HasPTWRITE = false;
bool HasINVPCID = false;
+ bool HasENQCMD = false;
protected:
/// Enumeration of all of the X86 CPUs supported by Clang.
@@ -122,8 +125,6 @@ protected:
CPUKind getCPUKind(StringRef CPU) const;
- std::string getCPUKindCanonicalName(CPUKind Kind) const;
-
enum FPMathKind { FP_Default, FP_SSE, FP_387 } FPMath = FP_Default;
public:
@@ -132,6 +133,10 @@ public:
LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
}
+ const char *getLongDoubleMangling() const override {
+ return LongDoubleFormat == &llvm::APFloat::IEEEquad() ? "g" : "e";
+ }
+
unsigned getFloatEvalMethod() const override {
// X87 evaluates with 80 bits "long double" precision.
return SSELevel == NoSSE ? 2 : 0;
@@ -199,7 +204,7 @@ public:
StringRef Expression) const override {
StringRef::iterator I, E;
for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
- if (isalpha(*I))
+ if (isalpha(*I) || *I == '@')
break;
}
if (I == E)
@@ -347,9 +352,8 @@ public:
(1 << TargetInfo::LongDouble));
// x86-32 has atomics up to 8 bytes
- // FIXME: Check that we actually have cmpxchg8b before setting
- // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
- MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+ MaxAtomicPromoteWidth = 64;
+ MaxAtomicInlineWidth = 32;
}
BuiltinVaListKind getBuiltinVaListKind() const override {
@@ -385,6 +389,11 @@ public:
return X86TargetInfo::validateOperandSize(Constraint, Size);
}
+ void setMaxAtomicWidth() override {
+ if (hasFeature("cx8"))
+ MaxAtomicInlineWidth = 64;
+ }
+
ArrayRef<Builtin::Info> getTargetBuiltins() const override;
};
@@ -476,7 +485,6 @@ public:
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
- WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
// The value of the following reflects processor type.
// 300=386, 400=486, 500=Pentium, 600=Blend (default)
// We lost the original triple, so we use the default.
@@ -740,7 +748,6 @@ public:
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
- WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
Builder.defineMacro("_M_X64", "100");
Builder.defineMacro("_M_AMD64", "100");
}
@@ -842,8 +849,6 @@ public:
: LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
LongDoubleFormat = &llvm::APFloat::IEEEquad();
}
-
- bool useFloat128ManglingForLongDouble() const override { return true; }
};
} // namespace targets
} // namespace clang
diff --git a/lib/Basic/Targets/XCore.cpp b/lib/Basic/Targets/XCore.cpp
index 793dca702dae..da614f10e338 100644
--- a/lib/Basic/Targets/XCore.cpp
+++ b/lib/Basic/Targets/XCore.cpp
@@ -1,9 +1,8 @@
//===--- XCore.cpp - Implement XCore target feature support ---------------===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
diff --git a/lib/Basic/Targets/XCore.h b/lib/Basic/Targets/XCore.h
index 346e0eee15b3..c94f93a99bca 100644
--- a/lib/Basic/Targets/XCore.h
+++ b/lib/Basic/Targets/XCore.h
@@ -1,9 +1,8 @@
//===--- XCore.h - Declare XCore target feature support ---------*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//