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authorMarcin Wojtas <mw@FreeBSD.org>2020-11-18 14:30:59 +0000
committerMarcin Wojtas <mw@FreeBSD.org>2020-11-18 14:30:59 +0000
commitd5fc5012bbae5e51a9be9f63372a1ef6fef10371 (patch)
tree3f6ac202c6e8f122208c8bf7eaab5564d2ea914f /ena_com.c
parent73cf51936f0f8f2a5661bf98d34521a7bf8feebd (diff)
downloadsrc-d5fc5012bbae5e51a9be9f63372a1ef6fef10371.tar.gz
src-d5fc5012bbae5e51a9be9f63372a1ef6fef10371.zip
ena-com: Fix ena-com to allocate cdesc aligned to 4kvendor/ena-com/2.2.1
The latest generation hardware requires IO CQ (completion queue) descriptors memory to be aligned to a 4K. It needs that feature for the best performance. Allocating unaligned descriptors will have a big performance impact as the packet processing in a HW won't be optimized properly. It's a critical fix, especially for the arm64 EC2 instances.
Notes
Notes: svn path=/vendor-sys/ena-com/dist/; revision=367793 svn path=/vendor-sys/ena-com/2.2.1/; revision=367794; tag=vendor/ena-com/2.2.1
Diffstat (limited to 'ena_com.c')
-rw-r--r--ena_com.c26
1 files changed, 14 insertions, 12 deletions
diff --git a/ena_com.c b/ena_com.c
index dde0c3357f63..266e39859102 100644
--- a/ena_com.c
+++ b/ena_com.c
@@ -449,19 +449,21 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
io_cq->bus = ena_dev->bus;
- ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
- size,
- io_cq->cdesc_addr.virt_addr,
- io_cq->cdesc_addr.phys_addr,
- io_cq->cdesc_addr.mem_handle,
- ctx->numa_node,
- prev_node);
+ ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(ena_dev->dmadev,
+ size,
+ io_cq->cdesc_addr.virt_addr,
+ io_cq->cdesc_addr.phys_addr,
+ io_cq->cdesc_addr.mem_handle,
+ ctx->numa_node,
+ prev_node,
+ ENA_CDESC_RING_SIZE_ALIGNMENT);
if (!io_cq->cdesc_addr.virt_addr) {
- ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
- size,
- io_cq->cdesc_addr.virt_addr,
- io_cq->cdesc_addr.phys_addr,
- io_cq->cdesc_addr.mem_handle);
+ ENA_MEM_ALLOC_COHERENT_ALIGNED(ena_dev->dmadev,
+ size,
+ io_cq->cdesc_addr.virt_addr,
+ io_cq->cdesc_addr.phys_addr,
+ io_cq->cdesc_addr.mem_handle,
+ ENA_CDESC_RING_SIZE_ALIGNMENT);
}
if (!io_cq->cdesc_addr.virt_addr) {