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authorJuli Mallett <jmallett@FreeBSD.org>2010-07-20 07:11:19 +0000
committerJuli Mallett <jmallett@FreeBSD.org>2010-07-20 07:11:19 +0000
commit1c305b501145f696d3597fb9b5b2091caaa6f67c (patch)
tree776ea14a76df76cd5ee4d9b63107c1e819c68914 /cvmx-csr-db.c
downloadsrc-1c305b501145f696d3597fb9b5b2091caaa6f67c.tar.gz
src-1c305b501145f696d3597fb9b5b2091caaa6f67c.zip
Initial import of Cavium Networks Octeon Simple Executive, SDK version 1.9.0.vendor/octeon-sdk/1.9.0
Notes
Notes: svn path=/vendor-sys/octeon-sdk/dist/; revision=210284 svn path=/vendor-sys/octeon-sdk/1.9.0/; revision=210285; tag=vendor/octeon-sdk/1.9.0
Diffstat (limited to 'cvmx-csr-db.c')
-rw-r--r--cvmx-csr-db.c74292
1 files changed, 74292 insertions, 0 deletions
diff --git a/cvmx-csr-db.c b/cvmx-csr-db.c
new file mode 100644
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+++ b/cvmx-csr-db.c
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+/***********************license start***************
+ * Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of Cavium Networks nor the names of
+ * its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Configuration and status register (CSR) address and type definitions for
+ * Octeon.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx-csr-db.h"
+
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xxp2[] = {
+ /* name , ---------------type, bits, off, #field, fld of */
+ {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
+ {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
+ {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
+ {"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
+ {"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
+ {"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
+ {"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
+ {"cvmx_asx#_rld_fcram_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
+ {"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
+ {"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
+ {"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
+ {"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 29},
+ {"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 31},
+ {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 33},
+ {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 35},
+ {"cvmx_asx#_rx_wol" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 3, 37},
+ {"cvmx_asx#_rx_wol_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 1, 40},
+ {"cvmx_asx#_rx_wol_powok" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 41},
+ {"cvmx_asx#_rx_wol_sig" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 43},
+ {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
+ {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 3, 47},
+ {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 50},
+ {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 52},
+ {"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 3, 54},
+ {"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 2, 57},
+ {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 66, 2, 59},
+ {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 67, 2, 61},
+ {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 68, 2, 63},
+ {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 69, 2, 65},
+ {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 70, 15, 67},
+ {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 103, 2, 82},
+ {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 136, 15, 84},
+ {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 169, 2, 99},
+ {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 2, 101},
+ {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 103},
+ {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 202, 2, 105},
+ {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 203, 2, 107},
+ {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 204, 2, 109},
+ {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 205, 1, 111},
+ {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 221, 3, 112},
+ {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 222, 2, 115},
+ {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 223, 4, 117},
+ {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 121},
+ {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 3, 123},
+ {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 7, 126},
+ {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 245, 7, 133},
+ {"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 3, 140},
+ {"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 247, 10, 143},
+ {"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 248, 2, 153},
+ {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 249, 2, 155},
+ {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 250, 4, 157},
+ {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 251, 3, 161},
+ {"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 21, 164},
+ {"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 253, 16, 185},
+ {"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 11, 201},
+ {"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 8, 212},
+ {"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 6, 220},
+ {"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 257, 6, 226},
+ {"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 232},
+ {"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 8, 234},
+ {"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 260, 1, 242},
+ {"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 1, 243},
+ {"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 1, 244},
+ {"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 263, 1, 245},
+ {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 6, 246},
+ {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 265, 7, 252},
+ {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 3, 259},
+ {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 262},
+ {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 280, 3, 264},
+ {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 281, 2, 267},
+ {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 29, 269},
+ {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 29, 298},
+ {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 2, 327},
+ {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 329},
+ {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 3, 331},
+ {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 3, 334},
+ {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 2, 337},
+ {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 2, 339},
+ {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 8, 341},
+ {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 306, 2, 349},
+ {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 3, 351},
+ {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 310, 2, 354},
+ {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 312, 5, 356},
+ {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 320, 1, 361},
+ {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 328, 1, 362},
+ {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 363},
+ {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 344, 1, 364},
+ {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 352, 1, 365},
+ {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 1, 366},
+ {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 2, 367},
+ {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 4, 369},
+ {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 373},
+ {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 11, 375},
+ {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 9, 386},
+ {"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 395},
+ {"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 2, 397},
+ {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 2, 399},
+ {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 20, 401},
+ {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 20, 421},
+ {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 441},
+ {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 4, 443},
+ {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 2, 447},
+ {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 2, 449},
+ {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 480, 2, 451},
+ {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 488, 2, 453},
+ {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 496, 2, 455},
+ {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 504, 2, 457},
+ {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 512, 2, 459},
+ {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 520, 2, 461},
+ {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 528, 2, 463},
+ {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 536, 2, 465},
+ {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 544, 4, 467},
+ {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 2, 471},
+ {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 560, 2, 473},
+ {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 568, 2, 475},
+ {"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 576, 2, 477},
+ {"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 578, 2, 479},
+ {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 610, 2, 481},
+ {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 483},
+ {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 620, 3, 485},
+ {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 5, 488},
+ {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 630, 2, 493},
+ {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 638, 2, 495},
+ {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 646, 3, 497},
+ {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 654, 2, 500},
+ {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 662, 2, 502},
+ {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 670, 2, 504},
+ {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 678, 2, 506},
+ {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 686, 2, 508},
+ {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 694, 2, 510},
+ {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 2, 512},
+ {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 2, 514},
+ {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 2, 516},
+ {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 726, 2, 518},
+ {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 734, 2, 520},
+ {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 2, 522},
+ {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 2, 524},
+ {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 2, 526},
+ {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 2, 528},
+ {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 2, 530},
+ {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 2, 532},
+ {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 2, 534},
+ {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 798, 2, 536},
+ {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 2, 538},
+ {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 2, 540},
+ {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 2, 542},
+ {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 3, 544},
+ {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 7, 547},
+ {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 7, 554},
+ {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 2, 561},
+ {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 2, 563},
+ {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 4, 565},
+ {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 2, 569},
+ {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 2, 571},
+ {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 2, 573},
+ {"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 830, 3, 575},
+ {"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 832, 3, 578},
+ {"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 581},
+ {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 836, 7, 583},
+ {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 852, 2, 590},
+ {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 853, 2, 592},
+ {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 854, 2, 594},
+ {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 855, 2, 596},
+ {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 856, 19, 598},
+ {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 6, 617},
+ {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 858, 3, 623},
+ {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 859, 3, 626},
+ {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 3, 629},
+ {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 5, 632},
+ {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 862, 5, 637},
+ {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 1, 642},
+ {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 864, 1, 643},
+ {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 5, 644},
+ {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 866, 5, 649},
+ {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 3, 654},
+ {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 3, 657},
+ {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 3, 660},
+ {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 870, 5, 663},
+ {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 871, 5, 668},
+ {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 872, 1, 673},
+ {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 873, 1, 674},
+ {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 874, 3, 675},
+ {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 3, 678},
+ {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 876, 3, 681},
+ {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 877, 2, 684},
+ {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 878, 2, 686},
+ {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 879, 2, 688},
+ {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 880, 2, 690},
+ {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 881, 17, 692},
+ {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 882, 2, 709},
+ {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 883, 1, 711},
+ {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 884, 9, 712},
+ {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 885, 6, 721},
+ {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 886, 6, 727},
+ {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 887, 2, 733},
+ {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 888, 2, 735},
+ {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 889, 3, 737},
+ {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 925, 2, 740},
+ {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 961, 6, 742},
+ {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 962, 2, 748},
+ {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 2, 750},
+ {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 971, 3, 752},
+ {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 972, 5, 755},
+ {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 980, 3, 760},
+ {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 981, 2, 763},
+ {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 982, 2, 765},
+ {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 4, 767},
+ {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 3, 771},
+ {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 5, 774},
+ {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 986, 5, 779},
+ {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 5, 784},
+ {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 988, 5, 789},
+ {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 989, 8, 794},
+ {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 9, 802},
+ {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 8, 811},
+ {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 5, 819},
+ {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 4, 824},
+ {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 2, 828},
+ {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 14, 830},
+ {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 19, 844},
+ {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 3, 863},
+ {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 3, 866},
+ {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 2, 869},
+ {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 17, 871},
+ {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 5, 888},
+ {"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 5, 893},
+ {"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 5, 898},
+ {"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 5, 903},
+ {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 2, 908},
+ {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1009, 3, 910},
+ {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1010, 2, 913},
+ {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 2, 915},
+ {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 2, 917},
+ {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 7, 919},
+ {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 4, 926},
+ {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1015, 3, 930},
+ {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1016, 3, 933},
+ {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1017, 2, 936},
+ {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 2, 938},
+ {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 2, 940},
+ {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 4, 942},
+ {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1021, 13, 946},
+ {"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 2, 959},
+ {"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 961},
+ {"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 2, 963},
+ {"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 2, 965},
+ {"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 967},
+ {"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 969},
+ {"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 2, 971},
+ {"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 2, 973},
+ {"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 2, 975},
+ {"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 2, 977},
+ {"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 2, 979},
+ {"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 2, 981},
+ {"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 2, 983},
+ {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1046, 9, 985},
+ {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 19, 994},
+ {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1048, 2, 1013},
+ {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 2, 1015},
+ {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1050, 18, 1017},
+ {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 5, 1035},
+ {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1052, 6, 1040},
+ {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 1046},
+ {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1054, 2, 1048},
+ {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 14, 1050},
+ {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1056, 9, 1064},
+ {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 2, 1073},
+ {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1058, 2, 1075},
+ {"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 3, 1077},
+ {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1060, 9, 1080},
+ {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 9, 1089},
+ {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1062, 4, 1098},
+ {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 3, 1102},
+ {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1064, 3, 1105},
+ {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 3, 1108},
+ {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1066, 5, 1111},
+ {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1068, 1, 1116},
+ {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 6, 1117},
+ {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 13, 1123},
+ {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1085, 4, 1136},
+ {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1086, 2, 1140},
+ {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 2, 1142},
+ {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1088, 8, 1144},
+ {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1089, 7, 1152},
+ {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1090, 2, 1159},
+ {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1091, 8, 1161},
+ {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1092, 2, 1169},
+ {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1093, 8, 1171},
+ {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1094, 12, 1179},
+ {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1095, 3, 1191},
+ {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1096, 3, 1194},
+ {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1097, 2, 1197},
+ {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1099, 2, 1199},
+ {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 2, 1201},
+ {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 7, 1203},
+ {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 2, 1210},
+ {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 7, 1212},
+ {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 4, 1219},
+ {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 8, 1223},
+ {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 9, 1231},
+ {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 7, 1240},
+ {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 9, 1247},
+ {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 2, 1256},
+ {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1121, 2, 1258},
+ {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 4, 1260},
+ {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 2, 1264},
+ {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 2, 1266},
+ {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1129, 2, 1268},
+ {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1131, 4, 1270},
+ {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 2, 1274},
+ {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1135, 2, 1276},
+ {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1137, 2, 1278},
+ {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 2, 1280},
+ {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 2, 1282},
+ {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1143, 2, 1284},
+ {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 6, 1286},
+ {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1147, 2, 1292},
+ {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1151, 2, 1294},
+ {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1155, 21, 1296},
+ {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1156, 3, 1317},
+ {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1160, 21, 1320},
+ {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1161, 2, 1341},
+ {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1162, 13, 1343},
+ {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1163, 3, 1356},
+ {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1164, 3, 1359},
+ {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1165, 3, 1362},
+ {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1166, 3, 1365},
+ {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1167, 2, 1368},
+ {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1168, 2, 1370},
+ {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1169, 9, 1372},
+ {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1170, 43, 1381},
+ {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1171, 43, 1424},
+ {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1172, 2, 1467},
+ {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1173, 2, 1469},
+ {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1174, 8, 1471},
+ {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1178, 1, 1479},
+ {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1179, 2, 1480},
+ {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1183, 38, 1482},
+ {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1184, 3, 1520},
+ {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1188, 2, 1523},
+ {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1192, 3, 1525},
+ {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1196, 3, 1528},
+ {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1200, 3, 1531},
+ {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1201, 4, 1534},
+ {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1202, 2, 1538},
+ {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1203, 13, 1540},
+ {"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1204, 13, 1553},
+ {"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1205, 13, 1566},
+ {"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1206, 13, 1579},
+ {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1207, 3, 1592},
+ {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1208, 33, 1595},
+ {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1209, 2, 1628},
+ {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1213, 2, 1630},
+ {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1214, 5, 1632},
+ {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1246, 2, 1637},
+ {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1247, 24, 1639},
+ {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1248, 2, 1663},
+ {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1249, 7, 1665},
+ {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1250, 5, 1672},
+ {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1251, 1, 1677},
+ {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1252, 5, 1678},
+ {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1253, 1, 1683},
+ {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1254, 4, 1684},
+ {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1255, 2, 1688},
+ {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1256, 1, 1690},
+ {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1257, 2, 1691},
+ {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1258, 4, 1693},
+ {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1259, 2, 1697},
+ {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1260, 4, 1699},
+ {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1261, 16, 1703},
+ {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1262, 1, 1719},
+ {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1263, 1, 1720},
+ {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1264, 18, 1721},
+ {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1265, 1, 1739},
+ {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1266, 1, 1740},
+ {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1267, 7, 1741},
+ {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1268, 7, 1748},
+ {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1269, 13, 1755},
+ {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1270, 10, 1768},
+ {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1271, 10, 1778},
+ {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1272, 7, 1788},
+ {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1273, 2, 1795},
+ {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1274, 1, 1797},
+ {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1275, 2, 1798},
+ {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1276, 16, 1800},
+ {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1277, 2, 1816},
+ {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1281, 1, 1818},
+ {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1283, 1, 1819},
+ {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1285, 1, 1820},
+ {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1287, 1, 1821},
+ {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1291, 35, 1822},
+ {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1292, 35, 1857},
+ {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1293, 35, 1892},
+ {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1294, 35, 1927},
+ {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1295, 2, 1962},
+ {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1296, 2, 1964},
+ {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1300, 1, 1966},
+ {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1304, 1, 1967},
+ {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1308, 1, 1968},
+ {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1312, 3, 1969},
+ {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1313, 3, 1972},
+ {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1314, 3, 1975},
+ {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1315, 3, 1978},
+ {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1316, 2, 1981},
+ {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1317, 2, 1983},
+ {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1318, 4, 1985},
+ {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1319, 1, 1989},
+ {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1320, 4, 1990},
+ {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1321, 1, 1994},
+ {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1322, 2, 1995},
+ {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 5, 1997},
+ {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1324, 2, 2002},
+ {"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 3, 2004},
+ {"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 2, 2007},
+ {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 4, 2009},
+ {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 8, 2013},
+ {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 16, 2021},
+ {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1335, 10, 2037},
+ {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1336, 10, 2047},
+ {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 2, 2057},
+ {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1338, 18, 2059},
+ {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 25, 2077},
+ {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1410, 2, 2102},
+ {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1474, 2, 2104},
+ {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1482, 9, 2106},
+ {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1486, 2, 2115},
+ {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1487, 2, 2117},
+ {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1523, 2, 2119},
+ {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1559, 2, 2121},
+ {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1595, 2, 2123},
+ {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1631, 2, 2125},
+ {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1667, 2, 2127},
+ {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1703, 2, 2129},
+ {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1739, 2, 2131},
+ {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1775, 2, 2133},
+ {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1811, 2, 2135},
+ {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1847, 2, 2137},
+ {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1848, 2, 2139},
+ {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1884, 2, 2141},
+ {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 1920, 2, 2143},
+ {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1956, 2, 2145},
+ {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2020, 2, 2147},
+ {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2021, 3, 2149},
+ {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2022, 3, 2152},
+ {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2023, 2, 2155},
+ {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2024, 2, 2157},
+ {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2025, 4, 2159},
+ {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2026, 5, 2163},
+ {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2027, 4, 2168},
+ {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2028, 5, 2172},
+ {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2029, 1, 2177},
+ {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2030, 4, 2178},
+ {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2031, 2, 2182},
+ {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2032, 5, 2184},
+ {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2033, 5, 2189},
+ {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2034, 1, 2194},
+ {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2035, 19, 2195},
+ {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2036, 7, 2214},
+ {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2037, 4, 2221},
+ {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2038, 6, 2225},
+ {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2039, 7, 2231},
+ {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2040, 9, 2238},
+ {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2041, 5, 2247},
+ {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2042, 13, 2252},
+ {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2043, 4, 2265},
+ {"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2044, 3, 2269},
+ {"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2046, 2, 2272},
+ {"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2047, 2, 2274},
+ {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2049, 2, 2276},
+ {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2050, 3, 2278},
+ {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2051, 5, 2281},
+ {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2052, 3, 2286},
+ {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2053, 3, 2289},
+ {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2054, 2, 2292},
+ {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2055, 3, 2294},
+ {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2056, 13, 2297},
+ {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2057, 2, 2310},
+ {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2058, 9, 2312},
+ {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2059, 3, 2321},
+ {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2060, 2, 2324},
+ {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2068, 2, 2326},
+ {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2069, 2, 2328},
+ {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2070, 2, 2330},
+ {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2071, 2, 2332},
+ {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2087, 5, 2334},
+ {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2095, 8, 2339},
+ {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2103, 2, 2347},
+ {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2104, 2, 2349},
+ {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2105, 2, 2351},
+ {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2113, 3, 2353},
+ {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2114, 4, 2356},
+ {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2130, 5, 2360},
+ {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2131, 7, 2365},
+ {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2147, 2, 2372},
+ {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2163, 3, 2374},
+ {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2164, 5, 2377},
+ {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 8, 2382},
+ {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2166, 6, 2390},
+ {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2167, 2, 2396},
+ {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2168, 4, 2398},
+ {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2169, 4, 2402},
+ {"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 2, 2406},
+ {"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 4, 2408},
+ {"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 11, 2412},
+ {"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 9, 2423},
+ {"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 16, 2432},
+ {"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 5, 2448},
+ {"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 4, 2453},
+ {"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2184, 6, 2457},
+ {"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 6, 2463},
+ {"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2188, 12, 2469},
+ {"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2190, 14, 2481},
+ {"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2192, 12, 2495},
+ {"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2194, 2, 2507},
+ {"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2196, 2, 2509},
+ {"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2198, 2, 2511},
+ {"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2200, 8, 2513},
+ {"cvmx_spx0_pll_bw_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2202, 2, 2521},
+ {"cvmx_spx0_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 2203, 2, 2523},
+ {"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2204, 5, 2525},
+ {"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2206, 2, 2530},
+ {"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2208, 6, 2532},
+ {"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2272, 4, 2538},
+ {"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2274, 5, 2542},
+ {"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2276, 2, 2547},
+ {"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2278, 4, 2549},
+ {"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2280, 3, 2553},
+ {"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2282, 2, 2556},
+ {"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2284, 9, 2558},
+ {"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2286, 10, 2567},
+ {"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2288, 9, 2577},
+ {"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2290, 2, 2586},
+ {"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2292, 6, 2588},
+ {"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 3, 2594},
+ {"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 4, 2597},
+ {"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 2, 2601},
+ {"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 2, 2603},
+ {"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 3, 2605},
+ {"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 2, 2608},
+ {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2368, 6, 2610},
+ {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2369, 3, 2616},
+ {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2370, 5, 2619},
+ {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2371, 4, 2624},
+ {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2372, 6, 2628},
+ {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 4, 2634},
+ {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2374, 2, 2638},
+ {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 4, 2640},
+ {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2376, 2, 2644},
+ {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 3, 2646},
+ {"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2378, 4, 2649},
+ {"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2379, 12, 2653},
+ {"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2380, 3, 2665},
+ {"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 2, 2668},
+ {"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2382, 2, 2670},
+ {"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 17, 2672},
+ {"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2384, 12, 2689},
+ {"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2385, 6, 2701},
+ {"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2386, 5, 2707},
+ {"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2387, 1, 2712},
+ {"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2388, 2, 2713},
+ {"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2389, 2, 2715},
+ {"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2390, 17, 2717},
+ {"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2391, 12, 2734},
+ {"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2392, 6, 2746},
+ {"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2393, 2, 2752},
+ {"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2394, 2, 2754},
+ {"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2395, 17, 2756},
+ {"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2396, 12, 2773},
+ {"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2397, 6, 2785},
+ {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2398, 3, 2791},
+ {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2399, 5, 2794},
+ {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2400, 3, 2799},
+ {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2401, 6, 2802},
+ {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2402, 2, 2808},
+ {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2403, 2, 2810},
+ {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2404, 2, 2812},
+ {NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
+ /* name , --------------address, ---------------type, bits, csr offset */
+ {"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
+ {"ASX1_INT_EN" , 0x11800B8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
+ {"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
+ {"ASX1_INT_REG" , 0x11800B8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
+ {"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
+ {"ASX1_PRT_LOOP" , 0x11800B8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
+ {"ASX0_RLD_BYPASS" , 0x11800B0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
+ {"ASX1_RLD_BYPASS" , 0x11800B8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
+ {"ASX0_RLD_BYPASS_SETTING" , 0x11800B0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
+ {"ASX1_RLD_BYPASS_SETTING" , 0x11800B8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
+ {"ASX0_RLD_COMP" , 0x11800B0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
+ {"ASX1_RLD_COMP" , 0x11800B8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
+ {"ASX0_RLD_DATA_DRV" , 0x11800B0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
+ {"ASX1_RLD_DATA_DRV" , 0x11800B8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
+ {"ASX0_RLD_FCRAM_MODE" , 0x11800B0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
+ {"ASX1_RLD_FCRAM_MODE" , 0x11800B8000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
+ {"ASX0_RLD_NCTL_STRONG" , 0x11800B0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
+ {"ASX1_RLD_NCTL_STRONG" , 0x11800B8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
+ {"ASX0_RLD_NCTL_WEAK" , 0x11800B0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
+ {"ASX1_RLD_NCTL_WEAK" , 0x11800B8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
+ {"ASX0_RLD_PCTL_STRONG" , 0x11800B0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
+ {"ASX1_RLD_PCTL_STRONG" , 0x11800B8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
+ {"ASX0_RLD_PCTL_WEAK" , 0x11800B0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
+ {"ASX1_RLD_PCTL_WEAK" , 0x11800B8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
+ {"ASX0_RLD_SETTING" , 0x11800B0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
+ {"ASX1_RLD_SETTING" , 0x11800B8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
+ {"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
+ {"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
+ {"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
+ {"ASX0_RX_CLK_SET003" , 0x11800B0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
+ {"ASX1_RX_CLK_SET000" , 0x11800B8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
+ {"ASX1_RX_CLK_SET001" , 0x11800B8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
+ {"ASX1_RX_CLK_SET002" , 0x11800B8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
+ {"ASX1_RX_CLK_SET003" , 0x11800B8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
+ {"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
+ {"ASX1_RX_PRT_EN" , 0x11800B8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
+ {"ASX0_RX_WOL" , 0x11800B0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
+ {"ASX1_RX_WOL" , 0x11800B8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
+ {"ASX0_RX_WOL_MSK" , 0x11800B0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
+ {"ASX1_RX_WOL_MSK" , 0x11800B8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
+ {"ASX0_RX_WOL_POWOK" , 0x11800B0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
+ {"ASX1_RX_WOL_POWOK" , 0x11800B8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
+ {"ASX0_RX_WOL_SIG" , 0x11800B0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
+ {"ASX1_RX_WOL_SIG" , 0x11800B8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
+ {"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
+ {"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
+ {"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
+ {"ASX0_TX_CLK_SET003" , 0x11800B0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
+ {"ASX1_TX_CLK_SET000" , 0x11800B8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
+ {"ASX1_TX_CLK_SET001" , 0x11800B8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
+ {"ASX1_TX_CLK_SET002" , 0x11800B8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
+ {"ASX1_TX_CLK_SET003" , 0x11800B8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
+ {"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
+ {"ASX1_TX_COMP_BYP" , 0x11800B8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
+ {"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
+ {"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
+ {"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
+ {"ASX0_TX_HI_WATER003" , 0x11800B0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
+ {"ASX1_TX_HI_WATER000" , 0x11800B8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
+ {"ASX1_TX_HI_WATER001" , 0x11800B8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
+ {"ASX1_TX_HI_WATER002" , 0x11800B8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
+ {"ASX1_TX_HI_WATER003" , 0x11800B8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
+ {"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
+ {"ASX1_TX_PRT_EN" , 0x11800B8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
+ {"ASX0_DBG_DATA_DRV" , 0x11800B0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
+ {"ASX0_DBG_DATA_ENABLE" , 0x11800B0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
+ {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
+ {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
+ {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
+ {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
+ {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT10_EN0" , 0x10700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT11_EN0" , 0x10700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT12_EN0" , 0x10700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT13_EN0" , 0x10700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT14_EN0" , 0x10700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT15_EN0" , 0x10700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT26_EN0" , 0x10700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT27_EN0" , 0x10700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT28_EN0" , 0x10700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT29_EN0" , 0x10700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT30_EN0" , 0x10700000003E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT31_EN0" , 0x10700000003F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT10_EN1" , 0x10700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT11_EN1" , 0x10700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT12_EN1" , 0x10700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT13_EN1" , 0x10700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT14_EN1" , 0x10700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT15_EN1" , 0x10700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT26_EN1" , 0x10700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT27_EN1" , 0x10700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT28_EN1" , 0x10700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT29_EN1" , 0x10700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT30_EN1" , 0x10700000003E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT31_EN1" , 0x10700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT20_SUM0" , 0x10700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT21_SUM0" , 0x10700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT22_SUM0" , 0x10700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT23_SUM0" , 0x10700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT24_SUM0" , 0x10700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT25_SUM0" , 0x10700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT26_SUM0" , 0x10700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT27_SUM0" , 0x10700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT28_SUM0" , 0x10700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT29_SUM0" , 0x10700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT30_SUM0" , 0x10700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT31_SUM0" , 0x10700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
+ {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR4" , 0x10700000006A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR5" , 0x10700000006A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR6" , 0x10700000006B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR7" , 0x10700000006B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR8" , 0x10700000006C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR9" , 0x10700000006C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR10" , 0x10700000006D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR11" , 0x10700000006D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR12" , 0x10700000006E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR13" , 0x10700000006E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR14" , 0x10700000006F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_CLR15" , 0x10700000006F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
+ {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
+ {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
+ {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
+ {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE4" , 0x10700000005A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE5" , 0x10700000005A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE6" , 0x10700000005B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE7" , 0x10700000005B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE8" , 0x10700000005C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE9" , 0x10700000005C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE10" , 0x10700000005D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE11" , 0x10700000005D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE12" , 0x10700000005E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE13" , 0x10700000005E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE14" , 0x10700000005F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_POKE15" , 0x10700000005F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
+ {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
+ {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
+ {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
+ {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
+ {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
+ {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
+ {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
+ {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
+ {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
+ {"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
+ {"DFA_BST0" , 0x11800300007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
+ {"DFA_BST1" , 0x11800300007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
+ {"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
+ {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
+ {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
+ {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
+ {"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
+ {"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
+ {"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
+ {"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
+ {"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
+ {"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
+ {"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
+ {"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
+ {"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
+ {"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
+ {"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
+ {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
+ {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
+ {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
+ {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
+ {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
+ {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
+ {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
+ {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
+ {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
+ {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
+ {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
+ {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
+ {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
+ {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
+ {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
+ {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
+ {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
+ {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
+ {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
+ {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
+ {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
+ {"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
+ {"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
+ {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
+ {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
+ {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
+ {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
+ {"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
+ {"GMX1_INF_MODE" , 0x11800100007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
+ {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
+ {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
+ {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX1_RX000_ADR_CAM4" , 0x11800100001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX1_RX001_ADR_CAM4" , 0x11800100009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX1_RX002_ADR_CAM4" , 0x11800100011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX1_RX003_ADR_CAM4" , 0x11800100019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX1_RX000_ADR_CAM5" , 0x11800100001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX1_RX001_ADR_CAM5" , 0x11800100009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX1_RX002_ADR_CAM5" , 0x11800100011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX1_RX003_ADR_CAM5" , 0x11800100019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX0_RX_PASS_EN" , 0x11800080005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
+ {"GMX1_RX_PASS_EN" , 0x11800100005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
+ {"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
+ {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
+ {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX1_SMAC001" , 0x1180010000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX1_SMAC003" , 0x1180010001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
+ {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
+ {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX1_TX001_APPEND" , 0x1180010000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX1_TX003_APPEND" , 0x1180010001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX1_TX001_BURST" , 0x1180010000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX1_TX003_BURST" , 0x1180010001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX0_TX003_CLK" , 0x1180008001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX1_TX001_CLK" , 0x1180010000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX1_TX003_CLK" , 0x1180010001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX1_TX001_CTL" , 0x1180010000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX1_TX003_CTL" , 0x1180010001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX1_TX001_MIN_PKT" , 0x1180010000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX1_TX003_MIN_PKT" , 0x1180010001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX1_TX001_SLOT" , 0x1180010000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX1_TX003_SLOT" , 0x1180010001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX1_TX001_STAT0" , 0x1180010000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX1_TX003_STAT0" , 0x1180010001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX1_TX001_STAT1" , 0x1180010000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX1_TX003_STAT1" , 0x1180010001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX1_TX001_STAT2" , 0x1180010000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX1_TX003_STAT2" , 0x1180010001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX1_TX001_STAT3" , 0x1180010000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX1_TX003_STAT3" , 0x1180010001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX1_TX000_STAT4" , 0x11800100002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX1_TX001_STAT4" , 0x1180010000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX1_TX002_STAT4" , 0x11800100012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX1_TX003_STAT4" , 0x1180010001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX1_TX000_STAT5" , 0x11800100002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX1_TX001_STAT5" , 0x1180010000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX1_TX002_STAT5" , 0x11800100012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX1_TX003_STAT5" , 0x1180010001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX1_TX000_STAT6" , 0x11800100002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX1_TX001_STAT6" , 0x1180010000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX1_TX002_STAT6" , 0x11800100012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX1_TX003_STAT6" , 0x1180010001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX1_TX000_STAT7" , 0x11800100002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX1_TX001_STAT7" , 0x1180010000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX1_TX002_STAT7" , 0x11800100012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX1_TX003_STAT7" , 0x1180010001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX1_TX000_STAT8" , 0x11800100002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX1_TX001_STAT8" , 0x1180010000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX1_TX002_STAT8" , 0x11800100012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX1_TX003_STAT8" , 0x1180010001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GMX1_TX000_STAT9" , 0x11800100002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GMX1_TX001_STAT9" , 0x1180010000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GMX1_TX002_STAT9" , 0x11800100012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GMX1_TX003_STAT9" , 0x1180010001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
+ {"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
+ {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
+ {"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
+ {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
+ {"GMX1_TX001_STATS_CTL" , 0x1180010000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
+ {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
+ {"GMX1_TX003_STATS_CTL" , 0x1180010001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
+ {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
+ {"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
+ {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
+ {"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
+ {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
+ {"GMX1_TX001_THRESH" , 0x1180010000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
+ {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
+ {"GMX1_TX003_THRESH" , 0x1180010001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
+ {"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
+ {"GMX1_TX_BP" , 0x11800100004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
+ {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
+ {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
+ {"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
+ {"GMX1_TX_CORRUPT" , 0x11800100004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
+ {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
+ {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
+ {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
+ {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
+ {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
+ {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
+ {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
+ {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
+ {"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
+ {"GMX1_TX_LFSR" , 0x11800100004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
+ {"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
+ {"GMX1_TX_OVR_BP" , 0x11800100004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
+ {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
+ {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
+ {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
+ {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
+ {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
+ {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
+ {"GMX0_TX_SPI_CTL" , 0x11800080004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
+ {"GMX1_TX_SPI_CTL" , 0x11800100004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
+ {"GMX0_TX_SPI_MAX" , 0x11800080004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
+ {"GMX1_TX_SPI_MAX" , 0x11800100004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
+ {"GMX0_TX_SPI_THRESH" , 0x11800080004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
+ {"GMX1_TX_SPI_THRESH" , 0x11800100004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
+ {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
+ {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
+ {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
+ {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
+ {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
+ {"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
+ {"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
+ {"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
+ {"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
+ {"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
+ {"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
+ {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
+ {"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
+ {"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
+ {"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
+ {"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
+ {"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
+ {"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
+ {"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
+ {"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
+ {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
+ {"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
+ {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
+ {"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
+ {"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
+ {"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
+ {"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
+ {"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
+ {"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
+ {"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
+ {"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
+ {"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
+ {"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
+ {"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
+ {"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
+ {"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
+ {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
+ {"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
+ {"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT4_BP_PAGE_CNT" , 0x14F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT5_BP_PAGE_CNT" , 0x14F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT6_BP_PAGE_CNT" , 0x14F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT7_BP_PAGE_CNT" , 0x14F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT8_BP_PAGE_CNT" , 0x14F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT9_BP_PAGE_CNT" , 0x14F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT10_BP_PAGE_CNT" , 0x14F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT11_BP_PAGE_CNT" , 0x14F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT12_BP_PAGE_CNT" , 0x14F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT13_BP_PAGE_CNT" , 0x14F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT14_BP_PAGE_CNT" , 0x14F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT15_BP_PAGE_CNT" , 0x14F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT16_BP_PAGE_CNT" , 0x14F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT17_BP_PAGE_CNT" , 0x14F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT18_BP_PAGE_CNT" , 0x14F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT19_BP_PAGE_CNT" , 0x14F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT20_BP_PAGE_CNT" , 0x14F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT21_BP_PAGE_CNT" , 0x14F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT22_BP_PAGE_CNT" , 0x14F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT23_BP_PAGE_CNT" , 0x14F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT24_BP_PAGE_CNT" , 0x14F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT25_BP_PAGE_CNT" , 0x14F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT26_BP_PAGE_CNT" , 0x14F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT27_BP_PAGE_CNT" , 0x14F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT28_BP_PAGE_CNT" , 0x14F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT29_BP_PAGE_CNT" , 0x14F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT30_BP_PAGE_CNT" , 0x14F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT31_BP_PAGE_CNT" , 0x14F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT34_BP_PAGE_CNT" , 0x14F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT35_BP_PAGE_CNT" , 0x14F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
+ {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14F0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14F0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14F0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14F0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14F0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14F0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14F0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14F0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14F0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14F0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14F0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14F0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14F0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14F0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14F0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14F0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14F0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14F00000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14F00000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14F00000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14F00000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14F00000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
+ {"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
+ {"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
+ {"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
+ {"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
+ {"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
+ {"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
+ {"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
+ {"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
+ {"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
+ {"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
+ {"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
+ {"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
+ {"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
+ {"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
+ {"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
+ {"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
+ {"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
+ {"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
+ {"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
+ {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
+ {"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
+ {"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
+ {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
+ {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
+ {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
+ {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
+ {"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
+ {"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
+ {"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
+ {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
+ {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
+ {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
+ {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
+ {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
+ {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
+ {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
+ {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
+ {"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
+ {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
+ {"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
+ {"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
+ {"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
+ {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
+ {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
+ {"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
+ {"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
+ {"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
+ {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
+ {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
+ {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
+ {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
+ {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
+ {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
+ {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
+ {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
+ {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
+ {"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
+ {"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
+ {"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
+ {"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
+ {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"LED_BLINK" , 0x1180000001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"LED_CLK_PHASE" , 0x1180000001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
+ {"LED_CYLON" , 0x1180000001AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
+ {"LED_DBG" , 0x1180000001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
+ {"LED_EN" , 0x1180000001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
+ {"LED_POLARITY" , 0x1180000001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
+ {"LED_PRT" , 0x1180000001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
+ {"LED_PRT_FMT" , 0x1180000001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
+ {"LED_PRT_STATUS0" , 0x1180000001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"LED_PRT_STATUS1" , 0x1180000001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"LED_PRT_STATUS2" , 0x1180000001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"LED_PRT_STATUS3" , 0x1180000001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"LED_PRT_STATUS4" , 0x1180000001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"LED_PRT_STATUS5" , 0x1180000001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"LED_PRT_STATUS6" , 0x1180000001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"LED_PRT_STATUS7" , 0x1180000001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"LED_UDD_CNT0" , 0x1180000001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
+ {"LED_UDD_CNT1" , 0x1180000001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
+ {"LED_UDD_DAT0" , 0x1180000001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
+ {"LED_UDD_DAT1" , 0x1180000001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
+ {"LED_UDD_DAT_CLR0" , 0x1180000001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
+ {"LED_UDD_DAT_CLR1" , 0x1180000001AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
+ {"LED_UDD_DAT_SET0" , 0x1180000001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
+ {"LED_UDD_DAT_SET1" , 0x1180000001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
+ {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
+ {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
+ {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
+ {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
+ {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
+ {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
+ {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
+ {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
+ {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
+ {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
+ {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
+ {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
+ {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
+ {"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
+ {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
+ {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
+ {"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
+ {"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
+ {"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
+ {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
+ {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
+ {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
+ {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
+ {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
+ {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
+ {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
+ {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
+ {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
+ {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
+ {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
+ {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
+ {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
+ {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
+ {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
+ {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
+ {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
+ {"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
+ {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
+ {"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
+ {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
+ {"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
+ {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
+ {"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
+ {"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
+ {"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
+ {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
+ {"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
+ {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
+ {"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
+ {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
+ {"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
+ {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
+ {"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
+ {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
+ {"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
+ {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
+ {"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
+ {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
+ {"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
+ {"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
+ {"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
+ {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
+ {"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
+ {"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
+ {"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
+ {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
+ {"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
+ {"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
+ {"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
+ {"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
+ {"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
+ {"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
+ {"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
+ {"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
+ {"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
+ {"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
+ {"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
+ {"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
+ {"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
+ {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
+ {"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
+ {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
+ {"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
+ {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
+ {"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
+ {"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
+ {"NPI_BASE_ADDR_INPUT1" , 0x11F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
+ {"NPI_BASE_ADDR_INPUT2" , 0x11F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
+ {"NPI_BASE_ADDR_INPUT3" , 0x11F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
+ {"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
+ {"NPI_BASE_ADDR_OUTPUT1" , 0x11F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
+ {"NPI_BASE_ADDR_OUTPUT2" , 0x11F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
+ {"NPI_BASE_ADDR_OUTPUT3" , 0x11F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
+ {"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
+ {"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
+ {"NPI_BUFF_SIZE_OUTPUT1" , 0x11F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
+ {"NPI_BUFF_SIZE_OUTPUT2" , 0x11F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
+ {"NPI_BUFF_SIZE_OUTPUT3" , 0x11F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
+ {"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
+ {"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
+ {"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
+ {"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
+ {"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
+ {"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 325},
+ {"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
+ {"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
+ {"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
+ {"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
+ {"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
+ {"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
+ {"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
+ {"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
+ {"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
+ {"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
+ {"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
+ {"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
+ {"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 335},
+ {"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
+ {"NPI_NUM_DESC_OUTPUT1" , 0x11F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
+ {"NPI_NUM_DESC_OUTPUT2" , 0x11F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
+ {"NPI_NUM_DESC_OUTPUT3" , 0x11F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
+ {"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
+ {"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
+ {"NPI_P1_DBPAIR_ADDR" , 0x11F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
+ {"NPI_P2_DBPAIR_ADDR" , 0x11F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
+ {"NPI_P3_DBPAIR_ADDR" , 0x11F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
+ {"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
+ {"NPI_P1_INSTR_ADDR" , 0x11F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
+ {"NPI_P2_INSTR_ADDR" , 0x11F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
+ {"NPI_P3_INSTR_ADDR" , 0x11F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
+ {"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
+ {"NPI_P1_INSTR_CNTS" , 0x11F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
+ {"NPI_P2_INSTR_CNTS" , 0x11F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
+ {"NPI_P3_INSTR_CNTS" , 0x11F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
+ {"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
+ {"NPI_P1_PAIR_CNTS" , 0x11F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
+ {"NPI_P2_PAIR_CNTS" , 0x11F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
+ {"NPI_P3_PAIR_CNTS" , 0x11F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
+ {"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
+ {"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
+ {"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
+ {"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
+ {"NPI_PORT33_INSTR_HDR" , 0x11F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
+ {"NPI_PORT34_INSTR_HDR" , 0x11F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
+ {"NPI_PORT35_INSTR_HDR" , 0x11F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
+ {"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
+ {"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
+ {"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
+ {"NPI_SIZE_INPUT1" , 0x11F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
+ {"NPI_SIZE_INPUT2" , 0x11F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
+ {"NPI_SIZE_INPUT3" , 0x11F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
+ {"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
+ {"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
+ {"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 354},
+ {"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 355},
+ {"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 356},
+ {"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 357},
+ {"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 358},
+ {"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 359},
+ {"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 360},
+ {"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 361},
+ {"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 362},
+ {"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 363},
+ {"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 364},
+ {"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 365},
+ {"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 366},
+ {"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 367},
+ {"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 368},
+ {"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 369},
+ {"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 370},
+ {"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 371},
+ {"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 372},
+ {"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 373},
+ {"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 374},
+ {"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 375},
+ {"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 376},
+ {"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 377},
+ {"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 378},
+ {"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 379},
+ {"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 380},
+ {"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 381},
+ {"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 382},
+ {"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 383},
+ {"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 384},
+ {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
+ {"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
+ {"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
+ {"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
+ {"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 386},
+ {"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 386},
+ {"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 387},
+ {"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 387},
+ {"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 388},
+ {"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 388},
+ {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
+ {"PCI_INSTR_COUNT1" , 0x8Cull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
+ {"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
+ {"PCI_INSTR_COUNT3" , 0x9Cull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
+ {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 390},
+ {"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 391},
+ {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 392},
+ {"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 393},
+ {"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 394},
+ {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
+ {"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
+ {"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
+ {"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
+ {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
+ {"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
+ {"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
+ {"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
+ {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
+ {"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
+ {"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
+ {"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
+ {"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
+ {"PCI_PKTS_SENT_TIME1" , 0x5Cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
+ {"PCI_PKTS_SENT_TIME2" , 0x6Cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
+ {"PCI_PKTS_SENT_TIME3" , 0x7Cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
+ {"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 399},
+ {"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 400},
+ {"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 401},
+ {"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
+ {"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 403},
+ {"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 404},
+ {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 405},
+ {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 406},
+ {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 407},
+ {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 408},
+ {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 409},
+ {"PIP_BCK_PRS" , 0x11800A0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
+ {"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
+ {"PIP_CRC_CTL0" , 0x11800A0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
+ {"PIP_CRC_CTL1" , 0x11800A0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
+ {"PIP_CRC_IV0" , 0x11800A0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
+ {"PIP_CRC_IV1" , 0x11800A0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
+ {"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
+ {"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
+ {"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
+ {"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
+ {"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
+ {"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
+ {"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
+ {"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
+ {"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
+ {"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG4" , 0x11800A0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG5" , 0x11800A0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG6" , 0x11800A0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG7" , 0x11800A0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG8" , 0x11800A0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG9" , 0x11800A0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG10" , 0x11800A0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG11" , 0x11800A0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG12" , 0x11800A0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG13" , 0x11800A0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG14" , 0x11800A0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG15" , 0x11800A0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG16" , 0x11800A0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG17" , 0x11800A0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG18" , 0x11800A0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG19" , 0x11800A0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG20" , 0x11800A00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG21" , 0x11800A00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG22" , 0x11800A00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG23" , 0x11800A00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG24" , 0x11800A00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG25" , 0x11800A00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG26" , 0x11800A00002D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG27" , 0x11800A00002D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG28" , 0x11800A00002E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG29" , 0x11800A00002E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG30" , 0x11800A00002F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG31" , 0x11800A00002F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG34" , 0x11800A0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_CFG35" , 0x11800A0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG4" , 0x11800A0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG5" , 0x11800A0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG6" , 0x11800A0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG7" , 0x11800A0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG8" , 0x11800A0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG9" , 0x11800A0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG10" , 0x11800A0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG11" , 0x11800A0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG12" , 0x11800A0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG13" , 0x11800A0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG14" , 0x11800A0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG15" , 0x11800A0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG16" , 0x11800A0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG17" , 0x11800A0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG18" , 0x11800A0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG19" , 0x11800A0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG20" , 0x11800A00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG21" , 0x11800A00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG22" , 0x11800A00004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG23" , 0x11800A00004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG24" , 0x11800A00004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG25" , 0x11800A00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG26" , 0x11800A00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG27" , 0x11800A00004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG28" , 0x11800A00004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG29" , 0x11800A00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG30" , 0x11800A00004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG31" , 0x11800A00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG34" , 0x11800A0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_PRT_TAG35" , 0x11800A0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
+ {"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
+ {"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
+ {"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
+ {"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
+ {"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT4" , 0x11800A0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT5" , 0x11800A0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT6" , 0x11800A00009E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT7" , 0x11800A0000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT8" , 0x11800A0000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT9" , 0x11800A0000AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT10" , 0x11800A0000B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT11" , 0x11800A0000B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT12" , 0x11800A0000BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT13" , 0x11800A0000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT14" , 0x11800A0000C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT15" , 0x11800A0000CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT16" , 0x11800A0000D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT17" , 0x11800A0000D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT18" , 0x11800A0000DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT19" , 0x11800A0000DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT20" , 0x11800A0000E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT21" , 0x11800A0000E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT22" , 0x11800A0000EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT23" , 0x11800A0000F30ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT24" , 0x11800A0000F80ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT25" , 0x11800A0000FD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT26" , 0x11800A0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT27" , 0x11800A0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT28" , 0x11800A00010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT29" , 0x11800A0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT30" , 0x11800A0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT31" , 0x11800A00011B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT34" , 0x11800A00012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT0_PRT35" , 0x11800A00012F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT4" , 0x11800A0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT5" , 0x11800A0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT6" , 0x11800A00009E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT7" , 0x11800A0000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT8" , 0x11800A0000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT9" , 0x11800A0000AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT10" , 0x11800A0000B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT11" , 0x11800A0000B78ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT12" , 0x11800A0000BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT13" , 0x11800A0000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT14" , 0x11800A0000C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT15" , 0x11800A0000CB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT16" , 0x11800A0000D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT17" , 0x11800A0000D58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT18" , 0x11800A0000DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT19" , 0x11800A0000DF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT20" , 0x11800A0000E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT21" , 0x11800A0000E98ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT22" , 0x11800A0000EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT23" , 0x11800A0000F38ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT24" , 0x11800A0000F88ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT25" , 0x11800A0000FD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT26" , 0x11800A0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT27" , 0x11800A0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT28" , 0x11800A00010C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT29" , 0x11800A0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT30" , 0x11800A0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT31" , 0x11800A00011B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT34" , 0x11800A00012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT1_PRT35" , 0x11800A00012F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT4" , 0x11800A0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT5" , 0x11800A00009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT6" , 0x11800A00009F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT7" , 0x11800A0000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT8" , 0x11800A0000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT9" , 0x11800A0000AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT10" , 0x11800A0000B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT11" , 0x11800A0000B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT12" , 0x11800A0000BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT13" , 0x11800A0000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT14" , 0x11800A0000C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT15" , 0x11800A0000CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT16" , 0x11800A0000D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT17" , 0x11800A0000D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT18" , 0x11800A0000DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT19" , 0x11800A0000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT20" , 0x11800A0000E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT21" , 0x11800A0000EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT22" , 0x11800A0000EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT23" , 0x11800A0000F40ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT24" , 0x11800A0000F90ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT25" , 0x11800A0000FE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT26" , 0x11800A0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT27" , 0x11800A0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT28" , 0x11800A00010D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT29" , 0x11800A0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT30" , 0x11800A0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT31" , 0x11800A00011C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT34" , 0x11800A00012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT2_PRT35" , 0x11800A0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT4" , 0x11800A0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT5" , 0x11800A00009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT6" , 0x11800A00009F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT7" , 0x11800A0000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT8" , 0x11800A0000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT9" , 0x11800A0000AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT10" , 0x11800A0000B38ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT11" , 0x11800A0000B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT12" , 0x11800A0000BD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT13" , 0x11800A0000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT14" , 0x11800A0000C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT15" , 0x11800A0000CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT16" , 0x11800A0000D18ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT17" , 0x11800A0000D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT18" , 0x11800A0000DB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT19" , 0x11800A0000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT20" , 0x11800A0000E58ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT21" , 0x11800A0000EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT22" , 0x11800A0000EF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT23" , 0x11800A0000F48ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT24" , 0x11800A0000F98ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT25" , 0x11800A0000FE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT26" , 0x11800A0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT27" , 0x11800A0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT28" , 0x11800A00010D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT29" , 0x11800A0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT30" , 0x11800A0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT31" , 0x11800A00011C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT34" , 0x11800A00012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT3_PRT35" , 0x11800A0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT4" , 0x11800A0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT5" , 0x11800A00009B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT6" , 0x11800A0000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT7" , 0x11800A0000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT8" , 0x11800A0000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT9" , 0x11800A0000AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT10" , 0x11800A0000B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT11" , 0x11800A0000B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT12" , 0x11800A0000BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT13" , 0x11800A0000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT14" , 0x11800A0000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT15" , 0x11800A0000CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT16" , 0x11800A0000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT17" , 0x11800A0000D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT18" , 0x11800A0000DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT19" , 0x11800A0000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT20" , 0x11800A0000E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT21" , 0x11800A0000EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT22" , 0x11800A0000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT23" , 0x11800A0000F50ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT24" , 0x11800A0000FA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT25" , 0x11800A0000FF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT26" , 0x11800A0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT27" , 0x11800A0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT28" , 0x11800A00010E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT29" , 0x11800A0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT30" , 0x11800A0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT31" , 0x11800A00011D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT34" , 0x11800A00012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT4_PRT35" , 0x11800A0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT4" , 0x11800A0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT5" , 0x11800A00009B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT6" , 0x11800A0000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT7" , 0x11800A0000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT8" , 0x11800A0000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT9" , 0x11800A0000AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT10" , 0x11800A0000B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT11" , 0x11800A0000B98ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT12" , 0x11800A0000BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT13" , 0x11800A0000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT14" , 0x11800A0000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT15" , 0x11800A0000CD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT16" , 0x11800A0000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT17" , 0x11800A0000D78ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT18" , 0x11800A0000DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT19" , 0x11800A0000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT20" , 0x11800A0000E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT21" , 0x11800A0000EB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT22" , 0x11800A0000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT23" , 0x11800A0000F58ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT24" , 0x11800A0000FA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT25" , 0x11800A0000FF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT26" , 0x11800A0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT27" , 0x11800A0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT28" , 0x11800A00010E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT29" , 0x11800A0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT30" , 0x11800A0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT31" , 0x11800A00011D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT34" , 0x11800A00012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT5_PRT35" , 0x11800A0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT4" , 0x11800A0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT5" , 0x11800A00009C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT6" , 0x11800A0000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT7" , 0x11800A0000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT8" , 0x11800A0000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT9" , 0x11800A0000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT10" , 0x11800A0000B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT11" , 0x11800A0000BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT12" , 0x11800A0000BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT13" , 0x11800A0000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT14" , 0x11800A0000C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT15" , 0x11800A0000CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT16" , 0x11800A0000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT17" , 0x11800A0000D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT18" , 0x11800A0000DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT19" , 0x11800A0000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT20" , 0x11800A0000E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT21" , 0x11800A0000EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT22" , 0x11800A0000F10ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT23" , 0x11800A0000F60ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT24" , 0x11800A0000FB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT25" , 0x11800A0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT26" , 0x11800A0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT27" , 0x11800A00010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT28" , 0x11800A00010F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT29" , 0x11800A0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT30" , 0x11800A0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT31" , 0x11800A00011E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT34" , 0x11800A00012D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT6_PRT35" , 0x11800A0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT4" , 0x11800A0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT5" , 0x11800A00009C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT6" , 0x11800A0000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT7" , 0x11800A0000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT8" , 0x11800A0000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT9" , 0x11800A0000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT10" , 0x11800A0000B58ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT11" , 0x11800A0000BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT12" , 0x11800A0000BF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT13" , 0x11800A0000C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT14" , 0x11800A0000C98ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT15" , 0x11800A0000CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT16" , 0x11800A0000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT17" , 0x11800A0000D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT18" , 0x11800A0000DD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT19" , 0x11800A0000E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT20" , 0x11800A0000E78ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT21" , 0x11800A0000EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT22" , 0x11800A0000F18ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT23" , 0x11800A0000F68ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT24" , 0x11800A0000FB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT25" , 0x11800A0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT26" , 0x11800A0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT27" , 0x11800A00010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT28" , 0x11800A00010F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT29" , 0x11800A0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT30" , 0x11800A0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT31" , 0x11800A00011E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT34" , 0x11800A00012D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT7_PRT35" , 0x11800A0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT4" , 0x11800A0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT5" , 0x11800A00009D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT6" , 0x11800A0000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT7" , 0x11800A0000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT8" , 0x11800A0000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT9" , 0x11800A0000B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT10" , 0x11800A0000B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT11" , 0x11800A0000BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT12" , 0x11800A0000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT13" , 0x11800A0000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT14" , 0x11800A0000CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT15" , 0x11800A0000CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT16" , 0x11800A0000D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT17" , 0x11800A0000D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT18" , 0x11800A0000DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT19" , 0x11800A0000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT20" , 0x11800A0000E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT21" , 0x11800A0000ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT22" , 0x11800A0000F20ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT23" , 0x11800A0000F70ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT24" , 0x11800A0000FC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT25" , 0x11800A0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT26" , 0x11800A0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT27" , 0x11800A00010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT28" , 0x11800A0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT29" , 0x11800A0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT30" , 0x11800A00011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT31" , 0x11800A00011F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT34" , 0x11800A00012E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT8_PRT35" , 0x11800A0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT4" , 0x11800A0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT5" , 0x11800A00009D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT6" , 0x11800A0000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT7" , 0x11800A0000A78ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT8" , 0x11800A0000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT9" , 0x11800A0000B18ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT10" , 0x11800A0000B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT11" , 0x11800A0000BB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT12" , 0x11800A0000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT13" , 0x11800A0000C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT14" , 0x11800A0000CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT15" , 0x11800A0000CF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT16" , 0x11800A0000D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT17" , 0x11800A0000D98ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT18" , 0x11800A0000DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT19" , 0x11800A0000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT20" , 0x11800A0000E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT21" , 0x11800A0000ED8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT22" , 0x11800A0000F28ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT23" , 0x11800A0000F78ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT24" , 0x11800A0000FC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT25" , 0x11800A0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT26" , 0x11800A0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT27" , 0x11800A00010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT28" , 0x11800A0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT29" , 0x11800A0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT30" , 0x11800A00011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT31" , 0x11800A00011F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT34" , 0x11800A00012E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT9_PRT35" , 0x11800A0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
+ {"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS4" , 0x11800A0001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS5" , 0x11800A0001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS6" , 0x11800A0001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS7" , 0x11800A0001AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS8" , 0x11800A0001B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS9" , 0x11800A0001B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS10" , 0x11800A0001B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS11" , 0x11800A0001B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS12" , 0x11800A0001B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS13" , 0x11800A0001BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS14" , 0x11800A0001BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS15" , 0x11800A0001BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS16" , 0x11800A0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS17" , 0x11800A0001C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS18" , 0x11800A0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS19" , 0x11800A0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS20" , 0x11800A0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS21" , 0x11800A0001CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS22" , 0x11800A0001CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS23" , 0x11800A0001CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS24" , 0x11800A0001D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS25" , 0x11800A0001D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS26" , 0x11800A0001D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS27" , 0x11800A0001D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS28" , 0x11800A0001D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS29" , 0x11800A0001DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS30" , 0x11800A0001DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS31" , 0x11800A0001DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS34" , 0x11800A0001E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_ERRS35" , 0x11800A0001E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS4" , 0x11800A0001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS5" , 0x11800A0001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS6" , 0x11800A0001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS7" , 0x11800A0001AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS8" , 0x11800A0001B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS9" , 0x11800A0001B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS10" , 0x11800A0001B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS11" , 0x11800A0001B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS12" , 0x11800A0001B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS13" , 0x11800A0001BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS14" , 0x11800A0001BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS15" , 0x11800A0001BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS16" , 0x11800A0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS17" , 0x11800A0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS18" , 0x11800A0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS19" , 0x11800A0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS20" , 0x11800A0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS21" , 0x11800A0001CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS22" , 0x11800A0001CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS23" , 0x11800A0001CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS24" , 0x11800A0001D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS25" , 0x11800A0001D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS26" , 0x11800A0001D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS27" , 0x11800A0001D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS28" , 0x11800A0001D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS29" , 0x11800A0001DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS30" , 0x11800A0001DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS31" , 0x11800A0001DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS34" , 0x11800A0001E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_OCTS35" , 0x11800A0001E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS4" , 0x11800A0001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS5" , 0x11800A0001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS6" , 0x11800A0001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS7" , 0x11800A0001AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS8" , 0x11800A0001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS9" , 0x11800A0001B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS10" , 0x11800A0001B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS11" , 0x11800A0001B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS12" , 0x11800A0001B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS13" , 0x11800A0001BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS14" , 0x11800A0001BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS15" , 0x11800A0001BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS16" , 0x11800A0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS17" , 0x11800A0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS18" , 0x11800A0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS19" , 0x11800A0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS20" , 0x11800A0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS21" , 0x11800A0001CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS22" , 0x11800A0001CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS23" , 0x11800A0001CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS24" , 0x11800A0001D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS25" , 0x11800A0001D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS26" , 0x11800A0001D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS27" , 0x11800A0001D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS28" , 0x11800A0001D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS29" , 0x11800A0001DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS30" , 0x11800A0001DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS31" , 0x11800A0001DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS34" , 0x11800A0001E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_STAT_INB_PKTS35" , 0x11800A0001E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
+ {"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
+ {"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
+ {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
+ {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
+ {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
+ {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
+ {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
+ {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
+ {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
+ {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
+ {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
+ {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
+ {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
+ {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
+ {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
+ {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
+ {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
+ {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
+ {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
+ {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
+ {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
+ {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
+ {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
+ {"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
+ {"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
+ {"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
+ {"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
+ {"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
+ {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
+ {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
+ {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
+ {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
+ {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
+ {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
+ {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
+ {"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 476},
+ {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 477},
+ {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
+ {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
+ {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
+ {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
+ {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 491},
+ {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
+ {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
+ {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
+ {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
+ {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
+ {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
+ {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
+ {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
+ {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
+ {"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
+ {"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
+ {"SPX0_BIST_STAT" , 0x11800900007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
+ {"SPX1_BIST_STAT" , 0x11800980007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
+ {"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
+ {"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
+ {"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
+ {"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
+ {"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
+ {"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
+ {"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
+ {"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
+ {"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
+ {"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
+ {"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
+ {"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
+ {"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
+ {"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
+ {"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
+ {"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
+ {"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
+ {"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
+ {"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
+ {"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
+ {"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
+ {"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
+ {"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
+ {"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
+ {"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
+ {"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
+ {"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
+ {"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
+ {"SPX0_PLL_BW_CTL" , 0x1180090000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
+ {"SPX0_PLL_SETTING" , 0x1180090000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
+ {"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
+ {"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
+ {"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
+ {"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
+ {"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL020" , 0x11800900000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL021" , 0x11800900000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL022" , 0x11800900000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL023" , 0x11800900000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL024" , 0x11800900000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL025" , 0x11800900000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL026" , 0x11800900000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL027" , 0x11800900000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL028" , 0x11800900000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL029" , 0x11800900000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL030" , 0x11800900000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_CAL031" , 0x11800900000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL020" , 0x11800980000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL021" , 0x11800980000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL022" , 0x11800980000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL023" , 0x11800980000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL024" , 0x11800980000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL025" , 0x11800980000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL026" , 0x11800980000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL027" , 0x11800980000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL028" , 0x11800980000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL029" , 0x11800980000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL030" , 0x11800980000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX1_SPI4_CAL031" , 0x11800980000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
+ {"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
+ {"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
+ {"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
+ {"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
+ {"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
+ {"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
+ {"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
+ {"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
+ {"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
+ {"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
+ {"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
+ {"STX0_INT_MSK" , 0x11800900006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
+ {"STX1_INT_MSK" , 0x11800980006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
+ {"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
+ {"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
+ {"STX0_INT_SYNC" , 0x11800900006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
+ {"STX1_INT_SYNC" , 0x11800980006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
+ {"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
+ {"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
+ {"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL020" , 0x11800900004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL021" , 0x11800900004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL022" , 0x11800900004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL023" , 0x11800900004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL024" , 0x11800900004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL025" , 0x11800900004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL026" , 0x11800900004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL027" , 0x11800900004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL028" , 0x11800900004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL029" , 0x11800900004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL030" , 0x11800900004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_CAL031" , 0x11800900004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL020" , 0x11800980004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL021" , 0x11800980004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL022" , 0x11800980004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL023" , 0x11800980004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL024" , 0x11800980004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL025" , 0x11800980004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL026" , 0x11800980004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL027" , 0x11800980004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL028" , 0x11800980004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL029" , 0x11800980004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL030" , 0x11800980004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX1_SPI4_CAL031" , 0x11800980004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
+ {"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
+ {"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
+ {"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
+ {"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
+ {"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
+ {"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
+ {"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
+ {"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
+ {"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
+ {"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
+ {"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
+ {"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
+ {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
+ {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
+ {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
+ {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
+ {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
+ {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
+ {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
+ {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
+ {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
+ {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
+ {"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
+ {"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
+ {"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
+ {"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
+ {"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
+ {"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
+ {"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
+ {"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
+ {"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
+ {"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
+ {"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
+ {"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
+ {"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
+ {"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
+ {"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
+ {"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
+ {"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
+ {"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
+ {"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
+ {"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
+ {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
+ {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
+ {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
+ {"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
+ {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
+ {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
+ {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
+ {NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
+ /* name , bit, width, csr, type, rst un, typ un, reset, typical */
+ {"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
+ {"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
+ {"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
+ {"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
+ {"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
+ {"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
+ {"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
+ {"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
+ {"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
+ {"PCTL" , 4, 4, 5, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 5, "RAZ", 1, 1, 0, 0},
+ {"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
+ {"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
+ {"MODE" , 0, 1, 7, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 7, "RAZ", 1, 1, 0, 0},
+ {"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
+ {"NCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
+ {"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
+ {"PCTL" , 0, 5, 11, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
+ {"SETTING" , 0, 5, 12, "RO", 1, 1, 0, 0},
+ {"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
+ {"SETTING" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
+ {"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
+ {"PRT_EN" , 0, 4, 14, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_4_63" , 4, 60, 14, "RAZ", 1, 1, 0, 0},
+ {"ENABLE" , 0, 1, 15, "RO", 1, 1, 0, 0},
+ {"STATUS" , 1, 1, 15, "RO", 1, 1, 0, 0},
+ {"RESERVED_2_63" , 2, 62, 15, "RAZ", 1, 1, 0, 0},
+ {"MSK" , 0, 64, 16, "R/W", 0, 1, 0ull, 0},
+ {"POWEROK" , 0, 1, 17, "R/W", 0, 1, 1ull, 0},
+ {"RESERVED_1_63" , 1, 63, 17, "RAZ", 1, 1, 0, 0},
+ {"SIG" , 0, 32, 18, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 18, "RAZ", 1, 1, 0, 0},
+ {"SETTING" , 0, 5, 19, "R/W", 0, 0, 24ull, 24ull},
+ {"RESERVED_5_63" , 5, 59, 19, "RAZ", 1, 1, 0, 0},
+ {"NCTL" , 0, 4, 20, "R/W", 0, 0, 8ull, 8ull},
+ {"PCTL" , 4, 4, 20, "R/W", 0, 0, 8ull, 8ull},
+ {"RESERVED_8_63" , 8, 56, 20, "RAZ", 1, 1, 0, 0},
+ {"MARK" , 0, 4, 21, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
+ {"PRT_EN" , 0, 4, 22, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_4_63" , 4, 60, 22, "RAZ", 1, 1, 0, 0},
+ {"NCTL" , 0, 4, 23, "R/W", 0, 1, 15ull, 0},
+ {"PCTL" , 4, 4, 23, "R/W", 0, 1, 15ull, 0},
+ {"RESERVED_8_63" , 8, 56, 23, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 1, 24, "R/W", 0, 1, 1ull, 0},
+ {"RESERVED_1_63" , 1, 63, 24, "RAZ", 1, 1, 0, 0},
+ {"BIST" , 0, 4, 25, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 25, "RAZ", 1, 1, 0, 0},
+ {"DINT" , 0, 16, 26, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 26, "RAZ", 1, 1, 0, 0},
+ {"FUSE" , 0, 16, 27, "RO", 1, 1, 0, 0},
+ {"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
+ {"GSTOP" , 0, 1, 28, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 28, "RAZ", 1, 1, 0, 0},
+ {"WORKQ" , 0, 16, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"GPIO" , 16, 16, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"MBOX" , 32, 2, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"UART" , 34, 2, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"PCI_INT" , 36, 4, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"PCI_MSI" , 40, 4, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_44_44" , 44, 1, 29, "RAZ", 1, 1, 0, 0},
+ {"TWSI" , 45, 1, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"RML" , 46, 1, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"TRACE" , 47, 1, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"GMX_DRP" , 48, 2, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"IPD_DRP" , 50, 1, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"KEY_ZERO" , 51, 1, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"TIMER" , 52, 4, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_56_63" , 56, 8, 29, "RAZ", 1, 1, 0, 0},
+ {"WDOG" , 0, 16, 30, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 30, "RAZ", 1, 1, 0, 0},
+ {"WORKQ" , 0, 16, 31, "RO", 0, 0, 0ull, 0ull},
+ {"GPIO" , 16, 16, 31, "RO", 0, 0, 0ull, 0ull},
+ {"MBOX" , 32, 2, 31, "RO", 0, 0, 0ull, 0ull},
+ {"UART" , 34, 2, 31, "RO", 0, 0, 0ull, 0ull},
+ {"PCI_INT" , 36, 4, 31, "RO", 0, 0, 0ull, 0ull},
+ {"PCI_MSI" , 40, 4, 31, "RO", 0, 0, 0ull, 0ull},
+ {"WDOG_SUM" , 44, 1, 31, "RO", 0, 0, 0ull, 0ull},
+ {"TWSI" , 45, 1, 31, "RO", 0, 0, 0ull, 0ull},
+ {"RML" , 46, 1, 31, "RO", 0, 0, 0ull, 0ull},
+ {"TRACE" , 47, 1, 31, "RO", 0, 0, 0ull, 0ull},
+ {"GMX_DRP" , 48, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
+ {"IPD_DRP" , 50, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
+ {"KEY_ZERO" , 51, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TIMER" , 52, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_56_63" , 56, 8, 31, "RAZ", 1, 1, 0, 0},
+ {"WDOG" , 0, 16, 32, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 32, "RAZ", 1, 1, 0, 0},
+ {"BITS" , 0, 32, 33, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 33, "RAZ", 1, 1, 0, 0},
+ {"BITS" , 0, 32, 34, "R/W1", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 34, "RAZ", 1, 1, 0, 0},
+ {"NMI" , 0, 16, 35, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
+ {"INTR" , 0, 2, 36, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 36, "RAZ", 1, 1, 0, 0},
+ {"PPDBG" , 0, 16, 37, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 37, "RAZ", 1, 1, 0, 0},
+ {"POKE" , 0, 64, 38, "RAZ", 1, 1, 0, 0},
+ {"RST0" , 0, 1, 39, "R/W", 1, 1, 0, 0},
+ {"RST" , 1, 15, 39, "R/W", 0, 0, 32767ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 39, "RAZ", 1, 1, 0, 0},
+ {"SOFT_BIST" , 0, 1, 40, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 40, "RAZ", 1, 1, 0, 0},
+ {"SOFT_PRST" , 0, 1, 41, "R/W", 0, 0, 1ull, 0ull},
+ {"NPI" , 1, 1, 41, "R/W", 0, 0, 0ull, 0ull},
+ {"HOST64" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_3_63" , 3, 61, 41, "RAZ", 1, 1, 0, 0},
+ {"SOFT_RST" , 0, 1, 42, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 42, "RAZ", 1, 1, 0, 0},
+ {"LEN" , 0, 36, 43, "R/W", 0, 0, 0ull, 0ull},
+ {"ONE_SHOT" , 36, 1, 43, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_37_63" , 37, 27, 43, "RAZ", 1, 1, 0, 0},
+ {"MODE" , 0, 2, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"STATE" , 2, 2, 44, "RO", 0, 0, 0ull, 0ull},
+ {"LEN" , 4, 16, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT" , 20, 24, 44, "RO", 0, 0, 0ull, 0ull},
+ {"DSTOP" , 44, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"GSTOPEN" , 45, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_46_63" , 46, 18, 44, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 17, 45, "RO", 0, 1, 0ull, 0},
+ {"DSEL_EXT" , 17, 1, 45, "R/W", 0, 0, 1ull, 0ull},
+ {"C_MUL" , 18, 5, 45, "RO", 1, 1, 0, 0},
+ {"CCLK_DIV2" , 23, 1, 45, "RO", 1, 1, 0, 0},
+ {"DCLK_MUL2" , 24, 1, 45, "RO", 1, 1, 0, 0},
+ {"D_MUL" , 25, 4, 45, "RO", 1, 1, 0, 0},
+ {"RESERVED_29_63" , 29, 35, 45, "RAZ", 1, 1, 0, 0},
+ {"PDF" , 0, 16, 46, "RO", 0, 0, 0ull, 0ull},
+ {"RDF" , 16, 16, 46, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 46, "RAZ", 0, 0, 0ull, 0ull},
+ {"P1_BRF" , 0, 8, 47, "RO", 0, 0, 0ull, 0ull},
+ {"P0_BRF" , 8, 8, 47, "RO", 0, 0, 0ull, 0ull},
+ {"P1_BWB" , 16, 1, 47, "RO", 0, 0, 0ull, 0ull},
+ {"P0_BWB" , 17, 1, 47, "RO", 0, 0, 0ull, 0ull},
+ {"CRF" , 18, 1, 47, "RO", 0, 0, 0ull, 0ull},
+ {"DRF" , 19, 1, 47, "RO", 0, 0, 0ull, 0ull},
+ {"GFU" , 20, 1, 47, "RO", 0, 0, 0ull, 0ull},
+ {"IFU" , 21, 1, 47, "RO", 0, 0, 0ull, 0ull},
+ {"CRQ" , 22, 1, 47, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_63" , 23, 41, 47, "RAZ", 0, 0, 0ull, 0ull},
+ {"SARB" , 0, 1, 48, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_1_63" , 1, 63, 48, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 20, 49, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_20_63" , 20, 44, 49, "RAZ", 1, 1, 0, 0},
+ {"SIZE" , 0, 9, 50, "R/W", 0, 1, 3ull, 0},
+ {"POOL" , 9, 3, 50, "R/W", 0, 1, 0ull, 0},
+ {"DWBCNT" , 12, 8, 50, "R/W", 0, 1, 1ull, 0},
+ {"RESERVED_20_63" , 20, 44, 50, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_4" , 0, 5, 51, "RAZ", 1, 1, 0, 0},
+ {"RDPTR" , 5, 31, 51, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 51, "RAZ", 1, 1, 0, 0},
+ {"CP2ECCENA" , 0, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2SBE" , 1, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CP2DBE" , 2, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CP2SBINA" , 3, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2DBINA" , 4, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2SYN" , 5, 8, 52, "RO", 0, 0, 0ull, 0ull},
+ {"DTEECCENA" , 13, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"DTESBE" , 14, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTEDBE" , 15, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTESBINA" , 16, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"DTEDBINA" , 17, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"DTESYN" , 18, 7, 52, "RO", 0, 0, 0ull, 0ull},
+ {"DTEPARENA" , 25, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"DTEPERR" , 26, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTEPINA" , 27, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2PARENA" , 28, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2PERR" , 29, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CP2PINA" , 30, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"DBLOVF" , 31, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DBLINA" , 32, 1, 52, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_33_63" , 33, 31, 52, "RAZ", 1, 1, 0, 0},
+ {"ENA_P1" , 0, 1, 53, "R/W", 0, 0, 1ull, 1ull},
+ {"ENA_P0" , 1, 1, 53, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_2_2" , 2, 1, 53, "RAZ", 1, 1, 0, 0},
+ {"MTYPE" , 3, 1, 53, "R/W", 0, 0, 0ull, 0ull},
+ {"SIL_LAT" , 4, 2, 53, "R/W", 0, 0, 0ull, 0ull},
+ {"RW_DLY" , 6, 4, 53, "R/W", 0, 0, 1ull, 1ull},
+ {"WR_DLY" , 10, 4, 53, "R/W", 0, 0, 2ull, 2ull},
+ {"FPRCH" , 14, 2, 53, "R/W", 0, 0, 0ull, 0ull},
+ {"BPRCH" , 16, 2, 53, "R/W", 0, 0, 0ull, 0ull},
+ {"BLEN" , 18, 1, 53, "R/W", 0, 0, 0ull, 0ull},
+ {"PBUNK" , 19, 3, 53, "R/W", 0, 0, 2ull, 2ull},
+ {"R2R_PBUNK" , 22, 1, 53, "R/W", 0, 0, 1ull, 1ull},
+ {"INIT_P1" , 23, 1, 53, "R/W", 0, 0, 0ull, 0ull},
+ {"INIT_P0" , 24, 1, 53, "R/W", 0, 0, 0ull, 0ull},
+ {"BUNK_INIT" , 25, 2, 53, "R/W", 0, 0, 3ull, 3ull},
+ {"RESERVED_27_63" , 27, 37, 53, "RAZ", 1, 1, 0, 0},
+ {"REF_INT" , 0, 4, 54, "R/W", 0, 0, 3ull, 3ull},
+ {"TSKW" , 4, 2, 54, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_7" , 6, 2, 54, "RAZ", 0, 0, 0ull, 0ull},
+ {"TRL" , 8, 4, 54, "R/W", 0, 0, 6ull, 6ull},
+ {"TWL" , 12, 4, 54, "R/W", 0, 0, 7ull, 7ull},
+ {"TRC" , 16, 4, 54, "R/W", 0, 0, 6ull, 6ull},
+ {"TMRSC" , 20, 3, 54, "R/W", 0, 0, 6ull, 6ull},
+ {"MRS_ENA" , 23, 1, 54, "R/W", 0, 0, 0ull, 0ull},
+ {"AREF_ENA" , 24, 1, 54, "R/W", 0, 0, 0ull, 0ull},
+ {"REF_INTLO" , 25, 9, 54, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 54, "RAZ", 1, 1, 0, 0},
+ {"FCRAM2P" , 0, 1, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"MAXBNK" , 1, 1, 55, "R/W", 0, 0, 1ull, 1ull},
+ {"UA_START" , 2, 2, 55, "R/W", 0, 0, 1ull, 1ull},
+ {"REFSHORT" , 4, 1, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"TRFC" , 5, 5, 55, "R/W", 0, 0, 9ull, 9ull},
+ {"SILRST" , 10, 1, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"DTECLKDIS" , 11, 1, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 55, "RAZ", 1, 1, 0, 0},
+ {"MADDR" , 0, 24, 56, "RO", 0, 0, 0ull, 0ull},
+ {"BNUM" , 24, 3, 56, "RO", 0, 0, 0ull, 0ull},
+ {"PNUM" , 27, 1, 56, "RO", 0, 0, 0ull, 0ull},
+ {"FSRC" , 28, 2, 56, "RO", 0, 0, 0ull, 0ull},
+ {"FDST" , 30, 9, 56, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_39_63" , 39, 25, 56, "RAZ", 1, 1, 0, 0},
+ {"MRS" , 0, 15, 57, "R/W", 0, 0, 66ull, 66ull},
+ {"RESERVED_15_15" , 15, 1, 57, "RAZ", 1, 1, 0, 0},
+ {"EMRS" , 16, 15, 57, "R/W", 0, 0, 64ull, 64ull},
+ {"RESERVED_31_31" , 31, 1, 57, "RAZ", 1, 1, 0, 0},
+ {"EMRS2" , 32, 15, 57, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_47_63" , 47, 17, 57, "RAZ", 1, 1, 0, 0},
+ {"MRSDAT" , 0, 23, 58, "R/W", 0, 0, 2ull, 2ull},
+ {"RESERVED_23_63" , 23, 41, 58, "RAZ", 1, 1, 0, 0},
+ {"IMODE" , 0, 1, 59, "R/W", 0, 0, 1ull, 1ull},
+ {"QMODE" , 1, 1, 59, "R/W", 0, 0, 1ull, 1ull},
+ {"PMODE" , 2, 1, 59, "R/W", 0, 0, 1ull, 1ull},
+ {"DTMODE" , 3, 1, 59, "R/W", 0, 0, 1ull, 1ull},
+ {"DCMODE" , 4, 1, 59, "R/W", 0, 0, 0ull, 0ull},
+ {"SBDLCK" , 5, 1, 59, "R/W", 0, 0, 0ull, 0ull},
+ {"SBDNUM" , 6, 4, 59, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_63" , 10, 54, 59, "RAZ", 1, 1, 0, 0},
+ {"SBD0" , 0, 64, 60, "RO", 1, 1, 0, 0},
+ {"SBD1" , 0, 64, 61, "RO", 1, 1, 0, 0},
+ {"SBD2" , 0, 64, 62, "RO", 1, 1, 0, 0},
+ {"SBD3" , 0, 64, 63, "RO", 1, 1, 0, 0},
+ {"FDR" , 0, 1, 64, "RO", 0, 0, 0ull, 0ull},
+ {"FFR" , 1, 1, 64, "RO", 0, 0, 0ull, 0ull},
+ {"FPF1" , 2, 1, 64, "RO", 0, 0, 0ull, 0ull},
+ {"FPF0" , 3, 1, 64, "RO", 0, 0, 0ull, 0ull},
+ {"FRD" , 4, 1, 64, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 64, "RAZ", 1, 1, 0, 0},
+ {"MEM0_ERR" , 0, 7, 65, "R/W", 0, 0, 0ull, 0ull},
+ {"MEM1_ERR" , 7, 7, 65, "R/W", 0, 0, 0ull, 0ull},
+ {"ENB" , 14, 1, 65, "R/W", 0, 0, 0ull, 0ull},
+ {"USE_STT" , 15, 1, 65, "R/W", 0, 0, 0ull, 0ull},
+ {"USE_LDT" , 16, 1, 65, "R/W", 0, 0, 0ull, 0ull},
+ {"RESET" , 17, 1, 65, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
+ {"FPF_RD" , 0, 11, 66, "R/W", 0, 0, 64ull, 0ull},
+ {"FPF_WR" , 11, 11, 66, "R/W", 0, 0, 196ull, 0ull},
+ {"RESERVED_22_63" , 22, 42, 66, "RAZ", 1, 1, 0, 0},
+ {"FPF_SIZ" , 0, 11, 67, "R/W", 0, 0, 256ull, 0ull},
+ {"RESERVED_11_63" , 11, 53, 67, "RAZ", 1, 1, 0, 0},
+ {"FPF_RD" , 0, 12, 68, "R/W", 0, 0, 64ull, 0ull},
+ {"FPF_WR" , 12, 12, 68, "R/W", 0, 0, 196ull, 0ull},
+ {"RESERVED_24_63" , 24, 40, 68, "RAZ", 1, 1, 0, 0},
+ {"FPF_SIZ" , 0, 12, 69, "R/W", 0, 0, 256ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 69, "RAZ", 1, 1, 0, 0},
+ {"FED0_SBE" , 0, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"FED0_DBE" , 1, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"FED1_SBE" , 2, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"FED1_DBE" , 3, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q0_UND" , 4, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q0_COFF" , 5, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q0_PERR" , 6, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q1_UND" , 7, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q1_COFF" , 8, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q1_PERR" , 9, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q2_UND" , 10, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q2_COFF" , 11, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q2_PERR" , 12, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q3_UND" , 13, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q3_COFF" , 14, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q3_PERR" , 15, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q4_UND" , 16, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q4_COFF" , 17, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q4_PERR" , 18, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q5_UND" , 19, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q5_COFF" , 20, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q5_PERR" , 21, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q6_UND" , 22, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q6_COFF" , 23, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q6_PERR" , 24, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q7_UND" , 25, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q7_COFF" , 26, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"Q7_PERR" , 27, 1, 70, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_28_63" , 28, 36, 70, "RAZ", 1, 1, 0, 0},
+ {"FED0_SBE" , 0, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FED0_DBE" , 1, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FED1_SBE" , 2, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FED1_DBE" , 3, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q0_UND" , 4, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q0_COFF" , 5, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q0_PERR" , 6, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q1_UND" , 7, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q1_COFF" , 8, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q1_PERR" , 9, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q2_UND" , 10, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q2_COFF" , 11, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q2_PERR" , 12, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q3_UND" , 13, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q3_COFF" , 14, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q3_PERR" , 15, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q4_UND" , 16, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q4_COFF" , 17, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q4_PERR" , 18, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q5_UND" , 19, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q5_COFF" , 20, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q5_PERR" , 21, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q6_UND" , 22, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q6_COFF" , 23, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q6_PERR" , 24, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q7_UND" , 25, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q7_COFF" , 26, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q7_PERR" , 27, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_28_63" , 28, 36, 71, "RAZ", 1, 1, 0, 0},
+ {"QUE_SIZ" , 0, 29, 72, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_29_63" , 29, 35, 72, "RAZ", 1, 1, 0, 0},
+ {"PG_NUM" , 0, 25, 73, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_25_63" , 25, 39, 73, "RAZ", 1, 1, 0, 0},
+ {"ACT_INDX" , 0, 26, 74, "RO", 0, 1, 0ull, 0},
+ {"ACT_QUE" , 26, 3, 74, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 74, "RAZ", 0, 0, 0ull, 7ull},
+ {"EXP_INDX" , 0, 26, 75, "RO", 0, 1, 0ull, 0},
+ {"EXP_QUE" , 26, 3, 75, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 75, "RAZ", 0, 0, 0ull, 7ull},
+ {"CTL" , 0, 16, 76, "R/W", 1, 0, 0, 0ull},
+ {"RESERVED_16_63" , 16, 48, 76, "RAZ", 1, 1, 0, 0},
+ {"STATUS" , 0, 32, 77, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 77, "RAZ", 1, 1, 0, 0},
+ {"OUT_COL" , 0, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
+ {"NCB_OVR" , 1, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
+ {"OUT_OVR" , 2, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_21" , 18, 4, 78, "RAZ", 0, 0, 0ull, 0ull},
+ {"LOSTSTAT" , 22, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
+ {"STATOVR" , 26, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
+ {"INB_NXA" , 27, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_31_63" , 31, 33, 78, "RAZ", 1, 1, 0, 0},
+ {"STATUS" , 0, 10, 79, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_63" , 10, 54, 79, "RAZ", 1, 1, 0, 0},
+ {"TYPE" , 0, 1, 80, "RO", 1, 1, 0, 0},
+ {"EN" , 1, 1, 80, "RO", 1, 1, 0, 0},
+ {"RESERVED_2_63" , 2, 62, 80, "RAZ", 1, 1, 0, 0},
+ {"PRT" , 0, 6, 81, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_6_63" , 6, 58, 81, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 1, 82, "R/W", 0, 1, 0ull, 0},
+ {"SPEED" , 1, 1, 82, "R/W", 0, 1, 1ull, 0},
+ {"DUPLEX" , 2, 1, 82, "R/W", 0, 1, 1ull, 0},
+ {"SLOTTIME" , 3, 1, 82, "R/W", 0, 1, 1ull, 0},
+ {"RESERVED_4_63" , 4, 60, 82, "RAZ", 1, 1, 0, 0},
+ {"ADR" , 0, 64, 83, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 84, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 85, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 86, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 87, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 88, "R/W", 0, 1, 0ull, 0},
+ {"EN" , 0, 8, 89, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 89, "RAZ", 1, 1, 0, 0},
+ {"BCST" , 0, 1, 90, "R/W", 0, 1, 1ull, 0},
+ {"MCST" , 1, 2, 90, "R/W", 0, 1, 0ull, 0},
+ {"CAM_MODE" , 3, 1, 90, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_4_63" , 4, 60, 90, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 5, 91, "R/W", 0, 0, 24ull, 24ull},
+ {"RESERVED_5_63" , 5, 59, 91, "RAZ", 1, 1, 0, 0},
+ {"MINERR" , 0, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"CAREXT" , 1, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"MAXERR" , 2, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"JABBER" , 3, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"FCSERR" , 4, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"ALNERR" , 5, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"LENERR" , 6, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"RCVERR" , 7, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"SKPERR" , 8, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"NIBERR" , 9, 1, 92, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_10_63" , 10, 54, 92, "RAZ", 1, 1, 0, 0},
+ {"PRE_CHK" , 0, 1, 93, "R/W", 0, 0, 1ull, 1ull},
+ {"PRE_STRP" , 1, 1, 93, "R/W", 0, 0, 1ull, 1ull},
+ {"CTL_DRP" , 2, 1, 93, "R/W", 0, 0, 1ull, 1ull},
+ {"CTL_BCK" , 3, 1, 93, "R/W", 0, 0, 1ull, 1ull},
+ {"CTL_MCST" , 4, 1, 93, "R/W", 0, 0, 1ull, 1ull},
+ {"CTL_SMAC" , 5, 1, 93, "R/W", 0, 0, 1ull, 1ull},
+ {"PRE_FREE" , 6, 1, 93, "R/W", 0, 0, 0ull, 0ull},
+ {"VLAN_LEN" , 7, 1, 93, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 93, "RAZ", 1, 1, 0, 0},
+ {"LEN" , 0, 16, 94, "R/W", 0, 0, 1536ull, 1536ull},
+ {"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
+ {"LEN" , 0, 16, 95, "R/W", 0, 0, 64ull, 64ull},
+ {"RESERVED_16_63" , 16, 48, 95, "RAZ", 1, 1, 0, 0},
+ {"IFG" , 0, 4, 96, "R/W", 0, 0, 12ull, 12ull},
+ {"RESERVED_4_63" , 4, 60, 96, "RAZ", 1, 1, 0, 0},
+ {"MINERR" , 0, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"CAREXT" , 1, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"MAXERR" , 2, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"JABBER" , 3, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"FCSERR" , 4, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"ALNERR" , 5, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"LENERR" , 6, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"RCVERR" , 7, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"SKPERR" , 8, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"NIBERR" , 9, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"OVRERR" , 10, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"PCTERR" , 11, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"RSVERR" , 12, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"FALERR" , 13, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"COLDET" , 14, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"IFGERR" , 15, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"PHY_LINK" , 16, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"PHY_SPD" , 17, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"PHY_DUPX" , 18, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 97, "RAZ", 1, 1, 0, 0},
+ {"MINERR" , 0, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CAREXT" , 1, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MAXERR" , 2, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"JABBER" , 3, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FCSERR" , 4, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ALNERR" , 5, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"LENERR" , 6, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RCVERR" , 7, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SKPERR" , 8, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"NIBERR" , 9, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"OVRERR" , 10, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCTERR" , 11, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RSVERR" , 12, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FALERR" , 13, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"COLDET" , 14, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"IFGERR" , 15, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PHY_LINK" , 16, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PHY_SPD" , 17, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PHY_DUPX" , 18, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 98, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 16, 99, "R/W", 0, 0, 10240ull, 10240ull},
+ {"RESERVED_16_63" , 16, 48, 99, "RAZ", 1, 1, 0, 0},
+ {"STATUS" , 0, 1, 100, "RO", 0, 1, 0ull, 0},
+ {"SPEED" , 1, 2, 100, "RO", 0, 1, 0ull, 0},
+ {"DUPLEX" , 3, 1, 100, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_4_63" , 4, 60, 100, "RAZ", 1, 1, 0, 0},
+ {"RD_CLR" , 0, 1, 101, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 48, 102, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 102, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 48, 103, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 103, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 48, 104, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 48, 105, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 105, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 108, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 108, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 109, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 109, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 110, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 110, "RAZ", 1, 1, 0, 0},
+ {"LEN" , 0, 7, 111, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_7" , 7, 1, 111, "RAZ", 1, 1, 0, 0},
+ {"FCSSEL" , 8, 1, 111, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 111, "RAZ", 1, 1, 0, 0},
+ {"MARK" , 0, 6, 112, "R/W", 1, 1, 0, 0},
+ {"RESERVED_6_63" , 6, 58, 112, "RAZ", 1, 1, 0, 0},
+ {"MARK" , 0, 6, 113, "R/W", 0, 0, 16ull, 16ull},
+ {"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
+ {"MARK" , 0, 9, 114, "R/W", 1, 1, 0, 0},
+ {"RESERVED_9_63" , 9, 55, 114, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 16, 115, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 115, "RAZ", 1, 1, 0, 0},
+ {"DPRT" , 0, 4, 116, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 116, "RAZ", 1, 1, 0, 0},
+ {"PRTS" , 0, 3, 117, "R/W", 0, 0, 4ull, 4ull},
+ {"RESERVED_3_63" , 3, 61, 117, "RAZ", 1, 1, 0, 0},
+ {"SMAC" , 0, 48, 118, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 118, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 16, 119, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BP" , 16, 1, 119, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_63" , 17, 47, 119, "RAZ", 1, 1, 0, 0},
+ {"PREAMBLE" , 0, 1, 120, "R/W", 0, 0, 1ull, 1ull},
+ {"PAD" , 1, 1, 120, "R/W", 0, 0, 1ull, 1ull},
+ {"FCS" , 2, 1, 120, "R/W", 0, 0, 1ull, 1ull},
+ {"FORCE_FCS" , 3, 1, 120, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_4_63" , 4, 60, 120, "RAZ", 1, 1, 0, 0},
+ {"BURST" , 0, 16, 121, "R/W", 0, 0, 8192ull, 8192ull},
+ {"RESERVED_16_63" , 16, 48, 121, "RAZ", 1, 1, 0, 0},
+ {"CLK_CNT" , 0, 6, 122, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_6_63" , 6, 58, 122, "RAZ", 1, 1, 0, 0},
+ {"XSCOL_EN" , 0, 1, 123, "R/W", 0, 0, 1ull, 1ull},
+ {"XSDEF_EN" , 1, 1, 123, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_2_63" , 2, 62, 123, "RAZ", 1, 1, 0, 0},
+ {"MIN_SIZE" , 0, 8, 124, "R/W", 0, 0, 59ull, 59ull},
+ {"RESERVED_8_63" , 8, 56, 124, "RAZ", 1, 1, 0, 0},
+ {"INTERVAL" , 0, 16, 125, "R/W", 0, 1, 16ull, 0},
+ {"RESERVED_16_63" , 16, 48, 125, "RAZ", 1, 1, 0, 0},
+ {"TIME" , 0, 16, 126, "R/W", 0, 1, 96ull, 0},
+ {"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
+ {"TIME" , 0, 16, 127, "RO", 1, 1, 0, 0},
+ {"RESERVED_16_63" , 16, 48, 127, "RAZ", 1, 1, 0, 0},
+ {"SEND" , 0, 1, 128, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_1_63" , 1, 63, 128, "RAZ", 1, 1, 0, 0},
+ {"SLOT" , 0, 10, 129, "R/W", 0, 0, 512ull, 512ull},
+ {"RESERVED_10_63" , 10, 54, 129, "RAZ", 1, 1, 0, 0},
+ {"TIME" , 0, 16, 130, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 130, "RAZ", 1, 1, 0, 0},
+ {"XSCOL" , 0, 32, 131, "RC/W", 0, 1, 0ull, 0},
+ {"XSDEF" , 32, 32, 131, "RC/W", 0, 1, 0ull, 0},
+ {"MCOL" , 0, 32, 132, "RC/W", 0, 1, 0ull, 0},
+ {"SCOL" , 32, 32, 132, "RC/W", 0, 1, 0ull, 0},
+ {"OCTS" , 0, 48, 133, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 133, "RAZ", 1, 1, 0, 0},
+ {"PKTS" , 0, 32, 134, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 134, "RAZ", 1, 1, 0, 0},
+ {"HIST0" , 0, 32, 135, "RC/W", 0, 1, 0ull, 0},
+ {"HIST1" , 32, 32, 135, "RC/W", 0, 1, 0ull, 0},
+ {"HIST2" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
+ {"HIST3" , 32, 32, 136, "RC/W", 0, 1, 0ull, 0},
+ {"HIST4" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
+ {"HIST5" , 32, 32, 137, "RC/W", 0, 1, 0ull, 0},
+ {"HIST6" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
+ {"HIST7" , 32, 32, 138, "RC/W", 0, 1, 0ull, 0},
+ {"BCST" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
+ {"MCST" , 32, 32, 139, "RC/W", 0, 1, 0ull, 0},
+ {"CTL" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
+ {"UNDFLW" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
+ {"RD_CLR" , 0, 1, 141, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 141, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 9, 142, "R/W", 0, 0, 32ull, 32ull},
+ {"RESERVED_9_63" , 9, 55, 142, "RAZ", 1, 1, 0, 0},
+ {"BP" , 0, 4, 143, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 143, "RAZ", 1, 1, 0, 0},
+ {"LIMIT" , 0, 5, 144, "R/W", 0, 0, 16ull, 16ull},
+ {"RESERVED_5_63" , 5, 59, 144, "RAZ", 1, 1, 0, 0},
+ {"CORRUPT" , 0, 4, 145, "R/W", 0, 0, 15ull, 15ull},
+ {"RESERVED_4_63" , 4, 60, 145, "RAZ", 1, 1, 0, 0},
+ {"IFG1" , 0, 4, 146, "R/W", 0, 1, 8ull, 0},
+ {"IFG2" , 4, 4, 146, "R/W", 0, 1, 4ull, 0},
+ {"RESERVED_8_63" , 8, 56, 146, "RAZ", 1, 1, 0, 0},
+ {"PKO_NXA" , 0, 1, 147, "R/W", 0, 0, 0ull, 0ull},
+ {"NCB_NXA" , 1, 1, 147, "R/W", 0, 0, 0ull, 0ull},
+ {"UNDFLW" , 2, 4, 147, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_7" , 6, 2, 147, "RAZ", 0, 0, 0ull, 0ull},
+ {"XSCOL" , 8, 4, 147, "R/W", 0, 0, 0ull, 0ull},
+ {"XSDEF" , 12, 4, 147, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 147, "RAZ", 1, 1, 0, 0},
+ {"PKO_NXA" , 0, 1, 148, "R/W1C", 0, 0, 0ull, 0ull},
+ {"NCB_NXA" , 1, 1, 148, "R/W1C", 0, 0, 0ull, 0ull},
+ {"UNDFLW" , 2, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_7" , 6, 2, 148, "RAZ", 0, 0, 0ull, 0ull},
+ {"XSCOL" , 8, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
+ {"XSDEF" , 12, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 148, "RAZ", 1, 1, 0, 0},
+ {"JAM" , 0, 8, 149, "R/W", 0, 1, 238ull, 0},
+ {"RESERVED_8_63" , 8, 56, 149, "RAZ", 1, 1, 0, 0},
+ {"LFSR" , 0, 16, 150, "R/W", 0, 1, 65535ull, 0},
+ {"RESERVED_16_63" , 16, 48, 150, "RAZ", 1, 1, 0, 0},
+ {"IGN_FULL" , 0, 4, 151, "R/W", 0, 0, 0ull, 0ull},
+ {"BP" , 4, 4, 151, "R/W", 0, 0, 0ull, 0ull},
+ {"EN" , 8, 4, 151, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 151, "RAZ", 1, 1, 0, 0},
+ {"DMAC" , 0, 48, 152, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
+ {"RESERVED_48_63" , 48, 16, 152, "RAZ", 1, 1, 0, 0},
+ {"TYPE" , 0, 16, 153, "R/W", 0, 0, 34824ull, 34824ull},
+ {"RESERVED_16_63" , 16, 48, 153, "RAZ", 1, 1, 0, 0},
+ {"PRTS" , 0, 5, 154, "R/W", 0, 1, 1ull, 0},
+ {"RESERVED_5_63" , 5, 59, 154, "RAZ", 1, 1, 0, 0},
+ {"CONT_PKT" , 0, 1, 155, "R/W", 0, 1, 0ull, 0},
+ {"TPA_CLR" , 1, 1, 155, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_2_63" , 2, 62, 155, "RAZ", 0, 0, 0ull, 0ull},
+ {"MAX1" , 0, 8, 156, "R/W", 0, 1, 8ull, 0},
+ {"MAX2" , 8, 8, 156, "R/W", 0, 1, 4ull, 0},
+ {"RESERVED_16_63" , 16, 48, 156, "RAZ", 1, 1, 0, 0},
+ {"THRESH" , 0, 6, 157, "R/W", 0, 1, 4ull, 0},
+ {"RESERVED_6_63" , 6, 58, 157, "RAZ", 1, 1, 0, 0},
+ {"TX_OE" , 0, 1, 158, "R/W", 0, 0, 0ull, 0ull},
+ {"RX_XOR" , 1, 1, 158, "R/W", 0, 0, 0ull, 0ull},
+ {"INT_EN" , 2, 1, 158, "R/W", 0, 0, 0ull, 0ull},
+ {"INT_TYPE" , 3, 1, 158, "R/W", 0, 0, 0ull, 0ull},
+ {"FIL_CNT" , 4, 4, 158, "R/W", 0, 0, 0ull, 0ull},
+ {"FIL_SEL" , 8, 4, 158, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 158, "RAZ", 1, 1, 0, 0},
+ {"TYPE" , 0, 16, 159, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
+ {"DAT" , 0, 16, 160, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 160, "RAZ", 1, 1, 0, 0},
+ {"CLR" , 0, 16, 161, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 161, "RAZ", 1, 1, 0, 0},
+ {"SET" , 0, 16, 162, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
+ {"ICD" , 0, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"IBD" , 1, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICRP1" , 2, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICRP0" , 3, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICRN1" , 4, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICRN0" , 5, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"IBRQ1" , 6, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"IBRQ0" , 7, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICNRT" , 8, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"IBR1" , 9, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"IBR0" , 10, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"IBDR1" , 11, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"IBDR0" , 12, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICNR0" , 13, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICNR1" , 14, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICR1" , 15, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICR0" , 16, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"ICNRCB" , 17, 1, 163, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 163, "RAZ", 1, 1, 0, 0},
+ {"FAU_END" , 0, 1, 164, "R/W", 0, 0, 0ull, 0ull},
+ {"DWB_ENB" , 1, 1, 164, "R/W", 0, 0, 1ull, 1ull},
+ {"PKO_ENB" , 2, 1, 164, "R/W", 0, 0, 0ull, 0ull},
+ {"INB_MAT" , 3, 1, 164, "R/W1C", 0, 0, 0ull, 0ull},
+ {"OUTB_MAT" , 4, 1, 164, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 164, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 15, 165, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_ENB" , 15, 1, 165, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 165, "RAZ", 1, 1, 0, 0},
+ {"TOUT_VAL" , 0, 12, 166, "R/W", 0, 0, 4ull, 4ull},
+ {"TOUT_ENB" , 12, 1, 166, "R/W", 0, 0, 1ull, 0ull},
+ {"RESERVED_13_63" , 13, 51, 166, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 15, 167, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_ENB" , 15, 1, 167, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 8, 168, "R/W", 0, 1, 0ull, 0},
+ {"DST" , 8, 9, 168, "R/W", 0, 1, 0ull, 0},
+ {"OPC" , 17, 4, 168, "R/W", 0, 1, 0ull, 0},
+ {"MASK" , 21, 8, 168, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 168, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 8, 169, "R/W", 0, 1, 0ull, 0},
+ {"DST" , 8, 9, 169, "R/W", 0, 1, 0ull, 0},
+ {"OPC" , 17, 4, 169, "R/W", 0, 1, 0ull, 0},
+ {"MASK" , 21, 8, 169, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 169, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 64, 170, "R/W", 0, 1, 0ull, 0},
+ {"DATA" , 0, 64, 171, "R/W", 0, 1, 0ull, 0},
+ {"NP_SOP" , 0, 1, 172, "R/W", 0, 0, 0ull, 0ull},
+ {"NP_EOP" , 1, 1, 172, "R/W", 0, 0, 0ull, 0ull},
+ {"P_SOP" , 2, 1, 172, "R/W", 0, 0, 0ull, 0ull},
+ {"P_EOP" , 3, 1, 172, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 172, "RAZ", 1, 1, 0, 0},
+ {"NP_SOP" , 0, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
+ {"NP_EOP" , 1, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P_SOP" , 2, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P_EOP" , 3, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 173, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 15, 174, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_ENB" , 15, 1, 174, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 174, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 15, 175, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_ENB" , 15, 1, 175, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 175, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 15, 176, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_ENB" , 15, 1, 176, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 176, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 9, 177, "R/W", 0, 1, 0ull, 0},
+ {"DST" , 9, 8, 177, "R/W", 0, 1, 0ull, 0},
+ {"EOT" , 17, 1, 177, "R/W", 0, 1, 0ull, 0},
+ {"MASK" , 18, 8, 177, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_26_63" , 26, 38, 177, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 9, 178, "R/W", 0, 1, 0ull, 0},
+ {"DST" , 9, 8, 178, "R/W", 0, 1, 0ull, 0},
+ {"EOT" , 17, 1, 178, "R/W", 0, 1, 0ull, 0},
+ {"MASK" , 18, 8, 178, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_26_63" , 26, 38, 178, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 64, 179, "R/W", 0, 1, 0ull, 0},
+ {"DATA" , 0, 64, 180, "R/W", 0, 1, 0ull, 0},
+ {"CNT_VAL" , 0, 15, 181, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_ENB" , 15, 1, 181, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 181, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 15, 182, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_ENB" , 15, 1, 182, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 182, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 15, 183, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_ENB" , 15, 1, 183, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 183, "RAZ", 1, 1, 0, 0},
+ {"PORT" , 0, 6, 184, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_6_63" , 6, 58, 184, "RAZ", 1, 1, 0, 0},
+ {"SKIP_SZ" , 0, 6, 185, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 185, "RAZ", 1, 1, 0, 0},
+ {"BACK" , 0, 4, 186, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 186, "RAZ", 1, 1, 0, 0},
+ {"BACK" , 0, 4, 187, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 187, "RAZ", 1, 1, 0, 0},
+ {"PWP" , 0, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"IPD_NEW" , 1, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"IPD_OLD" , 2, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PRC_OFF" , 3, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ0" , 4, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ1" , 5, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PBM_WORD" , 6, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PBM0" , 7, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PBM1" , 8, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PBM2" , 9, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PBM3" , 10, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"IPQ_PBE0" , 11, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"IPQ_PBE1" , 12, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ_POW" , 13, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ_WP1" , 14, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ_WQED" , 15, 1, 188, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 188, "RAZ", 1, 1, 0, 0},
+ {"PRT_ENB" , 0, 36, 189, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 189, "RAZ", 1, 1, 0, 0},
+ {"CLK_CNT" , 0, 64, 190, "RO", 0, 0, 0ull, 0ull},
+ {"IPD_EN" , 0, 1, 191, "R/W", 0, 0, 0ull, 0ull},
+ {"OPC_MODE" , 1, 2, 191, "R/W", 0, 0, 0ull, 0ull},
+ {"PBP_EN" , 3, 1, 191, "R/W", 0, 0, 0ull, 0ull},
+ {"WQE_LEND" , 4, 1, 191, "R/W", 0, 0, 0ull, 0ull},
+ {"PKT_LEND" , 5, 1, 191, "R/W", 0, 0, 0ull, 0ull},
+ {"NADDBUF" , 6, 1, 191, "R/W", 0, 0, 0ull, 0ull},
+ {"ADDPKT" , 7, 1, 191, "R/W", 0, 0, 0ull, 0ull},
+ {"RESET" , 8, 1, 191, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 191, "RAZ", 1, 1, 0, 0},
+ {"PRC_PAR0" , 0, 1, 192, "R/W", 0, 0, 0ull, 0ull},
+ {"PRC_PAR1" , 1, 1, 192, "R/W", 0, 0, 0ull, 0ull},
+ {"PRC_PAR2" , 2, 1, 192, "R/W", 0, 0, 0ull, 0ull},
+ {"PRC_PAR3" , 3, 1, 192, "R/W", 0, 0, 0ull, 0ull},
+ {"BP_SUB" , 4, 1, 192, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 192, "RAZ", 1, 1, 0, 0},
+ {"PRC_PAR0" , 0, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PRC_PAR1" , 1, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PRC_PAR2" , 2, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PRC_PAR3" , 3, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BP_SUB" , 4, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 193, "RAZ", 1, 1, 0, 0},
+ {"SKIP_SZ" , 0, 6, 194, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 194, "RAZ", 1, 1, 0, 0},
+ {"MB_SIZE" , 0, 12, 195, "R/W", 0, 0, 32ull, 32ull},
+ {"RESERVED_12_63" , 12, 52, 195, "RAZ", 1, 1, 0, 0},
+ {"PAGE_CNT" , 0, 17, 196, "R/W", 0, 0, 0ull, 0ull},
+ {"BP_ENB" , 17, 1, 196, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 196, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 25, 197, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_25_63" , 25, 39, 197, "RAZ", 1, 1, 0, 0},
+ {"WQE_PCNT" , 0, 7, 198, "RO", 0, 0, 0ull, 0ull},
+ {"PKT_PCNT" , 7, 7, 198, "RO", 0, 0, 0ull, 0ull},
+ {"PFIF_CNT" , 14, 3, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WQEV_CNT" , 17, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"PKTV_CNT" , 18, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 198, "RAZ", 1, 1, 0, 0},
+ {"PASS" , 0, 32, 199, "R/W", 0, 1, 0ull, 0},
+ {"DROP" , 32, 32, 199, "R/W", 0, 1, 0ull, 0},
+ {"Q0_PCNT" , 0, 32, 200, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 200, "RAZ", 1, 1, 0, 0},
+ {"PRT_ENB" , 0, 36, 201, "R/W", 0, 0, 0ull, 0ull},
+ {"AVG_DLY" , 36, 14, 201, "R/W", 0, 1, 0ull, 0},
+ {"PRB_DLY" , 50, 14, 201, "R/W", 0, 0, 0ull, 0ull},
+ {"PRB_CON" , 0, 32, 202, "R/W", 0, 1, 0ull, 0},
+ {"AVG_CON" , 32, 8, 202, "R/W", 0, 1, 0ull, 0},
+ {"NEW_CON" , 40, 8, 202, "R/W", 0, 1, 0ull, 0},
+ {"USE_PCNT" , 48, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_49_63" , 49, 15, 202, "RAZ", 1, 1, 0, 0},
+ {"PAGE_CNT" , 0, 25, 203, "R/W", 1, 0, 0, 0ull},
+ {"PORT" , 25, 6, 203, "R/W", 1, 0, 0, 0ull},
+ {"RESERVED_31_63" , 31, 33, 203, "RAZ", 1, 1, 0, 0},
+ {"PORT_BIT" , 0, 32, 204, "R/W", 0, 0, 4294967295ull, 4294967295ull},
+ {"RESERVED_32_63" , 32, 32, 204, "RAZ", 1, 1, 0, 0},
+ {"WQE_POOL" , 0, 3, 205, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_3_63" , 3, 61, 205, "RAZ", 1, 1, 0, 0},
+ {"MEM0" , 0, 1, 206, "RO", 0, 0, 0ull, 0ull},
+ {"MEM1" , 1, 1, 206, "RO", 0, 0, 0ull, 0ull},
+ {"RRC" , 2, 1, 206, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 206, "RAZ", 1, 1, 0, 0},
+ {"MEM0_ERR" , 0, 7, 207, "R/W", 0, 0, 0ull, 0ull},
+ {"MEM1_ERR" , 7, 7, 207, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_14_63" , 14, 50, 207, "RAZ", 1, 1, 0, 0},
+ {"KED0_SBE" , 0, 1, 208, "R/W", 0, 0, 0ull, 0ull},
+ {"KED0_DBE" , 1, 1, 208, "R/W", 0, 0, 0ull, 0ull},
+ {"KED1_SBE" , 2, 1, 208, "R/W", 0, 0, 0ull, 0ull},
+ {"KED1_DBE" , 3, 1, 208, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 208, "RAZ", 1, 1, 0, 0},
+ {"KED0_SBE" , 0, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
+ {"KED0_DBE" , 1, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
+ {"KED1_SBE" , 2, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
+ {"KED1_DBE" , 3, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 209, "RAZ", 1, 1, 0, 0},
+ {"WLB_DAT" , 0, 4, 210, "RO", 0, 0, 0ull, 0ull},
+ {"STIN_MSK" , 4, 1, 210, "RO", 0, 0, 0ull, 0ull},
+ {"DT" , 5, 1, 210, "RO", 0, 0, 0ull, 0ull},
+ {"DTCNT" , 6, 13, 210, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 210, "RAZ", 0, 0, 0ull, 0ull},
+ {"L2T" , 0, 9, 211, "RO", 0, 0, 0ull, 0ull},
+ {"VAB_VWCF" , 9, 1, 211, "RO", 0, 0, 0ull, 0ull},
+ {"LRF" , 10, 2, 211, "RO", 0, 0, 0ull, 0ull},
+ {"VWDF" , 12, 4, 211, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 211, "RAZ", 0, 0, 0ull, 0ull},
+ {"XRDDAT" , 0, 1, 212, "RO", 0, 0, 0ull, 0ull},
+ {"XRDMSK" , 1, 1, 212, "RO", 0, 0, 0ull, 0ull},
+ {"PICBST" , 2, 1, 212, "RO", 0, 0, 0ull, 0ull},
+ {"IPCBST" , 3, 1, 212, "RO", 0, 0, 0ull, 0ull},
+ {"RHDF" , 4, 4, 212, "RO", 0, 0, 0ull, 0ull},
+ {"RMDF" , 8, 4, 212, "RO", 0, 0, 0ull, 0ull},
+ {"MRB" , 12, 4, 212, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 212, "RAZ", 0, 0, 0ull, 0ull},
+ {"LRF_ARB_MODE" , 0, 1, 213, "R/W", 0, 0, 1ull, 1ull},
+ {"RFB_ARB_MODE" , 1, 1, 213, "R/W", 0, 0, 1ull, 1ull},
+ {"RSP_ARB_MODE" , 2, 1, 213, "R/W", 0, 0, 1ull, 1ull},
+ {"MWF_CRD" , 3, 4, 213, "R/W", 0, 0, 2ull, 2ull},
+ {"IDXALIAS" , 7, 1, 213, "R/W", 0, 0, 0ull, 1ull},
+ {"FPEN" , 8, 1, 213, "R/W", 0, 0, 0ull, 0ull},
+ {"FPEMPTY" , 9, 1, 213, "R/W", 0, 0, 0ull, 0ull},
+ {"FPEXP" , 10, 4, 213, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_14_63" , 14, 50, 213, "RAZ", 1, 1, 0, 0},
+ {"L2T" , 0, 1, 214, "R/W", 0, 0, 0ull, 0ull},
+ {"L2D" , 1, 1, 214, "R/W", 0, 0, 0ull, 0ull},
+ {"FINV" , 2, 1, 214, "R/W", 0, 0, 0ull, 0ull},
+ {"SET" , 3, 3, 214, "R/W", 0, 0, 0ull, 0ull},
+ {"PPNUM" , 6, 4, 214, "R/W", 0, 0, 0ull, 0ull},
+ {"LFB_DMP" , 10, 1, 214, "R/W", 0, 0, 0ull, 0ull},
+ {"LFB_ENUM" , 11, 4, 214, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_15_63" , 15, 49, 214, "RAZ", 0, 0, 0ull, 0ull},
+ {"DT_TAG" , 0, 29, 215, "RO", 0, 0, 0ull, 0ull},
+ {"DT_VLD" , 29, 1, 215, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_30_30" , 30, 1, 215, "RAZ", 0, 0, 0ull, 0ull},
+ {"DTENA" , 31, 1, 215, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 215, "RAZ", 0, 0, 0ull, 0ull},
+ {"LCK_ENA" , 0, 1, 216, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_3" , 1, 3, 216, "RAZ", 0, 0, 0ull, 0ull},
+ {"LCK_BASE" , 4, 27, 216, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_31_63" , 31, 33, 216, "RAZ", 0, 0, 0ull, 0ull},
+ {"LCK_OFFSET" , 0, 10, 217, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_63" , 10, 54, 217, "RAZ", 0, 0, 0ull, 0ull},
+ {"VLD" , 0, 1, 218, "RO", 0, 0, 0ull, 0ull},
+ {"CMD" , 1, 4, 218, "RO", 0, 0, 0ull, 0ull},
+ {"SID" , 5, 9, 218, "RO", 0, 0, 0ull, 0ull},
+ {"VABNUM" , 14, 4, 218, "RO", 0, 0, 0ull, 0ull},
+ {"SET" , 18, 3, 218, "RO", 0, 0, 0ull, 0ull},
+ {"IHD" , 21, 1, 218, "RO", 0, 0, 0ull, 0ull},
+ {"ITL" , 22, 1, 218, "RO", 0, 0, 0ull, 0ull},
+ {"INXT" , 23, 4, 218, "RO", 0, 0, 0ull, 0ull},
+ {"VAM" , 27, 1, 218, "RO", 0, 0, 0ull, 0ull},
+ {"STCFL" , 28, 1, 218, "RO", 0, 0, 0ull, 0ull},
+ {"STINV" , 29, 1, 218, "RO", 0, 0, 0ull, 0ull},
+ {"STPND" , 30, 1, 218, "RO", 0, 0, 0ull, 0ull},
+ {"STCPND" , 31, 1, 218, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 218, "RAZ", 0, 0, 0ull, 0ull},
+ {"VLD" , 0, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTPRB" , 1, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"PRBRTY" , 2, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTMFL" , 3, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTVTM" , 4, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTSTRSC" , 5, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTSTRSP" , 6, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTSTDT" , 7, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTRDA" , 8, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTSTM" , 9, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTWRM" , 10, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTWHF" , 11, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTWHP" , 12, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTDQ" , 13, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTDW" , 14, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"WTRSP" , 15, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"BID" , 16, 2, 219, "RO", 0, 0, 0ull, 0ull},
+ {"DSGOING" , 18, 1, 219, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 219, "RAZ", 0, 0, 0ull, 0ull},
+ {"LFB_IDX" , 0, 10, 220, "RO", 0, 0, 0ull, 0ull},
+ {"LFB_TAG" , 10, 17, 220, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_27_63" , 27, 37, 220, "RAZ", 0, 0, 0ull, 0ull},
+ {"LFB_HWM" , 0, 4, 221, "R/W", 0, 0, 15ull, 15ull},
+ {"STPARTDIS" , 4, 1, 221, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 221, "RAZ", 0, 0, 0ull, 0ull},
+ {"PFCNT0" , 0, 36, 222, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 222, "RAZ", 0, 0, 0ull, 0ull},
+ {"CNT0SEL" , 0, 6, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT0CLR" , 6, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT0ENA" , 7, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT1SEL" , 8, 6, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT1CLR" , 14, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT1ENA" , 15, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT2SEL" , 16, 6, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT2CLR" , 22, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT2ENA" , 23, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT3SEL" , 24, 6, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT3CLR" , 30, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT3ENA" , 31, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT0RDCLR" , 32, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT1RDCLR" , 33, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT2RDCLR" , 34, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT3RDCLR" , 35, 1, 223, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 223, "RAZ", 0, 0, 0ull, 0ull},
+ {"UMSK0" , 0, 8, 224, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK1" , 8, 8, 224, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK2" , 16, 8, 224, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK3" , 24, 8, 224, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 224, "RAZ", 0, 0, 0ull, 0ull},
+ {"UMSK4" , 0, 8, 225, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK5" , 8, 8, 225, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK6" , 16, 8, 225, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK7" , 24, 8, 225, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 225, "RAZ", 0, 0, 0ull, 0ull},
+ {"UMSK8" , 0, 8, 226, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK9" , 8, 8, 226, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK10" , 16, 8, 226, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK11" , 24, 8, 226, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 226, "RAZ", 0, 0, 0ull, 0ull},
+ {"UMSK12" , 0, 8, 227, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK13" , 8, 8, 227, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK14" , 16, 8, 227, "R/W", 0, 0, 0ull, 0ull},
+ {"UMSK15" , 24, 8, 227, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 227, "RAZ", 0, 0, 0ull, 0ull},
+ {"UMSKIOB" , 0, 8, 228, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 228, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q0STAT" , 0, 34, 229, "RO", 0, 0, 0ull, 0ull},
+ {"FTL" , 34, 1, 229, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_35_63" , 35, 29, 229, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q1STAT" , 0, 34, 230, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 230, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q2STAT" , 0, 34, 231, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 231, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q3STAT" , 0, 34, 232, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 232, "RAZ", 0, 0, 0ull, 0ull},
+ {"ECC_ENA" , 0, 1, 233, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_INTENA" , 1, 1, 233, "R/W", 0, 0, 0ull, 1ull},
+ {"DED_INTENA" , 2, 1, 233, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_ERR" , 3, 1, 233, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DED_ERR" , 4, 1, 233, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BMHCLSEL" , 5, 1, 233, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 233, "RAZ", 0, 0, 0ull, 0ull},
+ {"FADR" , 0, 11, 234, "RO", 0, 0, 0ull, 0ull},
+ {"FSET" , 11, 3, 234, "RO", 0, 0, 0ull, 0ull},
+ {"FOWMSK" , 14, 4, 234, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 234, "RAZ", 0, 0, 0ull, 0ull},
+ {"FSYN_OW0" , 0, 10, 235, "RO", 0, 0, 0ull, 0ull},
+ {"FSYN_OW1" , 10, 10, 235, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 235, "RAZ", 0, 0, 0ull, 0ull},
+ {"FSYN_OW2" , 0, 10, 236, "RO", 0, 0, 0ull, 0ull},
+ {"FSYN_OW3" , 10, 10, 236, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 236, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q0FUS" , 0, 34, 237, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 237, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q1FUS" , 0, 34, 238, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 238, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q2FUS" , 0, 34, 239, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 239, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q3FUS" , 0, 34, 240, "RO", 0, 0, 0ull, 0ull},
+ {"CRIP_512K" , 34, 1, 240, "RO", 0, 0, 0ull, 0ull},
+ {"CRIP_256K" , 35, 1, 240, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 240, "RAZ", 0, 0, 0ull, 0ull},
+ {"ECC_ENA" , 0, 1, 241, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_INTENA" , 1, 1, 241, "R/W", 0, 0, 0ull, 1ull},
+ {"DED_INTENA" , 2, 1, 241, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_ERR" , 3, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DED_ERR" , 4, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FSYN" , 5, 6, 241, "RO", 0, 0, 0ull, 0ull},
+ {"FADR" , 11, 10, 241, "RO", 0, 0, 0ull, 0ull},
+ {"FSET" , 21, 3, 241, "RO", 0, 0, 0ull, 0ull},
+ {"LCKERR" , 24, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
+ {"LCK_INTENA" , 25, 1, 241, "R/W", 0, 0, 0ull, 1ull},
+ {"LCKERR2" , 26, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
+ {"LCK_INTENA2" , 27, 1, 241, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_28_63" , 28, 36, 241, "RAZ", 0, 0, 0ull, 0ull},
+ {"RATE" , 0, 8, 242, "R/W", 0, 0, 4ull, 4ull},
+ {"RESERVED_8_63" , 8, 56, 242, "RAZ", 1, 1, 0, 0},
+ {"PHASE" , 0, 7, 243, "R/W", 0, 0, 4ull, 4ull},
+ {"RESERVED_7_63" , 7, 57, 243, "RAZ", 1, 1, 0, 0},
+ {"RATE" , 0, 16, 244, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 244, "RAZ", 1, 1, 0, 0},
+ {"DBG_EN" , 0, 1, 245, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 245, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 1, 246, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_1_63" , 1, 63, 246, "RAZ", 1, 1, 0, 0},
+ {"POLARITY" , 0, 1, 247, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 247, "RAZ", 1, 1, 0, 0},
+ {"PRT_EN" , 0, 8, 248, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 248, "RAZ", 1, 1, 0, 0},
+ {"FORMAT" , 0, 4, 249, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_4_63" , 4, 60, 249, "RAZ", 1, 1, 0, 0},
+ {"STATUS" , 0, 6, 250, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 250, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 6, 251, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 251, "RAZ", 1, 1, 0, 0},
+ {"DAT" , 0, 32, 252, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 252, "RAZ", 1, 1, 0, 0},
+ {"CLR" , 0, 32, 253, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 253, "RAZ", 1, 1, 0, 0},
+ {"SET" , 0, 32, 254, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 254, "RAZ", 1, 1, 0, 0},
+ {"PCTL_DAT" , 0, 4, 255, "R/W", 0, 1, 0ull, 0},
+ {"PCTL_CMD" , 4, 4, 255, "R/W", 0, 1, 0ull, 0},
+ {"PCTL_CLK" , 8, 4, 255, "R/W", 0, 1, 0ull, 0},
+ {"PCTL_CSR" , 12, 4, 255, "R/W", 0, 1, 15ull, 0},
+ {"NCTL_DAT" , 16, 4, 255, "R/W", 0, 1, 0ull, 0},
+ {"NCTL_CMD" , 20, 4, 255, "R/W", 0, 1, 0ull, 0},
+ {"NCTL_CLK" , 24, 4, 255, "R/W", 0, 1, 0ull, 0},
+ {"NCTL_CSR" , 28, 4, 255, "R/W", 0, 1, 15ull, 0},
+ {"RESERVED_32_63" , 32, 32, 255, "RAZ", 0, 0, 0ull, 0ull},
+ {"DIC" , 0, 2, 256, "R/W", 0, 0, 0ull, 0ull},
+ {"QS_DIC" , 2, 2, 256, "R/W", 0, 0, 2ull, 2ull},
+ {"TSKW" , 4, 2, 256, "R/W", 0, 0, 0ull, 1ull},
+ {"SIL_LAT" , 6, 2, 256, "R/W", 0, 0, 1ull, 1ull},
+ {"BPRCH" , 8, 1, 256, "R/W", 0, 1, 0ull, 0},
+ {"FPRCH2" , 9, 1, 256, "R/W", 0, 0, 0ull, 1ull},
+ {"MODE128B" , 10, 1, 256, "R/W", 0, 0, 1ull, 1ull},
+ {"SET_ZERO" , 11, 1, 256, "R/W", 0, 0, 0ull, 0ull},
+ {"INORDER_MRF" , 12, 1, 256, "R/W", 0, 0, 0ull, 0ull},
+ {"INORDER_MWF" , 13, 1, 256, "R/W", 0, 0, 0ull, 0ull},
+ {"R2R_SLOT" , 14, 1, 256, "R/W", 0, 0, 0ull, 0ull},
+ {"RDIMM_ENA" , 15, 1, 256, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_17" , 16, 2, 256, "RAZ", 0, 0, 0ull, 0ull},
+ {"MAX_WRITE_BATCH" , 18, 4, 256, "R/W", 0, 0, 8ull, 8ull},
+ {"XOR_BANK" , 22, 1, 256, "R/W", 0, 0, 0ull, 1ull},
+ {"SLOW_SCF" , 23, 1, 256, "R/W", 0, 0, 0ull, 0ull},
+ {"DDR__PCTL" , 24, 4, 256, "RO", 1, 1, 0, 0},
+ {"DDR__NCTL" , 28, 4, 256, "RO", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 256, "RAZ", 1, 1, 0, 0},
+ {"DCLKCNT_HI" , 0, 32, 257, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 257, "RAZ", 1, 1, 0, 0},
+ {"DCLKCNT_LO" , 0, 32, 258, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 258, "RAZ", 1, 1, 0, 0},
+ {"DDR2" , 0, 1, 259, "R/W", 0, 0, 1ull, 1ull},
+ {"RDQS" , 1, 1, 259, "R/W", 0, 0, 0ull, 0ull},
+ {"DLL90_BYP" , 2, 1, 259, "R/W", 0, 0, 0ull, 0ull},
+ {"DLL90_VLU" , 3, 5, 259, "R/W", 0, 1, 0ull, 0},
+ {"QDLL_ENA" , 8, 1, 259, "R/W", 0, 0, 0ull, 0ull},
+ {"ODT_ENA" , 9, 1, 259, "R/W", 0, 0, 0ull, 0ull},
+ {"DDR2T" , 10, 1, 259, "R/W", 0, 1, 0ull, 0},
+ {"CRIP_MODE" , 11, 1, 259, "R/W", 0, 0, 0ull, 0ull},
+ {"TFAW" , 12, 5, 259, "R/W", 0, 0, 0ull, 9ull},
+ {"DDR_EOF" , 17, 4, 259, "R/W", 0, 0, 2ull, 2ull},
+ {"SILO_HC" , 21, 1, 259, "R/W", 0, 1, 1ull, 0},
+ {"TWR" , 22, 3, 259, "R/W", 0, 0, 3ull, 1ull},
+ {"BWCNT" , 25, 1, 259, "R/W", 0, 0, 0ull, 0ull},
+ {"POCAS" , 26, 1, 259, "R/W", 0, 0, 0ull, 0ull},
+ {"ADDLAT" , 27, 3, 259, "R/W", 0, 0, 0ull, 0ull},
+ {"BURST8" , 30, 1, 259, "R/W", 0, 0, 0ull, 1ull},
+ {"BANK8" , 31, 1, 259, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 259, "RAZ", 0, 0, 0ull, 0ull},
+ {"MRDSYN0" , 0, 8, 260, "RO", 0, 0, 0ull, 0ull},
+ {"MRDSYN1" , 8, 8, 260, "RO", 0, 0, 0ull, 0ull},
+ {"MRDSYN2" , 16, 8, 260, "RO", 0, 0, 0ull, 0ull},
+ {"MRDSYN3" , 24, 8, 260, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 260, "RAZ", 1, 1, 0, 0},
+ {"FCOL" , 0, 12, 261, "RO", 0, 0, 0ull, 0ull},
+ {"FROW" , 12, 14, 261, "RO", 0, 0, 0ull, 0ull},
+ {"FBANK" , 26, 3, 261, "RO", 0, 0, 0ull, 0ull},
+ {"FBUNK" , 29, 1, 261, "RO", 0, 0, 0ull, 0ull},
+ {"FDIMM" , 30, 2, 261, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 261, "RAZ", 1, 1, 0, 0},
+ {"IFBCNT_HI" , 0, 32, 262, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 262, "RAZ", 1, 1, 0, 0},
+ {"IFBCNT_LO" , 0, 32, 263, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 263, "RAZ", 1, 1, 0, 0},
+ {"INIT_START" , 0, 1, 264, "R/W", 0, 0, 0ull, 0ull},
+ {"ECC_ENA" , 1, 1, 264, "R/W", 0, 0, 0ull, 1ull},
+ {"ROW_LSB" , 2, 3, 264, "R/W", 0, 1, 3ull, 0},
+ {"PBANK_LSB" , 5, 4, 264, "R/W", 0, 1, 5ull, 0},
+ {"REF_INT" , 9, 6, 264, "R/W", 0, 0, 1ull, 2ull},
+ {"TCL" , 15, 4, 264, "R/W", 0, 1, 3ull, 0},
+ {"INTR_SEC_ENA" , 19, 1, 264, "R/W", 0, 0, 0ull, 1ull},
+ {"INTR_DED_ENA" , 20, 1, 264, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_ERR" , 21, 4, 264, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DED_ERR" , 25, 4, 264, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BUNK_ENA" , 29, 1, 264, "R/W", 0, 1, 0ull, 0},
+ {"SILO_QC" , 30, 1, 264, "R/W", 0, 1, 0ull, 0},
+ {"RESET" , 31, 1, 264, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 264, "RAZ", 1, 1, 0, 0},
+ {"TRAS" , 0, 5, 265, "R/W", 0, 0, 12ull, 12ull},
+ {"TRCD" , 5, 4, 265, "R/W", 0, 0, 4ull, 4ull},
+ {"TWTR" , 9, 4, 265, "R/W", 0, 0, 2ull, 2ull},
+ {"TRP" , 13, 4, 265, "R/W", 0, 0, 5ull, 4ull},
+ {"TRFC" , 17, 5, 265, "R/W", 0, 0, 6ull, 7ull},
+ {"TMRD" , 22, 3, 265, "R/W", 0, 0, 2ull, 2ull},
+ {"CASLAT" , 25, 3, 265, "R/W", 0, 0, 4ull, 4ull},
+ {"TRRD" , 28, 3, 265, "R/W", 0, 0, 2ull, 2ull},
+ {"RESERVED_31_63" , 31, 33, 265, "RAZ", 1, 1, 0, 0},
+ {"OPSCNT_HI" , 0, 32, 266, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 266, "RAZ", 1, 1, 0, 0},
+ {"OPSCNT_LO" , 0, 32, 267, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 267, "RAZ", 1, 1, 0, 0},
+ {"BWCTL" , 0, 4, 268, "R/W", 0, 0, 0ull, 0ull},
+ {"BWUPD" , 4, 1, 268, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 268, "RAZ", 1, 1, 0, 0},
+ {"RODT_LO0" , 0, 4, 269, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_LO1" , 4, 4, 269, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_LO2" , 8, 4, 269, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_LO3" , 12, 4, 269, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_HI0" , 16, 4, 269, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_HI1" , 20, 4, 269, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_HI2" , 24, 4, 269, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_HI3" , 28, 4, 269, "R/W", 0, 0, 15ull, 15ull},
+ {"RESERVED_32_63" , 32, 32, 269, "RAZ", 1, 1, 0, 0},
+ {"WODT_LO0" , 0, 4, 270, "R/W", 0, 0, 15ull, 15ull},
+ {"WODT_LO1" , 4, 4, 270, "R/W", 0, 0, 15ull, 15ull},
+ {"WODT_LO2" , 8, 4, 270, "R/W", 0, 0, 15ull, 15ull},
+ {"WODT_LO3" , 12, 4, 270, "R/W", 0, 0, 15ull, 15ull},
+ {"WODT_HI0" , 16, 4, 270, "R/W", 0, 0, 15ull, 15ull},
+ {"WODT_HI1" , 20, 4, 270, "R/W", 0, 0, 15ull, 15ull},
+ {"WODT_HI2" , 24, 4, 270, "R/W", 0, 0, 15ull, 15ull},
+ {"WODT_HI3" , 28, 4, 270, "R/W", 0, 0, 15ull, 15ull},
+ {"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
+ {"NCBI" , 0, 1, 271, "RO", 0, 0, 0ull, 0ull},
+ {"LOC" , 1, 1, 271, "RO", 0, 0, 0ull, 0ull},
+ {"NCBO_0" , 2, 1, 271, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 271, "RAZ", 1, 1, 0, 0},
+ {"ADR_ERR" , 0, 1, 272, "R/W1C", 0, 0, 0ull, 0ull},
+ {"WAIT_ERR" , 1, 1, 272, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 272, "RAZ", 1, 1, 0, 0},
+ {"ADR_INT" , 0, 1, 273, "R/W", 0, 1, 0ull, 0},
+ {"WAIT_INT" , 1, 1, 273, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_2_63" , 2, 62, 273, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 274, "RAZ", 1, 1, 0, 0},
+ {"ADR" , 3, 5, 274, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 274, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 275, "RAZ", 1, 1, 0, 0},
+ {"BASE" , 3, 25, 275, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_28_30" , 28, 3, 275, "RAZ", 1, 1, 0, 0},
+ {"EN" , 31, 1, 275, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 64, 276, "R/W", 1, 1, 0, 0},
+ {"BASE" , 0, 16, 277, "R/W", 0, 1, 0ull, 0},
+ {"SIZE" , 16, 12, 277, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_28_29" , 28, 2, 277, "RAZ", 1, 1, 0, 0},
+ {"ORBIT" , 30, 1, 277, "R/W", 0, 1, 0ull, 0},
+ {"EN" , 31, 1, 277, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
+ {"ADR" , 0, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"CE" , 6, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"OE" , 12, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"WE" , 18, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"RD_HLD" , 24, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"WR_HLD" , 30, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"PAUSE" , 36, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"WAIT" , 42, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"PAGE" , 48, 6, 278, "R/W", 0, 1, 63ull, 0},
+ {"RESERVED_54_59" , 54, 6, 278, "RAZ", 1, 1, 0, 0},
+ {"PAGES" , 60, 2, 278, "R/W", 0, 1, 0ull, 0},
+ {"WAITM" , 62, 1, 278, "R/W", 0, 1, 0ull, 0},
+ {"PAGEM" , 63, 1, 278, "R/W", 0, 1, 0ull, 0},
+ {"FIF_THR" , 0, 6, 279, "R/W", 0, 0, 26ull, 26ull},
+ {"RESERVED_6_7" , 6, 2, 279, "RAZ", 1, 1, 0, 0},
+ {"FIF_CNT" , 8, 6, 279, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_14_63" , 14, 50, 279, "RAZ", 1, 1, 0, 0},
+ {"MAN_INFO" , 0, 32, 280, "RO", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 280, "RAZ", 1, 1, 0, 0},
+ {"MAN_INFO" , 0, 32, 281, "RO", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 281, "RAZ", 1, 1, 0, 0},
+ {"PP_DIS" , 0, 16, 282, "RO", 1, 1, 0, 0},
+ {"CHIP_ID" , 16, 8, 282, "RO", 1, 1, 0, 0},
+ {"BIST_DIS" , 24, 1, 282, "RO", 1, 1, 0, 0},
+ {"RST_SHT" , 25, 1, 282, "RO", 1, 1, 0, 0},
+ {"NOCRYPTO" , 26, 1, 282, "RO", 1, 1, 0, 0},
+ {"NOMUL" , 27, 1, 282, "RO", 1, 1, 0, 0},
+ {"NODFA_CP2" , 28, 1, 282, "RO", 1, 1, 0, 0},
+ {"RESERVED_29_63" , 29, 35, 282, "RAZ", 1, 1, 0, 0},
+ {"ICACHE" , 0, 24, 283, "RO", 1, 1, 0, 0},
+ {"NODFA_DTE" , 24, 1, 283, "RO", 1, 1, 0, 0},
+ {"NOZIP" , 25, 1, 283, "RO", 1, 1, 0, 0},
+ {"EFUS_IGN" , 26, 1, 283, "RO", 1, 1, 0, 0},
+ {"EFUS_LCK" , 27, 1, 283, "RO", 1, 1, 0, 0},
+ {"BAR2_EN" , 28, 1, 283, "RO", 1, 1, 0, 0},
+ {"RESERVED_29_63" , 29, 35, 283, "RAZ", 1, 1, 0, 0},
+ {"PROG" , 0, 1, 284, "R/W", 1, 1, 0, 0},
+ {"RESERVED_1_63" , 1, 63, 284, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 7, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_7" , 7, 1, 285, "RAZ", 1, 1, 0, 0},
+ {"EFUSE" , 8, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_11" , 9, 3, 285, "RAZ", 1, 1, 0, 0},
+ {"PEND" , 12, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_13_15" , 13, 3, 285, "RAZ", 1, 1, 0, 0},
+ {"DAT" , 16, 8, 285, "RO", 1, 1, 0, 0},
+ {"RESERVED_24_63" , 24, 40, 285, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 10, 286, "R/W", 1, 1, 0, 0},
+ {"RESERVED_10_63" , 10, 54, 286, "RAZ", 1, 1, 0, 0},
+ {"ST_INT" , 0, 1, 287, "R/W1C", 0, 1, 0ull, 0},
+ {"TS_INT" , 1, 1, 287, "R/W1C", 0, 1, 0ull, 0},
+ {"CORE_INT" , 2, 1, 287, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_3_3" , 3, 1, 287, "RAZ", 1, 1, 0, 0},
+ {"ST_EN" , 4, 1, 287, "R/W", 0, 1, 0ull, 0},
+ {"TS_EN" , 5, 1, 287, "R/W", 0, 1, 0ull, 0},
+ {"CORE_EN" , 6, 1, 287, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_7_63" , 7, 57, 287, "RAZ", 1, 1, 0, 0},
+ {"D" , 0, 32, 288, "R/W", 0, 1, 0ull, 0},
+ {"EOP_IA" , 32, 3, 288, "R/W", 0, 1, 0ull, 0},
+ {"IA" , 35, 5, 288, "R/W", 0, 1, 0ull, 0},
+ {"A" , 40, 10, 288, "R/W", 0, 1, 0ull, 0},
+ {"SCR" , 50, 2, 288, "R/W", 0, 1, 0ull, 0},
+ {"SIZE" , 52, 3, 288, "R/W", 0, 1, 0ull, 0},
+ {"SOVR" , 55, 1, 288, "R/W", 0, 1, 0ull, 0},
+ {"R" , 56, 1, 288, "R/W", 0, 1, 0ull, 0},
+ {"OP" , 57, 4, 288, "R/W", 0, 1, 0ull, 0},
+ {"EIA" , 61, 1, 288, "R/W", 0, 1, 0ull, 0},
+ {"SLONLY" , 62, 1, 288, "R/W", 0, 1, 0ull, 0},
+ {"V" , 63, 1, 288, "RC/W", 0, 1, 0ull, 0},
+ {"D" , 0, 32, 289, "R/W", 0, 1, 0ull, 0},
+ {"IA" , 32, 8, 289, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_40_63" , 40, 24, 289, "RAZ", 1, 1, 0, 0},
+ {"D" , 0, 32, 290, "R/W", 1, 1, 0, 0},
+ {"RESERVED_32_61" , 32, 30, 290, "RAZ", 1, 1, 0, 0},
+ {"V" , 62, 2, 290, "RC/W", 0, 1, 0ull, 0},
+ {"DLH" , 0, 8, 291, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 291, "RAZ", 1, 1, 0, 0},
+ {"DLL" , 0, 8, 292, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 292, "RAZ", 1, 1, 0, 0},
+ {"FAR" , 0, 1, 293, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 293, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 1, 294, "WO", 0, 1, 0ull, 0},
+ {"RXFR" , 1, 1, 294, "WO", 0, 1, 0ull, 0},
+ {"TXFR" , 2, 1, 294, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_3_3" , 3, 1, 294, "RAZ", 0, 1, 0ull, 0},
+ {"TXTRIG" , 4, 2, 294, "WO", 0, 1, 0ull, 0},
+ {"RXTRIG" , 6, 2, 294, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 294, "RAZ", 1, 1, 0, 0},
+ {"HTX" , 0, 1, 295, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 295, "RAZ", 1, 1, 0, 0},
+ {"ERBFI" , 0, 1, 296, "R/W", 0, 1, 0ull, 0},
+ {"ETBEI" , 1, 1, 296, "R/W", 0, 1, 0ull, 0},
+ {"ELSI" , 2, 1, 296, "R/W", 0, 1, 0ull, 0},
+ {"EDSSI" , 3, 1, 296, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_4_6" , 4, 3, 296, "RAZ", 0, 1, 0ull, 0},
+ {"PTIME" , 7, 1, 296, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 296, "RAZ", 1, 1, 0, 0},
+ {"IID" , 0, 4, 297, "RO", 0, 1, 1ull, 0},
+ {"RESERVED_4_5" , 4, 2, 297, "RAZ", 0, 1, 0ull, 0},
+ {"FEN" , 6, 2, 297, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 297, "RAZ", 1, 1, 0, 0},
+ {"CLS" , 0, 2, 298, "R/W", 0, 1, 0ull, 0},
+ {"STOP" , 2, 1, 298, "R/W", 0, 1, 0ull, 0},
+ {"PEN" , 3, 1, 298, "R/W", 0, 1, 0ull, 0},
+ {"EPS" , 4, 1, 298, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_5" , 5, 1, 298, "RAZ", 0, 1, 0ull, 0},
+ {"BRK" , 6, 1, 298, "R/W", 0, 1, 0ull, 0},
+ {"DLAB" , 7, 1, 298, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 298, "RAZ", 1, 1, 0, 0},
+ {"DR" , 0, 1, 299, "RO", 0, 1, 0ull, 0},
+ {"OE" , 1, 1, 299, "RC", 0, 1, 0ull, 0},
+ {"PE" , 2, 1, 299, "RC", 0, 1, 0ull, 0},
+ {"FE" , 3, 1, 299, "RC", 0, 1, 0ull, 0},
+ {"BI" , 4, 1, 299, "RC", 0, 1, 0ull, 0},
+ {"THRE" , 5, 1, 299, "RO", 0, 1, 1ull, 0},
+ {"TEMT" , 6, 1, 299, "RO", 0, 1, 1ull, 0},
+ {"FERR" , 7, 1, 299, "RC", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 299, "RAZ", 1, 1, 0, 0},
+ {"DTR" , 0, 1, 300, "R/W", 0, 1, 0ull, 0},
+ {"RTS" , 1, 1, 300, "R/W", 0, 1, 0ull, 0},
+ {"OUT1" , 2, 1, 300, "R/W", 0, 1, 0ull, 0},
+ {"OUT2" , 3, 1, 300, "R/W", 0, 1, 0ull, 0},
+ {"LOOP" , 4, 1, 300, "R/W", 0, 1, 0ull, 0},
+ {"AFCE" , 5, 1, 300, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_6_63" , 6, 58, 300, "RAZ", 0, 1, 0ull, 0},
+ {"DCTS" , 0, 1, 301, "RC", 0, 1, 0ull, 0},
+ {"DDSR" , 1, 1, 301, "RC", 0, 1, 0ull, 0},
+ {"TERI" , 2, 1, 301, "RC", 0, 1, 0ull, 0},
+ {"DDCD" , 3, 1, 301, "RC", 0, 1, 0ull, 0},
+ {"CTS" , 4, 1, 301, "RO", 1, 1, 0, 0},
+ {"DSR" , 5, 1, 301, "RO", 0, 1, 0ull, 0},
+ {"RI" , 6, 1, 301, "RO", 0, 1, 0ull, 0},
+ {"DCD" , 7, 1, 301, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 301, "RAZ", 1, 1, 0, 0},
+ {"RBR" , 0, 8, 302, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 302, "RAZ", 1, 1, 0, 0},
+ {"RFL" , 0, 7, 303, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_7_63" , 7, 57, 303, "RAZ", 1, 1, 0, 0},
+ {"RFWD" , 0, 8, 304, "WO", 0, 1, 0ull, 0},
+ {"RFPE" , 8, 1, 304, "WO", 0, 1, 0ull, 0},
+ {"RFFE" , 9, 1, 304, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_10_63" , 10, 54, 304, "RAZ", 1, 1, 0, 0},
+ {"SBCR" , 0, 1, 305, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 305, "RAZ", 1, 1, 0, 0},
+ {"SCR" , 0, 8, 306, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 306, "RAZ", 1, 1, 0, 0},
+ {"SFE" , 0, 1, 307, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 307, "RAZ", 1, 1, 0, 0},
+ {"USR" , 0, 1, 308, "WO", 0, 1, 0ull, 0},
+ {"SRFR" , 1, 1, 308, "WO", 0, 1, 0ull, 0},
+ {"STFR" , 2, 1, 308, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_3_63" , 3, 61, 308, "RAZ", 1, 1, 0, 0},
+ {"SRT" , 0, 2, 309, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_2_63" , 2, 62, 309, "RAZ", 1, 1, 0, 0},
+ {"SRTS" , 0, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 310, "RAZ", 1, 1, 0, 0},
+ {"STT" , 0, 2, 311, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_2_63" , 2, 62, 311, "RAZ", 1, 1, 0, 0},
+ {"TFL" , 0, 7, 312, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_7_63" , 7, 57, 312, "RAZ", 1, 1, 0, 0},
+ {"TFR" , 0, 8, 313, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 313, "RAZ", 1, 1, 0, 0},
+ {"THR" , 0, 8, 314, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 314, "RAZ", 1, 1, 0, 0},
+ {"BUSY" , 0, 1, 315, "RO", 0, 1, 0ull, 0},
+ {"TFNF" , 1, 1, 315, "RO", 0, 1, 1ull, 0},
+ {"TFE" , 2, 1, 315, "RO", 0, 1, 1ull, 0},
+ {"RFNE" , 3, 1, 315, "RO", 0, 1, 0ull, 0},
+ {"RFF" , 4, 1, 315, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 315, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 316, "RAZ", 1, 1, 0, 0},
+ {"BADDR" , 3, 61, 316, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_0_2" , 0, 3, 317, "RAZ", 1, 1, 0, 0},
+ {"BADDR" , 3, 61, 317, "R/W", 0, 1, 0ull, 0},
+ {"DPI_BS" , 0, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"PDF_BS" , 1, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"DOB_BS" , 2, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"NUS_BS" , 3, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"POS_BS" , 4, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"POF3_BS" , 5, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"POF2_BS" , 6, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"POF1_BS" , 7, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"POF0_BS" , 8, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"PIG_BS" , 9, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"PGF_BS" , 10, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"RDNL_BS" , 11, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"PCAD_BS" , 12, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"PCAC_BS" , 13, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"RDN_BS" , 14, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"PCN_BS" , 15, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"PCNC_BS" , 16, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"RDP_BS" , 17, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"DIF_BS" , 18, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"CSR_BS" , 19, 1, 318, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 318, "RAZ", 1, 1, 0, 0},
+ {"BSIZE" , 0, 16, 319, "R/W", 0, 1, 1024ull, 0},
+ {"ISIZE" , 16, 7, 319, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_23_63" , 23, 41, 319, "RAZ", 1, 1, 0, 0},
+ {"TIMER" , 0, 10, 320, "R/W", 0, 0, 0ull, 50ull},
+ {"RESERVED_10_31" , 10, 22, 320, "RAZ", 0, 0, 0ull, 0ull},
+ {"MAX_WORD" , 32, 5, 320, "R/W", 0, 0, 2ull, 0ull},
+ {"RESERVED_37_39" , 37, 3, 320, "RAZ", 0, 0, 0ull, 0ull},
+ {"WAIT_COM" , 40, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"PCI_WDIS" , 41, 1, 320, "R/W", 0, 0, 0ull, 0ull},
+ {"INS0_64B" , 42, 1, 320, "R/W", 0, 1, 0ull, 0},
+ {"INS1_64B" , 43, 1, 320, "R/W", 0, 1, 0ull, 0},
+ {"INS2_64B" , 44, 1, 320, "R/W", 0, 1, 0ull, 0},
+ {"INS3_64B" , 45, 1, 320, "R/W", 0, 1, 0ull, 0},
+ {"INS0_ENB" , 46, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"INS1_ENB" , 47, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"INS2_ENB" , 48, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"INS3_ENB" , 49, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"OUT0_ENB" , 50, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"OUT1_ENB" , 51, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"OUT2_ENB" , 52, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"OUT3_ENB" , 53, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"DIS_PNIW" , 54, 1, 320, "R/W", 0, 0, 0ull, 1ull},
+ {"CHIP_REV" , 55, 8, 320, "RO", 1, 1, 0, 0},
+ {"RESERVED_63_63" , 63, 1, 320, "RAZ", 1, 1, 0, 0},
+ {"DBG_SEL" , 0, 16, 321, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 321, "RAZ", 1, 1, 0, 0},
+ {"CSIZE" , 0, 14, 322, "R/W", 0, 1, 0ull, 0},
+ {"LP_ENB" , 14, 1, 322, "R/W", 0, 0, 0ull, 1ull},
+ {"HP_ENB" , 15, 1, 322, "R/W", 0, 0, 0ull, 1ull},
+ {"O_MODE" , 16, 1, 322, "R/W", 0, 0, 0ull, 1ull},
+ {"O_ES" , 17, 2, 322, "R/W", 0, 1, 0ull, 0},
+ {"O_NS" , 19, 1, 322, "R/W", 0, 1, 0ull, 0},
+ {"O_RO" , 20, 1, 322, "R/W", 0, 1, 0ull, 0},
+ {"O_ADD1" , 21, 1, 322, "R/W", 0, 0, 0ull, 1ull},
+ {"FPA_QUE" , 22, 3, 322, "R/W", 0, 1, 0ull, 0},
+ {"DWB_ICHK" , 25, 9, 322, "R/W", 0, 1, 0ull, 0},
+ {"DWB_DENB" , 34, 1, 322, "R/W", 0, 0, 0ull, 1ull},
+ {"B0_LEND" , 35, 1, 322, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 322, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 32, 323, "RO", 0, 0, 0ull, 0ull},
+ {"FCNT" , 32, 7, 323, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_39_63" , 39, 25, 323, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 36, 324, "RO", 0, 1, 0ull, 0},
+ {"STATE" , 36, 4, 324, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_40_63" , 40, 24, 324, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 32, 325, "RO", 0, 0, 0ull, 0ull},
+ {"FCNT" , 32, 7, 325, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_39_63" , 39, 25, 325, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 36, 326, "RO", 0, 1, 0ull, 0},
+ {"STATE" , 36, 4, 326, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_40_63" , 40, 24, 326, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 16, 327, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 327, "RAZ", 1, 1, 0, 0},
+ {"SADDR" , 0, 36, 328, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 328, "RAZ", 1, 1, 0, 0},
+ {"ROR" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
+ {"ESR" , 1, 2, 329, "R/W", 0, 1, 0ull, 0},
+ {"NSR" , 3, 1, 329, "R/W", 0, 1, 0ull, 0},
+ {"USE_CSR" , 4, 1, 329, "R/W", 0, 0, 0ull, 1ull},
+ {"D_ROR" , 5, 1, 329, "R/W", 0, 1, 0ull, 0},
+ {"D_ESR" , 6, 2, 329, "R/W", 0, 1, 0ull, 0},
+ {"D_NSR" , 8, 1, 329, "R/W", 0, 1, 0ull, 0},
+ {"PBP_DHI" , 9, 13, 329, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_22_63" , 22, 42, 329, "RAZ", 1, 1, 0, 0},
+ {"RML_RTO" , 0, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"RML_WTO" , 1, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"PCI_RSL" , 2, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"PO0_2SML" , 3, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"PO1_2SML" , 4, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"PO2_2SML" , 5, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"PO3_2SML" , 6, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I0_RTOUT" , 7, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I1_RTOUT" , 8, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I2_RTOUT" , 9, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I3_RTOUT" , 10, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I0_OVERF" , 11, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I1_OVERF" , 12, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I2_OVERF" , 13, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I3_OVERF" , 14, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P0_RTOUT" , 15, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P1_RTOUT" , 16, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P2_RTOUT" , 17, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P3_RTOUT" , 18, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P0_PERR" , 19, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P1_PERR" , 20, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P2_PERR" , 21, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P3_PERR" , 22, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"G0_RTOUT" , 23, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"G1_RTOUT" , 24, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"G2_RTOUT" , 25, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"G3_RTOUT" , 26, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P0_PPERR" , 27, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P1_PPERR" , 28, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P2_PPERR" , 29, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P3_PPERR" , 30, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P0_PTOUT" , 31, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P1_PTOUT" , 32, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P2_PTOUT" , 33, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P3_PTOUT" , 34, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I0_PPERR" , 35, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I1_PPERR" , 36, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I2_PPERR" , 37, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"I3_PPERR" , 38, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"WIN_RTO" , 39, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"P_DPERR" , 40, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBDMA" , 41, 1, 330, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_42_63" , 42, 22, 330, "RAZ", 1, 1, 0, 0},
+ {"RML_RTO" , 0, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RML_WTO" , 1, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCI_RSL" , 2, 1, 331, "RO", 0, 0, 0ull, 0ull},
+ {"PO0_2SML" , 3, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PO1_2SML" , 4, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PO2_2SML" , 5, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PO3_2SML" , 6, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I0_RTOUT" , 7, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I1_RTOUT" , 8, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I2_RTOUT" , 9, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I3_RTOUT" , 10, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I0_OVERF" , 11, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I1_OVERF" , 12, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I2_OVERF" , 13, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I3_OVERF" , 14, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P0_RTOUT" , 15, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P1_RTOUT" , 16, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P2_RTOUT" , 17, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P3_RTOUT" , 18, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P0_PERR" , 19, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P1_PERR" , 20, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P2_PERR" , 21, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P3_PERR" , 22, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"G0_RTOUT" , 23, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"G1_RTOUT" , 24, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"G2_RTOUT" , 25, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"G3_RTOUT" , 26, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P0_PPERR" , 27, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P1_PPERR" , 28, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P2_PPERR" , 29, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P3_PPERR" , 30, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P0_PTOUT" , 31, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P1_PTOUT" , 32, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P2_PTOUT" , 33, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P3_PTOUT" , 34, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I0_PPERR" , 35, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I1_PPERR" , 36, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I2_PPERR" , 37, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I3_PPERR" , 38, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"WIN_RTO" , 39, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P_DPERR" , 40, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"IOBDMA" , 41, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_42_63" , 42, 22, 331, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 16, 332, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 332, "RAZ", 1, 1, 0, 0},
+ {"SADDR" , 0, 36, 333, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 333, "RAZ", 1, 1, 0, 0},
+ {"BA" , 0, 28, 334, "R/W", 0, 1, 0ull, 0},
+ {"ROW" , 28, 1, 334, "R/W", 0, 1, 0ull, 0},
+ {"ROR" , 29, 1, 334, "R/W", 0, 1, 0ull, 0},
+ {"NSW" , 30, 1, 334, "R/W", 0, 1, 0ull, 0},
+ {"NSR" , 31, 1, 334, "R/W", 0, 1, 0ull, 0},
+ {"ESW" , 32, 2, 334, "R/W", 0, 1, 0ull, 0},
+ {"ESR" , 34, 2, 334, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 334, "RAZ", 1, 1, 0, 0},
+ {"INT_VEC" , 0, 64, 335, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SIZE" , 0, 32, 336, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 336, "RAZ", 1, 1, 0, 0},
+ {"ROR_SL0" , 0, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"NSR_SL0" , 1, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"ESR_SL0" , 2, 2, 337, "R/W", 0, 1, 0ull, 0},
+ {"ROR_SL1" , 4, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"NSR_SL1" , 5, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"ESR_SL1" , 6, 2, 337, "R/W", 0, 1, 0ull, 0},
+ {"ROR_SL2" , 8, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"NSR_SL2" , 9, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"ESR_SL2" , 10, 2, 337, "R/W", 0, 1, 0ull, 0},
+ {"ROR_SL3" , 12, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"NSR_SL3" , 13, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"ESR_SL3" , 14, 2, 337, "R/W", 0, 1, 0ull, 0},
+ {"IPTR_O0" , 16, 1, 337, "R/W", 0, 0, 0ull, 1ull},
+ {"IPTR_O1" , 17, 1, 337, "R/W", 0, 0, 0ull, 1ull},
+ {"IPTR_O2" , 18, 1, 337, "R/W", 0, 0, 0ull, 1ull},
+ {"IPTR_O3" , 19, 1, 337, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_20_23" , 20, 4, 337, "RAZ", 0, 0, 0ull, 0ull},
+ {"O0_CSRM" , 24, 1, 337, "R/W", 0, 0, 0ull, 1ull},
+ {"O1_CSRM" , 25, 1, 337, "R/W", 0, 0, 0ull, 1ull},
+ {"O2_CSRM" , 26, 1, 337, "R/W", 0, 0, 0ull, 1ull},
+ {"O3_CSRM" , 27, 1, 337, "R/W", 0, 0, 0ull, 1ull},
+ {"O0_RO" , 28, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"O0_NS" , 29, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"O0_ES" , 30, 2, 337, "R/W", 0, 1, 0ull, 0},
+ {"O1_RO" , 32, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"O1_NS" , 33, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"O1_ES" , 34, 2, 337, "R/W", 0, 1, 0ull, 0},
+ {"O2_RO" , 36, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"O2_NS" , 37, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"O2_ES" , 38, 2, 337, "R/W", 0, 1, 0ull, 0},
+ {"O3_RO" , 40, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"O3_NS" , 41, 1, 337, "R/W", 0, 1, 0ull, 0},
+ {"O3_ES" , 42, 2, 337, "R/W", 0, 1, 0ull, 0},
+ {"P0_BMODE" , 44, 1, 337, "R/W", 0, 0, 0ull, 0ull},
+ {"P1_BMODE" , 45, 1, 337, "R/W", 0, 0, 0ull, 0ull},
+ {"P2_BMODE" , 46, 1, 337, "R/W", 0, 0, 0ull, 0ull},
+ {"P3_BMODE" , 47, 1, 337, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_48_63" , 48, 16, 337, "RAZ", 1, 1, 0, 0},
+ {"NADDR" , 0, 61, 338, "RO", 0, 1, 0ull, 0},
+ {"STATE" , 61, 2, 338, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_63_63" , 63, 1, 338, "RAZ", 1, 1, 0, 0},
+ {"NADDR" , 0, 61, 339, "RO", 0, 1, 0ull, 0},
+ {"STATE" , 61, 3, 339, "RO", 0, 0, 0ull, 0ull},
+ {"AVAIL" , 0, 32, 340, "RO", 0, 0, 0ull, 0ull},
+ {"FCNT" , 32, 6, 340, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_38_63" , 38, 26, 340, "RAZ", 1, 1, 0, 0},
+ {"AVAIL" , 0, 32, 341, "RO", 0, 0, 0ull, 0ull},
+ {"FCNT" , 32, 5, 341, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_37_63" , 37, 27, 341, "RAZ", 1, 1, 0, 0},
+ {"RD_BRST" , 0, 7, 342, "R/W", 0, 0, 17ull, 64ull},
+ {"WR_BRST" , 7, 7, 342, "R/W", 0, 0, 16ull, 64ull},
+ {"RESERVED_14_63" , 14, 50, 342, "RAZ", 1, 1, 0, 0},
+ {"PARK_DEV" , 0, 3, 343, "R/W", 0, 1, 0ull, 0},
+ {"PARK_MOD" , 3, 1, 343, "R/W", 0, 1, 0ull, 0},
+ {"EN" , 4, 1, 343, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 343, "RAZ", 1, 1, 0, 0},
+ {"CMD_SIZE" , 0, 11, 344, "R/W", 0, 0, 9ull, 9ull},
+ {"RESERVED_11_63" , 11, 53, 344, "RAZ", 1, 1, 0, 0},
+ {"RSV_A" , 0, 6, 345, "R/W", 0, 1, 0ull, 0},
+ {"SKP_LEN" , 6, 7, 345, "R/W", 0, 1, 0ull, 0},
+ {"RSV_B" , 13, 1, 345, "R/W", 0, 1, 0ull, 0},
+ {"PAR_MODE" , 14, 2, 345, "R/W", 0, 1, 0ull, 0},
+ {"RSV_C" , 16, 5, 345, "R/W", 0, 1, 0ull, 0},
+ {"USE_IHDR" , 21, 1, 345, "R/W", 0, 1, 0ull, 0},
+ {"RSV_D" , 22, 6, 345, "R/W", 0, 1, 0ull, 0},
+ {"RSKP_LEN" , 28, 7, 345, "R/W", 0, 1, 8ull, 0},
+ {"RSV_E" , 35, 1, 345, "R/W", 0, 1, 0ull, 0},
+ {"RPARMODE" , 36, 2, 345, "R/W", 0, 1, 0ull, 0},
+ {"RSV_F" , 38, 5, 345, "R/W", 0, 1, 0ull, 0},
+ {"PBP" , 43, 1, 345, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_44_63" , 44, 20, 345, "RAZ", 1, 1, 0, 0},
+ {"RSV_A" , 0, 6, 346, "R/W", 0, 1, 0ull, 0},
+ {"SKP_LEN" , 6, 7, 346, "R/W", 0, 1, 0ull, 0},
+ {"RSV_B" , 13, 1, 346, "R/W", 0, 1, 0ull, 0},
+ {"PAR_MODE" , 14, 2, 346, "R/W", 0, 1, 0ull, 0},
+ {"RSV_C" , 16, 5, 346, "R/W", 0, 1, 0ull, 0},
+ {"USE_IHDR" , 21, 1, 346, "R/W", 0, 1, 0ull, 0},
+ {"RSV_D" , 22, 6, 346, "R/W", 0, 1, 0ull, 0},
+ {"RSKP_LEN" , 28, 7, 346, "R/W", 0, 1, 8ull, 0},
+ {"RSV_E" , 35, 1, 346, "R/W", 0, 1, 0ull, 0},
+ {"RPARMODE" , 36, 2, 346, "R/W", 0, 1, 0ull, 0},
+ {"RSV_F" , 38, 5, 346, "R/W", 0, 1, 0ull, 0},
+ {"PBP" , 43, 1, 346, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_44_63" , 44, 20, 346, "RAZ", 1, 1, 0, 0},
+ {"RSV_A" , 0, 6, 347, "R/W", 0, 1, 0ull, 0},
+ {"SKP_LEN" , 6, 7, 347, "R/W", 0, 1, 0ull, 0},
+ {"RSV_B" , 13, 1, 347, "R/W", 0, 1, 0ull, 0},
+ {"PAR_MODE" , 14, 2, 347, "R/W", 0, 1, 0ull, 0},
+ {"RSV_C" , 16, 5, 347, "R/W", 0, 1, 0ull, 0},
+ {"USE_IHDR" , 21, 1, 347, "R/W", 0, 1, 0ull, 0},
+ {"RSV_D" , 22, 6, 347, "R/W", 0, 1, 0ull, 0},
+ {"RSKP_LEN" , 28, 7, 347, "R/W", 0, 1, 8ull, 0},
+ {"RSV_E" , 35, 1, 347, "R/W", 0, 1, 0ull, 0},
+ {"RPARMODE" , 36, 2, 347, "R/W", 0, 1, 0ull, 0},
+ {"RSV_F" , 38, 5, 347, "R/W", 0, 1, 0ull, 0},
+ {"PBP" , 43, 1, 347, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_44_63" , 44, 20, 347, "RAZ", 1, 1, 0, 0},
+ {"RSV_A" , 0, 6, 348, "R/W", 0, 1, 0ull, 0},
+ {"SKP_LEN" , 6, 7, 348, "R/W", 0, 1, 0ull, 0},
+ {"RSV_B" , 13, 1, 348, "R/W", 0, 1, 0ull, 0},
+ {"PAR_MODE" , 14, 2, 348, "R/W", 0, 1, 0ull, 0},
+ {"RSV_C" , 16, 5, 348, "R/W", 0, 1, 0ull, 0},
+ {"USE_IHDR" , 21, 1, 348, "R/W", 0, 1, 0ull, 0},
+ {"RSV_D" , 22, 6, 348, "R/W", 0, 1, 0ull, 0},
+ {"RSKP_LEN" , 28, 7, 348, "R/W", 0, 1, 8ull, 0},
+ {"RSV_E" , 35, 1, 348, "R/W", 0, 1, 0ull, 0},
+ {"RPARMODE" , 36, 2, 348, "R/W", 0, 1, 0ull, 0},
+ {"RSV_F" , 38, 5, 348, "R/W", 0, 1, 0ull, 0},
+ {"PBP" , 43, 1, 348, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_44_63" , 44, 20, 348, "RAZ", 1, 1, 0, 0},
+ {"ENB" , 0, 4, 349, "R/W", 0, 0, 15ull, 15ull},
+ {"BP_ON" , 4, 4, 349, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 349, "RAZ", 1, 1, 0, 0},
+ {"MIO" , 0, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"GMX0" , 1, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"GMX1" , 2, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"NPI" , 3, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"KEY" , 4, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"FPA" , 5, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"DFA" , 6, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"ZIP" , 7, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_8" , 8, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"IPD" , 9, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"PKO" , 10, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"TIM" , 11, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"POW" , 12, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_13" , 13, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_14" , 14, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_15" , 15, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"L2C" , 16, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"LMC" , 17, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"SPX0" , 18, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"SPX1" , 19, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"PIP" , 20, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_21" , 21, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"ASX0" , 22, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"ASX1" , 23, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_24" , 24, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_25" , 25, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_26" , 26, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_27" , 27, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_28" , 28, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_29" , 29, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"IOB" , 30, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_31" , 31, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 350, "RAZ", 1, 1, 0, 0},
+ {"SIZE" , 0, 32, 351, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 351, "RAZ", 1, 1, 0, 0},
+ {"TIME" , 0, 32, 352, "R/W", 0, 0, 0ull, 131072ull},
+ {"RESERVED_32_63" , 32, 32, 352, "RAZ", 1, 1, 0, 0},
+ {"ADDR_V" , 0, 1, 353, "R/W", 0, 1, 0ull, 0},
+ {"END_SWP" , 1, 2, 353, "R/W", 0, 1, 0ull, 0},
+ {"CA" , 3, 1, 353, "R/W", 0, 0, 0ull, 0ull},
+ {"ADDR_IDX" , 4, 14, 353, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_18_31" , 18, 14, 353, "RAZ", 1, 1, 0, 0},
+ {"VENDID" , 0, 16, 354, "RO", 0, 0, 6013ull, 6013ull},
+ {"DEVID" , 16, 16, 354, "RO", 0, 0, 4ull, 4ull},
+ {"ISAE" , 0, 1, 355, "RO", 0, 0, 0ull, 0ull},
+ {"MSAE" , 1, 1, 355, "R/W", 0, 0, 0ull, 1ull},
+ {"ME" , 2, 1, 355, "R/W", 0, 0, 0ull, 1ull},
+ {"SCSE" , 3, 1, 355, "RO", 0, 0, 0ull, 0ull},
+ {"MWICE" , 4, 1, 355, "R/W", 0, 0, 0ull, 0ull},
+ {"VPS" , 5, 1, 355, "RO", 0, 0, 0ull, 0ull},
+ {"PEE" , 6, 1, 355, "R/W", 0, 0, 0ull, 1ull},
+ {"ADS" , 7, 1, 355, "RO", 0, 0, 0ull, 0ull},
+ {"SEE" , 8, 1, 355, "R/W", 0, 0, 0ull, 1ull},
+ {"FBBE" , 9, 1, 355, "R/W", 0, 0, 0ull, 1ull},
+ {"I_DIS" , 10, 1, 355, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_18" , 11, 8, 355, "RAZ", 1, 1, 0, 0},
+ {"I_STAT" , 19, 1, 355, "RO", 0, 0, 0ull, 0ull},
+ {"CLE" , 20, 1, 355, "RO", 0, 0, 1ull, 1ull},
+ {"M66" , 21, 1, 355, "RO", 0, 0, 1ull, 1ull},
+ {"RESERVED_22_22" , 22, 1, 355, "RAZ", 1, 1, 0, 0},
+ {"FBB" , 23, 1, 355, "RO", 0, 1, 1ull, 0},
+ {"MDPE" , 24, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DEVT" , 25, 2, 355, "RO", 0, 0, 1ull, 1ull},
+ {"STA" , 27, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RTA" , 28, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RMA" , 29, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SSE" , 30, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DPE" , 31, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RID" , 0, 8, 356, "RO", 0, 0, 1ull, 1ull},
+ {"CC" , 8, 24, 356, "RO", 0, 0, 1048576ull, 1048576ull},
+ {"CLS" , 0, 8, 357, "R/W", 0, 1, 0ull, 0},
+ {"LT" , 8, 8, 357, "R/W", 0, 0, 0ull, 64ull},
+ {"HT" , 16, 8, 357, "RO", 0, 0, 0ull, 0ull},
+ {"BCOD" , 24, 4, 357, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_28_29" , 28, 2, 357, "RAZ", 1, 1, 0, 0},
+ {"BRB" , 30, 1, 357, "R/W", 0, 0, 0ull, 0ull},
+ {"BCAP" , 31, 1, 357, "RO", 0, 0, 0ull, 0ull},
+ {"MSPC" , 0, 1, 358, "RO", 0, 0, 0ull, 0ull},
+ {"TYP" , 1, 2, 358, "RO", 0, 0, 2ull, 2ull},
+ {"PF" , 3, 1, 358, "RO", 0, 0, 1ull, 1ull},
+ {"LBASEZ" , 4, 8, 358, "RO", 0, 0, 0ull, 0ull},
+ {"LBASE" , 12, 20, 358, "R/W", 0, 1, 0ull, 0},
+ {"HBASE" , 0, 32, 359, "R/W", 0, 1, 0ull, 0},
+ {"MSPC" , 0, 1, 360, "RO", 0, 0, 0ull, 0ull},
+ {"TYP" , 1, 2, 360, "RO", 0, 0, 2ull, 2ull},
+ {"PF" , 3, 1, 360, "RO", 0, 0, 1ull, 1ull},
+ {"LBASEZ" , 4, 23, 360, "RO", 0, 0, 0ull, 0ull},
+ {"LBASE" , 27, 5, 360, "R/W", 0, 1, 0ull, 0},
+ {"HBASE" , 0, 32, 361, "R/W", 0, 1, 0ull, 0},
+ {"MSPC" , 0, 1, 362, "RO", 0, 0, 0ull, 0ull},
+ {"TYP" , 1, 2, 362, "RO", 0, 0, 2ull, 2ull},
+ {"PF" , 3, 1, 362, "RO", 0, 0, 1ull, 1ull},
+ {"LBASEZ" , 4, 28, 362, "RO", 0, 0, 0ull, 0ull},
+ {"HBASEZ" , 0, 7, 363, "RO", 0, 0, 0ull, 0ull},
+ {"HBASE" , 7, 25, 363, "R/W", 0, 1, 0ull, 0},
+ {"CISP" , 0, 32, 364, "RO", 0, 0, 0ull, 0ull},
+ {"SSVID" , 0, 16, 365, "RO", 0, 0, 6013ull, 6013ull},
+ {"SSID" , 16, 16, 365, "RO", 0, 0, 1ull, 1ull},
+ {"ERBAR_EN" , 0, 1, 366, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_10" , 1, 10, 366, "RAZ", 1, 1, 0, 0},
+ {"ERBARZ" , 11, 5, 366, "RO", 0, 0, 0ull, 0ull},
+ {"ERBAR" , 16, 16, 366, "R/W", 0, 1, 0ull, 0},
+ {"CP" , 0, 8, 367, "RO", 0, 0, 224ull, 224ull},
+ {"RESERVED_8_31" , 8, 24, 367, "RAZ", 1, 1, 0, 0},
+ {"IL" , 0, 8, 368, "R/W", 0, 1, 0ull, 0},
+ {"INTA" , 8, 8, 368, "RO", 0, 0, 1ull, 1ull},
+ {"MG" , 16, 8, 368, "RO", 0, 0, 64ull, 64ull},
+ {"ML" , 24, 8, 368, "RO", 0, 0, 64ull, 64ull},
+ {"MLTD" , 0, 1, 369, "R/W", 0, 0, 0ull, 1ull},
+ {"TSWC" , 1, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_2" , 2, 1, 369, "RAZ", 1, 1, 0, 0},
+ {"DPPMR" , 3, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"PBE" , 4, 12, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TILT" , 16, 4, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TSLTE" , 20, 3, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TMAE" , 23, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TWTAE" , 24, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TWSEN" , 25, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TWSEI" , 26, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TRTAE" , 27, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TRDRS" , 28, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"RDSATI" , 29, 1, 369, "R/W", 0, 0, 0ull, 0ull},
+ {"TRDARD" , 30, 1, 369, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TRDNPR" , 31, 1, 369, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TSCME" , 0, 32, 370, "R/W1C", 0, 1, 0ull, 0},
+ {"TDSRPS" , 0, 32, 371, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TDOMC" , 0, 5, 372, "R/W", 0, 0, 1ull, 1ull},
+ {"TIDOMC" , 5, 1, 372, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_6" , 6, 1, 372, "RAZ", 1, 1, 0, 0},
+ {"TIBDE" , 7, 1, 372, "R/W", 0, 0, 0ull, 0ull},
+ {"TIBCD" , 8, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_10" , 9, 2, 372, "RAZ", 1, 1, 0, 0},
+ {"TMAPES" , 11, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TMDPES" , 12, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TMSE" , 13, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TMEI" , 14, 1, 372, "RO", 0, 0, 0ull, 0ull},
+ {"TECI" , 15, 1, 372, "RO", 0, 0, 0ull, 0ull},
+ {"TMES" , 16, 8, 372, "RO", 0, 0, 0ull, 0ull},
+ {"MDRRMC" , 24, 3, 372, "R/W", 0, 0, 2ull, 2ull},
+ {"MDRIMC" , 27, 1, 372, "R/W", 0, 0, 0ull, 0ull},
+ {"MDRE" , 28, 1, 372, "R/W", 0, 0, 0ull, 0ull},
+ {"MDWE" , 29, 1, 372, "R/W", 0, 0, 0ull, 0ull},
+ {"MRBCI" , 30, 1, 372, "R/W", 0, 0, 0ull, 0ull},
+ {"MRBCM" , 31, 1, 372, "R/W", 0, 0, 1ull, 1ull},
+ {"MDSP" , 0, 32, 373, "R/W1C", 0, 1, 0ull, 0},
+ {"SCMRE" , 0, 32, 374, "R/W1C", 0, 1, 0ull, 0},
+ {"MTTV" , 0, 8, 375, "R/W", 0, 0, 0ull, 0ull},
+ {"MRV" , 8, 8, 375, "R/W", 0, 0, 0ull, 255ull},
+ {"MTTA" , 16, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MRA" , 17, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FLUSH" , 18, 1, 375, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_19_24" , 19, 6, 375, "RAZ", 1, 1, 0, 0},
+ {"MAC" , 25, 7, 375, "R/W", 0, 0, 0ull, 0ull},
+ {"PXCID" , 0, 8, 376, "RO", 0, 0, 7ull, 7ull},
+ {"NCP" , 8, 8, 376, "RO", 0, 0, 232ull, 232ull},
+ {"DPERE" , 16, 1, 376, "R/W", 0, 0, 0ull, 0ull},
+ {"ROE" , 17, 1, 376, "R/W", 0, 0, 1ull, 1ull},
+ {"MMBC" , 18, 2, 376, "R/W", 0, 0, 0ull, 0ull},
+ {"MOST" , 20, 3, 376, "R/W", 0, 0, 3ull, 3ull},
+ {"RESERVED_23_31" , 23, 9, 376, "RAZ", 1, 1, 0, 0},
+ {"FN" , 0, 3, 377, "RO", 0, 0, 0ull, 0ull},
+ {"DN" , 3, 5, 377, "RO", 0, 0, 31ull, 31ull},
+ {"BN" , 8, 8, 377, "RO", 0, 1, 17ull, 0},
+ {"W64" , 16, 1, 377, "RO", 0, 0, 1ull, 1ull},
+ {"M133" , 17, 1, 377, "RO", 0, 0, 1ull, 1ull},
+ {"SCD" , 18, 1, 377, "R/W1C", 0, 1, 0ull, 0},
+ {"USC" , 19, 1, 377, "R/W1C", 0, 1, 0ull, 0},
+ {"DC" , 20, 1, 377, "RO", 0, 0, 0ull, 0ull},
+ {"MMRBCD" , 21, 2, 377, "RO", 0, 0, 2ull, 2ull},
+ {"MOSTD" , 23, 3, 377, "RO", 0, 0, 3ull, 3ull},
+ {"MCRSD" , 26, 3, 377, "RO", 0, 0, 7ull, 7ull},
+ {"SCEMR" , 29, 1, 377, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_30_31" , 30, 2, 377, "RAZ", 1, 1, 0, 0},
+ {"PMCID" , 0, 8, 378, "RO", 0, 0, 1ull, 1ull},
+ {"NCP" , 8, 8, 378, "RO", 0, 0, 240ull, 240ull},
+ {"PCIMIV" , 16, 3, 378, "RO", 0, 0, 2ull, 2ull},
+ {"PMEC" , 19, 1, 378, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_20" , 20, 1, 378, "RAZ", 1, 1, 0, 0},
+ {"DSI" , 21, 1, 378, "RO", 0, 0, 0ull, 0ull},
+ {"AUXC" , 22, 3, 378, "RO", 0, 0, 0ull, 0ull},
+ {"D1S" , 25, 1, 378, "RO", 0, 0, 0ull, 0ull},
+ {"D2S" , 26, 1, 378, "RO", 0, 0, 0ull, 0ull},
+ {"PMES" , 27, 5, 378, "RO", 0, 0, 0ull, 0ull},
+ {"PS" , 0, 2, 379, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_7" , 2, 6, 379, "RAZ", 1, 1, 0, 0},
+ {"PMEENS" , 8, 1, 379, "R/W", 0, 0, 0ull, 0ull},
+ {"PMDS" , 9, 4, 379, "R/W", 0, 0, 0ull, 0ull},
+ {"PMEDSIA" , 13, 2, 379, "RO", 0, 0, 0ull, 0ull},
+ {"PMESS" , 15, 1, 379, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_21" , 16, 6, 379, "RAZ", 1, 1, 0, 0},
+ {"BD3H" , 22, 1, 379, "RO", 0, 0, 0ull, 0ull},
+ {"BPCCEN" , 23, 1, 379, "RO", 0, 0, 0ull, 0ull},
+ {"PMDIA" , 24, 8, 379, "RO", 0, 0, 0ull, 0ull},
+ {"MSICID" , 0, 8, 380, "RO", 0, 0, 5ull, 5ull},
+ {"NCP" , 8, 8, 380, "RO", 0, 0, 0ull, 0ull},
+ {"MSIEN" , 16, 1, 380, "R/W", 0, 0, 0ull, 0ull},
+ {"MMC" , 17, 3, 380, "RO", 0, 0, 0ull, 0ull},
+ {"MME" , 20, 3, 380, "R/W", 0, 0, 0ull, 0ull},
+ {"M64" , 23, 1, 380, "RO", 0, 0, 1ull, 1ull},
+ {"RESERVED_24_31" , 24, 8, 380, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_1" , 0, 2, 381, "RAZ", 1, 1, 0, 0},
+ {"MSI31T2" , 2, 30, 381, "R/W", 0, 1, 0ull, 0},
+ {"MSI" , 0, 32, 382, "R/W", 0, 1, 0ull, 0},
+ {"MSIMD" , 0, 16, 383, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_31" , 16, 16, 383, "RAZ", 1, 1, 0, 0},
+ {"BAR2_CAX" , 0, 1, 384, "R/W", 0, 0, 0ull, 0ull},
+ {"BAR2_ESX" , 1, 2, 384, "R/W", 0, 1, 0ull, 0},
+ {"BAR2_ENB" , 3, 1, 384, "R/W", 0, 0, 0ull, 1ull},
+ {"TSR_HWM" , 4, 3, 384, "R/W", 0, 1, 1ull, 0},
+ {"PMO_FPC" , 7, 3, 384, "R/W", 0, 0, 0ull, 0ull},
+ {"PMO_AMOD" , 10, 1, 384, "R/W", 0, 0, 0ull, 0ull},
+ {"B12_BIST" , 11, 1, 384, "RO", 0, 0, 0ull, 0ull},
+ {"AP_64AD" , 12, 1, 384, "RO", 1, 1, 0, 0},
+ {"AP_PCIX" , 13, 1, 384, "RO", 1, 1, 0, 0},
+ {"RESERVED_14_14" , 14, 1, 384, "RAZ", 0, 0, 0ull, 0ull},
+ {"EN_WFILT" , 15, 1, 384, "R/W", 0, 0, 0ull, 1ull},
+ {"SCM" , 16, 1, 384, "RO", 0, 1, 0ull, 0},
+ {"SCMTYP" , 17, 1, 384, "RO", 0, 1, 0ull, 0},
+ {"BAR2PRES" , 18, 1, 384, "R/W", 1, 1, 0, 0},
+ {"ERST_N" , 19, 1, 384, "RO", 0, 0, 1ull, 1ull},
+ {"RESERVED_20_31" , 20, 12, 384, "RAZ", 1, 1, 0, 0},
+ {"INC_VAL" , 0, 16, 385, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_31" , 16, 16, 385, "RAZ", 1, 1, 0, 0},
+ {"DMA_CNT" , 0, 32, 386, "R/W", 0, 0, 0ull, 0ull},
+ {"PKT_CNT" , 0, 32, 387, "R/W", 0, 1, 0ull, 0},
+ {"DMA_TIME" , 0, 32, 388, "R/W", 0, 1, 0ull, 0},
+ {"ICNT" , 0, 32, 389, "RO", 0, 0, 0ull, 0ull},
+ {"ITR_WABT" , 0, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IMR_WABT" , 1, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IMR_WTTO" , 2, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"ITR_ABT" , 3, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IMR_ABT" , 4, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IMR_TTO" , 5, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IMSI_PER" , 6, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IMSI_TABT" , 7, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IMSI_MABT" , 8, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IMSC_MSG" , 9, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"ITSR_ABT" , 10, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"ISERR" , 11, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IAPERR" , 12, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IDPERR" , 13, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RWR" , 14, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RRD" , 15, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IRSL_INT" , 16, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IPCNT0" , 17, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IPCNT1" , 18, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IPCNT2" , 19, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IPCNT3" , 20, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IPTIME0" , 21, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IPTIME1" , 22, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IPTIME2" , 23, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IPTIME3" , 24, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IDCNT0" , 25, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IDCNT1" , 26, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IDTIME0" , 27, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"IDTIME1" , 28, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"DMA0_FI" , 29, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"DMA1_FI" , 30, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"WIN_WR" , 31, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"ILL_WR" , 32, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RD" , 33, 1, 390, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_34_63" , 34, 30, 390, "RAZ", 1, 1, 0, 0},
+ {"RTR_WABT" , 0, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RMR_WABT" , 1, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RMR_WTTO" , 2, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RTR_ABT" , 3, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RMR_ABT" , 4, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RMR_TTO" , 5, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RMSI_PER" , 6, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RMSI_TABT" , 7, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RMSI_MABT" , 8, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RMSC_MSG" , 9, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RTSR_ABT" , 10, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RSERR" , 11, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RAPERR" , 12, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RDPERR" , 13, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RWR" , 14, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RRD" , 15, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RRSL_INT" , 16, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RPCNT0" , 17, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RPCNT1" , 18, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RPCNT2" , 19, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RPCNT3" , 20, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RPTIME0" , 21, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RPTIME1" , 22, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RPTIME2" , 23, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RPTIME3" , 24, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RDCNT0" , 25, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RDCNT1" , 26, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RDTIME0" , 27, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RDTIME1" , 28, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"DMA0_FI" , 29, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"DMA1_FI" , 30, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"WIN_WR" , 31, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"ILL_WR" , 32, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RD" , 33, 1, 391, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_34_63" , 34, 30, 391, "RAZ", 1, 1, 0, 0},
+ {"TR_WABT" , 0, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_WABT" , 1, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_WTTO" , 2, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TR_ABT" , 3, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_ABT" , 4, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_TTO" , 5, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_PER" , 6, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_TABT" , 7, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_MABT" , 8, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSC_MSG" , 9, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TSR_ABT" , 10, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SERR" , 11, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"APERR" , 12, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DPERR" , 13, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RWR" , 14, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RRD" , 15, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RSL_INT" , 16, 1, 392, "RO", 0, 0, 0ull, 0ull},
+ {"PCNT0" , 17, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCNT1" , 18, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCNT2" , 19, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCNT3" , 20, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME0" , 21, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME1" , 22, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME2" , 23, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME3" , 24, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DCNT0" , 25, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DCNT1" , 26, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTIME0" , 27, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTIME1" , 28, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DMA0_FI" , 29, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DMA1_FI" , 30, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"WIN_WR" , 31, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_WR" , 32, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RD" , 33, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 392, "RAZ", 1, 1, 0, 0},
+ {"TR_WABT" , 0, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_WABT" , 1, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_WTTO" , 2, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TR_ABT" , 3, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_ABT" , 4, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_TTO" , 5, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_PER" , 6, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_TABT" , 7, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_MABT" , 8, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSC_MSG" , 9, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TSR_ABT" , 10, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SERR" , 11, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"APERR" , 12, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DPERR" , 13, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RWR" , 14, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RRD" , 15, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RSL_INT" , 16, 1, 393, "RO", 0, 0, 0ull, 0ull},
+ {"PCNT0" , 17, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCNT1" , 18, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCNT2" , 19, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCNT3" , 20, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME0" , 21, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME1" , 22, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME2" , 23, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME3" , 24, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DCNT0" , 25, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DCNT1" , 26, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTIME0" , 27, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTIME1" , 28, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DMA0_FI" , 29, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DMA1_FI" , 30, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"WIN_WR" , 31, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_WR" , 32, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RD" , 33, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 393, "RAZ", 1, 1, 0, 0},
+ {"INTR" , 0, 6, 394, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_6_31" , 6, 26, 394, "R/W", 1, 1, 0, 0},
+ {"PTR_CNT" , 0, 16, 395, "R/W", 0, 1, 0ull, 0},
+ {"PKT_CNT" , 16, 16, 395, "R/W", 0, 1, 0ull, 0},
+ {"PKT_CNT" , 0, 32, 396, "RO", 0, 0, 0ull, 0ull},
+ {"PKT_CNT" , 0, 32, 397, "R/W", 0, 1, 0ull, 0},
+ {"PKT_TIME" , 0, 32, 398, "R/W", 0, 1, 0ull, 0},
+ {"PREFETCH" , 0, 3, 399, "R/W", 0, 0, 0ull, 2ull},
+ {"MIN_DATA" , 3, 6, 399, "R/W", 0, 0, 0ull, 4ull},
+ {"RESERVED_9_31" , 9, 23, 399, "RAZ", 1, 1, 0, 0},
+ {"PREFETCH" , 0, 3, 400, "R/W", 0, 0, 0ull, 3ull},
+ {"MIN_DATA" , 3, 6, 400, "R/W", 0, 0, 0ull, 6ull},
+ {"RESERVED_9_31" , 9, 23, 400, "RAZ", 1, 1, 0, 0},
+ {"PREFETCH" , 0, 3, 401, "R/W", 0, 0, 0ull, 3ull},
+ {"MIN_DATA" , 3, 6, 401, "R/W", 0, 0, 0ull, 6ull},
+ {"RESERVED_9_31" , 9, 23, 401, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 31, 402, "R/W", 0, 0, 10000ull, 10000ull},
+ {"ENB" , 31, 1, 402, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_32_63" , 32, 32, 402, "RAZ", 1, 1, 0, 0},
+ {"SCM" , 0, 32, 403, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 403, "RAZ", 1, 1, 0, 0},
+ {"TSR" , 0, 36, 404, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 404, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 405, "RAZ", 1, 1, 0, 0},
+ {"RD_ADDR" , 3, 45, 405, "R/W", 0, 1, 0ull, 0},
+ {"IOBIT" , 48, 1, 405, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_49_63" , 49, 15, 405, "RAZ", 1, 1, 0, 0},
+ {"RD_DATA" , 0, 64, 406, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_0_2" , 0, 3, 407, "RAZ", 1, 1, 0, 0},
+ {"WR_ADDR" , 3, 45, 407, "R/W", 0, 1, 0ull, 0},
+ {"IOBIT" , 48, 1, 407, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_49_63" , 49, 15, 407, "RAZ", 1, 1, 0, 0},
+ {"WR_DATA" , 0, 64, 408, "R/W", 0, 1, 0ull, 0},
+ {"WR_MASK" , 0, 8, 409, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 409, "RAZ", 1, 1, 0, 0},
+ {"LOWATER" , 0, 5, 410, "R/W", 0, 0, 4ull, 4ull},
+ {"RESERVED_5_7" , 5, 3, 410, "RAZ", 0, 1, 0ull, 0},
+ {"HIWATER" , 8, 5, 410, "R/W", 0, 0, 24ull, 24ull},
+ {"RESERVED_13_62" , 13, 50, 410, "RAZ", 0, 1, 0ull, 0},
+ {"BCKPRS" , 63, 1, 410, "RO", 0, 0, 0ull, 0ull},
+ {"BIST" , 0, 18, 411, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 411, "RAZ", 1, 1, 0, 0},
+ {"REFLECT" , 0, 1, 412, "R/W", 0, 0, 1ull, 1ull},
+ {"INVRES" , 1, 1, 412, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_2_63" , 2, 62, 412, "RAZ", 1, 1, 0, 0},
+ {"IV" , 0, 32, 413, "R/W", 0, 0, 1185899593ull, 1185899593ull},
+ {"RESERVED_32_63" , 32, 32, 413, "RAZ", 1, 1, 0, 0},
+ {"DPRT" , 0, 16, 414, "R/W", 0, 0, 0ull, 0ull},
+ {"UDP" , 16, 1, 414, "R/W", 0, 0, 0ull, 0ull},
+ {"TCP" , 17, 1, 414, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 414, "RAZ", 1, 1, 0, 0},
+ {"NIP_SHF" , 0, 3, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_7" , 3, 5, 415, "RAZ", 1, 1, 0, 0},
+ {"RAW_SHF" , 8, 3, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_15" , 11, 5, 415, "RAZ", 1, 1, 0, 0},
+ {"MAX_L2" , 16, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_UDP" , 17, 1, 415, "R/W", 0, 0, 1ull, 1ull},
+ {"TAG_SYN" , 18, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 415, "RAZ", 1, 1, 0, 0},
+ {"IP_CHK" , 0, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"IP_MAL" , 1, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"IP_HOP" , 2, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"IP4_OPTS" , 3, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"IP6_EEXT" , 4, 2, 416, "R/W", 0, 0, 1ull, 3ull},
+ {"RESERVED_6_7" , 6, 2, 416, "RAZ", 0, 1, 0ull, 0},
+ {"L4_MAL" , 8, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"L4_PRT" , 9, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"L4_CHK" , 10, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"L4_LEN" , 11, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"TCP_FLAG" , 12, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"L2_MAL" , 13, 1, 416, "R/W", 0, 0, 1ull, 1ull},
+ {"VS_QOS" , 14, 1, 416, "R/W", 0, 0, 0ull, 0ull},
+ {"VS_WQE" , 15, 1, 416, "R/W", 0, 0, 0ull, 0ull},
+ {"IGNRS" , 16, 1, 416, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_63" , 17, 47, 416, "RAZ", 0, 1, 0ull, 0},
+ {"PKTDRP" , 0, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"CRCERR" , 1, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"BCKPRS" , 2, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"PRTNXA" , 3, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"BADTAG" , 4, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"SKPRUNT" , 5, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"TODOOVR" , 6, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"FEPERR" , 7, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"BEPERR" , 8, 1, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 417, "RAZ", 1, 1, 0, 0},
+ {"PKTDRP" , 0, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CRCERR" , 1, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BCKPRS" , 2, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PRTNXA" , 3, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BADTAG" , 4, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SKPRUNT" , 5, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TODOOVR" , 6, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FEPERR" , 7, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BEPERR" , 8, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 418, "RAZ", 1, 1, 0, 0},
+ {"OFFSET" , 0, 3, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 419, "RAZ", 1, 1, 0, 0},
+ {"SKIP" , 0, 7, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_7" , 7, 1, 420, "RAZ", 1, 1, 0, 0},
+ {"MODE" , 8, 2, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_11" , 10, 2, 420, "RAZ", 1, 1, 0, 0},
+ {"CRC_EN" , 12, 1, 420, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_13_15" , 13, 3, 420, "RAZ", 1, 1, 0, 0},
+ {"QOS_VLAN" , 16, 1, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"QOS_DIFF" , 17, 1, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_19" , 18, 2, 420, "RAZ", 0, 0, 0ull, 0ull},
+ {"QOS_WAT" , 20, 4, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"QOS" , 24, 3, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_27_27" , 27, 1, 420, "RAZ", 1, 1, 0, 0},
+ {"GRP_WAT" , 28, 4, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"INST_HDR" , 32, 1, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"DYN_RS" , 33, 1, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"TAG_INC" , 34, 2, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"RAWDRP" , 36, 1, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_37_63" , 37, 27, 420, "RAZ", 1, 1, 0, 0},
+ {"GRP" , 0, 4, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"NON_TAG_TYPE" , 4, 2, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_TAG_TYPE" , 6, 2, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_TAG_TYPE" , 8, 2, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"TCP4_TAG_TYPE" , 10, 2, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"TCP6_TAG_TYPE" , 12, 2, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_SRC_FLAG" , 14, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_SRC_FLAG" , 15, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_DST_FLAG" , 16, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_DST_FLAG" , 17, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_PCTL_FLAG" , 18, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_NXTH_FLAG" , 19, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_SPRT_FLAG" , 20, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_SPRT_FLAG" , 21, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_DPRT_FLAG" , 22, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_DPRT_FLAG" , 23, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"INC_PRT_FLAG" , 24, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"INC_VLAN" , 25, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"INC_VS" , 26, 2, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"TAG_MODE" , 28, 2, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_30_30" , 30, 1, 421, "RAZ", 0, 0, 0ull, 0ull},
+ {"GRPTAG" , 31, 1, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"GRPTAGMASK" , 32, 4, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"GRPTAGBASE" , 36, 4, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_40_63" , 40, 24, 421, "RAZ", 1, 1, 0, 0},
+ {"QOS" , 0, 3, 422, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 422, "RAZ", 1, 1, 0, 0},
+ {"QOS" , 0, 3, 423, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 423, "RAZ", 1, 1, 0, 0},
+ {"MATCH_VALUE" , 0, 16, 424, "R/W", 0, 0, 0ull, 0ull},
+ {"MATCH_TYPE" , 16, 2, 424, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_19" , 18, 2, 424, "RAZ", 1, 1, 0, 0},
+ {"QOS" , 20, 3, 424, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_23" , 23, 1, 424, "RAZ", 1, 1, 0, 0},
+ {"GRP" , 24, 4, 424, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_28_31" , 28, 4, 424, "RAZ", 1, 1, 0, 0},
+ {"MASK" , 32, 16, 424, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_48_63" , 48, 16, 424, "RAZ", 1, 1, 0, 0},
+ {"WORD" , 0, 56, 425, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_56_63" , 56, 8, 425, "RAZ", 1, 1, 0, 0},
+ {"DRP_OCTS" , 0, 32, 426, "R/W", 0, 1, 0ull, 0},
+ {"DRP_PKTS" , 32, 32, 426, "R/W", 0, 1, 0ull, 0},
+ {"OCTS" , 0, 48, 427, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 427, "RAZ", 1, 1, 0, 0},
+ {"RAW" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
+ {"PKTS" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
+ {"MCST" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
+ {"BCST" , 32, 32, 429, "R/W", 0, 1, 0ull, 0},
+ {"H64" , 0, 32, 430, "R/W", 0, 1, 0ull, 0},
+ {"H65TO127" , 32, 32, 430, "R/W", 0, 1, 0ull, 0},
+ {"H128TO255" , 0, 32, 431, "R/W", 0, 1, 0ull, 0},
+ {"H256TO511" , 32, 32, 431, "R/W", 0, 1, 0ull, 0},
+ {"H512TO1023" , 0, 32, 432, "R/W", 0, 1, 0ull, 0},
+ {"H1024TO1518" , 32, 32, 432, "R/W", 0, 1, 0ull, 0},
+ {"H1519" , 0, 32, 433, "R/W", 0, 1, 0ull, 0},
+ {"FCS" , 32, 32, 433, "R/W", 0, 1, 0ull, 0},
+ {"UNDERSZ" , 0, 32, 434, "R/W", 0, 1, 0ull, 0},
+ {"FRAG" , 32, 32, 434, "R/W", 0, 1, 0ull, 0},
+ {"OVERSZ" , 0, 32, 435, "R/W", 0, 1, 0ull, 0},
+ {"JABBER" , 32, 32, 435, "R/W", 0, 1, 0ull, 0},
+ {"RDCLR" , 0, 1, 436, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_1_63" , 1, 63, 436, "RAZ", 1, 1, 0, 0},
+ {"ERRS" , 0, 16, 437, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 437, "RAZ", 1, 1, 0, 0},
+ {"OCTS" , 0, 48, 438, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 438, "RAZ", 1, 1, 0, 0},
+ {"PKTS" , 0, 32, 439, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 439, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 8, 440, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 440, "RAZ", 1, 1, 0, 0},
+ {"MASK" , 0, 16, 441, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 441, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 16, 442, "R/W", 0, 0, 0ull, 0ull},
+ {"DST" , 16, 16, 442, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 442, "RAZ", 1, 1, 0, 0},
+ {"ENTRY" , 0, 62, 443, "RO", 1, 1, 0, 0},
+ {"RESERVED_62_62" , 62, 1, 443, "RAZ", 1, 1, 0, 0},
+ {"VAL" , 63, 1, 443, "RO", 1, 1, 0, 0},
+ {"COUNT" , 0, 32, 444, "R/W1C", 1, 0, 0, 0ull},
+ {"RESERVED_32_63" , 32, 32, 444, "RAZ", 1, 1, 0, 0},
+ {"COUNT" , 0, 48, 445, "R/W1C", 1, 0, 0, 0ull},
+ {"RESERVED_48_63" , 48, 16, 445, "RAZ", 1, 1, 0, 0},
+ {"SIZE" , 0, 16, 446, "RO", 1, 0, 0, 0ull},
+ {"SEGS" , 16, 6, 446, "RO", 1, 0, 0, 0ull},
+ {"CMD" , 22, 14, 446, "RO", 1, 0, 0, 0ull},
+ {"FAU" , 36, 28, 446, "RO", 1, 0, 0, 0ull},
+ {"PTR" , 0, 40, 447, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 40, 16, 447, "RO", 1, 0, 0, 0ull},
+ {"POOL" , 56, 3, 447, "RO", 1, 0, 0, 0ull},
+ {"BACK" , 59, 4, 447, "RO", 1, 0, 0, 0ull},
+ {"I" , 63, 1, 447, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 0, 16, 448, "RO", 1, 0, 0, 0ull},
+ {"SEGS" , 16, 6, 448, "RO", 1, 0, 0, 0ull},
+ {"CMD" , 22, 14, 448, "RO", 1, 0, 0, 0ull},
+ {"FAU" , 36, 28, 448, "RO", 1, 0, 0, 0ull},
+ {"PTR" , 0, 40, 449, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 40, 16, 449, "RO", 1, 0, 0, 0ull},
+ {"POOL" , 56, 3, 449, "RO", 1, 0, 0, 0ull},
+ {"BACK" , 59, 4, 449, "RO", 1, 0, 0, 0ull},
+ {"I" , 63, 1, 449, "RO", 1, 0, 0, 0ull},
+ {"DATA" , 0, 64, 450, "RO", 1, 0, 0, 0ull},
+ {"WIDX2" , 0, 17, 451, "RO", 1, 0, 0, 0ull},
+ {"RIDX2" , 17, 17, 451, "RO", 1, 0, 0, 0ull},
+ {"WIDX" , 34, 17, 451, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_51_63" , 51, 13, 451, "RAZ", 1, 0, 0, 0ull},
+ {"RIDX" , 0, 17, 452, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_17_63" , 17, 47, 452, "RAZ", 1, 0, 0, 0ull},
+ {"PTR" , 0, 40, 453, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 40, 16, 453, "RO", 1, 0, 0, 0ull},
+ {"POOL" , 56, 3, 453, "RO", 1, 0, 0, 0ull},
+ {"BACK" , 59, 4, 453, "RO", 1, 0, 0, 0ull},
+ {"I" , 63, 1, 453, "RO", 1, 0, 0, 0ull},
+ {"PTR" , 0, 40, 454, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 40, 16, 454, "RO", 1, 0, 0, 0ull},
+ {"POOL" , 56, 3, 454, "RO", 1, 0, 0, 0ull},
+ {"BACK" , 59, 4, 454, "RO", 1, 0, 0, 0ull},
+ {"I" , 63, 1, 454, "RO", 1, 0, 0, 0ull},
+ {"DATA" , 0, 64, 455, "RO", 1, 0, 0, 0ull},
+ {"MAJOR" , 0, 4, 456, "RO", 1, 0, 0, 0ull},
+ {"MINOR" , 4, 2, 456, "RO", 1, 0, 0, 0ull},
+ {"WAIT" , 6, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"QID_BASE" , 7, 7, 456, "RO", 1, 0, 0, 0ull},
+ {"QID_OFF" , 14, 3, 456, "RO", 1, 0, 0, 0ull},
+ {"QCB_RIDX" , 17, 5, 456, "RO", 1, 0, 0, 0ull},
+ {"QOS" , 22, 3, 456, "RO", 1, 0, 0, 0ull},
+ {"ACTIVE" , 25, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"CHK_MODE" , 26, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_27_27" , 27, 1, 456, "RAZ", 1, 0, 0, 0ull},
+ {"CBUF_FRE" , 28, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"XFER_DWR" , 29, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"XFER_WOR" , 30, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"UID" , 31, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"CMND_SIZ" , 32, 16, 456, "RO", 1, 0, 0, 0ull},
+ {"DWRI_CNT" , 48, 13, 456, "RO", 1, 0, 0, 0ull},
+ {"DWRI_LEN" , 61, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"DWRI_SOP" , 62, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"DWRI_MOD" , 63, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"DWRI_MOD" , 0, 2, 457, "RO", 1, 0, 0, 0ull},
+ {"DWRI_UID" , 2, 1, 457, "RO", 1, 0, 0, 0ull},
+ {"DWRI_CHK" , 3, 1, 457, "RO", 1, 0, 0, 0ull},
+ {"WORK_MIN" , 4, 3, 457, "RO", 1, 0, 0, 0ull},
+ {"STATIC_P" , 7, 1, 457, "RO", 1, 0, 0, 0ull},
+ {"QID_OFFM" , 8, 3, 457, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_11_63" , 11, 53, 457, "RAZ", 1, 0, 0, 0ull},
+ {"SIZE" , 0, 16, 458, "RO", 1, 0, 0, 0ull},
+ {"START" , 16, 33, 458, "RO", 1, 0, 0, 0ull},
+ {"DWB" , 49, 9, 458, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_58_63" , 58, 6, 458, "RAZ", 1, 0, 0, 0ull},
+ {"QCB_RIDX" , 0, 6, 459, "RO", 1, 0, 0, 0ull},
+ {"QCB_WIDX" , 6, 6, 459, "RO", 1, 0, 0, 0ull},
+ {"BUF_PTR" , 12, 33, 459, "RO", 1, 0, 0, 0ull},
+ {"BUF_SIZ" , 45, 13, 459, "RO", 1, 0, 0, 0ull},
+ {"TAIL" , 58, 1, 459, "RO", 1, 0, 0, 0ull},
+ {"QOS" , 59, 5, 459, "RO", 1, 0, 0, 0ull},
+ {"QOS" , 0, 3, 460, "RO", 1, 0, 0, 0ull},
+ {"STATIC_Q" , 3, 1, 460, "RO", 1, 0, 0, 0ull},
+ {"S_TAIL" , 4, 1, 460, "RO", 1, 0, 0, 0ull},
+ {"STATIC_P" , 5, 1, 460, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_6_7" , 6, 2, 460, "RAZ", 1, 0, 0, 0ull},
+ {"DOORBELL" , 8, 20, 460, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_28_63" , 28, 36, 460, "RAZ", 1, 0, 0, 0ull},
+ {"QUEUE" , 0, 7, 461, "R/W", 1, 0, 0, 0ull},
+ {"PORT" , 7, 6, 461, "WR0", 1, 0, 0, 0ull},
+ {"INDEX" , 13, 3, 461, "WR0", 1, 0, 0, 0ull},
+ {"TAIL" , 16, 1, 461, "R/W", 1, 0, 0, 0ull},
+ {"BUF_PTR" , 17, 36, 461, "R/W", 1, 0, 0, 0ull},
+ {"QOS_MASK" , 53, 8, 461, "R/W", 1, 0, 0, 0ull},
+ {"STATIC_Q" , 61, 1, 461, "WR0", 1, 0, 0, 0ull},
+ {"STATIC_P" , 62, 1, 461, "WR0", 1, 0, 0, 0ull},
+ {"S_TAIL" , 63, 1, 461, "WR0", 1, 0, 0, 0ull},
+ {"QID" , 0, 7, 462, "R/W", 1, 0, 0, 0ull},
+ {"PID" , 7, 6, 462, "WR0", 1, 0, 0, 0ull},
+ {"RESERVED_13_52" , 13, 40, 462, "RAZ", 1, 0, 0, 0ull},
+ {"QOS_MASK" , 53, 8, 462, "R/W", 1, 0, 0, 0ull},
+ {"RESERVED_61_63" , 61, 3, 462, "RAZ", 1, 0, 0, 0ull},
+ {"PSB" , 0, 7, 463, "RO", 1, 0, 0, 0ull},
+ {"PDB" , 7, 4, 463, "RO", 1, 0, 0, 0ull},
+ {"QCB" , 11, 2, 463, "RO", 1, 0, 0, 0ull},
+ {"QSB" , 13, 2, 463, "RO", 1, 0, 0, 0ull},
+ {"CHK" , 15, 1, 463, "RO", 1, 0, 0, 0ull},
+ {"CRC" , 16, 1, 463, "RO", 1, 0, 0, 0ull},
+ {"OUT" , 17, 1, 463, "RO", 1, 0, 0, 0ull},
+ {"NCB" , 18, 1, 463, "RO", 1, 0, 0, 0ull},
+ {"WIF" , 19, 1, 463, "RO", 1, 0, 0, 0ull},
+ {"RIF" , 20, 1, 463, "RO", 1, 0, 0, 0ull},
+ {"COUNT" , 21, 1, 463, "RO", 1, 0, 0, 0ull},
+ {"PSB2" , 22, 5, 463, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_27_63" , 27, 37, 463, "RAZ", 1, 0, 0, 0ull},
+ {"SIZE" , 0, 13, 464, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_13_19" , 13, 7, 464, "RAZ", 0, 0, 0ull, 0ull},
+ {"POOL" , 20, 3, 464, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_63" , 23, 41, 464, "RAZ", 1, 0, 0, 0ull},
+ {"REFIN" , 0, 1, 465, "R/W", 0, 0, 1ull, 1ull},
+ {"INVRES" , 1, 1, 465, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_2_63" , 2, 62, 465, "RAZ", 1, 1, 0, 0},
+ {"ENABLE" , 0, 32, 466, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 466, "RAZ", 1, 0, 0, 0ull},
+ {"IV" , 0, 32, 467, "R/W", 0, 0, 1185899593ull, 1185899593ull},
+ {"RESERVED_32_63" , 32, 32, 467, "RAZ", 1, 1, 0, 0},
+ {"ASSERTS" , 0, 17, 468, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_63" , 17, 47, 468, "RAZ", 1, 0, 0, 0ull},
+ {"PARITY" , 0, 1, 469, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DOORBELL" , 1, 1, 469, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 469, "RAZ", 1, 0, 0, 0ull},
+ {"ENA_PKO" , 0, 1, 470, "R/W", 0, 0, 0ull, 0ull},
+ {"ENA_DWB" , 1, 1, 470, "R/W", 0, 0, 0ull, 0ull},
+ {"STORE_BE" , 2, 1, 470, "R/W", 0, 0, 0ull, 0ull},
+ {"RESET" , 3, 1, 470, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 470, "RAZ", 1, 0, 0, 0ull},
+ {"MODE0" , 0, 3, 471, "R/W", 0, 0, 0ull, 0ull},
+ {"MODE1" , 3, 3, 471, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 471, "RAZ", 1, 0, 0, 0ull},
+ {"PARITY" , 0, 1, 472, "R/W", 0, 0, 0ull, 0ull},
+ {"DOORBELL" , 1, 1, 472, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 472, "RAZ", 1, 0, 0, 0ull},
+ {"MODE" , 0, 2, 473, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 473, "RAZ", 1, 0, 0, 0ull},
+ {"INDEX" , 0, 8, 474, "R/W", 0, 0, 0ull, 0ull},
+ {"INC" , 8, 8, 474, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 474, "RAZ", 1, 0, 0, 0ull},
+ {"ADR0" , 0, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"ADR1" , 1, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"PEND0" , 2, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"PEND1" , 3, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"NBR0" , 4, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"NBR1" , 5, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"FIDX" , 6, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"INDEX" , 7, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"NBT" , 8, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"CAM" , 9, 1, 475, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_15" , 10, 6, 475, "RAZ", 1, 1, 0, 0},
+ {"PP" , 16, 16, 475, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 475, "RAZ", 1, 1, 0, 0},
+ {"DS_PC" , 0, 32, 476, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 476, "RAZ", 1, 1, 0, 0},
+ {"SBE" , 0, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DBE" , 1, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SBE_IE" , 2, 1, 477, "R/W", 0, 1, 0ull, 0},
+ {"DBE_IE" , 3, 1, 477, "R/W", 0, 1, 0ull, 0},
+ {"SYN" , 4, 5, 477, "RO", 1, 1, 0, 0},
+ {"RESERVED_9_11" , 9, 3, 477, "RAZ", 1, 1, 0, 0},
+ {"RPE" , 12, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RPE_IE" , 13, 1, 477, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_14_63" , 14, 50, 477, "RAZ", 1, 1, 0, 0},
+ {"NBR_THR" , 0, 5, 478, "R/W", 0, 0, 2ull, 2ull},
+ {"PFR_DIS" , 5, 1, 478, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 478, "RAZ", 1, 1, 0, 0},
+ {"IQ_CNT" , 0, 32, 479, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 479, "RAZ", 1, 1, 0, 0},
+ {"IQ_CNT" , 0, 32, 480, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 480, "RAZ", 1, 1, 0, 0},
+ {"NOS_CNT" , 0, 12, 481, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_12_63" , 12, 52, 481, "RAZ", 1, 1, 0, 0},
+ {"NW_TIM" , 0, 10, 482, "R/W", 0, 0, 0ull, 1023ull},
+ {"RESERVED_10_63" , 10, 54, 482, "RAZ", 1, 1, 0, 0},
+ {"GRP_MSK" , 0, 16, 483, "R/W", 0, 0, 65535ull, 65535ull},
+ {"RESERVED_16_63" , 16, 48, 483, "RAZ", 1, 1, 0, 0},
+ {"RND" , 0, 8, 484, "R/W", 0, 1, 255ull, 0},
+ {"RND_P1" , 8, 8, 484, "R/W", 0, 1, 255ull, 0},
+ {"RND_P2" , 16, 8, 484, "R/W", 0, 1, 255ull, 0},
+ {"RND_P3" , 24, 8, 484, "R/W", 0, 1, 255ull, 0},
+ {"RESERVED_32_63" , 32, 32, 484, "RAZ", 1, 1, 0, 0},
+ {"MIN_THR" , 0, 11, 485, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_11_11" , 11, 1, 485, "RAZ", 1, 1, 0, 0},
+ {"MAX_THR" , 12, 11, 485, "R/W", 0, 1, 2047ull, 0},
+ {"RESERVED_23_23" , 23, 1, 485, "RAZ", 1, 1, 0, 0},
+ {"FREE_CNT" , 24, 12, 485, "RO", 0, 1, 2027ull, 0},
+ {"BUF_CNT" , 36, 12, 485, "RO", 0, 1, 0ull, 0},
+ {"DES_CNT" , 48, 12, 485, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_60_63" , 60, 4, 485, "RAZ", 1, 1, 0, 0},
+ {"TS_PC" , 0, 32, 486, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 486, "RAZ", 1, 1, 0, 0},
+ {"WA_PC" , 0, 32, 487, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 487, "RAZ", 1, 1, 0, 0},
+ {"WA_PC" , 0, 32, 488, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
+ {"WQ_INT" , 0, 16, 489, "R/W1C", 0, 1, 0ull, 0},
+ {"IQ_DIS" , 16, 16, 489, "R/W1", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 489, "RAZ", 1, 1, 0, 0},
+ {"IQ_CNT" , 0, 12, 490, "RO", 0, 1, 0ull, 0},
+ {"DS_CNT" , 12, 12, 490, "RO", 0, 1, 0ull, 0},
+ {"TC_CNT" , 24, 4, 490, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_28_63" , 28, 36, 490, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_7" , 0, 8, 491, "RAZ", 1, 1, 0, 0},
+ {"PC_THR" , 8, 20, 491, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_28_31" , 28, 4, 491, "RAZ", 1, 1, 0, 0},
+ {"PC" , 32, 28, 491, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_60_63" , 60, 4, 491, "RAZ", 1, 1, 0, 0},
+ {"IQ_THR" , 0, 11, 492, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_11_11" , 11, 1, 492, "RAZ", 1, 1, 0, 0},
+ {"DS_THR" , 12, 11, 492, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_23_23" , 23, 1, 492, "RAZ", 1, 1, 0, 0},
+ {"TC_THR" , 24, 4, 492, "R/W", 0, 1, 0ull, 0},
+ {"TC_EN" , 28, 1, 492, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 492, "RAZ", 1, 1, 0, 0},
+ {"WS_PC" , 0, 32, 493, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 493, "RAZ", 1, 1, 0, 0},
+ {"MEM" , 0, 1, 494, "RO", 0, 0, 0ull, 0ull},
+ {"RRC" , 1, 1, 494, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 494, "RAZ", 1, 1, 0, 0},
+ {"ENT_EN" , 0, 1, 495, "R/W", 0, 0, 0ull, 0ull},
+ {"RNG_EN" , 1, 1, 495, "R/W", 0, 0, 0ull, 0ull},
+ {"RNM_RST" , 2, 1, 495, "R/W", 0, 0, 0ull, 0ull},
+ {"RNG_RST" , 3, 1, 495, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 495, "RAZ", 1, 1, 0, 0},
+ {"PHASE" , 0, 8, 496, "R/W", 0, 0, 100ull, 100ull},
+ {"SAMPLE" , 8, 4, 496, "R/W", 0, 0, 2ull, 2ull},
+ {"PREAMBLE" , 12, 1, 496, "R/W", 0, 0, 1ull, 1ull},
+ {"CLK_IDLE" , 13, 1, 496, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_14_14" , 14, 1, 496, "RAZ", 1, 1, 0, 0},
+ {"SAMPLE_MODE" , 15, 1, 496, "RAZ", 0, 0, 0ull, 0ull},
+ {"SAMPLE_HI" , 16, 5, 496, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_21_63" , 21, 43, 496, "RAZ", 1, 1, 0, 0},
+ {"REG_ADR" , 0, 5, 497, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_7" , 5, 3, 497, "RAZ", 1, 1, 0, 0},
+ {"PHY_ADR" , 8, 5, 497, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_13_15" , 13, 3, 497, "RAZ", 1, 1, 0, 0},
+ {"PHY_OP" , 16, 1, 497, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_17_63" , 17, 47, 497, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 1, 498, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_1_63" , 1, 63, 498, "RAZ", 1, 1, 0, 0},
+ {"DAT" , 0, 16, 499, "RO", 0, 1, 0ull, 0},
+ {"VAL" , 16, 1, 499, "RO", 0, 1, 0ull, 0},
+ {"PENDING" , 17, 1, 499, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_18_63" , 18, 46, 499, "RAZ", 1, 1, 0, 0},
+ {"DAT" , 0, 16, 500, "R/W", 0, 1, 0ull, 0},
+ {"VAL" , 16, 1, 500, "RO", 0, 1, 0ull, 0},
+ {"PENDING" , 17, 1, 500, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_18_63" , 18, 46, 500, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 501, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 501, "RAZ", 0, 0, 0ull, 0ull},
+ {"STAT0" , 0, 1, 502, "RO", 0, 0, 0ull, 0ull},
+ {"STAT1" , 1, 1, 502, "RO", 0, 0, 0ull, 0ull},
+ {"STAT2" , 2, 1, 502, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 502, "RAZ", 0, 0, 0ull, 0ull},
+ {"SRXDLCK" , 0, 1, 503, "R/W", 0, 0, 0ull, 1ull},
+ {"RCVTRN" , 1, 1, 503, "R/W", 0, 0, 0ull, 1ull},
+ {"DRPTRN" , 2, 1, 503, "R/W", 0, 0, 0ull, 1ull},
+ {"SNDTRN" , 3, 1, 503, "R/W", 0, 0, 0ull, 1ull},
+ {"STATRCV" , 4, 1, 503, "R/W", 0, 0, 0ull, 0ull},
+ {"STATDRV" , 5, 1, 503, "R/W", 0, 0, 0ull, 0ull},
+ {"RUNBIST" , 6, 1, 503, "R/W", 0, 0, 0ull, 0ull},
+ {"CLKDLY" , 7, 5, 503, "R/W", 0, 0, 16ull, 16ull},
+ {"RESERVED_12_15" , 12, 4, 503, "RAZ", 0, 0, 0ull, 0ull},
+ {"SEETRN" , 16, 1, 503, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_63" , 17, 47, 503, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_0_3" , 0, 4, 504, "RAZ", 0, 1, 0ull, 0},
+ {"D4CLK0" , 4, 1, 504, "R/W1C", 0, 1, 0ull, 0},
+ {"D4CLK1" , 5, 1, 504, "R/W1C", 0, 1, 0ull, 0},
+ {"S4CLK0" , 6, 1, 504, "R/W1C", 0, 1, 0ull, 0},
+ {"S4CLK1" , 7, 1, 504, "R/W1C", 0, 1, 0ull, 0},
+ {"SRXTRN" , 8, 1, 504, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_9_9" , 9, 1, 504, "RAZ", 0, 1, 0ull, 0},
+ {"STXCAL" , 10, 1, 504, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_11_63" , 11, 53, 504, "RAZ", 0, 0, 0ull, 0ull},
+ {"DLLDIS" , 0, 1, 505, "R/W", 1, 0, 0, 0ull},
+ {"DLLFRC" , 1, 1, 505, "WR0", 1, 0, 0, 0ull},
+ {"OFFDLY" , 2, 6, 505, "R/W", 1, 0, 0, 0ull},
+ {"BITSEL" , 8, 5, 505, "R/W", 1, 1, 0, 0},
+ {"OFFSET" , 13, 5, 505, "R/W", 1, 1, 0, 0},
+ {"MUX" , 18, 1, 505, "WR0", 1, 1, 0, 0},
+ {"INC" , 19, 1, 505, "WR0", 1, 1, 0, 0},
+ {"DEC" , 20, 1, 505, "WR0", 1, 1, 0, 0},
+ {"CLRDLY" , 21, 1, 505, "WR0", 1, 1, 0, 0},
+ {"RESERVED_22_23" , 22, 2, 505, "RAZ", 0, 0, 0ull, 0ull},
+ {"SSTEP" , 24, 1, 505, "R/W", 1, 0, 0, 0ull},
+ {"SSTEP_GO" , 25, 1, 505, "WR0", 1, 1, 0, 0},
+ {"RESERVED_26_27" , 26, 2, 505, "RAZ", 0, 0, 0ull, 0ull},
+ {"FALL8" , 28, 1, 505, "R/W", 0, 0, 0ull, 0ull},
+ {"FALLNOP" , 29, 1, 505, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_30_63" , 30, 34, 505, "RAZ", 0, 0, 0ull, 0ull},
+ {"OFFSET" , 0, 5, 506, "RO", 0, 1, 0ull, 0},
+ {"MUXSEL" , 5, 2, 506, "RO", 0, 1, 0ull, 0},
+ {"UNXTERM" , 7, 1, 506, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TESTRES" , 8, 1, 506, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 506, "RAZ", 0, 0, 0ull, 0ull},
+ {"SRX4CMP" , 0, 8, 507, "R/W", 0, 1, 0ull, 0},
+ {"STX4PCMP" , 8, 4, 507, "R/W", 0, 1, 0ull, 0},
+ {"STX4NCMP" , 12, 4, 507, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 507, "RAZ", 0, 0, 0ull, 0ull},
+ {"ERRCNT" , 0, 4, 508, "R/W", 0, 0, 0ull, 3ull},
+ {"RESERVED_4_5" , 4, 2, 508, "RAZ", 0, 0, 0ull, 0ull},
+ {"DIPPAY" , 6, 1, 508, "R/W", 0, 0, 0ull, 0ull},
+ {"DIPCLS" , 7, 1, 508, "R/W", 0, 0, 0ull, 0ull},
+ {"PRTNXA" , 8, 1, 508, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 508, "RAZ", 0, 0, 0ull, 0ull},
+ {"PRT" , 0, 8, 509, "RO", 0, 0, 0ull, 0ull},
+ {"RSVOP" , 8, 4, 509, "RO", 0, 0, 0ull, 0ull},
+ {"CALBNK" , 12, 2, 509, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_14_30" , 14, 17, 509, "RAZ", 0, 0, 0ull, 0ull},
+ {"MUL" , 31, 1, 509, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 509, "RAZ", 0, 0, 0ull, 0ull},
+ {"PRTNXA" , 0, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"ABNORM" , 1, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_3" , 2, 2, 510, "RAZ", 0, 0, 0ull, 0ull},
+ {"SPIOVR" , 4, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"CLSERR" , 5, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"DRWNNG" , 6, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"RSVERR" , 7, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"TPAOVR" , 8, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"DIPERR" , 9, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"SYNCERR" , 10, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"CALERR" , 11, 1, 510, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 510, "RAZ", 0, 0, 0ull, 0ull},
+ {"PRTNXA" , 0, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ABNORM" , 1, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_3" , 2, 2, 511, "RAZ", 0, 0, 0ull, 0ull},
+ {"SPIOVR" , 4, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CLSERR" , 5, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DRWNNG" , 6, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RSVERR" , 7, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TPAOVR" , 8, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DIPERR" , 9, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SYNCERR" , 10, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CALERR" , 11, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_30" , 12, 19, 511, "RAZ", 0, 0, 0ull, 0ull},
+ {"SPF" , 31, 1, 511, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 511, "RAZ", 0, 0, 0ull, 0ull},
+ {"PRTNXA" , 0, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"ABNORM" , 1, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_3" , 2, 2, 512, "RAZ", 0, 0, 0ull, 0ull},
+ {"SPIOVR" , 4, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"CLSERR" , 5, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"DRWNNG" , 6, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"RSVERR" , 7, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"TPAOVR" , 8, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"DIPERR" , 9, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"SYNCERR" , 10, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"CALERR" , 11, 1, 512, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 512, "RAZ", 0, 0, 0ull, 0ull},
+ {"CNT" , 0, 32, 513, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 513, "RAZ", 0, 0, 0ull, 0ull},
+ {"MAX" , 0, 32, 514, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 514, "RAZ", 0, 0, 0ull, 0ull},
+ {"PRTSEL" , 0, 4, 515, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 515, "RAZ", 0, 0, 0ull, 0ull},
+ {"MUX_EN" , 0, 1, 516, "R/W", 0, 0, 0ull, 0ull},
+ {"MACRO_EN" , 1, 1, 516, "R/W", 0, 0, 0ull, 0ull},
+ {"MAXDIST" , 2, 5, 516, "R/W", 0, 0, 0ull, 8ull},
+ {"SET_BOOT" , 7, 1, 516, "R/W", 0, 0, 0ull, 0ull},
+ {"CLR_BOOT" , 8, 1, 516, "R/W", 0, 0, 0ull, 0ull},
+ {"JITTER" , 9, 3, 516, "R/W", 0, 0, 0ull, 1ull},
+ {"TRNTEST" , 12, 1, 516, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_13_63" , 13, 51, 516, "RAZ", 0, 0, 0ull, 0ull},
+ {"BW_CTL" , 0, 5, 517, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 517, "RAZ", 0, 0, 0ull, 0ull},
+ {"SETTING" , 0, 17, 518, "RO", 1, 1, 0, 0},
+ {"RESERVED_17_63" , 17, 47, 518, "RAZ", 0, 0, 0ull, 0ull},
+ {"INF_EN" , 0, 1, 519, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_1_2" , 1, 2, 519, "RAZ", 0, 0, 0ull, 0ull},
+ {"ST_EN" , 3, 1, 519, "R/W", 0, 0, 0ull, 1ull},
+ {"PRTS" , 4, 4, 519, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 519, "RAZ", 0, 0, 0ull, 0ull},
+ {"IGNORE" , 0, 16, 520, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 520, "RAZ", 0, 0, 0ull, 0ull},
+ {"PRT0" , 0, 4, 521, "R/W", 1, 1, 0, 0},
+ {"PRT1" , 4, 4, 521, "R/W", 1, 1, 0, 0},
+ {"PRT2" , 8, 4, 521, "R/W", 1, 1, 0, 0},
+ {"PRT3" , 12, 4, 521, "R/W", 1, 1, 0, 0},
+ {"ODDPAR" , 16, 1, 521, "R/W", 1, 1, 0, 0},
+ {"RESERVED_17_63" , 17, 47, 521, "RAZ", 0, 0, 0ull, 0ull},
+ {"LEN" , 0, 7, 522, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_7_7" , 7, 1, 522, "RAZ", 0, 0, 0ull, 0ull},
+ {"M" , 8, 8, 522, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 522, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_0_2" , 0, 3, 523, "R/W", 0, 0, 0ull, 0ull},
+ {"IGNTPA" , 3, 1, 523, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_4" , 4, 1, 523, "R/W", 0, 0, 0ull, 0ull},
+ {"MINTRN" , 5, 1, 523, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 523, "RAZ", 0, 0, 0ull, 0ull},
+ {"CNT" , 0, 32, 524, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 524, "RAZ", 0, 0, 0ull, 0ull},
+ {"INF_EN" , 0, 1, 525, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_1_2" , 1, 2, 525, "RAZ", 0, 0, 0ull, 0ull},
+ {"ST_EN" , 3, 1, 525, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_4_63" , 4, 60, 525, "RAZ", 0, 0, 0ull, 0ull},
+ {"DIPMAX" , 0, 4, 526, "R/W", 0, 0, 0ull, 0ull},
+ {"FRMMAX" , 4, 4, 526, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 526, "RAZ", 0, 0, 0ull, 0ull},
+ {"IGNTPA" , 0, 16, 527, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 527, "RAZ", 0, 0, 0ull, 0ull},
+ {"CALPAR0" , 0, 1, 528, "R/W", 0, 0, 0ull, 0ull},
+ {"CALPAR1" , 1, 1, 528, "R/W", 0, 0, 0ull, 0ull},
+ {"OVRBST" , 2, 1, 528, "R/W", 0, 0, 0ull, 0ull},
+ {"DATOVR" , 3, 1, 528, "R/W", 0, 0, 0ull, 0ull},
+ {"DIPERR" , 4, 1, 528, "R/W", 0, 0, 0ull, 0ull},
+ {"NOSYNC" , 5, 1, 528, "R/W", 0, 0, 0ull, 0ull},
+ {"UNXFRM" , 6, 1, 528, "R/W", 0, 0, 0ull, 0ull},
+ {"FRMERR" , 7, 1, 528, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 528, "RAZ", 0, 0, 0ull, 0ull},
+ {"CALPAR0" , 0, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CALPAR1" , 1, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
+ {"OVRBST" , 2, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DATOVR" , 3, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DIPERR" , 4, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
+ {"NOSYNC" , 5, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
+ {"UNXFRM" , 6, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FRMERR" , 7, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SYNCERR" , 8, 1, 529, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 529, "RAZ", 0, 0, 0ull, 0ull},
+ {"CALPAR0" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
+ {"CALPAR1" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
+ {"OVRBST" , 2, 1, 530, "R/W", 0, 0, 0ull, 0ull},
+ {"DATOVR" , 3, 1, 530, "R/W", 0, 0, 0ull, 0ull},
+ {"DIPERR" , 4, 1, 530, "R/W", 0, 0, 0ull, 0ull},
+ {"NOSYNC" , 5, 1, 530, "R/W", 0, 0, 0ull, 0ull},
+ {"UNXFRM" , 6, 1, 530, "R/W", 0, 0, 0ull, 0ull},
+ {"FRMERR" , 7, 1, 530, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 530, "RAZ", 0, 0, 0ull, 0ull},
+ {"MINB" , 0, 9, 531, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 531, "RAZ", 0, 0, 0ull, 0ull},
+ {"PRT0" , 0, 4, 532, "R/W", 1, 1, 0, 0},
+ {"PRT1" , 4, 4, 532, "R/W", 1, 1, 0, 0},
+ {"PRT2" , 8, 4, 532, "R/W", 1, 1, 0, 0},
+ {"PRT3" , 12, 4, 532, "R/W", 1, 1, 0, 0},
+ {"ODDPAR" , 16, 1, 532, "R/W", 1, 1, 0, 0},
+ {"RESERVED_17_63" , 17, 47, 532, "RAZ", 0, 0, 0ull, 0ull},
+ {"MAX_T" , 0, 16, 533, "R/W", 0, 1, 0ull, 0},
+ {"ALPHA" , 16, 16, 533, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 533, "RAZ", 0, 0, 0ull, 0ull},
+ {"LEN" , 0, 7, 534, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_7_7" , 7, 1, 534, "RAZ", 0, 0, 0ull, 0ull},
+ {"M" , 8, 8, 534, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 534, "RAZ", 0, 0, 0ull, 0ull},
+ {"CNT" , 0, 32, 535, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 535, "RAZ", 0, 0, 0ull, 0ull},
+ {"CNT" , 0, 32, 536, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 536, "RAZ", 0, 0, 0ull, 0ull},
+ {"BCKPRS" , 0, 4, 537, "R/W", 0, 0, 0ull, 0ull},
+ {"CLR" , 4, 1, 537, "WR0", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 537, "RAZ", 0, 0, 0ull, 0ull},
+ {"CNT" , 0, 32, 538, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 538, "RAZ", 0, 0, 0ull, 0ull},
+ {"INTERVAL" , 0, 22, 539, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_22_23" , 22, 2, 539, "RAZ", 1, 0, 0, 0ull},
+ {"COUNT" , 24, 22, 539, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_46_46" , 46, 1, 539, "RAZ", 1, 0, 0, 0ull},
+ {"ENA" , 47, 1, 539, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_48_63" , 48, 16, 539, "RAZ", 1, 0, 0, 0ull},
+ {"BSIZE" , 0, 20, 540, "RO", 1, 0, 0, 0ull},
+ {"BASE" , 20, 31, 540, "RO", 1, 0, 0, 0ull},
+ {"BUCKET" , 51, 13, 540, "RO", 1, 0, 0, 0ull},
+ {"BUCKET" , 0, 7, 541, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_7_7" , 7, 1, 541, "RAZ", 1, 0, 0, 0ull},
+ {"CSIZE" , 8, 13, 541, "RO", 1, 0, 0, 0ull},
+ {"CPOOL" , 21, 3, 541, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_24_63" , 24, 40, 541, "RAZ", 1, 0, 0, 0ull},
+ {"RING" , 0, 4, 542, "R/W", 0, 0, 0ull, 0ull},
+ {"NUM_BUCKETS" , 4, 20, 542, "R/W", 0, 0, 0ull, 0ull},
+ {"FIRST_BUCKET" , 24, 31, 542, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_55_63" , 55, 9, 542, "RAZ", 1, 0, 0, 0ull},
+ {"RING" , 0, 4, 543, "R/W", 0, 0, 0ull, 0ull},
+ {"INTERVAL" , 4, 22, 543, "R/W", 0, 0, 0ull, 0ull},
+ {"WORDS_PER_CHUNK" , 26, 13, 543, "R/W", 0, 0, 0ull, 0ull},
+ {"POOL" , 39, 3, 543, "R/W", 0, 0, 0ull, 0ull},
+ {"ENABLE" , 42, 1, 543, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_43_63" , 43, 21, 543, "RAZ", 1, 0, 0, 0ull},
+ {"CTL" , 0, 1, 544, "RO", 1, 0, 0, 0ull},
+ {"NCB" , 1, 1, 544, "RO", 1, 0, 0, 0ull},
+ {"STA" , 2, 2, 544, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_4_63" , 4, 60, 544, "RAZ", 1, 0, 0, 0ull},
+ {"MASK" , 0, 16, 545, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 545, "RAZ", 1, 0, 0, 0ull},
+ {"ENABLE_TIMERS" , 0, 1, 546, "R/W", 0, 0, 0ull, 0ull},
+ {"ENABLE_DWB" , 1, 1, 546, "R/W", 0, 0, 0ull, 0ull},
+ {"RESET" , 2, 1, 546, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 546, "RAZ", 1, 0, 0, 0ull},
+ {"MASK" , 0, 16, 547, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 547, "RAZ", 1, 0, 0, 0ull},
+ {"INDEX" , 0, 8, 548, "R/W", 0, 0, 0ull, 0ull},
+ {"INC" , 8, 8, 548, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 548, "RAZ", 1, 0, 0, 0ull},
+ {"TDF0" , 0, 1, 549, "RO", 0, 0, 0ull, 0ull},
+ {"TDF1" , 1, 1, 549, "RO", 0, 0, 0ull, 0ull},
+ {"TCF" , 2, 1, 549, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 549, "RAZ", 0, 0, 0ull, 0ull},
+ {"ENA" , 0, 1, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"WRAP" , 1, 1, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"TRIG_CTL" , 2, 2, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"TIME_GRN" , 4, 3, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"FULL_THR" , 7, 2, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"CIU_TRG" , 9, 1, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"CIU_THR" , 10, 1, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"MCD0_TRG" , 11, 1, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"MCD0_THR" , 12, 1, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"MCD0_ENA" , 13, 1, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"IGNORE_O" , 14, 1, 550, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_15_63" , 15, 49, 550, "RAZ", 0, 0, 0ull, 0ull},
+ {"WPTR" , 0, 8, 551, "RO", 0, 0, 0ull, 0ull},
+ {"RPTR" , 8, 8, 551, "RO", 0, 0, 0ull, 0ull},
+ {"CYCLES" , 16, 48, 551, "RO", 0, 0, 0ull, 0ull},
+ {"ADR" , 0, 36, 552, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 552, "RAZ", 0, 0, 0ull, 0ull},
+ {"ADR" , 0, 36, 553, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 553, "RAZ", 0, 0, 0ull, 0ull},
+ {"DWB" , 0, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"PL2" , 1, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"PSL1" , 2, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"LDD" , 3, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"LDI" , 4, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"LDT" , 5, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"STF" , 6, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"STC" , 7, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"STP" , 8, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"STT" , 9, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD8" , 10, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD16" , 11, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD32" , 12, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD64" , 13, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBST" , 14, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBDMA" , 15, 1, 554, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_16_63" , 16, 48, 554, "RAZ", 0, 0, 0ull, 0ull},
+ {"MIO" , 0, 1, 555, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL3" , 1, 2, 555, "R/W", 0, 0, 0ull, 3ull},
+ {"PCI" , 3, 1, 555, "R/W", 0, 0, 0ull, 1ull},
+ {"KEY" , 4, 1, 555, "R/W", 0, 0, 0ull, 1ull},
+ {"FPA" , 5, 1, 555, "R/W", 0, 0, 0ull, 1ull},
+ {"DFA" , 6, 1, 555, "R/W", 0, 0, 0ull, 1ull},
+ {"ZIP" , 7, 1, 555, "R/W", 0, 0, 0ull, 1ull},
+ {"RNG" , 8, 1, 555, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL2" , 9, 3, 555, "R/W", 0, 0, 0ull, 7ull},
+ {"POW" , 12, 1, 555, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL" , 13, 19, 555, "R/W", 0, 0, 0ull, 524287ull},
+ {"RESERVED_32_63" , 32, 32, 555, "RAZ", 0, 0, 0ull, 0ull},
+ {"PP" , 0, 16, 556, "R/W", 0, 0, 0ull, 0ull},
+ {"PKI" , 16, 1, 556, "R/W", 0, 0, 0ull, 0ull},
+ {"PKO" , 17, 1, 556, "R/W", 0, 0, 0ull, 0ull},
+ {"IOBREQ" , 18, 1, 556, "R/W", 0, 0, 0ull, 0ull},
+ {"DWB" , 19, 1, 556, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 556, "RAZ", 0, 0, 0ull, 0ull},
+ {"CIU_TRG" , 0, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CIU_THR" , 1, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MCD0_TRG" , 2, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MCD0_THR" , 3, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 557, "RAZ", 0, 0, 0ull, 0ull},
+ {"DATA" , 0, 64, 558, "RO", 0, 0, 0ull, 0ull},
+ {"ADR" , 0, 36, 559, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 559, "RAZ", 0, 0, 0ull, 0ull},
+ {"ADR" , 0, 36, 560, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 560, "RAZ", 0, 0, 0ull, 0ull},
+ {"DWB" , 0, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"PL2" , 1, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"PSL1" , 2, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"LDD" , 3, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"LDI" , 4, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"LDT" , 5, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"STF" , 6, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"STC" , 7, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"STP" , 8, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"STT" , 9, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD8" , 10, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD16" , 11, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD32" , 12, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD64" , 13, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBST" , 14, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBDMA" , 15, 1, 561, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_16_63" , 16, 48, 561, "RAZ", 0, 0, 0ull, 0ull},
+ {"MIO" , 0, 1, 562, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL3" , 1, 2, 562, "R/W", 0, 0, 0ull, 3ull},
+ {"PCI" , 3, 1, 562, "R/W", 0, 0, 0ull, 1ull},
+ {"KEY" , 4, 1, 562, "R/W", 0, 0, 0ull, 1ull},
+ {"FPA" , 5, 1, 562, "R/W", 0, 0, 0ull, 1ull},
+ {"DFA" , 6, 1, 562, "R/W", 0, 0, 0ull, 1ull},
+ {"ZIP" , 7, 1, 562, "R/W", 0, 0, 0ull, 1ull},
+ {"RNG" , 8, 1, 562, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL2" , 9, 3, 562, "R/W", 0, 0, 0ull, 7ull},
+ {"POW" , 12, 1, 562, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL" , 13, 19, 562, "R/W", 0, 0, 0ull, 524287ull},
+ {"RESERVED_32_63" , 32, 32, 562, "RAZ", 0, 0, 0ull, 0ull},
+ {"PP" , 0, 16, 563, "R/W", 0, 0, 0ull, 0ull},
+ {"PKI" , 16, 1, 563, "R/W", 0, 0, 0ull, 0ull},
+ {"PKO" , 17, 1, 563, "R/W", 0, 0, 0ull, 0ull},
+ {"IOBREQ" , 18, 1, 563, "R/W", 0, 0, 0ull, 0ull},
+ {"DWB" , 19, 1, 563, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 563, "RAZ", 0, 0, 0ull, 0ull},
+ {"ADR" , 0, 36, 564, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 564, "RAZ", 0, 0, 0ull, 0ull},
+ {"ADR" , 0, 36, 565, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 565, "RAZ", 0, 0, 0ull, 0ull},
+ {"DWB" , 0, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"PL2" , 1, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"PSL1" , 2, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"LDD" , 3, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"LDI" , 4, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"LDT" , 5, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"STF" , 6, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"STC" , 7, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"STP" , 8, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"STT" , 9, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD8" , 10, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD16" , 11, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD32" , 12, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBLD64" , 13, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBST" , 14, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBDMA" , 15, 1, 566, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_16_63" , 16, 48, 566, "RAZ", 0, 0, 0ull, 0ull},
+ {"MIO" , 0, 1, 567, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL3" , 1, 2, 567, "R/W", 0, 0, 0ull, 3ull},
+ {"PCI" , 3, 1, 567, "R/W", 0, 0, 0ull, 1ull},
+ {"KEY" , 4, 1, 567, "R/W", 0, 0, 0ull, 1ull},
+ {"FPA" , 5, 1, 567, "R/W", 0, 0, 0ull, 1ull},
+ {"DFA" , 6, 1, 567, "R/W", 0, 0, 0ull, 1ull},
+ {"ZIP" , 7, 1, 567, "R/W", 0, 0, 0ull, 1ull},
+ {"RNG" , 8, 1, 567, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL2" , 9, 3, 567, "R/W", 0, 0, 0ull, 7ull},
+ {"POW" , 12, 1, 567, "R/W", 0, 0, 0ull, 1ull},
+ {"ILLEGAL" , 13, 19, 567, "R/W", 0, 0, 0ull, 524287ull},
+ {"RESERVED_32_63" , 32, 32, 567, "RAZ", 0, 0, 0ull, 0ull},
+ {"PP" , 0, 16, 568, "R/W", 0, 0, 0ull, 0ull},
+ {"PKI" , 16, 1, 568, "R/W", 0, 0, 0ull, 0ull},
+ {"PKO" , 17, 1, 568, "R/W", 0, 0, 0ull, 0ull},
+ {"IOBREQ" , 18, 1, 568, "R/W", 0, 0, 0ull, 0ull},
+ {"DWB" , 19, 1, 568, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 568, "RAZ", 0, 0, 0ull, 0ull},
+ {"ZIP_CTL" , 0, 4, 569, "RO", 1, 0, 0, 0ull},
+ {"ZIP_CORE" , 4, 27, 569, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_31_63" , 31, 33, 569, "RAZ", 1, 0, 0, 0ull},
+ {"PTR" , 0, 33, 570, "R/W", 0, 0, 0ull, 0ull},
+ {"SIZE" , 33, 13, 570, "R/W", 0, 0, 0ull, 0ull},
+ {"POOL" , 46, 3, 570, "R/W", 0, 0, 0ull, 0ull},
+ {"DWB" , 49, 9, 570, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_58_63" , 58, 6, 570, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESET" , 0, 1, 571, "RAZ", 0, 0, 0ull, 0ull},
+ {"FORCECLK" , 1, 1, 571, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 571, "RAZ", 0, 0, 0ull, 0ull},
+ {"DISABLED" , 0, 1, 572, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_7" , 1, 7, 572, "RAZ", 0, 0, 0ull, 0ull},
+ {"CTXSIZE" , 8, 12, 572, "RO", 0, 0, 1536ull, 1536ull},
+ {"ONFSIZE" , 20, 12, 572, "RO", 0, 0, 512ull, 512ull},
+ {"DEPTH" , 32, 16, 572, "RO", 0, 0, 15360ull, 15360ull},
+ {"RESERVED_48_63" , 48, 16, 572, "RAZ", 1, 0, 0, 0ull},
+ {"ASSERTS" , 0, 14, 573, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_14_63" , 14, 50, 573, "RAZ", 1, 0, 0, 0ull},
+ {"DOORBELL" , 0, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 574, "RAZ", 1, 0, 0, 0ull},
+ {"DOORBELL" , 0, 1, 575, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 575, "RAZ", 1, 0, 0, 0ull},
+ {NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn31xx[] = {
+ /* name , ---------------type, bits, off, #field, fld of */
+ {"cvmx_asx#_gmii_rx_clk_set" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 2, 0},
+ {"cvmx_asx#_gmii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 2},
+ {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 4},
+ {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 6, 10},
+ {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 4, 16},
+ {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 2, 20},
+ {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 22},
+ {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 24},
+ {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 4, 26},
+ {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 2, 30},
+ {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 32},
+ {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 17, 2, 34},
+ {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 18, 2, 36},
+ {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 19, 2, 38},
+ {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 20, 2, 40},
+ {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 21, 19, 42},
+ {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 26, 2, 61},
+ {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 31, 19, 63},
+ {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 36, 2, 82},
+ {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 37, 2, 84},
+ {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 39, 2, 86},
+ {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 41, 2, 88},
+ {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 42, 2, 90},
+ {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 43, 2, 92},
+ {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 44, 1, 94},
+ {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 46, 3, 95},
+ {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 47, 2, 98},
+ {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 48, 4, 100},
+ {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 49, 2, 104},
+ {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 50, 3, 106},
+ {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 54, 7, 109},
+ {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 6, 116},
+ {"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 3, 122},
+ {"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 7, 125},
+ {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 59, 2, 132},
+ {"cvmx_dfa_ddr2_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 6, 134},
+ {"cvmx_dfa_ddr2_bus" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 140},
+ {"cvmx_dfa_ddr2_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 16, 142},
+ {"cvmx_dfa_ddr2_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 6, 158},
+ {"cvmx_dfa_ddr2_emrs" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 4, 164},
+ {"cvmx_dfa_ddr2_fcnt" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 2, 168},
+ {"cvmx_dfa_ddr2_mrs" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 4, 170},
+ {"cvmx_dfa_ddr2_opt" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 3, 174},
+ {"cvmx_dfa_ddr2_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 14, 177},
+ {"cvmx_dfa_ddr2_tmg" , CVMX_CSR_DB_TYPE_RSL, 64, 69, 21, 191},
+ {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 70, 4, 212},
+ {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 71, 3, 216},
+ {"cvmx_dfa_eclkcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 14, 219},
+ {"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 73, 21, 233},
+ {"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 6, 254},
+ {"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 1, 260},
+ {"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 76, 1, 261},
+ {"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 1, 262},
+ {"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 78, 1, 263},
+ {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 6, 264},
+ {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 80, 7, 270},
+ {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 81, 29, 277},
+ {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 82, 29, 306},
+ {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 335},
+ {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 337},
+ {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 3, 339},
+ {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 100, 3, 342},
+ {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 345},
+ {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 102, 2, 347},
+ {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 8, 349},
+ {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 104, 2, 357},
+ {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 3, 359},
+ {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 106, 2, 362},
+ {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 5, 364},
+ {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 110, 1, 369},
+ {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 1, 370},
+ {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 1, 371},
+ {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 1, 372},
+ {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 1, 373},
+ {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 125, 1, 374},
+ {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 128, 2, 375},
+ {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 131, 4, 377},
+ {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 134, 2, 381},
+ {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 137, 11, 383},
+ {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 140, 9, 394},
+ {"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 143, 2, 403},
+ {"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 146, 2, 405},
+ {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 149, 2, 407},
+ {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 152, 20, 409},
+ {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 155, 20, 429},
+ {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 158, 2, 449},
+ {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 161, 4, 451},
+ {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 164, 2, 455},
+ {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 167, 2, 457},
+ {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 170, 2, 459},
+ {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 173, 2, 461},
+ {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 176, 2, 463},
+ {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 179, 2, 465},
+ {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 182, 2, 467},
+ {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 185, 2, 469},
+ {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 188, 2, 471},
+ {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 191, 2, 473},
+ {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 194, 4, 475},
+ {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 197, 2, 479},
+ {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 200, 2, 481},
+ {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 203, 2, 483},
+ {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 206, 4, 485},
+ {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 207, 2, 489},
+ {"cvmx_gmx#_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 208, 4, 491},
+ {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 209, 2, 495},
+ {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 212, 3, 497},
+ {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 213, 5, 500},
+ {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 216, 2, 505},
+ {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 219, 2, 507},
+ {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 222, 3, 509},
+ {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 225, 2, 512},
+ {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 228, 2, 514},
+ {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 231, 2, 516},
+ {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 234, 2, 518},
+ {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 237, 2, 520},
+ {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 240, 2, 522},
+ {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 243, 2, 524},
+ {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 2, 526},
+ {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 249, 2, 528},
+ {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 2, 530},
+ {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 2, 532},
+ {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 534},
+ {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 2, 536},
+ {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 538},
+ {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 267, 2, 540},
+ {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 2, 542},
+ {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 544},
+ {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 276, 2, 546},
+ {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 279, 2, 548},
+ {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 2, 550},
+ {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 2, 552},
+ {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 2, 554},
+ {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 285, 3, 556},
+ {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 8, 559},
+ {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 287, 8, 567},
+ {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 288, 2, 575},
+ {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 289, 2, 577},
+ {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 6, 579},
+ {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 291, 2, 585},
+ {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 587},
+ {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 293, 2, 589},
+ {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 294, 7, 591},
+ {"cvmx_gpio_boot_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 310, 3, 598},
+ {"cvmx_gpio_dbg_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 311, 2, 601},
+ {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 312, 2, 603},
+ {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 313, 2, 605},
+ {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 314, 2, 607},
+ {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 315, 2, 609},
+ {"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 316, 6, 611},
+ {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 324, 19, 617},
+ {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 325, 6, 636},
+ {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 326, 3, 642},
+ {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 327, 5, 645},
+ {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 328, 5, 650},
+ {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 329, 1, 655},
+ {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 330, 1, 656},
+ {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 331, 5, 657},
+ {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 332, 5, 662},
+ {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 333, 5, 667},
+ {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 334, 5, 672},
+ {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 335, 1, 677},
+ {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 678},
+ {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 337, 2, 679},
+ {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 338, 2, 681},
+ {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 339, 2, 683},
+ {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 340, 2, 685},
+ {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 341, 17, 687},
+ {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 342, 2, 704},
+ {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 343, 1, 706},
+ {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 344, 10, 707},
+ {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 345, 6, 717},
+ {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 346, 6, 723},
+ {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 347, 2, 729},
+ {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 348, 2, 731},
+ {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 349, 2, 733},
+ {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 350, 3, 735},
+ {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 355, 2, 738},
+ {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 360, 6, 740},
+ {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 361, 5, 746},
+ {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 362, 6, 751},
+ {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 363, 7, 757},
+ {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 364, 2, 764},
+ {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 372, 2, 766},
+ {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 373, 3, 768},
+ {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 374, 5, 771},
+ {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 382, 3, 776},
+ {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 383, 2, 779},
+ {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 384, 2, 781},
+ {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 385, 2, 783},
+ {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 386, 7, 785},
+ {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 387, 6, 792},
+ {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 8, 798},
+ {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 389, 9, 806},
+ {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 390, 10, 815},
+ {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 5, 825},
+ {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 4, 830},
+ {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 393, 2, 834},
+ {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 394, 17, 836},
+ {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 19, 853},
+ {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 3, 872},
+ {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 397, 4, 875},
+ {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 2, 879},
+ {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 402, 17, 881},
+ {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 4, 898},
+ {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 2, 902},
+ {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 405, 3, 904},
+ {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 406, 2, 907},
+ {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 909},
+ {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 911},
+ {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 7, 913},
+ {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 6, 920},
+ {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 411, 3, 926},
+ {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 3, 929},
+ {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 413, 2, 932},
+ {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 414, 2, 934},
+ {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 2, 936},
+ {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 3, 938},
+ {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 15, 941},
+ {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 418, 9, 956},
+ {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 419, 20, 965},
+ {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 2, 985},
+ {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 2, 987},
+ {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 422, 18, 989},
+ {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 423, 5, 1007},
+ {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 6, 1012},
+ {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 425, 2, 1018},
+ {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 2, 1020},
+ {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 427, 14, 1022},
+ {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 428, 10, 1036},
+ {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 429, 2, 1046},
+ {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 430, 2, 1048},
+ {"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 3, 1050},
+ {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 9, 1053},
+ {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 433, 5, 1062},
+ {"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 434, 5, 1067},
+ {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 435, 5, 1072},
+ {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 3, 1077},
+ {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 437, 3, 1080},
+ {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 438, 3, 1083},
+ {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 439, 5, 1086},
+ {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 441, 1, 1091},
+ {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 442, 10, 1092},
+ {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 13, 1102},
+ {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 4, 1115},
+ {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 2, 1119},
+ {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 2, 1121},
+ {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 461, 10, 1123},
+ {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 9, 1133},
+ {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 2, 1142},
+ {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 8, 1144},
+ {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 465, 4, 1152},
+ {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 2, 1156},
+ {"cvmx_mio_fus_unlock" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 2, 1158},
+ {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 1160},
+ {"cvmx_mio_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 2, 1162},
+ {"cvmx_mio_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 2, 1164},
+ {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 13, 1166},
+ {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 12, 1179},
+ {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 473, 3, 1191},
+ {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 474, 3, 1194},
+ {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 475, 2, 1197},
+ {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 477, 2, 1199},
+ {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 2, 1201},
+ {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 481, 7, 1203},
+ {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 483, 2, 1210},
+ {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 485, 7, 1212},
+ {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 4, 1219},
+ {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 8, 1223},
+ {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 9, 1231},
+ {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 493, 7, 1240},
+ {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 9, 1247},
+ {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 2, 1256},
+ {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 2, 1258},
+ {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 4, 1260},
+ {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 2, 1264},
+ {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 505, 2, 1266},
+ {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 2, 1268},
+ {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 509, 4, 1270},
+ {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 1274},
+ {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 513, 2, 1276},
+ {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 2, 1278},
+ {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 2, 1280},
+ {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 1282},
+ {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 521, 2, 1284},
+ {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 523, 6, 1286},
+ {"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 525, 13, 1292},
+ {"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 526, 2, 1305},
+ {"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 535, 4, 1307},
+ {"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 536, 6, 1311},
+ {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 537, 2, 1317},
+ {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 539, 2, 1319},
+ {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 541, 21, 1321},
+ {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 542, 3, 1342},
+ {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 544, 18, 1345},
+ {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 545, 2, 1363},
+ {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 546, 13, 1365},
+ {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 547, 3, 1378},
+ {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 548, 3, 1381},
+ {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 549, 3, 1384},
+ {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 550, 3, 1387},
+ {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 551, 2, 1390},
+ {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 552, 2, 1392},
+ {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 553, 9, 1394},
+ {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 554, 54, 1403},
+ {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 555, 54, 1457},
+ {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 556, 2, 1511},
+ {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 557, 2, 1513},
+ {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 558, 8, 1515},
+ {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 562, 1, 1523},
+ {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 563, 2, 1524},
+ {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 565, 23, 1526},
+ {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 566, 3, 1549},
+ {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 568, 2, 1552},
+ {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 570, 3, 1554},
+ {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 572, 3, 1557},
+ {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 574, 3, 1560},
+ {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 575, 4, 1563},
+ {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 576, 2, 1567},
+ {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 577, 13, 1569},
+ {"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 578, 13, 1582},
+ {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 579, 3, 1595},
+ {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 580, 33, 1598},
+ {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 581, 2, 1631},
+ {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 583, 2, 1633},
+ {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 584, 5, 1635},
+ {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 616, 2, 1640},
+ {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 617, 24, 1642},
+ {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 618, 2, 1666},
+ {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 619, 7, 1668},
+ {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 620, 5, 1675},
+ {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 621, 1, 1680},
+ {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 622, 5, 1681},
+ {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 623, 1, 1686},
+ {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 624, 4, 1687},
+ {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 625, 2, 1691},
+ {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 626, 1, 1693},
+ {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 627, 2, 1694},
+ {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 628, 4, 1696},
+ {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 629, 2, 1700},
+ {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 630, 4, 1702},
+ {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 631, 16, 1706},
+ {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 632, 1, 1722},
+ {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 633, 1, 1723},
+ {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 634, 18, 1724},
+ {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 635, 1, 1742},
+ {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 636, 1, 1743},
+ {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 637, 7, 1744},
+ {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 638, 7, 1751},
+ {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 639, 13, 1758},
+ {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 640, 10, 1771},
+ {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 641, 10, 1781},
+ {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 642, 7, 1791},
+ {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 643, 2, 1798},
+ {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 644, 1, 1800},
+ {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 645, 2, 1801},
+ {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 646, 16, 1803},
+ {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 647, 2, 1819},
+ {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 649, 1, 1821},
+ {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 651, 1, 1822},
+ {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 653, 1, 1823},
+ {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 655, 1, 1824},
+ {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 657, 33, 1825},
+ {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 658, 33, 1858},
+ {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 659, 33, 1891},
+ {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 660, 33, 1924},
+ {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 661, 2, 1957},
+ {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 662, 2, 1959},
+ {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 664, 1, 1961},
+ {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 666, 1, 1962},
+ {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 668, 1, 1963},
+ {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 670, 3, 1964},
+ {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 671, 3, 1967},
+ {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 672, 3, 1970},
+ {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 673, 3, 1973},
+ {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 674, 2, 1976},
+ {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 675, 2, 1978},
+ {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 676, 4, 1980},
+ {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 677, 1, 1984},
+ {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 678, 4, 1985},
+ {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 679, 1, 1989},
+ {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 680, 2, 1990},
+ {"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 681, 12, 1992},
+ {"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 685, 9, 2004},
+ {"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 689, 9, 2013},
+ {"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 693, 2, 2022},
+ {"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 697, 2, 2024},
+ {"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 701, 1, 2026},
+ {"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 705, 1, 2027},
+ {"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 709, 1, 2028},
+ {"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 713, 1, 2029},
+ {"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 717, 1, 2030},
+ {"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 721, 1, 2031},
+ {"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 725, 1, 2032},
+ {"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 729, 1, 2033},
+ {"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 733, 3, 2034},
+ {"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 737, 6, 2037},
+ {"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 741, 1, 2043},
+ {"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 745, 3, 2044},
+ {"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 749, 2, 2047},
+ {"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 753, 1, 2049},
+ {"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 757, 1, 2050},
+ {"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 761, 1, 2051},
+ {"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 765, 1, 2052},
+ {"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 769, 1, 2053},
+ {"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 773, 1, 2054},
+ {"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 777, 1, 2055},
+ {"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 781, 1, 2056},
+ {"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 785, 3, 2057},
+ {"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 789, 12, 2060},
+ {"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 791, 1, 2072},
+ {"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 793, 3, 2073},
+ {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 2, 2076},
+ {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 4, 2078},
+ {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 8, 2082},
+ {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 16, 2090},
+ {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 10, 2106},
+ {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 10, 2116},
+ {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 2, 2126},
+ {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 805, 16, 2128},
+ {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 25, 2144},
+ {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 2, 2169},
+ {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 2, 2171},
+ {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 887, 9, 2173},
+ {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 891, 2, 2182},
+ {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 892, 2, 2184},
+ {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 893, 2, 2186},
+ {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 898, 2, 2188},
+ {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 903, 2, 2190},
+ {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 908, 2, 2192},
+ {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 913, 2, 2194},
+ {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 918, 2, 2196},
+ {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 2198},
+ {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 2, 2200},
+ {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 933, 2, 2202},
+ {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 2, 2204},
+ {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 943, 2, 2206},
+ {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 944, 2, 2208},
+ {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 949, 2, 2210},
+ {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 954, 2, 2212},
+ {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 959, 2, 2214},
+ {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 2216},
+ {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 3, 2218},
+ {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 3, 2221},
+ {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 2224},
+ {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 2226},
+ {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 4, 2228},
+ {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 5, 2232},
+ {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 4, 2237},
+ {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 5, 2241},
+ {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 1, 2246},
+ {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 4, 2247},
+ {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 2, 2251},
+ {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 5, 2253},
+ {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 5, 2258},
+ {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 1, 2263},
+ {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 19, 2264},
+ {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 7, 2283},
+ {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 4, 2290},
+ {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1041, 6, 2294},
+ {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 6, 2300},
+ {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 9, 2306},
+ {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 5, 2315},
+ {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1045, 13, 2320},
+ {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1046, 4, 2333},
+ {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 2, 2337},
+ {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1048, 3, 2339},
+ {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 5, 2342},
+ {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1050, 3, 2347},
+ {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 3, 2350},
+ {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1052, 2, 2353},
+ {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 3, 2355},
+ {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1054, 12, 2358},
+ {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1055, 2, 2370},
+ {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1056, 9, 2372},
+ {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1057, 3, 2381},
+ {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1058, 2, 2384},
+ {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1066, 2, 2386},
+ {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1067, 2, 2388},
+ {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1068, 2, 2390},
+ {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1069, 2, 2392},
+ {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1071, 5, 2394},
+ {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1079, 10, 2399},
+ {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1087, 2, 2409},
+ {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1088, 2, 2411},
+ {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1089, 2, 2413},
+ {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1097, 3, 2415},
+ {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1098, 6, 2418},
+ {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1114, 5, 2424},
+ {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1115, 7, 2429},
+ {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1131, 2, 2436},
+ {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1147, 3, 2438},
+ {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1148, 5, 2441},
+ {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1149, 8, 2446},
+ {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1150, 6, 2454},
+ {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1151, 2, 2460},
+ {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1152, 4, 2462},
+ {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1153, 4, 2466},
+ {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1154, 6, 2470},
+ {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1155, 3, 2476},
+ {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1156, 5, 2479},
+ {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1157, 4, 2484},
+ {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1158, 6, 2488},
+ {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1159, 4, 2494},
+ {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1160, 2, 2498},
+ {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1161, 4, 2500},
+ {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 2, 2504},
+ {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1163, 3, 2506},
+ {"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1164, 4, 2509},
+ {"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1165, 12, 2513},
+ {"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 3, 2525},
+ {"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 2, 2528},
+ {"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 2, 2530},
+ {"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 17, 2532},
+ {"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 12, 2549},
+ {"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 6, 2561},
+ {"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 5, 2567},
+ {"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1173, 1, 2572},
+ {"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 2, 2573},
+ {"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 2, 2575},
+ {"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 17, 2577},
+ {"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 12, 2594},
+ {"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 6, 2606},
+ {"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 2, 2612},
+ {"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1180, 2, 2614},
+ {"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 17, 2616},
+ {"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1182, 12, 2633},
+ {"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 6, 2645},
+ {"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1184, 2, 2651},
+ {"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1185, 2, 2653},
+ {"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1186, 8, 2655},
+ {"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1187, 11, 2663},
+ {"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1188, 15, 2674},
+ {"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1193, 8, 2689},
+ {"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1198, 8, 2697},
+ {"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1199, 4, 2705},
+ {"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1204, 15, 2709},
+ {"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1209, 6, 2724},
+ {"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1214, 6, 2730},
+ {"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1215, 4, 2736},
+ {"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1220, 2, 2740},
+ {"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1224, 6, 2742},
+ {"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1225, 4, 2748},
+ {"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1226, 1, 2752},
+ {"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1227, 1, 2753},
+ {"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1228, 1, 2754},
+ {"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1229, 7, 2755},
+ {"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1230, 1, 2762},
+ {"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1231, 14, 2763},
+ {"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1232, 10, 2777},
+ {"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1233, 12, 2787},
+ {"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1234, 32, 2799},
+ {"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1235, 32, 2831},
+ {"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1236, 2, 2863},
+ {"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1237, 4, 2865},
+ {"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1238, 13, 2869},
+ {"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1239, 10, 2882},
+ {"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1240, 10, 2892},
+ {"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1241, 2, 2902},
+ {"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1242, 6, 2904},
+ {"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1243, 5, 2910},
+ {"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1244, 6, 2915},
+ {"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1245, 5, 2921},
+ {"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1246, 1, 2926},
+ {"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1247, 13, 2927},
+ {"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1248, 2, 2940},
+ {"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1249, 2, 2942},
+ {"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1250, 11, 2944},
+ {"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1258, 3, 2955},
+ {"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1259, 12, 2958},
+ {"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 1267, 12, 2970},
+ {"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 1275, 6, 2982},
+ {"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1283, 4, 2988},
+ {"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 1291, 2, 2992},
+ {"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 1292, 2, 2994},
+ {"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 1293, 15, 2996},
+ {"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1294, 2, 3011},
+ {"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1295, 3, 3013},
+ {"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 1296, 1, 3016},
+ {"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1304, 6, 3017},
+ {"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 4, 3023},
+ {"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1306, 15, 3027},
+ {"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1307, 6, 3042},
+ {"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1308, 2, 3048},
+ {"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1309, 2, 3050},
+ {"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1310, 2, 3052},
+ {"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1311, 2, 3054},
+ {"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1312, 2, 3056},
+ {"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1313, 2, 3058},
+ {"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1314, 2, 3060},
+ {"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1315, 2, 3062},
+ {"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1316, 2, 3064},
+ {"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1317, 2, 3066},
+ {"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1318, 2, 3068},
+ {"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1319, 2, 3070},
+ {"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1320, 2, 3072},
+ {"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1321, 2, 3074},
+ {"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1322, 2, 3076},
+ {"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1323, 2, 3078},
+ {"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 1324, 7, 3080},
+ {"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 39, 3087},
+ {"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1326, 39, 3126},
+ {"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 22, 3165},
+ {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1328, 3, 3187},
+ {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 5, 3190},
+ {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1330, 3, 3195},
+ {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 1331, 6, 3198},
+ {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1332, 2, 3204},
+ {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 2, 3206},
+ {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 2, 3208},
+ {NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
+ /* name , --------------address, ---------------type, bits, csr offset */
+ {"ASX0_GMII_RX_CLK_SET" , 0x11800B0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
+ {"ASX0_GMII_RX_DAT_SET" , 0x11800B0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
+ {"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
+ {"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
+ {"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
+ {"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
+ {"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
+ {"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
+ {"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
+ {"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
+ {"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
+ {"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
+ {"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
+ {"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
+ {"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
+ {"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
+ {"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
+ {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 11},
+ {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
+ {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
+ {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
+ {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
+ {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
+ {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
+ {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
+ {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
+ {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
+ {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
+ {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
+ {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
+ {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
+ {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
+ {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
+ {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
+ {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
+ {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
+ {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
+ {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
+ {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
+ {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
+ {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
+ {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
+ {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
+ {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
+ {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
+ {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
+ {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
+ {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
+ {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
+ {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
+ {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
+ {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
+ {"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
+ {"DFA_BST0" , 0x11800300007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
+ {"DFA_BST1" , 0x11800300007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
+ {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
+ {"DFA_DDR2_ADDR" , 0x1180030000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
+ {"DFA_DDR2_BUS" , 0x1180030000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
+ {"DFA_DDR2_CFG" , 0x1180030000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
+ {"DFA_DDR2_COMP" , 0x1180030000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
+ {"DFA_DDR2_EMRS" , 0x1180030000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
+ {"DFA_DDR2_FCNT" , 0x1180030000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
+ {"DFA_DDR2_MRS" , 0x1180030000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
+ {"DFA_DDR2_OPT" , 0x1180030000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
+ {"DFA_DDR2_PLL" , 0x1180030000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
+ {"DFA_DDR2_TMG" , 0x1180030000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
+ {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
+ {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 46},
+ {"DFA_ECLKCFG" , 0x1180030000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
+ {"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
+ {"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
+ {"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
+ {"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
+ {"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
+ {"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
+ {"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
+ {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
+ {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
+ {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
+ {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
+ {"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
+ {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
+ {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
+ {"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
+ {"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
+ {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
+ {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
+ {"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
+ {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
+ {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
+ {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
+ {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
+ {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
+ {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
+ {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
+ {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
+ {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
+ {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
+ {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
+ {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
+ {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
+ {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
+ {"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
+ {"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
+ {"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
+ {"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
+ {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
+ {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
+ {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
+ {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
+ {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
+ {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
+ {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
+ {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
+ {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
+ {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
+ {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
+ {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
+ {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
+ {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
+ {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
+ {"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
+ {"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
+ {"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
+ {"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
+ {"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
+ {"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
+ {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
+ {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
+ {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
+ {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
+ {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
+ {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
+ {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
+ {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
+ {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
+ {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
+ {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
+ {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
+ {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
+ {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
+ {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
+ {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
+ {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
+ {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
+ {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
+ {"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
+ {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
+ {"GMX0_RX_TX_STATUS" , 0x11800080007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
+ {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
+ {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
+ {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
+ {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
+ {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
+ {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
+ {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
+ {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
+ {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
+ {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
+ {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
+ {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
+ {"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
+ {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
+ {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
+ {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
+ {"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
+ {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
+ {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
+ {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
+ {"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
+ {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
+ {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
+ {"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
+ {"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
+ {"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
+ {"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
+ {"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
+ {"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
+ {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
+ {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
+ {"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
+ {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
+ {"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
+ {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
+ {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
+ {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
+ {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
+ {"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
+ {"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
+ {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
+ {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
+ {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
+ {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
+ {"GPIO_BOOT_ENA" , 0x10700000008A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
+ {"GPIO_DBG_ENA" , 0x10700000008A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
+ {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
+ {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
+ {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
+ {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
+ {"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
+ {"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
+ {"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
+ {"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
+ {"GPIO_XBIT_CFG20" , 0x1070000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
+ {"GPIO_XBIT_CFG21" , 0x1070000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
+ {"GPIO_XBIT_CFG22" , 0x1070000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
+ {"GPIO_XBIT_CFG23" , 0x1070000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
+ {"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
+ {"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
+ {"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
+ {"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
+ {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
+ {"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
+ {"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
+ {"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
+ {"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
+ {"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
+ {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
+ {"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
+ {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
+ {"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
+ {"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
+ {"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
+ {"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
+ {"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
+ {"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
+ {"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
+ {"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
+ {"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
+ {"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
+ {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
+ {"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
+ {"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
+ {"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
+ {"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
+ {"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
+ {"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
+ {"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
+ {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
+ {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
+ {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
+ {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
+ {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
+ {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
+ {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
+ {"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
+ {"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
+ {"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
+ {"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
+ {"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
+ {"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
+ {"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
+ {"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
+ {"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
+ {"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
+ {"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
+ {"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
+ {"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
+ {"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
+ {"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
+ {"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
+ {"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
+ {"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
+ {"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
+ {"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
+ {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
+ {"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
+ {"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
+ {"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
+ {"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
+ {"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
+ {"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
+ {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
+ {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
+ {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
+ {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
+ {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
+ {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
+ {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
+ {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
+ {"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
+ {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
+ {"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
+ {"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
+ {"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
+ {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
+ {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
+ {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
+ {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
+ {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
+ {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
+ {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
+ {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
+ {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
+ {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
+ {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
+ {"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
+ {"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
+ {"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
+ {"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
+ {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
+ {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
+ {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
+ {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
+ {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
+ {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
+ {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
+ {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
+ {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
+ {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
+ {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
+ {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
+ {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
+ {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
+ {"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
+ {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
+ {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
+ {"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
+ {"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
+ {"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
+ {"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
+ {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
+ {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
+ {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
+ {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
+ {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
+ {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
+ {"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
+ {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
+ {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
+ {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
+ {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
+ {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
+ {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
+ {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
+ {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
+ {"MIO_FUS_UNLOCK" , 0x1180000001578ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
+ {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
+ {"MIO_PLL_CTL" , 0x1180000001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
+ {"MIO_PLL_SETTING" , 0x1180000001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
+ {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
+ {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
+ {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
+ {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
+ {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
+ {"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
+ {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
+ {"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
+ {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
+ {"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
+ {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
+ {"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
+ {"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
+ {"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
+ {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
+ {"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
+ {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
+ {"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
+ {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
+ {"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
+ {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
+ {"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
+ {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
+ {"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
+ {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
+ {"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
+ {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
+ {"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
+ {"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
+ {"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
+ {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
+ {"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
+ {"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
+ {"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
+ {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
+ {"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
+ {"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
+ {"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
+ {"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
+ {"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
+ {"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
+ {"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
+ {"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
+ {"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
+ {"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
+ {"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
+ {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
+ {"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
+ {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
+ {"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
+ {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
+ {"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
+ {"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
+ {"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_DAT4" , 0x10700000010A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_DAT5" , 0x10700000010A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_DAT6" , 0x10700000010B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_DAT7" , 0x10700000010B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_DAT8" , 0x10700000010C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
+ {"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
+ {"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
+ {"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
+ {"NPI_BASE_ADDR_INPUT1" , 0x11F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
+ {"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
+ {"NPI_BASE_ADDR_OUTPUT1" , 0x11F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
+ {"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
+ {"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
+ {"NPI_BUFF_SIZE_OUTPUT1" , 0x11F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
+ {"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
+ {"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
+ {"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
+ {"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
+ {"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
+ {"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
+ {"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
+ {"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
+ {"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
+ {"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 302},
+ {"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
+ {"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
+ {"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
+ {"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 306},
+ {"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
+ {"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
+ {"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
+ {"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
+ {"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 308},
+ {"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 309},
+ {"NPI_NUM_DESC_OUTPUT1" , 0x11F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 309},
+ {"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 310},
+ {"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 311},
+ {"NPI_P1_DBPAIR_ADDR" , 0x11F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 311},
+ {"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 312},
+ {"NPI_P1_INSTR_ADDR" , 0x11F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 312},
+ {"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 313},
+ {"NPI_P1_INSTR_CNTS" , 0x11F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 313},
+ {"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
+ {"NPI_P1_PAIR_CNTS" , 0x11F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
+ {"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 315},
+ {"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
+ {"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
+ {"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
+ {"NPI_PORT33_INSTR_HDR" , 0x11F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
+ {"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
+ {"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
+ {"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
+ {"NPI_SIZE_INPUT1" , 0x11F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
+ {"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
+ {"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
+ {"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 325},
+ {"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 326},
+ {"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 327},
+ {"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 328},
+ {"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 329},
+ {"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 330},
+ {"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 331},
+ {"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 332},
+ {"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 333},
+ {"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 334},
+ {"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 335},
+ {"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 336},
+ {"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 337},
+ {"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 338},
+ {"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 339},
+ {"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 340},
+ {"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 341},
+ {"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 342},
+ {"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 343},
+ {"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 344},
+ {"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 345},
+ {"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 346},
+ {"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 347},
+ {"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 348},
+ {"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 349},
+ {"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 350},
+ {"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 351},
+ {"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 352},
+ {"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 353},
+ {"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 354},
+ {"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 355},
+ {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 356},
+ {"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 356},
+ {"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 357},
+ {"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 357},
+ {"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 358},
+ {"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 358},
+ {"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 359},
+ {"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 359},
+ {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
+ {"PCI_INSTR_COUNT1" , 0x8Cull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
+ {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 361},
+ {"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 362},
+ {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 363},
+ {"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 364},
+ {"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 365},
+ {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 366},
+ {"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 366},
+ {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 367},
+ {"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 367},
+ {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 368},
+ {"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 368},
+ {"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 369},
+ {"PCI_PKTS_SENT_TIME1" , 0x5Cull, CVMX_CSR_DB_TYPE_PCI, 32, 369},
+ {"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 370},
+ {"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 371},
+ {"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 372},
+ {"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
+ {"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 374},
+ {"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 375},
+ {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 376},
+ {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 377},
+ {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 378},
+ {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 379},
+ {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 380},
+ {"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
+ {"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
+ {"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
+ {"PCM3_DMA_CFG" , 0x107000001C018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
+ {"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
+ {"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
+ {"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
+ {"PCM3_INT_ENA" , 0x107000001C020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
+ {"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
+ {"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
+ {"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
+ {"PCM3_INT_SUM" , 0x107000001C028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
+ {"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
+ {"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
+ {"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
+ {"PCM3_RXADDR" , 0x107000001C068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
+ {"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
+ {"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
+ {"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
+ {"PCM3_RXCNT" , 0x107000001C060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
+ {"PCM0_RXMSK0" , 0x10700000100C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
+ {"PCM1_RXMSK0" , 0x10700000140C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
+ {"PCM2_RXMSK0" , 0x10700000180C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
+ {"PCM3_RXMSK0" , 0x107000001C0C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
+ {"PCM0_RXMSK1" , 0x10700000100C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
+ {"PCM1_RXMSK1" , 0x10700000140C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
+ {"PCM2_RXMSK1" , 0x10700000180C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
+ {"PCM3_RXMSK1" , 0x107000001C0C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
+ {"PCM0_RXMSK2" , 0x10700000100D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
+ {"PCM1_RXMSK2" , 0x10700000140D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
+ {"PCM2_RXMSK2" , 0x10700000180D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
+ {"PCM3_RXMSK2" , 0x107000001C0D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
+ {"PCM0_RXMSK3" , 0x10700000100D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
+ {"PCM1_RXMSK3" , 0x10700000140D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
+ {"PCM2_RXMSK3" , 0x10700000180D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
+ {"PCM3_RXMSK3" , 0x107000001C0D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
+ {"PCM0_RXMSK4" , 0x10700000100E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
+ {"PCM1_RXMSK4" , 0x10700000140E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
+ {"PCM2_RXMSK4" , 0x10700000180E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
+ {"PCM3_RXMSK4" , 0x107000001C0E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
+ {"PCM0_RXMSK5" , 0x10700000100E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
+ {"PCM1_RXMSK5" , 0x10700000140E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
+ {"PCM2_RXMSK5" , 0x10700000180E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
+ {"PCM3_RXMSK5" , 0x107000001C0E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
+ {"PCM0_RXMSK6" , 0x10700000100F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
+ {"PCM1_RXMSK6" , 0x10700000140F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
+ {"PCM2_RXMSK6" , 0x10700000180F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
+ {"PCM3_RXMSK6" , 0x107000001C0F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
+ {"PCM0_RXMSK7" , 0x10700000100F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
+ {"PCM1_RXMSK7" , 0x10700000140F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
+ {"PCM2_RXMSK7" , 0x10700000180F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
+ {"PCM3_RXMSK7" , 0x107000001C0F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
+ {"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
+ {"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
+ {"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
+ {"PCM3_RXSTART" , 0x107000001C058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
+ {"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
+ {"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
+ {"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
+ {"PCM3_TDM_CFG" , 0x107000001C010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
+ {"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
+ {"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
+ {"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
+ {"PCM3_TDM_DBG" , 0x107000001C030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
+ {"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
+ {"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
+ {"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
+ {"PCM3_TXADDR" , 0x107000001C050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
+ {"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
+ {"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
+ {"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
+ {"PCM3_TXCNT" , 0x107000001C048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
+ {"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
+ {"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
+ {"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
+ {"PCM3_TXMSK0" , 0x107000001C080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
+ {"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
+ {"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
+ {"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
+ {"PCM3_TXMSK1" , 0x107000001C088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
+ {"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
+ {"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
+ {"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
+ {"PCM3_TXMSK2" , 0x107000001C090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
+ {"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
+ {"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
+ {"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
+ {"PCM3_TXMSK3" , 0x107000001C098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
+ {"PCM0_TXMSK4" , 0x10700000100A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
+ {"PCM1_TXMSK4" , 0x10700000140A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
+ {"PCM2_TXMSK4" , 0x10700000180A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
+ {"PCM3_TXMSK4" , 0x107000001C0A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
+ {"PCM0_TXMSK5" , 0x10700000100A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
+ {"PCM1_TXMSK5" , 0x10700000140A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
+ {"PCM2_TXMSK5" , 0x10700000180A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
+ {"PCM3_TXMSK5" , 0x107000001C0A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
+ {"PCM0_TXMSK6" , 0x10700000100B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
+ {"PCM1_TXMSK6" , 0x10700000140B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
+ {"PCM2_TXMSK6" , 0x10700000180B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
+ {"PCM3_TXMSK6" , 0x107000001C0B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
+ {"PCM0_TXMSK7" , 0x10700000100B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
+ {"PCM1_TXMSK7" , 0x10700000140B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
+ {"PCM2_TXMSK7" , 0x10700000180B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
+ {"PCM3_TXMSK7" , 0x107000001C0B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
+ {"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
+ {"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
+ {"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
+ {"PCM3_TXSTART" , 0x107000001C040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
+ {"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
+ {"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
+ {"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
+ {"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
+ {"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
+ {"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
+ {"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
+ {"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
+ {"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
+ {"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
+ {"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
+ {"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
+ {"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
+ {"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
+ {"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
+ {"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
+ {"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
+ {"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
+ {"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
+ {"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
+ {"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
+ {"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
+ {"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
+ {"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
+ {"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
+ {"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
+ {"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
+ {"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
+ {"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
+ {"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
+ {"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
+ {"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
+ {"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
+ {"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
+ {"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
+ {"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
+ {"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
+ {"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
+ {"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
+ {"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
+ {"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
+ {"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
+ {"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
+ {"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
+ {"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
+ {"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
+ {"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
+ {"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
+ {"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
+ {"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
+ {"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
+ {"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
+ {"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
+ {"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
+ {"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
+ {"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
+ {"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
+ {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
+ {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
+ {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
+ {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
+ {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
+ {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
+ {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
+ {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
+ {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
+ {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
+ {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
+ {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
+ {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
+ {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
+ {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
+ {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
+ {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
+ {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
+ {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
+ {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
+ {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
+ {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
+ {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
+ {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
+ {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
+ {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
+ {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
+ {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
+ {"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 471},
+ {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 472},
+ {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
+ {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 474},
+ {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
+ {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 476},
+ {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 477},
+ {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
+ {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
+ {"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
+ {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
+ {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
+ {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
+ {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
+ {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
+ {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
+ {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
+ {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
+ {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
+ {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
+ {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
+ {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
+ {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
+ {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
+ {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
+ {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
+ {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
+ {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
+ {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
+ {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
+ {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
+ {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
+ {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
+ {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
+ {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
+ {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
+ {"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
+ {"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
+ {"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
+ {"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
+ {"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
+ {"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
+ {"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
+ {"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
+ {"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
+ {"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
+ {"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
+ {"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
+ {"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
+ {"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
+ {"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
+ {"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
+ {"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
+ {"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
+ {"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
+ {"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
+ {"USBC0_DAINT" , 0x16F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
+ {"USBC0_DAINTMSK" , 0x16F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 528},
+ {"USBC0_DCFG" , 0x16F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
+ {"USBC0_DCTL" , 0x16F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
+ {"USBC0_DIEPCTL000" , 0x16F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
+ {"USBC0_DIEPCTL001" , 0x16F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
+ {"USBC0_DIEPCTL002" , 0x16F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
+ {"USBC0_DIEPCTL003" , 0x16F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
+ {"USBC0_DIEPCTL004" , 0x16F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
+ {"USBC0_DIEPINT000" , 0x16F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
+ {"USBC0_DIEPINT001" , 0x16F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
+ {"USBC0_DIEPINT002" , 0x16F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
+ {"USBC0_DIEPINT003" , 0x16F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
+ {"USBC0_DIEPINT004" , 0x16F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
+ {"USBC0_DIEPMSK" , 0x16F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 533},
+ {"USBC0_DIEPTSIZ000" , 0x16F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
+ {"USBC0_DIEPTSIZ001" , 0x16F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
+ {"USBC0_DIEPTSIZ002" , 0x16F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
+ {"USBC0_DIEPTSIZ003" , 0x16F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
+ {"USBC0_DIEPTSIZ004" , 0x16F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
+ {"USBC0_DOEPCTL000" , 0x16F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
+ {"USBC0_DOEPCTL001" , 0x16F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
+ {"USBC0_DOEPCTL002" , 0x16F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
+ {"USBC0_DOEPCTL003" , 0x16F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
+ {"USBC0_DOEPCTL004" , 0x16F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
+ {"USBC0_DOEPINT000" , 0x16F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
+ {"USBC0_DOEPINT001" , 0x16F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
+ {"USBC0_DOEPINT002" , 0x16F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
+ {"USBC0_DOEPINT003" , 0x16F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
+ {"USBC0_DOEPINT004" , 0x16F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
+ {"USBC0_DOEPMSK" , 0x16F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 537},
+ {"USBC0_DOEPTSIZ000" , 0x16F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
+ {"USBC0_DOEPTSIZ001" , 0x16F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
+ {"USBC0_DOEPTSIZ002" , 0x16F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
+ {"USBC0_DOEPTSIZ003" , 0x16F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
+ {"USBC0_DOEPTSIZ004" , 0x16F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
+ {"USBC0_DPTXFSIZ001" , 0x16F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
+ {"USBC0_DPTXFSIZ002" , 0x16F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
+ {"USBC0_DPTXFSIZ003" , 0x16F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
+ {"USBC0_DPTXFSIZ004" , 0x16F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
+ {"USBC0_DSTS" , 0x16F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 540},
+ {"USBC0_DTKNQR1" , 0x16F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 541},
+ {"USBC0_DTKNQR2" , 0x16F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 542},
+ {"USBC0_DTKNQR3" , 0x16F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 543},
+ {"USBC0_DTKNQR4" , 0x16F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 544},
+ {"USBC0_GAHBCFG" , 0x16F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
+ {"USBC0_GHWCFG1" , 0x16F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 546},
+ {"USBC0_GHWCFG2" , 0x16F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
+ {"USBC0_GHWCFG3" , 0x16F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
+ {"USBC0_GHWCFG4" , 0x16F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
+ {"USBC0_GINTMSK" , 0x16F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
+ {"USBC0_GINTSTS" , 0x16F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 551},
+ {"USBC0_GNPTXFSIZ" , 0x16F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 552},
+ {"USBC0_GNPTXSTS" , 0x16F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 553},
+ {"USBC0_GOTGCTL" , 0x16F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 554},
+ {"USBC0_GOTGINT" , 0x16F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 555},
+ {"USBC0_GRSTCTL" , 0x16F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
+ {"USBC0_GRXFSIZ" , 0x16F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 557},
+ {"USBC0_GRXSTSPD" , 0x16F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 558},
+ {"USBC0_GRXSTSPH" , 0x16F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 559},
+ {"USBC0_GRXSTSRD" , 0x16F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 560},
+ {"USBC0_GRXSTSRH" , 0x16F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 561},
+ {"USBC0_GSNPSID" , 0x16F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 562},
+ {"USBC0_GUSBCFG" , 0x16F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 563},
+ {"USBC0_HAINT" , 0x16F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 564},
+ {"USBC0_HAINTMSK" , 0x16F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 565},
+ {"USBC0_HCCHAR000" , 0x16F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
+ {"USBC0_HCCHAR001" , 0x16F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
+ {"USBC0_HCCHAR002" , 0x16F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
+ {"USBC0_HCCHAR003" , 0x16F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
+ {"USBC0_HCCHAR004" , 0x16F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
+ {"USBC0_HCCHAR005" , 0x16F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
+ {"USBC0_HCCHAR006" , 0x16F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
+ {"USBC0_HCCHAR007" , 0x16F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
+ {"USBC0_HCFG" , 0x16F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 567},
+ {"USBC0_HCINT000" , 0x16F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
+ {"USBC0_HCINT001" , 0x16F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
+ {"USBC0_HCINT002" , 0x16F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
+ {"USBC0_HCINT003" , 0x16F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
+ {"USBC0_HCINT004" , 0x16F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
+ {"USBC0_HCINT005" , 0x16F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
+ {"USBC0_HCINT006" , 0x16F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
+ {"USBC0_HCINT007" , 0x16F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
+ {"USBC0_HCINTMSK000" , 0x16F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
+ {"USBC0_HCINTMSK001" , 0x16F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
+ {"USBC0_HCINTMSK002" , 0x16F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
+ {"USBC0_HCINTMSK003" , 0x16F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
+ {"USBC0_HCINTMSK004" , 0x16F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
+ {"USBC0_HCINTMSK005" , 0x16F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
+ {"USBC0_HCINTMSK006" , 0x16F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
+ {"USBC0_HCINTMSK007" , 0x16F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
+ {"USBC0_HCSPLT000" , 0x16F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
+ {"USBC0_HCSPLT001" , 0x16F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
+ {"USBC0_HCSPLT002" , 0x16F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
+ {"USBC0_HCSPLT003" , 0x16F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
+ {"USBC0_HCSPLT004" , 0x16F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
+ {"USBC0_HCSPLT005" , 0x16F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
+ {"USBC0_HCSPLT006" , 0x16F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
+ {"USBC0_HCSPLT007" , 0x16F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
+ {"USBC0_HCTSIZ000" , 0x16F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
+ {"USBC0_HCTSIZ001" , 0x16F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
+ {"USBC0_HCTSIZ002" , 0x16F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
+ {"USBC0_HCTSIZ003" , 0x16F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
+ {"USBC0_HCTSIZ004" , 0x16F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
+ {"USBC0_HCTSIZ005" , 0x16F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
+ {"USBC0_HCTSIZ006" , 0x16F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
+ {"USBC0_HCTSIZ007" , 0x16F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
+ {"USBC0_HFIR" , 0x16F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 572},
+ {"USBC0_HFNUM" , 0x16F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 573},
+ {"USBC0_HPRT" , 0x16F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 574},
+ {"USBC0_HPTXFSIZ" , 0x16F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 575},
+ {"USBC0_HPTXSTS" , 0x16F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 576},
+ {"USBC0_NPTXDFIFO000" , 0x16F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
+ {"USBC0_NPTXDFIFO001" , 0x16F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
+ {"USBC0_NPTXDFIFO002" , 0x16F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
+ {"USBC0_NPTXDFIFO003" , 0x16F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
+ {"USBC0_NPTXDFIFO004" , 0x16F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
+ {"USBC0_NPTXDFIFO005" , 0x16F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
+ {"USBC0_NPTXDFIFO006" , 0x16F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
+ {"USBC0_NPTXDFIFO007" , 0x16F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
+ {"USBC0_PCGCCTL" , 0x16F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 578},
+ {"USBN0_BIST_STATUS" , 0x11800680007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
+ {"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
+ {"USBN0_CTL_STATUS" , 0x16F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 581},
+ {"USBN0_DMA0_INB_CHN0" , 0x16F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 582},
+ {"USBN0_DMA0_INB_CHN1" , 0x16F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
+ {"USBN0_DMA0_INB_CHN2" , 0x16F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
+ {"USBN0_DMA0_INB_CHN3" , 0x16F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
+ {"USBN0_DMA0_INB_CHN4" , 0x16F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 586},
+ {"USBN0_DMA0_INB_CHN5" , 0x16F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 587},
+ {"USBN0_DMA0_INB_CHN6" , 0x16F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
+ {"USBN0_DMA0_INB_CHN7" , 0x16F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
+ {"USBN0_DMA0_OUTB_CHN0" , 0x16F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
+ {"USBN0_DMA0_OUTB_CHN1" , 0x16F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 591},
+ {"USBN0_DMA0_OUTB_CHN2" , 0x16F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
+ {"USBN0_DMA0_OUTB_CHN3" , 0x16F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
+ {"USBN0_DMA0_OUTB_CHN4" , 0x16F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
+ {"USBN0_DMA0_OUTB_CHN5" , 0x16F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 595},
+ {"USBN0_DMA0_OUTB_CHN6" , 0x16F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 596},
+ {"USBN0_DMA0_OUTB_CHN7" , 0x16F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
+ {"USBN0_DMA_TEST" , 0x16F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 598},
+ {"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
+ {"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
+ {"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
+ {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
+ {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
+ {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
+ {"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
+ {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 606},
+ {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
+ {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
+ {NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
+ /* name , bit, width, csr, type, rst un, typ un, reset, typical */
+ {"SETTING" , 0, 5, 0, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 0, "RAZ", 1, 1, 0, 0},
+ {"SETTING" , 0, 5, 1, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 1, "RAZ", 1, 1, 0, 0},
+ {"OVRFLW" , 0, 3, 2, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_3_3" , 3, 1, 2, "RAZ", 1, 1, 0, 0},
+ {"TXPOP" , 4, 3, 2, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
+ {"TXPSH" , 8, 3, 2, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_11_63" , 11, 53, 2, "RAZ", 1, 1, 0, 0},
+ {"OVRFLW" , 0, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_3" , 3, 1, 3, "RAZ", 1, 1, 0, 0},
+ {"TXPOP" , 4, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_7" , 7, 1, 3, "RAZ", 1, 1, 0, 0},
+ {"TXPSH" , 8, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_63" , 11, 53, 3, "RAZ", 1, 1, 0, 0},
+ {"INT_LOOP" , 0, 3, 4, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_3" , 3, 1, 4, "RAZ", 1, 1, 0, 0},
+ {"EXT_LOOP" , 4, 3, 4, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_63" , 7, 57, 4, "RAZ", 1, 1, 0, 0},
+ {"SETTING" , 0, 5, 5, "R/W", 0, 0, 24ull, 24ull},
+ {"RESERVED_5_63" , 5, 59, 5, "RAZ", 1, 1, 0, 0},
+ {"PRT_EN" , 0, 3, 6, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_3_63" , 3, 61, 6, "RAZ", 1, 1, 0, 0},
+ {"SETTING" , 0, 5, 7, "R/W", 0, 0, 24ull, 24ull},
+ {"RESERVED_5_63" , 5, 59, 7, "RAZ", 1, 1, 0, 0},
+ {"NCTL" , 0, 4, 8, "R/W", 0, 0, 8ull, 8ull},
+ {"PCTL" , 4, 4, 8, "R/W", 0, 0, 8ull, 8ull},
+ {"BYPASS" , 8, 1, 8, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 8, "RAZ", 1, 1, 0, 0},
+ {"MARK" , 0, 3, 9, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 9, "RAZ", 1, 1, 0, 0},
+ {"PRT_EN" , 0, 3, 10, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_3_63" , 3, 61, 10, "RAZ", 1, 1, 0, 0},
+ {"BIST" , 0, 4, 11, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 11, "RAZ", 1, 1, 0, 0},
+ {"DINT" , 0, 2, 12, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 12, "RAZ", 1, 1, 0, 0},
+ {"FUSE" , 0, 2, 13, "RO", 1, 1, 0, 0},
+ {"RESERVED_2_63" , 2, 62, 13, "RAZ", 1, 1, 0, 0},
+ {"GSTOP" , 0, 1, 14, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 14, "RAZ", 1, 1, 0, 0},
+ {"WORKQ" , 0, 16, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"GPIO" , 16, 16, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"MBOX" , 32, 2, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"UART" , 34, 2, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"PCI_INT" , 36, 4, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"PCI_MSI" , 40, 4, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_44_44" , 44, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"TWSI" , 45, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"RML" , 46, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"TRACE" , 47, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"GMX_DRP" , 48, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_49_49" , 49, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"IPD_DRP" , 50, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_51_51" , 51, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"TIMER" , 52, 4, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"USB" , 56, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"PCM" , 57, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"MPI" , 58, 1, 15, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_59_63" , 59, 5, 15, "RAZ", 1, 1, 0, 0},
+ {"WDOG" , 0, 2, 16, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 16, "RAZ", 1, 1, 0, 0},
+ {"WORKQ" , 0, 16, 17, "RO", 0, 0, 0ull, 0ull},
+ {"GPIO" , 16, 16, 17, "RO", 0, 0, 0ull, 0ull},
+ {"MBOX" , 32, 2, 17, "RO", 0, 0, 0ull, 0ull},
+ {"UART" , 34, 2, 17, "RO", 0, 0, 0ull, 0ull},
+ {"PCI_INT" , 36, 4, 17, "RO", 0, 0, 0ull, 0ull},
+ {"PCI_MSI" , 40, 4, 17, "RO", 0, 0, 0ull, 0ull},
+ {"WDOG_SUM" , 44, 1, 17, "RO", 0, 0, 0ull, 0ull},
+ {"TWSI" , 45, 1, 17, "RO", 0, 0, 0ull, 0ull},
+ {"RML" , 46, 1, 17, "RO", 0, 0, 0ull, 0ull},
+ {"TRACE" , 47, 1, 17, "RO", 0, 0, 0ull, 0ull},
+ {"GMX_DRP" , 48, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_49_49" , 49, 1, 17, "RAZ", 1, 1, 0, 0},
+ {"IPD_DRP" , 50, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_51_51" , 51, 1, 17, "RAZ", 1, 1, 0, 0},
+ {"TIMER" , 52, 4, 17, "R/W1C", 0, 0, 0ull, 0ull},
+ {"USB" , 56, 1, 17, "RO", 0, 0, 0ull, 0ull},
+ {"PCM" , 57, 1, 17, "RO", 0, 0, 0ull, 0ull},
+ {"MPI" , 58, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_59_63" , 59, 5, 17, "RAZ", 1, 1, 0, 0},
+ {"WDOG" , 0, 2, 18, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 18, "RAZ", 1, 1, 0, 0},
+ {"BITS" , 0, 32, 19, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 19, "RAZ", 1, 1, 0, 0},
+ {"BITS" , 0, 32, 20, "R/W1", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 20, "RAZ", 1, 1, 0, 0},
+ {"NMI" , 0, 2, 21, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 21, "RAZ", 1, 1, 0, 0},
+ {"INTR" , 0, 2, 22, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 22, "RAZ", 1, 1, 0, 0},
+ {"PPDBG" , 0, 2, 23, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 23, "RAZ", 1, 1, 0, 0},
+ {"POKE" , 0, 64, 24, "RAZ", 1, 1, 0, 0},
+ {"RST0" , 0, 1, 25, "R/W", 1, 1, 0, 0},
+ {"RST" , 1, 1, 25, "R/W", 0, 0, 1ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 25, "RAZ", 1, 1, 0, 0},
+ {"SOFT_BIST" , 0, 1, 26, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 26, "RAZ", 1, 1, 0, 0},
+ {"SOFT_PRST" , 0, 1, 27, "R/W", 0, 0, 1ull, 0ull},
+ {"NPI" , 1, 1, 27, "R/W", 0, 0, 0ull, 0ull},
+ {"HOST64" , 2, 1, 27, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 27, "RAZ", 1, 1, 0, 0},
+ {"SOFT_RST" , 0, 1, 28, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 28, "RAZ", 1, 1, 0, 0},
+ {"LEN" , 0, 36, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"ONE_SHOT" , 36, 1, 29, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_37_63" , 37, 27, 29, "RAZ", 1, 1, 0, 0},
+ {"MODE" , 0, 2, 30, "R/W", 0, 0, 0ull, 0ull},
+ {"STATE" , 2, 2, 30, "RO", 0, 0, 0ull, 0ull},
+ {"LEN" , 4, 16, 30, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT" , 20, 24, 30, "RO", 0, 0, 0ull, 0ull},
+ {"DSTOP" , 44, 1, 30, "R/W", 0, 0, 0ull, 0ull},
+ {"GSTOPEN" , 45, 1, 30, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_46_63" , 46, 18, 30, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 17, 31, "RO", 0, 1, 0ull, 0},
+ {"DSEL_EXT" , 17, 1, 31, "R/W", 0, 0, 1ull, 0ull},
+ {"C_MUL" , 18, 5, 31, "RO", 1, 1, 0, 0},
+ {"RESERVED_23_27" , 23, 5, 31, "RAZ", 1, 1, 0, 0},
+ {"PLL_MUL" , 28, 3, 31, "RO", 1, 1, 0, 0},
+ {"RESERVED_31_63" , 31, 33, 31, "RAZ", 1, 1, 0, 0},
+ {"PDF" , 0, 16, 32, "RO", 0, 0, 0ull, 0ull},
+ {"RDF" , 16, 16, 32, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 32, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_0_17" , 0, 18, 33, "RAZ", 0, 0, 0ull, 0ull},
+ {"CRF" , 18, 1, 33, "RO", 0, 0, 0ull, 0ull},
+ {"DRF" , 19, 1, 33, "RO", 0, 0, 0ull, 0ull},
+ {"GFU" , 20, 1, 33, "RO", 0, 0, 0ull, 0ull},
+ {"IFU" , 21, 1, 33, "RO", 0, 0, 0ull, 0ull},
+ {"CRQ" , 22, 1, 33, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_63" , 23, 41, 33, "RAZ", 0, 0, 0ull, 0ull},
+ {"DBELL" , 0, 20, 34, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_20_63" , 20, 44, 34, "RAZ", 1, 1, 0, 0},
+ {"NUM_COLS" , 0, 2, 35, "R/W", 0, 0, 1ull, 1ull},
+ {"NUM_COLROWS" , 2, 3, 35, "R/W", 0, 0, 1ull, 1ull},
+ {"RNK_LO" , 5, 1, 35, "R/W", 0, 0, 0ull, 0ull},
+ {"NUM_RNKS" , 6, 2, 35, "R/W", 0, 0, 0ull, 0ull},
+ {"RDIMM_ENA" , 8, 1, 35, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
+ {"BUS_CNT" , 0, 47, 36, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_47_63" , 47, 17, 36, "RAZ", 1, 1, 0, 0},
+ {"PRTENA" , 0, 1, 37, "R/W", 0, 0, 0ull, 1ull},
+ {"INIT" , 1, 1, 37, "R/W", 0, 0, 0ull, 0ull},
+ {"FPRCH" , 2, 1, 37, "R/W", 0, 0, 0ull, 0ull},
+ {"BPRCH" , 3, 1, 37, "R/W", 0, 0, 0ull, 0ull},
+ {"SIL_LAT" , 4, 2, 37, "R/W", 0, 0, 1ull, 1ull},
+ {"SILO_HC" , 6, 1, 37, "R/W", 0, 0, 0ull, 0ull},
+ {"SILO_QC" , 7, 1, 37, "R/W", 0, 0, 0ull, 0ull},
+ {"RNK_MSK" , 8, 4, 37, "R/W", 0, 0, 0ull, 15ull},
+ {"TSKW" , 12, 2, 37, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_14_15" , 14, 2, 37, "RAZ", 0, 0, 0ull, 0ull},
+ {"REF_INT" , 16, 13, 37, "R/W", 0, 0, 780ull, 780ull},
+ {"RESERVED_29_31" , 29, 3, 37, "RAZ", 1, 1, 0, 0},
+ {"FPIP" , 32, 3, 37, "R/W", 0, 0, 0ull, 0ull},
+ {"MRS_PGM" , 35, 1, 37, "R/W", 0, 0, 0ull, 0ull},
+ {"TRFC" , 36, 5, 37, "R/W", 0, 0, 9ull, 9ull},
+ {"RESERVED_41_63" , 41, 23, 37, "RAZ", 1, 1, 0, 0},
+ {"COMP_BYPASS" , 0, 1, 38, "R/W", 0, 0, 0ull, 1ull},
+ {"NCTL_CSR" , 1, 4, 38, "R/W", 0, 1, 13ull, 0},
+ {"PCTL_CSR" , 5, 4, 38, "R/W", 0, 1, 13ull, 0},
+ {"RESERVED_9_55" , 9, 47, 38, "RAZ", 1, 1, 0, 0},
+ {"DFA__NCTL" , 56, 4, 38, "RO", 1, 1, 0, 0},
+ {"DFA__PCTL" , 60, 4, 38, "RO", 1, 1, 0, 0},
+ {"EMRS1" , 0, 15, 39, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_15_15" , 15, 1, 39, "RAZ", 1, 1, 0, 0},
+ {"EMRS1_OCD" , 16, 15, 39, "R/W", 0, 0, 896ull, 896ull},
+ {"RESERVED_31_63" , 31, 33, 39, "RAZ", 1, 1, 0, 0},
+ {"FCYC_CNT" , 0, 47, 40, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_47_63" , 47, 17, 40, "RAZ", 1, 1, 0, 0},
+ {"MRS_DLL" , 0, 15, 41, "R/W", 0, 0, 1858ull, 1858ull},
+ {"RESERVED_15_15" , 15, 1, 41, "RAZ", 1, 1, 0, 0},
+ {"MRS" , 16, 15, 41, "R/W", 0, 0, 1602ull, 1602ull},
+ {"RESERVED_31_63" , 31, 33, 41, "RAZ", 1, 1, 0, 0},
+ {"MAX_WRITE_BATCH" , 0, 5, 42, "R/W", 0, 0, 31ull, 31ull},
+ {"MAX_READ_BATCH" , 5, 5, 42, "R/W", 0, 0, 31ull, 31ull},
+ {"RESERVED_10_63" , 10, 54, 42, "RAZ", 1, 1, 0, 0},
+ {"PLL_INIT" , 0, 1, 43, "R/W", 0, 0, 0ull, 1ull},
+ {"PLL_BYPASS" , 1, 1, 43, "R/W", 0, 0, 0ull, 0ull},
+ {"PLL_RATIO" , 2, 5, 43, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_7_7" , 7, 1, 43, "RAZ", 1, 1, 0, 0},
+ {"PLL_DIV2" , 8, 1, 43, "R/W", 0, 0, 0ull, 0ull},
+ {"BW_UPD" , 9, 1, 43, "R/W", 0, 0, 0ull, 0ull},
+ {"BW_CTL" , 10, 4, 43, "R/W", 0, 1, 0ull, 0},
+ {"QDLL_ENA" , 14, 1, 43, "R/W", 0, 0, 0ull, 1ull},
+ {"DLL_BYP" , 15, 1, 43, "R/W", 0, 1, 0ull, 0},
+ {"DLL_SETTING" , 16, 5, 43, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_21_26" , 21, 6, 43, "RAZ", 1, 1, 0, 0},
+ {"SETTING90" , 27, 5, 43, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_46" , 32, 15, 43, "RAZ", 1, 1, 0, 0},
+ {"PLL_SETTING" , 47, 17, 43, "RO", 0, 0, 0ull, 0ull},
+ {"DDR2T" , 0, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"TMRD" , 1, 2, 44, "R/W", 0, 0, 2ull, 2ull},
+ {"CASLAT" , 3, 3, 44, "R/W", 0, 0, 4ull, 4ull},
+ {"POCAS" , 6, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"ADDLAT" , 7, 3, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"TRCD" , 10, 4, 44, "R/W", 0, 0, 2ull, 2ull},
+ {"TRRD" , 14, 3, 44, "R/W", 0, 0, 2ull, 2ull},
+ {"TRAS" , 17, 5, 44, "R/W", 0, 0, 10ull, 10ull},
+ {"TRP" , 22, 4, 44, "R/W", 0, 0, 4ull, 4ull},
+ {"TWR" , 26, 3, 44, "R/W", 0, 0, 3ull, 3ull},
+ {"TWTR" , 29, 4, 44, "R/W", 0, 0, 2ull, 2ull},
+ {"TFAW" , 33, 5, 44, "R/W", 0, 0, 9ull, 9ull},
+ {"R2R_SLOT" , 38, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"DIC" , 39, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"DQSN_ENA" , 40, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"ODT_RTT" , 41, 2, 44, "R/W", 0, 0, 2ull, 2ull},
+ {"CTR_RST" , 43, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"CAVMIPO" , 44, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT_CLR" , 45, 1, 44, "R/W", 0, 0, 0ull, 0ull},
+ {"FCNT_MODE" , 46, 1, 44, "R/W", 0, 0, 1ull, 0ull},
+ {"RESERVED_47_63" , 47, 17, 44, "RAZ", 0, 0, 0ull, 0ull},
+ {"SIZE" , 0, 9, 45, "R/W", 0, 1, 3ull, 0},
+ {"POOL" , 9, 3, 45, "R/W", 0, 1, 0ull, 0},
+ {"DWBCNT" , 12, 8, 45, "R/W", 0, 1, 1ull, 0},
+ {"RESERVED_20_63" , 20, 44, 45, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_4" , 0, 5, 46, "RAZ", 1, 1, 0, 0},
+ {"RDPTR" , 5, 31, 46, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 46, "RAZ", 1, 1, 0, 0},
+ {"DFA_FRSTN" , 0, 1, 47, "R/W", 0, 0, 0ull, 1ull},
+ {"MAXBNK" , 1, 1, 47, "R/W", 0, 0, 1ull, 1ull},
+ {"DTECLKDIS" , 2, 1, 47, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_7" , 3, 5, 47, "RAZ", 0, 0, 0ull, 9ull},
+ {"SARB" , 8, 1, 47, "R/W", 0, 0, 1ull, 1ull},
+ {"IMODE" , 9, 1, 47, "R/W", 0, 0, 1ull, 1ull},
+ {"QMODE" , 10, 1, 47, "R/W", 0, 0, 1ull, 1ull},
+ {"PMODE" , 11, 1, 47, "R/W", 0, 0, 1ull, 1ull},
+ {"DTMODE" , 12, 1, 47, "R/W", 0, 0, 1ull, 1ull},
+ {"DCMODE" , 13, 1, 47, "R/W", 0, 0, 0ull, 0ull},
+ {"SBDLCK" , 14, 1, 47, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_15_15" , 15, 1, 47, "RAZ", 1, 1, 0, 0},
+ {"SBDNUM" , 16, 3, 47, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 47, "RAZ", 1, 1, 0, 0},
+ {"CP2ECCENA" , 0, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2SBE" , 1, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CP2DBE" , 2, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CP2SBINA" , 3, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2DBINA" , 4, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2SYN" , 5, 8, 48, "RO", 0, 0, 0ull, 0ull},
+ {"DTEECCENA" , 13, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"DTESBE" , 14, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTEDBE" , 15, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTESBINA" , 16, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"DTEDBINA" , 17, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"DTESYN" , 18, 7, 48, "RO", 0, 0, 0ull, 0ull},
+ {"DTEPARENA" , 25, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"DTEPERR" , 26, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTEPINA" , 27, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2PARENA" , 28, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"CP2PERR" , 29, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CP2PINA" , 30, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"DBLOVF" , 31, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DBLINA" , 32, 1, 48, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_33_63" , 33, 31, 48, "RAZ", 1, 1, 0, 0},
+ {"MADDR" , 0, 25, 49, "RO", 0, 0, 0ull, 0ull},
+ {"BNUM" , 25, 3, 49, "RO", 0, 0, 0ull, 0ull},
+ {"PNUM" , 28, 1, 49, "RO", 0, 0, 0ull, 0ull},
+ {"FSRC" , 29, 2, 49, "RO", 0, 0, 0ull, 0ull},
+ {"FDST" , 31, 9, 49, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_40_63" , 40, 24, 49, "RAZ", 1, 1, 0, 0},
+ {"SBD0" , 0, 64, 50, "RO", 1, 1, 0, 0},
+ {"SBD1" , 0, 64, 51, "RO", 1, 1, 0, 0},
+ {"SBD2" , 0, 64, 52, "RO", 1, 1, 0, 0},
+ {"SBD3" , 0, 64, 53, "RO", 1, 1, 0, 0},
+ {"FDR" , 0, 1, 54, "RO", 0, 0, 0ull, 0ull},
+ {"FFR" , 1, 1, 54, "RO", 0, 0, 0ull, 0ull},
+ {"FPF1" , 2, 1, 54, "RO", 0, 0, 0ull, 0ull},
+ {"FPF0" , 3, 1, 54, "RO", 0, 0, 0ull, 0ull},
+ {"FRD" , 4, 1, 54, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 54, "RAZ", 1, 1, 0, 0},
+ {"MEM0_ERR" , 0, 7, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"MEM1_ERR" , 7, 7, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"ENB" , 14, 1, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"USE_STT" , 15, 1, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"USE_LDT" , 16, 1, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"RESET" , 17, 1, 55, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 55, "RAZ", 1, 1, 0, 0},
+ {"FED0_SBE" , 0, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"FED0_DBE" , 1, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"FED1_SBE" , 2, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"FED1_DBE" , 3, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q0_UND" , 4, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q0_COFF" , 5, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q0_PERR" , 6, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q1_UND" , 7, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q1_COFF" , 8, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q1_PERR" , 9, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q2_UND" , 10, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q2_COFF" , 11, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q2_PERR" , 12, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q3_UND" , 13, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q3_COFF" , 14, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q3_PERR" , 15, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q4_UND" , 16, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q4_COFF" , 17, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q4_PERR" , 18, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q5_UND" , 19, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q5_COFF" , 20, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q5_PERR" , 21, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q6_UND" , 22, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q6_COFF" , 23, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q6_PERR" , 24, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q7_UND" , 25, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q7_COFF" , 26, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"Q7_PERR" , 27, 1, 56, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_28_63" , 28, 36, 56, "RAZ", 1, 1, 0, 0},
+ {"FED0_SBE" , 0, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FED0_DBE" , 1, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FED1_SBE" , 2, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FED1_DBE" , 3, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q0_UND" , 4, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q0_COFF" , 5, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q0_PERR" , 6, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q1_UND" , 7, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q1_COFF" , 8, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q1_PERR" , 9, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q2_UND" , 10, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q2_COFF" , 11, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q2_PERR" , 12, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q3_UND" , 13, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q3_COFF" , 14, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q3_PERR" , 15, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q4_UND" , 16, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q4_COFF" , 17, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q4_PERR" , 18, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q5_UND" , 19, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q5_COFF" , 20, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q5_PERR" , 21, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q6_UND" , 22, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q6_COFF" , 23, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q6_PERR" , 24, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q7_UND" , 25, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q7_COFF" , 26, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q7_PERR" , 27, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_28_63" , 28, 36, 57, "RAZ", 1, 1, 0, 0},
+ {"QUE_SIZ" , 0, 29, 58, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_29_63" , 29, 35, 58, "RAZ", 1, 1, 0, 0},
+ {"PG_NUM" , 0, 25, 59, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_25_63" , 25, 39, 59, "RAZ", 1, 1, 0, 0},
+ {"ACT_INDX" , 0, 26, 60, "RO", 0, 1, 0ull, 0},
+ {"ACT_QUE" , 26, 3, 60, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 60, "RAZ", 0, 0, 0ull, 7ull},
+ {"EXP_INDX" , 0, 26, 61, "RO", 0, 1, 0ull, 0},
+ {"EXP_QUE" , 26, 3, 61, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 61, "RAZ", 0, 0, 0ull, 7ull},
+ {"CTL" , 0, 16, 62, "R/W", 1, 0, 0, 0ull},
+ {"RESERVED_16_63" , 16, 48, 62, "RAZ", 1, 1, 0, 0},
+ {"STATUS" , 0, 32, 63, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 63, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_1" , 0, 2, 64, "RAZ", 0, 0, 0ull, 0ull},
+ {"OUT_OVR" , 2, 3, 64, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_21" , 5, 17, 64, "RAZ", 0, 0, 0ull, 0ull},
+ {"LOSTSTAT" , 22, 3, 64, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_25_25" , 25, 1, 64, "RAZ", 0, 0, 0ull, 0ull},
+ {"STATOVR" , 26, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
+ {"INB_NXA" , 27, 4, 64, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_31_63" , 31, 33, 64, "RAZ", 1, 1, 0, 0},
+ {"STATUS" , 0, 10, 65, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_63" , 10, 54, 65, "RAZ", 1, 1, 0, 0},
+ {"TYPE" , 0, 1, 66, "R/W", 0, 1, 0ull, 0},
+ {"EN" , 1, 1, 66, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_2_63" , 2, 62, 66, "RAZ", 1, 1, 0, 0},
+ {"PRT" , 0, 6, 67, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_6_63" , 6, 58, 67, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 1, 68, "R/W", 0, 1, 0ull, 0},
+ {"SPEED" , 1, 1, 68, "R/W", 0, 1, 1ull, 0},
+ {"DUPLEX" , 2, 1, 68, "R/W", 0, 1, 1ull, 0},
+ {"SLOTTIME" , 3, 1, 68, "R/W", 0, 1, 1ull, 0},
+ {"RESERVED_4_63" , 4, 60, 68, "RAZ", 1, 1, 0, 0},
+ {"ADR" , 0, 64, 69, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 70, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 71, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 72, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 73, "R/W", 0, 1, 0ull, 0},
+ {"ADR" , 0, 64, 74, "R/W", 0, 1, 0ull, 0},
+ {"EN" , 0, 8, 75, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 75, "RAZ", 1, 1, 0, 0},
+ {"BCST" , 0, 1, 76, "R/W", 0, 1, 1ull, 0},
+ {"MCST" , 1, 2, 76, "R/W", 0, 1, 0ull, 0},
+ {"CAM_MODE" , 3, 1, 76, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_4_63" , 4, 60, 76, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 5, 77, "R/W", 0, 0, 24ull, 24ull},
+ {"RESERVED_5_63" , 5, 59, 77, "RAZ", 1, 1, 0, 0},
+ {"MINERR" , 0, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"CAREXT" , 1, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"MAXERR" , 2, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"JABBER" , 3, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"FCSERR" , 4, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"ALNERR" , 5, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"LENERR" , 6, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"RCVERR" , 7, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"SKPERR" , 8, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"NIBERR" , 9, 1, 78, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_10_63" , 10, 54, 78, "RAZ", 1, 1, 0, 0},
+ {"PRE_CHK" , 0, 1, 79, "R/W", 0, 0, 1ull, 1ull},
+ {"PRE_STRP" , 1, 1, 79, "R/W", 0, 0, 1ull, 1ull},
+ {"CTL_DRP" , 2, 1, 79, "R/W", 0, 0, 1ull, 1ull},
+ {"CTL_BCK" , 3, 1, 79, "R/W", 0, 0, 1ull, 1ull},
+ {"CTL_MCST" , 4, 1, 79, "R/W", 0, 0, 1ull, 1ull},
+ {"CTL_SMAC" , 5, 1, 79, "R/W", 0, 0, 1ull, 1ull},
+ {"PRE_FREE" , 6, 1, 79, "R/W", 0, 0, 0ull, 0ull},
+ {"VLAN_LEN" , 7, 1, 79, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 79, "RAZ", 1, 1, 0, 0},
+ {"LEN" , 0, 16, 80, "R/W", 0, 0, 1536ull, 1536ull},
+ {"RESERVED_16_63" , 16, 48, 80, "RAZ", 1, 1, 0, 0},
+ {"LEN" , 0, 16, 81, "R/W", 0, 0, 64ull, 64ull},
+ {"RESERVED_16_63" , 16, 48, 81, "RAZ", 1, 1, 0, 0},
+ {"IFG" , 0, 4, 82, "R/W", 0, 0, 12ull, 12ull},
+ {"RESERVED_4_63" , 4, 60, 82, "RAZ", 1, 1, 0, 0},
+ {"MINERR" , 0, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"CAREXT" , 1, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"MAXERR" , 2, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"JABBER" , 3, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"FCSERR" , 4, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"ALNERR" , 5, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"LENERR" , 6, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"RCVERR" , 7, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"SKPERR" , 8, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"NIBERR" , 9, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"OVRERR" , 10, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"PCTERR" , 11, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"RSVERR" , 12, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"FALERR" , 13, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"COLDET" , 14, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"IFGERR" , 15, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"PHY_LINK" , 16, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"PHY_SPD" , 17, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"PHY_DUPX" , 18, 1, 83, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 83, "RAZ", 1, 1, 0, 0},
+ {"MINERR" , 0, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CAREXT" , 1, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MAXERR" , 2, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"JABBER" , 3, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FCSERR" , 4, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ALNERR" , 5, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"LENERR" , 6, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RCVERR" , 7, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SKPERR" , 8, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"NIBERR" , 9, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"OVRERR" , 10, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCTERR" , 11, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RSVERR" , 12, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FALERR" , 13, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"COLDET" , 14, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"IFGERR" , 15, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PHY_LINK" , 16, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PHY_SPD" , 17, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PHY_DUPX" , 18, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 84, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 16, 85, "R/W", 0, 0, 10240ull, 10240ull},
+ {"RESERVED_16_63" , 16, 48, 85, "RAZ", 1, 1, 0, 0},
+ {"STATUS" , 0, 1, 86, "RO", 0, 1, 0ull, 0},
+ {"SPEED" , 1, 2, 86, "RO", 0, 1, 0ull, 0},
+ {"DUPLEX" , 3, 1, 86, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_4_63" , 4, 60, 86, "RAZ", 1, 1, 0, 0},
+ {"RD_CLR" , 0, 1, 87, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 87, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 48, 88, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 88, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 48, 89, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 89, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 48, 90, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 90, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 48, 91, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 91, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 92, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 92, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 93, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 93, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 94, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 94, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 95, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 95, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 32, 96, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 96, "RAZ", 1, 1, 0, 0},
+ {"LEN" , 0, 7, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_7" , 7, 1, 97, "RAZ", 1, 1, 0, 0},
+ {"FCSSEL" , 8, 1, 97, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 97, "RAZ", 1, 1, 0, 0},
+ {"MARK" , 0, 6, 98, "R/W", 1, 1, 0, 0},
+ {"RESERVED_6_63" , 6, 58, 98, "RAZ", 1, 1, 0, 0},
+ {"MARK" , 0, 6, 99, "R/W", 0, 0, 16ull, 16ull},
+ {"RESERVED_6_63" , 6, 58, 99, "RAZ", 1, 1, 0, 0},
+ {"MARK" , 0, 9, 100, "R/W", 1, 1, 0, 0},
+ {"RESERVED_9_63" , 9, 55, 100, "RAZ", 1, 1, 0, 0},
+ {"COMMIT" , 0, 3, 101, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_15" , 3, 13, 101, "RAZ", 1, 1, 0, 0},
+ {"DROP" , 16, 3, 101, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 101, "RAZ", 1, 1, 0, 0},
+ {"PRTS" , 0, 3, 102, "R/W", 0, 0, 3ull, 3ull},
+ {"RESERVED_3_63" , 3, 61, 102, "RAZ", 1, 1, 0, 0},
+ {"RX" , 0, 3, 103, "RC", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_3" , 3, 1, 103, "RAZ", 1, 1, 0, 0},
+ {"TX" , 4, 3, 103, "RC", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_63" , 7, 57, 103, "RAZ", 1, 1, 0, 0},
+ {"SMAC" , 0, 48, 104, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 16, 105, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BP" , 16, 1, 105, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_63" , 17, 47, 105, "RAZ", 1, 1, 0, 0},
+ {"PREAMBLE" , 0, 1, 106, "R/W", 0, 0, 1ull, 1ull},
+ {"PAD" , 1, 1, 106, "R/W", 0, 0, 1ull, 1ull},
+ {"FCS" , 2, 1, 106, "R/W", 0, 0, 1ull, 1ull},
+ {"FORCE_FCS" , 3, 1, 106, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_4_63" , 4, 60, 106, "RAZ", 1, 1, 0, 0},
+ {"BURST" , 0, 16, 107, "R/W", 0, 0, 8192ull, 8192ull},
+ {"RESERVED_16_63" , 16, 48, 107, "RAZ", 1, 1, 0, 0},
+ {"CLK_CNT" , 0, 6, 108, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_6_63" , 6, 58, 108, "RAZ", 1, 1, 0, 0},
+ {"XSCOL_EN" , 0, 1, 109, "R/W", 0, 0, 1ull, 1ull},
+ {"XSDEF_EN" , 1, 1, 109, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_2_63" , 2, 62, 109, "RAZ", 1, 1, 0, 0},
+ {"MIN_SIZE" , 0, 8, 110, "R/W", 0, 0, 59ull, 59ull},
+ {"RESERVED_8_63" , 8, 56, 110, "RAZ", 1, 1, 0, 0},
+ {"INTERVAL" , 0, 16, 111, "R/W", 0, 1, 16ull, 0},
+ {"RESERVED_16_63" , 16, 48, 111, "RAZ", 1, 1, 0, 0},
+ {"TIME" , 0, 16, 112, "R/W", 0, 1, 96ull, 0},
+ {"RESERVED_16_63" , 16, 48, 112, "RAZ", 1, 1, 0, 0},
+ {"TIME" , 0, 16, 113, "RO", 1, 1, 0, 0},
+ {"RESERVED_16_63" , 16, 48, 113, "RAZ", 1, 1, 0, 0},
+ {"SEND" , 0, 1, 114, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_1_63" , 1, 63, 114, "RAZ", 1, 1, 0, 0},
+ {"SLOT" , 0, 10, 115, "R/W", 0, 0, 512ull, 512ull},
+ {"RESERVED_10_63" , 10, 54, 115, "RAZ", 1, 1, 0, 0},
+ {"TIME" , 0, 16, 116, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 116, "RAZ", 1, 1, 0, 0},
+ {"XSCOL" , 0, 32, 117, "RC/W", 0, 1, 0ull, 0},
+ {"XSDEF" , 32, 32, 117, "RC/W", 0, 1, 0ull, 0},
+ {"MCOL" , 0, 32, 118, "RC/W", 0, 1, 0ull, 0},
+ {"SCOL" , 32, 32, 118, "RC/W", 0, 1, 0ull, 0},
+ {"OCTS" , 0, 48, 119, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 119, "RAZ", 1, 1, 0, 0},
+ {"PKTS" , 0, 32, 120, "RC/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 120, "RAZ", 1, 1, 0, 0},
+ {"HIST0" , 0, 32, 121, "RC/W", 0, 1, 0ull, 0},
+ {"HIST1" , 32, 32, 121, "RC/W", 0, 1, 0ull, 0},
+ {"HIST2" , 0, 32, 122, "RC/W", 0, 1, 0ull, 0},
+ {"HIST3" , 32, 32, 122, "RC/W", 0, 1, 0ull, 0},
+ {"HIST4" , 0, 32, 123, "RC/W", 0, 1, 0ull, 0},
+ {"HIST5" , 32, 32, 123, "RC/W", 0, 1, 0ull, 0},
+ {"HIST6" , 0, 32, 124, "RC/W", 0, 1, 0ull, 0},
+ {"HIST7" , 32, 32, 124, "RC/W", 0, 1, 0ull, 0},
+ {"BCST" , 0, 32, 125, "RC/W", 0, 1, 0ull, 0},
+ {"MCST" , 32, 32, 125, "RC/W", 0, 1, 0ull, 0},
+ {"CTL" , 0, 32, 126, "RC/W", 0, 1, 0ull, 0},
+ {"UNDFLW" , 32, 32, 126, "RC/W", 0, 1, 0ull, 0},
+ {"RD_CLR" , 0, 1, 127, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 127, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 7, 128, "R/W", 0, 0, 32ull, 32ull},
+ {"RESERVED_7_63" , 7, 57, 128, "RAZ", 1, 1, 0, 0},
+ {"BP" , 0, 3, 129, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 129, "RAZ", 1, 1, 0, 0},
+ {"LIMIT" , 0, 5, 130, "R/W", 0, 0, 16ull, 16ull},
+ {"RESERVED_5_63" , 5, 59, 130, "RAZ", 1, 1, 0, 0},
+ {"CORRUPT" , 0, 3, 131, "R/W", 0, 0, 15ull, 15ull},
+ {"RESERVED_3_63" , 3, 61, 131, "RAZ", 1, 1, 0, 0},
+ {"IFG1" , 0, 4, 132, "R/W", 0, 1, 8ull, 0},
+ {"IFG2" , 4, 4, 132, "R/W", 0, 1, 4ull, 0},
+ {"RESERVED_8_63" , 8, 56, 132, "RAZ", 1, 1, 0, 0},
+ {"PKO_NXA" , 0, 1, 133, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_1" , 1, 1, 133, "RAZ", 0, 0, 0ull, 0ull},
+ {"UNDFLW" , 2, 3, 133, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_7" , 5, 3, 133, "RAZ", 0, 0, 0ull, 0ull},
+ {"XSCOL" , 8, 3, 133, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_11" , 11, 1, 133, "RAZ", 0, 0, 0ull, 0ull},
+ {"XSDEF" , 12, 3, 133, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_15_63" , 15, 49, 133, "RAZ", 0, 0, 0ull, 0ull},
+ {"PKO_NXA" , 0, 1, 134, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_1" , 1, 1, 134, "RAZ", 0, 0, 0ull, 0ull},
+ {"UNDFLW" , 2, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_7" , 5, 3, 134, "RAZ", 0, 0, 0ull, 0ull},
+ {"XSCOL" , 8, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_11" , 11, 1, 134, "RAZ", 0, 0, 0ull, 0ull},
+ {"XSDEF" , 12, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_15_63" , 15, 49, 134, "RAZ", 0, 0, 0ull, 0ull},
+ {"JAM" , 0, 8, 135, "R/W", 0, 1, 238ull, 0},
+ {"RESERVED_8_63" , 8, 56, 135, "RAZ", 1, 1, 0, 0},
+ {"LFSR" , 0, 16, 136, "R/W", 0, 1, 65535ull, 0},
+ {"RESERVED_16_63" , 16, 48, 136, "RAZ", 1, 1, 0, 0},
+ {"IGN_FULL" , 0, 3, 137, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_3" , 3, 1, 137, "RAZ", 0, 0, 0ull, 0ull},
+ {"BP" , 4, 3, 137, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_7" , 7, 1, 137, "RAZ", 0, 0, 0ull, 0ull},
+ {"EN" , 8, 3, 137, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_63" , 11, 53, 137, "RAZ", 0, 0, 0ull, 0ull},
+ {"DMAC" , 0, 48, 138, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
+ {"RESERVED_48_63" , 48, 16, 138, "RAZ", 1, 1, 0, 0},
+ {"TYPE" , 0, 16, 139, "R/W", 0, 0, 34824ull, 34824ull},
+ {"RESERVED_16_63" , 16, 48, 139, "RAZ", 1, 1, 0, 0},
+ {"PRTS" , 0, 5, 140, "R/W", 0, 1, 3ull, 0},
+ {"RESERVED_5_63" , 5, 59, 140, "RAZ", 1, 1, 0, 0},
+ {"TX_OE" , 0, 1, 141, "R/W", 0, 0, 0ull, 0ull},
+ {"RX_XOR" , 1, 1, 141, "R/W", 0, 0, 0ull, 0ull},
+ {"INT_EN" , 2, 1, 141, "R/W", 0, 0, 0ull, 0ull},
+ {"INT_TYPE" , 3, 1, 141, "R/W", 0, 0, 0ull, 0ull},
+ {"FIL_CNT" , 4, 4, 141, "R/W", 0, 0, 0ull, 0ull},
+ {"FIL_SEL" , 8, 4, 141, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 141, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_7" , 0, 8, 142, "RAZ", 1, 1, 0, 0},
+ {"BOOT_ENA" , 8, 4, 142, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_12_63" , 12, 52, 142, "RAZ", 1, 1, 0, 0},
+ {"DBG_ENA" , 0, 21, 143, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_21_63" , 21, 43, 143, "RAZ", 1, 1, 0, 0},
+ {"TYPE" , 0, 16, 144, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 144, "RAZ", 1, 1, 0, 0},
+ {"DAT" , 0, 24, 145, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_24_63" , 24, 40, 145, "RAZ", 1, 1, 0, 0},
+ {"CLR" , 0, 24, 146, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_24_63" , 24, 40, 146, "RAZ", 1, 1, 0, 0},
+ {"SET" , 0, 24, 147, "WO", 0, 0, 0ull, 0ull},
+ {"RESERVED_24_63" , 24, 40, 147, "RAZ", 1, 1, 0, 0},
+ {"TX_OE" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
+ {"RX_XOR" , 1, 1, 148, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_3" , 2, 2, 148, "RAZ", 1, 1, 0, 0},
+ {"FIL_CNT" , 4, 4, 148, "R/W", 0, 0, 0ull, 0ull},
+ {"FIL_SEL" , 8, 4, 148, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 148, "RAZ", 1, 1, 0, 0},
+ {"ICD" , 0, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"IBD" , 1, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICRP1" , 2, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICRP0" , 3, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICRN1" , 4, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICRN0" , 5, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"IBRQ1" , 6, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"IBRQ0" , 7, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICNRT" , 8, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"IBR1" , 9, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"IBR0" , 10, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"IBDR1" , 11, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"IBDR0" , 12, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICNR0" , 13, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICNR1" , 14, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICR1" , 15, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICR0" , 16, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"ICNRCB" , 17, 1, 149, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 149, "RAZ", 1, 1, 0, 0},
+ {"FAU_END" , 0, 1, 150, "R/W", 0, 0, 0ull, 0ull},
+ {"DWB_ENB" , 1, 1, 150, "R/W", 0, 0, 1ull, 1ull},
+ {"PKO_ENB" , 2, 1, 150, "R/W", 0, 0, 0ull, 0ull},
+ {"INB_MAT" , 3, 1, 150, "R/W1C", 0, 0, 0ull, 0ull},
+ {"OUTB_MAT" , 4, 1, 150, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 150, "RAZ", 1, 1, 0, 0},
+ {"TOUT_VAL" , 0, 12, 151, "R/W", 0, 0, 4ull, 4ull},
+ {"TOUT_ENB" , 12, 1, 151, "R/W", 0, 0, 1ull, 0ull},
+ {"RESERVED_13_63" , 13, 51, 151, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 8, 152, "R/W", 0, 1, 0ull, 0},
+ {"DST" , 8, 9, 152, "R/W", 0, 1, 0ull, 0},
+ {"OPC" , 17, 4, 152, "R/W", 0, 1, 0ull, 0},
+ {"MASK" , 21, 8, 152, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 152, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 8, 153, "R/W", 0, 1, 0ull, 0},
+ {"DST" , 8, 9, 153, "R/W", 0, 1, 0ull, 0},
+ {"OPC" , 17, 4, 153, "R/W", 0, 1, 0ull, 0},
+ {"MASK" , 21, 8, 153, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_29_63" , 29, 35, 153, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 64, 154, "R/W", 0, 1, 0ull, 0},
+ {"DATA" , 0, 64, 155, "R/W", 0, 1, 0ull, 0},
+ {"NP_SOP" , 0, 1, 156, "R/W", 0, 0, 0ull, 0ull},
+ {"NP_EOP" , 1, 1, 156, "R/W", 0, 0, 0ull, 0ull},
+ {"P_SOP" , 2, 1, 156, "R/W", 0, 0, 0ull, 0ull},
+ {"P_EOP" , 3, 1, 156, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 156, "RAZ", 1, 1, 0, 0},
+ {"NP_SOP" , 0, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
+ {"NP_EOP" , 1, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P_SOP" , 2, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P_EOP" , 3, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 157, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 9, 158, "R/W", 0, 1, 0ull, 0},
+ {"DST" , 9, 8, 158, "R/W", 0, 1, 0ull, 0},
+ {"EOT" , 17, 1, 158, "R/W", 0, 1, 0ull, 0},
+ {"MASK" , 18, 8, 158, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_26_63" , 26, 38, 158, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 9, 159, "R/W", 0, 1, 0ull, 0},
+ {"DST" , 9, 8, 159, "R/W", 0, 1, 0ull, 0},
+ {"EOT" , 17, 1, 159, "R/W", 0, 1, 0ull, 0},
+ {"MASK" , 18, 8, 159, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_26_63" , 26, 38, 159, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 64, 160, "R/W", 0, 1, 0ull, 0},
+ {"DATA" , 0, 64, 161, "R/W", 0, 1, 0ull, 0},
+ {"PORT" , 0, 6, 162, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_6_63" , 6, 58, 162, "RAZ", 1, 1, 0, 0},
+ {"SKIP_SZ" , 0, 6, 163, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 163, "RAZ", 1, 1, 0, 0},
+ {"BACK" , 0, 4, 164, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 164, "RAZ", 1, 1, 0, 0},
+ {"BACK" , 0, 4, 165, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 165, "RAZ", 1, 1, 0, 0},
+ {"PWP" , 0, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"IPD_NEW" , 1, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"IPD_OLD" , 2, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PRC_OFF" , 3, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ0" , 4, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ1" , 5, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PBM_WORD" , 6, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PBM0" , 7, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PBM1" , 8, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PBM2" , 9, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PBM3" , 10, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"IPQ_PBE0" , 11, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"IPQ_PBE1" , 12, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ_POW" , 13, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ_WP1" , 14, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"PWQ_WQED" , 15, 1, 166, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 166, "RAZ", 1, 1, 0, 0},
+ {"PRT_ENB" , 0, 36, 167, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 167, "RAZ", 1, 1, 0, 0},
+ {"CLK_CNT" , 0, 64, 168, "RO", 0, 0, 0ull, 0ull},
+ {"IPD_EN" , 0, 1, 169, "R/W", 0, 0, 0ull, 0ull},
+ {"OPC_MODE" , 1, 2, 169, "R/W", 0, 0, 0ull, 0ull},
+ {"PBP_EN" , 3, 1, 169, "R/W", 0, 0, 0ull, 0ull},
+ {"WQE_LEND" , 4, 1, 169, "R/W", 0, 0, 0ull, 0ull},
+ {"PKT_LEND" , 5, 1, 169, "R/W", 0, 0, 0ull, 0ull},
+ {"NADDBUF" , 6, 1, 169, "R/W", 0, 0, 0ull, 0ull},
+ {"ADDPKT" , 7, 1, 169, "R/W", 0, 0, 0ull, 0ull},
+ {"RESET" , 8, 1, 169, "R/W", 0, 0, 0ull, 0ull},
+ {"LEN_M8" , 9, 1, 169, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_10_63" , 10, 54, 169, "RAZ", 1, 1, 0, 0},
+ {"PRC_PAR0" , 0, 1, 170, "R/W", 0, 0, 0ull, 0ull},
+ {"PRC_PAR1" , 1, 1, 170, "R/W", 0, 0, 0ull, 0ull},
+ {"PRC_PAR2" , 2, 1, 170, "R/W", 0, 0, 0ull, 0ull},
+ {"PRC_PAR3" , 3, 1, 170, "R/W", 0, 0, 0ull, 0ull},
+ {"BP_SUB" , 4, 1, 170, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 170, "RAZ", 1, 1, 0, 0},
+ {"PRC_PAR0" , 0, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PRC_PAR1" , 1, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PRC_PAR2" , 2, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PRC_PAR3" , 3, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BP_SUB" , 4, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 171, "RAZ", 1, 1, 0, 0},
+ {"SKIP_SZ" , 0, 6, 172, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 172, "RAZ", 1, 1, 0, 0},
+ {"MB_SIZE" , 0, 12, 173, "R/W", 0, 0, 32ull, 32ull},
+ {"RESERVED_12_63" , 12, 52, 173, "RAZ", 1, 1, 0, 0},
+ {"PTR" , 0, 29, 174, "RO", 1, 1, 0, 0},
+ {"RESERVED_29_63" , 29, 35, 174, "RAZ", 1, 1, 0, 0},
+ {"PAGE_CNT" , 0, 17, 175, "R/W", 0, 0, 0ull, 0ull},
+ {"BP_ENB" , 17, 1, 175, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 175, "RAZ", 1, 1, 0, 0},
+ {"CNT_VAL" , 0, 25, 176, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_25_63" , 25, 39, 176, "RAZ", 1, 1, 0, 0},
+ {"RADDR" , 0, 3, 177, "R/W", 0, 0, 0ull, 0ull},
+ {"CENA" , 3, 1, 177, "R/W", 0, 0, 1ull, 1ull},
+ {"PTR" , 4, 29, 177, "RO", 1, 1, 0, 0},
+ {"PRADDR" , 33, 3, 177, "RO", 1, 1, 0, 0},
+ {"MAX_PKT" , 36, 3, 177, "RO", 0, 0, 5ull, 5ull},
+ {"RESERVED_39_63" , 39, 25, 177, "RAZ", 1, 1, 0, 0},
+ {"RADDR" , 0, 7, 178, "R/W", 0, 0, 0ull, 0ull},
+ {"CENA" , 7, 1, 178, "R/W", 0, 0, 1ull, 1ull},
+ {"PTR" , 8, 29, 178, "RO", 1, 1, 0, 0},
+ {"MAX_PKT" , 37, 7, 178, "RO", 0, 0, 5ull, 5ull},
+ {"RESERVED_44_63" , 44, 20, 178, "RAZ", 1, 1, 0, 0},
+ {"WQE_PCNT" , 0, 7, 179, "RO", 0, 0, 0ull, 0ull},
+ {"PKT_PCNT" , 7, 7, 179, "RO", 0, 0, 0ull, 0ull},
+ {"PFIF_CNT" , 14, 3, 179, "RO", 0, 0, 0ull, 0ull},
+ {"WQEV_CNT" , 17, 1, 179, "RO", 0, 0, 0ull, 0ull},
+ {"PKTV_CNT" , 18, 1, 179, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 179, "RAZ", 1, 1, 0, 0},
+ {"RADDR" , 0, 8, 180, "R/W", 0, 0, 0ull, 0ull},
+ {"CENA" , 8, 1, 180, "R/W", 0, 0, 1ull, 1ull},
+ {"PTR" , 9, 29, 180, "RO", 1, 1, 0, 0},
+ {"PRADDR" , 38, 8, 180, "RO", 1, 1, 0, 0},
+ {"WRADDR" , 46, 8, 180, "RO", 1, 1, 0, 0},
+ {"MAX_CNTS" , 54, 7, 180, "RO", 0, 0, 8ull, 8ull},
+ {"RESERVED_61_63" , 61, 3, 180, "RAZ", 1, 1, 0, 0},
+ {"PASS" , 0, 32, 181, "R/W", 0, 1, 0ull, 0},
+ {"DROP" , 32, 32, 181, "R/W", 0, 1, 0ull, 0},
+ {"Q0_PCNT" , 0, 32, 182, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 182, "RAZ", 1, 1, 0, 0},
+ {"PRT_ENB" , 0, 36, 183, "R/W", 0, 0, 0ull, 0ull},
+ {"AVG_DLY" , 36, 14, 183, "R/W", 0, 1, 0ull, 0},
+ {"PRB_DLY" , 50, 14, 183, "R/W", 0, 0, 0ull, 0ull},
+ {"PRB_CON" , 0, 32, 184, "R/W", 0, 1, 0ull, 0},
+ {"AVG_CON" , 32, 8, 184, "R/W", 0, 1, 0ull, 0},
+ {"NEW_CON" , 40, 8, 184, "R/W", 0, 1, 0ull, 0},
+ {"USE_PCNT" , 48, 1, 184, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_49_63" , 49, 15, 184, "RAZ", 1, 1, 0, 0},
+ {"PAGE_CNT" , 0, 25, 185, "R/W", 1, 0, 0, 0ull},
+ {"PORT" , 25, 6, 185, "R/W", 1, 0, 0, 0ull},
+ {"RESERVED_31_63" , 31, 33, 185, "RAZ", 1, 1, 0, 0},
+ {"PORT_BIT" , 0, 3, 186, "R/W", 0, 0, 7ull, 7ull},
+ {"RESERVED_3_63" , 3, 61, 186, "RAZ", 1, 1, 0, 0},
+ {"WQE_POOL" , 0, 3, 187, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_3_63" , 3, 61, 187, "RAZ", 1, 1, 0, 0},
+ {"PTR" , 0, 29, 188, "RO", 1, 1, 0, 0},
+ {"RESERVED_29_63" , 29, 35, 188, "RAZ", 1, 1, 0, 0},
+ {"WLB_DAT" , 0, 4, 189, "RO", 0, 0, 0ull, 0ull},
+ {"STIN_MSK" , 4, 1, 189, "RO", 0, 0, 0ull, 0ull},
+ {"DT" , 5, 1, 189, "RO", 0, 0, 0ull, 0ull},
+ {"DTCNT" , 6, 10, 189, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_18" , 16, 3, 189, "RAZ", 0, 0, 0ull, 0ull},
+ {"WLB_MSK" , 19, 4, 189, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_63" , 23, 41, 189, "RAZ", 0, 0, 0ull, 0ull},
+ {"L2T" , 0, 5, 190, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_8" , 5, 4, 190, "RAZ", 0, 0, 0ull, 0ull},
+ {"VAB_VWCF" , 9, 1, 190, "RO", 0, 0, 0ull, 0ull},
+ {"LRF" , 10, 2, 190, "RO", 0, 0, 0ull, 0ull},
+ {"VWDF" , 12, 4, 190, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 190, "RAZ", 0, 0, 0ull, 0ull},
+ {"XRDDAT" , 0, 1, 191, "RO", 0, 0, 0ull, 0ull},
+ {"XRDMSK" , 1, 1, 191, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_2" , 2, 1, 191, "RAZ", 0, 0, 0ull, 0ull},
+ {"IPCBST" , 3, 1, 191, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_7" , 4, 4, 191, "RAZ", 0, 0, 0ull, 0ull},
+ {"RMDF" , 8, 4, 191, "RO", 0, 0, 0ull, 0ull},
+ {"MRB" , 12, 4, 191, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 191, "RAZ", 0, 0, 0ull, 0ull},
+ {"LRF_ARB_MODE" , 0, 1, 192, "R/W", 0, 0, 1ull, 1ull},
+ {"RFB_ARB_MODE" , 1, 1, 192, "R/W", 0, 0, 1ull, 1ull},
+ {"RSP_ARB_MODE" , 2, 1, 192, "R/W", 0, 0, 1ull, 1ull},
+ {"MWF_CRD" , 3, 4, 192, "R/W", 0, 0, 2ull, 2ull},
+ {"IDXALIAS" , 7, 1, 192, "R/W", 0, 0, 0ull, 1ull},
+ {"FPEN" , 8, 1, 192, "R/W", 0, 0, 0ull, 0ull},
+ {"FPEMPTY" , 9, 1, 192, "R/W", 0, 0, 0ull, 0ull},
+ {"FPEXP" , 10, 4, 192, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_14_63" , 14, 50, 192, "RAZ", 1, 1, 0, 0},
+ {"L2T" , 0, 1, 193, "R/W", 0, 0, 0ull, 0ull},
+ {"L2D" , 1, 1, 193, "R/W", 0, 0, 0ull, 0ull},
+ {"FINV" , 2, 1, 193, "R/W", 0, 0, 0ull, 0ull},
+ {"SET" , 3, 2, 193, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_5" , 5, 1, 193, "RAZ", 0, 0, 0ull, 0ull},
+ {"PPNUM" , 6, 1, 193, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_9" , 7, 3, 193, "RAZ", 0, 0, 0ull, 0ull},
+ {"LFB_DMP" , 10, 1, 193, "R/W", 0, 0, 0ull, 0ull},
+ {"LFB_ENUM" , 11, 3, 193, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_14_63" , 14, 50, 193, "RAZ", 0, 0, 0ull, 0ull},
+ {"DT_TAG" , 0, 29, 194, "RO", 0, 0, 0ull, 0ull},
+ {"DT_VLD" , 29, 1, 194, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_30_30" , 30, 1, 194, "RAZ", 0, 0, 0ull, 0ull},
+ {"DTENA" , 31, 1, 194, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 194, "RAZ", 0, 0, 0ull, 0ull},
+ {"LCK_ENA" , 0, 1, 195, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_3" , 1, 3, 195, "RAZ", 0, 0, 0ull, 0ull},
+ {"LCK_BASE" , 4, 27, 195, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_31_63" , 31, 33, 195, "RAZ", 0, 0, 0ull, 0ull},
+ {"LCK_OFFSET" , 0, 10, 196, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_63" , 10, 54, 196, "RAZ", 0, 0, 0ull, 0ull},
+ {"VLD" , 0, 1, 197, "RO", 0, 0, 0ull, 0ull},
+ {"CMD" , 1, 4, 197, "RO", 0, 0, 0ull, 0ull},
+ {"SID" , 5, 9, 197, "RO", 0, 0, 0ull, 0ull},
+ {"VABNUM" , 14, 3, 197, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_17" , 17, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
+ {"SET" , 18, 2, 197, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_20" , 20, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
+ {"IHD" , 21, 1, 197, "RO", 0, 0, 0ull, 0ull},
+ {"ITL" , 22, 1, 197, "RO", 0, 0, 0ull, 0ull},
+ {"INXT" , 23, 3, 197, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_26_26" , 26, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
+ {"VAM" , 27, 1, 197, "RO", 0, 0, 0ull, 0ull},
+ {"STCFL" , 28, 1, 197, "RO", 0, 0, 0ull, 0ull},
+ {"STINV" , 29, 1, 197, "RO", 0, 0, 0ull, 0ull},
+ {"STPND" , 30, 1, 197, "RO", 0, 0, 0ull, 0ull},
+ {"STCPND" , 31, 1, 197, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 197, "RAZ", 0, 0, 0ull, 0ull},
+ {"VLD" , 0, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTPRB" , 1, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"PRBRTY" , 2, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTMFL" , 3, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTVTM" , 4, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTSTRSC" , 5, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTSTRSP" , 6, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTSTDT" , 7, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTRDA" , 8, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTSTM" , 9, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTWRM" , 10, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTWHF" , 11, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTWHP" , 12, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTDQ" , 13, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTDW" , 14, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"WTRSP" , 15, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"BID" , 16, 2, 198, "RO", 0, 0, 0ull, 0ull},
+ {"DSGOING" , 18, 1, 198, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 198, "RAZ", 0, 0, 0ull, 0ull},
+ {"LFB_IDX" , 0, 10, 199, "RO", 0, 0, 0ull, 0ull},
+ {"LFB_TAG" , 10, 17, 199, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_27_63" , 27, 37, 199, "RAZ", 0, 0, 0ull, 0ull},
+ {"LFB_HWM" , 0, 3, 200, "R/W", 0, 0, 7ull, 7ull},
+ {"RESERVED_3_3" , 3, 1, 200, "RAZ", 0, 0, 0ull, 0ull},
+ {"STPARTDIS" , 4, 1, 200, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 200, "RAZ", 0, 0, 0ull, 0ull},
+ {"PFCNT0" , 0, 36, 201, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 201, "RAZ", 0, 0, 0ull, 0ull},
+ {"CNT0SEL" , 0, 6, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT0CLR" , 6, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT0ENA" , 7, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT1SEL" , 8, 6, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT1CLR" , 14, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT1ENA" , 15, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT2SEL" , 16, 6, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT2CLR" , 22, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT2ENA" , 23, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT3SEL" , 24, 6, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT3CLR" , 30, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT3ENA" , 31, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT0RDCLR" , 32, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT1RDCLR" , 33, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT2RDCLR" , 34, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"CNT3RDCLR" , 35, 1, 202, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 202, "RAZ", 0, 0, 0ull, 0ull},
+ {"UMSK0" , 0, 4, 203, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_7" , 4, 4, 203, "RAZ", 0, 0, 0ull, 0ull},
+ {"UMSK1" , 8, 4, 203, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_12_63" , 12, 52, 203, "RAZ", 0, 0, 0ull, 0ull},
+ {"UMSKIOB" , 0, 4, 204, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 204, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q0STAT" , 0, 34, 205, "RO", 0, 0, 0ull, 0ull},
+ {"FTL" , 34, 1, 205, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_35_63" , 35, 29, 205, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q1STAT" , 0, 34, 206, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 206, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q2STAT" , 0, 34, 207, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 207, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q3STAT" , 0, 34, 208, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 208, "RAZ", 0, 0, 0ull, 0ull},
+ {"ECC_ENA" , 0, 1, 209, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_INTENA" , 1, 1, 209, "R/W", 0, 0, 0ull, 1ull},
+ {"DED_INTENA" , 2, 1, 209, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_ERR" , 3, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DED_ERR" , 4, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BMHCLSEL" , 5, 1, 209, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 209, "RAZ", 0, 0, 0ull, 0ull},
+ {"FADR" , 0, 10, 210, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_10" , 10, 1, 210, "RAZ", 0, 0, 0ull, 0ull},
+ {"FSET" , 11, 2, 210, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_13_13" , 13, 1, 210, "RAZ", 0, 0, 0ull, 0ull},
+ {"FOWMSK" , 14, 4, 210, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 210, "RAZ", 0, 0, 0ull, 0ull},
+ {"FSYN_OW0" , 0, 10, 211, "RO", 0, 0, 0ull, 0ull},
+ {"FSYN_OW1" , 10, 10, 211, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 211, "RAZ", 0, 0, 0ull, 0ull},
+ {"FSYN_OW2" , 0, 10, 212, "RO", 0, 0, 0ull, 0ull},
+ {"FSYN_OW3" , 10, 10, 212, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 212, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q0FUS" , 0, 34, 213, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 213, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q1FUS" , 0, 34, 214, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 214, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q2FUS" , 0, 34, 215, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 215, "RAZ", 0, 0, 0ull, 0ull},
+ {"Q3FUS" , 0, 34, 216, "RO", 0, 0, 0ull, 0ull},
+ {"CRIP_128K" , 34, 1, 216, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_35_63" , 35, 29, 216, "RAZ", 0, 0, 0ull, 0ull},
+ {"ECC_ENA" , 0, 1, 217, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_INTENA" , 1, 1, 217, "R/W", 0, 0, 0ull, 1ull},
+ {"DED_INTENA" , 2, 1, 217, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_ERR" , 3, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DED_ERR" , 4, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FSYN" , 5, 6, 217, "RO", 0, 0, 0ull, 0ull},
+ {"FADR" , 11, 9, 217, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_20" , 20, 1, 217, "RAZ", 0, 0, 0ull, 0ull},
+ {"FSET" , 21, 2, 217, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_23" , 23, 1, 217, "RAZ", 0, 0, 0ull, 0ull},
+ {"LCKERR" , 24, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
+ {"LCK_INTENA" , 25, 1, 217, "R/W", 0, 0, 0ull, 1ull},
+ {"LCKERR2" , 26, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
+ {"LCK_INTENA2" , 27, 1, 217, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_28_63" , 28, 36, 217, "RAZ", 0, 0, 0ull, 0ull},
+ {"PCTL_DAT" , 0, 4, 218, "R/W", 0, 1, 0ull, 0},
+ {"PCTL_CMD" , 4, 4, 218, "R/W", 0, 1, 0ull, 0},
+ {"PCTL_CLK" , 8, 4, 218, "R/W", 0, 1, 0ull, 0},
+ {"PCTL_CSR" , 12, 4, 218, "R/W", 0, 1, 15ull, 0},
+ {"NCTL_DAT" , 16, 4, 218, "R/W", 0, 1, 0ull, 0},
+ {"NCTL_CMD" , 20, 4, 218, "R/W", 0, 1, 0ull, 0},
+ {"NCTL_CLK" , 24, 4, 218, "R/W", 0, 1, 0ull, 0},
+ {"NCTL_CSR" , 28, 4, 218, "R/W", 0, 1, 15ull, 0},
+ {"RESERVED_32_63" , 32, 32, 218, "RAZ", 0, 0, 0ull, 0ull},
+ {"DIC" , 0, 2, 219, "R/W", 0, 0, 0ull, 0ull},
+ {"QS_DIC" , 2, 2, 219, "R/W", 0, 0, 2ull, 2ull},
+ {"TSKW" , 4, 2, 219, "R/W", 0, 0, 0ull, 1ull},
+ {"SIL_LAT" , 6, 2, 219, "R/W", 0, 0, 1ull, 1ull},
+ {"BPRCH" , 8, 1, 219, "R/W", 0, 1, 0ull, 0},
+ {"FPRCH2" , 9, 1, 219, "R/W", 0, 0, 0ull, 1ull},
+ {"MODE32B" , 10, 1, 219, "R/W", 0, 0, 0ull, 0ull},
+ {"DRESET" , 11, 1, 219, "R/W", 0, 0, 1ull, 0ull},
+ {"INORDER_MRF" , 12, 1, 219, "R/W", 0, 0, 0ull, 0ull},
+ {"INORDER_MWF" , 13, 1, 219, "RAZ", 0, 0, 0ull, 0ull},
+ {"R2R_SLOT" , 14, 1, 219, "R/W", 0, 0, 0ull, 0ull},
+ {"RDIMM_ENA" , 15, 1, 219, "R/W", 0, 1, 0ull, 0},
+ {"PLL_BYPASS" , 16, 1, 219, "R/W", 0, 0, 1ull, 1ull},
+ {"PLL_DIV2" , 17, 1, 219, "R/W", 0, 0, 0ull, 0ull},
+ {"MAX_WRITE_BATCH" , 18, 4, 219, "R/W", 0, 0, 8ull, 8ull},
+ {"XOR_BANK" , 22, 1, 219, "R/W", 0, 0, 0ull, 1ull},
+ {"SLOW_SCF" , 23, 1, 219, "R/W", 0, 0, 0ull, 0ull},
+ {"DDR__PCTL" , 24, 4, 219, "RO", 1, 1, 0, 0},
+ {"DDR__NCTL" , 28, 4, 219, "RO", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 219, "RAZ", 1, 1, 0, 0},
+ {"DCLKCNT_HI" , 0, 32, 220, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 220, "RAZ", 1, 1, 0, 0},
+ {"DCLKCNT_LO" , 0, 32, 221, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 221, "RAZ", 1, 1, 0, 0},
+ {"DDR2" , 0, 1, 222, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_1_1" , 1, 1, 222, "RAZ", 0, 0, 0ull, 0ull},
+ {"DLL90_BYP" , 2, 1, 222, "R/W", 0, 0, 0ull, 0ull},
+ {"DLL90_VLU" , 3, 5, 222, "R/W", 0, 1, 0ull, 0},
+ {"QDLL_ENA" , 8, 1, 222, "R/W", 0, 0, 0ull, 0ull},
+ {"ODT_ENA" , 9, 1, 222, "R/W", 0, 0, 0ull, 0ull},
+ {"DDR2T" , 10, 1, 222, "R/W", 0, 1, 0ull, 0},
+ {"CRIP_MODE" , 11, 1, 222, "R/W", 0, 0, 0ull, 0ull},
+ {"TFAW" , 12, 5, 222, "R/W", 0, 0, 0ull, 9ull},
+ {"DDR_EOF" , 17, 4, 222, "R/W", 0, 0, 2ull, 2ull},
+ {"SILO_HC" , 21, 1, 222, "R/W", 0, 1, 1ull, 0},
+ {"TWR" , 22, 3, 222, "R/W", 0, 0, 3ull, 1ull},
+ {"BWCNT" , 25, 1, 222, "R/W", 0, 0, 0ull, 0ull},
+ {"POCAS" , 26, 1, 222, "R/W", 0, 0, 0ull, 0ull},
+ {"ADDLAT" , 27, 3, 222, "R/W", 0, 0, 0ull, 0ull},
+ {"BURST8" , 30, 1, 222, "R/W", 0, 0, 0ull, 1ull},
+ {"BANK8" , 31, 1, 222, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 222, "RAZ", 0, 0, 0ull, 0ull},
+ {"MRDSYN0" , 0, 8, 223, "RO", 0, 0, 0ull, 0ull},
+ {"MRDSYN1" , 8, 8, 223, "RO", 0, 0, 0ull, 0ull},
+ {"MRDSYN2" , 16, 8, 223, "RO", 0, 0, 0ull, 0ull},
+ {"MRDSYN3" , 24, 8, 223, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 223, "RAZ", 1, 1, 0, 0},
+ {"FCOL" , 0, 12, 224, "RO", 0, 0, 0ull, 0ull},
+ {"FROW" , 12, 14, 224, "RO", 0, 0, 0ull, 0ull},
+ {"FBANK" , 26, 3, 224, "RO", 0, 0, 0ull, 0ull},
+ {"FBUNK" , 29, 1, 224, "RO", 0, 0, 0ull, 0ull},
+ {"FDIMM" , 30, 2, 224, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 224, "RAZ", 1, 1, 0, 0},
+ {"IFBCNT_HI" , 0, 32, 225, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 225, "RAZ", 1, 1, 0, 0},
+ {"IFBCNT_LO" , 0, 32, 226, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 226, "RAZ", 1, 1, 0, 0},
+ {"INIT_START" , 0, 1, 227, "R/W", 0, 0, 0ull, 0ull},
+ {"ECC_ENA" , 1, 1, 227, "R/W", 0, 0, 0ull, 1ull},
+ {"ROW_LSB" , 2, 3, 227, "R/W", 0, 1, 3ull, 0},
+ {"PBANK_LSB" , 5, 4, 227, "R/W", 0, 1, 5ull, 0},
+ {"REF_INT" , 9, 6, 227, "R/W", 0, 0, 1ull, 2ull},
+ {"TCL" , 15, 4, 227, "R/W", 0, 1, 3ull, 0},
+ {"INTR_SEC_ENA" , 19, 1, 227, "R/W", 0, 0, 0ull, 1ull},
+ {"INTR_DED_ENA" , 20, 1, 227, "R/W", 0, 0, 0ull, 1ull},
+ {"SEC_ERR" , 21, 4, 227, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DED_ERR" , 25, 4, 227, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BUNK_ENA" , 29, 1, 227, "R/W", 0, 1, 0ull, 0},
+ {"SILO_QC" , 30, 1, 227, "R/W", 0, 1, 0ull, 0},
+ {"RESET" , 31, 1, 227, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 227, "RAZ", 1, 1, 0, 0},
+ {"TRAS" , 0, 5, 228, "R/W", 0, 0, 12ull, 12ull},
+ {"TRCD" , 5, 4, 228, "R/W", 0, 0, 4ull, 4ull},
+ {"TWTR" , 9, 4, 228, "R/W", 0, 0, 2ull, 2ull},
+ {"TRP" , 13, 4, 228, "R/W", 0, 0, 5ull, 4ull},
+ {"TRFC" , 17, 5, 228, "R/W", 0, 0, 6ull, 7ull},
+ {"TMRD" , 22, 3, 228, "R/W", 0, 0, 2ull, 2ull},
+ {"CASLAT" , 25, 3, 228, "R/W", 0, 0, 4ull, 4ull},
+ {"TRRD" , 28, 3, 228, "R/W", 0, 0, 2ull, 2ull},
+ {"COMP_BYPASS" , 31, 1, 228, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 228, "RAZ", 1, 1, 0, 0},
+ {"OPSCNT_HI" , 0, 32, 229, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 229, "RAZ", 1, 1, 0, 0},
+ {"OPSCNT_LO" , 0, 32, 230, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 230, "RAZ", 1, 1, 0, 0},
+ {"BWCTL" , 0, 4, 231, "R/W", 0, 0, 0ull, 0ull},
+ {"BWUPD" , 4, 1, 231, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_63" , 5, 59, 231, "RAZ", 1, 1, 0, 0},
+ {"RODT_LO0" , 0, 4, 232, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_LO1" , 4, 4, 232, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_LO2" , 8, 4, 232, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_LO3" , 12, 4, 232, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_HI0" , 16, 4, 232, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_HI1" , 20, 4, 232, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_HI2" , 24, 4, 232, "R/W", 0, 0, 15ull, 15ull},
+ {"RODT_HI3" , 28, 4, 232, "R/W", 0, 0, 15ull, 15ull},
+ {"RESERVED_32_63" , 32, 32, 232, "RAZ", 1, 1, 0, 0},
+ {"WODT_D0_R0" , 0, 8, 233, "R/W", 0, 0, 255ull, 255ull},
+ {"WODT_D0_R1" , 8, 8, 233, "R/W", 0, 0, 255ull, 255ull},
+ {"WODT_D1_R0" , 16, 8, 233, "R/W", 0, 0, 255ull, 255ull},
+ {"WODT_D1_R1" , 24, 8, 233, "R/W", 0, 0, 255ull, 255ull},
+ {"RESERVED_32_63" , 32, 32, 233, "RAZ", 0, 0, 0ull, 0ull},
+ {"WODT_D2_R0" , 0, 8, 234, "R/W", 0, 0, 255ull, 255ull},
+ {"WODT_D2_R1" , 8, 8, 234, "R/W", 0, 0, 255ull, 255ull},
+ {"WODT_D3_R0" , 16, 8, 234, "R/W", 0, 0, 255ull, 255ull},
+ {"WODT_D3_R1" , 24, 8, 234, "R/W", 0, 0, 255ull, 255ull},
+ {"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
+ {"NCBI" , 0, 1, 235, "RO", 0, 0, 0ull, 0ull},
+ {"LOC" , 1, 1, 235, "RO", 0, 0, 0ull, 0ull},
+ {"NCBO_0" , 2, 1, 235, "RO", 0, 0, 0ull, 0ull},
+ {"NCBO_1" , 3, 1, 235, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 235, "RAZ", 1, 1, 0, 0},
+ {"ADR_ERR" , 0, 1, 236, "R/W1C", 0, 0, 0ull, 0ull},
+ {"WAIT_ERR" , 1, 1, 236, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 236, "RAZ", 1, 1, 0, 0},
+ {"ADR_INT" , 0, 1, 237, "R/W", 0, 1, 0ull, 0},
+ {"WAIT_INT" , 1, 1, 237, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_2_63" , 2, 62, 237, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 238, "RAZ", 1, 1, 0, 0},
+ {"ADR" , 3, 5, 238, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 238, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 239, "RAZ", 1, 1, 0, 0},
+ {"BASE" , 3, 25, 239, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_28_30" , 28, 3, 239, "RAZ", 1, 1, 0, 0},
+ {"EN" , 31, 1, 239, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 239, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 64, 240, "R/W", 1, 1, 0, 0},
+ {"BASE" , 0, 16, 241, "R/W", 0, 1, 0ull, 0},
+ {"SIZE" , 16, 12, 241, "R/W", 0, 1, 0ull, 0},
+ {"WIDTH" , 28, 1, 241, "R/W", 0, 1, 0ull, 0},
+ {"ALE" , 29, 1, 241, "R/W", 0, 1, 0ull, 0},
+ {"ORBIT" , 30, 1, 241, "R/W", 0, 1, 0ull, 0},
+ {"EN" , 31, 1, 241, "R/W", 0, 1, 0ull, 0},
+ {"OE_EXT" , 32, 2, 241, "R/W", 0, 1, 0ull, 0},
+ {"WE_EXT" , 34, 2, 241, "R/W", 0, 1, 0ull, 0},
+ {"SAM" , 36, 1, 241, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_37_63" , 37, 27, 241, "RAZ", 1, 1, 0, 0},
+ {"ADR" , 0, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"CE" , 6, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"OE" , 12, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"WE" , 18, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"RD_HLD" , 24, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"WR_HLD" , 30, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"PAUSE" , 36, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"WAIT" , 42, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"PAGE" , 48, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"ALE" , 54, 6, 242, "R/W", 0, 1, 63ull, 0},
+ {"PAGES" , 60, 2, 242, "R/W", 0, 1, 0ull, 0},
+ {"WAITM" , 62, 1, 242, "R/W", 0, 1, 0ull, 0},
+ {"PAGEM" , 63, 1, 242, "R/W", 0, 1, 0ull, 0},
+ {"FIF_THR" , 0, 6, 243, "R/W", 0, 0, 26ull, 26ull},
+ {"RESERVED_6_7" , 6, 2, 243, "RAZ", 1, 1, 0, 0},
+ {"FIF_CNT" , 8, 6, 243, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_14_63" , 14, 50, 243, "RAZ", 1, 1, 0, 0},
+ {"MAN_INFO" , 0, 32, 244, "RO", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 244, "RAZ", 1, 1, 0, 0},
+ {"MAN_INFO" , 0, 32, 245, "RO", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 245, "RAZ", 1, 1, 0, 0},
+ {"PP_DIS" , 0, 2, 246, "RO", 1, 1, 0, 0},
+ {"RESERVED_2_11" , 2, 10, 246, "RAZ", 1, 1, 0, 0},
+ {"PLL_OFF" , 12, 4, 246, "RO", 1, 1, 0, 0},
+ {"CHIP_ID" , 16, 8, 246, "RO", 1, 1, 0, 0},
+ {"BIST_DIS" , 24, 1, 246, "RO", 1, 1, 0, 0},
+ {"RST_SHT" , 25, 1, 246, "RO", 1, 1, 0, 0},
+ {"NOCRYPTO" , 26, 1, 246, "RO", 1, 1, 0, 0},
+ {"NOMUL" , 27, 1, 246, "RO", 1, 1, 0, 0},
+ {"NODFA_CP2" , 28, 1, 246, "RO", 1, 1, 0, 0},
+ {"RESERVED_29_63" , 29, 35, 246, "RAZ", 1, 1, 0, 0},
+ {"ICACHE" , 0, 24, 247, "RO", 1, 1, 0, 0},
+ {"NODFA_DTE" , 24, 1, 247, "RO", 1, 1, 0, 0},
+ {"NOZIP" , 25, 1, 247, "RO", 1, 1, 0, 0},
+ {"EFUS_IGN" , 26, 1, 247, "RO", 1, 1, 0, 0},
+ {"EFUS_LCK" , 27, 1, 247, "RO", 1, 1, 0, 0},
+ {"BAR2_EN" , 28, 1, 247, "RO", 1, 1, 0, 0},
+ {"ZIP_CRIP" , 29, 2, 247, "RO", 1, 1, 0, 0},
+ {"PLL_DIV4" , 31, 1, 247, "RO", 1, 1, 0, 0},
+ {"RESERVED_32_63" , 32, 32, 247, "RAZ", 1, 1, 0, 0},
+ {"PROG" , 0, 1, 248, "R/W", 1, 1, 0, 0},
+ {"RESERVED_1_63" , 1, 63, 248, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 7, 249, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_7" , 7, 1, 249, "RAZ", 1, 1, 0, 0},
+ {"EFUSE" , 8, 1, 249, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_11" , 9, 3, 249, "RAZ", 1, 1, 0, 0},
+ {"PEND" , 12, 1, 249, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_13_15" , 13, 3, 249, "RAZ", 1, 1, 0, 0},
+ {"DAT" , 16, 8, 249, "RO", 1, 1, 0, 0},
+ {"RESERVED_24_63" , 24, 40, 249, "RAZ", 1, 1, 0, 0},
+ {"REPAIR0" , 0, 14, 250, "RO", 0, 0, 0ull, 0ull},
+ {"REPAIR1" , 14, 14, 250, "RO", 0, 0, 0ull, 0ull},
+ {"REPAIR2" , 28, 14, 250, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_42_63" , 42, 22, 250, "RAZ", 1, 1, 0, 0},
+ {"TOO_MANY" , 0, 1, 251, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 251, "RAZ", 1, 1, 0, 0},
+ {"KEY" , 0, 24, 252, "R/W", 0, 0, 0ull, 5071723ull},
+ {"RESERVED_24_63" , 24, 40, 252, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 10, 253, "R/W", 1, 1, 0, 0},
+ {"RESERVED_10_63" , 10, 54, 253, "RAZ", 1, 1, 0, 0},
+ {"BW_CTL" , 0, 5, 254, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 254, "RAZ", 0, 0, 0ull, 0ull},
+ {"SETTING" , 0, 17, 255, "RO", 1, 1, 0, 0},
+ {"RESERVED_17_63" , 17, 47, 255, "RAZ", 0, 0, 0ull, 0ull},
+ {"ST_INT" , 0, 1, 256, "R/W1C", 0, 1, 0ull, 0},
+ {"TS_INT" , 1, 1, 256, "R/W1C", 0, 1, 0ull, 0},
+ {"CORE_INT" , 2, 1, 256, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_3_3" , 3, 1, 256, "RAZ", 1, 1, 0, 0},
+ {"ST_EN" , 4, 1, 256, "R/W", 0, 1, 0ull, 0},
+ {"TS_EN" , 5, 1, 256, "R/W", 0, 1, 0ull, 0},
+ {"CORE_EN" , 6, 1, 256, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_7_7" , 7, 1, 256, "RAZ", 1, 1, 0, 0},
+ {"SDA_OVR" , 8, 1, 256, "R/W", 0, 1, 0ull, 0},
+ {"SCL_OVR" , 9, 1, 256, "R/W", 0, 1, 0ull, 0},
+ {"SDA" , 10, 1, 256, "RO", 1, 1, 0, 0},
+ {"SCL" , 11, 1, 256, "RO", 1, 1, 0, 0},
+ {"RESERVED_12_63" , 12, 52, 256, "RAZ", 1, 1, 0, 0},
+ {"D" , 0, 32, 257, "R/W", 0, 1, 0ull, 0},
+ {"EOP_IA" , 32, 3, 257, "R/W", 0, 1, 0ull, 0},
+ {"IA" , 35, 5, 257, "R/W", 0, 1, 0ull, 0},
+ {"A" , 40, 10, 257, "R/W", 0, 1, 0ull, 0},
+ {"SCR" , 50, 2, 257, "R/W", 0, 1, 0ull, 0},
+ {"SIZE" , 52, 3, 257, "R/W", 0, 1, 0ull, 0},
+ {"SOVR" , 55, 1, 257, "R/W", 0, 1, 0ull, 0},
+ {"R" , 56, 1, 257, "R/W", 0, 1, 0ull, 0},
+ {"OP" , 57, 4, 257, "R/W", 0, 1, 0ull, 0},
+ {"EIA" , 61, 1, 257, "R/W", 0, 1, 0ull, 0},
+ {"SLONLY" , 62, 1, 257, "R/W", 0, 1, 0ull, 0},
+ {"V" , 63, 1, 257, "RC/W", 0, 1, 0ull, 0},
+ {"D" , 0, 32, 258, "R/W", 0, 1, 0ull, 0},
+ {"IA" , 32, 8, 258, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_40_63" , 40, 24, 258, "RAZ", 1, 1, 0, 0},
+ {"D" , 0, 32, 259, "R/W", 1, 1, 0, 0},
+ {"RESERVED_32_61" , 32, 30, 259, "RAZ", 1, 1, 0, 0},
+ {"V" , 62, 2, 259, "RC/W", 0, 1, 0ull, 0},
+ {"DLH" , 0, 8, 260, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 260, "RAZ", 1, 1, 0, 0},
+ {"DLL" , 0, 8, 261, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 261, "RAZ", 1, 1, 0, 0},
+ {"FAR" , 0, 1, 262, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 262, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 1, 263, "WO", 0, 1, 0ull, 0},
+ {"RXFR" , 1, 1, 263, "WO", 0, 1, 0ull, 0},
+ {"TXFR" , 2, 1, 263, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_3_3" , 3, 1, 263, "RAZ", 0, 1, 0ull, 0},
+ {"TXTRIG" , 4, 2, 263, "WO", 0, 1, 0ull, 0},
+ {"RXTRIG" , 6, 2, 263, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 263, "RAZ", 1, 1, 0, 0},
+ {"HTX" , 0, 1, 264, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 264, "RAZ", 1, 1, 0, 0},
+ {"ERBFI" , 0, 1, 265, "R/W", 0, 1, 0ull, 0},
+ {"ETBEI" , 1, 1, 265, "R/W", 0, 1, 0ull, 0},
+ {"ELSI" , 2, 1, 265, "R/W", 0, 1, 0ull, 0},
+ {"EDSSI" , 3, 1, 265, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_4_6" , 4, 3, 265, "RAZ", 0, 1, 0ull, 0},
+ {"PTIME" , 7, 1, 265, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 265, "RAZ", 1, 1, 0, 0},
+ {"IID" , 0, 4, 266, "RO", 0, 1, 1ull, 0},
+ {"RESERVED_4_5" , 4, 2, 266, "RAZ", 0, 1, 0ull, 0},
+ {"FEN" , 6, 2, 266, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 266, "RAZ", 1, 1, 0, 0},
+ {"CLS" , 0, 2, 267, "R/W", 0, 1, 0ull, 0},
+ {"STOP" , 2, 1, 267, "R/W", 0, 1, 0ull, 0},
+ {"PEN" , 3, 1, 267, "R/W", 0, 1, 0ull, 0},
+ {"EPS" , 4, 1, 267, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_5" , 5, 1, 267, "RAZ", 0, 1, 0ull, 0},
+ {"BRK" , 6, 1, 267, "R/W", 0, 1, 0ull, 0},
+ {"DLAB" , 7, 1, 267, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 267, "RAZ", 1, 1, 0, 0},
+ {"DR" , 0, 1, 268, "RO", 0, 1, 0ull, 0},
+ {"OE" , 1, 1, 268, "RC", 0, 1, 0ull, 0},
+ {"PE" , 2, 1, 268, "RC", 0, 1, 0ull, 0},
+ {"FE" , 3, 1, 268, "RC", 0, 1, 0ull, 0},
+ {"BI" , 4, 1, 268, "RC", 0, 1, 0ull, 0},
+ {"THRE" , 5, 1, 268, "RO", 0, 1, 1ull, 0},
+ {"TEMT" , 6, 1, 268, "RO", 0, 1, 1ull, 0},
+ {"FERR" , 7, 1, 268, "RC", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 268, "RAZ", 1, 1, 0, 0},
+ {"DTR" , 0, 1, 269, "R/W", 0, 1, 0ull, 0},
+ {"RTS" , 1, 1, 269, "R/W", 0, 1, 0ull, 0},
+ {"OUT1" , 2, 1, 269, "R/W", 0, 1, 0ull, 0},
+ {"OUT2" , 3, 1, 269, "R/W", 0, 1, 0ull, 0},
+ {"LOOP" , 4, 1, 269, "R/W", 0, 1, 0ull, 0},
+ {"AFCE" , 5, 1, 269, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_6_63" , 6, 58, 269, "RAZ", 0, 1, 0ull, 0},
+ {"DCTS" , 0, 1, 270, "RC", 0, 1, 0ull, 0},
+ {"DDSR" , 1, 1, 270, "RC", 0, 1, 0ull, 0},
+ {"TERI" , 2, 1, 270, "RC", 0, 1, 0ull, 0},
+ {"DDCD" , 3, 1, 270, "RC", 0, 1, 0ull, 0},
+ {"CTS" , 4, 1, 270, "RO", 1, 1, 0, 0},
+ {"DSR" , 5, 1, 270, "RO", 0, 1, 0ull, 0},
+ {"RI" , 6, 1, 270, "RO", 0, 1, 0ull, 0},
+ {"DCD" , 7, 1, 270, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 270, "RAZ", 1, 1, 0, 0},
+ {"RBR" , 0, 8, 271, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 271, "RAZ", 1, 1, 0, 0},
+ {"RFL" , 0, 7, 272, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_7_63" , 7, 57, 272, "RAZ", 1, 1, 0, 0},
+ {"RFWD" , 0, 8, 273, "WO", 0, 1, 0ull, 0},
+ {"RFPE" , 8, 1, 273, "WO", 0, 1, 0ull, 0},
+ {"RFFE" , 9, 1, 273, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_10_63" , 10, 54, 273, "RAZ", 1, 1, 0, 0},
+ {"SBCR" , 0, 1, 274, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 274, "RAZ", 1, 1, 0, 0},
+ {"SCR" , 0, 8, 275, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 275, "RAZ", 1, 1, 0, 0},
+ {"SFE" , 0, 1, 276, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 276, "RAZ", 1, 1, 0, 0},
+ {"USR" , 0, 1, 277, "WO", 0, 1, 0ull, 0},
+ {"SRFR" , 1, 1, 277, "WO", 0, 1, 0ull, 0},
+ {"STFR" , 2, 1, 277, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_3_63" , 3, 61, 277, "RAZ", 1, 1, 0, 0},
+ {"SRT" , 0, 2, 278, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_2_63" , 2, 62, 278, "RAZ", 1, 1, 0, 0},
+ {"SRTS" , 0, 1, 279, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_1_63" , 1, 63, 279, "RAZ", 1, 1, 0, 0},
+ {"STT" , 0, 2, 280, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_2_63" , 2, 62, 280, "RAZ", 1, 1, 0, 0},
+ {"TFL" , 0, 7, 281, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_7_63" , 7, 57, 281, "RAZ", 1, 1, 0, 0},
+ {"TFR" , 0, 8, 282, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 282, "RAZ", 1, 1, 0, 0},
+ {"THR" , 0, 8, 283, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_8_63" , 8, 56, 283, "RAZ", 1, 1, 0, 0},
+ {"BUSY" , 0, 1, 284, "RO", 0, 1, 0ull, 0},
+ {"TFNF" , 1, 1, 284, "RO", 0, 1, 1ull, 0},
+ {"TFE" , 2, 1, 284, "RO", 0, 1, 1ull, 0},
+ {"RFNE" , 3, 1, 284, "RO", 0, 1, 0ull, 0},
+ {"RFF" , 4, 1, 284, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 284, "RAZ", 1, 1, 0, 0},
+ {"ENABLE" , 0, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"IDLELO" , 1, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"CLK_CONT" , 2, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"WIREOR" , 3, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"LSBFIRST" , 4, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"INT_ENA" , 5, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"CSENA" , 6, 1, 285, "R/W", 0, 0, 0ull, 1ull},
+ {"CSHI" , 7, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"IDLECLKS" , 8, 2, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"TRITX" , 10, 1, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_15" , 11, 5, 285, "RAZ", 1, 1, 0, 0},
+ {"CLKDIV" , 16, 13, 285, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_29_63" , 29, 35, 285, "RAZ", 1, 1, 0, 0},
+ {"DATA" , 0, 8, 286, "R/W", 1, 1, 0, 0},
+ {"RESERVED_8_63" , 8, 56, 286, "RAZ", 1, 1, 0, 0},
+ {"BUSY" , 0, 1, 287, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_7" , 1, 7, 287, "RAZ", 1, 1, 0, 0},
+ {"RXNUM" , 8, 5, 287, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_13_63" , 13, 51, 287, "RAZ", 1, 1, 0, 0},
+ {"TOTNUM" , 0, 5, 288, "WO", 1, 0, 0, 2ull},
+ {"RESERVED_5_7" , 5, 3, 288, "RAZ", 1, 1, 0, 0},
+ {"TXNUM" , 8, 5, 288, "WO", 1, 0, 0, 1ull},
+ {"RESERVED_13_15" , 13, 3, 288, "RAZ", 1, 1, 0, 0},
+ {"LEAVECS" , 16, 1, 288, "WO", 1, 0, 0, 0ull},
+ {"RESERVED_17_63" , 17, 47, 288, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 289, "RAZ", 1, 1, 0, 0},
+ {"BADDR" , 3, 61, 289, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_0_2" , 0, 3, 290, "RAZ", 1, 1, 0, 0},
+ {"BADDR" , 3, 61, 290, "R/W", 0, 1, 0ull, 0},
+ {"DPI_BS" , 0, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"PDF_BS" , 1, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"DOB_BS" , 2, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"NUS_BS" , 3, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"POS_BS" , 4, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"POF3_BS" , 5, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"POF2_BS" , 6, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"POF1_BS" , 7, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"POF0_BS" , 8, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"PIG_BS" , 9, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"PGF_BS" , 10, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"RDNL_BS" , 11, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"PCAD_BS" , 12, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"PCAC_BS" , 13, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"RDN_BS" , 14, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"PCN_BS" , 15, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"PCNC_BS" , 16, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"RDP_BS" , 17, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"DIF_BS" , 18, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"CSR_BS" , 19, 1, 291, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_63" , 20, 44, 291, "RAZ", 1, 1, 0, 0},
+ {"BSIZE" , 0, 16, 292, "R/W", 0, 1, 1024ull, 0},
+ {"ISIZE" , 16, 7, 292, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_23_63" , 23, 41, 292, "RAZ", 1, 1, 0, 0},
+ {"TIMER" , 0, 10, 293, "R/W", 0, 0, 0ull, 50ull},
+ {"RESERVED_10_31" , 10, 22, 293, "RAZ", 0, 0, 0ull, 0ull},
+ {"MAX_WORD" , 32, 5, 293, "R/W", 0, 0, 2ull, 0ull},
+ {"RESERVED_37_39" , 37, 3, 293, "RAZ", 0, 0, 0ull, 0ull},
+ {"WAIT_COM" , 40, 1, 293, "R/W", 0, 0, 0ull, 1ull},
+ {"PCI_WDIS" , 41, 1, 293, "R/W", 0, 0, 0ull, 0ull},
+ {"INS0_64B" , 42, 1, 293, "R/W", 0, 1, 0ull, 0},
+ {"INS1_64B" , 43, 1, 293, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_44_45" , 44, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
+ {"INS0_ENB" , 46, 1, 293, "R/W", 0, 0, 0ull, 1ull},
+ {"INS1_ENB" , 47, 1, 293, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_48_49" , 48, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
+ {"OUT0_ENB" , 50, 1, 293, "R/W", 0, 0, 0ull, 1ull},
+ {"OUT1_ENB" , 51, 1, 293, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_52_53" , 52, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
+ {"DIS_PNIW" , 54, 1, 293, "R/W", 0, 0, 0ull, 1ull},
+ {"CHIP_REV" , 55, 8, 293, "RO", 1, 1, 0, 0},
+ {"RESERVED_63_63" , 63, 1, 293, "RAZ", 1, 1, 0, 0},
+ {"DBG_SEL" , 0, 16, 294, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 294, "RAZ", 1, 1, 0, 0},
+ {"CSIZE" , 0, 14, 295, "R/W", 0, 1, 0ull, 0},
+ {"LP_ENB" , 14, 1, 295, "R/W", 0, 0, 0ull, 1ull},
+ {"HP_ENB" , 15, 1, 295, "R/W", 0, 0, 0ull, 1ull},
+ {"O_MODE" , 16, 1, 295, "R/W", 0, 0, 0ull, 1ull},
+ {"O_ES" , 17, 2, 295, "R/W", 0, 1, 0ull, 0},
+ {"O_NS" , 19, 1, 295, "R/W", 0, 1, 0ull, 0},
+ {"O_RO" , 20, 1, 295, "R/W", 0, 1, 0ull, 0},
+ {"O_ADD1" , 21, 1, 295, "R/W", 0, 0, 0ull, 1ull},
+ {"FPA_QUE" , 22, 3, 295, "R/W", 0, 1, 0ull, 0},
+ {"DWB_ICHK" , 25, 9, 295, "R/W", 0, 1, 0ull, 0},
+ {"DWB_DENB" , 34, 1, 295, "R/W", 0, 0, 0ull, 1ull},
+ {"B0_LEND" , 35, 1, 295, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_36_63" , 36, 28, 295, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 32, 296, "RO", 0, 0, 0ull, 0ull},
+ {"FCNT" , 32, 7, 296, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_39_63" , 39, 25, 296, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 36, 297, "RO", 0, 1, 0ull, 0},
+ {"STATE" , 36, 4, 297, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_40_63" , 40, 24, 297, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 32, 298, "RO", 0, 0, 0ull, 0ull},
+ {"FCNT" , 32, 7, 298, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_39_63" , 39, 25, 298, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 36, 299, "RO", 0, 1, 0ull, 0},
+ {"STATE" , 36, 4, 299, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_40_63" , 40, 24, 299, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 16, 300, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 300, "RAZ", 1, 1, 0, 0},
+ {"SADDR" , 0, 36, 301, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 301, "RAZ", 1, 1, 0, 0},
+ {"ROR" , 0, 1, 302, "R/W", 0, 1, 0ull, 0},
+ {"ESR" , 1, 2, 302, "R/W", 0, 1, 0ull, 0},
+ {"NSR" , 3, 1, 302, "R/W", 0, 1, 0ull, 0},
+ {"USE_CSR" , 4, 1, 302, "R/W", 0, 0, 0ull, 1ull},
+ {"D_ROR" , 5, 1, 302, "R/W", 0, 1, 0ull, 0},
+ {"D_ESR" , 6, 2, 302, "R/W", 0, 1, 0ull, 0},
+ {"D_NSR" , 8, 1, 302, "R/W", 0, 1, 0ull, 0},
+ {"PBP_DHI" , 9, 13, 302, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_22_63" , 22, 42, 302, "RAZ", 1, 1, 0, 0},
+ {"RML_RTO" , 0, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RML_WTO" , 1, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PCI_RSL" , 2, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PO0_2SML" , 3, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PO1_2SML" , 4, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_5_6" , 5, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"I0_RTOUT" , 7, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"I1_RTOUT" , 8, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_9_10" , 9, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"I0_OVERF" , 11, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"I1_OVERF" , 12, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_13_14" , 13, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"P0_RTOUT" , 15, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"P1_RTOUT" , 16, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_17_18" , 17, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"P0_PERR" , 19, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"P1_PERR" , 20, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_21_22" , 21, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"G0_RTOUT" , 23, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"G1_RTOUT" , 24, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_25_26" , 25, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"P0_PPERR" , 27, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"P1_PPERR" , 28, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_29_30" , 29, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"P0_PTOUT" , 31, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"P1_PTOUT" , 32, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_33_34" , 33, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"I0_PPERR" , 35, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"I1_PPERR" , 36, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_37_38" , 37, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
+ {"WIN_RTO" , 39, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"P_DPERR" , 40, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"IOBDMA" , 41, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"FCR_S_E" , 42, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"FCR_A_F" , 43, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PCR_S_E" , 44, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PCR_A_F" , 45, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"Q2_S_E" , 46, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"Q2_A_F" , 47, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"Q3_S_E" , 48, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"Q3_A_F" , 49, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"COM_S_E" , 50, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"COM_A_F" , 51, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PNC_S_E" , 52, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PNC_A_F" , 53, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RWX_S_E" , 54, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RDX_S_E" , 55, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PCF_P_E" , 56, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PCF_P_F" , 57, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PDF_P_E" , 58, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"PDF_P_F" , 59, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"Q1_S_E" , 60, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"Q1_A_F" , 61, 1, 303, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_62_63" , 62, 2, 303, "RAZ", 1, 1, 0, 0},
+ {"RML_RTO" , 0, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RML_WTO" , 1, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCI_RSL" , 2, 1, 304, "RO", 0, 0, 0ull, 0ull},
+ {"PO0_2SML" , 3, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PO1_2SML" , 4, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_5_6" , 5, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"I0_RTOUT" , 7, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I1_RTOUT" , 8, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_10" , 9, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"I0_OVERF" , 11, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I1_OVERF" , 12, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_13_14" , 13, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"P0_RTOUT" , 15, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P1_RTOUT" , 16, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_18" , 17, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"P0_PERR" , 19, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P1_PERR" , 20, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_21_22" , 21, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"G0_RTOUT" , 23, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"G1_RTOUT" , 24, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_25_26" , 25, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"P0_PPERR" , 27, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P1_PPERR" , 28, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_29_30" , 29, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"P0_PTOUT" , 31, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P1_PTOUT" , 32, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_33_34" , 33, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"I0_PPERR" , 35, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"I1_PPERR" , 36, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_37_38" , 37, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
+ {"WIN_RTO" , 39, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"P_DPERR" , 40, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"IOBDMA" , 41, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FCR_S_E" , 42, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FCR_A_F" , 43, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCR_S_E" , 44, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCR_A_F" , 45, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q2_S_E" , 46, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q2_A_F" , 47, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q3_S_E" , 48, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q3_A_F" , 49, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"COM_S_E" , 50, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"COM_A_F" , 51, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PNC_S_E" , 52, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PNC_A_F" , 53, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RWX_S_E" , 54, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RDX_S_E" , 55, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCF_P_E" , 56, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCF_P_F" , 57, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PDF_P_E" , 58, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PDF_P_F" , 59, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q1_S_E" , 60, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"Q1_A_F" , 61, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_62_63" , 62, 2, 304, "RAZ", 1, 1, 0, 0},
+ {"DBELL" , 0, 16, 305, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 305, "RAZ", 1, 1, 0, 0},
+ {"SADDR" , 0, 36, 306, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 306, "RAZ", 1, 1, 0, 0},
+ {"BA" , 0, 28, 307, "R/W", 0, 1, 0ull, 0},
+ {"ROW" , 28, 1, 307, "R/W", 0, 1, 0ull, 0},
+ {"ROR" , 29, 1, 307, "R/W", 0, 1, 0ull, 0},
+ {"NSW" , 30, 1, 307, "R/W", 0, 1, 0ull, 0},
+ {"NSR" , 31, 1, 307, "R/W", 0, 1, 0ull, 0},
+ {"ESW" , 32, 2, 307, "R/W", 0, 1, 0ull, 0},
+ {"ESR" , 34, 2, 307, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 307, "RAZ", 1, 1, 0, 0},
+ {"INT_VEC" , 0, 64, 308, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SIZE" , 0, 32, 309, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 309, "RAZ", 1, 1, 0, 0},
+ {"ROR_SL0" , 0, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"NSR_SL0" , 1, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"ESR_SL0" , 2, 2, 310, "R/W", 0, 1, 0ull, 0},
+ {"ROR_SL1" , 4, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"NSR_SL1" , 5, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"ESR_SL1" , 6, 2, 310, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_15" , 8, 8, 310, "RAZ", 0, 0, 0ull, 0ull},
+ {"IPTR_O0" , 16, 1, 310, "R/W", 0, 0, 0ull, 1ull},
+ {"IPTR_O1" , 17, 1, 310, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_18_23" , 18, 6, 310, "RAZ", 0, 0, 0ull, 0ull},
+ {"O0_CSRM" , 24, 1, 310, "R/W", 0, 0, 0ull, 1ull},
+ {"O1_CSRM" , 25, 1, 310, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_26_27" , 26, 2, 310, "RAZ", 0, 0, 0ull, 0ull},
+ {"O0_RO" , 28, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"O0_NS" , 29, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"O0_ES" , 30, 2, 310, "R/W", 0, 1, 0ull, 0},
+ {"O1_RO" , 32, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"O1_NS" , 33, 1, 310, "R/W", 0, 1, 0ull, 0},
+ {"O1_ES" , 34, 2, 310, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_36_43" , 36, 8, 310, "RAZ", 0, 0, 0ull, 0ull},
+ {"P0_BMODE" , 44, 1, 310, "R/W", 0, 0, 0ull, 0ull},
+ {"P1_BMODE" , 45, 1, 310, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_46_63" , 46, 18, 310, "RAZ", 0, 0, 0ull, 0ull},
+ {"NADDR" , 0, 61, 311, "RO", 0, 1, 0ull, 0},
+ {"STATE" , 61, 2, 311, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_63_63" , 63, 1, 311, "RAZ", 1, 1, 0, 0},
+ {"NADDR" , 0, 61, 312, "RO", 0, 1, 0ull, 0},
+ {"STATE" , 61, 3, 312, "RO", 0, 0, 0ull, 0ull},
+ {"AVAIL" , 0, 32, 313, "RO", 0, 0, 0ull, 0ull},
+ {"FCNT" , 32, 6, 313, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_38_63" , 38, 26, 313, "RAZ", 1, 1, 0, 0},
+ {"AVAIL" , 0, 32, 314, "RO", 0, 0, 0ull, 0ull},
+ {"FCNT" , 32, 5, 314, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_37_63" , 37, 27, 314, "RAZ", 1, 1, 0, 0},
+ {"RD_BRST" , 0, 7, 315, "R/W", 0, 0, 17ull, 64ull},
+ {"WR_BRST" , 7, 7, 315, "R/W", 0, 0, 16ull, 64ull},
+ {"RESERVED_14_63" , 14, 50, 315, "RAZ", 1, 1, 0, 0},
+ {"PARK_DEV" , 0, 3, 316, "R/W", 0, 1, 0ull, 0},
+ {"PARK_MOD" , 3, 1, 316, "R/W", 0, 1, 0ull, 0},
+ {"EN" , 4, 1, 316, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_5_63" , 5, 59, 316, "RAZ", 1, 1, 0, 0},
+ {"CMD_SIZE" , 0, 11, 317, "R/W", 0, 0, 9ull, 9ull},
+ {"RESERVED_11_63" , 11, 53, 317, "RAZ", 1, 1, 0, 0},
+ {"RSV_A" , 0, 6, 318, "R/W", 0, 1, 0ull, 0},
+ {"SKP_LEN" , 6, 7, 318, "R/W", 0, 1, 0ull, 0},
+ {"RSV_B" , 13, 1, 318, "R/W", 0, 1, 0ull, 0},
+ {"PAR_MODE" , 14, 2, 318, "R/W", 0, 1, 0ull, 0},
+ {"RSV_C" , 16, 5, 318, "R/W", 0, 1, 0ull, 0},
+ {"USE_IHDR" , 21, 1, 318, "R/W", 0, 1, 0ull, 0},
+ {"RSV_D" , 22, 6, 318, "R/W", 0, 1, 0ull, 0},
+ {"RSKP_LEN" , 28, 7, 318, "R/W", 0, 1, 8ull, 0},
+ {"RSV_E" , 35, 1, 318, "R/W", 0, 1, 0ull, 0},
+ {"RPARMODE" , 36, 2, 318, "R/W", 0, 1, 0ull, 0},
+ {"RSV_F" , 38, 5, 318, "R/W", 0, 1, 0ull, 0},
+ {"PBP" , 43, 1, 318, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_44_63" , 44, 20, 318, "RAZ", 1, 1, 0, 0},
+ {"RSV_A" , 0, 6, 319, "R/W", 0, 1, 0ull, 0},
+ {"SKP_LEN" , 6, 7, 319, "R/W", 0, 1, 0ull, 0},
+ {"RSV_B" , 13, 1, 319, "R/W", 0, 1, 0ull, 0},
+ {"PAR_MODE" , 14, 2, 319, "R/W", 0, 1, 0ull, 0},
+ {"RSV_C" , 16, 5, 319, "R/W", 0, 1, 0ull, 0},
+ {"USE_IHDR" , 21, 1, 319, "R/W", 0, 1, 0ull, 0},
+ {"RSV_D" , 22, 6, 319, "R/W", 0, 1, 0ull, 0},
+ {"RSKP_LEN" , 28, 7, 319, "R/W", 0, 1, 8ull, 0},
+ {"RSV_E" , 35, 1, 319, "R/W", 0, 1, 0ull, 0},
+ {"RPARMODE" , 36, 2, 319, "R/W", 0, 1, 0ull, 0},
+ {"RSV_F" , 38, 5, 319, "R/W", 0, 1, 0ull, 0},
+ {"PBP" , 43, 1, 319, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_44_63" , 44, 20, 319, "RAZ", 1, 1, 0, 0},
+ {"ENB" , 0, 4, 320, "R/W", 0, 0, 15ull, 15ull},
+ {"BP_ON" , 4, 4, 320, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 320, "RAZ", 1, 1, 0, 0},
+ {"MIO" , 0, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"GMX0" , 1, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"GMX1" , 2, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"NPI" , 3, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"KEY" , 4, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"FPA" , 5, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"DFA" , 6, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"ZIP" , 7, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_8" , 8, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"IPD" , 9, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"PKO" , 10, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"TIM" , 11, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"POW" , 12, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"USB" , 13, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_14" , 14, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_15" , 15, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"L2C" , 16, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"LMC" , 17, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"SPX0" , 18, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"SPX1" , 19, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"PIP" , 20, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_21" , 21, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"ASX0" , 22, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"ASX1" , 23, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_24" , 24, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_25" , 25, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_26" , 26, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_27" , 27, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_28" , 28, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_29" , 29, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"IOB" , 30, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RINT_31" , 31, 1, 321, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
+ {"SIZE" , 0, 32, 322, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 322, "RAZ", 1, 1, 0, 0},
+ {"TIME" , 0, 32, 323, "R/W", 0, 0, 0ull, 131072ull},
+ {"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
+ {"ADDR_V" , 0, 1, 324, "R/W", 0, 1, 0ull, 0},
+ {"END_SWP" , 1, 2, 324, "R/W", 0, 1, 0ull, 0},
+ {"CA" , 3, 1, 324, "R/W", 0, 0, 0ull, 0ull},
+ {"ADDR_IDX" , 4, 14, 324, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_18_31" , 18, 14, 324, "RAZ", 1, 1, 0, 0},
+ {"VENDID" , 0, 16, 325, "RO", 0, 0, 6013ull, 6013ull},
+ {"DEVID" , 16, 16, 325, "RO", 0, 0, 32ull, 32ull},
+ {"ISAE" , 0, 1, 326, "RO", 0, 0, 0ull, 0ull},
+ {"MSAE" , 1, 1, 326, "R/W", 0, 0, 0ull, 1ull},
+ {"ME" , 2, 1, 326, "R/W", 0, 0, 0ull, 1ull},
+ {"SCSE" , 3, 1, 326, "RO", 0, 0, 0ull, 0ull},
+ {"MWICE" , 4, 1, 326, "R/W", 0, 0, 0ull, 0ull},
+ {"VPS" , 5, 1, 326, "RO", 0, 0, 0ull, 0ull},
+ {"PEE" , 6, 1, 326, "R/W", 0, 0, 0ull, 1ull},
+ {"ADS" , 7, 1, 326, "RO", 0, 0, 0ull, 0ull},
+ {"SEE" , 8, 1, 326, "R/W", 0, 0, 0ull, 1ull},
+ {"FBBE" , 9, 1, 326, "R/W", 0, 0, 0ull, 1ull},
+ {"I_DIS" , 10, 1, 326, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_18" , 11, 8, 326, "RAZ", 1, 1, 0, 0},
+ {"I_STAT" , 19, 1, 326, "RO", 0, 0, 0ull, 0ull},
+ {"CLE" , 20, 1, 326, "RO", 0, 0, 1ull, 1ull},
+ {"M66" , 21, 1, 326, "RO", 0, 0, 1ull, 1ull},
+ {"RESERVED_22_22" , 22, 1, 326, "RAZ", 1, 1, 0, 0},
+ {"FBB" , 23, 1, 326, "RO", 0, 1, 1ull, 0},
+ {"MDPE" , 24, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DEVT" , 25, 2, 326, "RO", 0, 0, 1ull, 1ull},
+ {"STA" , 27, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RTA" , 28, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RMA" , 29, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SSE" , 30, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DPE" , 31, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RID" , 0, 8, 327, "RO", 0, 0, 0ull, 0ull},
+ {"CC" , 8, 24, 327, "RO", 0, 0, 1048576ull, 1048576ull},
+ {"CLS" , 0, 8, 328, "R/W", 0, 1, 0ull, 0},
+ {"LT" , 8, 8, 328, "R/W", 0, 0, 0ull, 64ull},
+ {"HT" , 16, 8, 328, "RO", 0, 0, 0ull, 0ull},
+ {"BCOD" , 24, 4, 328, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_28_29" , 28, 2, 328, "RAZ", 1, 1, 0, 0},
+ {"BRB" , 30, 1, 328, "R/W", 0, 0, 0ull, 0ull},
+ {"BCAP" , 31, 1, 328, "RO", 0, 0, 0ull, 0ull},
+ {"MSPC" , 0, 1, 329, "RO", 0, 0, 0ull, 0ull},
+ {"TYP" , 1, 2, 329, "RO", 0, 0, 2ull, 2ull},
+ {"PF" , 3, 1, 329, "RO", 0, 0, 1ull, 1ull},
+ {"LBASEZ" , 4, 8, 329, "RO", 0, 0, 0ull, 0ull},
+ {"LBASE" , 12, 20, 329, "R/W", 0, 1, 0ull, 0},
+ {"HBASE" , 0, 32, 330, "R/W", 0, 1, 0ull, 0},
+ {"MSPC" , 0, 1, 331, "RO", 0, 0, 0ull, 0ull},
+ {"TYP" , 1, 2, 331, "RO", 0, 0, 2ull, 2ull},
+ {"PF" , 3, 1, 331, "RO", 0, 0, 1ull, 1ull},
+ {"LBASEZ" , 4, 23, 331, "RO", 0, 0, 0ull, 0ull},
+ {"LBASE" , 27, 5, 331, "R/W", 0, 1, 0ull, 0},
+ {"HBASE" , 0, 32, 332, "R/W", 0, 1, 0ull, 0},
+ {"MSPC" , 0, 1, 333, "RO", 0, 0, 0ull, 0ull},
+ {"TYP" , 1, 2, 333, "RO", 0, 0, 2ull, 2ull},
+ {"PF" , 3, 1, 333, "RO", 0, 0, 1ull, 1ull},
+ {"LBASEZ" , 4, 28, 333, "RO", 0, 0, 0ull, 0ull},
+ {"HBASEZ" , 0, 7, 334, "RO", 0, 0, 0ull, 0ull},
+ {"HBASE" , 7, 25, 334, "R/W", 0, 1, 0ull, 0},
+ {"CISP" , 0, 32, 335, "RO", 0, 0, 0ull, 0ull},
+ {"SSVID" , 0, 16, 336, "RO", 0, 0, 6013ull, 6013ull},
+ {"SSID" , 16, 16, 336, "RO", 0, 0, 1ull, 1ull},
+ {"ERBAR_EN" , 0, 1, 337, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_10" , 1, 10, 337, "RAZ", 1, 1, 0, 0},
+ {"ERBARZ" , 11, 5, 337, "RO", 0, 0, 0ull, 0ull},
+ {"ERBAR" , 16, 16, 337, "R/W", 0, 1, 0ull, 0},
+ {"CP" , 0, 8, 338, "RO", 0, 0, 224ull, 224ull},
+ {"RESERVED_8_31" , 8, 24, 338, "RAZ", 1, 1, 0, 0},
+ {"IL" , 0, 8, 339, "R/W", 0, 1, 0ull, 0},
+ {"INTA" , 8, 8, 339, "RO", 0, 0, 1ull, 1ull},
+ {"MG" , 16, 8, 339, "RO", 0, 0, 64ull, 64ull},
+ {"ML" , 24, 8, 339, "RO", 0, 0, 64ull, 64ull},
+ {"MLTD" , 0, 1, 340, "R/W", 0, 0, 0ull, 1ull},
+ {"TSWC" , 1, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_2" , 2, 1, 340, "RAZ", 1, 1, 0, 0},
+ {"DPPMR" , 3, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"PBE" , 4, 12, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TILT" , 16, 4, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TSLTE" , 20, 3, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TMAE" , 23, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TWTAE" , 24, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TWSEN" , 25, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TWSEI" , 26, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TRTAE" , 27, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TRDRS" , 28, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"RDSATI" , 29, 1, 340, "R/W", 0, 0, 0ull, 0ull},
+ {"TRDARD" , 30, 1, 340, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TRDNPR" , 31, 1, 340, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TSCME" , 0, 32, 341, "R/W1C", 0, 1, 0ull, 0},
+ {"TDSRPS" , 0, 32, 342, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TDOMC" , 0, 5, 343, "R/W", 0, 0, 1ull, 1ull},
+ {"TIDOMC" , 5, 1, 343, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_6" , 6, 1, 343, "RAZ", 1, 1, 0, 0},
+ {"TIBDE" , 7, 1, 343, "R/W", 0, 0, 0ull, 0ull},
+ {"TIBCD" , 8, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_10" , 9, 2, 343, "RAZ", 1, 1, 0, 0},
+ {"TMAPES" , 11, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TMDPES" , 12, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TMSE" , 13, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TMEI" , 14, 1, 343, "RO", 0, 0, 0ull, 0ull},
+ {"TECI" , 15, 1, 343, "RO", 0, 0, 0ull, 0ull},
+ {"TMES" , 16, 8, 343, "RO", 0, 0, 0ull, 0ull},
+ {"MDRRMC" , 24, 3, 343, "R/W", 0, 0, 2ull, 2ull},
+ {"MDRIMC" , 27, 1, 343, "R/W", 0, 0, 0ull, 0ull},
+ {"MDRE" , 28, 1, 343, "R/W", 0, 0, 0ull, 0ull},
+ {"MDWE" , 29, 1, 343, "R/W", 0, 0, 0ull, 0ull},
+ {"MRBCI" , 30, 1, 343, "R/W", 0, 0, 0ull, 0ull},
+ {"MRBCM" , 31, 1, 343, "R/W", 0, 0, 1ull, 1ull},
+ {"MDSP" , 0, 32, 344, "R/W1C", 0, 1, 0ull, 0},
+ {"SCMRE" , 0, 32, 345, "R/W1C", 0, 1, 0ull, 0},
+ {"MTTV" , 0, 8, 346, "R/W", 0, 0, 0ull, 0ull},
+ {"MRV" , 8, 8, 346, "R/W", 0, 0, 0ull, 255ull},
+ {"MTTA" , 16, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MRA" , 17, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FLUSH" , 18, 1, 346, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_19_24" , 19, 6, 346, "RAZ", 1, 1, 0, 0},
+ {"MAC" , 25, 7, 346, "R/W", 0, 0, 0ull, 0ull},
+ {"PXCID" , 0, 8, 347, "RO", 0, 0, 7ull, 7ull},
+ {"NCP" , 8, 8, 347, "RO", 0, 0, 232ull, 232ull},
+ {"DPERE" , 16, 1, 347, "R/W", 0, 0, 0ull, 0ull},
+ {"ROE" , 17, 1, 347, "R/W", 0, 0, 1ull, 1ull},
+ {"MMBC" , 18, 2, 347, "R/W", 0, 0, 0ull, 0ull},
+ {"MOST" , 20, 3, 347, "R/W", 0, 0, 3ull, 3ull},
+ {"RESERVED_23_31" , 23, 9, 347, "RAZ", 1, 1, 0, 0},
+ {"FN" , 0, 3, 348, "RO", 0, 0, 0ull, 0ull},
+ {"DN" , 3, 5, 348, "RO", 0, 0, 31ull, 31ull},
+ {"BN" , 8, 8, 348, "RO", 0, 1, 17ull, 0},
+ {"W64" , 16, 1, 348, "RO", 0, 0, 1ull, 1ull},
+ {"M133" , 17, 1, 348, "RO", 0, 0, 1ull, 1ull},
+ {"SCD" , 18, 1, 348, "R/W1C", 0, 1, 0ull, 0},
+ {"USC" , 19, 1, 348, "R/W1C", 0, 1, 0ull, 0},
+ {"DC" , 20, 1, 348, "RO", 0, 0, 0ull, 0ull},
+ {"MMRBCD" , 21, 2, 348, "RO", 0, 0, 2ull, 2ull},
+ {"MOSTD" , 23, 3, 348, "RO", 0, 0, 3ull, 3ull},
+ {"MCRSD" , 26, 3, 348, "RO", 0, 0, 7ull, 7ull},
+ {"SCEMR" , 29, 1, 348, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_30_31" , 30, 2, 348, "RAZ", 1, 1, 0, 0},
+ {"PMCID" , 0, 8, 349, "RO", 0, 0, 1ull, 1ull},
+ {"NCP" , 8, 8, 349, "RO", 0, 0, 240ull, 240ull},
+ {"PCIMIV" , 16, 3, 349, "RO", 0, 0, 2ull, 2ull},
+ {"PMEC" , 19, 1, 349, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_20_20" , 20, 1, 349, "RAZ", 1, 1, 0, 0},
+ {"DSI" , 21, 1, 349, "RO", 0, 0, 0ull, 0ull},
+ {"AUXC" , 22, 3, 349, "RO", 0, 0, 0ull, 0ull},
+ {"D1S" , 25, 1, 349, "RO", 0, 0, 0ull, 0ull},
+ {"D2S" , 26, 1, 349, "RO", 0, 0, 0ull, 0ull},
+ {"PMES" , 27, 5, 349, "RO", 0, 0, 0ull, 0ull},
+ {"PS" , 0, 2, 350, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_7" , 2, 6, 350, "RAZ", 1, 1, 0, 0},
+ {"PMEENS" , 8, 1, 350, "R/W", 0, 0, 0ull, 0ull},
+ {"PMDS" , 9, 4, 350, "R/W", 0, 0, 0ull, 0ull},
+ {"PMEDSIA" , 13, 2, 350, "RO", 0, 0, 0ull, 0ull},
+ {"PMESS" , 15, 1, 350, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_21" , 16, 6, 350, "RAZ", 1, 1, 0, 0},
+ {"BD3H" , 22, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"BPCCEN" , 23, 1, 350, "RO", 0, 0, 0ull, 0ull},
+ {"PMDIA" , 24, 8, 350, "RO", 0, 0, 0ull, 0ull},
+ {"MSICID" , 0, 8, 351, "RO", 0, 0, 5ull, 5ull},
+ {"NCP" , 8, 8, 351, "RO", 0, 0, 0ull, 0ull},
+ {"MSIEN" , 16, 1, 351, "R/W", 0, 0, 0ull, 0ull},
+ {"MMC" , 17, 3, 351, "RO", 0, 0, 0ull, 0ull},
+ {"MME" , 20, 3, 351, "R/W", 0, 0, 0ull, 0ull},
+ {"M64" , 23, 1, 351, "RO", 0, 0, 1ull, 1ull},
+ {"RESERVED_24_31" , 24, 8, 351, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_1" , 0, 2, 352, "RAZ", 1, 1, 0, 0},
+ {"MSI31T2" , 2, 30, 352, "R/W", 0, 1, 0ull, 0},
+ {"MSI" , 0, 32, 353, "R/W", 0, 1, 0ull, 0},
+ {"MSIMD" , 0, 16, 354, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_31" , 16, 16, 354, "RAZ", 1, 1, 0, 0},
+ {"BAR2_CAX" , 0, 1, 355, "R/W", 0, 0, 0ull, 0ull},
+ {"BAR2_ESX" , 1, 2, 355, "R/W", 0, 1, 0ull, 0},
+ {"BAR2_ENB" , 3, 1, 355, "R/W", 0, 0, 0ull, 1ull},
+ {"TSR_HWM" , 4, 3, 355, "R/W", 0, 1, 1ull, 0},
+ {"PMO_FPC" , 7, 3, 355, "R/W", 0, 0, 0ull, 0ull},
+ {"PMO_AMOD" , 10, 1, 355, "R/W", 0, 0, 0ull, 0ull},
+ {"B12_BIST" , 11, 1, 355, "RO", 0, 0, 0ull, 0ull},
+ {"AP_64AD" , 12, 1, 355, "RO", 0, 1, 0ull, 0},
+ {"AP_PCIX" , 13, 1, 355, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_14_14" , 14, 1, 355, "RAZ", 0, 0, 0ull, 0ull},
+ {"EN_WFILT" , 15, 1, 355, "R/W", 0, 0, 0ull, 1ull},
+ {"SCM" , 16, 1, 355, "RO", 0, 1, 0ull, 0},
+ {"SCMTYP" , 17, 1, 355, "RO", 0, 1, 0ull, 0},
+ {"BAR2PRES" , 18, 1, 355, "R/W", 1, 1, 0, 0},
+ {"ERST_N" , 19, 1, 355, "RO", 0, 0, 1ull, 1ull},
+ {"RESERVED_20_31" , 20, 12, 355, "RAZ", 1, 1, 0, 0},
+ {"INC_VAL" , 0, 16, 356, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_31" , 16, 16, 356, "RAZ", 1, 1, 0, 0},
+ {"DMA_CNT" , 0, 32, 357, "R/W", 0, 0, 0ull, 0ull},
+ {"PKT_CNT" , 0, 32, 358, "R/W", 0, 1, 0ull, 0},
+ {"DMA_TIME" , 0, 32, 359, "R/W", 0, 1, 0ull, 0},
+ {"ICNT" , 0, 32, 360, "RO", 0, 0, 0ull, 0ull},
+ {"ITR_WABT" , 0, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IMR_WABT" , 1, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IMR_WTTO" , 2, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"ITR_ABT" , 3, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IMR_ABT" , 4, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IMR_TTO" , 5, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IMSI_PER" , 6, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IMSI_TABT" , 7, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IMSI_MABT" , 8, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IMSC_MSG" , 9, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"ITSR_ABT" , 10, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"ISERR" , 11, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IAPERR" , 12, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IDPERR" , 13, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RWR" , 14, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RRD" , 15, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IRSL_INT" , 16, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IPCNT0" , 17, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IPCNT1" , 18, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_19_20" , 19, 2, 361, "RAZ", 0, 1, 0ull, 0},
+ {"IPTIME0" , 21, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IPTIME1" , 22, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_23_24" , 23, 2, 361, "RAZ", 0, 1, 0ull, 0},
+ {"IDCNT0" , 25, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IDCNT1" , 26, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IDTIME0" , 27, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"IDTIME1" , 28, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"DMA0_FI" , 29, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"DMA1_FI" , 30, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"WIN_WR" , 31, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"ILL_WR" , 32, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RD" , 33, 1, 361, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_34_63" , 34, 30, 361, "RAZ", 1, 1, 0, 0},
+ {"RTR_WABT" , 0, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RMR_WABT" , 1, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RMR_WTTO" , 2, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RTR_ABT" , 3, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RMR_ABT" , 4, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RMR_TTO" , 5, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RMSI_PER" , 6, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RMSI_TABT" , 7, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RMSI_MABT" , 8, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RMSC_MSG" , 9, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RTSR_ABT" , 10, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RSERR" , 11, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RAPERR" , 12, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RDPERR" , 13, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RWR" , 14, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RRD" , 15, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RRSL_INT" , 16, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RPCNT0" , 17, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RPCNT1" , 18, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_19_20" , 19, 2, 362, "RAZ", 0, 1, 0ull, 0},
+ {"RPTIME0" , 21, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RPTIME1" , 22, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_23_24" , 23, 2, 362, "RAZ", 0, 1, 0ull, 0},
+ {"RDCNT0" , 25, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RDCNT1" , 26, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RDTIME0" , 27, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RDTIME1" , 28, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"DMA0_FI" , 29, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"DMA1_FI" , 30, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"WIN_WR" , 31, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"ILL_WR" , 32, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"ILL_RD" , 33, 1, 362, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_34_63" , 34, 30, 362, "RAZ", 1, 1, 0, 0},
+ {"TR_WABT" , 0, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_WABT" , 1, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_WTTO" , 2, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TR_ABT" , 3, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_ABT" , 4, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_TTO" , 5, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_PER" , 6, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_TABT" , 7, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_MABT" , 8, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSC_MSG" , 9, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TSR_ABT" , 10, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SERR" , 11, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"APERR" , 12, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DPERR" , 13, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RWR" , 14, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RRD" , 15, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RSL_INT" , 16, 1, 363, "RO", 0, 0, 0ull, 0ull},
+ {"PCNT0" , 17, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCNT1" , 18, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_20" , 19, 2, 363, "RAZ", 0, 0, 0ull, 0ull},
+ {"PTIME0" , 21, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME1" , 22, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_24" , 23, 2, 363, "RAZ", 0, 0, 0ull, 0ull},
+ {"DCNT0" , 25, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DCNT1" , 26, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTIME0" , 27, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTIME1" , 28, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DMA0_FI" , 29, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DMA1_FI" , 30, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"WIN_WR" , 31, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_WR" , 32, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RD" , 33, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 363, "RAZ", 1, 1, 0, 0},
+ {"TR_WABT" , 0, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_WABT" , 1, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_WTTO" , 2, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TR_ABT" , 3, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_ABT" , 4, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MR_TTO" , 5, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_PER" , 6, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_TABT" , 7, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSI_MABT" , 8, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"MSC_MSG" , 9, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TSR_ABT" , 10, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SERR" , 11, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"APERR" , 12, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DPERR" , 13, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RWR" , 14, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RRD" , 15, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RSL_INT" , 16, 1, 364, "RO", 0, 0, 0ull, 0ull},
+ {"PCNT0" , 17, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PCNT1" , 18, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_20" , 19, 2, 364, "RAZ", 0, 0, 0ull, 0ull},
+ {"PTIME0" , 21, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PTIME1" , 22, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_24" , 23, 2, 364, "RAZ", 0, 0, 0ull, 0ull},
+ {"DCNT0" , 25, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DCNT1" , 26, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTIME0" , 27, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DTIME1" , 28, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DMA0_FI" , 29, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DMA1_FI" , 30, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"WIN_WR" , 31, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_WR" , 32, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"ILL_RD" , 33, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_34_63" , 34, 30, 364, "RAZ", 1, 1, 0, 0},
+ {"INTR" , 0, 6, 365, "WO", 0, 1, 0ull, 0},
+ {"RESERVED_6_31" , 6, 26, 365, "R/W", 1, 1, 0, 0},
+ {"PTR_CNT" , 0, 16, 366, "R/W", 0, 1, 0ull, 0},
+ {"PKT_CNT" , 16, 16, 366, "R/W", 0, 1, 0ull, 0},
+ {"PKT_CNT" , 0, 32, 367, "RO", 0, 0, 0ull, 0ull},
+ {"PKT_CNT" , 0, 32, 368, "R/W", 0, 1, 0ull, 0},
+ {"PKT_TIME" , 0, 32, 369, "R/W", 0, 1, 0ull, 0},
+ {"PREFETCH" , 0, 3, 370, "R/W", 0, 0, 0ull, 2ull},
+ {"MIN_DATA" , 3, 6, 370, "R/W", 0, 0, 0ull, 4ull},
+ {"RESERVED_9_31" , 9, 23, 370, "RAZ", 1, 1, 0, 0},
+ {"PREFETCH" , 0, 3, 371, "R/W", 0, 0, 0ull, 3ull},
+ {"MIN_DATA" , 3, 6, 371, "R/W", 0, 0, 0ull, 6ull},
+ {"RESERVED_9_31" , 9, 23, 371, "RAZ", 1, 1, 0, 0},
+ {"PREFETCH" , 0, 3, 372, "R/W", 0, 0, 0ull, 3ull},
+ {"MIN_DATA" , 3, 6, 372, "R/W", 0, 0, 0ull, 6ull},
+ {"RESERVED_9_31" , 9, 23, 372, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 31, 373, "R/W", 0, 0, 10000ull, 10000ull},
+ {"ENB" , 31, 1, 373, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_32_63" , 32, 32, 373, "RAZ", 1, 1, 0, 0},
+ {"SCM" , 0, 32, 374, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 374, "RAZ", 1, 1, 0, 0},
+ {"TSR" , 0, 36, 375, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_36_63" , 36, 28, 375, "RAZ", 1, 1, 0, 0},
+ {"RESERVED_0_1" , 0, 2, 376, "RAZ", 1, 1, 0, 0},
+ {"RD_ADDR" , 2, 46, 376, "R/W", 0, 1, 0ull, 0},
+ {"IOBIT" , 48, 1, 376, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_49_63" , 49, 15, 376, "RAZ", 1, 1, 0, 0},
+ {"RD_DATA" , 0, 64, 377, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_0_2" , 0, 3, 378, "RAZ", 1, 1, 0, 0},
+ {"WR_ADDR" , 3, 45, 378, "R/W", 0, 1, 0ull, 0},
+ {"IOBIT" , 48, 1, 378, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_49_63" , 49, 15, 378, "RAZ", 1, 1, 0, 0},
+ {"WR_DATA" , 0, 64, 379, "R/W", 0, 1, 0ull, 0},
+ {"WR_MASK" , 0, 8, 380, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 380, "RAZ", 1, 1, 0, 0},
+ {"THRESH" , 0, 4, 381, "R/W", 0, 0, 0ull, 8ull},
+ {"FETCHSIZ" , 4, 4, 381, "R/W", 0, 0, 0ull, 7ull},
+ {"TXRD" , 8, 10, 381, "R/W", 0, 0, 0ull, 1ull},
+ {"USELDT" , 18, 1, 381, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_19" , 19, 1, 381, "RAZ", 1, 1, 0, 0},
+ {"RXST" , 20, 10, 381, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_30_31" , 30, 2, 381, "RAZ", 1, 1, 0, 0},
+ {"TXSLOTS" , 32, 10, 381, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_42_43" , 42, 2, 381, "RAZ", 1, 1, 0, 0},
+ {"RXSLOTS" , 44, 10, 381, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_54_62" , 54, 9, 381, "RAZ", 1, 1, 0, 0},
+ {"RDPEND" , 63, 1, 381, "RO", 0, 0, 0ull, 0ull},
+ {"FSYNCMISSED" , 0, 1, 382, "R/W", 0, 0, 0ull, 1ull},
+ {"FSYNCEXTRA" , 1, 1, 382, "R/W", 0, 0, 0ull, 1ull},
+ {"RXWRAP" , 2, 1, 382, "R/W", 0, 0, 0ull, 1ull},
+ {"RXST" , 3, 1, 382, "R/W", 0, 0, 0ull, 1ull},
+ {"TXWRAP" , 4, 1, 382, "R/W", 0, 0, 0ull, 1ull},
+ {"TXRD" , 5, 1, 382, "R/W", 0, 0, 0ull, 1ull},
+ {"TXEMPTY" , 6, 1, 382, "R/W", 0, 0, 0ull, 1ull},
+ {"RXOVF" , 7, 1, 382, "R/W", 0, 0, 0ull, 1ull},
+ {"RESERVED_8_63" , 8, 56, 382, "RAZ", 1, 1, 0, 0},
+ {"FSYNCMISSED" , 0, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FSYNCEXTRA" , 1, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RXWRAP" , 2, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RXST" , 3, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TXWRAP" , 4, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TXRD" , 5, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TXEMPTY" , 6, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RXOVF" , 7, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 383, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 0, 36, 384, "R/W", 1, 1, 0, 0},
+ {"RESERVED_36_63" , 36, 28, 384, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 16, 385, "R/W", 1, 1, 0, 0},
+ {"RESERVED_16_63" , 16, 48, 385, "RAZ", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 386, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 387, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 388, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 389, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 390, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 391, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 392, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 393, "R/W", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 394, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 3, 33, 394, "R/W", 1, 1, 0, 0},
+ {"RESERVED_36_63" , 36, 28, 394, "RAZ", 1, 1, 0, 0},
+ {"ENABLE" , 0, 1, 395, "R/W", 0, 0, 0ull, 0ull},
+ {"USECLK1" , 1, 1, 395, "R/W", 0, 0, 0ull, 0ull},
+ {"LSBFIRST" , 2, 1, 395, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_31" , 3, 29, 395, "RAZ", 1, 1, 0, 0},
+ {"SAMPPT" , 32, 16, 395, "R/W", 0, 1, 0ull, 0},
+ {"DRVTIM" , 48, 16, 395, "R/W", 0, 1, 0ull, 0},
+ {"DEBUGINFO" , 0, 64, 396, "RO", 1, 1, 0, 0},
+ {"FRAM" , 0, 3, 397, "R/W", 1, 1, 0, 0},
+ {"ADDR" , 3, 33, 397, "R/W", 1, 1, 0, 0},
+ {"RESERVED_36_63" , 36, 28, 397, "RAZ", 1, 1, 0, 0},
+ {"CNT" , 0, 16, 398, "R/W", 1, 1, 0, 0},
+ {"RESERVED_16_63" , 16, 48, 398, "RAZ", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 399, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 400, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 401, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 402, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 403, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 404, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 405, "R/W", 1, 1, 0, 0},
+ {"MASK" , 0, 64, 406, "R/W", 1, 1, 0, 0},
+ {"RESERVED_0_2" , 0, 3, 407, "RAZ", 1, 1, 0, 0},
+ {"ADDR" , 3, 33, 407, "R/W", 1, 1, 0, 0},
+ {"RESERVED_36_63" , 36, 28, 407, "RAZ", 1, 1, 0, 0},
+ {"ENA" , 0, 1, 408, "R/W", 0, 0, 0ull, 0ull},
+ {"FSYNCPOL" , 1, 1, 408, "R/W", 0, 0, 0ull, 0ull},
+ {"BCLKPOL" , 2, 1, 408, "R/W", 0, 0, 0ull, 0ull},
+ {"BITLEN" , 3, 2, 408, "R/W", 0, 0, 0ull, 0ull},
+ {"EXTRABIT" , 5, 1, 408, "R/W", 0, 0, 0ull, 0ull},
+ {"NUMSLOTS" , 6, 10, 408, "R/W", 0, 1, 0ull, 0},
+ {"FSYNCLOC" , 16, 5, 408, "R/W", 0, 0, 0ull, 0ull},
+ {"FSYNCLEN" , 21, 5, 408, "R/W", 0, 0, 0ull, 2ull},
+ {"RESERVED_26_31" , 26, 6, 408, "RAZ", 1, 1, 0, 0},
+ {"FSYNCSAMP" , 32, 16, 408, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_62" , 48, 15, 408, "RAZ", 1, 1, 0, 0},
+ {"FSYNCGOOD" , 63, 1, 408, "RO", 0, 0, 0ull, 1ull},
+ {"DEBUGINFO" , 0, 64, 409, "RO", 1, 1, 0, 0},
+ {"N" , 0, 32, 410, "R/W", 0, 1, 0ull, 0},
+ {"NUMSAMP" , 32, 16, 410, "R/W", 0, 1, 0ull, 0},
+ {"DELTASAMP" , 48, 16, 410, "R/W", 0, 0, 0ull, 0ull},
+ {"BIST" , 0, 18, 411, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 411, "RAZ", 1, 1, 0, 0},
+ {"DPRT" , 0, 16, 412, "R/W", 0, 0, 0ull, 0ull},
+ {"UDP" , 16, 1, 412, "R/W", 0, 0, 0ull, 0ull},
+ {"TCP" , 17, 1, 412, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 412, "RAZ", 1, 1, 0, 0},
+ {"NIP_SHF" , 0, 3, 413, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_7" , 3, 5, 413, "RAZ", 1, 1, 0, 0},
+ {"RAW_SHF" , 8, 3, 413, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_11_15" , 11, 5, 413, "RAZ", 1, 1, 0, 0},
+ {"MAX_L2" , 16, 1, 413, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_UDP" , 17, 1, 413, "R/W", 0, 0, 1ull, 1ull},
+ {"TAG_SYN" , 18, 1, 413, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_19_63" , 19, 45, 413, "RAZ", 1, 1, 0, 0},
+ {"IP_CHK" , 0, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"IP_MAL" , 1, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"IP_HOP" , 2, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"IP4_OPTS" , 3, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"IP6_EEXT" , 4, 2, 414, "R/W", 0, 0, 1ull, 3ull},
+ {"RESERVED_6_7" , 6, 2, 414, "RAZ", 0, 1, 0ull, 0},
+ {"L4_MAL" , 8, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"L4_PRT" , 9, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"L4_CHK" , 10, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"L4_LEN" , 11, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"TCP_FLAG" , 12, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"L2_MAL" , 13, 1, 414, "R/W", 0, 0, 1ull, 1ull},
+ {"VS_QOS" , 14, 1, 414, "R/W", 0, 0, 0ull, 0ull},
+ {"VS_WQE" , 15, 1, 414, "R/W", 0, 0, 0ull, 0ull},
+ {"IGNRS" , 16, 1, 414, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_63" , 17, 47, 414, "RAZ", 0, 0, 0ull, 0ull},
+ {"PKTDRP" , 0, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"CRCERR" , 1, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"BCKPRS" , 2, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"PRTNXA" , 3, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"BADTAG" , 4, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"SKPRUNT" , 5, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"TODOOVR" , 6, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"FEPERR" , 7, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"BEPERR" , 8, 1, 415, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 415, "RAZ", 1, 1, 0, 0},
+ {"PKTDRP" , 0, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"CRCERR" , 1, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BCKPRS" , 2, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"PRTNXA" , 3, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BADTAG" , 4, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SKPRUNT" , 5, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"TODOOVR" , 6, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"FEPERR" , 7, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"BEPERR" , 8, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_63" , 9, 55, 416, "RAZ", 1, 1, 0, 0},
+ {"OFFSET" , 0, 3, 417, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 417, "RAZ", 1, 1, 0, 0},
+ {"SKIP" , 0, 7, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_7_7" , 7, 1, 418, "RAZ", 1, 1, 0, 0},
+ {"MODE" , 8, 2, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_10_15" , 10, 6, 418, "RAZ", 1, 1, 0, 0},
+ {"QOS_VLAN" , 16, 1, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"QOS_DIFF" , 17, 1, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_19" , 18, 2, 418, "RAZ", 0, 0, 0ull, 0ull},
+ {"QOS_WAT" , 20, 4, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"QOS" , 24, 3, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_27_27" , 27, 1, 418, "RAZ", 1, 1, 0, 0},
+ {"GRP_WAT" , 28, 4, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"INST_HDR" , 32, 1, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"DYN_RS" , 33, 1, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"TAG_INC" , 34, 2, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"RAWDRP" , 36, 1, 418, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_37_63" , 37, 27, 418, "RAZ", 1, 1, 0, 0},
+ {"GRP" , 0, 4, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"NON_TAG_TYPE" , 4, 2, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_TAG_TYPE" , 6, 2, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_TAG_TYPE" , 8, 2, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"TCP4_TAG_TYPE" , 10, 2, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"TCP6_TAG_TYPE" , 12, 2, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_SRC_FLAG" , 14, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_SRC_FLAG" , 15, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_DST_FLAG" , 16, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_DST_FLAG" , 17, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_PCTL_FLAG" , 18, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_NXTH_FLAG" , 19, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_SPRT_FLAG" , 20, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_SPRT_FLAG" , 21, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP4_DPRT_FLAG" , 22, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"IP6_DPRT_FLAG" , 23, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"INC_PRT_FLAG" , 24, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"INC_VLAN" , 25, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"INC_VS" , 26, 2, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"TAG_MODE" , 28, 2, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_30_30" , 30, 1, 419, "RAZ", 0, 0, 0ull, 0ull},
+ {"GRPTAG" , 31, 1, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"GRPTAGMASK" , 32, 4, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"GRPTAGBASE" , 36, 4, 419, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_40_63" , 40, 24, 419, "RAZ", 1, 1, 0, 0},
+ {"QOS" , 0, 3, 420, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 420, "RAZ", 1, 1, 0, 0},
+ {"QOS" , 0, 3, 421, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_3_63" , 3, 61, 421, "RAZ", 1, 1, 0, 0},
+ {"MATCH_VALUE" , 0, 16, 422, "R/W", 0, 0, 0ull, 0ull},
+ {"MATCH_TYPE" , 16, 2, 422, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_19" , 18, 2, 422, "RAZ", 1, 1, 0, 0},
+ {"QOS" , 20, 3, 422, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_23" , 23, 1, 422, "RAZ", 1, 1, 0, 0},
+ {"GRP" , 24, 4, 422, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_28_31" , 28, 4, 422, "RAZ", 1, 1, 0, 0},
+ {"MASK" , 32, 16, 422, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_48_63" , 48, 16, 422, "RAZ", 1, 1, 0, 0},
+ {"WORD" , 0, 56, 423, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_56_63" , 56, 8, 423, "RAZ", 1, 1, 0, 0},
+ {"RST" , 0, 1, 424, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_1_63" , 1, 63, 424, "RAZ", 1, 1, 0, 0},
+ {"DRP_OCTS" , 0, 32, 425, "R/W", 0, 1, 0ull, 0},
+ {"DRP_PKTS" , 32, 32, 425, "R/W", 0, 1, 0ull, 0},
+ {"OCTS" , 0, 48, 426, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 426, "RAZ", 1, 1, 0, 0},
+ {"RAW" , 0, 32, 427, "R/W", 0, 1, 0ull, 0},
+ {"PKTS" , 32, 32, 427, "R/W", 0, 1, 0ull, 0},
+ {"MCST" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
+ {"BCST" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
+ {"H64" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
+ {"H65TO127" , 32, 32, 429, "R/W", 0, 1, 0ull, 0},
+ {"H128TO255" , 0, 32, 430, "R/W", 0, 1, 0ull, 0},
+ {"H256TO511" , 32, 32, 430, "R/W", 0, 1, 0ull, 0},
+ {"H512TO1023" , 0, 32, 431, "R/W", 0, 1, 0ull, 0},
+ {"H1024TO1518" , 32, 32, 431, "R/W", 0, 1, 0ull, 0},
+ {"H1519" , 0, 32, 432, "R/W", 0, 1, 0ull, 0},
+ {"FCS" , 32, 32, 432, "R/W", 0, 1, 0ull, 0},
+ {"UNDERSZ" , 0, 32, 433, "R/W", 0, 1, 0ull, 0},
+ {"FRAG" , 32, 32, 433, "R/W", 0, 1, 0ull, 0},
+ {"OVERSZ" , 0, 32, 434, "R/W", 0, 1, 0ull, 0},
+ {"JABBER" , 32, 32, 434, "R/W", 0, 1, 0ull, 0},
+ {"RDCLR" , 0, 1, 435, "R/W", 0, 0, 1ull, 1ull},
+ {"RESERVED_1_63" , 1, 63, 435, "RAZ", 1, 1, 0, 0},
+ {"ERRS" , 0, 16, 436, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_16_63" , 16, 48, 436, "RAZ", 1, 1, 0, 0},
+ {"OCTS" , 0, 48, 437, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_48_63" , 48, 16, 437, "RAZ", 1, 1, 0, 0},
+ {"PKTS" , 0, 32, 438, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 438, "RAZ", 1, 1, 0, 0},
+ {"EN" , 0, 8, 439, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_8_63" , 8, 56, 439, "RAZ", 1, 1, 0, 0},
+ {"MASK" , 0, 16, 440, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 440, "RAZ", 1, 1, 0, 0},
+ {"SRC" , 0, 16, 441, "R/W", 0, 0, 0ull, 0ull},
+ {"DST" , 16, 16, 441, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_32_63" , 32, 32, 441, "RAZ", 1, 1, 0, 0},
+ {"ENTRY" , 0, 62, 442, "RO", 1, 1, 0, 0},
+ {"RESERVED_62_62" , 62, 1, 442, "RAZ", 1, 1, 0, 0},
+ {"VAL" , 63, 1, 442, "RO", 1, 1, 0, 0},
+ {"COUNT" , 0, 32, 443, "R/W1C", 1, 0, 0, 0ull},
+ {"RESERVED_32_63" , 32, 32, 443, "RAZ", 1, 1, 0, 0},
+ {"COUNT" , 0, 48, 444, "R/W1C", 1, 0, 0, 0ull},
+ {"RESERVED_48_63" , 48, 16, 444, "RAZ", 1, 1, 0, 0},
+ {"SIZE" , 0, 16, 445, "RO", 1, 0, 0, 0ull},
+ {"SEGS" , 16, 6, 445, "RO", 1, 0, 0, 0ull},
+ {"CMD" , 22, 14, 445, "RO", 1, 0, 0, 0ull},
+ {"FAU" , 36, 28, 445, "RO", 1, 0, 0, 0ull},
+ {"PTR" , 0, 40, 446, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 40, 16, 446, "RO", 1, 0, 0, 0ull},
+ {"POOL" , 56, 3, 446, "RO", 1, 0, 0, 0ull},
+ {"BACK" , 59, 4, 446, "RO", 1, 0, 0, 0ull},
+ {"I" , 63, 1, 446, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 0, 16, 447, "RO", 1, 0, 0, 0ull},
+ {"SEGS" , 16, 6, 447, "RO", 1, 0, 0, 0ull},
+ {"CMD" , 22, 14, 447, "RO", 1, 0, 0, 0ull},
+ {"FAU" , 36, 28, 447, "RO", 1, 0, 0, 0ull},
+ {"PTR" , 0, 40, 448, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 40, 16, 448, "RO", 1, 0, 0, 0ull},
+ {"POOL" , 56, 3, 448, "RO", 1, 0, 0, 0ull},
+ {"BACK" , 59, 4, 448, "RO", 1, 0, 0, 0ull},
+ {"I" , 63, 1, 448, "RO", 1, 0, 0, 0ull},
+ {"DATA" , 0, 64, 449, "RO", 1, 0, 0, 0ull},
+ {"WIDX2" , 0, 17, 450, "RO", 1, 0, 0, 0ull},
+ {"RIDX2" , 17, 17, 450, "RO", 1, 0, 0, 0ull},
+ {"WIDX" , 34, 17, 450, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_51_63" , 51, 13, 450, "RAZ", 1, 0, 0, 0ull},
+ {"RIDX" , 0, 17, 451, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_17_63" , 17, 47, 451, "RAZ", 1, 0, 0, 0ull},
+ {"PTR" , 0, 40, 452, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 40, 16, 452, "RO", 1, 0, 0, 0ull},
+ {"POOL" , 56, 3, 452, "RO", 1, 0, 0, 0ull},
+ {"BACK" , 59, 4, 452, "RO", 1, 0, 0, 0ull},
+ {"I" , 63, 1, 452, "RO", 1, 0, 0, 0ull},
+ {"PTR" , 0, 40, 453, "RO", 1, 0, 0, 0ull},
+ {"SIZE" , 40, 16, 453, "RO", 1, 0, 0, 0ull},
+ {"POOL" , 56, 3, 453, "RO", 1, 0, 0, 0ull},
+ {"BACK" , 59, 4, 453, "RO", 1, 0, 0, 0ull},
+ {"I" , 63, 1, 453, "RO", 1, 0, 0, 0ull},
+ {"DATA" , 0, 64, 454, "RO", 1, 0, 0, 0ull},
+ {"MAJOR" , 0, 4, 455, "RO", 1, 0, 0, 0ull},
+ {"MINOR" , 4, 2, 455, "RO", 1, 0, 0, 0ull},
+ {"WAIT" , 6, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"QID_BASE" , 7, 7, 455, "RO", 1, 0, 0, 0ull},
+ {"QID_OFF" , 14, 3, 455, "RO", 1, 0, 0, 0ull},
+ {"QCB_RIDX" , 17, 5, 455, "RO", 1, 0, 0, 0ull},
+ {"QOS" , 22, 3, 455, "RO", 1, 0, 0, 0ull},
+ {"ACTIVE" , 25, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"CHK_MODE" , 26, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_27_27" , 27, 1, 455, "RAZ", 1, 0, 0, 0ull},
+ {"CBUF_FRE" , 28, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"XFER_DWR" , 29, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"XFER_WOR" , 30, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"UID" , 31, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"CMND_SIZ" , 32, 16, 455, "RO", 1, 0, 0, 0ull},
+ {"DWRI_CNT" , 48, 13, 455, "RO", 1, 0, 0, 0ull},
+ {"DWRI_LEN" , 61, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"DWRI_SOP" , 62, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"DWRI_MOD" , 63, 1, 455, "RO", 1, 0, 0, 0ull},
+ {"DWRI_MOD" , 0, 2, 456, "RO", 1, 0, 0, 0ull},
+ {"DWRI_UID" , 2, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"DWRI_CHK" , 3, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"WORK_MIN" , 4, 3, 456, "RO", 1, 0, 0, 0ull},
+ {"STATIC_P" , 7, 1, 456, "RO", 1, 0, 0, 0ull},
+ {"QID_OFFM" , 8, 3, 456, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_11_63" , 11, 53, 456, "RAZ", 1, 0, 0, 0ull},
+ {"SIZE" , 0, 16, 457, "RO", 1, 0, 0, 0ull},
+ {"START" , 16, 33, 457, "RO", 1, 0, 0, 0ull},
+ {"DWB" , 49, 9, 457, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_58_63" , 58, 6, 457, "RAZ", 1, 0, 0, 0ull},
+ {"QCB_RIDX" , 0, 6, 458, "RO", 1, 0, 0, 0ull},
+ {"QCB_WIDX" , 6, 6, 458, "RO", 1, 0, 0, 0ull},
+ {"BUF_PTR" , 12, 33, 458, "RO", 1, 0, 0, 0ull},
+ {"BUF_SIZ" , 45, 13, 458, "RO", 1, 0, 0, 0ull},
+ {"TAIL" , 58, 1, 458, "RO", 1, 0, 0, 0ull},
+ {"QOS" , 59, 5, 458, "RO", 1, 0, 0, 0ull},
+ {"QOS" , 0, 3, 459, "RO", 1, 0, 0, 0ull},
+ {"STATIC_Q" , 3, 1, 459, "RO", 1, 0, 0, 0ull},
+ {"S_TAIL" , 4, 1, 459, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_5_7" , 5, 3, 459, "RAZ", 1, 0, 0, 0ull},
+ {"DOORBELL" , 8, 20, 459, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_28_63" , 28, 36, 459, "RAZ", 1, 0, 0, 0ull},
+ {"QUEUE" , 0, 7, 460, "R/W", 1, 0, 0, 0ull},
+ {"PORT" , 7, 6, 460, "WR0", 1, 0, 0, 0ull},
+ {"INDEX" , 13, 3, 460, "WR0", 1, 0, 0, 0ull},
+ {"TAIL" , 16, 1, 460, "R/W", 1, 0, 0, 0ull},
+ {"BUF_PTR" , 17, 36, 460, "R/W", 1, 0, 0, 0ull},
+ {"QOS_MASK" , 53, 8, 460, "R/W", 1, 0, 0, 0ull},
+ {"STATIC_Q" , 61, 1, 460, "WR0", 1, 0, 0, 0ull},
+ {"STATIC_P" , 62, 1, 460, "WR0", 1, 0, 0, 0ull},
+ {"S_TAIL" , 63, 1, 460, "WR0", 1, 0, 0, 0ull},
+ {"QID" , 0, 7, 461, "R/W", 1, 0, 0, 0ull},
+ {"PID" , 7, 6, 461, "WR0", 1, 0, 0, 0ull},
+ {"RESERVED_13_52" , 13, 40, 461, "RAZ", 1, 0, 0, 0ull},
+ {"QOS_MASK" , 53, 8, 461, "R/W", 1, 0, 0, 0ull},
+ {"RESERVED_61_63" , 61, 3, 461, "RAZ", 1, 0, 0, 0ull},
+ {"PSB" , 0, 7, 462, "RO", 1, 0, 0, 0ull},
+ {"PDB" , 7, 4, 462, "RO", 1, 0, 0, 0ull},
+ {"QCB" , 11, 2, 462, "RO", 1, 0, 0, 0ull},
+ {"QSB" , 13, 2, 462, "RO", 1, 0, 0, 0ull},
+ {"CHK" , 15, 1, 462, "RO", 1, 0, 0, 0ull},
+ {"CRC" , 16, 1, 462, "RO", 1, 0, 0, 0ull},
+ {"OUT" , 17, 1, 462, "RO", 1, 0, 0, 0ull},
+ {"NCB" , 18, 1, 462, "RO", 1, 0, 0, 0ull},
+ {"WIF" , 19, 1, 462, "RO", 1, 0, 0, 0ull},
+ {"RIF" , 20, 1, 462, "RO", 1, 0, 0, 0ull},
+ {"COUNT" , 21, 1, 462, "RO", 1, 0, 0, 0ull},
+ {"PSB2" , 22, 5, 462, "RO", 1, 0, 0, 0ull},
+ {"RESERVED_27_63" , 27, 37, 462, "RAZ", 1, 0, 0, 0ull},
+ {"SIZE" , 0, 13, 463, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_13_19" , 13, 7, 463, "RAZ", 0, 0, 0ull, 0ull},
+ {"POOL" , 20, 3, 463, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_23_63" , 23, 41, 463, "RAZ", 1, 0, 0, 0ull},
+ {"ASSERTS" , 0, 17, 464, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_17_63" , 17, 47, 464, "RAZ", 1, 0, 0, 0ull},
+ {"PARITY" , 0, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DOORBELL" , 1, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 465, "RAZ", 1, 0, 0, 0ull},
+ {"ENA_PKO" , 0, 1, 466, "R/W", 0, 0, 0ull, 0ull},
+ {"ENA_DWB" , 1, 1, 466, "R/W", 0, 0, 0ull, 0ull},
+ {"STORE_BE" , 2, 1, 466, "R/W", 0, 0, 0ull, 0ull},
+ {"RESET" , 3, 1, 466, "RAZ", 0, 0, 0ull, 0ull},
+ {"RESERVED_4_63" , 4, 60, 466, "RAZ", 1, 0, 0, 0ull},
+ {"MODE0" , 0, 3, 467, "R/W", 0, 0, 0ull, 0ull},
+ {"MODE1" , 3, 3, 467, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 467, "RAZ", 1, 0, 0, 0ull},
+ {"PARITY" , 0, 1, 468, "R/W", 0, 0, 0ull, 0ull},
+ {"DOORBELL" , 1, 1, 468, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 468, "RAZ", 1, 0, 0, 0ull},
+ {"MODE" , 0, 2, 469, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_2_63" , 2, 62, 469, "RAZ", 1, 0, 0, 0ull},
+ {"INDEX" , 0, 8, 470, "R/W", 0, 0, 0ull, 0ull},
+ {"INC" , 8, 8, 470, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_16_63" , 16, 48, 470, "RAZ", 1, 0, 0, 0ull},
+ {"ADR" , 0, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"PEND" , 1, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"NBR0" , 2, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"NBR1" , 3, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"FIDX" , 4, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"INDEX" , 5, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"NBT0" , 6, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"NBT1" , 7, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"CAM" , 8, 1, 471, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_9_15" , 9, 7, 471, "RAZ", 1, 1, 0, 0},
+ {"PP" , 16, 2, 471, "RO", 0, 0, 0ull, 0ull},
+ {"RESERVED_18_63" , 18, 46, 471, "RAZ", 1, 1, 0, 0},
+ {"DS_PC" , 0, 32, 472, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 472, "RAZ", 1, 1, 0, 0},
+ {"SBE" , 0, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
+ {"DBE" , 1, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
+ {"SBE_IE" , 2, 1, 473, "R/W", 0, 1, 0ull, 0},
+ {"DBE_IE" , 3, 1, 473, "R/W", 0, 1, 0ull, 0},
+ {"SYN" , 4, 5, 473, "RO", 1, 1, 0, 0},
+ {"RESERVED_9_11" , 9, 3, 473, "RAZ", 1, 1, 0, 0},
+ {"RPE" , 12, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
+ {"RPE_IE" , 13, 1, 473, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_14_63" , 14, 50, 473, "RAZ", 1, 1, 0, 0},
+ {"NBR_THR" , 0, 5, 474, "R/W", 0, 0, 2ull, 2ull},
+ {"PFR_DIS" , 5, 1, 474, "R/W", 0, 0, 0ull, 0ull},
+ {"RESERVED_6_63" , 6, 58, 474, "RAZ", 1, 1, 0, 0},
+ {"IQ_CNT" , 0, 32, 475, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 475, "RAZ", 1, 1, 0, 0},
+ {"IQ_CNT" , 0, 32, 476, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 476, "RAZ", 1, 1, 0, 0},
+ {"NOS_CNT" , 0, 9, 477, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_9_63" , 9, 55, 477, "RAZ", 1, 1, 0, 0},
+ {"NW_TIM" , 0, 10, 478, "R/W", 0, 0, 0ull, 1023ull},
+ {"RESERVED_10_63" , 10, 54, 478, "RAZ", 1, 1, 0, 0},
+ {"GRP_MSK" , 0, 16, 479, "R/W", 0, 0, 65535ull, 65535ull},
+ {"RESERVED_16_63" , 16, 48, 479, "RAZ", 1, 1, 0, 0},
+ {"RND" , 0, 8, 480, "R/W", 0, 1, 255ull, 0},
+ {"RND_P1" , 8, 8, 480, "R/W", 0, 1, 255ull, 0},
+ {"RND_P2" , 16, 8, 480, "R/W", 0, 1, 255ull, 0},
+ {"RND_P3" , 24, 8, 480, "R/W", 0, 1, 255ull, 0},
+ {"RESERVED_32_63" , 32, 32, 480, "RAZ", 1, 1, 0, 0},
+ {"MIN_THR" , 0, 8, 481, "R/W", 0, 1, 0ull, 0},
+ {"RESERVED_8_11" , 8, 4, 481, "RAZ", 1, 1, 0, 0},
+ {"MAX_THR" , 12, 8, 481, "R/W", 0, 1, 255ull, 0},
+ {"RESERVED_20_23" , 20, 4, 481, "RAZ", 1, 1, 0, 0},
+ {"FREE_CNT" , 24, 9, 481, "RO", 0, 1, 249ull, 0},
+ {"RESERVED_33_35" , 33, 3, 481, "RAZ", 1, 1, 0, 0},
+ {"BUF_CNT" , 36, 9, 481, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_45_47" , 45, 3, 481, "RAZ", 1, 1, 0, 0},
+ {"DES_CNT" , 48, 9, 481, "RO", 0, 1, 0ull, 0},
+ {"RESERVED_57_63" , 57, 7, 481, "RAZ", 1, 1, 0, 0},
+ {"TS_PC" , 0, 32, 482, "R/W1C", 0, 1, 0ull, 0},
+ {"RESERVED_32_63" , 32, 32, 482, "RAZ", 1, 1, 0, 0},
+ {"WA_PC" , 0, 32, 483, "R/W1C", 0, 1, 0ull, 0},
+ {