Import edk2-stable202005vendor/edk2/ca407c7246bf405da6d9b1b9d93e5e7f17b4b1f9vendor/edk2

As with the previous import, only the MdePkg subdirectory has been
brought in. The line-endings were also converted using:

% find . -type f | xargs -n 1 sed -I.BAK -e `printf "s/\r//g"`
% find . -name \*.BAK | xargs rm

21 files changed, 44325 insertions, 0 deletions

diff --git a/MdePkg/Include/Register/Intel/Msr/AtomMsr.h b/MdePkg/Include/Register/Intel/Msr/AtomMsr.h
new file mode 100644
index 000000000000..20bfd1fe6c74
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/AtomMsr.h
@@ -0,0 +1,784 @@
+/** @file
+  MSR Definitions for the Intel(R) Atom(TM) Processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __ATOM_MSR_H__
+#define __ATOM_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel(R) Atom(TM) Processor Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x1C || \
+    DisplayModel == 0x26 || \
+    DisplayModel == 0x27 || \
+    DisplayModel == 0x35 || \
+    DisplayModel == 0x36    \
+    )                       \
+   )
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_ATOM_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
+  @endcode
+  @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
+**/
+#define MSR_ATOM_PLATFORM_ID                     0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+    ///
+    UINT32  MaximumQualifiedRatio:5;
+    UINT32  Reserved2:19;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_ATOM_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
+**/
+#define MSR_ATOM_EBL_CR_POWERON                  0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Always 0.
+    ///
+    UINT32  DataErrorCheckingEnable:1;
+    ///
+    /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Always 0.
+    ///
+    UINT32  ResponseErrorCheckingEnable:1;
+    ///
+    /// [Bit 3] AERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Always 0.
+    ///
+    UINT32  AERR_DriveEnable:1;
+    ///
+    /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
+    /// Disabled Always 0.
+    ///
+    UINT32  BERR_Enable:1;
+    UINT32  Reserved2:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
+    ///
+    UINT32  BINIT_DriverEnable:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+    /// Always 0.
+    ///
+    UINT32  AERR_ObservationEnabled:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+    /// Always 0.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
+    ///
+    UINT32  ResetVector:1;
+    UINT32  Reserved7:1;
+    ///
+    /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
+    ///
+    UINT32  APICClusterID:2;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
+    ///
+    UINT32  SymmetricArbitrationID:2;
+    ///
+    /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
+    ///
+    UINT32  IntegerBusFrequencyRatio:5;
+    UINT32  Reserved9:5;
+    UINT32  Reserved10:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
+  record registers on the last branch record stack. The From_IP part of the
+  stack contains pointers to the source instruction . See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.5.
+
+  @param  ECX  MSR_ATOM_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
+  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
+  @endcode
+  @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
+  @{
+**/
+#define MSR_ATOM_LASTBRANCH_0_FROM_IP            0x00000040
+#define MSR_ATOM_LASTBRANCH_1_FROM_IP            0x00000041
+#define MSR_ATOM_LASTBRANCH_2_FROM_IP            0x00000042
+#define MSR_ATOM_LASTBRANCH_3_FROM_IP            0x00000043
+#define MSR_ATOM_LASTBRANCH_4_FROM_IP            0x00000044
+#define MSR_ATOM_LASTBRANCH_5_FROM_IP            0x00000045
+#define MSR_ATOM_LASTBRANCH_6_FROM_IP            0x00000046
+#define MSR_ATOM_LASTBRANCH_7_FROM_IP            0x00000047
+/// @}
+
+
+/**
+  Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
+  record registers on the last branch record stack. The To_IP part of the
+  stack contains pointers to the destination instruction.
+
+  @param  ECX  MSR_ATOM_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
+  @endcode
+  @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
+  @{
+**/
+#define MSR_ATOM_LASTBRANCH_0_TO_IP              0x00000060
+#define MSR_ATOM_LASTBRANCH_1_TO_IP              0x00000061
+#define MSR_ATOM_LASTBRANCH_2_TO_IP              0x00000062
+#define MSR_ATOM_LASTBRANCH_3_TO_IP              0x00000063
+#define MSR_ATOM_LASTBRANCH_4_TO_IP              0x00000064
+#define MSR_ATOM_LASTBRANCH_5_TO_IP              0x00000065
+#define MSR_ATOM_LASTBRANCH_6_TO_IP              0x00000066
+#define MSR_ATOM_LASTBRANCH_7_TO_IP              0x00000067
+/// @}
+
+
+/**
+  Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
+  bus clock speed for processors based on Intel Atom microarchitecture:.
+
+  @param  ECX  MSR_ATOM_FSB_FREQ (0x000000CD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_FSB_FREQ_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
+  @endcode
+  @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
+**/
+#define MSR_ATOM_FSB_FREQ                        0x000000CD
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] - Scalable Bus Speed
+    ///
+    /// Atom Processor Family
+    /// ---------------------
+    ///   111B: 083 MHz (FSB 333)
+    ///   101B: 100 MHz (FSB 400)
+    ///   001B: 133 MHz (FSB 533)
+    ///   011B: 167 MHz (FSB 667)
+    ///
+    /// 133.33 MHz should be utilized if performing calculation with
+    /// System Bus Speed when encoding is 001B.
+    /// 166.67 MHz should be utilized if performing calculation with
+    /// System Bus Speed when
+    /// encoding is 011B.
+    ///
+    UINT32  ScalableBusSpeed:3;
+    UINT32  Reserved1:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_FSB_FREQ_REGISTER;
+
+
+/**
+  Shared.
+
+  @param  ECX  MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_BBL_CR_CTL3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
+  AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
+**/
+#define MSR_ATOM_BBL_CR_CTL3                     0x0000011E
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
+    /// Indicates if the L2 is hardware-disabled.
+    ///
+    UINT32  L2HardwareEnabled:1;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 8] L2 Enabled. (R/W)  1 = L2 cache has been initialized 0 =
+    /// Disabled (default) Until this bit is set the processor will not
+    /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
+    ///
+    UINT32  L2Enabled:1;
+    UINT32  Reserved2:14;
+    ///
+    /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
+    ///
+    UINT32  L2NotPresent:1;
+    UINT32  Reserved3:8;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_BBL_CR_CTL3_REGISTER;
+
+
+/**
+  Shared.
+
+  @param  ECX  MSR_ATOM_PERF_STATUS (0x00000198)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_PERF_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
+  AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
+**/
+#define MSR_ATOM_PERF_STATUS                     0x00000198
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Current Performance State Value.
+    ///
+    UINT32  CurrentPerformanceStateValue:16;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
+    /// configured for the processor.
+    ///
+    UINT32  MaximumBusRatio:5;
+    UINT32  Reserved3:19;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_PERF_STATUS_REGISTER;
+
+
+/**
+  Shared.
+
+  @param  ECX  MSR_ATOM_THERM2_CTL (0x0000019D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_THERM2_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
+  AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
+**/
+#define MSR_ATOM_THERM2_CTL                      0x0000019D
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
+    /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
+    /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
+    /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
+    /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
+    ///
+    UINT32  TM_SELECT:1;
+    UINT32  Reserved2:15;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_THERM2_CTL_REGISTER;
+
+
+/**
+  Unique. Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_ATOM_IA32_MISC_ENABLE                0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2. Default value is 0.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
+    /// the processor to indicate a pending break event within the processor 0
+    /// = Indicates compatible FERR# signaling behavior This bit must be set
+    /// to 1 to support XAPIC interrupt model usage.
+    ///
+    UINT32  FERR:1;
+    ///
+    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    ///
+    /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
+    /// thermal sensor indicates that the die temperature is at the
+    /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
+    /// TM2 will reduce the bus to core ratio and voltage according to the
+    /// value last written to MSR_THERM2_CTL bits 15:0.
+    ///   When this bit is clear (0, default), the processor does not change
+    ///   the VID signals or the bus to core ratio when the processor enters a
+    ///   thermally managed state. The BIOS must enable this feature if the
+    ///   TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
+    ///   not set, this feature is not supported and BIOS must not alter the
+    ///   contents of the TM2 bit location. The processor is operating out of
+    ///   specification if both this bit and the TM1 bit are set to 0.
+    ///
+    UINT32  TM2:1;
+    UINT32  Reserved5:2;
+    ///
+    /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved7:1;
+    ///
+    /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
+    /// (R/WO) When set, this bit causes the following bits to become
+    /// read-only: -  Enhanced Intel SpeedStep Technology Select Lock (this
+    /// bit), -  Enhanced Intel SpeedStep Technology Enable bit. The bit must
+    /// be set before an Enhanced Intel SpeedStep Technology transition is
+    /// requested. This bit is cleared on reset.
+    ///
+    UINT32  EISTLock:1;
+    UINT32  Reserved8:1;
+    ///
+    /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved9:8;
+    UINT32  Reserved10:2;
+    ///
+    /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved11:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-2)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 40H).
+
+  @param  ECX  MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_ATOM_LASTBRANCH_TOS                  0x000001C9
+
+
+/**
+  Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_ATOM_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
+  @endcode
+  @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_ATOM_LER_FROM_LIP                    0x000001DD
+
+
+/**
+  Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_ATOM_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
+  @endcode
+  @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_ATOM_LER_TO_LIP                      0x000001DE
+
+
+/**
+  Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
+  (PEBS).".
+
+  @param  ECX  MSR_ATOM_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_ATOM_PEBS_ENABLE                     0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Package. Package C2 Residency Note: C-state values are processor specific
+  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+  C-States. Package. Package C2 Residency Counter. (R/O) Time that this
+  package is in processor-specific C2 states since last reset. Counts at 1 Mhz
+  frequency.
+
+  @param  ECX  MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
+  AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
+  @endcode
+  @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
+**/
+#define MSR_ATOM_PKG_C2_RESIDENCY                0x000003F8
+
+
+/**
+  Package. Package C4 Residency Note: C-state values are processor specific
+  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+  C-States. Package. Package C4 Residency Counter. (R/O) Time that this
+  package is in processor-specific C4 states since last reset. Counts at 1 Mhz
+  frequency.
+
+  @param  ECX  MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
+  AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
+  @endcode
+  @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
+**/
+#define MSR_ATOM_PKG_C4_RESIDENCY                0x000003F9
+
+
+/**
+  Package. Package C6 Residency Note: C-state values are processor specific
+  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+  C-States. Package. Package C6 Residency Counter. (R/O) Time that this
+  package is in processor-specific C6 states since last reset. Counts at 1 Mhz
+  frequency.
+
+  @param  ECX  MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_ATOM_PKG_C6_RESIDENCY                0x000003FA
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h b/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h
new file mode 100644
index 000000000000..f4de39c4df08
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h
@@ -0,0 +1,354 @@
+/** @file
+  MSR Definitions for Intel processors based on the Broadwell microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __BROADWELL_MSR_H__
+#define __BROADWELL_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Broadwell microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3D || \
+    DisplayModel == 0x47 || \
+    DisplayModel == 0x4F || \
+    DisplayModel == 0x56    \
+    )                       \
+   )
+
+/**
+  Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
+  Facilities.".
+
+  @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS    0x0000038E
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Ovf_PMC0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Ovf_PMC1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Ovf_PMC2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Ovf_PMC3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Ovf_FixedCtr0.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Ovf_FixedCtr1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Ovf_FixedCtr2.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
+    /// Addresses (ToPA).".
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:5;
+    ///
+    /// [Bit 61] Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Ovf_BufDSSAVE.
+    ///
+    UINT32  OvfBuf:1;
+    ///
+    /// [Bit 63] CondChgd.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
+
+  @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 0000b:
+    /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
+    /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
+    ///
+    UINT32  Limit:4;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    ///
+    /// [Bit 29] Enable Package C-State Auto-demotion (R/W).
+    ///
+    UINT32  CStateAutoDemotion:1;
+    ///
+    /// [Bit 30] Enable Package C-State Undemotion (R/W).
+    ///
+    UINT32  CStateUndemotion:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
+    /// limit of 5core active.
+    ///
+    UINT32  Maximum5C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
+    /// limit of 6core active.
+    ///
+    UINT32  Maximum6C:8;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT      0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  MAX_RATIO:7;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  MIN_RATIO:7;
+    UINT32  Reserved3:17;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_BROADWELL_PP0_ENERGY_STATUS          0x00000639
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/Core2Msr.h b/MdePkg/Include/Register/Intel/Msr/Core2Msr.h
new file mode 100644
index 000000000000..617daaaff848
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/Core2Msr.h
@@ -0,0 +1,1068 @@
+/** @file
+   MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __CORE2_MSR_H__
+#define __CORE2_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel(R) Core(TM) 2 Processor Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x0F || \
+    DisplayModel == 0x17    \
+    )                       \
+   )
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_CORE2_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
+  @endcode
+  @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
+**/
+#define MSR_CORE2_PLATFORM_ID                    0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+    ///
+    UINT32  MaximumQualifiedRatio:5;
+    UINT32  Reserved2:19;
+    UINT32  Reserved3:18;
+    ///
+    /// [Bits 52:50] See Table 2-2.
+    ///
+    UINT32  PlatformId:3;
+    UINT32  Reserved4:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_CORE2_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
+**/
+#define MSR_CORE2_EBL_CR_POWERON                 0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Note: Not all processor implements R/W.
+    ///
+    UINT32  DataErrorCheckingEnable:1;
+    ///
+    /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Note: Not all processor implements R/W.
+    ///
+    UINT32  ResponseErrorCheckingEnable:1;
+    ///
+    /// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
+    /// all processor implements R/W.
+    ///
+    UINT32  MCERR_DriveEnable:1;
+    ///
+    /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
+    /// Not all processor implements R/W.
+    ///
+    UINT32  AddressParityEnable:1;
+    UINT32  Reserved2:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
+    /// all processor implements R/W.
+    ///
+    UINT32  BINIT_DriverEnable:1;
+    ///
+    /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  OutputTriStateEnable:1;
+    ///
+    /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  MCERR_ObservationEnabled:1;
+    ///
+    /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.
+    ///
+    UINT32  IntelTXTCapableChipset:1;
+    ///
+    /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
+    ///
+    UINT32  ResetVector:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bits 17:16] APIC Cluster ID (R/O).
+    ///
+    UINT32  APICClusterID:2;
+    ///
+    /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =
+    /// Non-integer ratio.
+    ///
+    UINT32  NonIntegerBusRatio:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bits 21:20] Symmetric Arbitration ID (R/O).
+    ///
+    UINT32  SymmetricArbitrationID:2;
+    ///
+    /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
+    ///
+    UINT32  IntegerBusFrequencyRatio:5;
+    UINT32  Reserved7:5;
+    UINT32  Reserved8:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.
+
+  @param  ECX  MSR_CORE2_FEATURE_CONTROL (0x0000003A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
+**/
+#define MSR_CORE2_FEATURE_CONTROL                0x0000003A
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock
+    /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read
+    /// visible and writeable while in SMM.
+    ///
+    UINT32  SMRREnable:1;
+    UINT32  Reserved2:28;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
+  record registers on the last branch record stack. The From_IP part of the
+  stack contains pointers to the source instruction. See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.5.
+
+  @param  ECX  MSR_CORE2_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
+  AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
+  @endcode
+  @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
+  @{
+**/
+#define MSR_CORE2_LASTBRANCH_0_FROM_IP           0x00000040
+#define MSR_CORE2_LASTBRANCH_1_FROM_IP           0x00000041
+#define MSR_CORE2_LASTBRANCH_2_FROM_IP           0x00000042
+#define MSR_CORE2_LASTBRANCH_3_FROM_IP           0x00000043
+/// @}
+
+
+/**
+  Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
+  record registers on the last branch record stack. This To_IP part of the
+  stack contains pointers to the destination instruction.
+
+  @param  ECX  MSR_CORE2_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
+  @endcode
+  @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
+  @{
+**/
+#define MSR_CORE2_LASTBRANCH_0_TO_IP             0x00000060
+#define MSR_CORE2_LASTBRANCH_1_TO_IP             0x00000061
+#define MSR_CORE2_LASTBRANCH_2_TO_IP             0x00000062
+#define MSR_CORE2_LASTBRANCH_3_TO_IP             0x00000063
+/// @}
+
+
+/**
+  Unique. System Management Mode Base Address register (WO in SMM)
+  Model-specific implementation of SMRR-like interface, read visible and write
+  only in SMM.
+
+  @param  ECX  MSR_CORE2_SMRR_PHYSBASE (0x000000A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_SMRR_PHYSBASE_REGISTER  Msr;
+
+  Msr.Uint64 = 0;
+  AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
+**/
+#define MSR_CORE2_SMRR_PHYSBASE                  0x000000A0
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:12;
+    ///
+    /// [Bits 31:12] PhysBase. SMRR physical Base Address.
+    ///
+    UINT32  PhysBase:20;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_SMRR_PHYSBASE_REGISTER;
+
+
+/**
+  Unique. System Management Mode Physical Address Mask register (WO in SMM)
+  Model-specific implementation of SMRR-like interface, read visible and write
+  only in SMM.
+
+  @param  ECX  MSR_CORE2_SMRR_PHYSMASK (0x000000A1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_SMRR_PHYSMASK_REGISTER  Msr;
+
+  Msr.Uint64 = 0;
+  AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
+**/
+#define MSR_CORE2_SMRR_PHYSMASK                  0x000000A1
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:11;
+    ///
+    /// [Bit 11] Valid. Physical address base and range mask are valid.
+    ///
+    UINT32  Valid:1;
+    ///
+    /// [Bits 31:12] PhysMask. SMRR physical address range mask.
+    ///
+    UINT32  PhysMask:20;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_SMRR_PHYSMASK_REGISTER;
+
+
+/**
+  Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
+  bus clock speed for processors based on Intel Core microarchitecture:.
+
+  @param  ECX  MSR_CORE2_FSB_FREQ (0x000000CD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_FSB_FREQ_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
+  @endcode
+  @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
+**/
+#define MSR_CORE2_FSB_FREQ                       0x000000CD
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_FSB_FREQ
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] - Scalable Bus Speed
+    ///   101B: 100 MHz (FSB 400)
+    ///   001B: 133 MHz (FSB 533)
+    ///   011B: 167 MHz (FSB 667)
+    ///   010B: 200 MHz (FSB 800)
+    ///   000B: 267 MHz (FSB 1067)
+    ///   100B: 333 MHz (FSB 1333)
+    ///
+    ///   133.33 MHz should be utilized if performing calculation with System
+    ///   Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
+    ///   performing calculation with System Bus Speed when encoding is 011B.
+    ///   266.67 MHz should be utilized if performing calculation with System
+    ///   Bus Speed when encoding is 000B. 333.33 MHz should be utilized if
+    ///   performing calculation with System Bus Speed when encoding is 100B.
+    ///
+    UINT32  ScalableBusSpeed:3;
+    UINT32  Reserved1:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_FSB_FREQ_REGISTER;
+
+/**
+  Shared.
+
+  @param  ECX  MSR_CORE2_PERF_STATUS (0x00000198)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_PERF_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
+  AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
+**/
+#define MSR_CORE2_PERF_STATUS                    0x00000198
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PERF_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Current Performance State Value.
+    ///
+    UINT32  CurrentPerformanceStateValue:16;
+    UINT32  Reserved1:15;
+    ///
+    /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default
+    /// is cleared.
+    ///
+    UINT32  XEOperation:1;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
+    /// configured for the processor.
+    ///
+    UINT32  MaximumBusRatio:5;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio
+    /// is enabled. Applies processors based on Enhanced Intel Core
+    /// microarchitecture.
+    ///
+    UINT32  NonIntegerBusRatio:1;
+    UINT32  Reserved4:17;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PERF_STATUS_REGISTER;
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE2_THERM2_CTL (0x0000019D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_THERM2_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
+  AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
+**/
+#define MSR_CORE2_THERM2_CTL                     0x0000019D
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_THERM2_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
+    /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
+    /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
+    /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
+    /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
+    ///
+    UINT32  TM_SELECT:1;
+    UINT32  Reserved2:15;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_THERM2_CTL_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_CORE2_IA32_MISC_ENABLE               0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the
+    /// hardware prefetcher operation on streams of data. When clear
+    /// (default), enables the prefetch queue. Disabling of the hardware
+    /// prefetcher may impact processor performance.
+    ///
+    UINT32  HardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
+    /// the processor to indicate a pending break event within the processor 0
+    /// = Indicates compatible FERR# signaling behavior This bit must be set
+    /// to 1 to support XAPIC interrupt model usage.
+    ///
+    UINT32  FERR:1;
+    ///
+    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    ///
+    /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
+    /// thermal sensor indicates that the die temperature is at the
+    /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
+    /// TM2 will reduce the bus to core ratio and voltage according to the
+    /// value last written to MSR_THERM2_CTL bits 15:0.
+    ///   When this bit is clear (0, default), the processor does not change
+    ///   the VID signals or the bus to core ratio when the processor enters a
+    ///   thermally managed state. The BIOS must enable this feature if the
+    ///   TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
+    ///   not set, this feature is not supported and BIOS must not alter the
+    ///   contents of the TM2 bit location. The processor is operating out of
+    ///   specification if both this bit and the TM1 bit are set to 0.
+    ///
+    UINT32  TM2:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    ///
+    /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W)  When set
+    /// to 1, the processor fetches the cache line that contains data
+    /// currently required by the processor. When set to 0, the processor
+    /// fetches cache lines that comprise a cache line pair (128 bytes).
+    /// Single processor platforms should not set this bit. Server platforms
+    /// should set or clear this bit based on platform performance observed in
+    /// validation and testing. BIOS may contain a setup option that controls
+    /// the setting of this bit.
+    ///
+    UINT32  AdjacentCacheLinePrefetchDisable:1;
+    ///
+    /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
+    /// (R/WO) When set, this bit causes the following bits to become
+    /// read-only: -  Enhanced Intel SpeedStep Technology Select Lock (this
+    /// bit), -  Enhanced Intel SpeedStep Technology Enable bit. The bit must
+    /// be set before an Enhanced Intel SpeedStep Technology transition is
+    /// requested. This bit is cleared on reset.
+    ///
+    UINT32  EISTLock:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:2;
+    ///
+    /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU
+    /// L1 data cache prefetcher is disabled. The default value after reset is
+    /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is
+    /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple
+    /// loads from the same line done within a time limit, the DCU prefetcher
+    /// assumes the next line will be required. The next line is prefetched in
+    /// to the L1 data cache from memory or L2.
+    ///
+    UINT32  DCUPrefetcherDisable:1;
+    ///
+    /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that
+    /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled
+    /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
+    /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
+    /// reports the processor's support of IDA is enabled. Note: the power-on
+    /// default value is used by BIOS to detect hardware support of IDA. If
+    /// power-on default value is 1, IDA is available in the processor. If
+    /// power-on default value is 0, IDA is not available.
+    ///
+    UINT32  IDADisable:1;
+    ///
+    /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP
+    /// prefetcher is disabled. The default value after reset is 0. BIOS may
+    /// write '1' to disable this feature. The IP prefetcher is an L1 data
+    /// cache prefetcher. The IP prefetcher looks for sequential load history
+    /// to determine whether to prefetch the next expected data into the L1
+    /// cache from memory or L2.
+    ///
+    UINT32  IPPrefetcherDisable:1;
+    UINT32  Reserved10:24;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 40H).
+
+  @param  ECX  MSR_CORE2_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_CORE2_LASTBRANCH_TOS                 0x000001C9
+
+
+/**
+  Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_CORE2_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
+  @endcode
+  @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_CORE2_LER_FROM_LIP                   0x000001DD
+
+
+/**
+  Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_CORE2_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
+  @endcode
+  @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_CORE2_LER_TO_LIP                     0x000001DE
+
+
+/**
+  Unique. Fixed-Function Performance Counter Register n (R/W).
+
+  @param  ECX  MSR_CORE2_PERF_FIXED_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
+  AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.
+        MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.
+        MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.
+  @{
+**/
+#define MSR_CORE2_PERF_FIXED_CTR0                0x00000309
+#define MSR_CORE2_PERF_FIXED_CTR1                0x0000030A
+#define MSR_CORE2_PERF_FIXED_CTR2                0x0000030B
+/// @}
+
+
+/**
+  Unique. RO. This applies to processors that do not support architectural
+  perfmon version 2.
+
+  @param  ECX  MSR_CORE2_PERF_CAPABILITIES (0x00000345)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_PERF_CAPABILITIES_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
+  AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.
+**/
+#define MSR_CORE2_PERF_CAPABILITIES              0x00000345
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 5:0] LBR Format. See Table 2-2.
+    ///
+    UINT32  LBR_FMT:6;
+    ///
+    /// [Bit 6] PEBS Record Format.
+    ///
+    UINT32  PEBS_FMT:1;
+    ///
+    /// [Bit 7] PEBSSaveArchRegs. See Table 2-2.
+    ///
+    UINT32  PEBS_ARCH_REG:1;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PERF_CAPABILITIES_REGISTER;
+
+
+/**
+  Unique. Fixed-Function-Counter Control Register (R/W).
+
+  @param  ECX  MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
+  AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.
+**/
+#define MSR_CORE2_PERF_FIXED_CTR_CTRL            0x0000038D
+
+
+/**
+  Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
+
+  @param  ECX  MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_CORE2_PERF_GLOBAL_STATUS             0x0000038E
+
+
+/**
+  Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
+
+  @param  ECX  MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_CORE2_PERF_GLOBAL_CTRL               0x0000038F
+
+
+/**
+  Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
+
+  @param  ECX  MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
+  AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
+**/
+#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL           0x00000390
+
+
+/**
+  Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
+  (PEBS).".
+
+  @param  ECX  MSR_CORE2_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_CORE2_PEBS_ENABLE                    0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
+  processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
+
+  @param  ECX  MSR_CORE2_EMON_L3_CTR_CTLn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
+  AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
+  @endcode
+  @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
+  @{
+**/
+#define MSR_CORE2_EMON_L3_CTR_CTL0               0x000107CC
+#define MSR_CORE2_EMON_L3_CTR_CTL1               0x000107CD
+#define MSR_CORE2_EMON_L3_CTR_CTL2               0x000107CE
+#define MSR_CORE2_EMON_L3_CTR_CTL3               0x000107CF
+#define MSR_CORE2_EMON_L3_CTR_CTL4               0x000107D0
+#define MSR_CORE2_EMON_L3_CTR_CTL5               0x000107D1
+#define MSR_CORE2_EMON_L3_CTR_CTL6               0x000107D2
+#define MSR_CORE2_EMON_L3_CTR_CTL7               0x000107D3
+/// @}
+
+
+/**
+  Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor
+  7400 series (processor signature 06_1D) only. See Section 17.2.2.
+
+  @param  ECX  MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
+  AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
+  @endcode
+  @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.
+**/
+#define MSR_CORE2_EMON_L3_GL_CTL                 0x000107D8
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/CoreMsr.h b/MdePkg/Include/Register/Intel/Msr/CoreMsr.h
new file mode 100644
index 000000000000..a000ab718419
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/CoreMsr.h
@@ -0,0 +1,1056 @@
+/** @file
+  MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __CORE_MSR_H__
+#define __CORE_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel Core Solo and Intel Core Duo Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   ( \
+    DisplayModel == 0x0E \
+    ) \
+   )
+
+/**
+  Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
+
+  @param  ECX  MSR_CORE_P5_MC_ADDR (0x00000000)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
+  @endcode
+  @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
+**/
+#define MSR_CORE_P5_MC_ADDR                      0x00000000
+
+
+/**
+  Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
+
+  @param  ECX  MSR_CORE_P5_MC_TYPE (0x00000001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
+  @endcode
+  @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
+**/
+#define MSR_CORE_P5_MC_TYPE                      0x00000001
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_CORE_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
+**/
+#define MSR_CORE_EBL_CR_POWERON                  0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Note: Not all processor implements R/W.
+    ///
+    UINT32  DataErrorCheckingEnable:1;
+    ///
+    /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Note: Not all processor implements R/W.
+    ///
+    UINT32  ResponseErrorCheckingEnable:1;
+    ///
+    /// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
+    /// all processor implements R/W.
+    ///
+    UINT32  MCERR_DriveEnable:1;
+    ///
+    /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
+    /// Not all processor implements R/W.
+    ///
+    UINT32  AddressParityEnable:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
+    /// all processor implements R/W.
+    ///
+    UINT32  BINIT_DriverEnable:1;
+    ///
+    /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  OutputTriStateEnable:1;
+    ///
+    /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  MCERR_ObservationEnabled:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
+    ///
+    UINT32  ResetVector:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bits 17:16] APIC Cluster ID (R/O).
+    ///
+    UINT32  APICClusterID:2;
+    ///
+    /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
+    ///
+    UINT32  SystemBusFrequency:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bits 21:20] Symmetric Arbitration ID (R/O).
+    ///
+    UINT32  SymmetricArbitrationID:2;
+    ///
+    /// [Bits 26:22] Clock Frequency Ratio (R/O).
+    ///
+    UINT32  ClockFrequencyRatio:5;
+    UINT32  Reserved7:5;
+    UINT32  Reserved8:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
+  the last branch record stack: bits 31-0 hold the 'from' address and bits
+  63-32 hold the 'to' address. See also: -  Last Branch Record Stack TOS at
+  1C9H -  Section 17.15, "Last Branch, Interrupt, and Exception Recording
+  (Pentium M Processors).".
+
+  @param  ECX  MSR_CORE_LASTBRANCH_n
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
+  AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
+  @endcode
+  @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+        MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+        MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+        MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
+        MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
+        MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
+        MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
+        MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
+  @{
+**/
+#define MSR_CORE_LASTBRANCH_0                    0x00000040
+#define MSR_CORE_LASTBRANCH_1                    0x00000041
+#define MSR_CORE_LASTBRANCH_2                    0x00000042
+#define MSR_CORE_LASTBRANCH_3                    0x00000043
+#define MSR_CORE_LASTBRANCH_4                    0x00000044
+#define MSR_CORE_LASTBRANCH_5                    0x00000045
+#define MSR_CORE_LASTBRANCH_6                    0x00000046
+#define MSR_CORE_LASTBRANCH_7                    0x00000047
+/// @}
+
+
+/**
+  Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
+  clock speed:.
+
+  @param  ECX  MSR_CORE_FSB_FREQ (0x000000CD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_FSB_FREQ_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_FSB_FREQ_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_FSB_FREQ_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
+  @endcode
+  @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
+**/
+#define MSR_CORE_FSB_FREQ                        0x000000CD
+
+/**
+  MSR information returned for MSR index #MSR_CORE_FSB_FREQ
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] - Scalable Bus Speed
+    ///   101B: 100 MHz (FSB 400)
+    ///   001B: 133 MHz (FSB 533)
+    ///   011B: 167 MHz (FSB 667)
+    ///
+    /// 133.33 MHz should be utilized if performing calculation with System Bus
+    /// Speed when encoding is 101B. 166.67 MHz should be utilized if
+    /// performing calculation with System Bus Speed when encoding is 001B.
+    ///
+    UINT32  ScalableBusSpeed:3;
+    UINT32  Reserved1:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_FSB_FREQ_REGISTER;
+
+
+/**
+  Shared.
+
+  @param  ECX  MSR_CORE_BBL_CR_CTL3 (0x0000011E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_BBL_CR_CTL3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
+  AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
+**/
+#define MSR_CORE_BBL_CR_CTL3                     0x0000011E
+
+/**
+  MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
+    /// Indicates if the L2 is hardware-disabled.
+    ///
+    UINT32  L2HardwareEnabled:1;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 8] L2 Enabled (R/W)  1 = L2 cache has been initialized 0 =
+    /// Disabled (default) Until this bit is set the processor will not
+    /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
+    ///
+    UINT32  L2Enabled:1;
+    UINT32  Reserved2:14;
+    ///
+    /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
+    ///
+    UINT32  L2NotPresent:1;
+    UINT32  Reserved3:8;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_BBL_CR_CTL3_REGISTER;
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_THERM2_CTL (0x0000019D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_THERM2_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_THERM2_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_THERM2_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
+  AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
+**/
+#define MSR_CORE_THERM2_CTL                      0x0000019D
+
+/**
+  MSR information returned for MSR index #MSR_CORE_THERM2_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
+    /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
+    /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
+    /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
+    /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
+    ///
+    UINT32  TM_SELECT:1;
+    UINT32  Reserved2:15;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_THERM2_CTL_REGISTER;
+
+
+/**
+  Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_CORE_IA32_MISC_ENABLE                0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
+    /// the processor to indicate a pending break event within the processor 0
+    /// = Indicates compatible FERR# signaling behavior This bit must be set
+    /// to 1 to support XAPIC interrupt model usage.
+    ///
+    UINT32  FERR:1;
+    ///
+    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
+    /// thermal sensor indicates that the die temperature is at the
+    /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
+    /// TM2 will reduce the bus to core ratio and voltage according to the
+    /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear
+    /// (0, default), the processor does not change the VID signals or the bus
+    /// to core ratio when the processor enters a thermal managed state. If
+    /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID
+    /// with EAX = 1, then this feature is not supported and BIOS must not
+    /// alter the contents of this bit location. The processor is operating
+    /// out of spec if both this bit and the TM1 bit are set to disabled
+    /// states.
+    ///
+    UINT32  TM2:1;
+    UINT32  Reserved5:2;
+    ///
+    /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
+    /// Enhanced Intel SpeedStep Technology enabled.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved7:1;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this
+    /// bit may cause behavior in software that depends on the availability of
+    /// CPUID leaves greater than 2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    UINT32  Reserved9:9;
+    UINT32  Reserved10:2;
+    ///
+    /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved11:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 40H).
+
+  @param  ECX  MSR_CORE_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_CORE_LASTBRANCH_TOS                  0x000001C9
+
+
+/**
+  Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_CORE_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
+  @endcode
+  @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_CORE_LER_FROM_LIP                    0x000001DD
+
+
+/**
+  Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_CORE_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
+  @endcode
+  @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_CORE_LER_TO_LIP                      0x000001DE
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRPHYSBASEn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
+  AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
+  @endcode
+  @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
+        MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
+        MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
+        MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
+        MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
+        MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
+        MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
+        MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
+  @{
+**/
+#define MSR_CORE_MTRRPHYSBASE0                   0x00000200
+#define MSR_CORE_MTRRPHYSBASE1                   0x00000202
+#define MSR_CORE_MTRRPHYSBASE2                   0x00000204
+#define MSR_CORE_MTRRPHYSBASE3                   0x00000206
+#define MSR_CORE_MTRRPHYSBASE4                   0x00000208
+#define MSR_CORE_MTRRPHYSBASE5                   0x0000020A
+#define MSR_CORE_MTRRPHYSMASK6                   0x0000020D
+#define MSR_CORE_MTRRPHYSMASK7                   0x0000020F
+/// @}
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRPHYSMASKn (0x00000201)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
+  AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
+  @endcode
+  @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
+        MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
+        MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
+        MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
+        MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
+        MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
+        MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
+        MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
+  @{
+**/
+#define MSR_CORE_MTRRPHYSMASK0                   0x00000201
+#define MSR_CORE_MTRRPHYSMASK1                   0x00000203
+#define MSR_CORE_MTRRPHYSMASK2                   0x00000205
+#define MSR_CORE_MTRRPHYSMASK3                   0x00000207
+#define MSR_CORE_MTRRPHYSMASK4                   0x00000209
+#define MSR_CORE_MTRRPHYSMASK5                   0x0000020B
+#define MSR_CORE_MTRRPHYSBASE6                   0x0000020C
+#define MSR_CORE_MTRRPHYSBASE7                   0x0000020E
+/// @}
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX64K_00000 (0x00000250)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX64K_00000                0x00000250
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX16K_80000 (0x00000258)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX16K_80000                0x00000258
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX16K_A0000                0x00000259
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_C0000                 0x00000268
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_C8000                 0x00000269
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_D0000                 0x0000026A
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_D8000                 0x0000026B
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_E0000                 0x0000026C
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_E8000                 0x0000026D
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_F0000                 0x0000026E
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_F8000                 0x0000026F
+
+
+/**
+  Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
+
+  @param  ECX  MSR_CORE_MC4_CTL (0x0000040C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
+  AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
+  @endcode
+  @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
+**/
+#define MSR_CORE_MC4_CTL                         0x0000040C
+
+
+/**
+  Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
+
+  @param  ECX  MSR_CORE_MC4_STATUS (0x0000040D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
+  AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
+  @endcode
+  @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
+**/
+#define MSR_CORE_MC4_STATUS                      0x0000040D
+
+
+/**
+  Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
+  register is either not implemented or contains no address if the ADDRV flag
+  in the MSR_MC4_STATUS register is clear. When not implemented in the
+  processor, all reads and writes to this MSR will cause a general-protection
+  exception.
+
+  @param  ECX  MSR_CORE_MC4_ADDR (0x0000040E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
+  AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
+  @endcode
+  @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
+**/
+#define MSR_CORE_MC4_ADDR                        0x0000040E
+
+
+/**
+  Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
+  register is either not implemented or contains no address if the ADDRV flag
+  in the MSR_MC3_STATUS register is clear. When not implemented in the
+  processor, all reads and writes to this MSR will cause a general-protection
+  exception.
+
+  @param  ECX  MSR_CORE_MC3_ADDR (0x00000412)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
+  AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
+  @endcode
+  @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
+**/
+#define MSR_CORE_MC3_ADDR                        0x00000412
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC3_MISC (0x00000413)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
+  AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
+  @endcode
+  @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
+**/
+#define MSR_CORE_MC3_MISC                        0x00000413
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC5_CTL (0x00000414)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
+  AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
+  @endcode
+  @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
+**/
+#define MSR_CORE_MC5_CTL                         0x00000414
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC5_STATUS (0x00000415)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
+  AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
+  @endcode
+  @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
+**/
+#define MSR_CORE_MC5_STATUS                      0x00000415
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC5_ADDR (0x00000416)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
+  AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
+  @endcode
+  @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
+**/
+#define MSR_CORE_MC5_ADDR                        0x00000416
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC5_MISC (0x00000417)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
+  AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
+  @endcode
+  @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
+**/
+#define MSR_CORE_MC5_MISC                        0x00000417
+
+
+/**
+  Unique. See Table 2-2.
+
+  @param  ECX  MSR_CORE_IA32_EFER (0xC0000080)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_IA32_EFER_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_IA32_EFER_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_IA32_EFER_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
+  AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
+**/
+#define MSR_CORE_IA32_EFER                       0xC0000080
+
+/**
+  MSR information returned for MSR index #MSR_CORE_IA32_EFER
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:11;
+    ///
+    /// [Bit 11] Execute Disable Bit Enable.
+    ///
+    UINT32  NXE:1;
+    UINT32  Reserved2:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_IA32_EFER_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h b/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h
new file mode 100644
index 000000000000..a8da54c39459
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h
@@ -0,0 +1,2539 @@
+/** @file
+  MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __GOLDMONT_MSR_H__
+#define __GOLDMONT_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel Atom processors based on the Goldmont microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x5C    \
+    )                       \
+   )
+
+/**
+  Core. Control Features in Intel 64Processor (R/W).
+
+  @param  ECX  MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_FEATURE_CONTROL             0x0000003A
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock bit (R/WL)
+    ///
+    UINT32  Lock:1;
+    ///
+    /// [Bit 1] Enable VMX inside SMX operation (R/WL)
+    ///
+    UINT32  EnableVmxInsideSmx:1;
+    ///
+    /// [Bit 2] Enable VMX outside SMX operation (R/WL)
+    ///
+    UINT32  EnableVmxOutsideSmx:1;
+    UINT32  Reserved1:5;
+    ///
+    /// [Bits 14:8] SENTER local function enables (R/WL)
+    ///
+    UINT32  SenterLocalFunctionEnables:7;
+    ///
+    /// [Bit 15] SENTER global functions enable (R/WL)
+    ///
+    UINT32  SenterGlobalEnable:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 18] SGX global functions enable (R/WL)
+    ///
+    UINT32  SgxEnable:1;
+    UINT32  Reserved3:13;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_GOLDMONT_PLATFORM_INFO               0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    ///
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O)  When set to 1,
+    /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
+    /// specify an temperature offset.
+    ///
+    UINT32  TJOFFSET:1;
+    UINT32  Reserved3:1;
+    UINT32  Reserved4:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates. See http://biosbits.org.
+
+  @param  ECX  MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type
+               MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type
+               MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL      0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package C-State Limit (R/W)  Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power). for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 0000b:
+    /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8
+    /// 0111b: C9 1000b: C10.
+    ///
+    UINT32  Limit:4;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
+    /// IO_read instructions sent to IO register specified by
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
+    /// until next reset.
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:16;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.
+  Accessible only while in SMM.
+
+  @param  ECX  MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_GOLDMONT_SMM_MCA_CAP                 0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and the
+    /// MSR_SMM_FEATURE_CONTROL is supported.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
+    /// supported.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_GOLDMONT_IA32_MISC_ENABLE            0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2. Default value is 1.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved6:3;
+    ///
+    /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:3;
+    ///
+    /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
+    /// that support Intel Turbo Boost Technology, the turbo mode feature is
+    /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
+    /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
+    /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
+    /// the power-on default value is used by BIOS to detect hardware support
+    /// of turbo mode. If power-on default value is 1, turbo mode is available
+    /// in the processor. If power-on default value is 0, turbo mode is not
+    /// available.
+    ///
+    UINT32  TurboModeDisable:1;
+    UINT32  Reserved10:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Miscellaneous Feature Control (R/W).
+
+  @param  ECX  MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_MISC_FEATURE_CONTROL        0x000001A4
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
+    /// L2 hardware prefetcher, which fetches additional lines of code or data
+    /// into the L2 cache.
+    ///
+    UINT32  L2HardwarePrefetcherDisable:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
+    /// the L1 data cache prefetcher, which fetches the next cache line into
+    /// L1 data cache.
+    ///
+    UINT32  DCUHardwarePrefetcherDisable:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);
+  AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
+**/
+#define MSR_GOLDMONT_MISC_PWR_MGMT               0x000001AA
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables
+    /// hardware coordination of Enhanced Intel Speedstep Technology request
+    /// from processor cores; When 1, disables hardware coordination of
+    /// Enhanced Intel Speedstep Technology requests.
+    ///
+    UINT32  EISTHardwareCoordinationDisable:1;
+    UINT32  Reserved1:21;
+    ///
+    /// [Bit 22] Thermal Interrupt Coordination Enable (R/W)  If set, then
+    /// thermal interrupt on one core is routed to all cores.
+    ///
+    UINT32  ThermalInterruptCoordinationEnable:1;
+    UINT32  Reserved2:9;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies
+  Maximum Ratio Limit for each Core Group. Max ratio for groups with more
+  cores must decrease monotonically. For groups with less than 4 cores, the
+  max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must
+  be 22 or less. For groups with more than 5 cores, the max ratio must be 16
+  or less..
+
+  @param  ECX  MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_RATIO_LIMIT           0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 0 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup0:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 1 threshold and greater than Group 0 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup1:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 2 threshold and greater than Group 1 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup2:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 3 threshold and greater than Group 2 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup3:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 4 threshold and greater than Group 3 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup4:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 5 threshold and greater than Group 4 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup5:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 6 threshold and greater than Group 5 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup6:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 7 threshold and greater than Group 6 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup7:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of
+  0 threshold is ignored.
+
+  @param  ECX  MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);
+  AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_GROUP_CORECNT         0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 0 Max Turbo Ratio limit.
+    ///
+    UINT32  CoreCountThresholdGroup0:8;
+    ///
+    /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be
+    /// greater than Group 0 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup1:8;
+    ///
+    /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be
+    /// greater than Group 1 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup2:8;
+    ///
+    /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be
+    /// greater than Group 2 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup3:8;
+    ///
+    /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be
+    /// greater than Group 3 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup4:8;
+    ///
+    /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be
+    /// greater than Group 4 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup5:8;
+    ///
+    /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be
+    /// greater than Group 5 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup6:8;
+    ///
+    /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be
+    /// greater than Group 6 Core Count and not less than the total number of
+    /// processor cores in the package. E.g. specify 255.
+    ///
+    UINT32  CoreCountThresholdGroup7:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;
+
+
+/**
+  Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
+  "Filtering of Last Branch Records.".
+
+  @param  ECX  MSR_GOLDMONT_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_LBR_SELECT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);
+  AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_GOLDMONT_LBR_SELECT                  0x000001C8
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    ///
+    /// [Bit 9] EN_CALL_STACK.
+    ///
+    UINT32  EN_CALL_STACK:1;
+    UINT32  Reserved1:22;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_LBR_SELECT_REGISTER;
+
+
+/**
+  Core. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-4) that
+  points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP.
+
+  @param  ECX  MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_GOLDMONT_LASTBRANCH_TOS              0x000001C9
+
+
+/**
+  Core. Power Control Register. See http://biosbits.org.
+
+  @param  ECX  MSR_GOLDMONT_POWER_CTL (0x000001FC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_POWER_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);
+  AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.
+**/
+#define MSR_GOLDMONT_POWER_CTL                   0x000001FC
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Package. C1E Enable (R/W)  When set to '1', will enable the
+    /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
+    /// operating point when all execution cores enter MWAIT (C1).
+    ///
+    UINT32  C1EEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_POWER_CTL_REGISTER;
+
+
+/**
+  Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+  CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+  the package. Lower 64 bits of an 128-bit external entropy value for key
+  derivation of an enclave.
+
+  @param  ECX  MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);
+  @endcode
+  @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.
+**/
+#define MSR_GOLDMONT_SGXOWNEREPOCH0                   0x00000300
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER0                        MSR_GOLDMONT_SGXOWNEREPOCH0
+
+
+/**
+  Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
+  an 128-bit external entropy value for key derivation of an enclave.
+
+  @param  ECX  MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);
+  @endcode
+  @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.
+**/
+#define MSR_GOLDMONT_SGXOWNEREPOCH1                   0x00000301
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER1                        MSR_GOLDMONT_SGXOWNEREPOCH1
+
+
+/**
+  Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
+  Monitoring Version 4.".
+
+  @param  ECX  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
+
+/**
+  MSR information returned for MSR index
+  #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Set 1 to clear Ovf_PMC0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Set 1 to clear Ovf_PMC1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Set 1 to clear Ovf_PMC2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Set 1 to clear Ovf_PMC3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 58] Set 1 to clear LBR_Frz.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Set 1 to clear CTR_Frz.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Set 1 to clear ASCI.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Set 1 to clear Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    ///
+    /// [Bit 63] Set 1 to clear CondChgd.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
+
+
+/**
+  Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
+  Monitoring Version 4.".
+
+  @param  ECX  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
+
+/**
+  MSR information returned for MSR index
+  #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.
+    ///
+    UINT32  Ovf_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 58] Set 1 to cause LBR_Frz = 1.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Set 1 to cause CTR_Frz = 1.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Set 1 to cause ASCI = 1.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Set 1 to cause Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    UINT32  Reserved4:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
+
+
+/**
+  Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
+  (PEBS).".
+
+  @param  ECX  MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_GOLDMONT_PEBS_ENABLE                 0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC0. (R/W).
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C3 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C3_RESIDENCY            0x000003F8
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C6 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C6_RESIDENCY            0x000003F9
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C3 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_CORE_C3_RESIDENCY           0x000003FC
+
+
+/**
+  Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_SMM_FEATURE_CONTROL         0x000004E0
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
+    /// further changes.
+    ///
+    UINT32  Lock:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
+    /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
+    /// logical processors are prevented from executing SMM code outside the
+    /// ranges defined by the SMRR. When set to '1' any logical processor in
+    /// the package that attempts to execute SMM code not within the ranges
+    /// defined by the SMRR will assert an unrecoverable MCE.
+    ///
+    UINT32  SMM_Code_Chk_En:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
+  processors in the package. Available only while in SMM and
+  MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
+
+  @param  ECX  MSR_GOLDMONT_SMM_DELAYED (0x000004E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_SMM_DELAYED_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);
+  AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
+**/
+#define MSR_GOLDMONT_SMM_DELAYED                 0x000004E2
+
+
+/**
+  Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
+  processors in the package. Available only while in SMM.
+
+  @param  ECX  MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_SMM_BLOCKED_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);
+  AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
+**/
+#define MSR_GOLDMONT_SMM_BLOCKED                 0x000004E3
+
+
+/**
+  Core. Trace Control Register (R/W).
+
+  @param  ECX  MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
+**/
+#define MSR_IA32_RTIT_CTL                        0x00000570
+
+/**
+  MSR information returned for MSR index #MSR_IA32_RTIT_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] TraceEn.
+    ///
+    UINT32  TraceEn:1;
+    ///
+    /// [Bit 1] CYCEn.
+    ///
+    UINT32  CYCEn:1;
+    ///
+    /// [Bit 2] OS.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 3] User.
+    ///
+    UINT32  User:1;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 7] CR3 filter.
+    ///
+    UINT32  CR3:1;
+    ///
+    /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.
+    ///
+    UINT32  ToPA:1;
+    ///
+    /// [Bit 9] MTCEn.
+    ///
+    UINT32  MTCEn:1;
+    ///
+    /// [Bit 10] TSCEn.
+    ///
+    UINT32  TSCEn:1;
+    ///
+    /// [Bit 11] DisRETC.
+    ///
+    UINT32  DisRETC:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 13] BranchEn.
+    ///
+    UINT32  BranchEn:1;
+    ///
+    /// [Bits 17:14] MTCFreq.
+    ///
+    UINT32  MTCFreq:4;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 22:19] CYCThresh.
+    ///
+    UINT32  CYCThresh:4;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bits 27:24] PSBFreq.
+    ///
+    UINT32  PSBFreq:4;
+    UINT32  Reserved5:4;
+    ///
+    /// [Bits 35:32] ADDR0_CFG.
+    ///
+    UINT32  ADDR0_CFG:4;
+    ///
+    /// [Bits 39:36] ADDR1_CFG.
+    ///
+    UINT32  ADDR1_CFG:4;
+    UINT32  Reserved6:24;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
+  "RAPL Interfaces.".
+
+  @param  ECX  MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_GOLDMONT_RAPL_POWER_UNIT             0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Power Units. Power related information (in Watts) is in
+    /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits
+    /// 3:0. Default value is 1000b, indicating power unit is in 3.9
+    /// milliWatts increment.
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Energy Status Units. Energy related information (in
+    /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned
+    /// integer represented by bits 12:8. Default value is 01110b, indicating
+    /// energy unit is in 61 microJoules.
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Time Unit. Time related information (in seconds) is in
+    /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits
+    /// 19:16. Default value is 1010b, indicating power unit is in 0.977
+    /// millisecond.
+    ///
+    UINT32  TimeUnit:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. Package C3 Interrupt Response Limit (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates.
+
+  @param  ECX  MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKGC3_IRTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
+**/
+#define MSR_GOLDMONT_PKGC3_IRTL                  0x0000060A
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C3 state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKGC3_IRTL_REGISTER;
+
+
+/**
+  Package. Package C6/C7S Interrupt Response Limit 1 (R/W)  This MSR defines
+  the interrupt response time limit used by the processor to manage transition
+  to package C6 or C7S state. Note: C-state values are processor specific
+  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+  CStates.
+
+  @param  ECX  MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKGC_IRTL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
+**/
+#define MSR_GOLDMONT_PKGC_IRTL1                  0x0000060B
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C6 or C7S state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKGC_IRTL1_REGISTER;
+
+
+/**
+  Package. Package C7 Interrupt Response Limit 2 (R/W)  This MSR defines the
+  interrupt response time limit used by the processor to manage transition to
+  package C7 state. Note: C-state values are processor specific C-state code
+  names, unrelated to MWAIT extension C-state parameters or ACPI CStates.
+
+  @param  ECX  MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKGC_IRTL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
+**/
+#define MSR_GOLDMONT_PKGC_IRTL2                  0x0000060C
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C7 state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKGC_IRTL2_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C2 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C2_RESIDENCY            0x0000060D
+
+
+/**
+  Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
+  RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_PKG_POWER_LIMIT             0x00000610
+
+
+/**
+  Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PKG_ENERGY_STATUS           0x00000611
+
+
+/**
+  Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PKG_PERF_STATUS             0x00000613
+
+
+/**
+  Package. PKG RAPL Parameters (R/W).
+
+  @param  ECX  MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKG_POWER_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
+**/
+#define MSR_GOLDMONT_PKG_POWER_INFO              0x00000614
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] Thermal Spec Power (R/W)  See Section 14.9.3, "Package
+    /// RAPL Domain.".
+    ///
+    UINT32  ThermalSpecPower:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 30:16] Minimum Power (R/W)  See Section 14.9.3, "Package RAPL
+    /// Domain.".
+    ///
+    UINT32  MinimumPower:15;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bits 46:32] Maximum Power (R/W)  See Section 14.9.3, "Package RAPL
+    /// Domain.".
+    ///
+    UINT32  MaximumPower:15;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 54:48] Maximum Time Window (R/W)  Specified by 2^Y * (1.0 +
+    /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value
+    /// represented. by bits 52:48, "Z" is an unsigned integer represented by
+    /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of
+    /// MSR_RAPL_POWER_UNIT.
+    ///
+    UINT32  MaximumTimeWindow:7;
+    UINT32  Reserved4:9;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_POWER_LIMIT            0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_ENERGY_STATUS          0x00000619
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_PERF_STATUS            0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_POWER_INFO             0x0000061C
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,.
+  Package C10 Residency Counter. (R/O) Value since last reset that the entire
+  SOC is in an S0i3 state. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C10_RESIDENCY           0x00000632
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PP0_ENERGY_STATUS           0x00000639
+
+
+/**
+  Package. PP1 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PP1_ENERGY_STATUS           0x00000641
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);
+  AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO      0x0000064C
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
+    /// field.
+    ///
+    UINT32  MAX_NON_TURBO_RATIO:8;
+    UINT32  Reserved1:23;
+    ///
+    /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
+    /// content of this register is locked until a reset.
+    ///
+    UINT32  TURBO_ACTIVATION_RATIO_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS     0x0000064F
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
+    /// reduced below the operating system request due to assertion of
+    /// external PROCHOT.
+    ///
+    UINT32  PROCHOTStatus:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    ///
+    /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL1.
+    ///
+    UINT32  PL1Status:1;
+    ///
+    /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL2.
+    ///
+    UINT32  PL2Status:1;
+    UINT32  Reserved1:5;
+    ///
+    /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
+    /// below the operating system request due to domain-level power limiting.
+    ///
+    UINT32  PowerLimitingStatus:1;
+    ///
+    /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    ///
+    /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced
+    /// below the operating system request due to multi-core turbo limits.
+    ///
+    UINT32  MaxTurboLimitStatus:1;
+    ///
+    /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    ///
+    /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
+    /// is reduced below the operating system request due to Turbo transition
+    /// attenuation. This prevents performance degradation due to frequent
+    /// operating ratio changes.
+    ///
+    UINT32  TurboTransitionAttenuationStatus:1;
+    ///
+    /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency
+    /// is reduced below the maximum efficiency frequency.
+    ///
+    UINT32  MaximumEfficiencyFrequencyStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    ///
+    /// [Bit 18] Package-Level PL1 Power Limiting Log  When set, indicates
+    /// that the Package Level PL1 Power Limiting Status bit has asserted
+    /// since the log bit was last cleared. This log bit will remain set until
+    /// cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that
+    /// the Package Level PL2 Power Limiting Status bit has asserted since the
+    /// log bit was last cleared. This log bit will remain set until cleared
+    /// by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    UINT32  Reserved3:5;
+    ///
+    /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
+    /// Power Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CorePowerLimitingLog:1;
+    ///
+    /// [Bit 26] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    ///
+    /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 28] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    ///
+    /// [Bit 30] Maximum Efficiency Frequency Log  When set, indicates that
+    /// the Maximum Efficiency Frequency Status bit has asserted since the log
+    /// bit was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  MaximumEfficiencyFrequencyLog:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch
+  record registers on the last branch record stack. The From_IP part of the
+  stack contains pointers to the source instruction . See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.6 and record format in Section
+  17.4.8.1.
+
+  @param  ECX  MSR_GOLDMONT_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);
+  AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
+  @{
+**/
+#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP        0x00000680
+#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP        0x00000681
+#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP        0x00000682
+#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP        0x00000683
+#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP        0x00000684
+#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP        0x00000685
+#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP        0x00000686
+#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP        0x00000687
+#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP        0x00000688
+#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP        0x00000689
+#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP       0x0000068A
+#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP       0x0000068B
+#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP       0x0000068C
+#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP       0x0000068D
+#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP       0x0000068E
+#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP       0x0000068F
+#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP       0x00000690
+#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP       0x00000691
+#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP       0x00000692
+#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP       0x00000693
+#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP       0x00000694
+#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP       0x00000695
+#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP       0x00000696
+#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP       0x00000697
+#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP       0x00000698
+#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP       0x00000699
+#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP       0x0000069A
+#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP       0x0000069B
+#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP       0x0000069C
+#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP       0x0000069D
+#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP       0x0000069E
+#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP       0x0000069F
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP
+  to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] From Linear Address (R/W).
+    ///
+    UINT32  FromLinearAddress:32;
+    ///
+    /// [Bit 47:32] From Linear Address (R/W).
+    ///
+    UINT32  FromLinearAddressHi:16;
+    ///
+    /// [Bits 62:48] Signed extension of bits 47:0.
+    ///
+    UINT32  SignedExtension:15;
+    ///
+    /// [Bit 63] Mispred.
+    ///
+    UINT32  Mispred:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;
+
+
+/**
+  Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record
+  registers on the last branch record stack. The To_IP part of the stack
+  contains pointers to the Destination instruction and elapsed cycles from
+  last LBR update. See also: - Section 17.6.
+
+  @param  ECX  MSR_GOLDMONT_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
+  @{
+**/
+#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP          0x000006C0
+#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP          0x000006C1
+#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP          0x000006C2
+#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP          0x000006C3
+#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP          0x000006C4
+#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP          0x000006C5
+#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP          0x000006C6
+#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP          0x000006C7
+#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP          0x000006C8
+#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP          0x000006C9
+#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP         0x000006CA
+#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP         0x000006CB
+#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP         0x000006CC
+#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP         0x000006CD
+#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP         0x000006CE
+#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP         0x000006CF
+#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP         0x000006D0
+#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP         0x000006D1
+#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP         0x000006D2
+#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP         0x000006D3
+#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP         0x000006D4
+#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP         0x000006D5
+#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP         0x000006D6
+#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP         0x000006D7
+#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP         0x000006D8
+#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP         0x000006D9
+#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP         0x000006DA
+#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP         0x000006DB
+#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP         0x000006DC
+#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP         0x000006DD
+#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP         0x000006DE
+#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP         0x000006DF
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to
+  #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Target Linear Address (R/W).
+    ///
+    UINT32  TargetLinearAddress:32;
+    ///
+    /// [Bit 47:32] Target Linear Address (R/W).
+    ///
+    UINT32  TargetLinearAddressHi:16;
+    ///
+    /// [Bits 63:48] Elapsed cycles from last update to the LBR.
+    ///
+    UINT32  ElapsedCycles:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;
+
+
+/**
+  Core. Resource Association Register (R/W).
+
+  @param  ECX  MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PQR_ASSOC              0x00000C8F
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    ///
+    /// [Bits 33:32] COS (R/W).
+    ///
+    UINT32  COS:2;
+    UINT32  Reserved2:30;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+  Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
+  ECX=1):EDX.COS_MAX[15:0] >=n.
+
+  @param  ECX  MSR_GOLDMONT_IA32_L2_QOS_MASK_n
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.
+        MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.
+        MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.
+  @{
+**/
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0          0x00000D10
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1          0x00000D11
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2          0x00000D12
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to
+  #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
+    ///
+    UINT32  CBM:8;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;
+
+
+/**
+  Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,
+  ECX=1):EDX.COS_MAX[15:0] >=3.
+
+  @param  ECX  MSR_GOLDMONT_IA32_L2_QOS_MASK_3
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.
+**/
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3          0x00000D13
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
+    ///
+    UINT32  CBM:20;
+    UINT32  Reserved1:12;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;
+
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h b/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h
new file mode 100644
index 000000000000..95e7de91dfed
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h
@@ -0,0 +1,266 @@
+/** @file
+  MSR Definitions for Intel Atom processors based on the Goldmont Plus microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __GOLDMONT_PLUS_MSR_H__
+#define __GOLDMONT_PLUS_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel Atom processors based on the Goldmont plus microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x7A    \
+    )                       \
+   )
+
+/**
+  Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
+  Sampling (PEBS).".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_PEBS_ENABLE            0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC0.
+    ///
+    UINT32  Fix_Me_1:1;
+    ///
+    /// [Bit 1] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC1.
+    ///
+    UINT32  Fix_Me_2:1;
+    ///
+    /// [Bit 2] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC2.
+    ///
+    UINT32  Fix_Me_3:1;
+    ///
+    /// [Bit 3] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC3.
+    ///
+    UINT32  Fix_Me_4:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
+    ///
+    UINT32  Fix_Me_5:1;
+    ///
+    /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
+    ///
+    UINT32  Fix_Me_6:1;
+    ///
+    /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
+    ///
+    UINT32  Fix_Me_7:1;
+    UINT32  Reserved2:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
+  the first entry of the 32-entry LBR stack. The From_IP part of the stack
+  contains pointers to the source instruction. See also: -  Last Branch Record
+  Stack TOS at 1C9H. -  Section 17.7, "Last Branch, Call Stack, Interrupt, and
+  .. Exception Recording for Processors based on Goldmont Plus
+  Microarchitecture.".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP    0x00000680
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP    0x00000681
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP    0x00000682
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP    0x00000683
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP    0x00000684
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP    0x00000685
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP    0x00000686
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP    0x00000687
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP    0x00000688
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP    0x00000689
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP   0x0000068A
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP   0x0000068B
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP   0x0000068C
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP   0x0000068D
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP   0x0000068E
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP   0x0000068F
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP   0x00000690
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP   0x00000691
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP   0x00000692
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP   0x00000693
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP   0x00000694
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP   0x00000695
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP   0x00000696
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP   0x00000697
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP   0x00000698
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP   0x00000699
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP   0x0000069A
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP   0x0000069B
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP   0x0000069C
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP   0x0000069D
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP   0x0000069E
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP   0x0000069F
+
+/**
+  Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
+  the first entry of the 32-entry LBR stack. The To_IP part of the stack
+  contains pointers to the Destination instruction. See also: - Section 17.7,
+  "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
+  based on Goldmont Plus Microarchitecture.".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP      0x000006C0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP      0x000006C1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP      0x000006C2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP      0x000006C3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP      0x000006C4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP      0x000006C5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP      0x000006C6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP      0x000006C7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP      0x000006C8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP      0x000006C9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP     0x000006CA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP     0x000006CB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP     0x000006CC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP     0x000006CD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP     0x000006CE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP     0x000006CF
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP     0x000006D0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP     0x000006D1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP     0x000006D2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP     0x000006D3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP     0x000006D4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP     0x000006D5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP     0x000006D6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP     0x000006D7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP     0x000006D8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP     0x000006D9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP     0x000006DA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP     0x000006DB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP     0x000006DC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP     0x000006DD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP     0x000006DE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP     0x000006DF
+
+
+/**
+  Core. Last Branch Record N Additional Information (R/W) One of the three
+  MSRs that make up the first entry of the 32-entry LBR stack. This part of
+  the stack contains flag and elapsed cycle information. See also: -  Last
+  Branch Record Stack TOS at 1C9H. -  Section 17.9.1, "LBR Stack.".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0      0x00000DC0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1      0x00000DC1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2      0x00000DC2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3      0x00000DC3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4      0x00000DC4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5      0x00000DC5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6      0x00000DC6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7      0x00000DC7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8      0x00000DC8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9      0x00000DC9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10     0x00000DCA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11     0x00000DCB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12     0x00000DCC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13     0x00000DCD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14     0x00000DCE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15     0x00000DCF
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16     0x00000DD0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17     0x00000DD1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18     0x00000DD2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19     0x00000DD3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20     0x00000DD4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21     0x00000DD5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22     0x00000DD6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23     0x00000DD7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24     0x00000DD8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25     0x00000DD9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26     0x00000DDA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27     0x00000DDB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28     0x00000DDC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29     0x00000DDD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30     0x00000DDE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31     0x00000DDF
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h b/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h
new file mode 100644
index 000000000000..4fa6000f7066
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h
@@ -0,0 +1,6400 @@
+/** @file
+  MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __HASWELL_E_MSR_H__
+#define __HASWELL_E_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Haswell-E microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3F    \
+    )                       \
+   )
+
+/**
+  Package. Configured State of Enabled Processor Core Count and Logical
+  Processor Count (RO) -  After a Power-On RESET, enumerates factory
+  configuration of the number of processor cores and logical processors in the
+  physical package. -  Following the sequence of (i) BIOS modified a
+  Configuration Mask which selects a subset of processor cores to be active
+  post RESET and (ii) a RESET event after the modification, enumerates the
+  current configuration of enabled processor core count and logical processor
+  count in the physical package.
+
+  @param  ECX  MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);
+  @endcode
+  @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
+**/
+#define MSR_HASWELL_E_CORE_THREAD_COUNT          0x00000035
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are
+    /// currently enabled (by either factory configuration or BIOS
+    /// configuration) in the physical package.
+    ///
+    UINT32  Core_Count:16;
+    ///
+    /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
+    /// are currently enabled (by either factory configuration or BIOS
+    /// configuration) in the physical package.
+    ///
+    UINT32  Thread_Count:16;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;
+
+
+/**
+  Thread. A Hardware Assigned ID for the Logical Processor (RO).
+
+  @param  ECX  MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_THREAD_ID_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);
+  @endcode
+  @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
+**/
+#define MSR_HASWELL_E_THREAD_ID_INFO             0x00000053
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific
+    /// numerical. value physically assigned to each logical processor. This
+    /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
+    /// a physical package.
+    ///
+    UINT32  Logical_Processor_ID:8;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
+
+  @param  ECX  MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL     0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
+    /// 011b: C6 (retention) 111b: No Package C state limits. All C states
+    /// supported by the processor are available.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    ///
+    /// [Bit 29] Package C State Demotion Enable (R/W).
+    ///
+    UINT32  CStateDemotion:1;
+    ///
+    /// [Bit 30] Package C State UnDemotion Enable (R/W).
+    ///
+    UINT32  CStateUndemotion:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Thread. Global Machine Check Capability (R/O).
+
+  @param  ECX  MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_IA32_MCG_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
+  @endcode
+  @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
+**/
+#define MSR_HASWELL_E_IA32_MCG_CAP               0x00000179
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Count.
+    ///
+    UINT32  Count:8;
+    ///
+    /// [Bit 8] MCG_CTL_P.
+    ///
+    UINT32  MCG_CTL_P:1;
+    ///
+    /// [Bit 9] MCG_EXT_P.
+    ///
+    UINT32  MCG_EXT_P:1;
+    ///
+    /// [Bit 10] MCP_CMCI_P.
+    ///
+    UINT32  MCP_CMCI_P:1;
+    ///
+    /// [Bit 11] MCG_TES_P.
+    ///
+    UINT32  MCG_TES_P:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 23:16] MCG_EXT_CNT.
+    ///
+    UINT32  MCG_EXT_CNT:8;
+    ///
+    /// [Bit 24] MCG_SER_P.
+    ///
+    UINT32  MCG_SER_P:1;
+    ///
+    /// [Bit 25] MCG_EM_P.
+    ///
+    UINT32  MCG_EM_P:1;
+    ///
+    /// [Bit 26] MCG_ELOG_P.
+    ///
+    UINT32  MCG_ELOG_P:1;
+    UINT32  Reserved2:5;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;
+
+
+/**
+  THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_HASWELL_E_SMM_MCA_CAP                0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and a host-space interface
+    /// available to SMM handler.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and a host-space interface
+    /// available to SMM handler.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Package. MC Bank Error Configuration (R/W).
+
+  @param  ECX  MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_ERROR_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
+**/
+#define MSR_HASWELL_E_ERROR_CONTROL              0x0000017F
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank
+    /// to log additional info in bits 36:32.
+    ///
+    UINT32  MemErrorLogEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT          0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
+    /// limit of 5 core active.
+    ///
+    UINT32  Maximum5C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
+    /// limit of 6 core active.
+    ///
+    UINT32  Maximum6C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
+    /// limit of 7 core active.
+    ///
+    UINT32  Maximum7C:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
+    /// limit of 8 core active.
+    ///
+    UINT32  Maximum8C:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
+  @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
+**/
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1         0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
+    /// limit of 9 core active.
+    ///
+    UINT32  Maximum9C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
+    /// limit of 10 core active.
+    ///
+    UINT32  Maximum10C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
+    /// limit of 11 core active.
+    ///
+    UINT32  Maximum11C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
+    /// limit of 12 core active.
+    ///
+    UINT32  Maximum12C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
+    /// limit of 13 core active.
+    ///
+    UINT32  Maximum13C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
+    /// limit of 14 core active.
+    ///
+    UINT32  Maximum14C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
+    /// limit of 15 core active.
+    ///
+    UINT32  Maximum15C:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
+    /// limit of 16 core active.
+    ///
+    UINT32  Maximum16C:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
+  @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
+**/
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2         0x000001AF
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
+    /// limit of 17 core active.
+    ///
+    UINT32  Maximum17C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
+    /// limit of 18 core active.
+    ///
+    UINT32  Maximum18C:8;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:31;
+    ///
+    /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
+    /// the processor uses override configuration specified in
+    /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
+    /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
+    /// configuration (Default).
+    ///
+    UINT32  TurboRatioLimitConfigurationSemaphore:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O).
+
+  @param  ECX  MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_HASWELL_E_RAPL_POWER_UNIT            0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Package. Energy Status Units Energy related information
+    /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+    /// micro-joules).
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+    /// Interfaces.".
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_HASWELL_E_DRAM_POWER_LIMIT           0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  Energy Consumed by DRAM devices.
+
+  @param  ECX  MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_DRAM_ENERGY_STATUS         0x00000619
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
+    /// to enable DRAM RAPL mode 0 (Direct VR).
+    ///
+    UINT32  Energy:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_DRAM_PERF_STATUS           0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_HASWELL_E_DRAM_POWER_INFO            0x0000061C
+
+
+/**
+  Package. Configuration of PCIE PLL Relative to BCLK(R/W).
+
+  @param  ECX  MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
+**/
+#define MSR_HASWELL_E_PCIE_PLL_RATIO             0x0000061E
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz
+    /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use
+    /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
+    /// operation.
+    ///
+    UINT32  PCIERatio:2;
+    ///
+    /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
+    /// PCIE Ratio.
+    ///
+    UINT32  LPLLSelect:1;
+    ///
+    /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
+    /// before re-locking Gen2/Gen3 PLLs.
+    ///
+    UINT32  LONGRESET:1;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;
+
+
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT      0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  MAX_RATIO:7;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  MIN_RATIO:7;
+    UINT32  Reserved2:17;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+  Package. Reserved (R/O) Reads return 0.
+
+  @param  ECX  MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS          0x00000639
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS    0x00000690
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
+    /// reduced below the operating system request due to assertion of
+    /// external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    ///
+    /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
+    /// reduced below the operating system request due to PBM limit.
+    ///
+    UINT32  PowerBudgetManagementStatus:1;
+    ///
+    /// [Bit 3] Platform Configuration Services Status (R0) When set,
+    /// frequency is reduced below the operating system request due to PCS
+    /// limit.
+    ///
+    UINT32  PlatformConfigurationServicesStatus:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
+    /// When set, frequency is reduced below the operating system request
+    /// because the processor has detected that utilization is low.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
+    /// below the operating system request due to Multi-Core Turbo limits.
+    ///
+    UINT32  MultiCoreTurboStatus:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
+    /// below max non-turbo P1.
+    ///
+    UINT32  FrequencyP1Status:1;
+    ///
+    /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
+    /// set, frequency is reduced below max n-core turbo frequency.
+    ///
+    UINT32  TurboFrequencyLimitingStatus:1;
+    ///
+    /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
+    /// reduced below the operating system request.
+    ///
+    UINT32  FrequencyLimitingStatus:1;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    ///
+    /// [Bit 18] Power Budget Management Log  When set, indicates that the PBM
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  PowerBudgetManagementLog:1;
+    ///
+    /// [Bit 19] Platform Configuration Services Log  When set, indicates that
+    /// the PCS Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  PlatformConfigurationServicesLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the AUBFC Status bit has asserted since the log bit was
+    /// last cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    UINT32  Reserved7:1;
+    ///
+    /// [Bit 26] Multi-Core Turbo Log  When set, indicates that the Multi-Core
+    /// Turbo Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MultiCoreTurboLog:1;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
+    /// Frequency P1 Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CoreFrequencyP1Log:1;
+    ///
+    /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
+    /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  TurboFrequencyLimitingLog:1;
+    ///
+    /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
+    /// Frequency Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CoreFrequencyLimitingLog:1;
+    UINT32  Reserved9:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
+  ECX=0):EBX.RDT-M[bit 12] = 1.
+
+  @param  ECX  MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
+  AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
+**/
+#define MSR_HASWELL_E_IA32_QM_EVTSEL             0x00000C8D
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
+    /// occupancy monitoring all other encoding reserved..
+    ///
+    UINT32  EventID:8;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bits 41:32] RMID (RW).
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved2:22;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;
+
+
+/**
+  THREAD. Resource Association Register (R/W)..
+
+  @param  ECX  MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
+  AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
+**/
+#define MSR_HASWELL_E_IA32_PQR_ASSOC             0x00000C8F
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] RMID.
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved1:22;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+  Package. Uncore perfmon per-socket global control.
+
+  @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
+**/
+#define MSR_HASWELL_E_PMON_GLOBAL_CTL            0x00000700
+
+
+/**
+  Package. Uncore perfmon per-socket global status.
+
+  @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_PMON_GLOBAL_STATUS         0x00000701
+
+
+/**
+  Package. Uncore perfmon per-socket global configuration.
+
+  @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
+  AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
+**/
+#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG         0x00000702
+
+
+/**
+  Package. Uncore U-box UCLK fixed counter control.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL      0x00000703
+
+
+/**
+  Package. Uncore U-box UCLK fixed counter.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR      0x00000704
+
+
+/**
+  Package. Uncore U-box perfmon event select for U-box counter 0.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_EVNTSEL0            0x00000705
+
+
+/**
+  Package. Uncore U-box perfmon event select for U-box counter 1.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_EVNTSEL1            0x00000706
+
+
+/**
+  Package. Uncore U-box perfmon U-box wide status.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_BOX_STATUS          0x00000708
+
+
+/**
+  Package. Uncore U-box perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_CTR0                0x00000709
+
+
+/**
+  Package. Uncore U-box perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_CTR1                0x0000070A
+
+
+/**
+  Package. Uncore PCU perfmon for PCU-box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_BOX_CTL           0x00000710
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 0.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0          0x00000711
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 1.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1          0x00000712
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 2.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2          0x00000713
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 3.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3          0x00000714
+
+
+/**
+  Package. Uncore PCU perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER        0x00000715
+
+
+/**
+  Package. Uncore PCU perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS        0x00000716
+
+
+/**
+  Package. Uncore PCU perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_CTR0              0x00000717
+
+
+/**
+  Package. Uncore PCU perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_CTR1              0x00000718
+
+
+/**
+  Package. Uncore PCU perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_CTR2              0x00000719
+
+
+/**
+  Package. Uncore PCU perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_CTR3              0x0000071A
+
+
+/**
+  Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_BOX_CTL            0x00000720
+
+
+/**
+  Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL0           0x00000721
+
+
+/**
+  Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL1           0x00000722
+
+
+/**
+  Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL2           0x00000723
+
+
+/**
+  Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL3           0x00000724
+
+
+/**
+  Package. Uncore SBo 0 perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_BOX_FILTER         0x00000725
+
+
+/**
+  Package. Uncore SBo 0 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_CTR0               0x00000726
+
+
+/**
+  Package. Uncore SBo 0 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_CTR1               0x00000727
+
+
+/**
+  Package. Uncore SBo 0 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_CTR2               0x00000728
+
+
+/**
+  Package. Uncore SBo 0 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_CTR3               0x00000729
+
+
+/**
+  Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_BOX_CTL            0x0000072A
+
+
+/**
+  Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL0           0x0000072B
+
+
+/**
+  Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL1           0x0000072C
+
+
+/**
+  Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL2           0x0000072D
+
+
+/**
+  Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL3           0x0000072E
+
+
+/**
+  Package. Uncore SBo 1 perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_BOX_FILTER         0x0000072F
+
+
+/**
+  Package. Uncore SBo 1 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_CTR0               0x00000730
+
+
+/**
+  Package. Uncore SBo 1 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_CTR1               0x00000731
+
+
+/**
+  Package. Uncore SBo 1 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_CTR2               0x00000732
+
+
+/**
+  Package. Uncore SBo 1 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_CTR3               0x00000733
+
+
+/**
+  Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_BOX_CTL            0x00000734
+
+
+/**
+  Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL0           0x00000735
+
+
+/**
+  Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL1           0x00000736
+
+
+/**
+  Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL2           0x00000737
+
+
+/**
+  Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL3           0x00000738
+
+
+/**
+  Package. Uncore SBo 2 perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_BOX_FILTER         0x00000739
+
+
+/**
+  Package. Uncore SBo 2 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_CTR0               0x0000073A
+
+
+/**
+  Package. Uncore SBo 2 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_CTR1               0x0000073B
+
+
+/**
+  Package. Uncore SBo 2 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_CTR2               0x0000073C
+
+
+/**
+  Package. Uncore SBo 2 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_CTR3               0x0000073D
+
+
+/**
+  Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_BOX_CTL            0x0000073E
+
+
+/**
+  Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL0           0x0000073F
+
+
+/**
+  Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL1           0x00000740
+
+
+/**
+  Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL2           0x00000741
+
+
+/**
+  Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL3           0x00000742
+
+
+/**
+  Package. Uncore SBo 3 perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_BOX_FILTER         0x00000743
+
+
+/**
+  Package. Uncore SBo 3 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_CTR0               0x00000744
+
+
+/**
+  Package. Uncore SBo 3 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_CTR1               0x00000745
+
+
+/**
+  Package. Uncore SBo 3 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_CTR2               0x00000746
+
+
+/**
+  Package. Uncore SBo 3 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_CTR3               0x00000747
+
+
+/**
+  Package. Uncore C-box 0 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_BOX_CTL            0x00000E00
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL0           0x00000E01
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL1           0x00000E02
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL2           0x00000E03
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL3           0x00000E04
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0        0x00000E05
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide filter 1.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1        0x00000E06
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_BOX_STATUS         0x00000E07
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_CTR0               0x00000E08
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_CTR1               0x00000E09
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_CTR2               0x00000E0A
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_CTR3               0x00000E0B
+
+
+/**
+  Package. Uncore C-box 1 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_BOX_CTL            0x00000E10
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL0           0x00000E11
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL1           0x00000E12
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL2           0x00000E13
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL3           0x00000E14
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0        0x00000E15
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1        0x00000E16
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_BOX_STATUS         0x00000E17
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_CTR0               0x00000E18
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_CTR1               0x00000E19
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_CTR2               0x00000E1A
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_CTR3               0x00000E1B
+
+
+/**
+  Package. Uncore C-box 2 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_BOX_CTL            0x00000E20
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL0           0x00000E21
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL1           0x00000E22
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL2           0x00000E23
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL3           0x00000E24
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0        0x00000E25
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1        0x00000E26
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_BOX_STATUS         0x00000E27
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_CTR0               0x00000E28
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_CTR1               0x00000E29
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_CTR2               0x00000E2A
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_CTR3               0x00000E2B
+
+
+/**
+  Package. Uncore C-box 3 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_BOX_CTL            0x00000E30
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL0           0x00000E31
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL1           0x00000E32
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL2           0x00000E33
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL3           0x00000E34
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0        0x00000E35
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1        0x00000E36
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_BOX_STATUS         0x00000E37
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_CTR0               0x00000E38
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_CTR1               0x00000E39
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_CTR2               0x00000E3A
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_CTR3               0x00000E3B
+
+
+/**
+  Package. Uncore C-box 4 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_BOX_CTL            0x00000E40
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL0           0x00000E41
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL1           0x00000E42
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL2           0x00000E43
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL3           0x00000E44
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0        0x00000E45
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1        0x00000E46
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_BOX_STATUS         0x00000E47
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_CTR0               0x00000E48
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_CTR1               0x00000E49
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_CTR2               0x00000E4A
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_CTR3               0x00000E4B
+
+
+/**
+  Package. Uncore C-box 5 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_BOX_CTL            0x00000E50
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL0           0x00000E51
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL1           0x00000E52
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL2           0x00000E53
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL3           0x00000E54
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0        0x00000E55
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1        0x00000E56
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_BOX_STATUS         0x00000E57
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_CTR0               0x00000E58
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_CTR1               0x00000E59
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_CTR2               0x00000E5A
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_CTR3               0x00000E5B
+
+
+/**
+  Package. Uncore C-box 6 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_BOX_CTL            0x00000E60
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL0           0x00000E61
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL1           0x00000E62
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL2           0x00000E63
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL3           0x00000E64
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0        0x00000E65
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1        0x00000E66
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_BOX_STATUS         0x00000E67
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_CTR0               0x00000E68
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_CTR1               0x00000E69
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_CTR2               0x00000E6A
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_CTR3               0x00000E6B
+
+
+/**
+  Package. Uncore C-box 7 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_BOX_CTL            0x00000E70
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL0           0x00000E71
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL1           0x00000E72
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL2           0x00000E73
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL3           0x00000E74
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0        0x00000E75
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1        0x00000E76
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_BOX_STATUS         0x00000E77
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_CTR0               0x00000E78
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_CTR1               0x00000E79
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_CTR2               0x00000E7A
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_CTR3               0x00000E7B
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_BOX_CTL            0x00000E80
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL0           0x00000E81
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL1           0x00000E82
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL2           0x00000E83
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL3           0x00000E84
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0        0x00000E85
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1        0x00000E86
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_BOX_STATUS         0x00000E87
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_CTR0               0x00000E88
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_CTR1               0x00000E89
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_CTR2               0x00000E8A
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_CTR3               0x00000E8B
+
+
+/**
+  Package. Uncore C-box 9 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_BOX_CTL            0x00000E90
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL0           0x00000E91
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL1           0x00000E92
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL2           0x00000E93
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL3           0x00000E94
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0        0x00000E95
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1        0x00000E96
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_BOX_STATUS         0x00000E97
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_CTR0               0x00000E98
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_CTR1               0x00000E99
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_CTR2               0x00000E9A
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_CTR3               0x00000E9B
+
+
+/**
+  Package. Uncore C-box 10 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_BOX_CTL           0x00000EA0
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL0          0x00000EA1
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL1          0x00000EA2
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL2          0x00000EA3
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL3          0x00000EA4
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0       0x00000EA5
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1       0x00000EA6
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_BOX_STATUS        0x00000EA7
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_CTR0              0x00000EA8
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_CTR1              0x00000EA9
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_CTR2              0x00000EAA
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_CTR3              0x00000EAB
+
+
+/**
+  Package. Uncore C-box 11 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_BOX_CTL           0x00000EB0
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL0          0x00000EB1
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL1          0x00000EB2
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL2          0x00000EB3
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL3          0x00000EB4
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0       0x00000EB5
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1       0x00000EB6
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_BOX_STATUS        0x00000EB7
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_CTR0              0x00000EB8
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_CTR1              0x00000EB9
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_CTR2              0x00000EBA
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_CTR3              0x00000EBB
+
+
+/**
+  Package. Uncore C-box 12 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_BOX_CTL           0x00000EC0
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL0          0x00000EC1
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL1          0x00000EC2
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL2          0x00000EC3
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL3          0x00000EC4
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0       0x00000EC5
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1       0x00000EC6
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_BOX_STATUS        0x00000EC7
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_CTR0              0x00000EC8
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_CTR1              0x00000EC9
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_CTR2              0x00000ECA
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_CTR3              0x00000ECB
+
+
+/**
+  Package. Uncore C-box 13 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_BOX_CTL           0x00000ED0
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL0          0x00000ED1
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL1          0x00000ED2
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL2          0x00000ED3
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL3          0x00000ED4
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0       0x00000ED5
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1       0x00000ED6
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_BOX_STATUS        0x00000ED7
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_CTR0              0x00000ED8
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_CTR1              0x00000ED9
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_CTR2              0x00000EDA
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_CTR3              0x00000EDB
+
+
+/**
+  Package. Uncore C-box 14 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_BOX_CTL           0x00000EE0
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL0          0x00000EE1
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL1          0x00000EE2
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL2          0x00000EE3
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL3          0x00000EE4
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER        0x00000EE5
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1       0x00000EE6
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_BOX_STATUS        0x00000EE7
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_CTR0              0x00000EE8
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_CTR1              0x00000EE9
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_CTR2              0x00000EEA
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_CTR3              0x00000EEB
+
+
+/**
+  Package. Uncore C-box 15 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_BOX_CTL           0x00000EF0
+
+
+/**
+  Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL0          0x00000EF1
+
+
+/**
+  Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL1          0x00000EF2
+
+
+/**
+  Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL2          0x00000EF3
+
+
+/**
+  Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL3          0x00000EF4
+
+
+/**
+  Package. Uncore C-box 15 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0       0x00000EF5
+
+
+/**
+  Package. Uncore C-box 15 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1       0x00000EF6
+
+
+/**
+  Package. Uncore C-box 15 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_BOX_STATUS        0x00000EF7
+
+
+/**
+  Package. Uncore C-box 15 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_CTR0              0x00000EF8
+
+
+/**
+  Package. Uncore C-box 15 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_CTR1              0x00000EF9
+
+
+/**
+  Package. Uncore C-box 15 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_CTR2              0x00000EFA
+
+
+/**
+  Package. Uncore C-box 15 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_CTR3              0x00000EFB
+
+
+/**
+  Package. Uncore C-box 16 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_BOX_CTL           0x00000F00
+
+
+/**
+  Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL0          0x00000F01
+
+
+/**
+  Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL1          0x00000F02
+
+
+/**
+  Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL2          0x00000F03
+
+
+/**
+  Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL3          0x00000F04
+
+
+/**
+  Package. Uncore C-box 16 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0       0x00000F05
+
+
+/**
+  Package. Uncore C-box 16 perfmon box wide filter 1.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1       0x00000F06
+
+
+/**
+  Package. Uncore C-box 16 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_BOX_STATUS        0x00000F07
+
+
+/**
+  Package. Uncore C-box 16 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_CTR0              0x00000F08
+
+
+/**
+  Package. Uncore C-box 16 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_CTR1              0x00000F09
+
+
+/**
+  Package. Uncore C-box 16 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_CTR2              0x00000F0A
+
+
+/**
+  Package. Uncore C-box 16 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_CTR3              0x00000E0B
+
+
+/**
+  Package. Uncore C-box 17 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_BOX_CTL           0x00000F10
+
+
+/**
+  Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL0          0x00000F11
+
+
+/**
+  Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL1          0x00000F12
+
+
+/**
+  Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL2          0x00000F13
+
+
+/**
+  Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL3          0x00000F14
+
+
+/**
+  Package. Uncore C-box 17 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0       0x00000F15
+
+
+/**
+  Package. Uncore C-box 17 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1       0x00000F16
+
+/**
+  Package. Uncore C-box 17 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_BOX_STATUS        0x00000F17
+
+
+/**
+  Package. Uncore C-box 17 perfmon counter n.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
+  @{
+**/
+#define MSR_HASWELL_E_C17_PMON_CTR0              0x00000F18
+#define MSR_HASWELL_E_C17_PMON_CTR1              0x00000F19
+#define MSR_HASWELL_E_C17_PMON_CTR2              0x00000F1A
+#define MSR_HASWELL_E_C17_PMON_CTR3              0x00000F1B
+/// @}
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h b/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h
new file mode 100644
index 000000000000..da5c2e497c3d
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h
@@ -0,0 +1,2631 @@
+/** @file
+  MSR Definitions for Intel processors based on the Haswell microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __HASWELL_MSR_H__
+#define __HASWELL_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Haswell microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3C || \
+    DisplayModel == 0x45 || \
+    DisplayModel == 0x46    \
+    )                       \
+   )
+
+/**
+  Package.
+
+  @param  ECX  MSR_HASWELL_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_HASWELL_PLATFORM_INFO                0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
+    /// indicates that LPM is supported, and when set to 0, indicates LPM is
+    /// not supported.
+    ///
+    UINT32  LowPowerModeSupport:1;
+    ///
+    /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
+    /// TDP level available. 01: One additional TDP level available. 02: Two
+    /// additional TDP level available. 11: Reserved.
+    ///
+    UINT32  ConfigTDPLevels:2;
+    UINT32  Reserved4:5;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    ///
+    /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
+    /// minimum supported operating ratio in units of 100 MHz.
+    ///
+    UINT32  MinimumOperatingRatio:8;
+    UINT32  Reserved5:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Thread. Performance Event Select for Counter n (R/W) Supports all fields
+  described inTable 2-2 and the fields below.
+
+  @param  ECX  MSR_HASWELL_IA32_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_IA32_PERFEVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
+        MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
+        MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
+  @{
+**/
+#define MSR_HASWELL_IA32_PERFEVTSEL0             0x00000186
+#define MSR_HASWELL_IA32_PERFEVTSEL1             0x00000187
+#define MSR_HASWELL_IA32_PERFEVTSEL3             0x00000189
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,
+  #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Event Select: Selects a performance event logic unit.
+    ///
+    UINT32  EventSelect:8;
+    ///
+    /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
+    /// detect on the selected event logic.
+    ///
+    UINT32  UMASK:8;
+    ///
+    /// [Bit 16] USR: Counts while in privilege level is not ring 0.
+    ///
+    UINT32  USR:1;
+    ///
+    /// [Bit 17] OS: Counts while in privilege level is ring 0.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 18] Edge: Enables edge detection if set.
+    ///
+    UINT32  E:1;
+    ///
+    /// [Bit 19] PC: enables pin control.
+    ///
+    UINT32  PC:1;
+    ///
+    /// [Bit 20] INT: enables interrupt on counter overflow.
+    ///
+    UINT32  INT:1;
+    ///
+    /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
+    /// event conditions occurring across all logical processors sharing a
+    /// processor core. When set to 0, the counter only increments the
+    /// associated event conditions occurring in the logical processor which
+    /// programmed the MSR.
+    ///
+    UINT32  ANY:1;
+    ///
+    /// [Bit 22] EN: enables the corresponding performance counter to commence
+    /// counting when this bit is set.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 23] INV: invert the CMASK.
+    ///
+    UINT32  INV:1;
+    ///
+    /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
+    /// performance counter increments each cycle if the event count is
+    /// greater than or equal to the CMASK.
+    ///
+    UINT32  CMASK:8;
+    UINT32  Reserved:32;
+    ///
+    /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
+    /// AnyThread (bit 21) should be cleared to prevent incorrect results.
+    ///
+    UINT32  IN_TX:1;
+    UINT32  Reserved2:31;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;
+
+
+/**
+  Thread. Performance Event Select for Counter 2 (R/W) Supports all fields
+  described inTable 2-2 and the fields below.
+
+  @param  ECX  MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
+**/
+#define MSR_HASWELL_IA32_PERFEVTSEL2             0x00000188
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Event Select: Selects a performance event logic unit.
+    ///
+    UINT32  EventSelect:8;
+    ///
+    /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
+    /// detect on the selected event logic.
+    ///
+    UINT32  UMASK:8;
+    ///
+    /// [Bit 16] USR: Counts while in privilege level is not ring 0.
+    ///
+    UINT32  USR:1;
+    ///
+    /// [Bit 17] OS: Counts while in privilege level is ring 0.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 18] Edge: Enables edge detection if set.
+    ///
+    UINT32  E:1;
+    ///
+    /// [Bit 19] PC: enables pin control.
+    ///
+    UINT32  PC:1;
+    ///
+    /// [Bit 20] INT: enables interrupt on counter overflow.
+    ///
+    UINT32  INT:1;
+    ///
+    /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
+    /// event conditions occurring across all logical processors sharing a
+    /// processor core. When set to 0, the counter only increments the
+    /// associated event conditions occurring in the logical processor which
+    /// programmed the MSR.
+    ///
+    UINT32  ANY:1;
+    ///
+    /// [Bit 22] EN: enables the corresponding performance counter to commence
+    /// counting when this bit is set.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 23] INV: invert the CMASK.
+    ///
+    UINT32  INV:1;
+    ///
+    /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
+    /// performance counter increments each cycle if the event count is
+    /// greater than or equal to the CMASK.
+    ///
+    UINT32  CMASK:8;
+    UINT32  Reserved:32;
+    ///
+    /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
+    /// AnyThread (bit 21) should be cleared to prevent incorrect results.
+    ///
+    UINT32  IN_TX:1;
+    ///
+    /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and
+    /// in sampling, spurious PMI may occur and transactions may continuously
+    /// abort near overflow conditions. Software should favor using IN_TXCP
+    /// for counting over sampling. If sampling, software should use large
+    /// "sample-after" value after clearing the counter configured to use
+    /// IN_TXCP and also always reset the counter even when no overflow
+    /// condition was reported.
+    ///
+    UINT32  IN_TXCP:1;
+    UINT32  Reserved2:30;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Filtering Select Register (R/W).
+
+  @param  ECX  MSR_HASWELL_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_LBR_SELECT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
+  AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_HASWELL_LBR_SELECT                   0x000001C8
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    ///
+    /// [Bit 9] EN_CALL_STACK.
+    ///
+    UINT32  EN_CALL_STACK:1;
+    UINT32  Reserved1:22;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_LBR_SELECT_REGISTER;
+
+
+/**
+  Package. Package C6/C7 Interrupt Response Limit 1 (R/W)  This MSR defines
+  the interrupt response time limit used by the processor to manage transition
+  to package C6 or C7 state. The latency programmed in this register is for
+  the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.
+  Note: C-state values are processor specific C-state code names, unrelated to
+  MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKGC_IRTL1 (0x0000060B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKGC_IRTL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
+  AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
+**/
+#define MSR_HASWELL_PKGC_IRTL1                   0x0000060B
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C6 or C7 state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKGC_IRTL1_REGISTER;
+
+
+/**
+  Package. Package C6/C7 Interrupt Response Limit 2 (R/W)  This MSR defines
+  the interrupt response time limit used by the processor to manage transition
+  to package C6 or C7 state. The latency programmed in this register is for
+  the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.
+  Note: C-state values are processor specific C-state code names, unrelated to
+  MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKGC_IRTL2 (0x0000060C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKGC_IRTL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
+  AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
+**/
+#define MSR_HASWELL_PKGC_IRTL2                   0x0000060C
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C6 or C7 state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKGC_IRTL2_REGISTER;
+
+
+/**
+  Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_PKG_PERF_STATUS (0x00000613)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
+  @endcode
+  @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_HASWELL_PKG_PERF_STATUS              0x00000613
+
+
+/**
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_DRAM_ENERGY_STATUS           0x00000619
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_HASWELL_DRAM_PERF_STATUS             0x0000061B
+
+
+/**
+  Package. Base TDP Ratio (R/O).
+
+  @param  ECX  MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
+  @endcode
+  @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
+**/
+#define MSR_HASWELL_CONFIG_TDP_NOMINAL           0x00000648
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
+    /// specific processor (in units of 100 MHz).
+    ///
+    UINT32  Config_TDP_Base:8;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;
+
+
+/**
+  Package. ConfigTDP Level 1 ratio and power level (R/O).
+
+  @param  ECX  MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
+  @endcode
+  @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
+**/
+#define MSR_HASWELL_CONFIG_TDP_LEVEL1            0x00000649
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
+    ///
+    UINT32  PKG_TDP_LVL1:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
+    /// for this specific processor.
+    ///
+    UINT32  Config_TDP_LVL1_Ratio:8;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
+    /// Level 1.
+    ///
+    UINT32  PKG_MAX_PWR_LVL1:15;
+    ///
+    /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
+    /// Level 1.
+    ///
+    UINT32  PKG_MIN_PWR_LVL1:16;
+    UINT32  Reserved3:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;
+
+
+/**
+  Package. ConfigTDP Level 2 ratio and power level (R/O).
+
+  @param  ECX  MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
+  @endcode
+  @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
+**/
+#define MSR_HASWELL_CONFIG_TDP_LEVEL2            0x0000064A
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
+    ///
+    UINT32  PKG_TDP_LVL2:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
+    /// for this specific processor.
+    ///
+    UINT32  Config_TDP_LVL2_Ratio:8;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
+    /// Level 2.
+    ///
+    UINT32  PKG_MAX_PWR_LVL2:15;
+    ///
+    /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
+    /// Level 2.
+    ///
+    UINT32  PKG_MIN_PWR_LVL2:16;
+    UINT32  Reserved3:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
+**/
+#define MSR_HASWELL_CONFIG_TDP_CONTROL           0x0000064B
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
+    ///
+    UINT32  TDP_LEVEL:2;
+    UINT32  Reserved1:29;
+    ///
+    /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
+    /// this register is locked until a reset.
+    ///
+    UINT32  Config_TDP_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
+  AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
+**/
+#define MSR_HASWELL_TURBO_ACTIVATION_RATIO       0x0000064C
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
+    /// field.
+    ///
+    UINT32  MAX_NON_TURBO_RATIO:8;
+    UINT32  Reserved1:23;
+    ///
+    /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
+    /// content of this register is locked until a reset.
+    ///
+    UINT32  TURBO_ACTIVATION_RATIO_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.
+
+  @param  ECX  MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL       0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 0000b:
+    /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
+    /// 0100b: C7 0101b: C7s Package C states C7 are not available to
+    /// processor with signature 06_3CH.
+    ///
+    UINT32  Limit:4;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    UINT32  Reserved4:3;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_HASWELL_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_HASWELL_SMM_MCA_CAP                  0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and the
+    /// MSR_SMM_FEATURE_CONTROL is supported.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
+    /// supported.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_HASWELL_TURBO_RATIO_LIMIT            0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Uncore PMU global control.
+
+  @param  ECX  MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL         0x00000391
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core 0 select.
+    ///
+    UINT32  PMI_Sel_Core0:1;
+    ///
+    /// [Bit 1] Core 1 select.
+    ///
+    UINT32  PMI_Sel_Core1:1;
+    ///
+    /// [Bit 2] Core 2 select.
+    ///
+    UINT32  PMI_Sel_Core2:1;
+    ///
+    /// [Bit 3] Core 3 select.
+    ///
+    UINT32  PMI_Sel_Core3:1;
+    UINT32  Reserved1:15;
+    UINT32  Reserved2:10;
+    ///
+    /// [Bit 29] Enable all uncore counters.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 30] Enable wake on PMI.
+    ///
+    UINT32  WakePMI:1;
+    ///
+    /// [Bit 31] Enable Freezing counter when overflow.
+    ///
+    UINT32  FREEZE:1;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;
+
+
+/**
+  Package. Uncore PMU main status.
+
+  @param  ECX  MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS       0x00000392
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fixed counter overflowed.
+    ///
+    UINT32  Fixed:1;
+    ///
+    /// [Bit 1] An ARB counter overflowed.
+    ///
+    UINT32  ARB:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 3] A CBox counter overflowed (on any slice).
+    ///
+    UINT32  CBox:1;
+    UINT32  Reserved2:28;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Package. Uncore fixed counter control (R/W).
+
+  @param  ECX  MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
+**/
+#define MSR_HASWELL_UNC_PERF_FIXED_CTRL          0x00000394
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:20;
+    ///
+    /// [Bit 20] Enable overflow propagation.
+    ///
+    UINT32  EnableOverflow:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 22] Enable counting.
+    ///
+    UINT32  EnableCounting:1;
+    UINT32  Reserved3:9;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;
+
+
+/**
+  Package. Uncore fixed counter.
+
+  @param  ECX  MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
+**/
+#define MSR_HASWELL_UNC_PERF_FIXED_CTR           0x00000395
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Current count.
+    ///
+    UINT32  CurrentCount:32;
+    ///
+    /// [Bits 47:32] Current count.
+    ///
+    UINT32  CurrentCountHi:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;
+
+
+/**
+  Package. Uncore C-Box configuration information (R/O).
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_CBO_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_CONFIG               0x00000396
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
+    ///
+    UINT32  CBox:4;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;
+
+
+/**
+  Package. Uncore Arb unit, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_ARB_PERFCTR0             0x000003B0
+
+
+/**
+  Package. Uncore Arb unit, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_ARB_PERFCTR1             0x000003B1
+
+
+/**
+  Package. Uncore Arb unit, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0          0x000003B2
+
+
+/**
+  Package. Uncore Arb unit, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1          0x000003B3
+
+
+/**
+  Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
+**/
+#define MSR_HASWELL_SMM_FEATURE_CONTROL          0x000004E0
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
+    /// further changes.
+    ///
+    UINT32  Lock:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
+    /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
+    /// logical processors are prevented from executing SMM code outside the
+    /// ranges defined by the SMRR. When set to '1' any logical processor in
+    /// the package that attempts to execute SMM code not within the ranges
+    /// defined by the SMRR will assert an unrecoverable MCE.
+    ///
+    UINT32  SMM_Code_Chk_En:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
+  processors in the package. Available only while in SMM and
+  MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
+
+  [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
+  processor of its state in a long flow of internal operation which
+  delays servicing an interrupt. The corresponding bit will be set at
+  the start of long events such as: Microcode Update Load, C6, WBINVD,
+  Ratio Change, Throttle. The bit is automatically cleared at the end of
+  each long event. The reset value of this field is 0. Only bit
+  positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
+  updated.
+
+  [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
+  processor of its state in a long flow of internal operation which
+  delays servicing an interrupt. The corresponding bit will be set at
+  the start of long events such as: Microcode Update Load, C6, WBINVD,
+  Ratio Change, Throttle. The bit is automatically cleared at the end of
+  each long event. The reset value of this field is 0. Only bit
+  positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
+  updated.
+
+  @param  ECX  MSR_HASWELL_SMM_DELAYED (0x000004E2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);
+  @endcode
+  @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
+**/
+#define MSR_HASWELL_SMM_DELAYED                  0x000004E2
+
+
+/**
+  Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
+  processors in the package. Available only while in SMM.
+
+  [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
+  processor of its blocked state to service an SMI. The corresponding
+  bit will be set if the logical processor is in one of the following
+  states: Wait For SIPI or SENTER Sleep. The reset value of this field
+  is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
+  ECX=PKG_LVL):EBX[15:0] can be updated.
+
+
+  [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
+  processor of its blocked state to service an SMI. The corresponding
+  bit will be set if the logical processor is in one of the following
+  states: Wait For SIPI or SENTER Sleep. The reset value of this field
+  is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
+  ECX=PKG_LVL):EBX[15:0] can be updated.
+
+  @param  ECX  MSR_HASWELL_SMM_BLOCKED (0x000004E3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);
+  @endcode
+  @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
+**/
+#define MSR_HASWELL_SMM_BLOCKED                  0x000004E3
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O).
+
+  @param  ECX  MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_HASWELL_RAPL_POWER_UNIT              0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Package. Energy Status Units Energy related information
+    /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+    /// micro-joules).
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+    /// Interfaces.".
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_PP0_ENERGY_STATUS            0x00000639
+
+
+/**
+  Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
+  RAPL Domains.".
+
+  @param  ECX  MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
+**/
+#define MSR_HASWELL_PP1_POWER_LIMIT              0x00000640
+
+
+/**
+  Package. PP1 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_PP1_ENERGY_STATUS            0x00000641
+
+
+/**
+  Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_HASWELL_PP1_POLICY (0x00000642)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
+  AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);
+  @endcode
+  @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
+**/
+#define MSR_HASWELL_PP1_POLICY                   0x00000642
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS      0x00000690
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
+    /// reduced below the operating system request due to assertion of
+    /// external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
+    /// below the operating system request due to Processor Graphics driver
+    /// override.
+    ///
+    UINT32  GraphicsDriverStatus:1;
+    ///
+    /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
+    /// When set, frequency is reduced below the operating system request
+    /// because the processor has detected that utilization is low.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    ///
+    /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
+    /// below the operating system request due to domain-level power limiting.
+    ///
+    UINT32  PLStatus:1;
+    ///
+    /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL1.
+    ///
+    UINT32  PL1Status:1;
+    ///
+    /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL2.
+    ///
+    UINT32  PL2Status:1;
+    ///
+    /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
+    /// below the operating system request due to multi-core turbo limits.
+    ///
+    UINT32  MaxTurboLimitStatus:1;
+    ///
+    /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
+    /// is reduced below the operating system request due to Turbo transition
+    /// attenuation. This prevents performance degradation due to frequent
+    /// operating ratio changes.
+    ///
+    UINT32  TurboTransitionAttenuationStatus:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 20] Graphics Driver Log  When set, indicates that the Graphics
+    /// Driver Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  GraphicsDriverLog:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the Autonomous Utilization-Based Frequency Control
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    ///
+    /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
+    /// Power Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  PLLog:1;
+    ///
+    /// [Bit 26] Package-Level PL1 Power Limiting Log  When set, indicates
+    /// that the Package Level PL1 Power Limiting Status bit has asserted
+    /// since the log bit was last cleared. This log bit will remain set until
+    /// cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
+    /// the Package Level PL2 Power Limiting Status bit has asserted since the
+    /// log bit was last cleared. This log bit will remain set until cleared
+    /// by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    ///
+    /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    UINT32  Reserved6:2;
+    UINT32  Reserved7:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
+  (frequency refers to processor graphics frequency).
+
+  @param  ECX  MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS  0x000006B0
+
+/**
+  MSR information returned for MSR index
+  #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
+    /// operating system request due to assertion of external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
+    /// below the operating system request due to Processor Graphics driver
+    /// override.
+    ///
+    UINT32  GraphicsDriverStatus:1;
+    ///
+    /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
+    /// When set, frequency is reduced below the operating system request
+    /// because the processor has detected that utilization is low.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    ///
+    /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is
+    /// reduced below the operating system request due to domain-level power
+    /// limiting.
+    ///
+    UINT32  GraphicsPowerLimitingStatus:1;
+    ///
+    /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL1.
+    ///
+    UINT32  PL1STatus:1;
+    ///
+    /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL2.
+    ///
+    UINT32  PL2Status:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 20] Graphics Driver Log  When set, indicates that the Graphics
+    /// Driver Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  GraphicsDriverLog:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the Autonomous Utilization-Based Frequency Control
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    ///
+    /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
+    /// Power Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CorePowerLimitingLog:1;
+    ///
+    /// [Bit 26] Package-Level PL1 Power Limiting Log  When set, indicates
+    /// that the Package Level PL1 Power Limiting Status bit has asserted
+    /// since the log bit was last cleared. This log bit will remain set until
+    /// cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
+    /// the Package Level PL2 Power Limiting Status bit has asserted since the
+    /// log bit was last cleared. This log bit will remain set until cleared
+    /// by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    ///
+    /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    UINT32  Reserved6:2;
+    UINT32  Reserved7:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
+  (frequency refers to ring interconnect in the uncore).
+
+  @param  ECX  MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_HASWELL_RING_PERF_LIMIT_REASONS      0x000006B1
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
+    /// operating system request due to assertion of external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL1.
+    ///
+    UINT32  PL1STatus:1;
+    ///
+    /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL2.
+    ///
+    UINT32  PL2Status:1;
+    UINT32  Reserved4:4;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved5:2;
+    ///
+    /// [Bit 20] Graphics Driver Log  When set, indicates that the Graphics
+    /// Driver Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  GraphicsDriverLog:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the Autonomous Utilization-Based Frequency Control
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    ///
+    /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
+    /// Power Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CorePowerLimitingLog:1;
+    ///
+    /// [Bit 26] Package-Level PL1 Power Limiting Log  When set, indicates
+    /// that the Package Level PL1 Power Limiting Status bit has asserted
+    /// since the log bit was last cleared. This log bit will remain set until
+    /// cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
+    /// the Package Level PL2 Power Limiting Status bit has asserted since the
+    /// log bit was last cleared. This log bit will remain set until cleared
+    /// by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    ///
+    /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    UINT32  Reserved7:2;
+    UINT32  Reserved8:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Package. Uncore C-Box 0, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0        0x00000700
+
+
+/**
+  Package. Uncore C-Box 0, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1        0x00000701
+
+
+/**
+  Package. Uncore C-Box 0, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR0           0x00000706
+
+
+/**
+  Package. Uncore C-Box 0, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR1           0x00000707
+
+
+/**
+  Package. Uncore C-Box 1, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0        0x00000710
+
+
+/**
+  Package. Uncore C-Box 1, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1        0x00000711
+
+
+/**
+  Package. Uncore C-Box 1, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR0           0x00000716
+
+
+/**
+  Package. Uncore C-Box 1, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR1           0x00000717
+
+
+/**
+  Package. Uncore C-Box 2, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0        0x00000720
+
+
+/**
+  Package. Uncore C-Box 2, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1        0x00000721
+
+
+/**
+  Package. Uncore C-Box 2, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR0           0x00000726
+
+
+/**
+  Package. Uncore C-Box 2, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR1           0x00000727
+
+
+/**
+  Package. Uncore C-Box 3, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0        0x00000730
+
+
+/**
+  Package. Uncore C-Box 3, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1        0x00000731
+
+
+/**
+  Package. Uncore C-Box 3, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR0           0x00000736
+
+
+/**
+  Package. Uncore C-Box 3, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR1           0x00000737
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
+  AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
+**/
+#define MSR_HASWELL_PKG_C8_RESIDENCY             0x00000630
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
+    /// that this package is in processor-specific C8 states. Count at the
+    /// same frequency as the TSC.
+    ///
+    UINT32  C8ResidencyCounter:32;
+    ///
+    /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
+    /// reset that this package is in processor-specific C8 states. Count at
+    /// the same frequency as the TSC.
+    ///
+    UINT32  C8ResidencyCounterHi:28;
+    UINT32  Reserved:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
+  AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
+**/
+#define MSR_HASWELL_PKG_C9_RESIDENCY             0x00000631
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
+    /// that this package is in processor-specific C9 states. Count at the
+    /// same frequency as the TSC.
+    ///
+    UINT32  C9ResidencyCounter:32;
+    ///
+    /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
+    /// reset that this package is in processor-specific C9 states. Count at
+    /// the same frequency as the TSC.
+    ///
+    UINT32  C9ResidencyCounterHi:28;
+    UINT32  Reserved:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
+  AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
+**/
+#define MSR_HASWELL_PKG_C10_RESIDENCY            0x00000632
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
+    /// reset that this package is in processor-specific C10 states. Count at
+    /// the same frequency as the TSC.
+    ///
+    UINT32  C10ResidencyCounter:32;
+    ///
+    /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
+    /// reset that this package is in processor-specific C10 states. Count at
+    /// the same frequency as the TSC.
+    ///
+    UINT32  C10ResidencyCounterHi:28;
+    UINT32  Reserved:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h b/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h
new file mode 100644
index 000000000000..57fde2c677f0
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h
@@ -0,0 +1,2887 @@
+/** @file
+  MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __IVY_BRIDGE_MSR_H__
+#define __IVY_BRIDGE_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Ivy Bridge microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3A || \
+    DisplayModel == 0x3E    \
+    )                       \
+   )
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_IVY_BRIDGE_PLATFORM_INFO             0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
+    /// indicates that LPM is supported, and when set to 0, indicates LPM is
+    /// not supported.
+    ///
+    UINT32  LowPowerModeSupport:1;
+    ///
+    /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
+    /// TDP level available. 01: One additional TDP level available. 02: Two
+    /// additional TDP level available. 11: Reserved.
+    ///
+    UINT32  ConfigTDPLevels:2;
+    UINT32  Reserved4:5;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    ///
+    /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
+    /// minimum supported operating ratio in units of 100 MHz.
+    ///
+    UINT32  MinimumOperatingRatio:8;
+    UINT32  Reserved5:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI C-States. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL    0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power). for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
+    /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
+    /// This field cannot be used to limit package C-state to C3.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
+    /// IO_read instructions sent to IO register specified by
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
+    /// until next reset.
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C6/C7 requests to C3 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 undemotion (R/W)  When set, enables undemotion from
+    /// demoted C3.
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 undemotion (R/W)  When set, enables undemotion from
+    /// demoted C1.
+    ///
+    UINT32  C1Undemotion:1;
+    UINT32  Reserved4:3;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS         0x00000639
+
+
+/**
+  Package. Base TDP Ratio (R/O).
+
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
+  @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
+**/
+#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL        0x00000648
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
+    /// specific processor (in units of 100 MHz).
+    ///
+    UINT32  Config_TDP_Base:8;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;
+
+
+/**
+  Package. ConfigTDP Level 1 ratio and power level (R/O).
+
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
+  @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1         0x00000649
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
+    ///
+    UINT32  PKG_TDP_LVL1:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
+    /// for this specific processor.
+    ///
+    UINT32  Config_TDP_LVL1_Ratio:8;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
+    /// Level 1.
+    ///
+    UINT32  PKG_MAX_PWR_LVL1:15;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
+    /// Level 1.
+    ///
+    UINT32  PKG_MIN_PWR_LVL1:15;
+    UINT32  Reserved4:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;
+
+
+/**
+  Package. ConfigTDP Level 2 ratio and power level (R/O).
+
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
+  @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2         0x0000064A
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
+    ///
+    UINT32  PKG_TDP_LVL2:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
+    /// for this specific processor.
+    ///
+    UINT32  Config_TDP_LVL2_Ratio:8;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
+    /// Level 2.
+    ///
+    UINT32  PKG_MAX_PWR_LVL2:15;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
+    /// Level 2.
+    ///
+    UINT32  PKG_MIN_PWR_LVL2:15;
+    UINT32  Reserved4:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
+**/
+#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL        0x0000064B
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
+    ///
+    UINT32  TDP_LEVEL:2;
+    UINT32  Reserved1:29;
+    ///
+    /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
+    /// this register is locked until a reset.
+    ///
+    UINT32  Config_TDP_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
+**/
+#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO    0x0000064C
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
+    /// field.
+    ///
+    UINT32  MAX_NON_TURBO_RATIO:8;
+    UINT32  Reserved1:23;
+    ///
+    /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
+    /// content of this register is locked until a reset.
+    ///
+    UINT32  TURBO_ACTIVATION_RATIO_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_PPIN_CTL                  0x0000004E
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.
+    /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit
+    /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to
+    /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged
+    /// inventory initialization agent to access MSR_PPIN. After reading
+    /// MSR_PPIN, the privileged inventory initialization agent should write
+    /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
+    /// prevent unauthorized modification to MSR_PPIN_CTL.
+    ///
+    UINT32  LockOut:1;
+    ///
+    /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
+    /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
+    /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
+    /// is 0.
+    ///
+    UINT32  Enable_PPIN:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) A unique value within a given CPUID
+  family/model/stepping signature that a privileged inventory initialization
+  agent can access to identify each physical processor, when access to
+  MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
+  MSR_PPIN_CTL[bits 1:0] = '10b'.
+
+  @param  ECX  MSR_IVY_BRIDGE_PPIN (0x0000004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
+  @endcode
+  @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
+**/
+#define MSR_IVY_BRIDGE_PPIN                      0x0000004F
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_PLATFORM_INFO_1           0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:7;
+    ///
+    /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
+    /// Protected Processor Inventory Number (PPIN) capability can be enabled
+    /// for privileged system inventory agent to read PPIN from MSR_PPIN. When
+    /// set to 0, PPIN capability is not supported. An attempt to access
+    /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
+    ///
+    UINT32  PPIN_CAP:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    ///
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O)  When set to 1,
+    /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
+    /// specify an temperature offset.
+    ///
+    UINT32  TJOFFSET:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved6:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;
+
+
+/**
+  Package. MC Bank Error Configuration (R/W).
+
+  @param  ECX  MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
+**/
+#define MSR_IVY_BRIDGE_ERROR_CONTROL             0x0000017F
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank
+    /// to log additional info in bits 36:32.
+    ///
+    UINT32  MemErrorLogEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;
+
+
+/**
+  Package.
+
+  @param  ECX  MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
+**/
+#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET        0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (RO)  The minimum temperature at which
+    /// PROCHOT# will be asserted. The value is degree C.
+    ///
+    UINT32  TemperatureTarget:8;
+    ///
+    /// [Bits 27:24] TCC Activation Offset (R/W)  Specifies a temperature
+    /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
+    /// will assert at the offset target temperature. Write is permitted only
+    /// MSR_PLATFORM_INFO.[30] is set.
+    ///
+    UINT32  TCCActivationOffset:4;
+    UINT32  Reserved2:4;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
+  @endcode
+  @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1        0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
+    /// limit of 9 core active.
+    ///
+    UINT32  Maximum9C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
+    /// limit of 10core active.
+    ///
+    UINT32  Maximum10C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
+    /// limit of 11 core active.
+    ///
+    UINT32  Maximum11C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
+    /// limit of 12 core active.
+    ///
+    UINT32  Maximum12C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
+    /// limit of 13 core active.
+    ///
+    UINT32  Maximum13C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
+    /// limit of 14 core active.
+    ///
+    UINT32  Maximum14C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
+    /// limit of 15 core active.
+    ///
+    UINT32  Maximum15C:8;
+    UINT32  Reserved:7;
+    ///
+    /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
+    /// the processor uses override configuration specified in
+    /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
+    /// uses factory-set configuration (Default).
+    ///
+    UINT32  TurboRatioLimitConfigurationSemaphore:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;
+
+
+/**
+  Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
+**/
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC             0x0000041B
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 5:0] Recoverable Address LSB.
+    ///
+    UINT32  RecoverableAddressLSB:6;
+    ///
+    /// [Bits 8:6] Address Mode.
+    ///
+    UINT32  AddressMode:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bits 31:16] PCI Express Requestor ID.
+    ///
+    UINT32  PCIExpressRequestorID:16;
+    ///
+    /// [Bits 39:32] PCI Express Segment Number.
+    ///
+    UINT32  PCIExpressSegmentNumber:8;
+    UINT32  Reserved2:24;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
+
+
+/**
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+  15.3.2.4, "IA32_MCi_MISC MSRs.".
+
+  Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+  and its corresponding slice of L3.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_CTL
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.
+        MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.
+        MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.
+  @{
+**/
+#define MSR_IVY_BRIDGE_IA32_MC29_CTL             0x00000474
+#define MSR_IVY_BRIDGE_IA32_MC30_CTL             0x00000478
+#define MSR_IVY_BRIDGE_IA32_MC31_CTL             0x0000047C
+/// @}
+
+
+/**
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+  15.3.2.4, "IA32_MCi_MISC MSRs.".
+
+  Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+  and its corresponding slice of L3.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_STATUS
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.
+        MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.
+        MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.
+  @{
+**/
+#define MSR_IVY_BRIDGE_IA32_MC29_STATUS          0x00000475
+#define MSR_IVY_BRIDGE_IA32_MC30_STATUS          0x00000479
+#define MSR_IVY_BRIDGE_IA32_MC31_STATUS          0x0000047D
+/// @}
+
+
+/**
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+  15.3.2.4, "IA32_MCi_MISC MSRs.".
+
+  Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+  and its corresponding slice of L3.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_ADDR
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.
+        MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.
+        MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.
+  @{
+**/
+#define MSR_IVY_BRIDGE_IA32_MC29_ADDR            0x00000476
+#define MSR_IVY_BRIDGE_IA32_MC30_ADDR            0x0000047A
+#define MSR_IVY_BRIDGE_IA32_MC31_ADDR            0x0000047E
+/// @}
+
+
+/**
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+  15.3.2.4, "IA32_MCi_MISC MSRs.".
+
+  Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+  and its corresponding slice of L3.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_MISC
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.
+        MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.
+        MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.
+  @{
+**/
+#define MSR_IVY_BRIDGE_IA32_MC29_MISC            0x00000477
+#define MSR_IVY_BRIDGE_IA32_MC30_MISC            0x0000047B
+#define MSR_IVY_BRIDGE_IA32_MC31_MISC            0x0000047F
+/// @}
+
+
+/**
+  Package. Package RAPL Perf Status (R/O).
+
+  @param  ECX  MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
+  @endcode
+  @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PKG_PERF_STATUS           0x00000613
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT          0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS        0x00000619
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS          0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_IVY_BRIDGE_DRAM_POWER_INFO           0x0000061C
+
+
+/**
+  Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
+
+  @param  ECX  MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_IVY_BRIDGE_PEBS_ENABLE               0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC0:1;
+    ///
+    /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC1:1;
+    ///
+    /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC2:1;
+    ///
+    /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
+    ///
+    UINT32  LL_EN_PMC0:1;
+    ///
+    /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
+    ///
+    UINT32  LL_EN_PMC1:1;
+    ///
+    /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
+    ///
+    UINT32  LL_EN_PMC2:1;
+    ///
+    /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
+    ///
+    UINT32  LL_EN_PMC3:1;
+    UINT32  Reserved2:28;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Package. Uncore perfmon per-socket global control.
+
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL           0x00000C00
+
+
+/**
+  Package. Uncore perfmon per-socket global status.
+
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS        0x00000C01
+
+
+/**
+  Package. Uncore perfmon per-socket global configuration.
+
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
+**/
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG        0x00000C06
+
+
+/**
+  Package. Uncore U-box perfmon U-box wide status.
+
+  @param  ECX  MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS         0x00000C15
+
+
+/**
+  Package. Uncore PCU perfmon box wide status.
+
+  @param  ECX  MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS       0x00000C35
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1       0x00000D1A
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1       0x00000D3A
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1       0x00000D5A
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1       0x00000D7A
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1       0x00000D9A
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1       0x00000DBA
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1       0x00000DDA
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1       0x00000DFA
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL           0x00000E04
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0          0x00000E10
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1          0x00000E11
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2          0x00000E12
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3          0x00000E13
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER        0x00000E14
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_CTR0              0x00000E16
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_CTR1              0x00000E17
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_CTR2              0x00000E18
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_CTR3              0x00000E19
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1       0x00000E1A
+
+
+/**
+  Package. Uncore C-box 9 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL           0x00000E24
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0          0x00000E30
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1          0x00000E31
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2          0x00000E32
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3          0x00000E33
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER        0x00000E34
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_CTR0              0x00000E36
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_CTR1              0x00000E37
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_CTR2              0x00000E38
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_CTR3              0x00000E39
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1       0x00000E3A
+
+
+/**
+  Package. Uncore C-box 10 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL          0x00000E44
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0         0x00000E50
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1         0x00000E51
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2         0x00000E52
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3         0x00000E53
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER       0x00000E54
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_CTR0             0x00000E56
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_CTR1             0x00000E57
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_CTR2             0x00000E58
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_CTR3             0x00000E59
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1      0x00000E5A
+
+
+/**
+  Package. Uncore C-box 11 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL          0x00000E64
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0         0x00000E70
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1         0x00000E71
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2         0x00000E72
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3         0x00000E73
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER       0x00000E74
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_CTR0             0x00000E76
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_CTR1             0x00000E77
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_CTR2             0x00000E78
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_CTR3             0x00000E79
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1      0x00000E7A
+
+
+/**
+  Package. Uncore C-box 12 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL          0x00000E84
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0         0x00000E90
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1         0x00000E91
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2         0x00000E92
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3         0x00000E93
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER       0x00000E94
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_CTR0             0x00000E96
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_CTR1             0x00000E97
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_CTR2             0x00000E98
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_CTR3             0x00000E99
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1      0x00000E9A
+
+
+/**
+  Package. Uncore C-box 13 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL          0x00000EA4
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0         0x00000EB0
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1         0x00000EB1
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2         0x00000EB2
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3         0x00000EB3
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER       0x00000EB4
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_CTR0             0x00000EB6
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_CTR1             0x00000EB7
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_CTR2             0x00000EB8
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_CTR3             0x00000EB9
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1      0x00000EBA
+
+
+/**
+  Package. Uncore C-box 14 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL          0x00000EC4
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0         0x00000ED0
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1         0x00000ED1
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2         0x00000ED2
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3         0x00000ED3
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER       0x00000ED4
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_CTR0             0x00000ED6
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_CTR1             0x00000ED7
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_CTR2             0x00000ED8
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_CTR3             0x00000ED9
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1      0x00000EDA
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h b/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h
new file mode 100644
index 000000000000..74eef33449b6
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h
@@ -0,0 +1,7424 @@
+/** @file
+  MSR Definitions for Intel processors based on the Nehalem microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __NEHALEM_MSR_H__
+#define __NEHALEM_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Nehalem microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x1A || \
+    DisplayModel == 0x1E || \
+    DisplayModel == 0x1F || \
+    DisplayModel == 0x2E    \
+    )                       \
+   )
+
+/**
+  Package. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_NEHALEM_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
+  @endcode
+  @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
+**/
+#define MSR_NEHALEM_PLATFORM_ID                  0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:18;
+    ///
+    /// [Bits 52:50] See Table 2-2.
+    ///
+    UINT32  PlatformId:3;
+    UINT32  Reserved3:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PLATFORM_ID_REGISTER;
+
+
+/**
+  Thread. SMI Counter (R/O).
+
+  @param  ECX  MSR_NEHALEM_SMI_COUNT (0x00000034)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
+  @endcode
+  @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
+**/
+#define MSR_NEHALEM_SMI_COUNT                    0x00000034
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] SMI Count (R/O)  Running count of SMI events since last
+    /// RESET.
+    ///
+    UINT32  SMICount:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_SMI_COUNT_REGISTER;
+
+
+/**
+  Package. see http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_NEHALEM_PLATFORM_INFO                0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. The invariant TSC
+    /// frequency can be computed by multiplying this ratio by 133.33 MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)
+    /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are
+    /// programmable, and when set to 0, indicates TDC and TDP Limits for
+    /// Turbo mode are not programmable.
+    ///
+    UINT32  TDC_TDPLimit:1;
+    UINT32  Reserved3:2;
+    UINT32  Reserved4:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 133.33MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates. See http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL       0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power). for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
+    /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package
+    /// C-state limit. Note: This field cannot be used to limit package
+    /// C-state to C3.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
+    /// IO_read instructions sent to IO register specified by
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
+    /// until next reset.
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:8;
+    ///
+    /// [Bit 24] Interrupt filtering enable (R/W)  When set, processor cores
+    /// in a deep C-State will wake only when the event message is destined
+    /// for that core. When 0, all processor cores in a deep C-State will wake
+    /// for an event message.
+    ///
+    UINT32  InterruptFiltering:1;
+    ///
+    /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C6/C7 requests to C3 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    ///
+    /// [Bit 29] Package C State Demotion Enable (R/W).
+    ///
+    UINT32  CStateDemotion:1;
+    ///
+    /// [Bit 30] Package C State UnDemotion Enable (R/W).
+    ///
+    UINT32  CStateUndemotion:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Core. Power Management IO Redirection in C-state (R/W) See
+  http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
+  AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
+**/
+#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE          0x000000E4
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] LVL_2 Base Address (R/W)  Specifies the base address
+    /// visible to software for IO redirection. If IO MWAIT Redirection is
+    /// enabled, reads to this address will be consumed by the power
+    /// management logic and decoded to MWAIT instructions. When IO port
+    /// address redirection is enabled, this is the IO port address reported
+    /// to the OS/software.
+    ///
+    UINT32  Lvl2Base:16;
+    ///
+    /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
+    /// maximum C-State code name to be included when IO read to MWAIT
+    /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
+    /// is the max C-State to include 001b - C6 is the max C-State to include
+    /// 010b - C7 is the max C-State to include.
+    ///
+    UINT32  CStateRange:3;
+    UINT32  Reserved1:13;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_NEHALEM_IA32_MISC_ENABLE             0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2. Default value is 1.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved6:3;
+    ///
+    /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:3;
+    ///
+    /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
+    /// that support Intel Turbo Boost Technology, the turbo mode feature is
+    /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
+    /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
+    /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
+    /// the power-on default value is used by BIOS to detect hardware support
+    /// of turbo mode. If power-on default value is 1, turbo mode is available
+    /// in the processor. If power-on default value is 0, turbo mode is not
+    /// available.
+    ///
+    UINT32  TurboModeDisable:1;
+    UINT32  Reserved10:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Thread.
+
+  @param  ECX  MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
+**/
+#define MSR_NEHALEM_TEMPERATURE_TARGET           0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (R)  The minimum temperature at which
+    /// PROCHOT# will be asserted. The value is degree C.
+    ///
+    UINT32  TemperatureTarget:8;
+    UINT32  Reserved2:8;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;
+
+
+/**
+  Miscellaneous Feature Control (R/W).
+
+  @param  ECX  MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_NEHALEM_MISC_FEATURE_CONTROL         0x000001A4
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
+    /// L2 hardware prefetcher, which fetches additional lines of code or data
+    /// into the L2 cache.
+    ///
+    UINT32  L2HardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W)  If 1,
+    /// disables the adjacent cache line prefetcher, which fetches the cache
+    /// line that comprises a cache line pair (128 bytes).
+    ///
+    UINT32  L2AdjacentCacheLinePrefetcherDisable:1;
+    ///
+    /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
+    /// the L1 data cache prefetcher, which fetches the next cache line into
+    /// L1 data cache.
+    ///
+    UINT32  DCUHardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W)  If 1, disables the L1
+    /// data cache IP prefetcher, which uses sequential load history (based on
+    /// instruction Pointer of previous loads) to determine whether to
+    /// prefetch additional lines.
+    ///
+    UINT32  DCUIPPrefetcherDisable:1;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Thread. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
+  AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
+  @endcode
+  @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
+**/
+#define MSR_NEHALEM_OFFCORE_RSP_0                0x000001A6
+
+
+/**
+  See http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_MISC_PWR_MGMT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
+  AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
+**/
+#define MSR_NEHALEM_MISC_PWR_MGMT                0x000001AA
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,
+    /// enables hardware coordination of Enhanced Intel Speedstep Technology
+    /// request from processor cores; When 1, disables hardware coordination
+    /// of Enhanced Intel Speedstep Technology requests.
+    ///
+    UINT32  EISTHardwareCoordinationDisable:1;
+    ///
+    /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W)  This bit makes
+    /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with
+    /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by
+    /// CPUID.(EAX=06h):ECX[3].
+    ///
+    UINT32  EnergyPerformanceBiasEnable:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;
+
+
+/**
+  See http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
+  AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.
+**/
+#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT    0x000001AC
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] Package. TDP Limit (R/W)  TDP limit in 1/8 Watt
+    /// granularity.
+    ///
+    UINT32  TDPLimit:15;
+    ///
+    /// [Bit 15] Package. TDP Limit Override Enable (R/W)  A value = 0
+    /// indicates override is not active, and a value = 1 indicates active.
+    ///
+    UINT32  TDPLimitOverrideEnable:1;
+    ///
+    /// [Bits 30:16] Package. TDC Limit (R/W)  TDC limit in 1/8 Amp
+    /// granularity.
+    ///
+    UINT32  TDCLimit:15;
+    ///
+    /// [Bit 31] Package. TDC Limit Override Enable (R/W)  A value = 0
+    /// indicates override is not active, and a value = 1 indicates active.
+    ///
+    UINT32  TDCLimitOverrideEnable:1;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_NEHALEM_TURBO_RATIO_LIMIT            0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
+  "Filtering of Last Branch Records.".
+
+  @param  ECX  MSR_NEHALEM_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_LBR_SELECT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
+  AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_NEHALEM_LBR_SELECT                   0x000001C8
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    UINT32  Reserved1:23;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_LBR_SELECT_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 680H).
+
+  @param  ECX  MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_NEHALEM_LASTBRANCH_TOS               0x000001C9
+
+
+/**
+  Thread. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
+  @endcode
+  @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_NEHALEM_LER_FROM_LIP                 0x000001DD
+
+
+/**
+  Thread. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_NEHALEM_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
+  @endcode
+  @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_NEHALEM_LER_TO_LIP                   0x000001DE
+
+
+/**
+  Core. Power Control Register. See http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_POWER_CTL (0x000001FC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_POWER_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
+  AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.
+**/
+#define MSR_NEHALEM_POWER_CTL                    0x000001FC
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Package. C1E Enable (R/W)  When set to '1', will enable the
+    /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
+    /// operating point when all execution cores enter MWAIT (C1).
+    ///
+    UINT32  C1EEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_POWER_CTL_REGISTER;
+
+
+/**
+  Thread. (RO).
+
+  @param  ECX  MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);
+  @endcode
+  @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_NEHALEM_PERF_GLOBAL_STATUS           0x0000038E
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:29;
+    ///
+    /// [Bit 61] UNC_Ovf Uncore overflowed if 1.
+    ///
+    UINT32  Ovf_Uncore:1;
+    UINT32  Reserved3:2;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Thread. (R/W).
+
+  @param  ECX  MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL         0x00000390
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:29;
+    ///
+    /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.
+    ///
+    UINT32  Ovf_Uncore:1;
+    UINT32  Reserved3:2;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;
+
+
+/**
+  Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
+
+  @param  ECX  MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_NEHALEM_PEBS_ENABLE                  0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC0:1;
+    ///
+    /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC1:1;
+    ///
+    /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC2:1;
+    ///
+    /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
+    ///
+    UINT32  LL_EN_PMC0:1;
+    ///
+    /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
+    ///
+    UINT32  LL_EN_PMC1:1;
+    ///
+    /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
+    ///
+    UINT32  LL_EN_PMC2:1;
+    ///
+    /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
+    ///
+    UINT32  LL_EN_PMC3:1;
+    UINT32  Reserved2:28;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PEBS_LD_LAT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
+  AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
+**/
+#define MSR_NEHALEM_PEBS_LD_LAT                  0x000003F6
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Minimum threshold latency value of tagged load operation
+    /// that will be counted. (R/W).
+    ///
+    UINT32  MinimumThreshold:16;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value