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authorDimitry Andric <dim@FreeBSD.org>2014-01-01 00:36:21 +0000
committerDimitry Andric <dim@FreeBSD.org>2014-01-01 00:36:21 +0000
commit512b84fc6c12bc496cef739e69bfaaf27e7ccc8e (patch)
treedb8b2c2435249ad6e3b71b8f74ba7fdf112bb6cb
parentf8af5cf600354830d4ccf59732403f0f073eccb9 (diff)
downloadsrc-512b84fc6c12bc496cef739e69bfaaf27e7ccc8e.tar.gz
src-512b84fc6c12bc496cef739e69bfaaf27e7ccc8e.zip
Vendor import of llvm RELEASE_34/final tag r197956 (effectively, 3.4 release):vendor/llvm/llvm-release_34-r197956
Notes
Notes: svn path=/vendor/llvm/dist/; revision=260146 svn path=/vendor/llvm/llvm-release_34-r197956/; revision=260147; tag=vendor/llvm/llvm-release_34-r197956
-rw-r--r--docs/ReleaseNotes.rst27
-rw-r--r--lib/ExecutionEngine/RTDyldMemoryManager.cpp2
2 files changed, 15 insertions, 14 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst
index 0874f3a3c522..94663c4aa09b 100644
--- a/docs/ReleaseNotes.rst
+++ b/docs/ReleaseNotes.rst
@@ -47,9 +47,9 @@ Non-comprehensive list of changes in this release
* The R600 backend is not marked experimental anymore and is built by default.
-* APFloat::isNormal() was renamed to APFloat::isFiniteNonZero() and
- APFloat::isIEEENormal() was renamed to APFloat::isNormal(). This ensures that
- APFloat::isNormal() conforms to IEEE-754R-2008.
+* ``APFloat::isNormal()`` was renamed to ``APFloat::isFiniteNonZero()`` and
+ ``APFloat::isIEEENormal()`` was renamed to ``APFloat::isNormal()``. This
+ ensures that ``APFloat::isNormal()`` conforms to IEEE-754R-2008.
* The library call simplification pass has been removed. Its functionality
has been integrated into the instruction combiner and function attribute
@@ -59,20 +59,20 @@ Non-comprehensive list of changes in this release
or later instead. For more information, see the `Getting Started using Visual
Studio <GettingStartedVS.html>`_ page.
-* The Loop Vectorizer that was previously enabled for -O3 is now enabled for
- -Os and -O2.
+* The Loop Vectorizer that was previously enabled for ``-O3`` is now enabled
+ for ``-Os`` and ``-O2``.
* The new SLP Vectorizer is now enabled by default.
-* llvm-ar now uses the new Object library and produces archives and
+* ``llvm-ar`` now uses the new Object library and produces archives and
symbol tables in the gnu format.
-* FileCheck now allows specifing -check-prefix multiple times. This
+* FileCheck now allows specifing ``-check-prefix`` multiple times. This
helps reduce duplicate check lines when using multiple RUN lines.
* The bitcast instruction no longer allows casting between pointers
- with different address spaces. To achieve this, use the new
- addrspacecast instruction.
+ with different address spaces. To achieve this, use the new addrspacecast
+ instruction.
* Different sized pointers for different address spaces should now
generally work. This is primarily useful for GPU targets.
@@ -84,8 +84,8 @@ Mips Target
-----------
Support for the MIPS SIMD Architecture (MSA) has been added. MSA is supported
-through inline assembly, intrinsics with the prefix '__builtin_msa', and normal
-code generation.
+through inline assembly, intrinsics with the prefix '``__builtin_msa``', and
+normal code generation.
For more information on MSA (including documentation for the instruction set),
see the `MIPS SIMD page at Imagination Technologies
@@ -96,11 +96,12 @@ PowerPC Target
Changes in the PowerPC backend include:
-* fast-isel support (for faster -O0 code generation)
+* fast-isel support (for faster ``-O0`` code generation)
* many improvements to the builtin assembler
* support for generating unaligned (Altivec) vector loads
* support for generating the fcpsgn instruction
-* generate frin for round() (not nearbyint() and rint(), which had been done only in fast-math mode)
+* generate ``frin`` for ``round()`` (not ``nearbyint()`` and ``rint()``, which
+ had been done only in fast-math mode)
* improved instruction scheduling for embedded cores (such as the A2)
* improved prologue/epilogue generation (especially in 32-bit mode)
* support for dynamic stack alignment (and dynamic stack allocations with large alignments)
diff --git a/lib/ExecutionEngine/RTDyldMemoryManager.cpp b/lib/ExecutionEngine/RTDyldMemoryManager.cpp
index 58a64609b9bc..26e1fddd7695 100644
--- a/lib/ExecutionEngine/RTDyldMemoryManager.cpp
+++ b/lib/ExecutionEngine/RTDyldMemoryManager.cpp
@@ -34,7 +34,7 @@ RTDyldMemoryManager::~RTDyldMemoryManager() {}
// Determine whether we can register EH tables.
#if (defined(__GNUC__) && !defined(__ARM_EABI__) && !defined(__ia64__) && \
- !defined(__USING_SJLJ_EXCEPTIONS__))
+ !defined(__SEH__) && !defined(__USING_SJLJ_EXCEPTIONS__))
#define HAVE_EHTABLE_SUPPORT 1
#else
#define HAVE_EHTABLE_SUPPORT 0