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authorAlexander Kabaev <kan@FreeBSD.org>2007-08-14 02:45:23 +0000
committerAlexander Kabaev <kan@FreeBSD.org>2007-08-14 02:45:23 +0000
commit23baddbde1e3e9e59547d9f4e0429ef69906b216 (patch)
tree7b2fa7d3de8706d9ca72fdb284ce2a57f67d460a
parent888346df5fa8bb2a862c2298910fe7ae332efbcb (diff)
downloadsrc-23baddbde1e3e9e59547d9f4e0429ef69906b216.tar.gz
src-23baddbde1e3e9e59547d9f4e0429ef69906b216.zip
GCC 4.2.1 release.
Notes
Notes: svn path=/vendor/gcc/dist/; revision=171825
-rw-r--r--contrib/gcc/BASE-VER2
-rw-r--r--contrib/gcc/ChangeLog441
-rw-r--r--contrib/gcc/DATESTAMP2
-rw-r--r--contrib/gcc/Makefile.in2
-rw-r--r--contrib/gcc/calls.c14
-rw-r--r--contrib/gcc/combine.c10
-rw-r--r--contrib/gcc/config/arm/arm.c2
-rw-r--r--contrib/gcc/config/arm/cirrus.md22
-rw-r--r--contrib/gcc/config/i386/i386.c23
-rw-r--r--contrib/gcc/config/i386/i386.h3
-rw-r--r--contrib/gcc/config/i386/i386.md18
-rw-r--r--contrib/gcc/config/i386/sse.md7
-rw-r--r--contrib/gcc/config/mips/iris6.h7
-rw-r--r--contrib/gcc/config/rs6000/predicates.md4
-rw-r--r--contrib/gcc/config/rs6000/rs6000.c3
-rw-r--r--contrib/gcc/config/soft-fp/double.h14
-rw-r--r--contrib/gcc/config/soft-fp/extended.h54
-rw-r--r--contrib/gcc/config/soft-fp/floatundidf.c5
-rw-r--r--contrib/gcc/config/soft-fp/floatundisf.c5
-rw-r--r--contrib/gcc/config/soft-fp/floatunsidf.c5
-rw-r--r--contrib/gcc/config/soft-fp/floatunsisf.c5
-rw-r--r--contrib/gcc/config/soft-fp/op-2.h4
-rw-r--r--contrib/gcc/config/soft-fp/op-4.h4
-rw-r--r--contrib/gcc/config/soft-fp/op-common.h40
-rw-r--r--contrib/gcc/config/soft-fp/quad.h18
-rw-r--r--contrib/gcc/config/sparc/sparc.c28
-rw-r--r--contrib/gcc/cp/ChangeLog90
-rw-r--r--contrib/gcc/cp/call.c32
-rw-r--r--contrib/gcc/cp/class.c20
-rw-r--r--contrib/gcc/cp/cp-tree.h22
-rw-r--r--contrib/gcc/cp/decl.c86
-rw-r--r--contrib/gcc/cp/decl2.c1
-rw-r--r--contrib/gcc/cp/init.c8
-rw-r--r--contrib/gcc/cp/parser.c14
-rw-r--r--contrib/gcc/cp/pt.c77
-rw-r--r--contrib/gcc/cp/semantics.c7
-rw-r--r--contrib/gcc/cp/typeck.c6
-rw-r--r--contrib/gcc/cp/typeck2.c7
-rw-r--r--contrib/gcc/doc/cpp.152
-rw-r--r--contrib/gcc/doc/gcc.110814
-rw-r--r--contrib/gcc/doc/gcov.197
-rw-r--r--contrib/gcc/dwarf2out.c4
-rw-r--r--contrib/gcc/except.c6
-rw-r--r--contrib/gcc/fold-const.c33
-rw-r--r--contrib/gcc/function.c8
-rw-r--r--contrib/gcc/gimplify.c28
-rw-r--r--contrib/gcc/gthr-posix.c5
-rw-r--r--contrib/gcc/gthr-posix.h8
-rw-r--r--contrib/gcc/loop-iv.c2
-rw-r--r--contrib/gcc/objc/ChangeLog4
-rw-r--r--contrib/gcc/omp-low.c46
-rw-r--r--contrib/gcc/pointer-set.c179
-rw-r--r--contrib/gcc/pointer-set.h12
-rw-r--r--contrib/gcc/reload.c5
-rw-r--r--contrib/gcc/tree-if-conv.c118
-rw-r--r--contrib/gcc/tree-ssa-loop-niter.c6
-rw-r--r--contrib/gcc/tree-ssa-operands.c9
-rw-r--r--contrib/gcc/tree-ssa-structalias.c2516
-rw-r--r--contrib/gcc/tree-vrp.c135
59 files changed, 9359 insertions, 5840 deletions
diff --git a/contrib/gcc/BASE-VER b/contrib/gcc/BASE-VER
index 6aba2b245a84..fae6e3d04b2c 100644
--- a/contrib/gcc/BASE-VER
+++ b/contrib/gcc/BASE-VER
@@ -1 +1 @@
-4.2.0
+4.2.1
diff --git a/contrib/gcc/ChangeLog b/contrib/gcc/ChangeLog
index eee0de5eaa02..136b464191e0 100644
--- a/contrib/gcc/ChangeLog
+++ b/contrib/gcc/ChangeLog
@@ -1,3 +1,441 @@
+2007-07-19 Release Manager
+
+ * GCC 4.2.1 released.
+
+2007-07-18 Paolo Bonzini <bonzini@gnu.org>
+
+ Revert:
+
+ 2007-07-09 Paolo Bonzini <bonzini@gnu.org>
+
+ PR middle-end/32004
+ * function.c (rest_of_match_asm_constraints): Pass PROP_REG_INFO.
+
+ 2007-07-06 Paolo Bonzini <bonzini@gnu.org>
+
+ PR middle-end/32004
+ * function.c (match_asm_constraints_1, rest_of_match_asm_constraints,
+ pass_match_asm_constraints): New.
+ * passes.c (init_optimization_passes): Add new pass.
+ * stmt.c (expand_asm_operands): Set cfun->has_asm_statement.
+ * function.h (struct function): Add has_asm_statement bit.
+ (current_function_has_asm_statement): New.
+ * tree-pass.h (pass_match_asm_constraints): New.
+
+2007-07-16 Paul Brook <paul@codesourcery.com>
+
+ PR target/32753
+ gcc/
+ * config/arm/cirrus.md (cirrus_arm_movsi_insn): Remove dead insn.
+
+2007-07-10 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
+
+ PR target/32538
+ * config/mips/iris6.h (LIBGCC_SPEC): Add libm.
+
+2007-07-09 Paolo Bonzini <bonzini@gnu.org>
+
+ PR middle-end/32004
+ * function.c (rest_of_match_asm_constraints): Pass PROP_REG_INFO.
+
+2007-07-09 Uros Bizjak <ubizjak@gmail.com>
+
+ PR tree-optimization/32681
+ * tree-if-conv.c (find_phi_replacement_condition): Use the condition
+ saved in second_edge->aux when first_bb is a loop header.
+
+2007-07-07 Anatoly Sokolov <aesok@post.ru>
+
+ PR target/31331
+ * config/avr/avr.c (avr_naked_function_p): Handle receiving a type
+ rather than a decl.
+ (avr_attribute_table): Make "naked" attribute apply to function types
+ rather than to decls.
+ (avr_handle_fntype_attribute): New function.
+
+2007-07-06 Paolo Bonzini <bonzini@gnu.org>
+
+ PR middle-end/32004
+ * function.c (match_asm_constraints_1, rest_of_match_asm_constraints,
+ pass_match_asm_constraints): New.
+ * passes.c (init_optimization_passes): Add new pass.
+ * stmt.c (expand_asm_operands): Set cfun->has_asm_statement.
+ * function.h (struct function): Add has_asm_statement bit.
+ (current_function_has_asm_statement): New.
+ * tree-pass.h (pass_match_asm_constraints): New.
+
+2007-07-06 Uros Bizjak <ubizjak@gmail.com>
+
+ PR rtl-optimization/32450
+ * function.c (thread_prologue_and_epilogue_insns): Emit blockage insn
+ to ensure that instructions are not moved into the prologue when
+ profiling is on.
+
+2007-07-04 Richard Guenther <rguenther@suse.de>
+
+ PR tree-optimization/32500
+ * tree-ssa-loop-niter.c (infer_loop_bounds_from_undefined):
+ Only use basic blocks that are always executed to infer loop bounds.
+
+2007-07-04 Uros Bizjak <ubizjak@gmail.com>
+
+ PR tree-optimization/31966
+ PR tree-optimization/32533
+ * tree-if-conv.c (add_to_dst_predicate_list): Use "edge", not
+ "basic_block" description as its third argument. Update function
+ calls to get destination bb from "edge" argument. Save "cond" into
+ aux field of the edge. Update prototype for changed arguments.
+ (if_convertible_loop_p): Clear aux field of incoming edges if bb
+ contains phi node.
+ (find_phi_replacement_condition): Operate on incoming edges, not
+ on predecessor blocks. If there is a condition saved in the
+ incoming edge aux field, AND it with incoming bb predicate.
+ Return source bb of the first edge.
+ (clean_predicate_lists): Clean aux field of outgoing node edges.
+ (tree_if_conversion): Do not initialize cond variable. Move
+ variable declaration into the loop.
+ (replace_phi_with_cond_gimple_modify_stmt): Remove unneded
+ initializations of new_stmt, arg0 and arg1 variables.
+
+2007-07-04 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ PR target/32506
+ Backport from mainline.
+ * config/sh/sh.md (udivsi3_i1_media): Use target_reg_operand
+ predicate instead of target_operand.
+ (divsi3_i1_media, divsi3_media_2): Likewise.
+
+2007-07-03 Richard Guenther <rguenther@suse.de>
+
+ Backport from mainline:
+ 2006-12-11 Zdenek Dvorak <dvorakz@suse.cz>
+
+ PR rtl-optimization/30113
+ * loop-iv.c (implies_p): Require the mode of the operands to be
+ scalar.
+
+2007-07-03 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
+
+ PR target/28307
+ * gthr-posix.h [SUPPORTS_WEAK && GTHREAD_USE_WEAK]
+ (__gthrw_pragma): Provide default definition.
+ (__gthrw2): Use it.
+ * gthr-posix.c (__gthrw_pragma): Define.
+
+2007-07-02 Jakub Jelinek <jakub@redhat.com>
+
+ PR libgomp/32468
+ * omp-low.c (check_combined_parallel): New function.
+ (lower_omp_parallel): Call it via walk_stmts, set
+ OMP_PARALLEL_COMBINED if appropriate.
+ (determine_parallel_type): If OMP_FOR resp. OMP_SECTIONS
+ isn't the only statement in WS_ENTRY_BB or OMP_RETURN
+ the only one in PAR_EXIT_BB and not OMP_PARALLEL_COMBINED,
+ don't consider it as combined parallel.
+
+2007-06-30 Alexandre Oliva <aoliva@redhat.com>
+
+ * dwarf2out.c (dwarf2out_finish): Accept namespaces as context of
+ limbo die nodes.
+
+2007-06-28 Seongbae Park <seongbae.park@gmail.com>
+
+ * config/arm/arm.c (arm_get_frame_offsets): Set
+ offsets->locals_base to avoid negative stack size.
+ (thumb_expand_prologue): Assert on negative stack size.
+
+2007-06-28 Jakub Jelinek <jakub@redhat.com>
+
+ * config/rs6000/rs6000.c (rs6000_function_ok_for_sibcall): Ensure
+ decl is non-external for AIX ABI.
+
+2007-06-28 David Edelsohn <edelsohn@gnu.org>
+
+ * config/rs6000/predicates.md (current_file_function_operand):
+ Ensure the symbol is non-external for AIX ABI.
+
+2007-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.c (ix86_builtins): Add IX86_BUILTIN_VEC_EXT_V16QI.
+ (ix86_init_mmx_sse_builtins): Add __builtin_ia32_vec_ext_v16qi.
+ (ix86_expand_builtin): Handle IX86_BUILTIN_VEC_EXT_V16QI.
+
+2007-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/32362
+ * omp-low.c (lookup_decl_in_outer_ctx): Don't ICE if t is NULL,
+ but decl is a global var, instead return decl.
+ * gimplify.c (gimplify_adjust_omp_clauses_1): Add shared clauses
+ even for is_global_var decls, if they are private in some outer
+ context.
+
+2007-06-21 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/32389
+ * config/i386/i386.h (enum ix86_stack_slot): Add SLOT_VIRTUAL.
+ * config/i386/i386.c (assign_386_stack_local): Assert that
+ SLOT_VIRTUAL is valid only before virtual regs are instantiated.
+ (ix86_expand_builtin) [IX86_BUILTIN_LDMXCSR, IX86_BUILTIN_STMXCSR]:
+ Use SLOT_VIRTUAL stack slot instead of SLOT_TEMP.
+ * config/i386/i386.md (truncdfsf2, truncxfsf2, truncxfdf2): Ditto.
+
+2007-06-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR inline-asm/32109
+ * gimplify.c (gimplify_asm_expr): Issue error if type is addressable
+ and !allows_mem.
+
+ PR middle-end/32285
+ * calls.c (precompute_arguments): Also precompute CALL_EXPR arguments
+ if ACCUMULATE_OUTGOING_ARGS.
+
+2007-06-20 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ PR rtl-optimization/28011
+ Backport from mainline.
+ * reload.c (push_reload): Set dont_share if IN appears in OUT
+ also when IN is a PLUS rtx.
+ (reg_overlap_mentioned_for_reload_p): Return true if X and IN
+ are same PLUS rtx.
+
+2007-06-19 Richard Guenther <rguenther@suse.de>
+ Michael Matz <matz@suse.de>
+
+ PR tree-optimization/30252
+ * tree-ssa-structalias.c (solution_set_add): Make sure to
+ preserve all relevant vars.
+ (handle_ptr_arith): Make sure to only handle positive
+ offsets.
+ (push_fields_onto_fieldstack): Create fields for empty
+ bases.
+
+2007-06-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/32353
+ * tree-ssa-structalias.c (set_uids_in_ptset): Also handle RESULT_DECL.
+
+2007-06-17 Eric Botcazou <ebotcazou@libertysurf.fr>
+
+ * config/sparc/sparc.c (sparc_vis_init_builtins): Retrieve the
+ return mode from the builtin itself.
+ (sparc_fold_builtin): Fix cast of zero constant.
+
+2007-06-15 Diego Novillo <dnovillo@google.com>
+
+ PR 32327
+ * tree-ssa-operands.c (build_ssa_operands): Initially assume
+ that the statement does not take any addresses.
+
+2007-06-13 Eric Botcazou <ebotcazou@libertysurf.fr>
+
+ * config/sparc/sparc.c (sparc_override_options): Initialize
+ fpu mask correctly.
+
+2007-06-09 Ian Lance Taylor <iant@google.com>
+
+ PR tree-optimization/32169
+ * tree-vrp.c (extract_range_from_unary_expr): For NOP_EXPR and
+ CONVERT_EXPR, check whether min and max both converted to an
+ overflow infinity representation.
+
+2007-06-08 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ PR target/32163
+ Backport from mainline.
+ * config/sh/sh.md (symGOT_load): Don't schedule insns when
+ the symbol is generated with the stack protector.
+
+2007-06-06 Ian Lance Taylor <iant@google.com>
+
+ * fold-const.c (merge_ranges): If range_successor or
+ range_predecessor fail, just return 0.
+
+2007-06-05 Ian Lance Taylor <iant@google.com>
+
+ * tree-vrp.c (compare_values_warnv): Check TREE_NO_WARNING on a
+ PLUS_EXPR or MINUS_EXPR node before setting *strict_overflow_p.
+ (extract_range_from_assert): Set TREE_NO_WARNING when creating an
+ expression.
+ (test_for_singularity): Likewise.
+
+2007-06-04 Ian Lance Taylor <iant@google.com>
+
+ * tree-vrp.c (adjust_range_with_scev): When loop is not expected
+ to overflow, reduce overflow infinity to regular infinity.
+ (vrp_var_may_overflow): New static function.
+ (vrp_visit_phi_node): Check vrp_var_may_overflow.
+
+2007-05-31 H.J. Lu <hongjiu.lu@intel.com>
+
+ Backport from mainline:
+ 2007-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.c (__builtin_ia32_vec_ext_v2df): Mark it
+ with MASK_SSE2.
+ (__builtin_ia32_vec_ext_v2di): Likewise.
+ (__builtin_ia32_vec_ext_v4si): Likewise.
+ (__builtin_ia32_vec_ext_v8hi): Likewise.
+ (__builtin_ia32_vec_set_v8hi): Likewise.
+
+2007-05-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ Backport from mainline:
+ 2007-05-05 Aurelien Jarno <aurelien@aurel32.net>
+
+ * config/pa/pa.md: Split tgd_load, tld_load and tie_load
+ into pic and non-pic versions. Mark r19 as used for
+ tgd_load_pic, tld_load_pic and tie_load_pic. Mark r27 as used
+ for tgd_load, tld_load and tie_load .
+ * config/pa/pa.c (legitimize_tls_address): Emit pic or non-pic
+ version of tgd_load, tld_load and tie_load depending on the
+ value of flag_pic.
+
+2007-05-27 Daniel Berlin <dberlin@dberlin.org>
+
+ Fix PR/30052
+ Backport PTA solver from mainline
+
+ * pointer-set.c: Copy from mainline
+ * pointer-set.h: Ditto.
+ * tree-ssa-structalias.c: Copy solver portions from mainline.
+ * Makefile.in (tree-ssa-structalias.o): Update dependencies
+
+2007-05-30 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+
+ * tree-vrp.c (compare_names): Initialize sop.
+
+2007-05-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/31769
+ * except.c (duplicate_eh_regions): Clear prev_try if
+ ERT_MUST_NOT_THROW region is inside of ERT_TRY region.
+
+2007-05-28 Andrew Pinski <andrew_pinski@playstation.sony.com>
+
+ PR tree-opt/32100
+ * fold-const.c (tree_expr_nonnegative_warnv_p): Don't
+ return true when truth_value_p is true and the type
+ is of signed:1.
+
+2007-05-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ Backport from mainline:
+ 2007-05-25 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/sse.md (*vec_extractv2di_1_sse2): Do not calculate
+ "memory" attribute for "sseishft" type insn without operands[2].
+
+ 2007-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/sse.md (*vec_extractv2di_1_sse2): Correct shift.
+
+2007-05-22 Ian Lance Taylor <iant@google.com>
+
+ * tree-vrp.c (avoid_overflow_infinity): New static function,
+ broken out of set_value_range_to_value.
+ (set_value_range_to_value): Call avoid_overflow_infinity.
+ (extract_range_from_assert): Likewise.
+
+2007-05-23 Chen Liqin <liqin@sunnorth.com.cn>
+
+ PR target/30987
+ * config/score/misc.md (bitclr_c, bitset_c, bittgl_c): remove.
+ * config/score/predicate.md (const_pow2, const_npow2): remove.
+ * config/score/score.h (ASM_OUTPUT_EXTERNAL): add ASM_OUTPUT_EXTERNAL undef.
+ PR target/30474
+ * config/score/score.c (score_print_operand): makes sure that only lower
+ bits are used.
+
+2007-05-21 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/31167
+ Backport from mainline.
+ * config/i386/i386.md (*addti3_1, *addti3_1 splitter): Use
+ x86_64_general_operand as operand[2] predicate. Remove "iF"
+ from operand constraints and use "e" constraint instead.
+ (*subti3_1, *subti3_1 splitter): Ditto.
+ (*negti2_1, *negti2_1 splitter): Use nonimmediate_operand as
+ operand[1] predicate.
+
+2007-05-21 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/30041
+ Backport from mainline.
+ * config/i386/sse.md ("*sse3_movddup"): Use operands[0] and
+ operands[1] in insn constraint. Correct type attribute to sselog1.
+
+2007-05-20 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ PR target/31701
+ Backport from mainline.
+ * config/sh/sh.c (output_stack_adjust): Avoid using the frame
+ register itself to hold the offset constant. Tell flow the use
+ of r4 and r5 when they are used.
+
+2007-05-20 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ PR target/31480
+ Backport from mainline.
+ * config/sh/sh.md (length): Check if prev_nonnote_insn (insn)
+ is null.
+
+2007-05-20 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ PR target/31022
+ Backport from mainline.
+ * config/sh/sh.c (sh_adjust_cost): Use the result of single_set
+ instead of PATTERN.
+
+2007-05-20 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ PR target/27405
+ Backport from mainline.
+ * config/sh/sh.md (cmp{eq,gt,gtu}{si,di}_media): Remove.
+ (cmpsi{eq,gt,gtu}{si,di}_media): Rename to
+ cmp{eq,gt,gtu}{si,di}_media.
+ (*cmpne0si_media): Remove.
+ (*movsicc_umin): Adjust gen_cmp*_media call.
+ (unordered): Change the mode of unordered and operands[1] to
+ SImode.
+ (seq): Adjust gen_cmp*_media calls. Make the mode of
+ a temporary result of compare SImode if needed. If the mode
+ of operands[0] is DImode, extend the temporary result to DImode.
+ (slt, sle, sgt, sge, sgtu, sltu, sleu, sgue, sne): Likewise.
+ (sunorderd): Change the mode of match_operand and unorderd to
+ SImode.
+ (cmpeq{sf,df}_media): Remove.
+ (cmpsieq{sf,df}_media): Rename to cmpeq{sf,df}_media.
+ (cmp{gt,ge,un}{sf,df}_media): Change the mode of match_operand
+ and compare operation to SImode.
+
+2007-05-18 Joseph Myers <joseph@codesourcery.com>
+
+ * config/soft-fp/double.h, config/soft-fp/extended.h,
+ config/soft-fp/floatundidf.c, config/soft-fp/floatundisf.c,
+ config/soft-fp/floatunsidf.c, config/soft-fp/floatunsisf.c,
+ config/soft-fp/op-2.h, config/soft-fp/op-4.h,
+ config/soft-fp/op-common.h, config/soft-fp/quad.h: Update from
+ glibc CVS.
+
+2007-05-17 Ian Lance Taylor <iant@google.com>
+
+ PR tree-optimization/31953
+ * tree-vrp.c (set_value_range_to_value): Add equiv parameter.
+ Change all callers.
+ (set_value_range_to_null): Call set_value_range_to_value.
+ (extract_range_from_comparison): Likewise.
+
+2007-05-17 Eric Botcazou <ebotcazou@libertysurf.fr>
+
+ PR rtl-optimization/31691
+ * combine.c (simplify_set): Build a new src pattern instead of
+ substituting its operands in the COMPARE case.
+
+2007-05-14 Mark Mitchell <mark@codesourcery.com>
+
+ * BASE-VER: Set to 4.2.1.
+ * DEV-PHASE: Set to prerelease.
+
2007-05-13 Release Manager
* GCC 4.2.0 released.
@@ -307,7 +745,8 @@
2007-04-03 Stuart Hastings <stuart@apple.com>
PR 31281
- * objc/objc-act.c (next_sjlj_build_catch_list): Delete volatile from rethrow decl.
+ * objc/objc-act.c (next_sjlj_build_catch_list): Delete volatile
+ from rethrow decl.
* cse.c (record_jump_equiv): Bail out on CCmode comparisons.
2007-04-03 Jakub Jelinek <jakub@redhat.com>
diff --git a/contrib/gcc/DATESTAMP b/contrib/gcc/DATESTAMP
index 9fa4bc3e86ac..38e56c588fe2 100644
--- a/contrib/gcc/DATESTAMP
+++ b/contrib/gcc/DATESTAMP
@@ -1 +1 @@
-20070514
+20070719
diff --git a/contrib/gcc/Makefile.in b/contrib/gcc/Makefile.in
index 8c02cceedad7..e48d86370c72 100644
--- a/contrib/gcc/Makefile.in
+++ b/contrib/gcc/Makefile.in
@@ -1839,7 +1839,7 @@ stor-layout.o : stor-layout.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
tree-ssa-structalias.o: tree-ssa-structalias.c tree-ssa-structalias.h \
$(SYSTEM_H) $(CONFIG_H) $(GGC_H) $(TREE_H) $(TREE_FLOW_H) \
$(TM_H) coretypes.h $(CGRAPH_H) tree-pass.h $(TIMEVAR_H) \
- gt-tree-ssa-structalias.h $(PARAMS_H)
+ gt-tree-ssa-structalias.h $(PARAMS_H) pointer-set.h
tree-ssa.o : tree-ssa.c $(TREE_FLOW_H) $(CONFIG_H) $(SYSTEM_H) \
$(RTL_H) $(TREE_H) $(TM_P_H) $(EXPR_H) output.h $(DIAGNOSTIC_H) \
toplev.h $(FUNCTION_H) $(TIMEVAR_H) $(TM_H) coretypes.h \
diff --git a/contrib/gcc/calls.c b/contrib/gcc/calls.c
index 063e6847e98b..d1fcdadda33e 100644
--- a/contrib/gcc/calls.c
+++ b/contrib/gcc/calls.c
@@ -1238,13 +1238,25 @@ precompute_arguments (int flags, int num_actuals, struct arg_data *args)
/* If this is a libcall, then precompute all arguments so that we do not
get extraneous instructions emitted as part of the libcall sequence. */
- if ((flags & ECF_LIBCALL_BLOCK) == 0)
+
+ /* If we preallocated the stack space, and some arguments must be passed
+ on the stack, then we must precompute any parameter which contains a
+ function call which will store arguments on the stack.
+ Otherwise, evaluating the parameter may clobber previous parameters
+ which have already been stored into the stack. (we have code to avoid
+ such case by saving the outgoing stack arguments, but it results in
+ worse code) */
+ if ((flags & ECF_LIBCALL_BLOCK) == 0 && !ACCUMULATE_OUTGOING_ARGS)
return;
for (i = 0; i < num_actuals; i++)
{
enum machine_mode mode;
+ if ((flags & ECF_LIBCALL_BLOCK) == 0
+ && TREE_CODE (args[i].tree_value) != CALL_EXPR)
+ continue;
+
/* If this is an addressable type, we cannot pre-evaluate it. */
gcc_assert (!TREE_ADDRESSABLE (TREE_TYPE (args[i].tree_value)));
diff --git a/contrib/gcc/combine.c b/contrib/gcc/combine.c
index 512882e79d01..c5655ea40380 100644
--- a/contrib/gcc/combine.c
+++ b/contrib/gcc/combine.c
@@ -5341,14 +5341,14 @@ simplify_set (rtx x)
}
else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
{
- SUBST(SET_SRC (x), op0);
+ SUBST (SET_SRC (x), op0);
src = SET_SRC (x);
}
- else
+ /* Otherwise, update the COMPARE if needed. */
+ else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
{
- /* Otherwise, update the COMPARE if needed. */
- SUBST (XEXP (src, 0), op0);
- SUBST (XEXP (src, 1), op1);
+ SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
+ src = SET_SRC (x);
}
}
else
diff --git a/contrib/gcc/config/arm/arm.c b/contrib/gcc/config/arm/arm.c
index dc7aa77b6d6a..670e7912d293 100644
--- a/contrib/gcc/config/arm/arm.c
+++ b/contrib/gcc/config/arm/arm.c
@@ -10555,6 +10555,7 @@ arm_get_frame_offsets (void)
if (leaf && frame_size == 0)
{
offsets->outgoing_args = offsets->soft_frame;
+ offsets->locals_base = offsets->soft_frame;
return offsets;
}
@@ -13874,6 +13875,7 @@ thumb_expand_epilogue (void)
amount = offsets->locals_base - offsets->saved_regs;
}
+ gcc_assert (amount >= 0);
if (amount)
{
if (amount < 512)
diff --git a/contrib/gcc/config/arm/cirrus.md b/contrib/gcc/config/arm/cirrus.md
index b857cbb2084c..052198906c70 100644
--- a/contrib/gcc/config/arm/cirrus.md
+++ b/contrib/gcc/config/arm/cirrus.md
@@ -404,28 +404,6 @@
;; Cirrus SI values have been outlawed. Look in arm.h for the comment
;; on HARD_REGNO_MODE_OK.
-(define_insn "*cirrus_arm_movsi_insn"
- [(set (match_operand:SI 0 "general_operand" "=r,r,r,m,*v,r,*v,T,*v")
- (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,*v,T,*v,*v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
- "@
- mov%?\\t%0, %1
- mvn%?\\t%0, #%B1
- ldr%?\\t%0, %1
- str%?\\t%1, %0
- cfmv64lr%?\\t%Z0, %1
- cfmvr64l%?\\t%0, %Z1
- cfldr32%?\\t%V0, %1
- cfstr32%?\\t%V1, %0
- cfsh32%?\\t%V0, %V1, #0"
- [(set_attr "type" "*, *, load1,store1, *, *, load1,store1, *")
- (set_attr "pool_range" "*, *, 4096, *, *, *, 1024, *, *")
- (set_attr "neg_pool_range" "*, *, 4084, *, *, *, 1012, *, *")
- (set_attr "cirrus" "not,not, not, not,move,normal,normal,normal,normal")]
-)
-
(define_insn "*cirrus_movsf_hard_insn"
[(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
(match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
diff --git a/contrib/gcc/config/i386/i386.c b/contrib/gcc/config/i386/i386.c
index 29afed7cf019..729dd408d7cb 100644
--- a/contrib/gcc/config/i386/i386.c
+++ b/contrib/gcc/config/i386/i386.c
@@ -13478,6 +13478,9 @@ assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
gcc_assert (n < MAX_386_STACK_LOCALS);
+ /* Virtual slot is valid only before vregs are instantiated. */
+ gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
+
for (s = ix86_stack_locals; s; s = s->next)
if (s->mode == mode && s->n == n)
return s->rtl;
@@ -14567,6 +14570,7 @@ enum ix86_builtins
IX86_BUILTIN_VEC_EXT_V4SF,
IX86_BUILTIN_VEC_EXT_V4SI,
IX86_BUILTIN_VEC_EXT_V8HI,
+ IX86_BUILTIN_VEC_EXT_V16QI,
IX86_BUILTIN_VEC_EXT_V2SI,
IX86_BUILTIN_VEC_EXT_V4HI,
IX86_BUILTIN_VEC_SET_V8HI,
@@ -15539,13 +15543,13 @@ ix86_init_mmx_sse_builtins (void)
/* Access to the vec_extract patterns. */
ftype = build_function_type_list (double_type_node, V2DF_type_node,
integer_type_node, NULL_TREE);
- def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2df",
+ def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v2df",
ftype, IX86_BUILTIN_VEC_EXT_V2DF);
ftype = build_function_type_list (long_long_integer_type_node,
V2DI_type_node, integer_type_node,
NULL_TREE);
- def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2di",
+ def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v2di",
ftype, IX86_BUILTIN_VEC_EXT_V2DI);
ftype = build_function_type_list (float_type_node, V4SF_type_node,
@@ -15555,12 +15559,12 @@ ix86_init_mmx_sse_builtins (void)
ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
integer_type_node, NULL_TREE);
- def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si",
+ def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v4si",
ftype, IX86_BUILTIN_VEC_EXT_V4SI);
ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
integer_type_node, NULL_TREE);
- def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi",
+ def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v8hi",
ftype, IX86_BUILTIN_VEC_EXT_V8HI);
ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
@@ -15573,11 +15577,15 @@ ix86_init_mmx_sse_builtins (void)
def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
ftype, IX86_BUILTIN_VEC_EXT_V2SI);
+ ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
+ integer_type_node, NULL_TREE);
+ def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
+
/* Access to the vec_set patterns. */
ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
intHI_type_node,
integer_type_node, NULL_TREE);
- def_builtin (MASK_SSE, "__builtin_ia32_vec_set_v8hi",
+ def_builtin (MASK_SSE2, "__builtin_ia32_vec_set_v8hi",
ftype, IX86_BUILTIN_VEC_SET_V8HI);
ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
@@ -16121,13 +16129,13 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
case IX86_BUILTIN_LDMXCSR:
op0 = expand_normal (TREE_VALUE (arglist));
- target = assign_386_stack_local (SImode, SLOT_TEMP);
+ target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
emit_move_insn (target, op0);
emit_insn (gen_sse_ldmxcsr (target));
return 0;
case IX86_BUILTIN_STMXCSR:
- target = assign_386_stack_local (SImode, SLOT_TEMP);
+ target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
emit_insn (gen_sse_stmxcsr (target));
return copy_to_mode_reg (SImode, target);
@@ -16489,6 +16497,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
case IX86_BUILTIN_VEC_EXT_V4SF:
case IX86_BUILTIN_VEC_EXT_V4SI:
case IX86_BUILTIN_VEC_EXT_V8HI:
+ case IX86_BUILTIN_VEC_EXT_V16QI:
case IX86_BUILTIN_VEC_EXT_V2SI:
case IX86_BUILTIN_VEC_EXT_V4HI:
return ix86_expand_vec_ext_builtin (arglist, target);
diff --git a/contrib/gcc/config/i386/i386.h b/contrib/gcc/config/i386/i386.h
index ba732dc32ddd..1adb1a55c291 100644
--- a/contrib/gcc/config/i386/i386.h
+++ b/contrib/gcc/config/i386/i386.h
@@ -2164,7 +2164,8 @@ enum ix86_entity
enum ix86_stack_slot
{
- SLOT_TEMP = 0,
+ SLOT_VIRTUAL = 0,
+ SLOT_TEMP,
SLOT_CW_STORED,
SLOT_CW_TRUNC,
SLOT_CW_FLOOR,
diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md
index d24b32af42eb..f7481ed8c063 100644
--- a/contrib/gcc/config/i386/i386.md
+++ b/contrib/gcc/config/i386/i386.md
@@ -3716,7 +3716,7 @@
;
else
{
- rtx temp = assign_386_stack_local (SFmode, SLOT_TEMP);
+ rtx temp = assign_386_stack_local (SFmode, SLOT_VIRTUAL);
emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
DONE;
}
@@ -3868,7 +3868,7 @@
DONE;
}
else
- operands[2] = assign_386_stack_local (SFmode, SLOT_TEMP);
+ operands[2] = assign_386_stack_local (SFmode, SLOT_VIRTUAL);
})
(define_insn "*truncxfsf2_mixed"
@@ -3966,7 +3966,7 @@
DONE;
}
else
- operands[2] = assign_386_stack_local (DFmode, SLOT_TEMP);
+ operands[2] = assign_386_stack_local (DFmode, SLOT_VIRTUAL);
})
(define_insn "*truncxfdf2_mixed"
@@ -4749,7 +4749,7 @@
(define_insn "*addti3_1"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0,0")
- (match_operand:TI 2 "general_operand" "roiF,riF")))
+ (match_operand:TI 2 "x86_64_general_operand" "roe,re")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, TImode, operands)"
"#")
@@ -4757,7 +4757,7 @@
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "general_operand" "")))
+ (match_operand:TI 2 "x86_64_general_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed"
[(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
@@ -6483,7 +6483,7 @@
(define_insn "*subti3_1"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
(minus:TI (match_operand:TI 1 "nonimmediate_operand" "0,0")
- (match_operand:TI 2 "general_operand" "roiF,riF")))
+ (match_operand:TI 2 "x86_64_general_operand" "roe,re")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, TImode, operands)"
"#")
@@ -6491,7 +6491,7 @@
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "general_operand" "")))
+ (match_operand:TI 2 "x86_64_general_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed"
[(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
@@ -9326,7 +9326,7 @@
(define_insn "*negti2_1"
[(set (match_operand:TI 0 "nonimmediate_operand" "=ro")
- (neg:TI (match_operand:TI 1 "general_operand" "0")))
+ (neg:TI (match_operand:TI 1 "nonimmediate_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& ix86_unary_operator_ok (NEG, TImode, operands)"
@@ -9334,7 +9334,7 @@
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
- (neg:TI (match_operand:TI 1 "general_operand" "")))
+ (neg:TI (match_operand:TI 1 "nonimmediate_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed"
[(parallel
diff --git a/contrib/gcc/config/i386/sse.md b/contrib/gcc/config/i386/sse.md
index 96361e0b6caf..15817fcb1262 100644
--- a/contrib/gcc/config/i386/sse.md
+++ b/contrib/gcc/config/i386/sse.md
@@ -2055,11 +2055,11 @@
(match_dup 1))
(parallel [(const_int 0)
(const_int 2)])))]
- "TARGET_SSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ "TARGET_SSE3 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
movddup\t{%1, %0|%0, %1}
#"
- [(set_attr "type" "sselog,ssemov")
+ [(set_attr "type" "sselog1,ssemov")
(set_attr "mode" "V2DF")])
(define_split
@@ -3494,9 +3494,10 @@
"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
movhps\t{%1, %0|%0, %1}
- psrldq\t{$4, %0|%0, 4}
+ psrldq\t{$8, %0|%0, 8}
movq\t{%H1, %0|%0, %H1}"
[(set_attr "type" "ssemov,sseishft,ssemov")
+ (set_attr "memory" "*,none,*")
(set_attr "mode" "V2SF,TI,TI")])
;; Not sure this is ever used, but it doesn't hurt to have it. -aoliva
diff --git a/contrib/gcc/config/mips/iris6.h b/contrib/gcc/config/mips/iris6.h
index 8686b14fa944..87d9a219bbd2 100644
--- a/contrib/gcc/config/mips/iris6.h
+++ b/contrib/gcc/config/mips/iris6.h
@@ -1,6 +1,6 @@
/* Definitions of target machine for GNU compiler. IRIX version 6.
Copyright (C) 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
- 2005, 2006
+ 2005, 2006, 2007
Free Software Foundation, Inc.
This file is part of GCC.
@@ -96,10 +96,11 @@ Boston, MA 02110-1301, USA. */
" %{pthread:-lpthread} %{p:libprof1.a%s}%{pg:libprof1.a%s} -lc " \
SUBTARGET_WARN_UNUSED_SPEC "}"
-/* Avoid getting two warnings for libgcc.a everytime we link. */
+/* Avoid getting two warnings for libgcc.a everytime we link. libgcc.a
+ contains references to copysignl, so link with libm to resolve them. */
#undef LIBGCC_SPEC
#define LIBGCC_SPEC \
- SUBTARGET_DONT_WARN_UNUSED_SPEC " -lgcc " SUBTARGET_WARN_UNUSED_SPEC
+ SUBTARGET_DONT_WARN_UNUSED_SPEC " -lgcc -lm " SUBTARGET_WARN_UNUSED_SPEC
#undef ENDFILE_SPEC
#define ENDFILE_SPEC \
diff --git a/contrib/gcc/config/rs6000/predicates.md b/contrib/gcc/config/rs6000/predicates.md
index 6aefe2dd0c98..65231e1a61ae 100644
--- a/contrib/gcc/config/rs6000/predicates.md
+++ b/contrib/gcc/config/rs6000/predicates.md
@@ -694,7 +694,9 @@
(define_predicate "current_file_function_operand"
(and (match_code "symbol_ref")
(match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
- && (SYMBOL_REF_LOCAL_P (op)
+ && ((SYMBOL_REF_LOCAL_P (op)
+ && (DEFAULT_ABI != ABI_AIX
+ || !SYMBOL_REF_EXTERNAL_P (op)))
|| (op == XEXP (DECL_RTL (current_function_decl),
0)))")))
diff --git a/contrib/gcc/config/rs6000/rs6000.c b/contrib/gcc/config/rs6000/rs6000.c
index 5e9d0fef02e7..6670a2034f20 100644
--- a/contrib/gcc/config/rs6000/rs6000.c
+++ b/contrib/gcc/config/rs6000/rs6000.c
@@ -13515,7 +13515,8 @@ rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
}
}
if (DEFAULT_ABI == ABI_DARWIN
- || (*targetm.binds_local_p) (decl))
+ || ((*targetm.binds_local_p) (decl)
+ && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
{
tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
diff --git a/contrib/gcc/config/soft-fp/double.h b/contrib/gcc/config/soft-fp/double.h
index c8f4420af859..b012d9d51be7 100644
--- a/contrib/gcc/config/soft-fp/double.h
+++ b/contrib/gcc/config/soft-fp/double.h
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Definitions for IEEE Double Precision
- Copyright (C) 1997,1998,1999,2006 Free Software Foundation, Inc.
+ Copyright (C) 1997,1998,1999,2006,2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Richard Henderson (rth@cygnus.com),
Jakub Jelinek (jj@ultra.linux.cz),
@@ -168,13 +168,13 @@ union _FP_UNION_D
DFtype flt;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
- unsigned sign : 1;
- unsigned exp : _FP_EXPBITS_D;
- unsigned long frac : _FP_FRACBITS_D - (_FP_IMPLBIT_D != 0);
+ unsigned sign : 1;
+ unsigned exp : _FP_EXPBITS_D;
+ _FP_W_TYPE frac : _FP_FRACBITS_D - (_FP_IMPLBIT_D != 0);
#else
- unsigned long frac : _FP_FRACBITS_D - (_FP_IMPLBIT_D != 0);
- unsigned exp : _FP_EXPBITS_D;
- unsigned sign : 1;
+ _FP_W_TYPE frac : _FP_FRACBITS_D - (_FP_IMPLBIT_D != 0);
+ unsigned exp : _FP_EXPBITS_D;
+ unsigned sign : 1;
#endif
} bits __attribute__((packed));
};
diff --git a/contrib/gcc/config/soft-fp/extended.h b/contrib/gcc/config/soft-fp/extended.h
index bbf39429e7f7..e5f16debecb9 100644
--- a/contrib/gcc/config/soft-fp/extended.h
+++ b/contrib/gcc/config/soft-fp/extended.h
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Definitions for IEEE Extended Precision.
- Copyright (C) 1999,2006 Free Software Foundation, Inc.
+ Copyright (C) 1999,2006,2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Jakub Jelinek (jj@ultra.linux.cz).
@@ -94,12 +94,6 @@ union _FP_UNION_E
X##_f[1] = _flo.bits.frac1; \
X##_e = _flo.bits.exp; \
X##_s = _flo.bits.sign; \
- if (!X##_e && (X##_f[1] || X##_f[0]) \
- && !(X##_f[1] & _FP_IMPLBIT_E)) \
- { \
- X##_e++; \
- FP_SET_EXCEPTION(FP_EX_DENORM); \
- } \
} while (0)
#define FP_UNPACK_RAW_EP(X, val) \
@@ -112,12 +106,6 @@ union _FP_UNION_E
X##_f[1] = _flo->bits.frac1; \
X##_e = _flo->bits.exp; \
X##_s = _flo->bits.sign; \
- if (!X##_e && (X##_f[1] || X##_f[0]) \
- && !(X##_f[1] & _FP_IMPLBIT_E)) \
- { \
- X##_e++; \
- FP_SET_EXCEPTION(FP_EX_DENORM); \
- } \
} while (0)
#define FP_PACK_RAW_E(val, X) \
@@ -164,13 +152,13 @@ union _FP_UNION_E
#define FP_UNPACK_SEMIRAW_E(X,val) \
do { \
- _FP_UNPACK_RAW_E(X,val); \
+ FP_UNPACK_RAW_E(X,val); \
_FP_UNPACK_SEMIRAW(E,4,X); \
} while (0)
#define FP_UNPACK_SEMIRAW_EP(X,val) \
do { \
- _FP_UNPACK_RAW_EP(X,val); \
+ FP_UNPACK_RAW_EP(X,val); \
_FP_UNPACK_SEMIRAW(E,4,X); \
} while (0)
@@ -189,13 +177,13 @@ union _FP_UNION_E
#define FP_PACK_SEMIRAW_E(val,X) \
do { \
_FP_PACK_SEMIRAW(E,4,X); \
- _FP_PACK_RAW_E(val,X); \
+ FP_PACK_RAW_E(val,X); \
} while (0)
#define FP_PACK_SEMIRAW_EP(val,X) \
do { \
_FP_PACK_SEMIRAW(E,4,X); \
- _FP_PACK_RAW_EP(val,X); \
+ FP_PACK_RAW_EP(val,X); \
} while (0)
#define FP_ISSIGNAN_E(X) _FP_ISSIGNAN(E,4,X)
@@ -277,14 +265,14 @@ union _FP_UNION_E
XFtype flt;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
- unsigned long pad : (_FP_W_TYPE_SIZE - 1 - _FP_EXPBITS_E);
- unsigned sign : 1;
- unsigned exp : _FP_EXPBITS_E;
- unsigned long frac : _FP_W_TYPE_SIZE;
+ _FP_W_TYPE pad : (_FP_W_TYPE_SIZE - 1 - _FP_EXPBITS_E);
+ unsigned sign : 1;
+ unsigned exp : _FP_EXPBITS_E;
+ _FP_W_TYPE frac : _FP_W_TYPE_SIZE;
#else
- unsigned long frac : _FP_W_TYPE_SIZE;
- unsigned exp : _FP_EXPBITS_E;
- unsigned sign : 1;
+ _FP_W_TYPE frac : _FP_W_TYPE_SIZE;
+ unsigned exp : _FP_EXPBITS_E;
+ unsigned sign : 1;
#endif
} bits;
};
@@ -299,11 +287,6 @@ union _FP_UNION_E
X##_f1 = 0; \
X##_e = _flo.bits.exp; \
X##_s = _flo.bits.sign; \
- if (!X##_e && X##_f0 && !(X##_f0 & _FP_IMPLBIT_E)) \
- { \
- X##_e++; \
- FP_SET_EXCEPTION(FP_EX_DENORM); \
- } \
} while (0)
#define FP_UNPACK_RAW_EP(X, val) \
@@ -315,11 +298,6 @@ union _FP_UNION_E
X##_f1 = 0; \
X##_e = _flo->bits.exp; \
X##_s = _flo->bits.sign; \
- if (!X##_e && X##_f0 && !(X##_f0 & _FP_IMPLBIT_E)) \
- { \
- X##_e++; \
- FP_SET_EXCEPTION(FP_EX_DENORM); \
- } \
} while (0)
#define FP_PACK_RAW_E(val, X) \
@@ -365,13 +343,13 @@ union _FP_UNION_E
#define FP_UNPACK_SEMIRAW_E(X,val) \
do { \
- _FP_UNPACK_RAW_E(X,val); \
+ FP_UNPACK_RAW_E(X,val); \
_FP_UNPACK_SEMIRAW(E,2,X); \
} while (0)
#define FP_UNPACK_SEMIRAW_EP(X,val) \
do { \
- _FP_UNPACK_RAW_EP(X,val); \
+ FP_UNPACK_RAW_EP(X,val); \
_FP_UNPACK_SEMIRAW(E,2,X); \
} while (0)
@@ -390,13 +368,13 @@ union _FP_UNION_E
#define FP_PACK_SEMIRAW_E(val,X) \
do { \
_FP_PACK_SEMIRAW(E,2,X); \
- _FP_PACK_RAW_E(val,X); \
+ FP_PACK_RAW_E(val,X); \
} while (0)
#define FP_PACK_SEMIRAW_EP(val,X) \
do { \
_FP_PACK_SEMIRAW(E,2,X); \
- _FP_PACK_RAW_EP(val,X); \
+ FP_PACK_RAW_EP(val,X); \
} while (0)
#define FP_ISSIGNAN_E(X) _FP_ISSIGNAN(E,2,X)
diff --git a/contrib/gcc/config/soft-fp/floatundidf.c b/contrib/gcc/config/soft-fp/floatundidf.c
index 2169a3f19889..af8e4a5aefe8 100644
--- a/contrib/gcc/config/soft-fp/floatundidf.c
+++ b/contrib/gcc/config/soft-fp/floatundidf.c
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Convert a 64bit unsigned integer to IEEE double
- Copyright (C) 1997,1999, 2006 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1999, 2006, 2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Richard Henderson (rth@cygnus.com) and
Jakub Jelinek (jj@ultra.linux.cz).
@@ -32,8 +32,7 @@
#include "soft-fp.h"
#include "double.h"
-double
-__floatundidf(UDItype i)
+DFtype __floatundidf(UDItype i)
{
FP_DECL_EX;
FP_DECL_D(A);
diff --git a/contrib/gcc/config/soft-fp/floatundisf.c b/contrib/gcc/config/soft-fp/floatundisf.c
index 5f08764dc50c..977f7dfc79f9 100644
--- a/contrib/gcc/config/soft-fp/floatundisf.c
+++ b/contrib/gcc/config/soft-fp/floatundisf.c
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Convert a 64bit unsigned integer to IEEE single
- Copyright (C) 1997,1999, 2006 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1999, 2006, 2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Richard Henderson (rth@cygnus.com) and
Jakub Jelinek (jj@ultra.linux.cz).
@@ -32,8 +32,7 @@
#include "soft-fp.h"
#include "single.h"
-float
-__floatundisf(UDItype i)
+SFtype __floatundisf(UDItype i)
{
FP_DECL_EX;
FP_DECL_S(A);
diff --git a/contrib/gcc/config/soft-fp/floatunsidf.c b/contrib/gcc/config/soft-fp/floatunsidf.c
index 97b488ab68a3..12d0f25bf0fe 100644
--- a/contrib/gcc/config/soft-fp/floatunsidf.c
+++ b/contrib/gcc/config/soft-fp/floatunsidf.c
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Convert a 32bit unsigned integer to IEEE double
- Copyright (C) 1997,1999, 2006 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1999, 2006, 2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Richard Henderson (rth@cygnus.com) and
Jakub Jelinek (jj@ultra.linux.cz).
@@ -32,8 +32,7 @@
#include "soft-fp.h"
#include "double.h"
-double
-__floatunsidf(USItype i)
+DFtype __floatunsidf(USItype i)
{
FP_DECL_EX;
FP_DECL_D(A);
diff --git a/contrib/gcc/config/soft-fp/floatunsisf.c b/contrib/gcc/config/soft-fp/floatunsisf.c
index 2ec16ba7b7f9..80c5d3d359fa 100644
--- a/contrib/gcc/config/soft-fp/floatunsisf.c
+++ b/contrib/gcc/config/soft-fp/floatunsisf.c
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Convert a 32bit unsigned integer to IEEE single
- Copyright (C) 1997,1999, 2006 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1999, 2006, 2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Richard Henderson (rth@cygnus.com) and
Jakub Jelinek (jj@ultra.linux.cz).
@@ -32,8 +32,7 @@
#include "soft-fp.h"
#include "single.h"
-float
-__floatunsisf(USItype i)
+SFtype __floatunsisf(USItype i)
{
FP_DECL_EX;
FP_DECL_S(A);
diff --git a/contrib/gcc/config/soft-fp/op-2.h b/contrib/gcc/config/soft-fp/op-2.h
index 5c9bce4c1792..3a3b3aa06913 100644
--- a/contrib/gcc/config/soft-fp/op-2.h
+++ b/contrib/gcc/config/soft-fp/op-2.h
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Basic two-word fraction declaration and manipulation.
- Copyright (C) 1997,1998,1999,2006 Free Software Foundation, Inc.
+ Copyright (C) 1997,1998,1999,2006,2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Richard Henderson (rth@cygnus.com),
Jakub Jelinek (jj@ultra.linux.cz),
@@ -613,3 +613,5 @@
#define _FP_FRAC_COPY_1_2(D, S) (D##_f = S##_f0)
#define _FP_FRAC_COPY_2_1(D, S) ((D##_f0 = S##_f), (D##_f1 = 0))
+
+#define _FP_FRAC_COPY_2_2(D,S) _FP_FRAC_COPY_2(D,S)
diff --git a/contrib/gcc/config/soft-fp/op-4.h b/contrib/gcc/config/soft-fp/op-4.h
index 1b90535c56e5..70b9fafbe5a5 100644
--- a/contrib/gcc/config/soft-fp/op-4.h
+++ b/contrib/gcc/config/soft-fp/op-4.h
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Basic four-word fraction declaration and manipulation.
- Copyright (C) 1997,1998,1999,2006 Free Software Foundation, Inc.
+ Copyright (C) 1997,1998,1999,2006,2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Richard Henderson (rth@cygnus.com),
Jakub Jelinek (jj@ultra.linux.cz),
@@ -684,3 +684,5 @@ do { \
D##_f[1] = S##_f1; \
D##_f[2] = D##_f[3] = 0; \
} while (0)
+
+#define _FP_FRAC_COPY_4_4(D,S) _FP_FRAC_COPY_4(D,S)
diff --git a/contrib/gcc/config/soft-fp/op-common.h b/contrib/gcc/config/soft-fp/op-common.h
index 0aa6e3e05d84..ef11b527b706 100644
--- a/contrib/gcc/config/soft-fp/op-common.h
+++ b/contrib/gcc/config/soft-fp/op-common.h
@@ -1153,7 +1153,8 @@ do { \
if (_FP_FRACBITS_##dfs < _FP_FRACBITS_##sfs \
|| (_FP_EXPMAX_##dfs - _FP_EXPBIAS_##dfs \
< _FP_EXPMAX_##sfs - _FP_EXPBIAS_##sfs) \
- || _FP_EXPBIAS_##dfs < _FP_EXPBIAS_##sfs + _FP_FRACBITS_##sfs - 1) \
+ || (_FP_EXPBIAS_##dfs < _FP_EXPBIAS_##sfs + _FP_FRACBITS_##sfs - 1 \
+ && _FP_EXPBIAS_##dfs != _FP_EXPBIAS_##sfs)) \
abort(); \
D##_s = S##_s; \
_FP_FRAC_COPY_##dwc##_##swc(D, S); \
@@ -1168,6 +1169,14 @@ do { \
{ \
if (_FP_FRAC_ZEROP_##swc(S)) \
D##_e = 0; \
+ else if (_FP_EXPBIAS_##dfs \
+ < _FP_EXPBIAS_##sfs + _FP_FRACBITS_##sfs - 1) \
+ { \
+ FP_SET_EXCEPTION(FP_EX_DENORM); \
+ _FP_FRAC_SLL_##dwc(D, (_FP_FRACBITS_##dfs \
+ - _FP_FRACBITS_##sfs)); \
+ D##_e = 0; \
+ } \
else \
{ \
int _lz; \
@@ -1199,7 +1208,8 @@ do { \
#define FP_TRUNC(dfs,sfs,dwc,swc,D,S) \
do { \
if (_FP_FRACBITS_##sfs < _FP_FRACBITS_##dfs \
- || _FP_EXPBIAS_##sfs < _FP_EXPBIAS_##dfs + _FP_FRACBITS_##dfs - 1) \
+ || (_FP_EXPBIAS_##sfs < _FP_EXPBIAS_##dfs + _FP_FRACBITS_##dfs - 1 \
+ && _FP_EXPBIAS_##sfs != _FP_EXPBIAS_##dfs)) \
abort(); \
D##_s = S##_s; \
if (_FP_EXP_NORMAL(sfs, swc, S)) \
@@ -1211,8 +1221,11 @@ do { \
{ \
if (D##_e <= 0) \
{ \
- if (D##_e <= 1 - _FP_FRACBITS_##dfs) \
- _FP_FRAC_SET_##swc(S, _FP_ZEROFRAC_##swc); \
+ if (D##_e < 1 - _FP_FRACBITS_##dfs) \
+ { \
+ _FP_FRAC_SET_##swc(S, _FP_ZEROFRAC_##swc); \
+ _FP_FRAC_LOW_##swc(S) |= 1; \
+ } \
else \
{ \
_FP_FRAC_HIGH_##sfs(S) |= _FP_IMPLBIT_SH_##sfs; \
@@ -1234,11 +1247,24 @@ do { \
if (S##_e == 0) \
{ \
D##_e = 0; \
- _FP_FRAC_SET_##dwc(D, _FP_ZEROFRAC_##dwc); \
- if (!_FP_FRAC_ZEROP_##swc(S)) \
+ if (_FP_FRAC_ZEROP_##swc(S)) \
+ _FP_FRAC_SET_##dwc(D, _FP_ZEROFRAC_##dwc); \
+ else \
{ \
FP_SET_EXCEPTION(FP_EX_DENORM); \
- FP_SET_EXCEPTION(FP_EX_INEXACT); \
+ if (_FP_EXPBIAS_##sfs \
+ < _FP_EXPBIAS_##dfs + _FP_FRACBITS_##dfs - 1) \
+ { \
+ _FP_FRAC_SRS_##swc(S, (_FP_WFRACBITS_##sfs \
+ - _FP_WFRACBITS_##dfs), \
+ _FP_WFRACBITS_##sfs); \
+ _FP_FRAC_COPY_##dwc##_##swc(D, S); \
+ } \
+ else \
+ { \
+ _FP_FRAC_SET_##dwc(D, _FP_ZEROFRAC_##dwc); \
+ _FP_FRAC_LOW_##dwc(D) |= 1; \
+ } \
} \
} \
else \
diff --git a/contrib/gcc/config/soft-fp/quad.h b/contrib/gcc/config/soft-fp/quad.h
index d7840ff06623..c22e944029f4 100644
--- a/contrib/gcc/config/soft-fp/quad.h
+++ b/contrib/gcc/config/soft-fp/quad.h
@@ -1,6 +1,6 @@
/* Software floating-point emulation.
Definitions for IEEE Quad Precision.
- Copyright (C) 1997,1998,1999,2006 Free Software Foundation, Inc.
+ Copyright (C) 1997,1998,1999,2006,2007 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Richard Henderson (rth@cygnus.com),
Jakub Jelinek (jj@ultra.linux.cz),
@@ -176,15 +176,15 @@ union _FP_UNION_Q
} longs;
struct {
#if __BYTE_ORDER == __BIG_ENDIAN
- unsigned sign : 1;
- unsigned exp : _FP_EXPBITS_Q;
- unsigned long frac1 : _FP_FRACBITS_Q-(_FP_IMPLBIT_Q != 0)-_FP_W_TYPE_SIZE;
- unsigned long frac0 : _FP_W_TYPE_SIZE;
+ unsigned sign : 1;
+ unsigned exp : _FP_EXPBITS_Q;
+ _FP_W_TYPE frac1 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0) - _FP_W_TYPE_SIZE;
+ _FP_W_TYPE frac0 : _FP_W_TYPE_SIZE;
#else
- unsigned long frac0 : _FP_W_TYPE_SIZE;
- unsigned long frac1 : _FP_FRACBITS_Q-(_FP_IMPLBIT_Q != 0)-_FP_W_TYPE_SIZE;
- unsigned exp : _FP_EXPBITS_Q;
- unsigned sign : 1;
+ _FP_W_TYPE frac0 : _FP_W_TYPE_SIZE;
+ _FP_W_TYPE frac1 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0) - _FP_W_TYPE_SIZE;
+ unsigned exp : _FP_EXPBITS_Q;
+ unsigned sign : 1;
#endif
} bits;
};
diff --git a/contrib/gcc/config/sparc/sparc.c b/contrib/gcc/config/sparc/sparc.c
index 692e46e55843..738264aa3454 100644
--- a/contrib/gcc/config/sparc/sparc.c
+++ b/contrib/gcc/config/sparc/sparc.c
@@ -703,7 +703,7 @@ sparc_override_options (void)
error ("-mcmodel= is not supported on 32 bit systems");
}
- fpu = TARGET_FPU; /* save current -mfpu status */
+ fpu = target_flags & MASK_FPU; /* save current -mfpu status */
/* Set the default CPU. */
for (def = &cpu_default[0]; def->name; ++def)
@@ -7968,8 +7968,10 @@ sparc_vis_init_builtins (void)
Expand builtin functions for sparc intrinsics. */
static rtx
-sparc_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
- enum machine_mode tmode, int ignore ATTRIBUTE_UNUSED)
+sparc_expand_builtin (tree exp, rtx target,
+ rtx subtarget ATTRIBUTE_UNUSED,
+ enum machine_mode tmode ATTRIBUTE_UNUSED,
+ int ignore ATTRIBUTE_UNUSED)
{
tree arglist;
tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
@@ -7978,14 +7980,13 @@ sparc_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
enum machine_mode mode[4];
int arg_count = 0;
- mode[arg_count] = tmode;
-
- if (target == 0
- || GET_MODE (target) != tmode
- || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
- op[arg_count] = gen_reg_rtx (tmode);
+ mode[0] = insn_data[icode].operand[0].mode;
+ if (!target
+ || GET_MODE (target) != mode[0]
+ || ! (*insn_data[icode].operand[0].predicate) (target, mode[0]))
+ op[0] = gen_reg_rtx (mode[0]);
else
- op[arg_count] = target;
+ op[0] = target;
for (arglist = TREE_OPERAND (exp, 1); arglist;
arglist = TREE_CHAIN (arglist))
@@ -8101,11 +8102,11 @@ sparc_fold_builtin (tree fndecl, tree arglist, bool ignore)
{
tree arg0, arg1, arg2;
tree rtype = TREE_TYPE (TREE_TYPE (fndecl));
-
- if (ignore && DECL_FUNCTION_CODE (fndecl) != CODE_FOR_alignaddrsi_vis
+ if (ignore
+ && DECL_FUNCTION_CODE (fndecl) != CODE_FOR_alignaddrsi_vis
&& DECL_FUNCTION_CODE (fndecl) != CODE_FOR_alignaddrdi_vis)
- return build_int_cst (rtype, 0);
+ return fold_convert (rtype, integer_zero_node);
switch (DECL_FUNCTION_CODE (fndecl))
{
@@ -8219,6 +8220,7 @@ sparc_fold_builtin (tree fndecl, tree arglist, bool ignore)
default:
break;
}
+
return NULL_TREE;
}
diff --git a/contrib/gcc/cp/ChangeLog b/contrib/gcc/cp/ChangeLog
index e2cc82e4013d..34c036f01c17 100644
--- a/contrib/gcc/cp/ChangeLog
+++ b/contrib/gcc/cp/ChangeLog
@@ -1,3 +1,93 @@
+2007-07-19 Release Manager
+
+ * GCC 4.2.1 released.
+
+2007-07-07 Mark Mitchell <mark@codesourcery.com>
+
+ PR c++/32232
+ * pt.c (resolve_overloaded_unification): Robustify. Return a
+ bool, not an int.
+ (type_unification_real): Adjust accordingly.
+
+2007-07-06 Mark Mitchell <mark@codesourcery.com>
+
+ PR c++/32245
+ * init.c (build_zero_init): Always build an initializer for
+ non-static storage.
+ * typeck2.c (build_functional_cast): Use build_zero_init.
+
+ PR c++/32251
+ * init.c (build_new_1): Always pass the allocation function to
+ build_op_delete_call.
+ * call.c (build_op_delete_call): Handle operator delete with a
+ variable-argument list. Do not issue an error when no matching
+ deallocation function is available for a new operator.
+
+ PR c++/31992
+ * cp-tree.h (any_value_dependent_elements_p): Declare it.
+ * decl.c (value_dependent_init_p): New function.
+ (cp_finish_decl): Use it.
+ * pt.c (value_dependent_expression_p): Use
+ any_value_dependent_elements_p.
+ * parser.c (cp_parser_primary_expression): Add comment about
+ treating dependent qualified names as integral
+ constant-expressions.
+
+2007-07-03 Mark Mitchell <mark@codesourcery.com>
+
+ PR c++/31338
+ * cp-tree.h (ARITHMETIC_TYPE): Include COMPLEX_TYPE.
+ * typeck.c (type_after_usual_arithmetic_conversions): Adjust, as
+ COMPLEX_TYPE is now an ARITHMETIC_TYPE.
+ * init.c (build_zero_init): Adjust, as
+ COMPLEX_TYPE is now a SCALAR_TYPE.
+ * typeck2.c (digest_init): Allow brace-enclosed initializers for
+ COMPLEX_TYPE, even though that is now a SCALAR_TYPE.
+
+2007-07-03 Richard Guenther <rguenther@suse.de>
+
+ PR c++/32609
+ * class.c (fixed_type_or_null): Re-lookup the hashtable slot
+ after recursing.
+
+2007-07-02 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/31748
+ * semantics.c (finish_omp_clauses): Use %qD instead of %qE for
+ DECL_P in not a variable and appears more than once error messages.
+
+2007-06-27 Simon Martin <simartin@users.sourceforge.net>
+
+ PR c++/27492
+ * decl.c (duplicate_decls): Don't reset DECL_INVALID_OVERRIDER_P for
+ function decls.
+
+2007-06-15 Mark Mitchell <mark@codesourcery.com>
+
+ * cp-tree.h (DECL_VAR_MARKED_P): Remove.
+ (DECL_ANON_UNION_VAR_P): New macro.
+ * class.c (fixed_type_or_null): Tidy. Use a hash table, rather
+ than DECL_VAR_MARKED_P, to keep track of which variables we have
+ seen.
+ * decl.c (redeclaration_error_message): Complain about redeclaring
+ anonymous union members at namespace scope.
+ * decl2.c (build_anon_union_vars): Set DECL_ANON_UNION_VAR_P.
+
+2007-06-08 Dirk Mueller <dmueller@suse.de>
+
+ PR c++/31809
+ PR c++/31806
+ Backport from mainline:
+ 2007-05-31 Jakub Jelinek <jakub@redhat.com>
+
+ * decl.c (cp_finish_decl): Also clear was_readonly if a static var
+ needs runtime initialization.
+
+ 2007-05-30 Jakub Jelinek <jakub@redhat.com>
+
+ * decl.c (cp_finish_decl): Clear TREE_READONLY flag on TREE_STATIC
+ variables that need runtime initialization.
+
2007-05-13 Release Manager
* GCC 4.2.0 released.
diff --git a/contrib/gcc/cp/call.c b/contrib/gcc/cp/call.c
index 6d6740a44fec..862c3d0ecca1 100644
--- a/contrib/gcc/cp/call.c
+++ b/contrib/gcc/cp/call.c
@@ -3985,8 +3985,12 @@ build_new_op (enum tree_code code, int flags, tree arg1, tree arg2, tree arg3,
GLOBAL_P is true if the delete-expression should not consider
class-specific delete operators.
PLACEMENT is the corresponding placement new call, or NULL_TREE.
- If PLACEMENT is non-NULL, then ALLOC_FN is the allocation function
- called to perform the placement new. */
+
+ If this call to "operator delete" is being generated as part to
+ deallocate memory allocated via a new-expression (as per [expr.new]
+ which requires that if the initialization throws an exception then
+ we call a deallocation function), then ALLOC_FN is the allocation
+ function. */
tree
build_op_delete_call (enum tree_code code, tree addr, tree size,
@@ -4077,9 +4081,13 @@ build_op_delete_call (enum tree_code code, tree addr, tree size,
if (!a && !t)
break;
}
- /* On the second pass, the second argument must be
- "size_t". */
+ /* On the second pass, look for a function with exactly two
+ arguments: "void *" and "size_t". */
else if (pass == 1
+ /* For "operator delete(void *, ...)" there will be
+ no second argument, but we will not get an exact
+ match above. */
+ && t
&& same_type_p (TREE_VALUE (t), sizetype)
&& TREE_CHAIN (t) == void_list_node)
break;
@@ -4119,10 +4127,18 @@ build_op_delete_call (enum tree_code code, tree addr, tree size,
return build_function_call (fn, args);
}
- /* If we are doing placement delete we do nothing if we don't find a
- matching op delete. */
- if (placement)
- return NULL_TREE;
+ /* [expr.new]
+
+ If no unambiguous matching deallocation function can be found,
+ propagating the exception does not cause the object's memory to
+ be freed. */
+ if (alloc_fn)
+ {
+ if (!placement)
+ warning (0, "no corresponding deallocation function for `%D'",
+ alloc_fn);
+ return NULL_TREE;
+ }
error ("no suitable %<operator %s%> for %qT",
operator_name_info[(int)code].name, type);
diff --git a/contrib/gcc/cp/class.c b/contrib/gcc/cp/class.c
index ff1d84bbdefa..1f30524acf80 100644
--- a/contrib/gcc/cp/class.c
+++ b/contrib/gcc/cp/class.c
@@ -5350,22 +5350,34 @@ fixed_type_or_null (tree instance, int* nonnull, int* cdtorp)
}
else if (TREE_CODE (TREE_TYPE (instance)) == REFERENCE_TYPE)
{
+ /* We only need one hash table because it is always left empty. */
+ static htab_t ht;
+ if (!ht)
+ ht = htab_create (37,
+ htab_hash_pointer,
+ htab_eq_pointer,
+ /*htab_del=*/NULL);
+
/* Reference variables should be references to objects. */
if (nonnull)
*nonnull = 1;
- /* DECL_VAR_MARKED_P is used to prevent recursion; a
+ /* Enter the INSTANCE in a table to prevent recursion; a
variable's initializer may refer to the variable
itself. */
if (TREE_CODE (instance) == VAR_DECL
&& DECL_INITIAL (instance)
- && !DECL_VAR_MARKED_P (instance))
+ && !htab_find (ht, instance))
{
tree type;
- DECL_VAR_MARKED_P (instance) = 1;
+ void **slot;
+
+ slot = htab_find_slot (ht, instance, INSERT);
+ *slot = instance;
type = fixed_type_or_null (DECL_INITIAL (instance),
nonnull, cdtorp);
- DECL_VAR_MARKED_P (instance) = 0;
+ htab_remove_elt (ht, instance);
+
return type;
}
}
diff --git a/contrib/gcc/cp/cp-tree.h b/contrib/gcc/cp/cp-tree.h
index 7cdf362bf8a5..9e0342a3903a 100644
--- a/contrib/gcc/cp/cp-tree.h
+++ b/contrib/gcc/cp/cp-tree.h
@@ -107,7 +107,7 @@ struct diagnostic_context;
DECL_IMPLICIT_TYPEDEF_P (in a TYPE_DECL)
3: DECL_IN_AGGR_P.
4: DECL_C_BIT_FIELD (in a FIELD_DECL)
- DECL_VAR_MARKED_P (in a VAR_DECL)
+ DECL_ANON_UNION_VAR_P (in a VAR_DECL)
DECL_SELF_REFERENCE_P (in a TYPE_DECL)
DECL_INVALID_OVERRIDER_P (in a FUNCTION_DECL)
5: DECL_INTERFACE_KNOWN.
@@ -2111,10 +2111,10 @@ extern void decl_shadowed_for_var_insert (tree, tree);
(DECL_LANG_SPECIFIC (VAR_TEMPL_TYPE_OR_FUNCTION_DECL_CHECK (NODE)) \
->decl_flags.u.template_info)
-/* For a VAR_DECL, indicates that the variable has been processed.
- This flag is set and unset throughout the code; it is always
- used for a temporary purpose. */
-#define DECL_VAR_MARKED_P(NODE) \
+/* For a VAR_DECL, indicates that the variable is actually a
+ non-static data member of anonymous union that has been promoted to
+ variable status. */
+#define DECL_ANON_UNION_VAR_P(NODE) \
(DECL_LANG_FLAG_4 (VAR_DECL_CHECK (NODE)))
/* Template information for a RECORD_TYPE or UNION_TYPE. */
@@ -2418,14 +2418,21 @@ extern void decl_shadowed_for_var_insert (tree, tree);
/* [basic.fundamental]
Integral and floating types are collectively called arithmetic
- types. Keep these checks in ascending code order. */
+ types.
+
+ As a GNU extension, we also accept complex types.
+
+ Keep these checks in ascending code order. */
#define ARITHMETIC_TYPE_P(TYPE) \
- (CP_INTEGRAL_TYPE_P (TYPE) || TREE_CODE (TYPE) == REAL_TYPE)
+ (CP_INTEGRAL_TYPE_P (TYPE) \
+ || TREE_CODE (TYPE) == REAL_TYPE \
+ || TREE_CODE (TYPE) == COMPLEX_TYPE)
/* [basic.types]
Arithmetic types, enumeration types, pointer types, and
pointer-to-member types, are collectively called scalar types.
+
Keep these checks in ascending code order. */
#define SCALAR_TYPE_P(TYPE) \
(TYPE_PTRMEM_P (TYPE) \
@@ -4146,6 +4153,7 @@ extern bool dependent_template_id_p (tree, tree);
extern bool type_dependent_expression_p (tree);
extern bool any_type_dependent_arguments_p (tree);
extern bool value_dependent_expression_p (tree);
+extern bool any_value_dependent_elements_p (tree);
extern tree resolve_typename_type (tree, bool);
extern tree template_for_substitution (tree);
extern tree build_non_dependent_expr (tree);
diff --git a/contrib/gcc/cp/decl.c b/contrib/gcc/cp/decl.c
index c3d71bcdd4e1..28e653b0751e 100644
--- a/contrib/gcc/cp/decl.c
+++ b/contrib/gcc/cp/decl.c
@@ -1573,6 +1573,7 @@ duplicate_decls (tree newdecl, tree olddecl, bool newdecl_is_friend)
DECL_STATIC_DESTRUCTOR (newdecl) |= DECL_STATIC_DESTRUCTOR (olddecl);
DECL_PURE_VIRTUAL_P (newdecl) |= DECL_PURE_VIRTUAL_P (olddecl);
DECL_VIRTUAL_P (newdecl) |= DECL_VIRTUAL_P (olddecl);
+ DECL_INVALID_OVERRIDER_P (newdecl) |= DECL_INVALID_OVERRIDER_P (olddecl);
DECL_THIS_STATIC (newdecl) |= DECL_THIS_STATIC (olddecl);
if (DECL_OVERLOADED_OPERATOR_P (olddecl) != ERROR_MARK)
SET_OVERLOADED_OPERATOR_CODE
@@ -2161,8 +2162,24 @@ redeclaration_error_message (tree newdecl, tree olddecl)
}
else if (toplevel_bindings_p () || DECL_NAMESPACE_SCOPE_P (newdecl))
{
- /* Objects declared at top level: */
- /* If at least one is a reference, it's ok. */
+ /* The objects have been declared at namespace scope. If either
+ is a member of an anonymous union, then this is an invalid
+ redeclaration. For example:
+
+ int i;
+ union { int i; };
+
+ is invalid. */
+ if (DECL_ANON_UNION_VAR_P (newdecl)
+ || DECL_ANON_UNION_VAR_P (olddecl))
+ return "redeclaration of %q#D";
+ /* If at least one declaration is a reference, there is no
+ conflict. For example:
+
+ int i = 3;
+ extern int i;
+
+ is valid. */
if (DECL_EXTERNAL (newdecl) || DECL_EXTERNAL (olddecl))
return NULL;
/* Reject two definitions. */
@@ -5076,6 +5093,36 @@ initialize_artificial_var (tree decl, tree init)
make_rtl_for_nonlocal_decl (decl, init, /*asmspec=*/NULL);
}
+/* INIT is the initializer for a variable, as represented by the
+ parser. Returns true iff INIT is value-dependent. */
+
+static bool
+value_dependent_init_p (tree init)
+{
+ if (TREE_CODE (init) == TREE_LIST)
+ /* A parenthesized initializer, e.g.: int i (3, 2); ? */
+ return any_value_dependent_elements_p (init);
+ else if (TREE_CODE (init) == CONSTRUCTOR)
+ /* A brace-enclosed initializer, e.g.: int i = { 3 }; ? */
+ {
+ VEC(constructor_elt, gc) *elts;
+ size_t nelts;
+ size_t i;
+
+ elts = CONSTRUCTOR_ELTS (init);
+ nelts = VEC_length (constructor_elt, elts);
+ for (i = 0; i < nelts; ++i)
+ if (value_dependent_init_p (VEC_index (constructor_elt,
+ elts, i)->value))
+ return true;
+ }
+ else
+ /* It must be a simple expression, e.g., int i = 3; */
+ return value_dependent_expression_p (init);
+
+ return false;
+}
+
/* Finish processing of a declaration;
install its line number and initial value.
If the length of an array type is not known before,
@@ -5148,18 +5195,16 @@ cp_finish_decl (tree decl, tree init, bool init_const_expr_p,
TREE_CONSTANT (decl) = 1;
}
- if (!init
- || !DECL_CLASS_SCOPE_P (decl)
- || !DECL_INTEGRAL_CONSTANT_VAR_P (decl)
- || type_dependent_p
- || value_dependent_expression_p (init)
- /* Check also if initializer is a value dependent
- { integral_constant_expression }. */
- || (TREE_CODE (init) == CONSTRUCTOR
- && VEC_length (constructor_elt, CONSTRUCTOR_ELTS (init)) == 1
- && value_dependent_expression_p
- (VEC_index (constructor_elt,
- CONSTRUCTOR_ELTS (init), 0)->value)))
+ /* Generally, initializers in templates are expanded when the
+ template is instantiated. But, if DECL is an integral
+ constant static data member, then it can be used in future
+ integral constant expressions, and its value must be
+ available. */
+ if (!(init
+ && DECL_CLASS_SCOPE_P (decl)
+ && DECL_INTEGRAL_CONSTANT_VAR_P (decl)
+ && !type_dependent_p
+ && !value_dependent_init_p (init)))
{
if (init)
DECL_INITIAL (decl) = init;
@@ -5368,7 +5413,18 @@ cp_finish_decl (tree decl, tree init, bool init_const_expr_p,
initializer. It is not legal to redeclare a static data
member, so this issue does not arise in that case. */
if (var_definition_p && TREE_STATIC (decl))
- expand_static_init (decl, init);
+ {
+ /* If a TREE_READONLY variable needs initialization
+ at runtime, it is no longer readonly and we need to
+ avoid MEM_READONLY_P being set on RTL created for it. */
+ if (init)
+ {
+ if (TREE_READONLY (decl))
+ TREE_READONLY (decl) = 0;
+ was_readonly = 0;
+ }
+ expand_static_init (decl, init);
+ }
}
}
diff --git a/contrib/gcc/cp/decl2.c b/contrib/gcc/cp/decl2.c
index 8e1a70111560..00bcc16b7a5a 100644
--- a/contrib/gcc/cp/decl2.c
+++ b/contrib/gcc/cp/decl2.c
@@ -1056,6 +1056,7 @@ build_anon_union_vars (tree type, tree object)
tree base;
decl = build_decl (VAR_DECL, DECL_NAME (field), TREE_TYPE (field));
+ DECL_ANON_UNION_VAR_P (decl) = 1;
base = get_base_address (object);
TREE_PUBLIC (decl) = TREE_PUBLIC (base);
diff --git a/contrib/gcc/cp/init.c b/contrib/gcc/cp/init.c
index 0ea68882ee9d..70bc76470f1c 100644
--- a/contrib/gcc/cp/init.c
+++ b/contrib/gcc/cp/init.c
@@ -178,8 +178,7 @@ build_zero_init (tree type, tree nelts, bool static_storage_p)
items with static storage duration that are not otherwise
initialized are initialized to zero. */
;
- else if (SCALAR_TYPE_P (type)
- || TREE_CODE (type) == COMPLEX_TYPE)
+ else if (SCALAR_TYPE_P (type))
init = convert (type, integer_zero_node);
else if (CLASS_TYPE_P (type))
{
@@ -196,7 +195,7 @@ build_zero_init (tree type, tree nelts, bool static_storage_p)
corresponding to base classes as well. Thus, iterating
over TYPE_FIELDs will result in correct initialization of
all of the subobjects. */
- if (static_storage_p && !zero_init_p (TREE_TYPE (field)))
+ if (!static_storage_p || !zero_init_p (TREE_TYPE (field)))
{
tree value = build_zero_init (TREE_TYPE (field),
/*nelts=*/NULL_TREE,
@@ -1970,8 +1969,7 @@ build_new_1 (tree placement, tree type, tree nelts, tree init,
globally_qualified_p,
(placement_allocation_fn_p
? alloc_call : NULL_TREE),
- (placement_allocation_fn_p
- ? alloc_fn : NULL_TREE));
+ alloc_fn);
if (!cleanup)
/* We're done. */;
diff --git a/contrib/gcc/cp/parser.c b/contrib/gcc/cp/parser.c
index 62097ab37dc1..e060d49c343b 100644
--- a/contrib/gcc/cp/parser.c
+++ b/contrib/gcc/cp/parser.c
@@ -3197,7 +3197,19 @@ cp_parser_primary_expression (cp_parser *parser,
/* If name lookup gives us a SCOPE_REF, then the
qualifying scope was dependent. */
if (TREE_CODE (decl) == SCOPE_REF)
- return decl;
+ {
+ /* At this point, we do not know if DECL is a valid
+ integral constant expression. We assume that it is
+ in fact such an expression, so that code like:
+
+ template <int N> struct A {
+ int a[B<N>::i];
+ };
+
+ is accepted. At template-instantiation time, we
+ will check that B<N>::i is actually a constant. */
+ return decl;
+ }
/* Check to see if DECL is a local variable in a context
where that is forbidden. */
if (parser->local_variables_forbidden_p
diff --git a/contrib/gcc/cp/pt.c b/contrib/gcc/cp/pt.c
index cca1f38a2730..477265d49d0d 100644
--- a/contrib/gcc/cp/pt.c
+++ b/contrib/gcc/cp/pt.c
@@ -91,8 +91,8 @@ static htab_t local_specializations;
static void push_access_scope (tree);
static void pop_access_scope (tree);
-static int resolve_overloaded_unification (tree, tree, tree, tree,
- unification_kind_t, int);
+static bool resolve_overloaded_unification (tree, tree, tree, tree,
+ unification_kind_t, int);
static int try_one_overload (tree, tree, tree, tree, tree,
unification_kind_t, int, bool);
static int unify (tree, tree, tree, tree, int);
@@ -9943,17 +9943,18 @@ type_unification_real (tree tparms,
gcc_assert (TREE_TYPE (arg) != NULL_TREE);
if (type_unknown_p (arg))
{
- /* [temp.deduct.type] A template-argument can be deduced from
- a pointer to function or pointer to member function
- argument if the set of overloaded functions does not
- contain function templates and at most one of a set of
- overloaded functions provides a unique match. */
+ /* [temp.deduct.type]
+ A template-argument can be deduced from a pointer to
+ function or pointer to member function argument if
+ the set of overloaded functions does not contain
+ function templates and at most one of a set of
+ overloaded functions provides a unique match. */
if (resolve_overloaded_unification
- (tparms, targs, parm, arg, strict, sub_strict)
- != 0)
- return 1;
- continue;
+ (tparms, targs, parm, arg, strict, sub_strict))
+ continue;
+
+ return 1;
}
arg = unlowered_expr_type (arg);
if (arg == error_mark_node)
@@ -10006,12 +10007,13 @@ type_unification_real (tree tparms,
return 0;
}
-/* Subroutine of type_unification_real. Args are like the variables at the
- call site. ARG is an overloaded function (or template-id); we try
- deducing template args from each of the overloads, and if only one
- succeeds, we go with that. Modifies TARGS and returns 0 on success. */
+/* Subroutine of type_unification_real. Args are like the variables
+ at the call site. ARG is an overloaded function (or template-id);
+ we try deducing template args from each of the overloads, and if
+ only one succeeds, we go with that. Modifies TARGS and returns
+ true on success. */
-static int
+static bool
resolve_overloaded_unification (tree tparms,
tree targs,
tree parm,
@@ -10070,16 +10072,17 @@ resolve_overloaded_unification (tree tparms,
}
}
}
+ else if (TREE_CODE (arg) != OVERLOAD
+ && TREE_CODE (arg) != FUNCTION_DECL)
+ /* If ARG is, for example, "(0, &f)" then its type will be unknown
+ -- but the deduction does not succeed because the expression is
+ not just the function on its own. */
+ return false;
else
- {
- gcc_assert (TREE_CODE (arg) == OVERLOAD
- || TREE_CODE (arg) == FUNCTION_DECL);
-
- for (; arg; arg = OVL_NEXT (arg))
- good += try_one_overload (tparms, targs, tempargs, parm,
- TREE_TYPE (OVL_CURRENT (arg)),
- strict, sub_strict, addr_p);
- }
+ for (; arg; arg = OVL_NEXT (arg))
+ good += try_one_overload (tparms, targs, tempargs, parm,
+ TREE_TYPE (OVL_CURRENT (arg)),
+ strict, sub_strict, addr_p);
/* [temp.deduct.type] A template-argument can be deduced from a pointer
to function or pointer to member function argument if the set of
@@ -10097,9 +10100,9 @@ resolve_overloaded_unification (tree tparms,
TREE_VEC_ELT (targs, i) = TREE_VEC_ELT (tempargs, i);
}
if (good)
- return 0;
+ return true;
- return 1;
+ return false;
}
/* Subroutine of resolve_overloaded_unification; does deduction for a single
@@ -12895,12 +12898,7 @@ value_dependent_expression_p (tree expression)
}
if (TREE_CODE (expression) == TREE_LIST)
- {
- for (; expression; expression = TREE_CHAIN (expression))
- if (value_dependent_expression_p (TREE_VALUE (expression)))
- return true;
- return false;
- }
+ return any_value_dependent_elements_p (expression);
return value_dependent_expression_p (expression);
}
@@ -13104,6 +13102,19 @@ any_type_dependent_arguments_p (tree args)
return false;
}
+/* Returns TRUE if LIST (a TREE_LIST whose TREE_VALUEs are
+ expressions) contains any value-dependent expressions. */
+
+bool
+any_value_dependent_elements_p (tree list)
+{
+ for (; list; list = TREE_CHAIN (list))
+ if (value_dependent_expression_p (TREE_VALUE (list)))
+ return true;
+
+ return false;
+}
+
/* Returns TRUE if the ARG (a template argument) is dependent. */
static bool
diff --git a/contrib/gcc/cp/semantics.c b/contrib/gcc/cp/semantics.c
index 3235edbe1035..8ad197858d0f 100644
--- a/contrib/gcc/cp/semantics.c
+++ b/contrib/gcc/cp/semantics.c
@@ -3344,14 +3344,17 @@ finish_omp_clauses (tree clauses)
{
if (processing_template_decl)
break;
- error ("%qE is not a variable in clause %qs", t, name);
+ if (DECL_P (t))
+ error ("%qD is not a variable in clause %qs", t, name);
+ else
+ error ("%qE is not a variable in clause %qs", t, name);
remove = true;
}
else if (bitmap_bit_p (&generic_head, DECL_UID (t))
|| bitmap_bit_p (&firstprivate_head, DECL_UID (t))
|| bitmap_bit_p (&lastprivate_head, DECL_UID (t)))
{
- error ("%qE appears more than once in data clauses", t);
+ error ("%qD appears more than once in data clauses", t);
remove = true;
}
else
diff --git a/contrib/gcc/cp/typeck.c b/contrib/gcc/cp/typeck.c
index dbdcb447551c..4ae2f073abde 100644
--- a/contrib/gcc/cp/typeck.c
+++ b/contrib/gcc/cp/typeck.c
@@ -256,11 +256,9 @@ type_after_usual_arithmetic_conversions (tree t1, tree t2)
/* FIXME: Attributes. */
gcc_assert (ARITHMETIC_TYPE_P (t1)
- || TREE_CODE (t1) == COMPLEX_TYPE
|| TREE_CODE (t1) == VECTOR_TYPE
|| TREE_CODE (t1) == ENUMERAL_TYPE);
gcc_assert (ARITHMETIC_TYPE_P (t2)
- || TREE_CODE (t2) == COMPLEX_TYPE
|| TREE_CODE (t2) == VECTOR_TYPE
|| TREE_CODE (t2) == ENUMERAL_TYPE);
@@ -761,9 +759,9 @@ common_type (tree t1, tree t2)
code2 = TREE_CODE (t2);
if ((ARITHMETIC_TYPE_P (t1) || code1 == ENUMERAL_TYPE
- || code1 == COMPLEX_TYPE || code1 == VECTOR_TYPE)
+ || code1 == VECTOR_TYPE)
&& (ARITHMETIC_TYPE_P (t2) || code2 == ENUMERAL_TYPE
- || code2 == COMPLEX_TYPE || code2 == VECTOR_TYPE))
+ || code2 == VECTOR_TYPE))
return type_after_usual_arithmetic_conversions (t1, t2);
else if ((TYPE_PTR_P (t1) && TYPE_PTR_P (t2))
diff --git a/contrib/gcc/cp/typeck2.c b/contrib/gcc/cp/typeck2.c
index a3654c00047f..baedbad9fb99 100644
--- a/contrib/gcc/cp/typeck2.c
+++ b/contrib/gcc/cp/typeck2.c
@@ -710,7 +710,8 @@ digest_init (tree type, tree init)
}
/* Handle scalar types (including conversions) and references. */
- if (SCALAR_TYPE_P (type) || code == REFERENCE_TYPE)
+ if (TREE_CODE (type) != COMPLEX_TYPE
+ && (SCALAR_TYPE_P (type) || code == REFERENCE_TYPE))
return convert_for_initialization (0, type, init, LOOKUP_NORMAL,
"initialization", NULL_TREE, 0);
@@ -1347,7 +1348,9 @@ build_functional_cast (tree exp, tree parms)
&& !CLASSTYPE_NON_POD_P (type)
&& TYPE_HAS_DEFAULT_CONSTRUCTOR (type))
{
- exp = build_constructor (type, NULL);
+ exp = build_zero_init (type,
+ /*nelts=*/NULL_TREE,
+ /*static_storage_p=*/false);
return get_target_expr (exp);
}
diff --git a/contrib/gcc/doc/cpp.1 b/contrib/gcc/doc/cpp.1
index 17fdd0136c21..9abc9fda3d95 100644
--- a/contrib/gcc/doc/cpp.1
+++ b/contrib/gcc/doc/cpp.1
@@ -129,13 +129,14 @@
.\" ========================================================================
.\"
.IX Title "CPP 1"
-.TH CPP 1 "2006-03-06" "gcc-3.4.6" "GNU"
+.TH CPP 1 "2007-07-19" "gcc-4.2.1" "GNU"
.SH "NAME"
cpp \- The C Preprocessor
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
cpp [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR]
- [\fB\-I\fR\fIdir\fR...] [\fB\-W\fR\fIwarn\fR...]
+ [\fB\-I\fR\fIdir\fR...] [\fB\-iquote\fR\fIdir\fR...]
+ [\fB\-W\fR\fIwarn\fR...]
[\fB\-M\fR|\fB\-MM\fR] [\fB\-MG\fR] [\fB\-MF\fR \fIfilename\fR]
[\fB\-MP\fR] [\fB\-MQ\fR \fItarget\fR...]
[\fB\-MT\fR \fItarget\fR...]
@@ -218,7 +219,6 @@ options may \fInot\fR be grouped: \fB\-dM\fR is very different from
Predefine \fIname\fR as a macro, with definition \f(CW1\fR.
.IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4
.IX Item "-D name=definition"
-Predefine \fIname\fR as a macro, with definition \fIdefinition\fR.
The contents of \fIdefinition\fR are tokenized and processed as if
they appeared during translation phase three in a \fB#define\fR
directive. In particular, the definition will be truncated by
@@ -282,7 +282,6 @@ comment, or whenever a backslash-newline appears in a \fB//\fR comment.
(Both forms have the same effect.)
.IP "\fB\-Wtrigraphs\fR" 4
.IX Item "-Wtrigraphs"
-@anchor{Wtrigraphs}
Most trigraphs in comments cannot affect the meaning of the program.
However, a trigraph that would form an escaped newline (\fB??/\fR at
the end of a line) can, by changing where the comment begins or ends.
@@ -316,7 +315,7 @@ time it is redefined or undefined.
Built-in macros, macros defined on the command line, and macros
defined in include files are not warned about.
.Sp
-\&\fBNote:\fR If a macro is actually used, but only used in skipped
+\&\fINote:\fR If a macro is actually used, but only used in skipped
conditional blocks, then \s-1CPP\s0 will report it as unused. To avoid the
warning in such a case, you might improve the scope of the macro's
definition by, for example, moving it into the first skipped block.
@@ -397,8 +396,6 @@ This implies that the choice of angle brackets or double quotes in an
\&\fB#include\fR directive does not in itself determine whether that
header will appear in \fB\-MM\fR dependency output. This is a
slight change in semantics from \s-1GCC\s0 versions 3.0 and earlier.
-.Sp
-@anchor{dashMF}
.IP "\fB\-MF\fR \fIfile\fR" 4
.IX Item "-MF file"
When used with \fB\-M\fR or \fB\-MM\fR, specifies a
@@ -471,8 +468,7 @@ argument but with a suffix of \fI.d\fR, otherwise it take the
basename of the input file and applies a \fI.d\fR suffix.
.Sp
If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any
-\&\fB\-o\fR switch is understood to specify the dependency output file
-(but \f(CW@pxref\fR{dashMF,,\-MF}), but if used without \fB\-E\fR, each \fB\-o\fR
+\&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR
is understood to specify a target object file.
.Sp
Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate
@@ -480,7 +476,7 @@ a dependency output file as a side-effect of the compilation process.
.IP "\fB\-MMD\fR" 4
.IX Item "-MMD"
Like \fB\-MD\fR except mention only user header files, not system
-\&\-header files.
+header files.
.IP "\fB\-x c\fR" 4
.IX Item "-x c"
.PD 0
@@ -500,7 +496,7 @@ extensions for \*(C+ and assembly are also recognized. If cpp does not
recognize the extension, it will treat the file as C; this is the most
generic mode.
.Sp
-\&\fBNote:\fR Previous versions of cpp accepted a \fB\-lang\fR option
+\&\fINote:\fR Previous versions of cpp accepted a \fB\-lang\fR option
which selected both the language and the standards conformance level.
This option has been removed, because it conflicts with the \fB\-l\fR
option.
@@ -584,6 +580,8 @@ directories are searched for all \fB#include\fR directives.
.Sp
In addition, \fB\-I\-\fR inhibits the use of the directory of the current
file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR.
+.Sp
+This option has been deprecated.
.IP "\fB\-nostdinc\fR" 4
.IX Item "-nostdinc"
Do not search the standard system directories for header files.
@@ -634,16 +632,34 @@ Append \fIdir\fR to the prefix specified previously with
\&\fB\-iprefix\fR, and add the resulting directory to the include search
path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR
would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would.
+.IP "\fB\-isysroot\fR \fIdir\fR" 4
+.IX Item "-isysroot dir"
+This option is like the \fB\-\-sysroot\fR option, but applies only to
+header files. See the \fB\-\-sysroot\fR option for more information.
+.IP "\fB\-imultilib\fR \fIdir\fR" 4
+.IX Item "-imultilib dir"
+Use \fIdir\fR as a subdirectory of the directory containing
+target-specific \*(C+ headers.
.IP "\fB\-isystem\fR \fIdir\fR" 4
.IX Item "-isystem dir"
Search \fIdir\fR for header files, after all directories specified by
\&\fB\-I\fR but before the standard system directories. Mark it
as a system directory, so that it gets the same special treatment as
is applied to the standard system directories.
+.IP "\fB\-iquote\fR \fIdir\fR" 4
+.IX Item "-iquote dir"
+Search \fIdir\fR only for header files requested with
+\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for
+\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR, before all directories specified by
+\&\fB\-I\fR and before the standard system directories.
.IP "\fB\-fdollars\-in\-identifiers\fR" 4
.IX Item "-fdollars-in-identifiers"
-@anchor{fdollars\-in\-identifiers}
Accept \fB$\fR in identifiers.
+.IP "\fB\-fextended\-identifiers\fR" 4
+.IX Item "-fextended-identifiers"
+Accept universal character names in identifiers. This option is
+experimental; in a future version of \s-1GCC\s0, it will be enabled by
+default for C99 and \*(C+.
.IP "\fB\-fpreprocessed\fR" 4
.IX Item "-fpreprocessed"
Indicate to the preprocessor that the input file has already been
@@ -674,17 +690,17 @@ supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine.
Set the wide execution character set, used for wide string and
character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever
corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with
-\&\fB\-ftarget\-charset\fR, \fIcharset\fR can be any encoding supported
+\&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported
by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have
problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR.
.IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4
.IX Item "-finput-charset=charset"
Set the input character set, used for translation from the character
-set of the input file to the source character set used by \s-1GCC\s0. If the
+set of the input file to the source character set used by \s-1GCC\s0. If the
locale does not specify, or \s-1GCC\s0 cannot get this information from the
-locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale
-or this command line option. Currently the command line option takes
-precedence if there's a conflict. \fIcharset\fR can be any encoding
+locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale
+or this command line option. Currently the command line option takes
+precedence if there's a conflict. \fIcharset\fR can be any encoding
supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine.
.IP "\fB\-fworking\-directory\fR" 4
.IX Item "-fworking-directory"
@@ -892,7 +908,7 @@ main input file is omitted.
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
Copyright (c) 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
-1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
+1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
diff --git a/contrib/gcc/doc/gcc.1 b/contrib/gcc/doc/gcc.1
index 1fd2c2bcea67..b095c87656e6 100644
--- a/contrib/gcc/doc/gcc.1
+++ b/contrib/gcc/doc/gcc.1
@@ -129,7 +129,7 @@
.\" ========================================================================
.\"
.IX Title "GCC 1"
-.TH GCC 1 "2006-03-06" "gcc-3.4.6" "GNU"
+.TH GCC 1 "2007-07-19" "gcc-4.2.1" "GNU"
.SH "NAME"
gcc \- GNU project C and C++ compiler
.SH "SYNOPSIS"
@@ -140,14 +140,14 @@ gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR]
[\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...]
[\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR]
[\fB\-f\fR\fIoption\fR...] [\fB\-m\fR\fImachine-option\fR...]
- [\fB\-o\fR \fIoutfile\fR] \fIinfile\fR...
+ [\fB\-o\fR \fIoutfile\fR] [@\fIfile\fR] \fIinfile\fR...
.PP
Only the most useful options are listed here; see below for the
remainder. \fBg++\fR accepts mostly the same options as \fBgcc\fR.
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
When you invoke \s-1GCC\s0, it normally does preprocessing, compilation,
-assembly and linking. The ``overall options'' allow you to stop this
+assembly and linking. The \*(L"overall options\*(R" allow you to stop this
process at an intermediate stage. For example, the \fB\-c\fR option
says not to run the linker. Then the output consists of object files
output by the assembler.
@@ -173,8 +173,8 @@ of the same kind; for example, if you specify \fB\-L\fR more than once,
the directories are searched in the order specified.
.PP
Many options have long names starting with \fB\-f\fR or with
-\&\fB\-W\fR\-\-\-for example, \fB\-fforce\-mem\fR,
-\&\fB\-fstrength\-reduce\fR, \fB\-Wformat\fR and so on. Most of
+\&\fB\-W\fR\-\-\-for example,
+\&\fB\-fmove\-loop\-invariants\fR, \fB\-Wformat\fR and so on. Most of
these have both positive and negative forms; the negative form of
\&\fB\-ffoo\fR would be \fB\-fno\-foo\fR. This manual documents
only one of these two forms, whichever one is not the default.
@@ -186,22 +186,22 @@ Here is a summary of all the options, grouped by type. Explanations are
in the following sections.
.IP "\fIOverall Options\fR" 4
.IX Item "Overall Options"
-\&\fB\-c \-S \-E \-o\fR \fIfile\fR \fB\-pipe \-pass\-exit\-codes
-\&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help \-\-target\-help \-\-version\fR
+\&\fB\-c \-S \-E \-o\fR \fIfile\fR \fB\-combine \-pipe \-pass\-exit\-codes
+\&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help \-\-target\-help \-\-version @\fR\fIfile\fR
.IP "\fIC Language Options\fR" 4
.IX Item "C Language Options"
-\&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-aux\-info\fR \fIfilename\fR
+\&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline
+\&\-aux\-info\fR \fIfilename\fR
\&\fB\-fno\-asm \-fno\-builtin \-fno\-builtin\-\fR\fIfunction\fR
-\&\fB\-fhosted \-ffreestanding \-fms\-extensions
+\&\fB\-fhosted \-ffreestanding \-fopenmp \-fms\-extensions
\&\-trigraphs \-no\-integrated\-cpp \-traditional \-traditional\-cpp
\&\-fallow\-single\-precision \-fcond\-mismatch
\&\-fsigned\-bitfields \-fsigned\-char
-\&\-funsigned\-bitfields \-funsigned\-char
-\&\-fwritable\-strings\fR
+\&\-funsigned\-bitfields \-funsigned\-char\fR
.IP "\fI\*(C+ Language Options\fR" 4
.IX Item " Language Options"
\&\fB\-fabi\-version=\fR\fIn\fR \fB\-fno\-access\-control \-fcheck\-new
-\&\-fconserve\-space \-fno\-const\-strings
+\&\-fconserve\-space \-ffriend\-injection
\&\-fno\-elide\-constructors
\&\-fno\-enforce\-eh\-specs
\&\-ffor\-scope \-fno\-for\-scope \-fno\-gnu\-keywords
@@ -211,71 +211,107 @@ in the following sections.
\&\-fno\-nonansi\-builtins \-fno\-operator\-names
\&\-fno\-optional\-diags \-fpermissive
\&\-frepo \-fno\-rtti \-fstats \-ftemplate\-depth\-\fR\fIn\fR
-\&\fB\-fuse\-cxa\-atexit \-fno\-weak \-nostdinc++
-\&\-fno\-default\-inline \-Wabi \-Wctor\-dtor\-privacy
+\&\fB\-fno\-threadsafe\-statics \-fuse\-cxa\-atexit \-fno\-weak \-nostdinc++
+\&\-fno\-default\-inline \-fvisibility\-inlines\-hidden
+\&\-Wabi \-Wctor\-dtor\-privacy
\&\-Wnon\-virtual\-dtor \-Wreorder
-\&\-Weffc++ \-Wno\-deprecated
+\&\-Weffc++ \-Wno\-deprecated \-Wstrict\-null\-sentinel
\&\-Wno\-non\-template\-friend \-Wold\-style\-cast
\&\-Woverloaded\-virtual \-Wno\-pmf\-conversions
\&\-Wsign\-promo\fR
-.IP "\fIObjective-C Language Options\fR" 4
-.IX Item "Objective-C Language Options"
+.IP "\fIObjective-C and Objective\-\*(C+ Language Options\fR" 4
+.IX Item "Objective-C and Objective- Language Options"
\&\fB\-fconstant\-string\-class=\fR\fIclass-name\fR
\&\fB\-fgnu\-runtime \-fnext\-runtime
\&\-fno\-nil\-receivers
+\&\-fobjc\-call\-cxx\-cdtors
+\&\-fobjc\-direct\-dispatch
\&\-fobjc\-exceptions
+\&\-fobjc\-gc
\&\-freplace\-objc\-classes
\&\-fzero\-link
\&\-gen\-decls
-\&\-Wno\-protocol \-Wselector \-Wundeclared\-selector\fR
+\&\-Wassign\-intercept
+\&\-Wno\-protocol \-Wselector
+\&\-Wstrict\-selector\-match
+\&\-Wundeclared\-selector\fR
.IP "\fILanguage Independent Options\fR" 4
.IX Item "Language Independent Options"
\&\fB\-fmessage\-length=\fR\fIn\fR
-\&\fB\-fdiagnostics\-show\-location=\fR[\fBonce\fR|\fBevery-line\fR]
+\&\fB\-fdiagnostics\-show\-location=\fR[\fBonce\fR|\fBevery-line\fR]
+\&\fB\-fdiagnostics\-show\-option\fR
.IP "\fIWarning Options\fR" 4
.IX Item "Warning Options"
\&\fB\-fsyntax\-only \-pedantic \-pedantic\-errors
-\&\-w \-Wextra \-Wall \-Waggregate\-return
-\&\-Wcast\-align \-Wcast\-qual \-Wchar\-subscripts \-Wcomment
+\&\-w \-Wextra \-Wall \-Waddress \-Waggregate\-return \-Wno\-attributes
+\&\-Wc++\-compat \-Wcast\-align \-Wcast\-qual \-Wchar\-subscripts \-Wcomment
\&\-Wconversion \-Wno\-deprecated\-declarations
-\&\-Wdisabled\-optimization \-Wno\-div\-by\-zero \-Wendif\-labels
-\&\-Werror \-Werror\-implicit\-function\-declaration
-\&\-Wfloat\-equal \-Wformat \-Wformat=2
+\&\-Wdisabled\-optimization \-Wno\-div\-by\-zero \-Wno\-endif\-labels
+\&\-Werror \-Werror=* \-Werror\-implicit\-function\-declaration
+\&\-Wfatal\-errors \-Wfloat\-equal \-Wformat \-Wformat=2
\&\-Wno\-format\-extra\-args \-Wformat\-nonliteral
\&\-Wformat\-security \-Wformat\-y2k
\&\-Wimplicit \-Wimplicit\-function\-declaration \-Wimplicit\-int
\&\-Wimport \-Wno\-import \-Winit\-self \-Winline
+\&\-Wno\-int\-to\-pointer\-cast
\&\-Wno\-invalid\-offsetof \-Winvalid\-pch
-\&\-Wlarger\-than\-\fR\fIlen\fR \fB\-Wlong\-long
-\&\-Wmain \-Wmissing\-braces
-\&\-Wmissing\-format\-attribute \-Wmissing\-noreturn
-\&\-Wno\-multichar \-Wnonnull \-Wpacked \-Wpadded
-\&\-Wparentheses \-Wpointer\-arith \-Wredundant\-decls
+\&\-Wlarger\-than\-\fR\fIlen\fR \fB\-Wunsafe\-loop\-optimizations \-Wlong\-long
+\&\-Wmain \-Wmissing\-braces \-Wmissing\-field\-initializers
+\&\-Wmissing\-format\-attribute \-Wmissing\-include\-dirs
+\&\-Wmissing\-noreturn
+\&\-Wno\-multichar \-Wnonnull \-Wno\-overflow
+\&\-Woverlength\-strings \-Wpacked \-Wpadded
+\&\-Wparentheses \-Wpointer\-arith \-Wno\-pointer\-to\-int\-cast
+\&\-Wredundant\-decls
\&\-Wreturn\-type \-Wsequence\-point \-Wshadow
-\&\-Wsign\-compare \-Wstrict\-aliasing
-\&\-Wswitch \-Wswitch\-default \-Wswitch\-enum
+\&\-Wsign\-compare \-Wstack\-protector
+\&\-Wstrict\-aliasing \-Wstrict\-aliasing=2
+\&\-Wstrict\-overflow \-Wstrict\-overflow=\fR\fIn\fR
+\&\fB\-Wswitch \-Wswitch\-default \-Wswitch\-enum
\&\-Wsystem\-headers \-Wtrigraphs \-Wundef \-Wuninitialized
-\&\-Wunknown\-pragmas \-Wunreachable\-code
+\&\-Wunknown\-pragmas \-Wno\-pragmas \-Wunreachable\-code
\&\-Wunused \-Wunused\-function \-Wunused\-label \-Wunused\-parameter
-\&\-Wunused\-value \-Wunused\-variable \-Wwrite\-strings\fR
+\&\-Wunused\-value \-Wunused\-variable \-Wvariadic\-macros
+\&\-Wvolatile\-register\-var \-Wwrite\-strings\fR
.IP "\fIC\-only Warning Options\fR" 4
.IX Item "C-only Warning Options"
\&\fB\-Wbad\-function\-cast \-Wmissing\-declarations
\&\-Wmissing\-prototypes \-Wnested\-externs \-Wold\-style\-definition
\&\-Wstrict\-prototypes \-Wtraditional
-\&\-Wdeclaration\-after\-statement\fR
+\&\-Wdeclaration\-after\-statement \-Wpointer\-sign\fR
.IP "\fIDebugging Options\fR" 4
.IX Item "Debugging Options"
\&\fB\-d\fR\fIletters\fR \fB\-dumpspecs \-dumpmachine \-dumpversion
-\&\-fdump\-unnumbered \-fdump\-translation\-unit\fR[\fB\-\fR\fIn\fR]
+\&\-fdump\-noaddr \-fdump\-unnumbered \-fdump\-translation\-unit\fR[\fB\-\fR\fIn\fR]
\&\fB\-fdump\-class\-hierarchy\fR[\fB\-\fR\fIn\fR]
-\&\fB\-fdump\-tree\-original\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-ipa\-all \-fdump\-ipa\-cgraph
+\&\-fdump\-tree\-all
+\&\-fdump\-tree\-original\fR[\fB\-\fR\fIn\fR]
\&\fB\-fdump\-tree\-optimized\fR[\fB\-\fR\fIn\fR]
\&\fB\-fdump\-tree\-inlined\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-cfg \-fdump\-tree\-vcg \-fdump\-tree\-alias
+\&\-fdump\-tree\-ch
+\&\-fdump\-tree\-ssa\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-pre\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-ccp\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-dce\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-gimple\fR[\fB\-raw\fR] \fB\-fdump\-tree\-mudflap\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-dom\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-dse\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-phiopt\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-forwprop\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-copyrename\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-nrv \-fdump\-tree\-vect
+\&\-fdump\-tree\-sink
+\&\-fdump\-tree\-sra\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-salias
+\&\-fdump\-tree\-fre\fR[\fB\-\fR\fIn\fR]
+\&\fB\-fdump\-tree\-vrp\fR[\fB\-\fR\fIn\fR]
+\&\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR
+\&\fB\-fdump\-tree\-storeccp\fR[\fB\-\fR\fIn\fR]
\&\fB\-feliminate\-dwarf2\-dups \-feliminate\-unused\-debug\-types
-\&\-feliminate\-unused\-debug\-symbols \-fmem\-report \-fprofile\-arcs
+\&\-feliminate\-unused\-debug\-symbols \-femit\-class\-debug\-always
+\&\-fmem\-report \-fprofile\-arcs
\&\-frandom\-seed=\fR\fIstring\fR \fB\-fsched\-verbose=\fR\fIn\fR
-\&\fB\-ftest\-coverage \-ftime\-report
+\&\fB\-ftest\-coverage \-ftime\-report \-fvar\-tracking
\&\-g \-g\fR\fIlevel\fR \fB\-gcoff \-gdwarf\-2
\&\-ggdb \-gstabs \-gstabs+ \-gvms \-gxcoff \-gxcoff+
\&\-p \-pg \-print\-file\-name=\fR\fIlibrary\fR \fB\-print\-libgcc\-file\-name
@@ -286,38 +322,50 @@ in the following sections.
.IX Item "Optimization Options"
\&\fB\-falign\-functions=\fR\fIn\fR \fB\-falign\-jumps=\fR\fIn\fR
\&\fB\-falign\-labels=\fR\fIn\fR \fB\-falign\-loops=\fR\fIn\fR
-\&\fB\-fbranch\-probabilities \-fprofile\-values \-fvpt \-fbranch\-target\-load\-optimize
-\&\-fbranch\-target\-load\-optimize2 \-fcaller\-saves \-fcprop\-registers
-\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks \-fdata\-sections
-\&\-fdelayed\-branch \-fdelete\-null\-pointer\-checks
+\&\fB\-fbounds\-check \-fmudflap \-fmudflapth \-fmudflapir
+\&\-fbranch\-probabilities \-fprofile\-values \-fvpt \-fbranch\-target\-load\-optimize
+\&\-fbranch\-target\-load\-optimize2 \-fbtr\-bb\-exclusive
+\&\-fcaller\-saves \-fcprop\-registers \-fcse\-follow\-jumps
+\&\-fcse\-skip\-blocks \-fcx\-limited\-range \-fdata\-sections
+\&\-fdelayed\-branch \-fdelete\-null\-pointer\-checks \-fearly\-inlining
\&\-fexpensive\-optimizations \-ffast\-math \-ffloat\-store
-\&\-fforce\-addr \-fforce\-mem \-ffunction\-sections
-\&\-fgcse \-fgcse\-lm \-fgcse\-sm \-fgcse\-las \-floop\-optimize
+\&\-fforce\-addr \-ffunction\-sections
+\&\-fgcse \-fgcse\-lm \-fgcse\-sm \-fgcse\-las \-fgcse\-after\-reload
\&\-fcrossjumping \-fif\-conversion \-fif\-conversion2
-\&\-finline\-functions \-finline\-limit=\fR\fIn\fR \fB\-fkeep\-inline\-functions
+\&\-finline\-functions \-finline\-functions\-called\-once
+\&\-finline\-limit=\fR\fIn\fR \fB\-fkeep\-inline\-functions
\&\-fkeep\-static\-consts \-fmerge\-constants \-fmerge\-all\-constants
-\&\-fmove\-all\-movables \-fnew\-ra \-fno\-branch\-count\-reg
-\&\-fno\-default\-inline \-fno\-defer\-pop
+\&\-fmodulo\-sched \-fno\-branch\-count\-reg
+\&\-fno\-default\-inline \-fno\-defer\-pop \-fmove\-loop\-invariants
\&\-fno\-function\-cse \-fno\-guess\-branch\-probability
\&\-fno\-inline \-fno\-math\-errno \-fno\-peephole \-fno\-peephole2
-\&\-funsafe\-math\-optimizations \-ffinite\-math\-only
-\&\-fno\-trapping\-math \-fno\-zero\-initialized\-in\-bss
+\&\-funsafe\-math\-optimizations \-funsafe\-loop\-optimizations \-ffinite\-math\-only
+\&\-fno\-toplevel\-reorder \-fno\-trapping\-math \-fno\-zero\-initialized\-in\-bss
\&\-fomit\-frame\-pointer \-foptimize\-register\-move
\&\-foptimize\-sibling\-calls \-fprefetch\-loop\-arrays
\&\-fprofile\-generate \-fprofile\-use
-\&\-freduce\-all\-givs \-fregmove \-frename\-registers
-\&\-freorder\-blocks \-freorder\-functions
-\&\-frerun\-cse\-after\-loop \-frerun\-loop\-opt
-\&\-frounding\-math \-fschedule\-insns \-fschedule\-insns2
+\&\-fregmove \-frename\-registers
+\&\-freorder\-blocks \-freorder\-blocks\-and\-partition \-freorder\-functions
+\&\-frerun\-cse\-after\-loop
+\&\-frounding\-math \-frtl\-abstract\-sequences
+\&\-fschedule\-insns \-fschedule\-insns2
\&\-fno\-sched\-interblock \-fno\-sched\-spec \-fsched\-spec\-load
\&\-fsched\-spec\-load\-dangerous
-\&\-fsched\-stalled\-insns=\fR\fIn\fR \fB\-sched\-stalled\-insns\-dep=\fR\fIn\fR
+\&\-fsched\-stalled\-insns=\fR\fIn\fR \fB\-fsched\-stalled\-insns\-dep=\fR\fIn\fR
\&\fB\-fsched2\-use\-superblocks
-\&\-fsched2\-use\-traces \-fsignaling\-nans
-\&\-fsingle\-precision\-constant
-\&\-fstrength\-reduce \-fstrict\-aliasing \-ftracer \-fthread\-jumps
+\&\-fsched2\-use\-traces \-fsee \-freschedule\-modulo\-scheduled\-loops
+\&\-fsection\-anchors \-fsignaling\-nans \-fsingle\-precision\-constant
+\&\-fstack\-protector \-fstack\-protector\-all
+\&\-fstrict\-aliasing \-fstrict\-overflow \-ftracer \-fthread\-jumps
\&\-funroll\-all\-loops \-funroll\-loops \-fpeel\-loops
-\&\-funswitch\-loops \-fold\-unroll\-loops \-fold\-unroll\-all\-loops
+\&\-fsplit\-ivs\-in\-unroller \-funswitch\-loops
+\&\-fvariable\-expansion\-in\-unroller
+\&\-ftree\-pre \-ftree\-ccp \-ftree\-dce \-ftree\-loop\-optimize
+\&\-ftree\-loop\-linear \-ftree\-loop\-im \-ftree\-loop\-ivcanon \-fivopts
+\&\-ftree\-dominator\-opts \-ftree\-dse \-ftree\-copyrename \-ftree\-sink
+\&\-ftree\-ch \-ftree\-sra \-ftree\-ter \-ftree\-lrs \-ftree\-fre \-ftree\-vectorize
+\&\-ftree\-vect\-loop\-version \-ftree\-salias \-fipa\-pta \-fweb
+\&\-ftree\-copy\-prop \-ftree\-store\-ccp \-ftree\-store\-copy\-prop \-fwhole\-program
\&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR
\&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os\fR
.IP "\fIPreprocessor Options\fR" 4
@@ -330,6 +378,7 @@ in the following sections.
\&\fB\-include\fR \fIfile\fR \fB\-imacros\fR \fIfile\fR
\&\fB\-iprefix\fR \fIfile\fR \fB\-iwithprefix\fR \fIdir\fR
\&\fB\-iwithprefixbefore\fR \fIdir\fR \fB\-isystem\fR \fIdir\fR
+\&\fB\-imultilib\fR \fIdir\fR \fB\-isysroot\fR \fIdir\fR
\&\fB\-M \-MM \-MF \-MG \-MP \-MQ \-MT \-nostdinc
\&\-P \-fworking\-directory \-remap
\&\-trigraphs \-undef \-U\fR\fImacro\fR \fB\-Wp,\fR\fIoption\fR
@@ -340,62 +389,35 @@ in the following sections.
.IP "\fILinker Options\fR" 4
.IX Item "Linker Options"
\&\fIobject-file-name\fR \fB\-l\fR\fIlibrary\fR
-\&\fB\-nostartfiles \-nodefaultlibs \-nostdlib \-pie
+\&\fB\-nostartfiles \-nodefaultlibs \-nostdlib \-pie \-rdynamic
\&\-s \-static \-static\-libgcc \-shared \-shared\-libgcc \-symbolic
\&\-Wl,\fR\fIoption\fR \fB\-Xlinker\fR \fIoption\fR
\&\fB\-u\fR \fIsymbol\fR
.IP "\fIDirectory Options\fR" 4
.IX Item "Directory Options"
-\&\fB\-B\fR\fIprefix\fR \fB\-I\fR\fIdir\fR \fB\-I\- \-L\fR\fIdir\fR \fB\-specs=\fR\fIfile\fR
+\&\fB\-B\fR\fIprefix\fR \fB\-I\fR\fIdir\fR \fB\-iquote\fR\fIdir\fR \fB\-L\fR\fIdir\fR
+\&\fB\-specs=\fR\fIfile\fR \fB\-I\- \-\-sysroot=\fR\fIdir\fR
.IP "\fITarget Options\fR" 4
.IX Item "Target Options"
\&\fB\-V\fR \fIversion\fR \fB\-b\fR \fImachine\fR
.IP "\fIMachine Dependent Options\fR" 4
.IX Item "Machine Dependent Options"
-\&\fIM680x0 Options\fR
-\&\fB\-m68000 \-m68020 \-m68020\-40 \-m68020\-60 \-m68030 \-m68040
-\&\-m68060 \-mcpu32 \-m5200 \-m68881 \-mbitfield \-mc68000 \-mc68020
-\&\-mnobitfield \-mrtd \-mshort \-msoft\-float \-mpcrel
-\&\-malign\-int \-mstrict\-align \-msep\-data \-mno\-sep\-data
-\&\-mshared\-library\-id=n \-mid\-shared\-library \-mno\-id\-shared\-library\fR
-.Sp
-\&\fIM68hc1x Options\fR
-\&\fB\-m6811 \-m6812 \-m68hc11 \-m68hc12 \-m68hcs12
-\&\-mauto\-incdec \-minmax \-mlong\-calls \-mshort
-\&\-msoft\-reg\-count=\fR\fIcount\fR
-.Sp
-\&\fI\s-1VAX\s0 Options\fR
-\&\fB\-mg \-mgnu \-munix\fR
-.Sp
-\&\fI\s-1SPARC\s0 Options\fR
-\&\fB\-mcpu=\fR\fIcpu-type\fR
-\&\fB\-mtune=\fR\fIcpu-type\fR
-\&\fB\-mcmodel=\fR\fIcode-model\fR
-\&\fB\-m32 \-m64 \-mapp\-regs \-mno\-app\-regs
-\&\-mfaster\-structs \-mno\-faster\-structs
-\&\-mflat \-mno\-flat \-mfpu \-mno\-fpu
-\&\-mhard\-float \-msoft\-float
-\&\-mhard\-quad\-float \-msoft\-quad\-float
-\&\-mimpure\-text \-mno\-impure\-text \-mlittle\-endian
-\&\-mstack\-bias \-mno\-stack\-bias
-\&\-munaligned\-doubles \-mno\-unaligned\-doubles
-\&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis
-\&\-mcypress \-mf930 \-mf934
-\&\-msparclite \-msupersparc \-mv8
-\&\-threads \-pthreads\fR
+\&\fI\s-1ARC\s0 Options\fR
+\&\fB\-EB \-EL
+\&\-mmangle\-cpu \-mcpu=\fR\fIcpu\fR \fB\-mtext=\fR\fItext-section\fR
+\&\fB\-mdata=\fR\fIdata-section\fR \fB\-mrodata=\fR\fIreadonly-data-section\fR
.Sp
\&\fI\s-1ARM\s0 Options\fR
\&\fB\-mapcs\-frame \-mno\-apcs\-frame
-\&\-mapcs\-26 \-mapcs\-32
-\&\-mapcs\-stack\-check \-mno\-apcs\-stack\-check
+\&\-mabi=\fR\fIname\fR
+\&\fB\-mapcs\-stack\-check \-mno\-apcs\-stack\-check
\&\-mapcs\-float \-mno\-apcs\-float
\&\-mapcs\-reentrant \-mno\-apcs\-reentrant
\&\-msched\-prolog \-mno\-sched\-prolog
\&\-mlittle\-endian \-mbig\-endian \-mwords\-little\-endian
-\&\-malignment\-traps \-mno\-alignment\-traps
-\&\-msoft\-float \-mhard\-float \-mfpe
+\&\-mfloat\-abi=\fR\fIname\fR \fB\-msoft\-float \-mhard\-float \-mfpe
\&\-mthumb\-interwork \-mno\-thumb\-interwork
-\&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpe=\fR\fIname\fR
+\&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpu=\fR\fIname\fR
\&\fB\-mstructure\-size\-boundary=\fR\fIn\fR
\&\fB\-mabort\-on\-noreturn
\&\-mlong\-calls \-mno\-long\-calls
@@ -406,13 +428,145 @@ in the following sections.
\&\-mpoke\-function\-name
\&\-mthumb \-marm
\&\-mtpcs\-frame \-mtpcs\-leaf\-frame
-\&\-mcaller\-super\-interworking \-mcallee\-super\-interworking\fR
+\&\-mcaller\-super\-interworking \-mcallee\-super\-interworking
+\&\-mtp=\fR\fIname\fR
.Sp
-\&\fI\s-1MN10300\s0 Options\fR
-\&\fB\-mmult\-bug \-mno\-mult\-bug
-\&\-mam33 \-mno\-am33
-\&\-mam33\-2 \-mno\-am33\-2
-\&\-mno\-crt0 \-mrelax\fR
+\&\fI\s-1AVR\s0 Options\fR
+\&\fB\-mmcu=\fR\fImcu\fR \fB\-msize \-minit\-stack=\fR\fIn\fR \fB\-mno\-interrupts
+\&\-mcall\-prologues \-mno\-tablejump \-mtiny\-stack \-mint8\fR
+.Sp
+\&\fIBlackfin Options\fR
+\&\fB\-momit\-leaf\-frame\-pointer \-mno\-omit\-leaf\-frame\-pointer
+\&\-mspecld\-anomaly \-mno\-specld\-anomaly \-mcsync\-anomaly \-mno\-csync\-anomaly
+\&\-mlow\-64k \-mno\-low64k \-mid\-shared\-library
+\&\-mno\-id\-shared\-library \-mshared\-library\-id=\fR\fIn\fR
+\&\fB\-mlong\-calls \-mno\-long\-calls\fR
+.Sp
+\&\fI\s-1CRIS\s0 Options\fR
+\&\fB\-mcpu=\fR\fIcpu\fR \fB\-march=\fR\fIcpu\fR \fB\-mtune=\fR\fIcpu\fR
+\&\fB\-mmax\-stack\-frame=\fR\fIn\fR \fB\-melinux\-stacksize=\fR\fIn\fR
+\&\fB\-metrax4 \-metrax100 \-mpdebug \-mcc\-init \-mno\-side\-effects
+\&\-mstack\-align \-mdata\-align \-mconst\-align
+\&\-m32\-bit \-m16\-bit \-m8\-bit \-mno\-prologue\-epilogue \-mno\-gotplt
+\&\-melf \-maout \-melinux \-mlinux \-sim \-sim2
+\&\-mmul\-bug\-workaround \-mno\-mul\-bug\-workaround\fR
+.Sp
+\&\fI\s-1CRX\s0 Options\fR
+\&\fB\-mmac \-mpush\-args\fR
+.Sp
+\&\fIDarwin Options\fR
+\&\fB\-all_load \-allowable_client \-arch \-arch_errors_fatal
+\&\-arch_only \-bind_at_load \-bundle \-bundle_loader
+\&\-client_name \-compatibility_version \-current_version
+\&\-dead_strip
+\&\-dependency\-file \-dylib_file \-dylinker_install_name
+\&\-dynamic \-dynamiclib \-exported_symbols_list
+\&\-filelist \-flat_namespace \-force_cpusubtype_ALL
+\&\-force_flat_namespace \-headerpad_max_install_names
+\&\-image_base \-init \-install_name \-keep_private_externs
+\&\-multi_module \-multiply_defined \-multiply_defined_unused
+\&\-noall_load \-no_dead_strip_inits_and_terms
+\&\-nofixprebinding \-nomultidefs \-noprebind \-noseglinkedit
+\&\-pagezero_size \-prebind \-prebind_all_twolevel_modules
+\&\-private_bundle \-read_only_relocs \-sectalign
+\&\-sectobjectsymbols \-whyload \-seg1addr
+\&\-sectcreate \-sectobjectsymbols \-sectorder
+\&\-segaddr \-segs_read_only_addr \-segs_read_write_addr
+\&\-seg_addr_table \-seg_addr_table_filename \-seglinkedit
+\&\-segprot \-segs_read_only_addr \-segs_read_write_addr
+\&\-single_module \-static \-sub_library \-sub_umbrella
+\&\-twolevel_namespace \-umbrella \-undefined
+\&\-unexported_symbols_list \-weak_reference_mismatches
+\&\-whatsloaded \-F \-gused \-gfull \-mmacosx\-version\-min=\fR\fIversion\fR
+\&\fB\-mkernel \-mone\-byte\-bool\fR
+.Sp
+\&\fI\s-1DEC\s0 Alpha Options\fR
+\&\fB\-mno\-fp\-regs \-msoft\-float \-malpha\-as \-mgas
+\&\-mieee \-mieee\-with\-inexact \-mieee\-conformant
+\&\-mfp\-trap\-mode=\fR\fImode\fR \fB\-mfp\-rounding\-mode=\fR\fImode\fR
+\&\fB\-mtrap\-precision=\fR\fImode\fR \fB\-mbuild\-constants
+\&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR
+\&\fB\-mbwx \-mmax \-mfix \-mcix
+\&\-mfloat\-vax \-mfloat\-ieee
+\&\-mexplicit\-relocs \-msmall\-data \-mlarge\-data
+\&\-msmall\-text \-mlarge\-text
+\&\-mmemory\-latency=\fR\fItime\fR
+.Sp
+\&\fI\s-1DEC\s0 Alpha/VMS Options\fR
+\&\fB\-mvms\-return\-codes\fR
+.Sp
+\&\fI\s-1FRV\s0 Options\fR
+\&\fB\-mgpr\-32 \-mgpr\-64 \-mfpr\-32 \-mfpr\-64
+\&\-mhard\-float \-msoft\-float
+\&\-malloc\-cc \-mfixed\-cc \-mdword \-mno\-dword
+\&\-mdouble \-mno\-double
+\&\-mmedia \-mno\-media \-mmuladd \-mno\-muladd
+\&\-mfdpic \-minline\-plt \-mgprel\-ro \-multilib\-library\-pic
+\&\-mlinked\-fp \-mlong\-calls \-malign\-labels
+\&\-mlibrary\-pic \-macc\-4 \-macc\-8
+\&\-mpack \-mno\-pack \-mno\-eflags \-mcond\-move \-mno\-cond\-move
+\&\-moptimize\-membar \-mno\-optimize\-membar
+\&\-mscc \-mno\-scc \-mcond\-exec \-mno\-cond\-exec
+\&\-mvliw\-branch \-mno\-vliw\-branch
+\&\-mmulti\-cond\-exec \-mno\-multi\-cond\-exec \-mnested\-cond\-exec
+\&\-mno\-nested\-cond\-exec \-mtomcat\-stats
+\&\-mTLS \-mtls
+\&\-mcpu=\fR\fIcpu\fR
+.Sp
+\&\fIGNU/Linux Options\fR
+\&\fB\-muclibc\fR
+.Sp
+\&\fIH8/300 Options\fR
+\&\fB\-mrelax \-mh \-ms \-mn \-mint32 \-malign\-300\fR
+.Sp
+\&\fI\s-1HPPA\s0 Options\fR
+\&\fB\-march=\fR\fIarchitecture-type\fR
+\&\fB\-mbig\-switch \-mdisable\-fpregs \-mdisable\-indexing
+\&\-mfast\-indirect\-calls \-mgas \-mgnu\-ld \-mhp\-ld
+\&\-mfixed\-range=\fR\fIregister-range\fR
+\&\fB\-mjump\-in\-delay \-mlinker\-opt \-mlong\-calls
+\&\-mlong\-load\-store \-mno\-big\-switch \-mno\-disable\-fpregs
+\&\-mno\-disable\-indexing \-mno\-fast\-indirect\-calls \-mno\-gas
+\&\-mno\-jump\-in\-delay \-mno\-long\-load\-store
+\&\-mno\-portable\-runtime \-mno\-soft\-float
+\&\-mno\-space\-regs \-msoft\-float \-mpa\-risc\-1\-0
+\&\-mpa\-risc\-1\-1 \-mpa\-risc\-2\-0 \-mportable\-runtime
+\&\-mschedule=\fR\fIcpu-type\fR \fB\-mspace\-regs \-msio \-mwsio
+\&\-munix=\fR\fIunix-std\fR \fB\-nolibdld \-static \-threads\fR
+.Sp
+\&\fIi386 and x86\-64 Options\fR
+\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR
+\&\fB\-mfpmath=\fR\fIunit\fR
+\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387
+\&\-mno\-fp\-ret\-in\-387 \-msoft\-float \-msvr3\-shlib
+\&\-mno\-wide\-multiply \-mrtd \-malign\-double
+\&\-mpreferred\-stack\-boundary=\fR\fInum\fR
+\&\fB\-mmmx \-msse \-msse2 \-msse3 \-m3dnow
+\&\-mthreads \-mno\-align\-stringops \-minline\-all\-stringops
+\&\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double
+\&\-m96bit\-long\-double \-mregparm=\fR\fInum\fR \fB\-msseregparm
+\&\-mstackrealign
+\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs
+\&\-mcmodel=\fR\fIcode-model\fR
+\&\fB\-m32 \-m64 \-mlarge\-data\-threshold=\fR\fInum\fR
+.Sp
+\&\fI\s-1IA\-64\s0 Options\fR
+\&\fB\-mbig\-endian \-mlittle\-endian \-mgnu\-as \-mgnu\-ld \-mno\-pic
+\&\-mvolatile\-asm\-stop \-mregister\-names \-mno\-sdata
+\&\-mconstant\-gp \-mauto\-pic \-minline\-float\-divide\-min\-latency
+\&\-minline\-float\-divide\-max\-throughput
+\&\-minline\-int\-divide\-min\-latency
+\&\-minline\-int\-divide\-max\-throughput
+\&\-minline\-sqrt\-min\-latency \-minline\-sqrt\-max\-throughput
+\&\-mno\-dwarf2\-asm \-mearly\-stop\-bits
+\&\-mfixed\-range=\fR\fIregister-range\fR \fB\-mtls\-size=\fR\fItls-size\fR
+\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-mt \-pthread \-milp32 \-mlp64
+\&\-mno\-sched\-br\-data\-spec \-msched\-ar\-data\-spec \-mno\-sched\-control\-spec
+\&\-msched\-br\-in\-data\-spec \-msched\-ar\-in\-data\-spec \-msched\-in\-control\-spec
+\&\-msched\-ldc \-mno\-sched\-control\-ldc \-mno\-sched\-spec\-verbose
+\&\-mno\-sched\-prefer\-non\-data\-spec\-insns
+\&\-mno\-sched\-prefer\-non\-control\-spec\-insns
+\&\-mno\-sched\-count\-spec\-in\-critical\-path\fR
.Sp
\&\fIM32R/D Options\fR
\&\fB\-m32r2 \-m32rx \-m32r
@@ -426,6 +580,81 @@ in the following sections.
\&\fB\-mno\-flush\-trap \-mflush\-trap=\fR\fInumber\fR
\&\fB\-G\fR \fInum\fR
.Sp
+\&\fIM32C Options\fR
+\&\fB\-mcpu=\fR\fIcpu\fR \fB\-msim \-memregs=\fR\fInumber\fR
+.Sp
+\&\fIM680x0 Options\fR
+\&\fB\-m68000 \-m68020 \-m68020\-40 \-m68020\-60 \-m68030 \-m68040
+\&\-m68060 \-mcpu32 \-m5200 \-mcfv4e \-m68881 \-mbitfield
+\&\-mc68000 \-mc68020
+\&\-mnobitfield \-mrtd \-mshort \-msoft\-float \-mpcrel
+\&\-malign\-int \-mstrict\-align \-msep\-data \-mno\-sep\-data
+\&\-mshared\-library\-id=n \-mid\-shared\-library \-mno\-id\-shared\-library\fR
+.Sp
+\&\fIM68hc1x Options\fR
+\&\fB\-m6811 \-m6812 \-m68hc11 \-m68hc12 \-m68hcs12
+\&\-mauto\-incdec \-minmax \-mlong\-calls \-mshort
+\&\-msoft\-reg\-count=\fR\fIcount\fR
+.Sp
+\&\fIMCore Options\fR
+\&\fB\-mhardlit \-mno\-hardlit \-mdiv \-mno\-div \-mrelax\-immediates
+\&\-mno\-relax\-immediates \-mwide\-bitfields \-mno\-wide\-bitfields
+\&\-m4byte\-functions \-mno\-4byte\-functions \-mcallgraph\-data
+\&\-mno\-callgraph\-data \-mslow\-bytes \-mno\-slow\-bytes \-mno\-lsim
+\&\-mlittle\-endian \-mbig\-endian \-m210 \-m340 \-mstack\-increment\fR
+.Sp
+\&\fI\s-1MIPS\s0 Options\fR
+\&\fB\-EL \-EB \-march=\fR\fIarch\fR \fB\-mtune=\fR\fIarch\fR
+\&\fB\-mips1 \-mips2 \-mips3 \-mips4 \-mips32 \-mips32r2 \-mips64
+\&\-mips16 \-mno\-mips16 \-mabi=\fR\fIabi\fR \fB\-mabicalls \-mno\-abicalls
+\&\-mshared \-mno\-shared \-mxgot \-mno\-xgot \-mgp32 \-mgp64
+\&\-mfp32 \-mfp64 \-mhard\-float \-msoft\-float
+\&\-msingle\-float \-mdouble\-float \-mdsp \-mpaired\-single \-mips3d
+\&\-mlong64 \-mlong32 \-msym32 \-mno\-sym32
+\&\-G\fR\fInum\fR \fB\-membedded\-data \-mno\-embedded\-data
+\&\-muninit\-const\-in\-rodata \-mno\-uninit\-const\-in\-rodata
+\&\-msplit\-addresses \-mno\-split\-addresses
+\&\-mexplicit\-relocs \-mno\-explicit\-relocs
+\&\-mcheck\-zero\-division \-mno\-check\-zero\-division
+\&\-mdivide\-traps \-mdivide\-breaks
+\&\-mmemcpy \-mno\-memcpy \-mlong\-calls \-mno\-long\-calls
+\&\-mmad \-mno\-mad \-mfused\-madd \-mno\-fused\-madd \-nocpp
+\&\-mfix\-r4000 \-mno\-fix\-r4000 \-mfix\-r4400 \-mno\-fix\-r4400
+\&\-mfix\-vr4120 \-mno\-fix\-vr4120 \-mfix\-vr4130
+\&\-mfix\-sb1 \-mno\-fix\-sb1
+\&\-mflush\-func=\fR\fIfunc\fR \fB\-mno\-flush\-func
+\&\-mbranch\-likely \-mno\-branch\-likely
+\&\-mfp\-exceptions \-mno\-fp\-exceptions
+\&\-mvr4130\-align \-mno\-vr4130\-align\fR
+.Sp
+\&\fI\s-1MMIX\s0 Options\fR
+\&\fB\-mlibfuncs \-mno\-libfuncs \-mepsilon \-mno\-epsilon \-mabi=gnu
+\&\-mabi=mmixware \-mzero\-extend \-mknuthdiv \-mtoplevel\-symbols
+\&\-melf \-mbranch\-predict \-mno\-branch\-predict \-mbase\-addresses
+\&\-mno\-base\-addresses \-msingle\-exit \-mno\-single\-exit\fR
+.Sp
+\&\fI\s-1MN10300\s0 Options\fR
+\&\fB\-mmult\-bug \-mno\-mult\-bug
+\&\-mam33 \-mno\-am33
+\&\-mam33\-2 \-mno\-am33\-2
+\&\-mreturn\-pointer\-on\-d0
+\&\-mno\-crt0 \-mrelax\fR
+.Sp
+\&\fI\s-1MT\s0 Options\fR
+\&\fB\-mno\-crt0 \-mbacc \-msim
+\&\-march=\fR\fIcpu-type\fR\fB \fR
+.Sp
+\&\fI\s-1PDP\-11\s0 Options\fR
+\&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10
+\&\-mbcopy \-mbcopy\-builtin \-mint32 \-mno\-int16
+\&\-mint16 \-mno\-int32 \-mfloat32 \-mno\-float64
+\&\-mfloat64 \-mno\-float32 \-mabshi \-mno\-abshi
+\&\-mbranch\-expensive \-mbranch\-cheap
+\&\-msplit \-mno\-split \-munix\-asm \-mdec\-asm\fR
+.Sp
+\&\fIPowerPC Options\fR
+See \s-1RS/6000\s0 and PowerPC Options.
+.Sp
\&\fI\s-1RS/6000\s0 and PowerPC Options\fR
\&\fB\-mcpu=\fR\fIcpu-type\fR
\&\fB\-mtune=\fR\fIcpu-type\fR
@@ -434,6 +663,7 @@ in the following sections.
\&\-maltivec \-mno\-altivec
\&\-mpowerpc\-gpopt \-mno\-powerpc\-gpopt
\&\-mpowerpc\-gfxopt \-mno\-powerpc\-gfxopt
+\&\-mmfcrf \-mno\-mfcrf \-mpopcntb \-mno\-popcntb \-mfprnd \-mno\-fprnd
\&\-mnew\-mnemonics \-mold\-mnemonics
\&\-mfull\-toc \-mminimal\-toc \-mno\-fp\-in\-toc \-mno\-sum\-in\-toc
\&\-m64 \-m32 \-mxl\-compat \-mno\-xl\-compat \-mpe
@@ -444,137 +674,73 @@ in the following sections.
\&\-mstrict\-align \-mno\-strict\-align \-mrelocatable
\&\-mno\-relocatable \-mrelocatable\-lib \-mno\-relocatable\-lib
\&\-mtoc \-mno\-toc \-mlittle \-mlittle\-endian \-mbig \-mbig\-endian
-\&\-mdynamic\-no\-pic
+\&\-mdynamic\-no\-pic \-maltivec \-mswdiv
\&\-mprioritize\-restricted\-insns=\fR\fIpriority\fR
\&\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR
\&\fB\-minsert\-sched\-nops=\fR\fIscheme\fR
\&\fB\-mcall\-sysv \-mcall\-netbsd
\&\-maix\-struct\-return \-msvr4\-struct\-return
-\&\-mabi=altivec \-mabi=no\-altivec
-\&\-mabi=spe \-mabi=no\-spe
+\&\-mabi=\fR\fIabi-type\fR \fB\-msecure\-plt \-mbss\-plt
+\&\-misel \-mno\-isel
\&\-misel=yes \-misel=no
+\&\-mspe \-mno\-spe
\&\-mspe=yes \-mspe=no
-\&\-mfloat\-gprs=yes \-mfloat\-gprs=no
+\&\-mvrsave \-mno\-vrsave
+\&\-mmulhw \-mno\-mulhw
+\&\-mdlmzb \-mno\-dlmzb
+\&\-mfloat\-gprs=yes \-mfloat\-gprs=no \-mfloat\-gprs=single \-mfloat\-gprs=double
\&\-mprototype \-mno\-prototype
\&\-msim \-mmvme \-mads \-myellowknife \-memb \-msdata
\&\-msdata=\fR\fIopt\fR \fB\-mvxworks \-mwindiss \-G\fR \fInum\fR \fB\-pthread\fR
.Sp
-\&\fIDarwin Options\fR
-\&\fB\-all_load \-allowable_client \-arch \-arch_errors_fatal
-\&\-arch_only \-bind_at_load \-bundle \-bundle_loader
-\&\-client_name \-compatibility_version \-current_version
-\&\-dependency\-file \-dylib_file \-dylinker_install_name
-\&\-dynamic \-dynamiclib \-exported_symbols_list
-\&\-filelist \-flat_namespace \-force_cpusubtype_ALL
-\&\-force_flat_namespace \-headerpad_max_install_names
-\&\-image_base \-init \-install_name \-keep_private_externs
-\&\-multi_module \-multiply_defined \-multiply_defined_unused
-\&\-noall_load \-nofixprebinding \-nomultidefs \-noprebind \-noseglinkedit
-\&\-pagezero_size \-prebind \-prebind_all_twolevel_modules
-\&\-private_bundle \-read_only_relocs \-sectalign
-\&\-sectobjectsymbols \-whyload \-seg1addr
-\&\-sectcreate \-sectobjectsymbols \-sectorder
-\&\-seg_addr_table \-seg_addr_table_filename \-seglinkedit
-\&\-segprot \-segs_read_only_addr \-segs_read_write_addr
-\&\-single_module \-static \-sub_library \-sub_umbrella
-\&\-twolevel_namespace \-umbrella \-undefined
-\&\-unexported_symbols_list \-weak_reference_mismatches
-\&\-whatsloaded\fR
-.Sp
-\&\fI\s-1MIPS\s0 Options\fR
-\&\fB\-EL \-EB \-march=\fR\fIarch\fR \fB\-mtune=\fR\fIarch\fR
-\&\fB\-mips1 \-mips2 \-mips3 \-mips4 \-mips32 \-mips32r2 \-mips64
-\&\-mips16 \-mno\-mips16 \-mabi=\fR\fIabi\fR \fB\-mabicalls \-mno\-abicalls
-\&\-mxgot \-mno\-xgot \-membedded\-pic \-mno\-embedded\-pic
-\&\-mgp32 \-mgp64 \-mfp32 \-mfp64 \-mhard\-float \-msoft\-float
-\&\-msingle\-float \-mdouble\-float \-mint64 \-mlong64 \-mlong32
-\&\-G\fR\fInum\fR \fB\-membedded\-data \-mno\-embedded\-data
-\&\-muninit\-const\-in\-rodata \-mno\-uninit\-const\-in\-rodata
-\&\-msplit\-addresses \-mno\-split\-addresses
-\&\-mexplicit\-relocs \-mno\-explicit\-relocs
-\&\-mrnames \-mno\-rnames
-\&\-mcheck\-zero\-division \-mno\-check\-zero\-division
-\&\-mmemcpy \-mno\-memcpy \-mlong\-calls \-mno\-long\-calls
-\&\-mmad \-mno\-mad \-mfused\-madd \-mno\-fused\-madd \-nocpp
-\&\-mfix\-sb1 \-mno\-fix\-sb1 \-mflush\-func=\fR\fIfunc\fR
-\&\fB\-mno\-flush\-func \-mbranch\-likely \-mno\-branch\-likely\fR
-.Sp
-\&\fIi386 and x86\-64 Options\fR
+\&\fIS/390 and zSeries Options\fR
\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR
-\&\fB\-mfpmath=\fR\fIunit\fR
-\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387
-\&\-mno\-fp\-ret\-in\-387 \-msoft\-float \-msvr3\-shlib
-\&\-mno\-wide\-multiply \-mrtd \-malign\-double
-\&\-mpreferred\-stack\-boundary=\fR\fInum\fR
-\&\fB\-mmmx \-msse \-msse2 \-msse3 \-m3dnow
-\&\-mthreads \-mno\-align\-stringops \-minline\-all\-stringops
-\&\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double
-\&\-m96bit\-long\-double \-mregparm=\fR\fInum\fR \fB\-momit\-leaf\-frame\-pointer
-\&\-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs
-\&\-mcmodel=\fR\fIcode-model\fR
-\&\fB\-m32 \-m64\fR
-.Sp
-\&\fI\s-1HPPA\s0 Options\fR
-\&\fB\-march=\fR\fIarchitecture-type\fR
-\&\fB\-mbig\-switch \-mdisable\-fpregs \-mdisable\-indexing
-\&\-mfast\-indirect\-calls \-mgas \-mgnu\-ld \-mhp\-ld
-\&\-mjump\-in\-delay \-mlinker\-opt \-mlong\-calls
-\&\-mlong\-load\-store \-mno\-big\-switch \-mno\-disable\-fpregs
-\&\-mno\-disable\-indexing \-mno\-fast\-indirect\-calls \-mno\-gas
-\&\-mno\-jump\-in\-delay \-mno\-long\-load\-store
-\&\-mno\-portable\-runtime \-mno\-soft\-float
-\&\-mno\-space\-regs \-msoft\-float \-mpa\-risc\-1\-0
-\&\-mpa\-risc\-1\-1 \-mpa\-risc\-2\-0 \-mportable\-runtime
-\&\-mschedule=\fR\fIcpu-type\fR \fB\-mspace\-regs \-msio \-mwsio
-\&\-nolibdld \-static \-threads\fR
-.Sp
-\&\fIIntel 960 Options\fR
-\&\fB\-m\fR\fIcpu-type\fR \fB\-masm\-compat \-mclean\-linkage
-\&\-mcode\-align \-mcomplex\-addr \-mleaf\-procedures
-\&\-mic\-compat \-mic2.0\-compat \-mic3.0\-compat
-\&\-mintel\-asm \-mno\-clean\-linkage \-mno\-code\-align
-\&\-mno\-complex\-addr \-mno\-leaf\-procedures
-\&\-mno\-old\-align \-mno\-strict\-align \-mno\-tail\-call
-\&\-mnumerics \-mold\-align \-msoft\-float \-mstrict\-align
-\&\-mtail\-call\fR
-.Sp
-\&\fI\s-1DEC\s0 Alpha Options\fR
-\&\fB\-mno\-fp\-regs \-msoft\-float \-malpha\-as \-mgas
-\&\-mieee \-mieee\-with\-inexact \-mieee\-conformant
-\&\-mfp\-trap\-mode=\fR\fImode\fR \fB\-mfp\-rounding\-mode=\fR\fImode\fR
-\&\fB\-mtrap\-precision=\fR\fImode\fR \fB\-mbuild\-constants
-\&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR
-\&\fB\-mbwx \-mmax \-mfix \-mcix
-\&\-mfloat\-vax \-mfloat\-ieee
-\&\-mexplicit\-relocs \-msmall\-data \-mlarge\-data
-\&\-msmall\-text \-mlarge\-text
-\&\-mmemory\-latency=\fR\fItime\fR
+\&\fB\-mhard\-float \-msoft\-float \-mlong\-double\-64 \-mlong\-double\-128
+\&\-mbackchain \-mno\-backchain \-mpacked\-stack \-mno\-packed\-stack
+\&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle
+\&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch
+\&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd
+\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR
.Sp
-\&\fI\s-1DEC\s0 Alpha/VMS Options\fR
-\&\fB\-mvms\-return\-codes\fR
-.Sp
-\&\fIH8/300 Options\fR
-\&\fB\-mrelax \-mh \-ms \-mn \-mint32 \-malign\-300\fR
+\&\fIScore Options\fR
+\&\fB\-meb \-mel
+\&\-mnhwloop
+\&\-muls
+\&\-mmac
+\&\-mscore5 \-mscore5u \-mscore7 \-mscore7d\fR
.Sp
\&\fI\s-1SH\s0 Options\fR
\&\fB\-m1 \-m2 \-m2e \-m3 \-m3e
\&\-m4\-nofpu \-m4\-single\-only \-m4\-single \-m4
+\&\-m4a\-nofpu \-m4a\-single\-only \-m4a\-single \-m4a \-m4al
\&\-m5\-64media \-m5\-64media\-nofpu
\&\-m5\-32media \-m5\-32media\-nofpu
\&\-m5\-compact \-m5\-compact\-nofpu
\&\-mb \-ml \-mdalign \-mrelax
-\&\-mbigtable \-mfmovd \-mhitachi \-mnomacsave
+\&\-mbigtable \-mfmovd \-mhitachi \-mrenesas \-mno\-renesas \-mnomacsave
\&\-mieee \-misize \-mpadstruct \-mspace
-\&\-mprefergot \-musermode\fR
+\&\-mprefergot \-musermode \-multcost=\fR\fInumber\fR \fB\-mdiv=\fR\fIstrategy\fR
+\&\fB\-mdivsi3_libfunc=\fR\fIname\fR
+\&\fB\-madjust\-unroll \-mindexed\-addressing \-mgettrcost=\fR\fInumber\fR \fB\-mpt\-fixed
+ \-minvalid\-symbols\fR
+.Sp
+\&\fI\s-1SPARC\s0 Options\fR
+\&\fB\-mcpu=\fR\fIcpu-type\fR
+\&\fB\-mtune=\fR\fIcpu-type\fR
+\&\fB\-mcmodel=\fR\fIcode-model\fR
+\&\fB\-m32 \-m64 \-mapp\-regs \-mno\-app\-regs
+\&\-mfaster\-structs \-mno\-faster\-structs
+\&\-mfpu \-mno\-fpu \-mhard\-float \-msoft\-float
+\&\-mhard\-quad\-float \-msoft\-quad\-float
+\&\-mimpure\-text \-mno\-impure\-text \-mlittle\-endian
+\&\-mstack\-bias \-mno\-stack\-bias
+\&\-munaligned\-doubles \-mno\-unaligned\-doubles
+\&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis
+\&\-threads \-pthreads \-pthread\fR
.Sp
\&\fISystem V Options\fR
\&\fB\-Qy \-Qn \-YP,\fR\fIpaths\fR \fB\-Ym,\fR\fIdir\fR
.Sp
-\&\fI\s-1ARC\s0 Options\fR
-\&\fB\-EB \-EL
-\&\-mmangle\-cpu \-mcpu=\fR\fIcpu\fR \fB\-mtext=\fR\fItext-section\fR
-\&\fB\-mdata=\fR\fIdata-section\fR \fB\-mrodata=\fR\fIreadonly-data-section\fR
-.Sp
\&\fITMS320C3x/C4x Options\fR
\&\fB\-mcpu=\fR\fIcpu\fR \fB\-mbig \-msmall \-mregparm \-mmemparm
\&\-mfast\-fix \-mmpyi \-mbk \-mti \-mdp\-isr\-reload
@@ -591,67 +757,11 @@ in the following sections.
\&\-mv850e
\&\-mv850 \-mbig\-switch\fR
.Sp
-\&\fI\s-1NS32K\s0 Options\fR
-\&\fB\-m32032 \-m32332 \-m32532 \-m32081 \-m32381
-\&\-mmult\-add \-mnomult\-add \-msoft\-float \-mrtd \-mnortd
-\&\-mregparam \-mnoregparam \-msb \-mnosb
-\&\-mbitfield \-mnobitfield \-mhimem \-mnohimem\fR
-.Sp
-\&\fI\s-1AVR\s0 Options\fR
-\&\fB\-mmcu=\fR\fImcu\fR \fB\-msize \-minit\-stack=\fR\fIn\fR \fB\-mno\-interrupts
-\&\-mcall\-prologues \-mno\-tablejump \-mtiny\-stack\fR
-.Sp
-\&\fIMCore Options\fR
-\&\fB\-mhardlit \-mno\-hardlit \-mdiv \-mno\-div \-mrelax\-immediates
-\&\-mno\-relax\-immediates \-mwide\-bitfields \-mno\-wide\-bitfields
-\&\-m4byte\-functions \-mno\-4byte\-functions \-mcallgraph\-data
-\&\-mno\-callgraph\-data \-mslow\-bytes \-mno\-slow\-bytes \-mno\-lsim
-\&\-mlittle\-endian \-mbig\-endian \-m210 \-m340 \-mstack\-increment\fR
-.Sp
-\&\fI\s-1MMIX\s0 Options\fR
-\&\fB\-mlibfuncs \-mno\-libfuncs \-mepsilon \-mno\-epsilon \-mabi=gnu
-\&\-mabi=mmixware \-mzero\-extend \-mknuthdiv \-mtoplevel\-symbols
-\&\-melf \-mbranch\-predict \-mno\-branch\-predict \-mbase\-addresses
-\&\-mno\-base\-addresses \-msingle\-exit \-mno\-single\-exit\fR
-.Sp
-\&\fI\s-1IA\-64\s0 Options\fR
-\&\fB\-mbig\-endian \-mlittle\-endian \-mgnu\-as \-mgnu\-ld \-mno\-pic
-\&\-mvolatile\-asm\-stop \-mb\-step \-mregister\-names \-mno\-sdata
-\&\-mconstant\-gp \-mauto\-pic \-minline\-float\-divide\-min\-latency
-\&\-minline\-float\-divide\-max\-throughput
-\&\-minline\-int\-divide\-min\-latency
-\&\-minline\-int\-divide\-max\-throughput
-\&\-minline\-sqrt\-min\-latency \-minline\-sqrt\-max\-throughput
-\&\-mno\-dwarf2\-asm \-mearly\-stop\-bits
-\&\-mfixed\-range=\fR\fIregister-range\fR \fB\-mtls\-size=\fR\fItls-size\fR
-\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-mt \-pthread \-milp32 \-mlp64\fR
-.Sp
-\&\fID30V Options\fR
-\&\fB\-mextmem \-mextmemory \-monchip \-mno\-asm\-optimize
-\&\-masm\-optimize \-mbranch\-cost=\fR\fIn\fR \fB\-mcond\-exec=\fR\fIn\fR
-.Sp
-\&\fIS/390 and zSeries Options\fR
-\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR
-\&\fB\-mhard\-float \-msoft\-float \-mbackchain \-mno\-backchain
-\&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle
-\&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch \-mfused\-madd \-mno\-fused\-madd\fR
-.Sp
-\&\fI\s-1CRIS\s0 Options\fR
-\&\fB\-mcpu=\fR\fIcpu\fR \fB\-march=\fR\fIcpu\fR \fB\-mtune=\fR\fIcpu\fR
-\&\fB\-mmax\-stack\-frame=\fR\fIn\fR \fB\-melinux\-stacksize=\fR\fIn\fR
-\&\fB\-metrax4 \-metrax100 \-mpdebug \-mcc\-init \-mno\-side\-effects
-\&\-mstack\-align \-mdata\-align \-mconst\-align
-\&\-m32\-bit \-m16\-bit \-m8\-bit \-mno\-prologue\-epilogue \-mno\-gotplt
-\&\-melf \-maout \-melinux \-mlinux \-sim \-sim2
-\&\-mmul\-bug\-workaround \-mno\-mul\-bug\-workaround\fR
+\&\fI\s-1VAX\s0 Options\fR
+\&\fB\-mg \-mgnu \-munix\fR
.Sp
-\&\fI\s-1PDP\-11\s0 Options\fR
-\&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10
-\&\-mbcopy \-mbcopy\-builtin \-mint32 \-mno\-int16
-\&\-mint16 \-mno\-int32 \-mfloat32 \-mno\-float64
-\&\-mfloat64 \-mno\-float32 \-mabshi \-mno\-abshi
-\&\-mbranch\-expensive \-mbranch\-cheap
-\&\-msplit \-mno\-split \-munix\-asm \-mdec\-asm\fR
+\&\fIx86\-64 Options\fR
+See i386 and x86\-64 Options.
.Sp
\&\fIXstormy16 Options\fR
\&\fB\-msim\fR
@@ -663,19 +773,8 @@ in the following sections.
\&\-mtarget\-align \-mno\-target\-align
\&\-mlongcalls \-mno\-longcalls\fR
.Sp
-\&\fI\s-1FRV\s0 Options\fR
-\&\fB\-mgpr\-32 \-mgpr\-64 \-mfpr\-32 \-mfpr\-64
-\&\-mhard\-float \-msoft\-float
-\&\-malloc\-cc \-mfixed\-cc \-mdword \-mno\-dword
-\&\-mdouble \-mno\-double
-\&\-mmedia \-mno\-media \-mmuladd \-mno\-muladd
-\&\-mlibrary\-pic \-macc\-4 \-macc\-8
-\&\-mpack \-mno\-pack \-mno\-eflags \-mcond\-move \-mno\-cond\-move
-\&\-mscc \-mno\-scc \-mcond\-exec \-mno\-cond\-exec
-\&\-mvliw\-branch \-mno\-vliw\-branch
-\&\-mmulti\-cond\-exec \-mno\-multi\-cond\-exec \-mnested\-cond\-exec
-\&\-mno\-nested\-cond\-exec \-mtomcat\-stats
-\&\-mcpu=\fR\fIcpu\fR
+\&\fIzSeries Options\fR
+See S/390 and zSeries Options.
.IP "\fICode Generation Options\fR" 4
.IX Item "Code Generation Options"
\&\fB\-fcall\-saved\-\fR\fIreg\fR \fB\-fcall\-used\-\fR\fIreg\fR
@@ -685,14 +784,16 @@ in the following sections.
\&\-finhibit\-size\-directive \-finstrument\-functions
\&\-fno\-common \-fno\-ident
\&\-fpcc\-struct\-return \-fpic \-fPIC \-fpie \-fPIE
-\&\-freg\-struct\-return \-fshared\-data \-fshort\-enums
+\&\-fno\-jump\-tables
+\&\-freg\-struct\-return \-fshort\-enums
\&\-fshort\-double \-fshort\-wchar
-\&\-fverbose\-asm \-fpack\-struct \-fstack\-check
+\&\-fverbose\-asm \-fpack\-struct[=\fR\fIn\fR\fB] \-fstack\-check
\&\-fstack\-limit\-register=\fR\fIreg\fR \fB\-fstack\-limit\-symbol=\fR\fIsym\fR
\&\fB\-fargument\-alias \-fargument\-noalias
-\&\-fargument\-noalias\-global \-fleading\-underscore
-\&\-ftls\-model=\fR\fImodel\fR
-\&\fB\-ftrapv \-fwrapv \-fbounds\-check\fR
+\&\-fargument\-noalias\-global \-fargument\-noalias\-anything
+\&\-fleading\-underscore \-ftls\-model=\fR\fImodel\fR
+\&\fB\-ftrapv \-fwrapv \-fbounds\-check
+\&\-fvisibility\fR
.Sh "Options Controlling the Kind of Output"
.IX Subsection "Options Controlling the Kind of Output"
Compilation can involve up to four stages: preprocessing, compilation
@@ -716,14 +817,27 @@ C source code which should not be preprocessed.
\&\*(C+ source code which should not be preprocessed.
.IP "\fIfile\fR\fB.m\fR" 4
.IX Item "file.m"
-Objective-C source code. Note that you must link with the library
-\&\fIlibobjc.a\fR to make an Objective-C program work.
+Objective-C source code. Note that you must link with the \fIlibobjc\fR
+library to make an Objective-C program work.
.IP "\fIfile\fR\fB.mi\fR" 4
.IX Item "file.mi"
Objective-C source code which should not be preprocessed.
+.IP "\fIfile\fR\fB.mm\fR" 4
+.IX Item "file.mm"
+.PD 0
+.IP "\fIfile\fR\fB.M\fR" 4
+.IX Item "file.M"
+.PD
+Objective\-\*(C+ source code. Note that you must link with the \fIlibobjc\fR
+library to make an Objective\-\*(C+ program work. Note that \fB.M\fR refers
+to a literal capital M.
+.IP "\fIfile\fR\fB.mii\fR" 4
+.IX Item "file.mii"
+Objective\-\*(C+ source code which should not be preprocessed.
.IP "\fIfile\fR\fB.h\fR" 4
.IX Item "file.h"
-C or \*(C+ header file to be turned into a precompiled header.
+C, \*(C+, Objective-C or Objective\-\*(C+ header file to be turned into a
+precompiled header.
.IP "\fIfile\fR\fB.cc\fR" 4
.IX Item "file.cc"
.PD 0
@@ -743,6 +857,16 @@ C or \*(C+ header file to be turned into a precompiled header.
\&\*(C+ source code which must be preprocessed. Note that in \fB.cxx\fR,
the last two letters must both be literally \fBx\fR. Likewise,
\&\fB.C\fR refers to a literal capital C.
+.IP "\fIfile\fR\fB.mm\fR" 4
+.IX Item "file.mm"
+.PD 0
+.IP "\fIfile\fR\fB.M\fR" 4
+.IX Item "file.M"
+.PD
+Objective\-\*(C+ source code which must be preprocessed.
+.IP "\fIfile\fR\fB.mii\fR" 4
+.IX Item "file.mii"
+Objective\-\*(C+ source code which should not be preprocessed.
.IP "\fIfile\fR\fB.hh\fR" 4
.IX Item "file.hh"
.PD 0
@@ -758,7 +882,7 @@ the last two letters must both be literally \fBx\fR. Likewise,
.IP "\fIfile\fR\fB.FOR\fR" 4
.IX Item "file.FOR"
.PD
-Fortran source code which should not be preprocessed.
+Fixed form Fortran source code which should not be preprocessed.
.IP "\fIfile\fR\fB.F\fR" 4
.IX Item "file.F"
.PD 0
@@ -767,12 +891,23 @@ Fortran source code which should not be preprocessed.
.IP "\fIfile\fR\fB.FPP\fR" 4
.IX Item "file.FPP"
.PD
-Fortran source code which must be preprocessed (with the traditional
+Fixed form Fortran source code which must be preprocessed (with the traditional
preprocessor).
-.IP "\fIfile\fR\fB.r\fR" 4
-.IX Item "file.r"
-Fortran source code which must be preprocessed with a \s-1RATFOR\s0
-preprocessor (not included with \s-1GCC\s0).
+.IP "\fIfile\fR\fB.f90\fR" 4
+.IX Item "file.f90"
+.PD 0
+.IP "\fIfile\fR\fB.f95\fR" 4
+.IX Item "file.f95"
+.PD
+Free form Fortran source code which should not be preprocessed.
+.IP "\fIfile\fR\fB.F90\fR" 4
+.IX Item "file.F90"
+.PD 0
+.IP "\fIfile\fR\fB.F95\fR" 4
+.IX Item "file.F95"
+.PD
+Free form Fortran source code which must be preprocessed (with the
+traditional preprocessor).
.IP "\fIfile\fR\fB.ads\fR" 4
.IX Item "file.ads"
Ada source code file which contains a library unit declaration (a
@@ -803,13 +938,14 @@ Specify explicitly the \fIlanguage\fR for the following input files
name suffix). This option applies to all following input files until
the next \fB\-x\fR option. Possible values for \fIlanguage\fR are:
.Sp
-.Vb 8
-\& c c-header cpp-output
+.Vb 9
+\& c c-header c-cpp-output
\& c++ c++-header c++-cpp-output
-\& objective-c objective-c-header objc-cpp-output
+\& objective-c objective-c-header objective-c-cpp-output
+\& objective-c++ objective-c++-header objective-c++-cpp-output
\& assembler assembler-with-cpp
\& ada
-\& f77 f77-cpp-input ratfor
+\& f95 f95-cpp-input
\& java
\& treelang
.Ve
@@ -824,7 +960,8 @@ Normally the \fBgcc\fR program will exit with the code of 1 if any
phase of the compiler returns a non-success return code. If you specify
\&\fB\-pass\-exit\-codes\fR, the \fBgcc\fR program will instead return with
numerically highest error produced by any phase that returned an error
-indication.
+indication. The C, \*(C+, and Fortran frontends return 4, if an internal
+compiler error is encountered.
.PP
If you only want some of the stages of compilation, you can use
\&\fB\-x\fR (or filename suffixes) to tell \fBgcc\fR where to start, and
@@ -865,14 +1002,12 @@ Place output in file \fIfile\fR. This applies regardless to whatever
sort of output is being produced, whether it be an executable file,
an object file, an assembler file or preprocessed C code.
.Sp
-If you specify \fB\-o\fR when compiling more than one input file, or
-you are producing an executable file as output, all the source files
-on the command line will be compiled at once.
-.Sp
-If \fB\-o\fR is not specified, the default is to put an executable file
-in \fIa.out\fR, the object file for \fI\fIsource\fI.\fIsuffix\fI\fR in
-\&\fI\fIsource\fI.o\fR, its assembler file in \fI\fIsource\fI.s\fR, and
-all preprocessed C source on standard output.
+If \fB\-o\fR is not specified, the default is to put an executable
+file in \fIa.out\fR, the object file for
+\&\fI\fIsource\fI.\fIsuffix\fI\fR in \fI\fIsource\fI.o\fR, its
+assembler file in \fI\fIsource\fI.s\fR, a precompiled header file in
+\&\fI\fIsource\fI.\fIsuffix\fI.gch\fR, and all preprocessed C source on
+standard output.
.IP "\fB\-v\fR" 4
.IX Item "-v"
Print (on standard error output) the commands executed to run the stages
@@ -889,6 +1024,22 @@ Use pipes rather than temporary files for communication between the
various stages of compilation. This fails to work on some systems where
the assembler is unable to read from a pipe; but the \s-1GNU\s0 assembler has
no trouble.
+.IP "\fB\-combine\fR" 4
+.IX Item "-combine"
+If you are compiling multiple source files, this option tells the driver
+to pass all the source files to the compiler at once (for those
+languages for which the compiler can handle this). This will allow
+intermodule analysis (\s-1IMA\s0) to be performed by the compiler. Currently the only
+language for which this is supported is C. If you pass source files for
+multiple languages to the driver, using this option, the driver will invoke
+the compiler(s) that support \s-1IMA\s0 once each, passing each compiler all the
+source files appropriate for it. For those languages that do not support
+\&\s-1IMA\s0 this option will be ignored, and the compiler will be invoked once for
+each source file in that language. If you use this option in conjunction
+with \fB\-save\-temps\fR, the compiler will generate multiple
+pre-processed files
+(one for each source file), but only one (combined) \fI.o\fR or
+\&\fI.s\fR file.
.IP "\fB\-\-help\fR" 4
.IX Item "--help"
Print (on the standard output) a description of the command line options
@@ -905,6 +1056,19 @@ line options for each tool.
.IP "\fB\-\-version\fR" 4
.IX Item "--version"
Display the version number and copyrights of the invoked \s-1GCC\s0.
+.IP "\fB@\fR\fIfile\fR" 4
+.IX Item "@file"
+Read command-line options from \fIfile\fR. The options read are
+inserted in place of the original @\fIfile\fR option. If \fIfile\fR
+does not exist, or cannot be read, then the option will be treated
+literally, and not removed.
+.Sp
+Options in \fIfile\fR are separated by whitespace. A whitespace
+character may be included in an option by surrounding the entire
+option in either single or double quotes. Any character (including a
+backslash) may be included by prefixing the character to be included
+with a backslash. The \fIfile\fR may itself contain additional
+@\fIfile\fR options; any such options will be processed recursively.
.Sh "Compiling \*(C+ Programs"
.IX Subsection "Compiling Programs"
\&\*(C+ source files conventionally use one of the suffixes \fB.C\fR,
@@ -915,15 +1079,14 @@ files with these names and compiles them as \*(C+ programs even if you
call the compiler the same way as for compiling C programs (usually
with the name \fBgcc\fR).
.PP
-However, \*(C+ programs often require class libraries as well as a
-compiler that understands the \*(C+ language\-\-\-and under some
-circumstances, you might want to compile programs or header files from
-standard input, or otherwise without a suffix that flags them as \*(C+
-programs. You might also like to precompile a C header file with a
-\&\fB.h\fR extension to be used in \*(C+ compilations. \fBg++\fR is a
-program that calls \s-1GCC\s0 with the default language set to \*(C+, and
-automatically specifies linking against the \*(C+ library. On many
-systems, \fBg++\fR is also installed with the name \fBc++\fR.
+However, the use of \fBgcc\fR does not add the \*(C+ library.
+\&\fBg++\fR is a program that calls \s-1GCC\s0 and treats \fB.c\fR,
+\&\fB.h\fR and \fB.i\fR files as \*(C+ source files instead of C source
+files unless \fB\-x\fR is used, and automatically specifies linking
+against the \*(C+ library. This program is also useful when
+precompiling a C header file with a \fB.h\fR extension for use in \*(C+
+compilations. On many systems, \fBg++\fR is also installed with
+the name \fBc++\fR.
.PP
When you compile \*(C+ programs, you may specify many of the same
command-line options that you use for compiling programs in any
@@ -932,7 +1095,8 @@ languages; or options that are meaningful only for \*(C+ programs.
.Sh "Options Controlling C Dialect"
.IX Subsection "Options Controlling C Dialect"
The following options control the dialect of C (or languages derived
-from C, such as \*(C+ and Objective\-C) that the compiler accepts:
+from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler
+accepts:
.IP "\fB\-ansi\fR" 4
.IX Item "-ansi"
In C mode, support all \s-1ISO\s0 C90 programs. In \*(C+ mode,
@@ -995,7 +1159,7 @@ provided; possible values are
.IX Item "iso9899:199x"
.PD
\&\s-1ISO\s0 C99. Note that this standard is not yet fully supported; see
-<\fBhttp://gcc.gnu.org/gcc\-3.4/c99status.html\fR> for more information. The
+<\fBhttp://gcc.gnu.org/gcc\-4.2/c99status.html\fR> for more information. The
names \fBc9x\fR and \fBiso9899:199x\fR are deprecated.
.IP "\fBgnu89\fR" 4
.IX Item "gnu89"
@@ -1028,6 +1192,26 @@ effects as \fB\-ansi\fR, except that features that were not in \s-1ISO\s0 C90
but are in the specified version (for example, \fB//\fR comments and
the \f(CW\*(C`inline\*(C'\fR keyword in \s-1ISO\s0 C99) are not disabled.
.RE
+.IP "\fB\-fgnu89\-inline\fR" 4
+.IX Item "-fgnu89-inline"
+The option \fB\-fgnu89\-inline\fR tells \s-1GCC\s0 to use the traditional
+\&\s-1GNU\s0 semantics for \f(CW\*(C`inline\*(C'\fR functions when in C99 mode.
+ Using this
+option is roughly equivalent to adding the \f(CW\*(C`gnu_inline\*(C'\fR function
+attribute to all inline functions.
+.Sp
+This option is accepted by \s-1GCC\s0 versions 4.1.3 and up. In \s-1GCC\s0 versions
+prior to 4.3, C99 inline semantics are not supported, and thus this
+option is effectively assumed to be present regardless of whether or not
+it is specified; the only effect of specifying it explicitly is to
+disable warnings about using inline functions in C99 mode. Likewise,
+the option \fB\-fno\-gnu89\-inline\fR is not supported in versions of
+\&\s-1GCC\s0 before 4.3. It will be supported only in C99 or gnu99 mode, not in
+C89 or gnu89 mode.
+.Sp
+The preprocesor macros \f(CW\*(C`_\|_GNUC_GNU_INLINE_\|_\*(C'\fR and
+\&\f(CW\*(C`_\|_GNUC_STDC_INLINE_\|_\*(C'\fR may be used to check which semantics are
+in effect for \f(CW\*(C`inline\*(C'\fR functions.
.IP "\fB\-aux\-info\fR \fIfilename\fR" 4
.IX Item "-aux-info filename"
Output to the given filename prototyped declarations for all functions
@@ -1071,7 +1255,14 @@ instructions that adjust the stack directly, and calls to \f(CW\*(C`memcpy\*(C'\
may become inline copy loops. The resulting code is often both smaller
and faster, but since the function calls no longer appear as such, you
cannot set a breakpoint on those calls, nor can you change the behavior
-of the functions by linking with a different library.
+of the functions by linking with a different library. In addition,
+when a function is recognized as a built-in function, \s-1GCC\s0 may use
+information about that function to warn about problems with calls to
+that function, or to generate more efficient code, even if the
+resulting code still contains calls to that function. For example,
+warnings are given with \fB\-Wformat\fR for bad calls to
+\&\f(CW\*(C`printf\*(C'\fR, when \f(CW\*(C`printf\*(C'\fR is built in, and \f(CW\*(C`strlen\*(C'\fR is
+known not to modify global memory.
.Sp
With the \fB\-fno\-builtin\-\fR\fIfunction\fR option
only the built-in function \fIfunction\fR is
@@ -1100,9 +1291,18 @@ implies \fB\-fno\-builtin\fR. A freestanding environment
is one in which the standard library may not exist, and program startup may
not necessarily be at \f(CW\*(C`main\*(C'\fR. The most obvious example is an \s-1OS\s0 kernel.
This is equivalent to \fB\-fno\-hosted\fR.
+.IP "\fB\-fopenmp\fR" 4
+.IX Item "-fopenmp"
+Enable handling of OpenMP directives \f(CW\*(C`#pragma omp\*(C'\fR in C/\*(C+ and
+\&\f(CW\*(C`!$omp\*(C'\fR in Fortran. When \fB\-fopenmp\fR is specified, the
+compiler generates parallel code according to the OpenMP Application
+Program Interface v2.5 <\fBhttp://www.openmp.org/\fR>.
.IP "\fB\-fms\-extensions\fR" 4
.IX Item "-fms-extensions"
Accept some non-standard constructs used in Microsoft header files.
+.Sp
+Some cases of unnamed fields in structures and unions are only
+accepted with this option.
.IP "\fB\-trigraphs\fR" 4
.IX Item "-trigraphs"
Support \s-1ISO\s0 C trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR
@@ -1111,9 +1311,9 @@ options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR.
.IX Item "-no-integrated-cpp"
Performs a compilation in two passes: preprocessing and compiling. This
option allows a user supplied \*(L"cc1\*(R", \*(L"cc1plus\*(R", or \*(L"cc1obj\*(R" via the
-\&\fB\-B\fR option. The user supplied compilation step can then add in
+\&\fB\-B\fR option. The user supplied compilation step can then add in
an additional preprocessing step after normal preprocessing but before
-compiling. The default is to use the integrated cpp (internal cpp)
+compiling. The default is to use the integrated cpp (internal cpp)
.Sp
The semantics of this option will change if \*(L"cc1\*(R", \*(L"cc1plus\*(R", and
\&\*(L"cc1obj\*(R" are merged.
@@ -1171,16 +1371,6 @@ These options control whether a bit-field is signed or unsigned, when the
declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By
default, such a bit-field is signed, because this is consistent: the
basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types.
-.IP "\fB\-fwritable\-strings\fR" 4
-.IX Item "-fwritable-strings"
-Store string constants in the writable data segment and don't uniquize
-them. This is for compatibility with old programs which assume they can
-write into string constants.
-.Sp
-Writing into string constants is a very bad idea; ``constants'' should
-be constant.
-.Sp
-This option is deprecated.
.Sh "Options Controlling \*(C+ Dialect"
.IX Subsection "Options Controlling Dialect"
This section describes the command-line options that are only meaningful
@@ -1233,17 +1423,19 @@ two definitions were merged.
.Sp
This option is no longer useful on most targets, now that support has
been added for putting variables into \s-1BSS\s0 without making them common.
-.IP "\fB\-fno\-const\-strings\fR" 4
-.IX Item "-fno-const-strings"
-Give string constants type \f(CW\*(C`char *\*(C'\fR instead of type \f(CW\*(C`const
-char *\*(C'\fR. By default, G++ uses type \f(CW\*(C`const char *\*(C'\fR as required by
-the standard. Even if you use \fB\-fno\-const\-strings\fR, you cannot
-actually modify the value of a string constant, unless you also use
-\&\fB\-fwritable\-strings\fR.
-.Sp
-This option might be removed in a future release of G++. For maximum
-portability, you should structure your code so that it works with
-string constants that have type \f(CW\*(C`const char *\*(C'\fR.
+.IP "\fB\-ffriend\-injection\fR" 4
+.IX Item "-ffriend-injection"
+Inject friend functions into the enclosing namespace, so that they are
+visible outside the scope of the class in which they are declared.
+Friend functions were documented to work this way in the old Annotated
+\&\*(C+ Reference Manual, and versions of G++ before 4.1 always worked
+that way. However, in \s-1ISO\s0 \*(C+ a friend function which is not declared
+in an enclosing scope can only be found using argument dependent
+lookup. This option causes friends to be injected as they were in
+earlier releases.
+.Sp
+This option is for compatibility, and may be removed in a future
+release of G++.
.IP "\fB\-fno\-elide\-constructors\fR" 4
.IX Item "-fno-elide-constructors"
The \*(C+ standard allows an implementation to omit creating a temporary
@@ -1252,10 +1444,13 @@ Specifying this option disables that optimization, and forces G++ to
call the copy constructor in all cases.
.IP "\fB\-fno\-enforce\-eh\-specs\fR" 4
.IX Item "-fno-enforce-eh-specs"
-Don't check for violation of exception specifications at runtime. This
-option violates the \*(C+ standard, but may be useful for reducing code
-size in production builds, much like defining \fB\s-1NDEBUG\s0\fR. The compiler
-will still optimize based on the exception specifications.
+Don't generate code to check for violation of exception specifications
+at runtime. This option violates the \*(C+ standard, but may be useful
+for reducing code size in production builds, much like defining
+\&\fB\s-1NDEBUG\s0\fR. This does not give user code permission to throw
+exceptions in violation of the exception specifications; the compiler
+will still optimize based on the specifications, so throwing an
+unexpected exception will result in undefined behavior.
.IP "\fB\-ffor\-scope\fR" 4
.IX Item "-ffor-scope"
.PD 0
@@ -1327,7 +1522,9 @@ functions for use by the \*(C+ runtime type identification features
(\fBdynamic_cast\fR and \fBtypeid\fR). If you don't use those parts
of the language, you can save some space by using this flag. Note that
exception handling uses the same information, but it will generate it as
-needed.
+needed. The \fBdynamic_cast\fR operator can still be used for casts that
+do not require runtime type information, i.e. casts to \f(CW\*(C`void *\*(C'\fR or to
+unambiguous base classes.
.IP "\fB\-fstats\fR" 4
.IX Item "-fstats"
Emit statistics about front-end processing at the end of the compilation.
@@ -1338,6 +1535,12 @@ Set the maximum instantiation depth for template classes to \fIn\fR.
A limit on the template instantiation depth is needed to detect
endless recursions during template class instantiation. \s-1ANSI/ISO\s0 \*(C+
conforming programs must not rely on a maximum depth greater than 17.
+.IP "\fB\-fno\-threadsafe\-statics\fR" 4
+.IX Item "-fno-threadsafe-statics"
+Do not emit the extra code to use the routines specified in the \*(C+
+\&\s-1ABI\s0 for thread-safe initialization of local statics. You can use this
+option to reduce code size slightly in code that doesn't need to be
+thread\-safe.
.IP "\fB\-fuse\-cxa\-atexit\fR" 4
.IX Item "-fuse-cxa-atexit"
Register destructors for objects with static storage duration with the
@@ -1345,6 +1548,37 @@ Register destructors for objects with static storage duration with the
This option is required for fully standards-compliant handling of static
destructors, but will only work if your C library supports
\&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR.
+.IP "\fB\-fno\-use\-cxa\-get\-exception\-ptr\fR" 4
+.IX Item "-fno-use-cxa-get-exception-ptr"
+Don't use the \f(CW\*(C`_\|_cxa_get_exception_ptr\*(C'\fR runtime routine. This
+will cause \f(CW\*(C`std::uncaught_exception\*(C'\fR to be incorrect, but is necessary
+if the runtime routine is not available.
+.IP "\fB\-fvisibility\-inlines\-hidden\fR" 4
+.IX Item "-fvisibility-inlines-hidden"
+This switch declares that the user does not attempt to compare
+pointers to inline methods where the addresses of the two functions
+were taken in different shared objects.
+.Sp
+The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with
+\&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not
+appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection
+when used within the \s-1DSO\s0. Enabling this option can have a dramatic effect
+on load and link times of a \s-1DSO\s0 as it massively reduces the size of the
+dynamic export table when the library makes heavy use of templates.
+.Sp
+The behaviour of this switch is not quite the same as marking the
+methods as hidden directly, because it does not affect static variables
+local to the function or cause the compiler to deduce that
+the function is defined in only one shared object.
+.Sp
+You may mark a method as having a visibility explicitly to negate the
+effect of the switch for that method. For example, if you do want to
+compare pointers to a particular inline method, you might mark it as
+having default visibility. Marking the enclosing class with explicit
+visibility will have no effect.
+.Sp
+Explicitly instantiated inline methods are unaffected by this option
+as their linkage might otherwise cross a shared library boundary.
.IP "\fB\-fno\-weak\fR" 4
.IX Item "-fno-weak"
Do not use weak symbol support, even if it is provided by the linker.
@@ -1468,8 +1702,8 @@ public static member functions.
.IP "\fB\-Wnon\-virtual\-dtor\fR (\*(C+ only)" 4
.IX Item "-Wnon-virtual-dtor ( only)"
Warn when a class appears to be polymorphic, thereby requiring a virtual
-destructor, yet it declares a non-virtual one.
-This warning is enabled by \fB\-Wall\fR.
+destructor, yet it declares a non-virtual one. This warning is also
+enabled if \-Weffc++ is specified.
.IP "\fB\-Wreorder\fR (\*(C+ only)" 4
.IX Item "-Wreorder ( only)"
Warn when the order of member initializers given in the code does not
@@ -1524,6 +1758,13 @@ to filter out those warnings.
.IP "\fB\-Wno\-deprecated\fR (\*(C+ only)" 4
.IX Item "-Wno-deprecated ( only)"
Do not warn about usage of deprecated features.
+.IP "\fB\-Wstrict\-null\-sentinel\fR (\*(C+ only)" 4
+.IX Item "-Wstrict-null-sentinel ( only)"
+Warn also about the use of an uncasted \f(CW\*(C`NULL\*(C'\fR as sentinel. When
+compiling only with \s-1GCC\s0 this is a valid sentinel, as \f(CW\*(C`NULL\*(C'\fR is defined
+to \f(CW\*(C`_\|_null\*(C'\fR. Although it is a null pointer constant not a null pointer,
+it is guaranteed to of the same size as a pointer. But this use is
+not portable across different compilers.
.IP "\fB\-Wno\-non\-template\-friend\fR (\*(C+ only)" 4
.IX Item "-Wno-non-template-friend ( only)"
Disable warnings when non-templatized friend functions are declared
@@ -1542,9 +1783,9 @@ but disables the helpful warning.
.IP "\fB\-Wold\-style\-cast\fR (\*(C+ only)" 4
.IX Item "-Wold-style-cast ( only)"
Warn if an old-style (C\-style) cast to a non-void type is used within
-a \*(C+ program. The new-style casts (\fBstatic_cast\fR,
-\&\fBreinterpret_cast\fR, and \fBconst_cast\fR) are less vulnerable to
-unintended effects and much easier to search for.
+a \*(C+ program. The new-style casts (\fBdynamic_cast\fR,
+\&\fBstatic_cast\fR, \fBreinterpret_cast\fR, and \fBconst_cast\fR) are
+less vulnerable to unintended effects and much easier to search for.
.IP "\fB\-Woverloaded\-virtual\fR (\*(C+ only)" 4
.IX Item "-Woverloaded-virtual ( only)"
Warn when a function declaration hides virtual functions from a
@@ -1599,26 +1840,31 @@ unsignedness, but the standard mandates the current behavior.
.Sp
In this example, G++ will synthesize a default \fBA& operator =
(const A&);\fR, while cfront will use the user-defined \fBoperator =\fR.
-.Sh "Options Controlling Objective-C Dialect"
-.IX Subsection "Options Controlling Objective-C Dialect"
-(\s-1NOTE:\s0 This manual does not describe the Objective-C language itself. See
-<\fBhttp://gcc.gnu.org/readings.html\fR> for references.)
+.Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects"
+.IX Subsection "Options Controlling Objective-C and Objective- Dialects"
+(\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+
+languages themselves. See
.PP
This section describes the command-line options that are only meaningful
-for Objective-C programs, but you can also use most of the \s-1GNU\s0 compiler
-options regardless of what language your program is in. For example,
-you might compile a file \f(CW\*(C`some_class.m\*(C'\fR like this:
+for Objective-C and Objective\-\*(C+ programs, but you can also use most of
+the language-independent \s-1GNU\s0 compiler options.
+For example, you might compile a file \f(CW\*(C`some_class.m\*(C'\fR like this:
.PP
.Vb 1
\& gcc -g -fgnu-runtime -O -c some_class.m
.Ve
.PP
In this example, \fB\-fgnu\-runtime\fR is an option meant only for
-Objective-C programs; you can use the other options with any language
-supported by \s-1GCC\s0.
+Objective-C and Objective\-\*(C+ programs; you can use the other options with
+any language supported by \s-1GCC\s0.
+.PP
+Note that since Objective-C is an extension of the C language, Objective-C
+compilations may also use options specific to the C front-end (e.g.,
+\&\fB\-Wtraditional\fR). Similarly, Objective\-\*(C+ compilations may use
+\&\*(C+\-specific options (e.g., \fB\-Wabi\fR).
.PP
Here is a list of options that are \fIonly\fR for compiling Objective-C
-programs:
+and Objective\-\*(C+ programs:
.IP "\fB\-fconstant\-string\-class=\fR\fIclass-name\fR" 4
.IX Item "-fconstant-string-class=class-name"
Use \fIclass-name\fR as the name of the class to instantiate for each
@@ -1642,14 +1888,42 @@ used.
.IX Item "-fno-nil-receivers"
Assume that all Objective-C message dispatches (e.g.,
\&\f(CW\*(C`[receiver message:arg]\*(C'\fR) in this translation unit ensure that the receiver
-is not \f(CW\*(C`nil\*(C'\fR. This allows for more efficient entry points in the runtime to be
-used. Currently, this option is only available in conjunction with
+is not \f(CW\*(C`nil\*(C'\fR. This allows for more efficient entry points in the runtime
+to be used. Currently, this option is only available in conjunction with
the NeXT runtime on Mac \s-1OS\s0 X 10.3 and later.
+.IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4
+.IX Item "-fobjc-call-cxx-cdtors"
+For each Objective-C class, check if any of its instance variables is a
+\&\*(C+ object with a non-trivial default constructor. If so, synthesize a
+special \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR instance method that will run
+non-trivial default constructors on any such instance variables, in order,
+and then return \f(CW\*(C`self\*(C'\fR. Similarly, check if any instance variable
+is a \*(C+ object with a non-trivial destructor, and if so, synthesize a
+special \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR method that will run
+all such default destructors, in reverse order.
+.Sp
+The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and/or \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods
+thusly generated will only operate on instance variables declared in the
+current Objective-C class, and not those inherited from superclasses. It
+is the responsibility of the Objective-C runtime to invoke all such methods
+in an object's inheritance hierarchy. The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR methods
+will be invoked by the runtime immediately after a new object
+instance is allocated; the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods will
+be invoked immediately before the runtime deallocates an object instance.
+.Sp
+As of this writing, only the NeXT runtime on Mac \s-1OS\s0 X 10.4 and later has
+support for invoking the \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and
+\&\f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods.
+.IP "\fB\-fobjc\-direct\-dispatch\fR" 4
+.IX Item "-fobjc-direct-dispatch"
+Allow fast jumps to the message dispatcher. On Darwin this is
+accomplished via the comm page.
.IP "\fB\-fobjc\-exceptions\fR" 4
.IX Item "-fobjc-exceptions"
Enable syntactic support for structured exception handling in Objective\-C,
-similar to what is offered by \*(C+ and Java. Currently, this option is only
-available in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.3 and later.
+similar to what is offered by \*(C+ and Java. This option is
+unavailable in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.2 and
+earlier.
.Sp
.Vb 23
\& @try {
@@ -1736,6 +2010,9 @@ Unlike Java, Objective-C does not allow for entire methods to be marked
\&\f(CW@synchronized\fR blocks is allowed, and will cause the guarding object
to be unlocked properly.
.RE
+.IP "\fB\-fobjc\-gc\fR" 4
+.IX Item "-fobjc-gc"
+Enable garbage collection (\s-1GC\s0) in Objective-C and Objective\-\*(C+ programs.
.IP "\fB\-freplace\-objc\-classes\fR" 4
.IX Item "-freplace-objc-classes"
Emit a special marker instructing \fB\f(BIld\fB\|(1)\fR not to statically link in
@@ -1759,13 +2036,17 @@ for individual class implementations to be modified during program execution.
.IX Item "-gen-decls"
Dump interface declarations for all classes seen in the source file to a
file named \fI\fIsourcename\fI.decl\fR.
+.IP "\fB\-Wassign\-intercept\fR" 4
+.IX Item "-Wassign-intercept"
+Warn whenever an Objective-C assignment is being intercepted by the
+garbage collector.
.IP "\fB\-Wno\-protocol\fR" 4
.IX Item "-Wno-protocol"
If a class is declared to implement a protocol, a warning is issued for
every method in the protocol that is not implemented by the class. The
default behavior is to issue a warning for every method not explicitly
implemented in the class, even if a method implementation is inherited
-from the superclass. If you use the \f(CW\*(C`\-Wno\-protocol\*(C'\fR option, then
+from the superclass. If you use the \fB\-Wno\-protocol\fR option, then
methods inherited from the superclass are considered to be implemented,
and no warning is issued for them.
.IP "\fB\-Wselector\fR" 4
@@ -1778,8 +2059,16 @@ expression, and a corresponding method for that selector has been found
during compilation. Because these checks scan the method table only at
the end of compilation, these warnings are not produced if the final
stage of compilation is not reached, for example because an error is
-found during compilation, or because the \f(CW\*(C`\-fsyntax\-only\*(C'\fR option is
+found during compilation, or because the \fB\-fsyntax\-only\fR option is
being used.
+.IP "\fB\-Wstrict\-selector\-match\fR" 4
+.IX Item "-Wstrict-selector-match"
+Warn if multiple methods with differing argument and/or return types are
+found for a given selector when attempting to send a message using this
+selector to a receiver of type \f(CW\*(C`id\*(C'\fR or \f(CW\*(C`Class\*(C'\fR. When this flag
+is off (which is the default behavior), the compiler will omit such warnings
+if any differences found are confined to types which share the same size
+and alignment.
.IP "\fB\-Wundeclared\-selector\fR" 4
.IX Item "-Wundeclared-selector"
Warn if a \f(CW\*(C`@selector(...)\*(C'\fR expression referring to an
@@ -1789,7 +2078,7 @@ method with that name has been declared before the
\&\f(CW@interface\fR or \f(CW@protocol\fR declaration, or implicitly in
an \f(CW@implementation\fR section. This option always performs its
checks as soon as a \f(CW\*(C`@selector(...)\*(C'\fR expression is found,
-while \f(CW\*(C`\-Wselector\*(C'\fR only performs its checks in the final stage of
+while \fB\-Wselector\fR only performs its checks in the final stage of
compilation. This also enforces the coding style convention
that methods and selectors must be declared before being used.
.IP "\fB\-print\-objc\-runtime\-info\fR" 4
@@ -1826,6 +2115,12 @@ Only meaningful in line-wrapping mode. Instructs the diagnostic
messages reporter to emit the same source location information (as
prefix) for physical lines that result from the process of breaking
a message which is too long to fit on a single line.
+.IP "\fB\-fdiagnostics\-show\-option\fR" 4
+.IX Item "-fdiagnostics-show-option"
+This option instructs the diagnostic machinery to add text to each
+diagnostic emitted, which indicates which command line option directly
+controls that diagnostic, when such an option is known to the
+diagnostic machinery.
.Sh "Options to Request or Suppress Warnings"
.IX Subsection "Options to Request or Suppress Warnings"
Warnings are diagnostic messages that report constructions which
@@ -1841,7 +2136,8 @@ two forms, whichever is not the default.
.PP
The following options control the amount and kinds of warnings produced
by \s-1GCC\s0; for further, language-specific options also refer to
-\&\fB\*(C+ Dialect Options\fR and \fBObjective-C Dialect Options\fR.
+\&\fB\*(C+ Dialect Options\fR and \fBObjective-C and Objective\-\*(C+ Dialect
+Options\fR.
.IP "\fB\-fsyntax\-only\fR" 4
.IX Item "-fsyntax-only"
Check the code for syntax errors, but don't do anything beyond that.
@@ -1899,10 +2195,17 @@ Inhibit warning messages about the use of \fB#import\fR.
Warn if an array subscript has type \f(CW\*(C`char\*(C'\fR. This is a common cause
of error, as programmers often forget that this type is signed on some
machines.
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wcomment\fR" 4
.IX Item "-Wcomment"
Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR
comment, or whenever a Backslash-Newline appears in a \fB//\fR comment.
+This warning is enabled by \fB\-Wall\fR.
+.IP "\fB\-Wfatal\-errors\fR" 4
+.IX Item "-Wfatal-errors"
+This option causes the compiler to abort compilation on the first error
+occurred rather than trying to keep going and printing further error
+messages.
.IP "\fB\-Wformat\fR" 4
.IX Item "-Wformat"
Check calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR, etc., to make sure that
@@ -1911,7 +2214,11 @@ specified, and that the conversions specified in the format string make
sense. This includes standard functions, and others specified by format
attributes, in the \f(CW\*(C`printf\*(C'\fR,
\&\f(CW\*(C`scanf\*(C'\fR, \f(CW\*(C`strftime\*(C'\fR and \f(CW\*(C`strfmon\*(C'\fR (an X/Open extension,
-not in the C standard) families.
+not in the C standard) families (or other target-specific families).
+Which functions are checked without format attributes having been
+specified depends on the standard version selected, and such checks of
+functions without the attribute specified are disabled by
+\&\fB\-ffreestanding\fR or \fB\-fno\-builtin\fR.
.Sp
The formats are checked against the format features supported by \s-1GNU\s0
libc version 2.2. These include all \s-1ISO\s0 C90 and C99 features, as well
@@ -1980,8 +2287,8 @@ requiring a non-null value by the \f(CW\*(C`nonnull\*(C'\fR function attribute.
.Sp
\&\fB\-Wnonnull\fR is included in \fB\-Wall\fR and \fB\-Wformat\fR. It
can be disabled with the \fB\-Wno\-nonnull\fR option.
-.IP "\fB\-Winit\-self\fR (C, \*(C+, and Objective-C only)" 4
-.IX Item "-Winit-self (C, , and Objective-C only)"
+.IP "\fB\-Winit\-self\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4
+.IX Item "-Winit-self (C, , Objective-C and Objective- only)"
Warn about uninitialized variables which are initialized with themselves.
Note this option can only be used with the \fB\-Wuninitialized\fR option,
which in turn only works with \fB\-O1\fR and above.
@@ -1999,6 +2306,7 @@ following snippet only when \fB\-Winit\-self\fR has been specified:
.IP "\fB\-Wimplicit\-int\fR" 4
.IX Item "-Wimplicit-int"
Warn when a declaration does not specify a type.
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wimplicit\-function\-declaration\fR" 4
.IX Item "-Wimplicit-function-declaration"
.PD 0
@@ -2006,15 +2314,19 @@ Warn when a declaration does not specify a type.
.IX Item "-Werror-implicit-function-declaration"
.PD
Give a warning (or error) whenever a function is used before being
-declared.
+declared. The form \fB\-Wno\-error\-implicit\-function\-declaration\fR
+is not supported.
+This warning is enabled by \fB\-Wall\fR (as a warning, not an error).
.IP "\fB\-Wimplicit\fR" 4
.IX Item "-Wimplicit"
Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR.
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wmain\fR" 4
.IX Item "-Wmain"
Warn if the type of \fBmain\fR is suspicious. \fBmain\fR should be a
function with external linkage, returning int, taking either zero
arguments, two, or three arguments of appropriate types.
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wmissing\-braces\fR" 4
.IX Item "-Wmissing-braces"
Warn if an aggregate or union initializer is not fully bracketed. In
@@ -2025,12 +2337,23 @@ bracketed, but that for \fBb\fR is fully bracketed.
\& int a[2][2] = { 0, 1, 2, 3 };
\& int b[2][2] = { { 0, 1 }, { 2, 3 } };
.Ve
+.Sp
+This warning is enabled by \fB\-Wall\fR.
+.IP "\fB\-Wmissing\-include\-dirs\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4
+.IX Item "-Wmissing-include-dirs (C, , Objective-C and Objective- only)"
+Warn if a user-supplied include directory does not exist.
.IP "\fB\-Wparentheses\fR" 4
.IX Item "-Wparentheses"
Warn if parentheses are omitted in certain contexts, such
as when there is an assignment in a context where a truth value
is expected, or when operators are nested whose precedence people
-often get confused about.
+often get confused about. Only the warning for an assignment used as
+a truth value is supported when compiling \*(C+; the other warnings are
+only supported when compiling C.
+.Sp
+Also warn if a comparison like \fBx<=y<=z\fR appears; this is
+equivalent to \fB(x<=y ? 1 : 0) <= z\fR, which is a different
+interpretation from that of ordinary mathematical notation.
.Sp
Also warn about constructions where there may be confusion to which
\&\f(CW\*(C`if\*(C'\fR statement an \f(CW\*(C`else\*(C'\fR branch belongs. Here is an example of
@@ -2066,17 +2389,19 @@ the enclosing \f(CW\*(C`if\*(C'\fR. The resulting code would look like this:
\& }
\& }
.Ve
+.Sp
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wsequence\-point\fR" 4
.IX Item "-Wsequence-point"
Warn about code that may have undefined semantics because of violations
-of sequence point rules in the C standard.
-.Sp
-The C standard defines the order in which expressions in a C program are
-evaluated in terms of \fIsequence points\fR, which represent a partial
-ordering between the execution of parts of the program: those executed
-before the sequence point, and those executed after it. These occur
-after the evaluation of a full expression (one which is not part of a
-larger expression), after the evaluation of the first operand of a
+of sequence point rules in the C and \*(C+ standards.
+.Sp
+The C and \*(C+ standards defines the order in which expressions in a C/\*(C+
+program are evaluated in terms of \fIsequence points\fR, which represent
+a partial ordering between the execution of parts of the program: those
+executed before the sequence point, and those executed after it. These
+occur after the evaluation of a full expression (one which is not part
+of a larger expression), after the evaluation of the first operand of a
\&\f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, \f(CW\*(C`? :\*(C'\fR or \f(CW\*(C`,\*(C'\fR (comma) operator, before a
function is called (but after the evaluation of its arguments and the
expression denoting the called function), and in certain other places.
@@ -2090,11 +2415,11 @@ ruled that function calls do not overlap.
.Sp
It is not specified when between sequence points modifications to the
values of objects take effect. Programs whose behavior depends on this
-have undefined behavior; the C standard specifies that ``Between the
-previous and next sequence point an object shall have its stored value
-modified at most once by the evaluation of an expression. Furthermore,
-the prior value shall be read only to determine the value to be
-stored.''. If a program breaks these rules, the results on any
+have undefined behavior; the C and \*(C+ standards specify that \*(L"Between
+the previous and next sequence point an object shall have its stored
+value modified at most once by the evaluation of an expression.
+Furthermore, the prior value shall be read only to determine the value
+to be stored.\*(R". If a program breaks these rules, the results on any
particular implementation are entirely unpredictable.
.Sp
Examples of code with undefined behavior are \f(CW\*(C`a = a++;\*(C'\fR, \f(CW\*(C`a[n]
@@ -2103,23 +2428,30 @@ diagnosed by this option, and it may give an occasional false positive
result, but in general it has been found fairly effective at detecting
this sort of problem in programs.
.Sp
-The present implementation of this option only works for C programs. A
-future implementation may also work for \*(C+ programs.
-.Sp
-The C standard is worded confusingly, therefore there is some debate
+The standard is worded confusingly, therefore there is some debate
over the precise meaning of the sequence point rules in subtle cases.
Links to discussions of the problem, including proposed formal
definitions, may be found on the \s-1GCC\s0 readings page, at
<\fBhttp://gcc.gnu.org/readings.html\fR>.
+.Sp
+This warning is enabled by \fB\-Wall\fR for C and \*(C+.
.IP "\fB\-Wreturn\-type\fR" 4
.IX Item "-Wreturn-type"
Warn whenever a function is defined with a return-type that defaults to
\&\f(CW\*(C`int\*(C'\fR. Also warn about any \f(CW\*(C`return\*(C'\fR statement with no
return-value in a function whose return-type is not \f(CW\*(C`void\*(C'\fR.
.Sp
+For C, also warn if the return type of a function has a type qualifier
+such as \f(CW\*(C`const\*(C'\fR. Such a type qualifier has no effect, since the
+value returned by a function is not an lvalue. \s-1ISO\s0 C prohibits
+qualified \f(CW\*(C`void\*(C'\fR return types on function definitions, so such
+return types always receive a warning even without this option.
+.Sp
For \*(C+, a function without return type always produces a diagnostic
message, even when \fB\-Wno\-return\-type\fR is specified. The only
exceptions are \fBmain\fR and functions defined in system headers.
+.Sp
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wswitch\fR" 4
.IX Item "-Wswitch"
Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type
@@ -2127,6 +2459,7 @@ and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that
enumeration. (The presence of a \f(CW\*(C`default\*(C'\fR label prevents this
warning.) \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also
provoke warnings when this option is used.
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wswitch\-default\fR" 4
.IX Item "-Wswitch-default"
Warn whenever a \f(CW\*(C`switch\*(C'\fR statement does not have a \f(CW\*(C`default\*(C'\fR
@@ -2141,13 +2474,16 @@ provoke warnings when this option is used.
.IX Item "-Wtrigraphs"
Warn if any trigraphs are encountered that might change the meaning of
the program (trigraphs within comments are not warned about).
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wunused\-function\fR" 4
.IX Item "-Wunused-function"
Warn whenever a static function is declared but not defined or a
-non\e\-inline static function is unused.
+non-inline static function is unused.
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wunused\-label\fR" 4
.IX Item "-Wunused-label"
Warn whenever a label is declared but not used.
+This warning is enabled by \fB\-Wall\fR.
.Sp
To suppress this warning use the \fBunused\fR attribute.
.IP "\fB\-Wunused\-parameter\fR" 4
@@ -2158,12 +2494,14 @@ To suppress this warning use the \fBunused\fR attribute.
.IP "\fB\-Wunused\-variable\fR" 4
.IX Item "-Wunused-variable"
Warn whenever a local variable or non-constant static variable is unused
-aside from its declaration
+aside from its declaration.
+This warning is enabled by \fB\-Wall\fR.
.Sp
To suppress this warning use the \fBunused\fR attribute.
.IP "\fB\-Wunused\-value\fR" 4
.IX Item "-Wunused-value"
Warn whenever a statement computes a result that is explicitly not used.
+This warning is enabled by \fB\-Wall\fR.
.Sp
To suppress this warning cast the expression to \fBvoid\fR.
.IP "\fB\-Wunused\fR" 4
@@ -2180,17 +2518,20 @@ if a variable may be clobbered by a \f(CW\*(C`setjmp\*(C'\fR call.
.Sp
These warnings are possible only in optimizing compilation,
because they require data flow information that is computed only
-when optimizing. If you don't specify \fB\-O\fR, you simply won't
-get these warnings.
+when optimizing. If you do not specify \fB\-O\fR, you will not get
+these warnings. Instead, \s-1GCC\s0 will issue a warning about \fB\-Wuninitialized\fR
+requiring \fB\-O\fR.
.Sp
If you want to warn about code which uses the uninitialized value of the
variable in its own initializer, use the \fB\-Winit\-self\fR option.
.Sp
-These warnings occur only for variables that are candidates for
-register allocation. Therefore, they do not occur for a variable that
-is declared \f(CW\*(C`volatile\*(C'\fR, or whose address is taken, or whose size
-is other than 1, 2, 4 or 8 bytes. Also, they do not occur for
-structures, unions or arrays, even when they are in registers.
+These warnings occur for individual uninitialized or clobbered
+elements of structure, union or array variables as well as for
+variables which are uninitialized or clobbered as a whole. They do
+not occur for variables or elements declared \f(CW\*(C`volatile\*(C'\fR. Because
+these warnings depend on optimization, the exact variables or elements
+for which there are warnings will depend on the precise optimization
+options and version of \s-1GCC\s0 used.
.Sp
Note that there may be no warning about a variable that is used only
to compute a value that itself is never used, because such
@@ -2244,19 +2585,90 @@ in fact be called at the place which would cause a problem.
.Sp
Some spurious warnings can be avoided if you declare all the functions
you use that never return as \f(CW\*(C`noreturn\*(C'\fR.
+.Sp
+This warning is enabled by \fB\-Wall\fR.
.IP "\fB\-Wunknown\-pragmas\fR" 4
.IX Item "-Wunknown-pragmas"
Warn when a #pragma directive is encountered which is not understood by
\&\s-1GCC\s0. If this command line option is used, warnings will even be issued
for unknown pragmas in system header files. This is not the case if
the warnings were only enabled by the \fB\-Wall\fR command line option.
+.IP "\fB\-Wno\-pragmas\fR" 4
+.IX Item "-Wno-pragmas"
+Do not warn about misuses of pragmas, such as incorrect parameters,
+invalid syntax, or conflicts between pragmas. See also
+\&\fB\-Wunknown\-pragmas\fR.
.IP "\fB\-Wstrict\-aliasing\fR" 4
.IX Item "-Wstrict-aliasing"
This option is only active when \fB\-fstrict\-aliasing\fR is active.
It warns about code which might break the strict aliasing rules that the
-compiler is using for optimization. The warning does not catch all
-cases, but does attempt to catch the more common pitfalls. It is
+compiler is using for optimization. The warning does not catch all
+cases, but does attempt to catch the more common pitfalls. It is
included in \fB\-Wall\fR.
+.IP "\fB\-Wstrict\-aliasing=2\fR" 4
+.IX Item "-Wstrict-aliasing=2"
+This option is only active when \fB\-fstrict\-aliasing\fR is active.
+It warns about code which might break the strict aliasing rules that the
+compiler is using for optimization. This warning catches more cases than
+\&\fB\-Wstrict\-aliasing\fR, but it will also give a warning for some ambiguous
+cases that are safe.
+.IP "\fB\-Wstrict\-overflow\fR" 4
+.IX Item "-Wstrict-overflow"
+.PD 0
+.IP "\fB\-Wstrict\-overflow=\fR\fIn\fR" 4
+.IX Item "-Wstrict-overflow=n"
+.PD
+This option is only active when \fB\-fstrict\-overflow\fR is active.
+It warns about cases where the compiler optimizes based on the
+assumption that signed overflow does not occur. Note that it does not
+warn about all cases where the code might overflow: it only warns
+about cases where the compiler implements some optimization. Thus
+this warning depends on the optimization level.
+.Sp
+An optimization which assumes that signed overflow does not occur is
+perfectly safe if the values of the variables involved are such that
+overflow never does, in fact, occur. Therefore this warning can
+easily give a false positive: a warning about code which is not
+actually a problem. To help focus on important issues, several
+warning levels are defined. No warnings are issued for the use of
+undefined signed overflow when estimating how many iterations a loop
+will require, in particular when determining whether a loop will be
+executed at all.
+.RS 4
+.IP "@option<\-Wstrict\-overflow=1>" 4
+.IX Item "@option<-Wstrict-overflow=1>"
+Warn about cases which are both questionable and easy to avoid. For
+example: \f(CW\*(C`x + 1 > x\*(C'\fR; with \fB\-fstrict\-overflow\fR, the
+compiler will simplify this to \f(CW1\fR. This level of
+\&\fB\-Wstrict\-overflow\fR is enabled by \fB\-Wall\fR; higher levels
+are not, and must be explicitly requested.
+.IP "@option<\-Wstrict\-overflow=2>" 4
+.IX Item "@option<-Wstrict-overflow=2>"
+Also warn about other cases where a comparison is simplified to a
+constant. For example: \f(CW\*(C`abs (x) >= 0\*(C'\fR. This can only be
+simplified when \fB\-fstrict\-overflow\fR is in effect, because
+\&\f(CW\*(C`abs (INT_MIN)\*(C'\fR overflows to \f(CW\*(C`INT_MIN\*(C'\fR, which is less than
+zero. \fB\-Wstrict\-overflow\fR (with no level) is the same as
+\&\fB\-Wstrict\-overflow=2\fR.
+.IP "@option<\-Wstrict\-overflow=3>" 4
+.IX Item "@option<-Wstrict-overflow=3>"
+Also warn about other cases where a comparison is simplified. For
+example: \f(CW\*(C`x + 1 > 1\*(C'\fR will be simplified to \f(CW\*(C`x > 0\*(C'\fR.
+.IP "@option<\-Wstrict\-overflow=4>" 4
+.IX Item "@option<-Wstrict-overflow=4>"
+Also warn about other simplifications not covered by the above cases.
+For example: \f(CW\*(C`(x * 10) / 5\*(C'\fR will be simplified to \f(CW\*(C`x * 2\*(C'\fR.
+.IP "@option<\-Wstrict\-overflow=5>" 4
+.IX Item "@option<-Wstrict-overflow=5>"
+Also warn about cases where the compiler reduces the magnitude of a
+constant involved in a comparison. For example: \f(CW\*(C`x + 2 > y\*(C'\fR will
+be simplified to \f(CW\*(C`x + 1 >= y\*(C'\fR. This is reported only at the
+highest warning level because this simplification applies to many
+comparisons, so this warning level will give a very large number of
+false positives.
+.RE
+.RS 4
+.RE
.IP "\fB\-Wall\fR" 4
.IX Item "-Wall"
All of the above \fB\-W\fR options combined. This enables all the
@@ -2264,7 +2676,7 @@ warnings about constructions that some users consider questionable, and
that are easy to avoid (or modify to prevent the warning), even in
conjunction with macros. This also enables some language-specific
warnings described in \fB\*(C+ Dialect Options\fR and
-\&\fBObjective-C Dialect Options\fR.
+\&\fBObjective-C and Objective\-\*(C+ Dialect Options\fR.
.PP
The following \fB\-W...\fR options are not implied by \fB\-Wall\fR.
Some of them warn about constructions that users generally do not
@@ -2300,19 +2712,9 @@ but \fBx[(void)i,j]\fR will not.
.IP "*" 4
An unsigned value is compared against zero with \fB<\fR or \fB>=\fR.
.IP "*" 4
-A comparison like \fBx<=y<=z\fR appears; this is equivalent to
-\&\fB(x<=y ? 1 : 0) <= z\fR, which is a different interpretation from
-that of ordinary mathematical notation.
-.IP "*" 4
Storage-class specifiers like \f(CW\*(C`static\*(C'\fR are not the first things in
a declaration. According to the C Standard, this usage is obsolescent.
.IP "*" 4
-The return type of a function has a type qualifier such as \f(CW\*(C`const\*(C'\fR.
-Such a type qualifier has no effect, since the value returned by a
-function is not an lvalue. (But don't warn about the \s-1GNU\s0 extension of
-\&\f(CW\*(C`volatile void\*(C'\fR return types. That extension will be warned about
-if \fB\-pedantic\fR is specified.)
-.IP "*" 4
If \fB\-Wall\fR or \fB\-Wunused\fR is also specified, warn about unused
arguments.
.IP "*" 4
@@ -2321,13 +2723,12 @@ incorrect result when the signed value is converted to unsigned.
(But don't warn if \fB\-Wno\-sign\-compare\fR is also specified.)
.IP "*" 4
An aggregate has an initializer which does not initialize all members.
-For example, the following code would cause such a warning, because
-\&\f(CW\*(C`x.h\*(C'\fR would be implicitly initialized to zero:
-.Sp
-.Vb 2
-\& struct s { int f, g, h; };
-\& struct s x = { 3, 4 };
-.Ve
+This warning can be independently controlled by
+\&\fB\-Wmissing\-field\-initializers\fR.
+.IP "*" 4
+An initialized field without side effects is overridden when using
+designated initializers. This warning can be independently controlled by
+\&\fB\-Woverride\-init\fR.
.IP "*" 4
A function parameter is declared without a type specifier in K&R\-style
functions:
@@ -2342,9 +2743,6 @@ A pointer is compared against integer zero with \fB<\fR, \fB<=\fR,
\&\fB>\fR, or \fB>=\fR.
.IP "*" 4
A variable might be changed by \fBlongjmp\fR or \fBvfork\fR.
-.IP "*" 4
-Any of several floating-point events that often indicate errors, such as
-overflow, underflow, loss of precision, etc.
.IP "*<(\*(C+ only)>" 4
.IX Item "*<( only)>"
An enumerator and a non-enumerator both appear in a conditional expression.
@@ -2479,9 +2877,9 @@ allowed in \s-1GCC\s0. It is not supported by \s-1ISO\s0 C90 and was not suppor
.IP "\fB\-Wundef\fR" 4
.IX Item "-Wundef"
Warn if an undefined identifier is evaluated in an \fB#if\fR directive.
-.IP "\fB\-Wendif\-labels\fR" 4
-.IX Item "-Wendif-labels"
-Warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text.
+.IP "\fB\-Wno\-endif\-labels\fR" 4
+.IX Item "-Wno-endif-labels"
+Do not warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text.
.IP "\fB\-Wshadow\fR" 4
.IX Item "-Wshadow"
Warn whenever a local variable shadows another local variable, parameter or
@@ -2489,9 +2887,15 @@ global variable or whenever a built-in function is shadowed.
.IP "\fB\-Wlarger\-than\-\fR\fIlen\fR" 4
.IX Item "-Wlarger-than-len"
Warn whenever an object of larger than \fIlen\fR bytes is defined.
+.IP "\fB\-Wunsafe\-loop\-optimizations\fR" 4
+.IX Item "-Wunsafe-loop-optimizations"
+Warn if the loop cannot be optimized because the compiler could not
+assume anything on the bounds of the loop indices. With
+\&\fB\-funsafe\-loop\-optimizations\fR warn if the compiler made
+such assumptions.
.IP "\fB\-Wpointer\-arith\fR" 4
.IX Item "-Wpointer-arith"
-Warn about anything that depends on the ``size of'' a function type or
+Warn about anything that depends on the \*(L"size of\*(R" a function type or
of \f(CW\*(C`void\*(C'\fR. \s-1GNU\s0 C assigns these types a size of 1, for
convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers
to functions.
@@ -2499,6 +2903,11 @@ to functions.
.IX Item "-Wbad-function-cast (C only)"
Warn whenever a function call is cast to a non-matching type.
For example, warn if \f(CW\*(C`int malloc()\*(C'\fR is cast to \f(CW\*(C`anything *\*(C'\fR.
+.IP "\fB\-Wc++\-compat\fR" 4
+.IX Item "-Wc++-compat"
+Warn about \s-1ISO\s0 C constructs that are outside of the common subset of
+\&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+, e.g. request for implicit conversion from
+\&\f(CW\*(C`void *\*(C'\fR to a pointer to non\-\f(CW\*(C`void\*(C'\fR type.
.IP "\fB\-Wcast\-qual\fR" 4
.IX Item "-Wcast-qual"
Warn whenever a pointer is cast so as to remove a type qualifier from
@@ -2516,7 +2925,8 @@ When compiling C, give string constants the type \f(CW\*(C`const
char[\f(CIlength\f(CW]\*(C'\fR so that
copying the address of one into a non\-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR
pointer will get a warning; when compiling \*(C+, warn about the
-deprecated conversion from string constants to \f(CW\*(C`char *\*(C'\fR.
+deprecated conversion from string literals to \f(CW\*(C`char *\*(C'\fR. This
+warning, by default, is enabled for \*(C+ programs.
These warnings will help you find at
compile time code that can try to write into a string constant, but
only if you have been very careful about using \f(CW\*(C`const\*(C'\fR in
@@ -2540,11 +2950,30 @@ Warn when a comparison between signed and unsigned values could produce
an incorrect result when the signed value is converted to unsigned.
This warning is also enabled by \fB\-Wextra\fR; to get the other warnings
of \fB\-Wextra\fR without this warning, use \fB\-Wextra \-Wno\-sign\-compare\fR.
+.IP "\fB\-Waddress\fR" 4
+.IX Item "-Waddress"
+Warn about suspicious uses of memory addresses. These include using
+the address of a function in a conditional expression, such as
+\&\f(CW\*(C`void func(void); if (func)\*(C'\fR, and comparisons against the memory
+address of a string literal, such as \f(CW\*(C`if (x == "abc")\*(C'\fR. Such
+uses typically indicate a programmer error: the address of a function
+always evaluates to true, so their use in a conditional usually
+indicate that the programmer forgot the parentheses in a function
+call; and comparisons against string literals result in unspecified
+behavior and are not portable in C, so they usually indicate that the
+programmer intended to use \f(CW\*(C`strcmp\*(C'\fR. This warning is enabled by
+\&\fB\-Wall\fR.
.IP "\fB\-Waggregate\-return\fR" 4
.IX Item "-Waggregate-return"
Warn if any functions that return structures or unions are defined or
called. (In languages where you can return an array, this also elicits
a warning.)
+.IP "\fB\-Wno\-attributes\fR" 4
+.IX Item "-Wno-attributes"
+Do not warn if an unexpected \f(CW\*(C`_\|_attribute_\|_\*(C'\fR is used, such as
+unrecognized attributes, function attributes applied to variables,
+etc. This will not stop errors for incorrect use of supported
+attributes.
.IP "\fB\-Wstrict\-prototypes\fR (C only)" 4
.IX Item "-Wstrict-prototypes (C only)"
Warn if a function is declared or defined without specifying the
@@ -2567,6 +2996,27 @@ Warn if a global function is defined without a previous declaration.
Do so even if the definition itself provides a prototype.
Use this option to detect global functions that are not declared in
header files.
+.IP "\fB\-Wmissing\-field\-initializers\fR" 4
+.IX Item "-Wmissing-field-initializers"
+Warn if a structure's initializer has some fields missing. For
+example, the following code would cause such a warning, because
+\&\f(CW\*(C`x.h\*(C'\fR is implicitly zero:
+.Sp
+.Vb 2
+\& struct s { int f, g, h; };
+\& struct s x = { 3, 4 };
+.Ve
+.Sp
+This option does not warn about designated initializers, so the following
+modification would not trigger a warning:
+.Sp
+.Vb 2
+\& struct s { int f, g, h; };
+\& struct s x = { .f = 3, .g = 4 };
+.Ve
+.Sp
+This warning is included in \fB\-Wextra\fR. To get other \fB\-Wextra\fR
+warnings without this one, use \fB\-Wextra \-Wno\-missing\-field\-initializers\fR.
.IP "\fB\-Wmissing\-noreturn\fR" 4
.IX Item "-Wmissing-noreturn"
Warn about functions which might be candidates for attribute \f(CW\*(C`noreturn\*(C'\fR.
@@ -2577,25 +3027,85 @@ bugs could be introduced. You will not get a warning for \f(CW\*(C`main\*(C'\fR
hosted C environments.
.IP "\fB\-Wmissing\-format\-attribute\fR" 4
.IX Item "-Wmissing-format-attribute"
-If \fB\-Wformat\fR is enabled, also warn about functions which might be
-candidates for \f(CW\*(C`format\*(C'\fR attributes. Note these are only possible
-candidates, not absolute ones. \s-1GCC\s0 will guess that \f(CW\*(C`format\*(C'\fR
-attributes might be appropriate for any function that calls a function
-like \f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the
+Warn about function pointers which might be candidates for \f(CW\*(C`format\*(C'\fR
+attributes. Note these are only possible candidates, not absolute ones.
+\&\s-1GCC\s0 will guess that function pointers with \f(CW\*(C`format\*(C'\fR attributes that
+are used in assignment, initialization, parameter passing or return
+statements should have a corresponding \f(CW\*(C`format\*(C'\fR attribute in the
+resulting type. I.e. the left-hand side of the assignment or
+initialization, the type of the parameter variable, or the return type
+of the containing function respectively should also have a \f(CW\*(C`format\*(C'\fR
+attribute to avoid the warning.
+.Sp
+\&\s-1GCC\s0 will also warn about function definitions which might be
+candidates for \f(CW\*(C`format\*(C'\fR attributes. Again, these are only
+possible candidates. \s-1GCC\s0 will guess that \f(CW\*(C`format\*(C'\fR attributes
+might be appropriate for any function that calls a function like
+\&\f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the
case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are
-appropriate may not be detected. This option has no effect unless
-\&\fB\-Wformat\fR is enabled (possibly by \fB\-Wall\fR).
+appropriate may not be detected.
.IP "\fB\-Wno\-multichar\fR" 4
.IX Item "-Wno-multichar"
Do not warn if a multicharacter constant (\fB'\s-1FOOF\s0'\fR) is used.
Usually they indicate a typo in the user's code, as they have
implementation-defined values, and should not be used in portable code.
+.IP "\fB\-Wnormalized=<none|id|nfc|nfkc>\fR" 4
+.IX Item "-Wnormalized=<none|id|nfc|nfkc>"
+In \s-1ISO\s0 C and \s-1ISO\s0 \*(C+, two identifiers are different if they are
+different sequences of characters. However, sometimes when characters
+outside the basic \s-1ASCII\s0 character set are used, you can have two
+different character sequences that look the same. To avoid confusion,
+the \s-1ISO\s0 10646 standard sets out some \fInormalization rules\fR which
+when applied ensure that two sequences that look the same are turned into
+the same sequence. \s-1GCC\s0 can warn you if you are using identifiers which
+have not been normalized; this option controls that warning.
+.Sp
+There are four levels of warning that \s-1GCC\s0 supports. The default is
+\&\fB\-Wnormalized=nfc\fR, which warns about any identifier which is
+not in the \s-1ISO\s0 10646 \*(L"C\*(R" normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the
+recommended form for most uses.
+.Sp
+Unfortunately, there are some characters which \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ allow
+in identifiers that when turned into \s-1NFC\s0 aren't allowable as
+identifiers. That is, there's no way to use these symbols in portable
+\&\s-1ISO\s0 C or \*(C+ and have all your identifiers in \s-1NFC\s0.
+\&\fB\-Wnormalized=id\fR suppresses the warning for these characters.
+It is hoped that future versions of the standards involved will correct
+this, which is why this option is not the default.
+.Sp
+You can switch the warning off for all characters by writing
+\&\fB\-Wnormalized=none\fR. You would only want to do this if you
+were using some other normalization scheme (like \*(L"D\*(R"), because
+otherwise you can easily create bugs that are literally impossible to see.
+.Sp
+Some characters in \s-1ISO\s0 10646 have distinct meanings but look identical
+in some fonts or display methodologies, especially once formatting has
+been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT\s0 \s-1LATIN\s0 \s-1SMALL\s0
+\&\s-1LETTER\s0 N\*(R", will display just like a regular \f(CW\*(C`n\*(C'\fR which has been
+placed in a superscript. \s-1ISO\s0 10646 defines the \fI\s-1NFKC\s0\fR
+normalization scheme to convert all these into a standard form as
+well, and \s-1GCC\s0 will warn if your code is not in \s-1NFKC\s0 if you use
+\&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning
+about every identifier that contains the letter O because it might be
+confused with the digit 0, and so is not the default, but may be
+useful as a local coding convention if the programming environment is
+unable to be fixed to display these characters distinctly.
.IP "\fB\-Wno\-deprecated\-declarations\fR" 4
.IX Item "-Wno-deprecated-declarations"
-Do not warn about uses of functions, variables, and types marked as
-deprecated by using the \f(CW\*(C`deprecated\*(C'\fR attribute.
-(@pxref{Function Attributes}, \f(CW@pxref\fR{Variable Attributes},
-\&\f(CW@pxref\fR{Type Attributes}.)
+Do not warn about uses of functions,
+variables, and types marked as deprecated by using the \f(CW\*(C`deprecated\*(C'\fR
+attribute.
+.IP "\fB\-Wno\-overflow\fR" 4
+.IX Item "-Wno-overflow"
+Do not warn about compile-time overflow in constant expressions.
+.IP "\fB\-Woverride\-init\fR" 4
+.IX Item "-Woverride-init"
+Warn if an initialized field without side effects is overridden when
+using designated initializers.
+.Sp
+This warning is included in \fB\-Wextra\fR. To get other
+\&\fB\-Wextra\fR warnings without this one, use \fB\-Wextra
+\&\-Wno\-override\-init\fR.
.IP "\fB\-Wpacked\fR" 4
.IX Item "-Wpacked"
Warn if a structure is given the packed attribute, but the packed
@@ -2657,7 +3167,7 @@ inline functions declared in system headers.
.Sp
The compiler uses a variety of heuristics to determine whether or not
to inline a function. For example, the compiler takes into account
-the size of the function being inlined and the the amount of inlining
+the size of the function being inlined and the amount of inlining
that has already been done in the current function. Therefore,
seemingly insignificant changes in the source program can cause the
warnings produced by \fB\-Winline\fR to appear or disappear.
@@ -2675,6 +3185,14 @@ warning about it.
.Sp
The restrictions on \fBoffsetof\fR may be relaxed in a future version
of the \*(C+ standard.
+.IP "\fB\-Wno\-int\-to\-pointer\-cast\fR (C only)" 4
+.IX Item "-Wno-int-to-pointer-cast (C only)"
+Suppress warnings from casts to pointer type of an integer of a
+different size.
+.IP "\fB\-Wno\-pointer\-to\-int\-cast\fR (C only)" 4
+.IX Item "-Wno-pointer-to-int-cast (C only)"
+Suppress warnings from casts from a pointer to an integer type of a
+different size.
.IP "\fB\-Winvalid\-pch\fR" 4
.IX Item "-Winvalid-pch"
Warn if a precompiled header is found in
@@ -2685,6 +3203,16 @@ Warn if \fBlong long\fR type is used. This is default. To inhibit
the warning messages, use \fB\-Wno\-long\-long\fR. Flags
\&\fB\-Wlong\-long\fR and \fB\-Wno\-long\-long\fR are taken into account
only when \fB\-pedantic\fR flag is used.
+.IP "\fB\-Wvariadic\-macros\fR" 4
+.IX Item "-Wvariadic-macros"
+Warn if variadic macros are used in pedantic \s-1ISO\s0 C90 mode, or the \s-1GNU\s0
+alternate syntax when in pedantic \s-1ISO\s0 C99 mode. This is default.
+To inhibit the warning messages, use \fB\-Wno\-variadic\-macros\fR.
+.IP "\fB\-Wvolatile\-register\-var\fR" 4
+.IX Item "-Wvolatile-register-var"
+Warn if a register variable is declared volatile. The volatile
+modifier does not inhibit all optimizations that may eliminate reads
+and/or writes to register variables.
.IP "\fB\-Wdisabled\-optimization\fR" 4
.IX Item "-Wdisabled-optimization"
Warn if a requested optimization pass is disabled. This warning does
@@ -2693,9 +3221,49 @@ merely indicates that \s-1GCC\s0's optimizers were unable to handle the code
effectively. Often, the problem is that your code is too big or too
complex; \s-1GCC\s0 will refuse to optimize programs when the optimization
itself is likely to take inordinate amounts of time.
+.IP "\fB\-Wpointer\-sign\fR" 4
+.IX Item "-Wpointer-sign"
+Warn for pointer argument passing or assignment with different signedness.
+This option is only supported for C and Objective\-C. It is implied by
+\&\fB\-Wall\fR and by \fB\-pedantic\fR, which can be disabled with
+\&\fB\-Wno\-pointer\-sign\fR.
.IP "\fB\-Werror\fR" 4
.IX Item "-Werror"
Make all warnings into errors.
+.IP "\fB\-Werror=\fR" 4
+.IX Item "-Werror="
+Make the specified warning into an errors. The specifier for a
+warning is appended, for example \fB\-Werror=switch\fR turns the
+warnings controlled by \fB\-Wswitch\fR into errors. This switch
+takes a negative form, to be used to negate \fB\-Werror\fR for
+specific warnings, for example \fB\-Wno\-error=switch\fR makes
+\&\fB\-Wswitch\fR warnings not be errors, even when \fB\-Werror\fR
+is in effect. You can use the \fB\-fdiagnostics\-show\-option\fR
+option to have each controllable warning amended with the option which
+controls it, to determine what to use with this option.
+.Sp
+Note that specifying \fB\-Werror=\fR\fIfoo\fR automatically implies
+\&\fB\-W\fR\fIfoo\fR. However, \fB\-Wno\-error=\fR\fIfoo\fR does not
+imply anything.
+.IP "\fB\-Wstack\-protector\fR" 4
+.IX Item "-Wstack-protector"
+This option is only active when \fB\-fstack\-protector\fR is active. It
+warns about functions that will not be protected against stack smashing.
+.IP "\fB\-Woverlength\-strings\fR" 4
+.IX Item "-Woverlength-strings"
+Warn about string constants which are longer than the \*(L"minimum
+maximum\*(R" length specified in the C standard. Modern compilers
+generally allow string constants which are much longer than the
+standard's minimum limit, but very portable programs should avoid
+using longer strings.
+.Sp
+The limit applies \fIafter\fR string constant concatenation, and does
+not count the trailing \s-1NUL\s0. In C89, the limit was 509 characters; in
+C99, it was raised to 4095. \*(C+98 does not specify a normative
+minimum maximum, so we do not diagnose overlength strings in \*(C+.
+.Sp
+This option is implied by \fB\-pedantic\fR, and can be disabled with
+\&\fB\-Wno\-overlength\-strings\fR.
.Sh "Options for Debugging Your Program or \s-1GCC\s0"
.IX Subsection "Options for Debugging Your Program or GCC"
\&\s-1GCC\s0 has various special options that are used for debugging
@@ -2703,7 +3271,7 @@ either your program or \s-1GCC:\s0
.IP "\fB\-g\fR" 4
.IX Item "-g"
Produce debugging information in the operating system's native format
-(stabs, \s-1COFF\s0, \s-1XCOFF\s0, or \s-1DWARF\s0). \s-1GDB\s0 can work with this debugging
+(stabs, \s-1COFF\s0, \s-1XCOFF\s0, or \s-1DWARF\s0 2). \s-1GDB\s0 can work with this debugging
information.
.Sp
On most systems that use stabs format, \fB\-g\fR enables use of extra
@@ -2714,7 +3282,7 @@ refuse to read the program. If you want to control for certain whether
to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR,
\&\fB\-gxcoff+\fR, \fB\-gxcoff\fR, or \fB\-gvms\fR (see below).
.Sp
-Unlike most other C compilers, \s-1GCC\s0 allows you to use \fB\-g\fR with
+\&\s-1GCC\s0 allows you to use \fB\-g\fR with
\&\fB\-O\fR. The shortcuts taken by optimized code may occasionally
produce surprising results: some variables you declared may not exist
at all; flow of control may briefly move where you did not expect it;
@@ -2744,6 +3312,14 @@ On System V Release 4 systems this option requires the \s-1GNU\s0 assembler.
.IX Item "-feliminate-unused-debug-symbols"
Produce debugging information in stabs format (if that is supported),
for only symbols that are actually used.
+.IP "\fB\-femit\-class\-debug\-always\fR" 4
+.IX Item "-femit-class-debug-always"
+Instead of emitting debugging information for a \*(C+ class in only one
+object file, emit it in all object files using the class. This option
+should be used only with debuggers that are unable to handle the way \s-1GCC\s0
+normally emits debugging information for classes because using this
+option will increase the size of debugging information by as much as a
+factor of two.
.IP "\fB\-gstabs+\fR" 4
.IX Item "-gstabs+"
Produce debugging information in stabs format (if that is supported),
@@ -2769,7 +3345,10 @@ assembler (\s-1GAS\s0) to fail with an error.
.IP "\fB\-gdwarf\-2\fR" 4
.IX Item "-gdwarf-2"
Produce debugging information in \s-1DWARF\s0 version 2 format (if that is
-supported). This is the format used by \s-1DBX\s0 on \s-1IRIX\s0 6.
+supported). This is the format used by \s-1DBX\s0 on \s-1IRIX\s0 6. With this
+option, \s-1GCC\s0 uses features of \s-1DWARF\s0 version 3 when they are useful;
+version 3 is upward compatible with version 2, but may still cause
+problems for older debuggers.
.IP "\fB\-gvms\fR" 4
.IX Item "-gvms"
Produce debugging information in \s-1VMS\s0 debug format (if that is
@@ -2800,10 +3379,13 @@ Level 3 includes extra information, such as all the macro definitions
present in the program. Some debuggers support macro expansion when
you use \fB\-g3\fR.
.Sp
-Note that in order to avoid confusion between \s-1DWARF1\s0 debug level 2,
-and \s-1DWARF2\s0 \fB\-gdwarf\-2\fR does not accept a concatenated debug
-level. Instead use an additional \fB\-g\fR\fIlevel\fR option to
-change the debug level for \s-1DWARF2\s0.
+\&\fB\-gdwarf\-2\fR does not accept a concatenated debug level, because
+\&\s-1GCC\s0 used to support an option \fB\-gdwarf\fR that meant to generate
+debug information in version 1 of the \s-1DWARF\s0 format (which is very
+different from version 2), and it would have been too confusing. That
+debug format is long obsolete, but the option cannot be changed now.
+Instead use an additional \fB\-g\fR\fIlevel\fR option to change the
+debug level for \s-1DWARF2\s0.
.IP "\fB\-feliminate\-dwarf2\-dups\fR" 4
.IX Item "-feliminate-dwarf2-dups"
Compress \s-1DWARF2\s0 debugging information by eliminating duplicated
@@ -2839,42 +3421,43 @@ Add code so that program flow \fIarcs\fR are instrumented. During
execution the program records how many times each branch and call is
executed and how many times it is taken or returns. When the compiled
program exits it saves this data to a file called
-\&\fI\fIauxname\fI.gcda\fR for each source file. The data may be used for
+\&\fI\fIauxname\fI.gcda\fR for each source file. The data may be used for
profile-directed optimizations (\fB\-fbranch\-probabilities\fR), or for
-test coverage analysis (\fB\-ftest\-coverage\fR). Each object file's
+test coverage analysis (\fB\-ftest\-coverage\fR). Each object file's
\&\fIauxname\fR is generated from the name of the output file, if
explicitly specified and it is not the final executable, otherwise it is
-the basename of the source file. In both cases any suffix is removed
-(e.g. \fIfoo.gcda\fR for input file \fIdir/foo.c\fR, or
+the basename of the source file. In both cases any suffix is removed
+(e.g. \fIfoo.gcda\fR for input file \fIdir/foo.c\fR, or
\&\fIdir/foo.gcda\fR for output file specified as \fB\-o dir/foo.o\fR).
+.IP "\fB\-\-coverage\fR" 4
+.IX Item "--coverage"
+This option is used to compile and link code instrumented for coverage
+analysis. The option is a synonym for \fB\-fprofile\-arcs\fR
+\&\fB\-ftest\-coverage\fR (when compiling) and \fB\-lgcov\fR (when
+linking). See the documentation for those options for more details.
.RS 4
-.IP "@bullet" 4
-.IX Item "@bullet"
+.IP "*" 4
Compile the source files with \fB\-fprofile\-arcs\fR plus optimization
-and code generation options. For test coverage analysis, use the
-additional \fB\-ftest\-coverage\fR option. You do not need to profile
+and code generation options. For test coverage analysis, use the
+additional \fB\-ftest\-coverage\fR option. You do not need to profile
every source file in a program.
-.IP "@cvmmfu" 4
-.IX Item "@cvmmfu"
+.IP "*" 4
Link your object files with \fB\-lgcov\fR or \fB\-fprofile\-arcs\fR
(the latter implies the former).
-.IP "@dwnngv" 4
-.IX Item "@dwnngv"
+.IP "*" 4
Run the program on a representative workload to generate the arc profile
-information. This may be repeated any number of times. You can run
+information. This may be repeated any number of times. You can run
concurrent instances of your program, and provided that the file system
-supports locking, the data files will be correctly updated. Also
+supports locking, the data files will be correctly updated. Also
\&\f(CW\*(C`fork\*(C'\fR calls are detected and correctly handled (double counting
will not happen).
-.IP "@exoohw" 4
-.IX Item "@exoohw"
+.IP "*" 4
For profile-directed optimizations, compile the source files again with
the same optimization and code generation options plus
\&\fB\-fbranch\-probabilities\fR.
-.IP "@fyppix" 4
-.IX Item "@fyppix"
+.IP "*" 4
For test coverage analysis, use \fBgcov\fR to produce human readable
-information from the \fI.gcno\fR and \fI.gcda\fR files. Refer to the
+information from the \fI.gcno\fR and \fI.gcda\fR files. Refer to the
\&\fBgcov\fR documentation for further information.
.RE
.RS 4
@@ -2890,180 +3473,325 @@ block must be created to hold the instrumentation code.
.IP "\fB\-ftest\-coverage\fR" 4
.IX Item "-ftest-coverage"
Produce a notes file that the \fBgcov\fR code-coverage utility can use to
-show program coverage. Each source file's note file is called
-\&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile\-arcs\fR option
+show program coverage. Each source file's note file is called
+\&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile\-arcs\fR option
above for a description of \fIauxname\fR and instructions on how to
-generate test coverage data. Coverage data will match the source files
+generate test coverage data. Coverage data will match the source files
more closely, if you do not optimize.
.IP "\fB\-d\fR\fIletters\fR" 4
.IX Item "-dletters"
+.PD 0
+.IP "\fB\-fdump\-rtl\-\fR\fIpass\fR" 4
+.IX Item "-fdump-rtl-pass"
+.PD
Says to make debugging dumps during compilation at times specified by
-\&\fIletters\fR. This is used for debugging the compiler. The file names
-for most of the dumps are made by appending a pass number and a word to
-the \fIdumpname\fR. \fIdumpname\fR is generated from the name of the
-output file, if explicitly specified and it is not an executable,
-otherwise it is the basename of the source file. In both cases any
-suffix is removed (e.g. \fIfoo.01.rtl\fR or \fIfoo.02.sibling\fR).
-Here are the possible letters for use in \fIletters\fR, and their
-meanings:
+\&\fIletters\fR. This is used for debugging the RTL-based passes of the
+compiler. The file names for most of the dumps are made by appending a
+pass number and a word to the \fIdumpname\fR. \fIdumpname\fR is generated
+from the name of the output file, if explicitly specified and it is not
+an executable, otherwise it is the basename of the source file.
+.Sp
+Most debug dumps can be enabled either passing a letter to the \fB\-d\fR
+option, or with a long \fB\-fdump\-rtl\fR switch; here are the possible
+letters for use in \fIletters\fR and \fIpass\fR, and their meanings:
.RS 4
-.IP "\fBA\fR" 4
-.IX Item "A"
+.IP "\fB\-dA\fR" 4
+.IX Item "-dA"
Annotate the assembler output with miscellaneous debugging information.
-.IP "\fBb\fR" 4
-.IX Item "b"
-Dump after computing branch probabilities, to \fI\fIfile\fI.12.bp\fR.
-.IP "\fBB\fR" 4
-.IX Item "B"
-Dump after block reordering, to \fI\fIfile\fI.31.bbro\fR.
-.IP "\fBc\fR" 4
-.IX Item "c"
-Dump after instruction combination, to the file \fI\fIfile\fI.20.combine\fR.
-.IP "\fBC\fR" 4
-.IX Item "C"
-Dump after the first if conversion, to the file \fI\fIfile\fI.14.ce1\fR.
-Also dump after the second if conversion, to the file \fI\fIfile\fI.21.ce2\fR.
-.IP "\fBd\fR" 4
-.IX Item "d"
-Dump after branch target load optimization, to to \fI\fIfile\fI.32.btl\fR.
-Also dump after delayed branch scheduling, to \fI\fIfile\fI.36.dbr\fR.
-.IP "\fBD\fR" 4
-.IX Item "D"
+.IP "\fB\-dB\fR" 4
+.IX Item "-dB"
+.PD 0
+.IP "\fB\-fdump\-rtl\-bbro\fR" 4
+.IX Item "-fdump-rtl-bbro"
+.PD
+Dump after block reordering, to \fI\fIfile\fI.148r.bbro\fR.
+.IP "\fB\-dc\fR" 4
+.IX Item "-dc"
+.PD 0
+.IP "\fB\-fdump\-rtl\-combine\fR" 4
+.IX Item "-fdump-rtl-combine"
+.PD
+Dump after instruction combination, to the file \fI\fIfile\fI.129r.combine\fR.
+.IP "\fB\-dC\fR" 4
+.IX Item "-dC"
+.PD 0
+.IP "\fB\-fdump\-rtl\-ce1\fR" 4
+.IX Item "-fdump-rtl-ce1"
+.IP "\fB\-fdump\-rtl\-ce2\fR" 4
+.IX Item "-fdump-rtl-ce2"
+.PD
+\&\fB\-dC\fR and \fB\-fdump\-rtl\-ce1\fR enable dumping after the
+first if conversion, to the file \fI\fIfile\fI.117r.ce1\fR. \fB\-dC\fR
+and \fB\-fdump\-rtl\-ce2\fR enable dumping after the second if
+conversion, to the file \fI\fIfile\fI.130r.ce2\fR.
+.IP "\fB\-dd\fR" 4
+.IX Item "-dd"
+.PD 0
+.IP "\fB\-fdump\-rtl\-btl\fR" 4
+.IX Item "-fdump-rtl-btl"
+.IP "\fB\-fdump\-rtl\-dbr\fR" 4
+.IX Item "-fdump-rtl-dbr"
+.PD
+\&\fB\-dd\fR and \fB\-fdump\-rtl\-btl\fR enable dumping after branch
+target load optimization, to \fI\fIfile\fI.31.btl\fR. \fB\-dd\fR
+and \fB\-fdump\-rtl\-dbr\fR enable dumping after delayed branch
+scheduling, to \fI\fIfile\fI.36.dbr\fR.
+.IP "\fB\-dD\fR" 4
+.IX Item "-dD"
Dump all macro definitions, at the end of preprocessing, in addition to
normal output.
-.IP "\fBE\fR" 4
-.IX Item "E"
-Dump after the third if conversion, to \fI\fIfile\fI.30.ce3\fR.
-.IP "\fBf\fR" 4
-.IX Item "f"
-Dump after control and data flow analysis, to \fI\fIfile\fI.11.cfg\fR.
-Also dump after life analysis, to \fI\fIfile\fI.19.life\fR.
-.IP "\fBF\fR" 4
-.IX Item "F"
-Dump after purging \f(CW\*(C`ADDRESSOF\*(C'\fR codes, to \fI\fIfile\fI.07.addressof\fR.
-.IP "\fBg\fR" 4
-.IX Item "g"
-Dump after global register allocation, to \fI\fIfile\fI.25.greg\fR.
-.IP "\fBG\fR" 4
-.IX Item "G"
-Dump after \s-1GCSE\s0, to \fI\fIfile\fI.08.gcse\fR.
-Also dump after jump bypassing and control flow optimizations, to
-\&\fI\fIfile\fI.10.bypass\fR.
-.IP "\fBh\fR" 4
-.IX Item "h"
-Dump after finalization of \s-1EH\s0 handling code, to \fI\fIfile\fI.03.eh\fR.
-.IP "\fBi\fR" 4
-.IX Item "i"
-Dump after sibling call optimizations, to \fI\fIfile\fI.02.sibling\fR.
-.IP "\fBj\fR" 4
-.IX Item "j"
-Dump after the first jump optimization, to \fI\fIfile\fI.04.jump\fR.
-.IP "\fBk\fR" 4
-.IX Item "k"
-Dump after conversion from registers to stack, to \fI\fIfile\fI.34.stack\fR.
-.IP "\fBl\fR" 4
-.IX Item "l"
-Dump after local register allocation, to \fI\fIfile\fI.24.lreg\fR.
-.IP "\fBL\fR" 4
-.IX Item "L"
-Dump after loop optimization passes, to \fI\fIfile\fI.09.loop\fR and
-\&\fI\fIfile\fI.16.loop2\fR.
-.IP "\fBM\fR" 4
-.IX Item "M"
+.IP "\fB\-dE\fR" 4
+.IX Item "-dE"
+.PD 0
+.IP "\fB\-fdump\-rtl\-ce3\fR" 4
+.IX Item "-fdump-rtl-ce3"
+.PD
+Dump after the third if conversion, to \fI\fIfile\fI.146r.ce3\fR.
+.IP "\fB\-df\fR" 4
+.IX Item "-df"
+.PD 0
+.IP "\fB\-fdump\-rtl\-cfg\fR" 4
+.IX Item "-fdump-rtl-cfg"
+.IP "\fB\-fdump\-rtl\-life\fR" 4
+.IX Item "-fdump-rtl-life"
+.PD
+\&\fB\-df\fR and \fB\-fdump\-rtl\-cfg\fR enable dumping after control
+and data flow analysis, to \fI\fIfile\fI.116r.cfg\fR. \fB\-df\fR
+and \fB\-fdump\-rtl\-cfg\fR enable dumping dump after life analysis,
+to \fI\fIfile\fI.128r.life1\fR and \fI\fIfile\fI.135r.life2\fR.
+.IP "\fB\-dg\fR" 4
+.IX Item "-dg"
+.PD 0
+.IP "\fB\-fdump\-rtl\-greg\fR" 4
+.IX Item "-fdump-rtl-greg"
+.PD
+Dump after global register allocation, to \fI\fIfile\fI.139r.greg\fR.
+.IP "\fB\-dG\fR" 4
+.IX Item "-dG"
+.PD 0
+.IP "\fB\-fdump\-rtl\-gcse\fR" 4
+.IX Item "-fdump-rtl-gcse"
+.IP "\fB\-fdump\-rtl\-bypass\fR" 4
+.IX Item "-fdump-rtl-bypass"
+.PD
+\&\fB\-dG\fR and \fB\-fdump\-rtl\-gcse\fR enable dumping after \s-1GCSE\s0, to
+\&\fI\fIfile\fI.114r.gcse\fR. \fB\-dG\fR and \fB\-fdump\-rtl\-bypass\fR
+enable dumping after jump bypassing and control flow optimizations, to
+\&\fI\fIfile\fI.115r.bypass\fR.
+.IP "\fB\-dh\fR" 4
+.IX Item "-dh"
+.PD 0
+.IP "\fB\-fdump\-rtl\-eh\fR" 4
+.IX Item "-fdump-rtl-eh"
+.PD
+Dump after finalization of \s-1EH\s0 handling code, to \fI\fIfile\fI.02.eh\fR.
+.IP "\fB\-di\fR" 4
+.IX Item "-di"
+.PD 0
+.IP "\fB\-fdump\-rtl\-sibling\fR" 4
+.IX Item "-fdump-rtl-sibling"
+.PD
+Dump after sibling call optimizations, to \fI\fIfile\fI.106r.sibling\fR.
+.IP "\fB\-dj\fR" 4
+.IX Item "-dj"
+.PD 0
+.IP "\fB\-fdump\-rtl\-jump\fR" 4
+.IX Item "-fdump-rtl-jump"
+.PD
+Dump after the first jump optimization, to \fI\fIfile\fI.112r.jump\fR.
+.IP "\fB\-dk\fR" 4
+.IX Item "-dk"
+.PD 0
+.IP "\fB\-fdump\-rtl\-stack\fR" 4
+.IX Item "-fdump-rtl-stack"
+.PD
+Dump after conversion from registers to stack, to \fI\fIfile\fI.152r.stack\fR.
+.IP "\fB\-dl\fR" 4
+.IX Item "-dl"
+.PD 0
+.IP "\fB\-fdump\-rtl\-lreg\fR" 4
+.IX Item "-fdump-rtl-lreg"
+.PD
+Dump after local register allocation, to \fI\fIfile\fI.138r.lreg\fR.
+.IP "\fB\-dL\fR" 4
+.IX Item "-dL"
+.PD 0
+.IP "\fB\-fdump\-rtl\-loop2\fR" 4
+.IX Item "-fdump-rtl-loop2"
+.PD
+\&\fB\-dL\fR and \fB\-fdump\-rtl\-loop2\fR enable dumping after the
+loop optimization pass, to \fI\fIfile\fI.119r.loop2\fR,
+\&\fI\fIfile\fI.120r.loop2_init\fR,
+\&\fI\fIfile\fI.121r.loop2_invariant\fR, and
+\&\fI\fIfile\fI.125r.loop2_done\fR.
+.IP "\fB\-dm\fR" 4
+.IX Item "-dm"
+.PD 0
+.IP "\fB\-fdump\-rtl\-sms\fR" 4
+.IX Item "-fdump-rtl-sms"
+.PD
+Dump after modulo scheduling, to \fI\fIfile\fI.136r.sms\fR.
+.IP "\fB\-dM\fR" 4
+.IX Item "-dM"
+.PD 0
+.IP "\fB\-fdump\-rtl\-mach\fR" 4
+.IX Item "-fdump-rtl-mach"
+.PD
Dump after performing the machine dependent reorganization pass, to
-\&\fI\fIfile\fI.35.mach\fR.
-.IP "\fBn\fR" 4
-.IX Item "n"
-Dump after register renumbering, to \fI\fIfile\fI.29.rnreg\fR.
-.IP "\fBN\fR" 4
-.IX Item "N"
-Dump after the register move pass, to \fI\fIfile\fI.22.regmove\fR.
-.IP "\fBo\fR" 4
-.IX Item "o"
-Dump after post-reload optimizations, to \fI\fIfile\fI.26.postreload\fR.
-.IP "\fBr\fR" 4
-.IX Item "r"
-Dump after \s-1RTL\s0 generation, to \fI\fIfile\fI.01.rtl\fR.
-.IP "\fBR\fR" 4
-.IX Item "R"
-Dump after the second scheduling pass, to \fI\fIfile\fI.33.sched2\fR.
-.IP "\fBs\fR" 4
-.IX Item "s"
+\&\fI\fIfile\fI.155r.mach\fR.
+.IP "\fB\-dn\fR" 4
+.IX Item "-dn"
+.PD 0
+.IP "\fB\-fdump\-rtl\-rnreg\fR" 4
+.IX Item "-fdump-rtl-rnreg"
+.PD
+Dump after register renumbering, to \fI\fIfile\fI.147r.rnreg\fR.
+.IP "\fB\-dN\fR" 4
+.IX Item "-dN"
+.PD 0
+.IP "\fB\-fdump\-rtl\-regmove\fR" 4
+.IX Item "-fdump-rtl-regmove"
+.PD
+Dump after the register move pass, to \fI\fIfile\fI.132r.regmove\fR.
+.IP "\fB\-do\fR" 4
+.IX Item "-do"
+.PD 0
+.IP "\fB\-fdump\-rtl\-postreload\fR" 4
+.IX Item "-fdump-rtl-postreload"
+.PD
+Dump after post-reload optimizations, to \fI\fIfile\fI.24.postreload\fR.
+.IP "\fB\-dr\fR" 4
+.IX Item "-dr"
+.PD 0
+.IP "\fB\-fdump\-rtl\-expand\fR" 4
+.IX Item "-fdump-rtl-expand"
+.PD
+Dump after \s-1RTL\s0 generation, to \fI\fIfile\fI.104r.expand\fR.
+.IP "\fB\-dR\fR" 4
+.IX Item "-dR"
+.PD 0
+.IP "\fB\-fdump\-rtl\-sched2\fR" 4
+.IX Item "-fdump-rtl-sched2"
+.PD
+Dump after the second scheduling pass, to \fI\fIfile\fI.150r.sched2\fR.
+.IP "\fB\-ds\fR" 4
+.IX Item "-ds"
+.PD 0
+.IP "\fB\-fdump\-rtl\-cse\fR" 4
+.IX Item "-fdump-rtl-cse"
+.PD
Dump after \s-1CSE\s0 (including the jump optimization that sometimes follows
-\&\s-1CSE\s0), to \fI\fIfile\fI.06.cse\fR.
-.IP "\fBS\fR" 4
-.IX Item "S"
-Dump after the first scheduling pass, to \fI\fIfile\fI.23.sched\fR.
-.IP "\fBt\fR" 4
-.IX Item "t"
+\&\s-1CSE\s0), to \fI\fIfile\fI.113r.cse\fR.
+.IP "\fB\-dS\fR" 4
+.IX Item "-dS"
+.PD 0
+.IP "\fB\-fdump\-rtl\-sched\fR" 4
+.IX Item "-fdump-rtl-sched"
+.PD
+Dump after the first scheduling pass, to \fI\fIfile\fI.21.sched\fR.
+.IP "\fB\-dt\fR" 4
+.IX Item "-dt"
+.PD 0
+.IP "\fB\-fdump\-rtl\-cse2\fR" 4
+.IX Item "-fdump-rtl-cse2"
+.PD
Dump after the second \s-1CSE\s0 pass (including the jump optimization that
-sometimes follows \s-1CSE\s0), to \fI\fIfile\fI.18.cse2\fR.
-.IP "\fBT\fR" 4
-.IX Item "T"
-Dump after running tracer, to \fI\fIfile\fI.15.tracer\fR.
-.IP "\fBu\fR" 4
-.IX Item "u"
-Dump after null pointer elimination pass to \fI\fIfile\fI.05.null\fR.
-.IP "\fBU\fR" 4
-.IX Item "U"
-Dump callgraph and unit-at-a-time optimization \fI\fIfile\fI.00.unit\fR.
-.IP "\fBV\fR" 4
-.IX Item "V"
-Dump after the value profile transformations, to \fI\fIfile\fI.13.vpt\fR.
-.IP "\fBw\fR" 4
-.IX Item "w"
-Dump after the second flow pass, to \fI\fIfile\fI.27.flow2\fR.
-.IP "\fBz\fR" 4
-.IX Item "z"
-Dump after the peephole pass, to \fI\fIfile\fI.28.peephole2\fR.
-.IP "\fBZ\fR" 4
-.IX Item "Z"
-Dump after constructing the web, to \fI\fIfile\fI.17.web\fR.
-.IP "\fBa\fR" 4
-.IX Item "a"
+sometimes follows \s-1CSE\s0), to \fI\fIfile\fI.127r.cse2\fR.
+.IP "\fB\-dT\fR" 4
+.IX Item "-dT"
+.PD 0
+.IP "\fB\-fdump\-rtl\-tracer\fR" 4
+.IX Item "-fdump-rtl-tracer"
+.PD
+Dump after running tracer, to \fI\fIfile\fI.118r.tracer\fR.
+.IP "\fB\-dV\fR" 4
+.IX Item "-dV"
+.PD 0
+.IP "\fB\-fdump\-rtl\-vpt\fR" 4
+.IX Item "-fdump-rtl-vpt"
+.IP "\fB\-fdump\-rtl\-vartrack\fR" 4
+.IX Item "-fdump-rtl-vartrack"
+.PD
+\&\fB\-dV\fR and \fB\-fdump\-rtl\-vpt\fR enable dumping after the value
+profile transformations, to \fI\fIfile\fI.10.vpt\fR. \fB\-dV\fR
+and \fB\-fdump\-rtl\-vartrack\fR enable dumping after variable tracking,
+to \fI\fIfile\fI.154r.vartrack\fR.
+.IP "\fB\-dw\fR" 4
+.IX Item "-dw"
+.PD 0
+.IP "\fB\-fdump\-rtl\-flow2\fR" 4
+.IX Item "-fdump-rtl-flow2"
+.PD
+Dump after the second flow pass, to \fI\fIfile\fI.142r.flow2\fR.
+.IP "\fB\-dz\fR" 4
+.IX Item "-dz"
+.PD 0
+.IP "\fB\-fdump\-rtl\-peephole2\fR" 4
+.IX Item "-fdump-rtl-peephole2"
+.PD
+Dump after the peephole pass, to \fI\fIfile\fI.145r.peephole2\fR.
+.IP "\fB\-dZ\fR" 4
+.IX Item "-dZ"
+.PD 0
+.IP "\fB\-fdump\-rtl\-web\fR" 4
+.IX Item "-fdump-rtl-web"
+.PD
+Dump after live range splitting, to \fI\fIfile\fI.126r.web\fR.
+.IP "\fB\-da\fR" 4
+.IX Item "-da"
+.PD 0
+.IP "\fB\-fdump\-rtl\-all\fR" 4
+.IX Item "-fdump-rtl-all"
+.PD
Produce all the dumps listed above.
-.IP "\fBH\fR" 4
-.IX Item "H"
+.IP "\fB\-dH\fR" 4
+.IX Item "-dH"
Produce a core dump whenever an error occurs.
-.IP "\fBm\fR" 4
-.IX Item "m"
+.IP "\fB\-dm\fR" 4
+.IX Item "-dm"
Print statistics on memory usage, at the end of the run, to
standard error.
-.IP "\fBp\fR" 4
-.IX Item "p"
+.IP "\fB\-dp\fR" 4
+.IX Item "-dp"
Annotate the assembler output with a comment indicating which
pattern and alternative was used. The length of each instruction is
also printed.
-.IP "\fBP\fR" 4
-.IX Item "P"
+.IP "\fB\-dP\fR" 4
+.IX Item "-dP"
Dump the \s-1RTL\s0 in the assembler output as a comment before each instruction.
Also turns on \fB\-dp\fR annotation.
-.IP "\fBv\fR" 4
-.IX Item "v"
-For each of the other indicated dump files (except for
-\&\fI\fIfile\fI.01.rtl\fR), dump a representation of the control flow graph
-suitable for viewing with \s-1VCG\s0 to \fI\fIfile\fI.\fIpass\fI.vcg\fR.
-.IP "\fBx\fR" 4
-.IX Item "x"
+.IP "\fB\-dv\fR" 4
+.IX Item "-dv"
+For each of the other indicated dump files (either with \fB\-d\fR or
+\&\fB\-fdump\-rtl\-\fR\fIpass\fR), dump a representation of the control flow
+graph suitable for viewing with \s-1VCG\s0 to \fI\fIfile\fI.\fIpass\fI.vcg\fR.
+.IP "\fB\-dx\fR" 4
+.IX Item "-dx"
Just generate \s-1RTL\s0 for a function instead of compiling it. Usually used
-with \fBr\fR.
-.IP "\fBy\fR" 4
-.IX Item "y"
+with \fBr\fR (\fB\-fdump\-rtl\-expand\fR).
+.IP "\fB\-dy\fR" 4
+.IX Item "-dy"
Dump debugging information during parsing, to standard error.
.RE
.RS 4
.RE
+.IP "\fB\-fdump\-noaddr\fR" 4
+.IX Item "-fdump-noaddr"
+When doing debugging dumps (see \fB\-d\fR option above), suppress
+address output. This makes it more feasible to use diff on debugging
+dumps for compiler invocations with different compiler binaries and/or
+different text / bss / data / heap / stack / dso start locations.
.IP "\fB\-fdump\-unnumbered\fR" 4
.IX Item "-fdump-unnumbered"
When doing debugging dumps (see \fB\-d\fR option above), suppress instruction
-numbers and line number note output. This makes it more feasible to
+numbers, line number note and address output. This makes it more feasible to
use diff on debugging dumps for compiler invocations with different
options, in particular with and without \fB\-g\fR.
-.IP "\fB\-fdump\-translation\-unit\fR (C and \*(C+ only)" 4
-.IX Item "-fdump-translation-unit (C and only)"
+.IP "\fB\-fdump\-translation\-unit\fR (\*(C+ only)" 4
+.IX Item "-fdump-translation-unit ( only)"
.PD 0
-.IP "\fB\-fdump\-translation\-unit\-\fR\fIoptions\fR\fB \fR(C and \*(C+ only)" 4
-.IX Item "-fdump-translation-unit-options (C and only)"
+.IP "\fB\-fdump\-translation\-unit\-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4
+.IX Item "-fdump-translation-unit-options ( only)"
.PD
Dump a representation of the tree structure for the entire translation
unit to a file. The file name is made by appending \fI.tu\fR to the
@@ -3081,33 +3809,74 @@ table layout to a file. The file name is made by appending \fI.class\fR
to the source file name. If the \fB\-\fR\fIoptions\fR form is used,
\&\fIoptions\fR controls the details of the dump as described for the
\&\fB\-fdump\-tree\fR options.
-.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB \fR(\*(C+ only)" 4
-.IX Item "-fdump-tree-switch ( only)"
+.IP "\fB\-fdump\-ipa\-\fR\fIswitch\fR" 4
+.IX Item "-fdump-ipa-switch"
+Control the dumping at various stages of inter-procedural analysis
+language tree to a file. The file name is generated by appending a switch
+specific suffix to the source file name. The following dumps are possible:
+.RS 4
+.IP "\fBall\fR" 4
+.IX Item "all"
+Enables all inter-procedural analysis dumps; currently the only produced
+dump is the \fBcgraph\fR dump.
+.IP "\fBcgraph\fR" 4
+.IX Item "cgraph"
+Dumps information about call-graph optimization, unused function removal,
+and inlining decisions.
+.RE
+.RS 4
+.RE
+.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR" 4
+.IX Item "-fdump-tree-switch"
.PD 0
-.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4
-.IX Item "-fdump-tree-switch-options ( only)"
+.IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4
+.IX Item "-fdump-tree-switch-options"
.PD
Control the dumping at various stages of processing the intermediate
language tree to a file. The file name is generated by appending a switch
specific suffix to the source file name. If the \fB\-\fR\fIoptions\fR
form is used, \fIoptions\fR is a list of \fB\-\fR separated options that
-control the details of the dump. Not all options are applicable to all
-dumps, those which are not meaningful will be ignored. The following
+control the details of the dump. Not all options are applicable to all
+dumps, those which are not meaningful will be ignored. The following
options are available
.RS 4
.IP "\fBaddress\fR" 4
.IX Item "address"
Print the address of each node. Usually this is not meaningful as it
-changes according to the environment and source file. Its primary use
+changes according to the environment and source file. Its primary use
is for tying up a dump file with a debug environment.
.IP "\fBslim\fR" 4
.IX Item "slim"
Inhibit dumping of members of a scope or body of a function merely
-because that scope has been reached. Only dump such items when they
-are directly reachable by some other path.
+because that scope has been reached. Only dump such items when they
+are directly reachable by some other path. When dumping pretty-printed
+trees, this option inhibits dumping the bodies of control structures.
+.IP "\fBraw\fR" 4
+.IX Item "raw"
+Print a raw representation of the tree. By default, trees are
+pretty-printed into a C\-like representation.
+.IP "\fBdetails\fR" 4
+.IX Item "details"
+Enable more detailed dumps (not honored by every dump option).
+.IP "\fBstats\fR" 4
+.IX Item "stats"
+Enable dumping various statistics about the pass (not honored by every dump
+option).
+.IP "\fBblocks\fR" 4
+.IX Item "blocks"
+Enable showing basic block boundaries (disabled in raw dumps).
+.IP "\fBvops\fR" 4
+.IX Item "vops"
+Enable showing virtual operands for every statement.
+.IP "\fBlineno\fR" 4
+.IX Item "lineno"
+Enable showing line numbers for statements.
+.IP "\fBuid\fR" 4
+.IX Item "uid"
+Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable.
.IP "\fBall\fR" 4
.IX Item "all"
-Turn on all options.
+Turn on all options, except \fBraw\fR, \fBslim\fR and \fBlineno\fR.
.RE
.RS 4
.Sp
@@ -3121,16 +3890,148 @@ Dump after all tree based optimization, to \fI\fIfile\fI.optimized\fR.
.IP "\fBinlined\fR" 4
.IX Item "inlined"
Dump after function inlining, to \fI\fIfile\fI.inlined\fR.
+.IP "\fBgimple\fR" 4
+.IX Item "gimple"
+Dump each function before and after the gimplification pass to a file. The
+file name is made by appending \fI.gimple\fR to the source file name.
+.IP "\fBcfg\fR" 4
+.IX Item "cfg"
+Dump the control flow graph of each function to a file. The file name is
+made by appending \fI.cfg\fR to the source file name.
+.IP "\fBvcg\fR" 4
+.IX Item "vcg"
+Dump the control flow graph of each function to a file in \s-1VCG\s0 format. The
+file name is made by appending \fI.vcg\fR to the source file name. Note
+that if the file contains more than one function, the generated file cannot
+be used directly by \s-1VCG\s0. You will need to cut and paste each function's
+graph into its own separate file first.
+.IP "\fBch\fR" 4
+.IX Item "ch"
+Dump each function after copying loop headers. The file name is made by
+appending \fI.ch\fR to the source file name.
+.IP "\fBssa\fR" 4
+.IX Item "ssa"
+Dump \s-1SSA\s0 related information to a file. The file name is made by appending
+\&\fI.ssa\fR to the source file name.
+.IP "\fBsalias\fR" 4
+.IX Item "salias"
+Dump structure aliasing variable information to a file. This file name
+is made by appending \fI.salias\fR to the source file name.
+.IP "\fBalias\fR" 4
+.IX Item "alias"
+Dump aliasing information for each function. The file name is made by
+appending \fI.alias\fR to the source file name.
+.IP "\fBccp\fR" 4
+.IX Item "ccp"
+Dump each function after \s-1CCP\s0. The file name is made by appending
+\&\fI.ccp\fR to the source file name.
+.IP "\fBstoreccp\fR" 4
+.IX Item "storeccp"
+Dump each function after \s-1STORE\-CCP\s0. The file name is made by appending
+\&\fI.storeccp\fR to the source file name.
+.IP "\fBpre\fR" 4
+.IX Item "pre"
+Dump trees after partial redundancy elimination. The file name is made
+by appending \fI.pre\fR to the source file name.
+.IP "\fBfre\fR" 4
+.IX Item "fre"
+Dump trees after full redundancy elimination. The file name is made
+by appending \fI.fre\fR to the source file name.
+.IP "\fBcopyprop\fR" 4
+.IX Item "copyprop"
+Dump trees after copy propagation. The file name is made
+by appending \fI.copyprop\fR to the source file name.
+.IP "\fBstore_copyprop\fR" 4
+.IX Item "store_copyprop"
+Dump trees after store copy\-propagation. The file name is made
+by appending \fI.store_copyprop\fR to the source file name.
+.IP "\fBdce\fR" 4
+.IX Item "dce"
+Dump each function after dead code elimination. The file name is made by
+appending \fI.dce\fR to the source file name.
+.IP "\fBmudflap\fR" 4
+.IX Item "mudflap"
+Dump each function after adding mudflap instrumentation. The file name is
+made by appending \fI.mudflap\fR to the source file name.
+.IP "\fBsra\fR" 4
+.IX Item "sra"
+Dump each function after performing scalar replacement of aggregates. The
+file name is made by appending \fI.sra\fR to the source file name.
+.IP "\fBsink\fR" 4
+.IX Item "sink"
+Dump each function after performing code sinking. The file name is made
+by appending \fI.sink\fR to the source file name.
+.IP "\fBdom\fR" 4
+.IX Item "dom"
+Dump each function after applying dominator tree optimizations. The file
+name is made by appending \fI.dom\fR to the source file name.
+.IP "\fBdse\fR" 4
+.IX Item "dse"
+Dump each function after applying dead store elimination. The file
+name is made by appending \fI.dse\fR to the source file name.
+.IP "\fBphiopt\fR" 4
+.IX Item "phiopt"
+Dump each function after optimizing \s-1PHI\s0 nodes into straightline code. The file
+name is made by appending \fI.phiopt\fR to the source file name.
+.IP "\fBforwprop\fR" 4
+.IX Item "forwprop"
+Dump each function after forward propagating single use variables. The file
+name is made by appending \fI.forwprop\fR to the source file name.
+.IP "\fBcopyrename\fR" 4
+.IX Item "copyrename"
+Dump each function after applying the copy rename optimization. The file
+name is made by appending \fI.copyrename\fR to the source file name.
+.IP "\fBnrv\fR" 4
+.IX Item "nrv"
+Dump each function after applying the named return value optimization on
+generic trees. The file name is made by appending \fI.nrv\fR to the source
+file name.
+.IP "\fBvect\fR" 4
+.IX Item "vect"
+Dump each function after applying vectorization of loops. The file name is
+made by appending \fI.vect\fR to the source file name.
+.IP "\fBvrp\fR" 4
+.IX Item "vrp"
+Dump each function after Value Range Propagation (\s-1VRP\s0). The file name
+is made by appending \fI.vrp\fR to the source file name.
+.IP "\fBall\fR" 4
+.IX Item "all"
+Enable all the available tree dumps with the flags provided in this option.
.RE
.RS 4
.RE
+.IP "\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR" 4
+.IX Item "-ftree-vectorizer-verbose=n"
+This option controls the amount of debugging output the vectorizer prints.
+This information is written to standard error, unless
+\&\fB\-fdump\-tree\-all\fR or \fB\-fdump\-tree\-vect\fR is specified,
+in which case it is output to the usual dump listing file, \fI.vect\fR.
+For \fIn\fR=0 no diagnostic information is reported.
+If \fIn\fR=1 the vectorizer reports each loop that got vectorized,
+and the total number of loops that got vectorized.
+If \fIn\fR=2 the vectorizer also reports non-vectorized loops that passed
+the first analysis phase (vect_analyze_loop_form) \- i.e. countable,
+inner\-most, single\-bb, single\-entry/exit loops. This is the same verbosity
+level that \fB\-fdump\-tree\-vect\-stats\fR uses.
+Higher verbosity levels mean either more information dumped for each
+reported loop, or same amount of information reported for more loops:
+If \fIn\fR=3, alignment related information is added to the reports.
+If \fIn\fR=4, data-references related information (e.g. memory dependences,
+memory access\-patterns) is added to the reports.
+If \fIn\fR=5, the vectorizer reports also non-vectorized inner-most loops
+that did not pass the first analysis phase (i.e. may not be countable, or
+may have complicated control\-flow).
+If \fIn\fR=6, the vectorizer reports also non-vectorized nested loops.
+For \fIn\fR=7, all the information the vectorizer generates during its
+analysis and transformation is reported. This is the same verbosity level
+that \fB\-fdump\-tree\-vect\-details\fR uses.
.IP "\fB\-frandom\-seed=\fR\fIstring\fR" 4
.IX Item "-frandom-seed=string"
This option provides a seed that \s-1GCC\s0 uses when it would otherwise use
random numbers. It is used to generate certain symbol names
-that have to be different in every compiled file. It is also used to
+that have to be different in every compiled file. It is also used to
place unique stamps in coverage data files and the object files that
-produce them. You can use the \fB\-frandom\-seed\fR option to produce
+produce them. You can use the \fB\-frandom\-seed\fR option to produce
reproducibly identical object files.
.Sp
The \fIstring\fR should be different for every file you compile.
@@ -3152,12 +4053,18 @@ at abort point, control-flow and regions info. And for \fIn\fR over
four, \fB\-fsched\-verbose\fR also includes dependence info.
.IP "\fB\-save\-temps\fR" 4
.IX Item "-save-temps"
-Store the usual ``temporary'' intermediate files permanently; place them
+Store the usual \*(L"temporary\*(R" intermediate files permanently; place them
in the current directory and name them based on the source file. Thus,
compiling \fIfoo.c\fR with \fB\-c \-save\-temps\fR would produce files
\&\fIfoo.i\fR and \fIfoo.s\fR, as well as \fIfoo.o\fR. This creates a
preprocessed \fIfoo.i\fR output file even though the compiler now
normally uses an integrated preprocessor.
+.Sp
+When used in combination with the \fB\-x\fR command line option,
+\&\fB\-save\-temps\fR is sensible enough to avoid over writing an
+input source file with the same extension as an intermediate file.
+The corresponding intermediate file may be obtained by renaming the
+source file before using \fB\-save\-temps\fR.
.IP "\fB\-time\fR" 4
.IX Item "-time"
Report the \s-1CPU\s0 time taken by each subprocess in the compilation
@@ -3169,10 +4076,19 @@ sequence. For C source files, this is the compiler proper and assembler
\& # as 0.00 0.01
.Ve
.Sp
-The first number on each line is the ``user time,'' that is time spent
-executing the program itself. The second number is ``system time,''
+The first number on each line is the \*(L"user time\*(R", that is time spent
+executing the program itself. The second number is \*(L"system time\*(R",
time spent executing operating system routines on behalf of the program.
Both numbers are in seconds.
+.IP "\fB\-fvar\-tracking\fR" 4
+.IX Item "-fvar-tracking"
+Run variable tracking pass. It computes where variables are stored at each
+position in code. Better debugging information is then generated
+(if the debugging information format supports this information).
+.Sp
+It is enabled by default when compiling with optimization (\fB\-Os\fR,
+\&\fB\-O\fR, \fB\-O2\fR, ...), debugging information (\fB\-g\fR) and
+the debug info format supports it.
.IP "\fB\-print\-file\-name=\fR\fIlibrary\fR" 4
.IX Item "-print-file-name=library"
Print the full absolute name of the library file \fIlibrary\fR that
@@ -3214,7 +4130,7 @@ This is useful when \fBgcc\fR prints the error message
To resolve this you either need to put \fIcpp0\fR and the other compiler
components where \fBgcc\fR expects to find them, or you can set the environment
variable \fB\s-1GCC_EXEC_PREFIX\s0\fR to the directory where you installed them.
-Don't forget the trailing '/'.
+Don't forget the trailing \fB/\fR.
.IP "\fB\-dumpmachine\fR" 4
.IX Item "-dumpmachine"
Print the compiler's target machine (for example,
@@ -3255,10 +4171,11 @@ the performance and/or code size at the expense of compilation time
and possibly the ability to debug the program.
.PP
The compiler performs optimization based on the knowledge it has of
-the program. Using the \fB\-funit\-at\-a\-time\fR flag will allow the
-compiler to consider information gained from later functions in the
-file when compiling a function. Compiling multiple files at once to a
-single output file (and using \fB\-funit\-at\-a\-time\fR) will allow
+the program. Optimization levels \fB\-O\fR and above, in
+particular, enable \fIunit-at-a-time\fR mode, which allows the
+compiler to consider information gained from later functions in
+the file when compiling a function. Compiling multiple files at
+once to a single output file in \fIunit-at-a-time\fR mode allows
the compiler to use information gained from all of the files when
compiling each of them.
.PP
@@ -3279,14 +4196,23 @@ compilation time.
.Sp
\&\fB\-O\fR turns on the following optimization flags:
\&\fB\-fdefer\-pop
-\&\-fmerge\-constants
-\&\-fthread\-jumps
-\&\-floop\-optimize
-\&\-fif\-conversion
-\&\-fif\-conversion2
\&\-fdelayed\-branch
\&\-fguess\-branch\-probability
-\&\-fcprop\-registers\fR
+\&\-fcprop\-registers
+\&\-fif\-conversion
+\&\-fif\-conversion2
+\&\-ftree\-ccp
+\&\-ftree\-dce
+\&\-ftree\-dominator\-opts
+\&\-ftree\-dse
+\&\-ftree\-ter
+\&\-ftree\-lrs
+\&\-ftree\-sra
+\&\-ftree\-copyrename
+\&\-ftree\-fre
+\&\-ftree\-ch
+\&\-funit\-at\-a\-time
+\&\-fmerge\-constants\fR
.Sp
\&\fB\-O\fR also turns on \fB\-fomit\-frame\-pointer\fR on machines
where doing so does not interfere with debugging.
@@ -3300,34 +4226,37 @@ and the performance of the generated code.
.Sp
\&\fB\-O2\fR turns on all optimization flags specified by \fB\-O\fR. It
also turns on the following optimization flags:
-\&\fB\-fforce\-mem
+\&\fB\-fthread\-jumps
+\&\-fcrossjumping
\&\-foptimize\-sibling\-calls
-\&\-fstrength\-reduce
\&\-fcse\-follow\-jumps \-fcse\-skip\-blocks
-\&\-frerun\-cse\-after\-loop \-frerun\-loop\-opt
-\&\-fgcse \-fgcse\-lm \-fgcse\-sm \-fgcse\-las
-\&\-fdelete\-null\-pointer\-checks
+\&\-fgcse \-fgcse\-lm
\&\-fexpensive\-optimizations
-\&\-fregmove
-\&\-fschedule\-insns \-fschedule\-insns2
-\&\-fsched\-interblock \-fsched\-spec
+\&\-frerun\-cse\-after\-loop
\&\-fcaller\-saves
\&\-fpeephole2
+\&\-fschedule\-insns \-fschedule\-insns2
+\&\-fsched\-interblock \-fsched\-spec
+\&\-fregmove
+\&\-fstrict\-aliasing \-fstrict\-overflow
+\&\-fdelete\-null\-pointer\-checks
\&\-freorder\-blocks \-freorder\-functions
-\&\-fstrict\-aliasing
-\&\-funit\-at\-a\-time
\&\-falign\-functions \-falign\-jumps
\&\-falign\-loops \-falign\-labels
-\&\-fcrossjumping\fR
+\&\-ftree\-vrp
+\&\-ftree\-pre\fR
.Sp
Please note the warning under \fB\-fgcse\fR about
invoking \fB\-O2\fR on programs that use computed gotos.
+.Sp
+\&\fB\-O2\fR doesn't turn on \fB\-ftree\-vrp\fR for the Ada compiler.
+This option must be explicitly specified on the command line to be
+enabled for the Ada compiler.
.IP "\fB\-O3\fR" 4
.IX Item "-O3"
Optimize yet more. \fB\-O3\fR turns on all optimizations specified by
\&\fB\-O2\fR and also turns on the \fB\-finline\-functions\fR,
-\&\fB\-fweb\fR, \fB\-frename\-registers\fR and \fB\-funswitch\-loops\fR
-options.
+\&\fB\-funswitch\-loops\fR and \fB\-fgcse\-after\-reload\fR options.
.IP "\fB\-O0\fR" 4
.IX Item "-O0"
Do not optimize. This is the default.
@@ -3339,7 +4268,8 @@ optimizations designed to reduce code size.
.Sp
\&\fB\-Os\fR disables the following optimization flags:
\&\fB\-falign\-functions \-falign\-jumps \-falign\-loops
-\&\-falign\-labels \-freorder\-blocks \-fprefetch\-loop\-arrays\fR
+\&\-falign\-labels \-freorder\-blocks \-freorder\-blocks\-and\-partition
+\&\-fprefetch\-loop\-arrays \-ftree\-vect\-loop\-version\fR
.Sp
If you use multiple \fB\-O\fR options, with or without level numbers,
the last such option is the one that is effective.
@@ -3353,7 +4283,7 @@ or adding it.
.PP
The following options control specific optimizations. They are either
activated by \fB\-O\fR options or are related to ones that are. You
-can use the following flags in the rare cases when ``fine\-tuning'' of
+can use the following flags in the rare cases when \*(L"fine\-tuning\*(R" of
optimizations to be performed is desired.
.IP "\fB\-fno\-default\-inline\fR" 4
.IX Item "-fno-default-inline"
@@ -3376,14 +4306,11 @@ Force memory operands to be copied into registers before doing
arithmetic on them. This produces better code by making all memory
references potential common subexpressions. When they are not common
subexpressions, instruction combination should eliminate the separate
-register\-load.
-.Sp
-Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
+register\-load. This option is now a nop and will be removed in 4.3.
.IP "\fB\-fforce\-addr\fR" 4
.IX Item "-fforce-addr"
Force memory address constants to be copied into registers before
-doing arithmetic on them. This may produce better code just as
-\&\fB\-fforce\-mem\fR may.
+doing arithmetic on them.
.IP "\fB\-fomit\-frame\-pointer\fR" 4
.IX Item "-fomit-frame-pointer"
Don't keep the frame pointer in a register for functions that
@@ -3420,6 +4347,23 @@ declared \f(CW\*(C`static\*(C'\fR, then the function is normally not output as
assembler code in its own right.
.Sp
Enabled at level \fB\-O3\fR.
+.IP "\fB\-finline\-functions\-called\-once\fR" 4
+.IX Item "-finline-functions-called-once"
+Consider all \f(CW\*(C`static\*(C'\fR functions called once for inlining into their
+caller even if they are not marked \f(CW\*(C`inline\*(C'\fR. If a call to a given
+function is integrated, then the function is not output as assembler code
+in its own right.
+.Sp
+Enabled if \fB\-funit\-at\-a\-time\fR is enabled.
+.IP "\fB\-fearly\-inlining\fR" 4
+.IX Item "-fearly-inlining"
+Inline functions marked by \f(CW\*(C`always_inline\*(C'\fR and functions whose body seems
+smaller than the function call overhead early before doing
+\&\fB\-fprofile\-generate\fR instrumentation and real inlining pass. Doing so
+makes profiling significantly cheaper and usually inlining faster on programs
+having large chains of nested wrapper functions.
+.Sp
+Enabled by default.
.IP "\fB\-finline\-limit=\fR\fIn\fR" 4
.IX Item "-finline-limit=n"
By default, \s-1GCC\s0 limits the size of functions that can be inlined. This flag
@@ -3439,16 +4383,25 @@ specified individually by using \fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR.
The \fB\-finline\-limit=\fR\fIn\fR option sets some of these parameters
as follows:
.RS 4
-.Sp
-.Vb 8
-\& @item max-inline-insns-single
-\& is set to I<n>/2.
-\& @item max-inline-insns-auto
-\& is set to I<n>/2.
-\& @item min-inline-insns
-\& is set to 130 or I<n>/4, whichever is smaller.
-\& @item max-inline-insns-rtl
-\& is set to I<n>.
+.IP "\fBmax-inline-insns-single\fR" 4
+.IX Item "max-inline-insns-single"
+.Vb 1
+\& is set to I<n>/2.
+.Ve
+.IP "\fBmax-inline-insns-auto\fR" 4
+.IX Item "max-inline-insns-auto"
+.Vb 1
+\& is set to I<n>/2.
+.Ve
+.IP "\fBmin-inline-insns\fR" 4
+.IX Item "min-inline-insns"
+.Vb 1
+\& is set to 130 or I<n>/4, whichever is smaller.
+.Ve
+.IP "\fBmax-inline-insns-rtl\fR" 4
+.IX Item "max-inline-insns-rtl"
+.Vb 1
+\& is set to I<n>.
.Ve
.RE
.RS 4
@@ -3457,16 +4410,17 @@ See below for a documentation of the individual
parameters controlling inlining.
.Sp
\&\fINote:\fR pseudo instruction represents, in this particular context, an
-abstract measurement of function's size. In no way, it represents a count
+abstract measurement of function's size. In no way does it represent a count
of assembly instructions and as such its exact meaning might change from one
release to an another.
.RE
.IP "\fB\-fkeep\-inline\-functions\fR" 4
.IX Item "-fkeep-inline-functions"
-Even if all calls to a given function are integrated, and the function
-is declared \f(CW\*(C`static\*(C'\fR, nevertheless output a separate run-time
-callable version of the function. This switch does not affect
-\&\f(CW\*(C`extern inline\*(C'\fR functions.
+In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR
+into the object file, even if the function has been inlined into all
+of its callers. This switch does not affect functions using the
+\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU\s0 C. In \*(C+, emit any and all
+inline functions into the object file.
.IP "\fB\-fkeep\-static\-consts\fR" 4
.IX Item "-fkeep-static-consts"
Emit variables declared \f(CW\*(C`static const\*(C'\fR when optimization isn't turned
@@ -3495,21 +4449,20 @@ arrays or initialized constant variables with integral or floating point
types. Languages like C or \*(C+ require each non-automatic variable to
have distinct location, so using this option will result in non-conforming
behavior.
-.IP "\fB\-fnew\-ra\fR" 4
-.IX Item "-fnew-ra"
-Use a graph coloring register allocator. Currently this option is meant
-only for testing. Users should not specify this option, since it is not
-yet ready for production use.
+.IP "\fB\-fmodulo\-sched\fR" 4
+.IX Item "-fmodulo-sched"
+Perform swing modulo scheduling immediately before the first scheduling
+pass. This pass looks at innermost loops and reorders their
+instructions by overlapping different iterations.
.IP "\fB\-fno\-branch\-count\-reg\fR" 4
.IX Item "-fno-branch-count-reg"
-Do not use ``decrement and branch'' instructions on a count register,
+Do not use \*(L"decrement and branch\*(R" instructions on a count register,
but instead generate a sequence of instructions that decrement a
register, compare it against zero, then branch based upon the result.
This option is only meaningful on architectures that support such
instructions, which include x86, PowerPC, \s-1IA\-64\s0 and S/390.
.Sp
-The default is \fB\-fbranch\-count\-reg\fR, enabled when
-\&\fB\-fstrength\-reduce\fR is enabled.
+The default is \fB\-fbranch\-count\-reg\fR.
.IP "\fB\-fno\-function\-cse\fR" 4
.IX Item "-fno-function-cse"
Do not put function addresses in registers; make each instruction that
@@ -3532,12 +4485,33 @@ resulting executable can find the beginning of that section and/or make
assumptions based on that.
.Sp
The default is \fB\-fzero\-initialized\-in\-bss\fR.
-.IP "\fB\-fstrength\-reduce\fR" 4
-.IX Item "-fstrength-reduce"
-Perform the optimizations of loop strength reduction and
-elimination of iteration variables.
-.Sp
-Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
+.IP "\fB\-fbounds\-check\fR" 4
+.IX Item "-fbounds-check"
+For front-ends that support it, generate additional code to check that
+indices used to access arrays are within the declared range. This is
+currently only supported by the Java and Fortran front\-ends, where
+this option defaults to true and false respectively.
+.IP "\fB\-fmudflap \-fmudflapth \-fmudflapir\fR" 4
+.IX Item "-fmudflap -fmudflapth -fmudflapir"
+For front-ends that support it (C and \*(C+), instrument all risky
+pointer/array dereferencing operations, some standard library
+string/heap functions, and some other associated constructs with
+range/validity tests. Modules so instrumented should be immune to
+buffer overflows, invalid heap use, and some other classes of C/\*(C+
+programming errors. The instrumentation relies on a separate runtime
+library (\fIlibmudflap\fR), which will be linked into a program if
+\&\fB\-fmudflap\fR is given at link time. Run-time behavior of the
+instrumented program is controlled by the \fB\s-1MUDFLAP_OPTIONS\s0\fR
+environment variable. See \f(CW\*(C`env MUDFLAP_OPTIONS=\-help a.out\*(C'\fR
+for its options.
+.Sp
+Use \fB\-fmudflapth\fR instead of \fB\-fmudflap\fR to compile and to
+link if your program is multi\-threaded. Use \fB\-fmudflapir\fR, in
+addition to \fB\-fmudflap\fR or \fB\-fmudflapth\fR, if
+instrumentation should ignore pointer reads. This produces less
+instrumentation (and therefore faster execution) and still provides
+some protection against outright memory corrupting writes, but allows
+erroneously read data to propagate within a program.
.IP "\fB\-fthread\-jumps\fR" 4
.IX Item "-fthread-jumps"
Perform optimizations where we check to see if a jump branches to a
@@ -3546,7 +4520,7 @@ so, the first branch is redirected to either the destination of the
second branch or a point immediately following it, depending on whether
the condition is known to be true or false.
.Sp
-Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
+Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IP "\fB\-fcse\-follow\-jumps\fR" 4
.IX Item "-fcse-follow-jumps"
In common subexpression elimination, scan through jump instructions
@@ -3571,11 +4545,6 @@ Re-run common subexpression elimination after loop optimizations has been
performed.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
-.IP "\fB\-frerun\-loop\-opt\fR" 4
-.IX Item "-frerun-loop-opt"
-Run the loop optimizer twice.
-.Sp
-Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IP "\fB\-fgcse\fR" 4
.IX Item "-fgcse"
Perform a global common subexpression elimination pass.
@@ -3603,27 +4572,33 @@ stores out of loops. When used in conjunction with \fB\-fgcse\-lm\fR,
loops containing a load/store sequence can be changed to a load before
the loop and a store after the loop.
.Sp
-Enabled by default when gcse is enabled.
+Not enabled at any optimization level.
.IP "\fB\-fgcse\-las\fR" 4
.IX Item "-fgcse-las"
When \fB\-fgcse\-las\fR is enabled, the global common subexpression
elimination pass eliminates redundant loads that come after stores to the
same memory location (both partial and full redundancies).
.Sp
-Enabled by default when gcse is enabled.
-.IP "\fB\-floop\-optimize\fR" 4
-.IX Item "-floop-optimize"
-Perform loop optimizations: move constant expressions out of loops, simplify
-exit test conditions and optionally do strength-reduction and loop unrolling as
-well.
-.Sp
-Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
+Not enabled at any optimization level.
+.IP "\fB\-fgcse\-after\-reload\fR" 4
+.IX Item "-fgcse-after-reload"
+When \fB\-fgcse\-after\-reload\fR is enabled, a redundant load elimination
+pass is performed after reload. The purpose of this pass is to cleanup
+redundant spilling.
+.IP "\fB\-funsafe\-loop\-optimizations\fR" 4
+.IX Item "-funsafe-loop-optimizations"
+If given, the loop optimizer will assume that loop indices do not
+overflow, and that the loops with nontrivial exit condition are not
+infinite. This enables a wider range of loop optimizations even if
+the loop optimizer itself cannot prove that these assumptions are valid.
+Using \fB\-Wunsafe\-loop\-optimizations\fR, the compiler will warn you
+if it finds this kind of loop.
.IP "\fB\-fcrossjumping\fR" 4
.IX Item "-fcrossjumping"
-Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The
+Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The
resulting code may or may not perform better than without cross\-jumping.
.Sp
-Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
+Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IP "\fB\-fif\-conversion\fR" 4
.IX Item "-fif-conversion"
Attempt to transform conditional jumps into branch-less equivalents. This
@@ -3743,10 +4718,19 @@ size of superblocks using tracer pass. See \fB\-ftracer\fR for details on
trace formation.
.Sp
This mode should produce faster but significantly longer programs. Also
-without \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR the traces constructed may not match the
-reality and hurt the performance. This only makes
+without \fB\-fbranch\-probabilities\fR the traces constructed may not
+match the reality and hurt the performance. This only makes
sense when scheduling after register allocation, i.e. with
\&\fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher.
+.IP "\fB\-fsee\fR" 4
+.IX Item "-fsee"
+Eliminates redundant extension instructions and move the non redundant
+ones to optimal placement using \s-1LCM\s0.
+.IP "\fB\-freschedule\-modulo\-scheduled\-loops\fR" 4
+.IX Item "-freschedule-modulo-scheduled-loops"
+The modulo scheduling comes before the traditional scheduling, if a loop was modulo scheduled
+we may want to prevent the later scheduling passes from changing its schedule, we use this
+option to control that.
.IP "\fB\-fcaller\-saves\fR" 4
.IX Item "-fcaller-saves"
Enable values to be allocated in registers that will be clobbered by
@@ -3758,30 +4742,178 @@ This option is always enabled by default on certain machines, usually
those which have no call-preserved registers to use instead.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
-.IP "\fB\-fmove\-all\-movables\fR" 4
-.IX Item "-fmove-all-movables"
-Forces all invariant computations in loops to be moved
-outside the loop.
-.IP "\fB\-freduce\-all\-givs\fR" 4
-.IX Item "-freduce-all-givs"
-Forces all general-induction variables in loops to be
-strength\-reduced.
-.Sp
-\&\fINote:\fR When compiling programs written in Fortran,
-\&\fB\-fmove\-all\-movables\fR and \fB\-freduce\-all\-givs\fR are enabled
-by default when you use the optimizer.
-.Sp
-These options may generate better or worse code; results are highly
-dependent on the structure of loops within the source code.
+.IP "\fB\-ftree\-pre\fR" 4
+.IX Item "-ftree-pre"
+Perform Partial Redundancy Elimination (\s-1PRE\s0) on trees. This flag is
+enabled by default at \fB\-O2\fR and \fB\-O3\fR.
+.IP "\fB\-ftree\-fre\fR" 4
+.IX Item "-ftree-fre"
+Perform Full Redundancy Elimination (\s-1FRE\s0) on trees. The difference
+between \s-1FRE\s0 and \s-1PRE\s0 is that \s-1FRE\s0 only considers expressions
+that are computed on all paths leading to the redundant computation.
+This analysis faster than \s-1PRE\s0, though it exposes fewer redundancies.
+This flag is enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-copy\-prop\fR" 4
+.IX Item "-ftree-copy-prop"
+Perform copy propagation on trees. This pass eliminates unnecessary
+copy operations. This flag is enabled by default at \fB\-O\fR and
+higher.
+.IP "\fB\-ftree\-store\-copy\-prop\fR" 4
+.IX Item "-ftree-store-copy-prop"
+Perform copy propagation of memory loads and stores. This pass
+eliminates unnecessary copy operations in memory references
+(structures, global variables, arrays, etc). This flag is enabled by
+default at \fB\-O2\fR and higher.
+.IP "\fB\-ftree\-salias\fR" 4
+.IX Item "-ftree-salias"
+Perform structural alias analysis on trees. This flag
+is enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-fipa\-pta\fR" 4
+.IX Item "-fipa-pta"
+Perform interprocedural pointer analysis.
+.IP "\fB\-ftree\-sink\fR" 4
+.IX Item "-ftree-sink"
+Perform forward store motion on trees. This flag is
+enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-ccp\fR" 4
+.IX Item "-ftree-ccp"
+Perform sparse conditional constant propagation (\s-1CCP\s0) on trees. This
+pass only operates on local scalar variables and is enabled by default
+at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-store\-ccp\fR" 4
+.IX Item "-ftree-store-ccp"
+Perform sparse conditional constant propagation (\s-1CCP\s0) on trees. This
+pass operates on both local scalar variables and memory stores and
+loads (global variables, structures, arrays, etc). This flag is
+enabled by default at \fB\-O2\fR and higher.
+.IP "\fB\-ftree\-dce\fR" 4
+.IX Item "-ftree-dce"
+Perform dead code elimination (\s-1DCE\s0) on trees. This flag is enabled by
+default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-dominator\-opts\fR" 4
+.IX Item "-ftree-dominator-opts"
+Perform a variety of simple scalar cleanups (constant/copy
+propagation, redundancy elimination, range propagation and expression
+simplification) based on a dominator tree traversal. This also
+performs jump threading (to reduce jumps to jumps). This flag is
+enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-ch\fR" 4
+.IX Item "-ftree-ch"
+Perform loop header copying on trees. This is beneficial since it increases
+effectiveness of code motion optimizations. It also saves one jump. This flag
+is enabled by default at \fB\-O\fR and higher. It is not enabled
+for \fB\-Os\fR, since it usually increases code size.
+.IP "\fB\-ftree\-loop\-optimize\fR" 4
+.IX Item "-ftree-loop-optimize"
+Perform loop optimizations on trees. This flag is enabled by default
+at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-loop\-linear\fR" 4
+.IX Item "-ftree-loop-linear"
+Perform linear loop transformations on tree. This flag can improve cache
+performance and allow further loop optimizations to take place.
+.IP "\fB\-ftree\-loop\-im\fR" 4
+.IX Item "-ftree-loop-im"
+Perform loop invariant motion on trees. This pass moves only invariants that
+would be hard to handle at \s-1RTL\s0 level (function calls, operations that expand to
+nontrivial sequences of insns). With \fB\-funswitch\-loops\fR it also moves
+operands of conditions that are invariant out of the loop, so that we can use
+just trivial invariantness analysis in loop unswitching. The pass also includes
+store motion.
+.IP "\fB\-ftree\-loop\-ivcanon\fR" 4
+.IX Item "-ftree-loop-ivcanon"
+Create a canonical counter for number of iterations in the loop for that
+determining number of iterations requires complicated analysis. Later
+optimizations then may determine the number easily. Useful especially
+in connection with unrolling.
+.IP "\fB\-fivopts\fR" 4
+.IX Item "-fivopts"
+Perform induction variable optimizations (strength reduction, induction
+variable merging and induction variable elimination) on trees.
+.IP "\fB\-ftree\-sra\fR" 4
+.IX Item "-ftree-sra"
+Perform scalar replacement of aggregates. This pass replaces structure
+references with scalars to prevent committing structures to memory too
+early. This flag is enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-copyrename\fR" 4
+.IX Item "-ftree-copyrename"
+Perform copy renaming on trees. This pass attempts to rename compiler
+temporaries to other variables at copy locations, usually resulting in
+variable names which more closely resemble the original variables. This flag
+is enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-ter\fR" 4
+.IX Item "-ftree-ter"
+Perform temporary expression replacement during the \s-1SSA\-\s0>normal phase. Single
+use/single def temporaries are replaced at their use location with their
+defining expression. This results in non-GIMPLE code, but gives the expanders
+much more complex trees to work on resulting in better \s-1RTL\s0 generation. This is
+enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-lrs\fR" 4
+.IX Item "-ftree-lrs"
+Perform live range splitting during the \s-1SSA\-\s0>normal phase. Distinct live
+ranges of a variable are split into unique variables, allowing for better
+optimization later. This is enabled by default at \fB\-O\fR and higher.
+.IP "\fB\-ftree\-vectorize\fR" 4
+.IX Item "-ftree-vectorize"
+Perform loop vectorization on trees.
+.IP "\fB\-ftree\-vect\-loop\-version\fR" 4
+.IX Item "-ftree-vect-loop-version"
+Perform loop versioning when doing loop vectorization on trees. When a loop
+appears to be vectorizable except that data alignment or data dependence cannot
+be determined at compile time then vectorized and non-vectorized versions of
+the loop are generated along with runtime checks for alignment or dependence
+to control which version is executed. This option is enabled by default
+except at level \fB\-Os\fR where it is disabled.
+.IP "\fB\-ftree\-vrp\fR" 4
+.IX Item "-ftree-vrp"
+Perform Value Range Propagation on trees. This is similar to the
+constant propagation pass, but instead of values, ranges of values are
+propagated. This allows the optimizers to remove unnecessary range
+checks like array bound checks and null pointer checks. This is
+enabled by default at \fB\-O2\fR and higher. Null pointer check
+elimination is only done if \fB\-fdelete\-null\-pointer\-checks\fR is
+enabled.
+.IP "\fB\-ftracer\fR" 4
+.IX Item "-ftracer"
+Perform tail duplication to enlarge superblock size. This transformation
+simplifies the control flow of the function allowing other optimizations to do
+better job.
+.IP "\fB\-funroll\-loops\fR" 4
+.IX Item "-funroll-loops"
+Unroll loops whose number of iterations can be determined at compile
+time or upon entry to the loop. \fB\-funroll\-loops\fR implies
+\&\fB\-frerun\-cse\-after\-loop\fR. This option makes code larger,
+and may or may not make it run faster.
+.IP "\fB\-funroll\-all\-loops\fR" 4
+.IX Item "-funroll-all-loops"
+Unroll all loops, even if their number of iterations is uncertain when
+the loop is entered. This usually makes programs run more slowly.
+\&\fB\-funroll\-all\-loops\fR implies the same options as
+\&\fB\-funroll\-loops\fR,
+.IP "\fB\-fsplit\-ivs\-in\-unroller\fR" 4
+.IX Item "-fsplit-ivs-in-unroller"
+Enables expressing of values of induction variables in later iterations
+of the unrolled loop using the value in the first iteration. This breaks
+long dependency chains, thus improving efficiency of the scheduling passes.
+.Sp
+Combination of \fB\-fweb\fR and \s-1CSE\s0 is often sufficient to obtain the
+same effect. However in cases the loop body is more complicated than
+a single basic block, this is not reliable. It also does not work at all
+on some of the architectures due to restrictions in the \s-1CSE\s0 pass.
+.Sp
+This optimization is enabled by default.
+.IP "\fB\-fvariable\-expansion\-in\-unroller\fR" 4
+.IX Item "-fvariable-expansion-in-unroller"
+With this option, the compiler will create multiple copies of some
+local variables when unrolling a loop which can result in superior code.
+.IP "\fB\-fprefetch\-loop\-arrays\fR" 4
+.IX Item "-fprefetch-loop-arrays"
+If supported by the target machine, generate instructions to prefetch
+memory to improve the performance of loops that access large arrays.
.Sp
-These two options are intended to be removed someday, once
-they have helped determine the efficacy of various
-approaches to improving loop optimizations.
+This option may generate better or worse code; results are highly
+dependent on the structure of loops within the source code.
.Sp
-Please contact <\fBgcc@gcc.gnu.org\fR>, and describe how use of
-these options affects the performance of your production code.
-Examples of code that runs \fIslower\fR when these options are
-\&\fIenabled\fR are very valuable.
+Disabled at level \fB\-Os\fR.
.IP "\fB\-fno\-peephole\fR" 4
.IX Item "-fno-peephole"
.PD 0
@@ -3797,19 +4929,17 @@ other, a few use both.
\&\fB\-fpeephole2\fR enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IP "\fB\-fno\-guess\-branch\-probability\fR" 4
.IX Item "-fno-guess-branch-probability"
-Do not guess branch probabilities using a randomized model.
-.Sp
-Sometimes \s-1GCC\s0 will opt to use a randomized model to guess branch
-probabilities, when none are available from either profiling feedback
-(\fB\-fprofile\-arcs\fR) or \fB_\|_builtin_expect\fR. This means that
-different runs of the compiler on the same program may produce different
-object code.
-.Sp
-In a hard real-time system, people don't want different runs of the
-compiler to produce code that has different behavior; minimizing
-non-determinism is of paramount import. This switch allows users to
-reduce non\-determinism, possibly at the expense of inferior
-optimization.
+Do not guess branch probabilities using heuristics.
+.Sp
+\&\s-1GCC\s0 will use heuristics to guess branch probabilities if they are
+not provided by profiling feedback (\fB\-fprofile\-arcs\fR). These
+heuristics are based on the control flow graph. If some branch probabilities
+are specified by \fB_\|_builtin_expect\fR, then the heuristics will be
+used to guess branch probabilities for the rest of the control flow graph,
+taking the \fB_\|_builtin_expect\fR info into account. The interactions
+between the heuristics and \fB_\|_builtin_expect\fR can be complex, and in
+some cases, it may be useful to disable the heuristics so that the effects
+of \fB_\|_builtin_expect\fR are easier to understand.
.Sp
The default is \fB\-fguess\-branch\-probability\fR at levels
\&\fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
@@ -3819,10 +4949,21 @@ Reorder basic blocks in the compiled function in order to reduce number of
taken branches and improve code locality.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR.
+.IP "\fB\-freorder\-blocks\-and\-partition\fR" 4
+.IX Item "-freorder-blocks-and-partition"
+In addition to reordering basic blocks in the compiled function, in order
+to reduce number of taken branches, partitions hot and cold basic blocks
+into separate sections of the assembly and .o files, to improve
+paging and cache locality performance.
+.Sp
+This optimization is automatically turned off in the presence of
+exception handling, for linkonce sections, for functions with a user-defined
+section attribute and on any architecture that does not support named
+sections.
.IP "\fB\-freorder\-functions\fR" 4
.IX Item "-freorder-functions"
-Reorder basic blocks in the compiled function in order to reduce number of
-taken branches and improve code locality. This is implemented by using special
+Reorder functions in the object file in order to
+improve code locality. This is implemented by using special
subsections \f(CW\*(C`.text.hot\*(C'\fR for most frequently executed functions and
\&\f(CW\*(C`.text.unlikely\*(C'\fR for unlikely executed functions. Reordering is done by
the linker so object file format must support named sections and linker must
@@ -3861,7 +5002,7 @@ Pay special attention to code like this:
.Ve
.Sp
The practice of reading from a different union member than the one most
-recently written to (called ``type\-punning'') is common. Even with
+recently written to (called \*(L"type\-punning\*(R") is common. Even with
\&\fB\-fstrict\-aliasing\fR, type-punning is allowed, provided the memory
is accessed through the union type. So, the code above will work as
expected. However, this code might not:
@@ -3883,6 +5024,31 @@ allowed to alias. For an example, see the C front-end function
\&\f(CW\*(C`c_get_alias_set\*(C'\fR.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
+.IP "\fB\-fstrict\-overflow\fR" 4
+.IX Item "-fstrict-overflow"
+Allow the compiler to assume strict signed overflow rules, depending
+on the language being compiled. For C (and \*(C+) this means that
+overflow when doing arithmetic with signed numbers is undefined, which
+means that the compiler may assume that it will not happen. This
+permits various optimizations. For example, the compiler will assume
+that an expression like \f(CW\*(C`i + 10 > i\*(C'\fR will always be true for
+signed \f(CW\*(C`i\*(C'\fR. This assumption is only valid if signed overflow is
+undefined, as the expression is false if \f(CW\*(C`i + 10\*(C'\fR overflows when
+using twos complement arithmetic. When this option is in effect any
+attempt to determine whether an operation on signed numbers will
+overflow must be written carefully to not actually involve overflow.
+.Sp
+See also the \fB\-fwrapv\fR option. Using \fB\-fwrapv\fR means
+that signed overflow is fully defined: it wraps. When
+\&\fB\-fwrapv\fR is used, there is no difference between
+\&\fB\-fstrict\-overflow\fR and \fB\-fno\-strict\-overflow\fR. With
+\&\fB\-fwrapv\fR certain types of overflow are permitted. For
+example, if the compiler gets an overflow when doing arithmetic on
+constants, the overflowed value can still be used with
+\&\fB\-fwrapv\fR, but not otherwise.
+.Sp
+The \fB\-fstrict\-overflow\fR option is enabled at levels
+\&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IP "\fB\-falign\-functions\fR" 4
.IX Item "-falign-functions"
.PD 0
@@ -3959,13 +5125,49 @@ equivalent and mean that loops will not be aligned.
If \fIn\fR is not specified or is zero, use a machine-dependent default.
.Sp
Enabled at levels \fB\-O2\fR, \fB\-O3\fR.
-.IP "\fB\-frename\-registers\fR" 4
-.IX Item "-frename-registers"
-Attempt to avoid false dependencies in scheduled code by making use
-of registers left over after register allocation. This optimization
-will most benefit processors with lots of registers. It can, however,
-make debugging impossible, since variables will no longer stay in
-a ``home register''.
+.IP "\fB\-funit\-at\-a\-time\fR" 4
+.IX Item "-funit-at-a-time"
+Parse the whole compilation unit before starting to produce code.
+This allows some extra optimizations to take place but consumes
+more memory (in general). There are some compatibility issues
+with \fIunit-at-a-time\fR mode:
+.RS 4
+.IP "*" 4
+enabling \fIunit-at-a-time\fR mode may change the order
+in which functions, variables, and top-level \f(CW\*(C`asm\*(C'\fR statements
+are emitted, and will likely break code relying on some particular
+ordering. The majority of such top-level \f(CW\*(C`asm\*(C'\fR statements,
+though, can be replaced by \f(CW\*(C`section\*(C'\fR attributes. The
+\&\fBfno-toplevel-reorder\fR option may be used to keep the ordering
+used in the input file, at the cost of some optimizations.
+.IP "*" 4
+\&\fIunit-at-a-time\fR mode removes unreferenced static variables
+and functions. This may result in undefined references
+when an \f(CW\*(C`asm\*(C'\fR statement refers directly to variables or functions
+that are otherwise unused. In that case either the variable/function
+shall be listed as an operand of the \f(CW\*(C`asm\*(C'\fR statement operand or,
+in the case of top-level \f(CW\*(C`asm\*(C'\fR statements the attribute \f(CW\*(C`used\*(C'\fR
+shall be used on the declaration.
+.IP "*" 4
+Static functions now can use non-standard passing conventions that
+may break \f(CW\*(C`asm\*(C'\fR statements calling functions directly. Again,
+attribute \f(CW\*(C`used\*(C'\fR will prevent this behavior.
+.RE
+.RS 4
+.Sp
+As a temporary workaround, \fB\-fno\-unit\-at\-a\-time\fR can be used,
+but this scheme may not be supported by future releases of \s-1GCC\s0.
+.Sp
+Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
+.RE
+.IP "\fB\-fno\-toplevel\-reorder\fR" 4
+.IX Item "-fno-toplevel-reorder"
+Do not reorder top-level functions, variables, and \f(CW\*(C`asm\*(C'\fR
+statements. Output them in the same order that they appear in the
+input file. When this option is used, unreferenced static variables
+will not be removed. This option is intended to support existing code
+which relies on a particular ordering. For new code, it is better to
+use attributes.
.IP "\fB\-fweb\fR" 4
.IX Item "-fweb"
Constructs webs as commonly used for register allocation purposes and assign
@@ -3973,9 +5175,20 @@ each web individual pseudo register. This allows the register allocation pass
to operate on pseudos directly, but also strengthens several other optimization
passes, such as \s-1CSE\s0, loop optimizer and trivial dead code remover. It can,
however, make debugging impossible, since variables will no longer stay in a
-``home register''.
-.Sp
-Enabled at levels \fB\-O3\fR.
+\&\*(L"home register\*(R".
+.Sp
+Enabled by default with \fB\-funroll\-loops\fR.
+.IP "\fB\-fwhole\-program\fR" 4
+.IX Item "-fwhole-program"
+Assume that the current compilation unit represents whole program being
+compiled. All public functions and variables with the exception of \f(CW\*(C`main\*(C'\fR
+and those merged by attribute \f(CW\*(C`externally_visible\*(C'\fR become static functions
+and in a affect gets more aggressively optimized by interprocedural optimizers.
+While this option is equivalent to proper use of \f(CW\*(C`static\*(C'\fR keyword for
+programs consisting of single file, in combination with option
+\&\fB\-\-combine\fR this flag can be used to compile most of smaller scale C
+programs since the functions and variables become local for the whole combined
+compilation unit, not for the single source file itself.
.IP "\fB\-fno\-cprop\-registers\fR" 4
.IX Item "-fno-cprop-registers"
After register allocation and post-register allocation instruction splitting,
@@ -3987,7 +5200,7 @@ Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR.
.IX Item "-fprofile-generate"
Enable options usually used for instrumenting application to produce
profile useful for later recompilation with profile feedback based
-optimization. You must use \f(CW\*(C`\-fprofile\-generate\*(C'\fR both when
+optimization. You must use \fB\-fprofile\-generate\fR both when
compiling and when linking your program.
.Sp
The following options are enabled: \f(CW\*(C`\-fprofile\-arcs\*(C'\fR, \f(CW\*(C`\-fprofile\-values\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR.
@@ -3996,8 +5209,8 @@ The following options are enabled: \f(CW\*(C`\-fprofile\-arcs\*(C'\fR, \f(CW\*(C
Enable profile feedback directed optimizations, and optimizations
generally profitable only with profile feedback available.
.Sp
-The following options are enabled: \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR,
-\&\f(CW\*(C`\-fvpt\*(C'\fR, \f(CW\*(C`\-funroll\-loops\*(C'\fR, \f(CW\*(C`\-fpeel\-loops\*(C'\fR, \f(CW\*(C`\-ftracer\*(C'\fR.
+The following options are enabled: \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR,
+\&\f(CW\*(C`\-funroll\-loops\*(C'\fR, \f(CW\*(C`\-fpeel\-loops\*(C'\fR, \f(CW\*(C`\-ftracer\*(C'\fR
.PP
The following options control compiler behavior regarding floating
point arithmetic. These options trade off between speed and
@@ -4018,7 +5231,8 @@ them to store all pertinent intermediate computations into variables.
.IP "\fB\-ffast\-math\fR" 4
.IX Item "-ffast-math"
Sets \fB\-fno\-math\-errno\fR, \fB\-funsafe\-math\-optimizations\fR, \fB\-fno\-trapping\-math\fR, \fB\-ffinite\-math\-only\fR,
-\&\fB\-fno\-rounding\-math\fR and \fB\-fno\-signaling\-nans\fR.
+\&\fB\-fno\-rounding\-math\fR, \fB\-fno\-signaling\-nans\fR
+and \fBfcx-limited-range\fR.
.Sp
This option causes the preprocessor macro \f(CW\*(C`_\|_FAST_MATH_\|_\*(C'\fR to be defined.
.Sp
@@ -4039,6 +5253,10 @@ an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for
math functions.
.Sp
The default is \fB\-fmath\-errno\fR.
+.Sp
+On Darwin systems, the math library never sets \f(CW\*(C`errno\*(C'\fR. There is therefore
+no reason for the compiler to consider the possibility that it might,
+and \fB\-fno\-math\-errno\fR is the default.
.IP "\fB\-funsafe\-math\-optimizations\fR" 4
.IX Item "-funsafe-math-optimizations"
Allow optimizations for floating-point arithmetic that (a) assume
@@ -4069,7 +5287,7 @@ Compile code assuming that floating-point operations cannot generate
user-visible traps. These traps include division by zero, overflow,
underflow, inexact result and invalid operation. This option implies
\&\fB\-fno\-signaling\-nans\fR. Setting this option may allow faster
-code if one relies on ``non\-stop'' \s-1IEEE\s0 arithmetic, for example.
+code if one relies on \*(L"non\-stop\*(R" \s-1IEEE\s0 arithmetic, for example.
.Sp
This option should never be turned on by any \fB\-O\fR option since
it can result in incorrect output for programs which depend on
@@ -4096,6 +5314,13 @@ disable all \s-1GCC\s0 optimizations that are affected by rounding mode.
Future versions of \s-1GCC\s0 may provide finer control of this setting
using C99's \f(CW\*(C`FENV_ACCESS\*(C'\fR pragma. This command line option
will be used to specify the default state for \f(CW\*(C`FENV_ACCESS\*(C'\fR.
+.IP "\fB\-frtl\-abstract\-sequences\fR" 4
+.IX Item "-frtl-abstract-sequences"
+It is a size optimization method. This option is to find identical
+sequences of code, which can be turned into pseudo-procedures and
+then replace all occurrences with calls to the newly created
+subroutine. It is kind of an opposite of \fB\-finline\-functions\fR.
+This optimization runs at \s-1RTL\s0 level.
.IP "\fB\-fsignaling\-nans\fR" 4
.IX Item "-fsignaling-nans"
Compile code assuming that \s-1IEEE\s0 signaling NaNs may generate user-visible
@@ -4114,6 +5339,19 @@ disable all \s-1GCC\s0 optimizations that affect signaling NaN behavior.
.IX Item "-fsingle-precision-constant"
Treat floating point constant as single precision constant instead of
implicitly converting it to double precision constant.
+.IP "\fB\-fcx\-limited\-range\fR" 4
+.IX Item "-fcx-limited-range"
+.PD 0
+.IP "\fB\-fno\-cx\-limited\-range\fR" 4
+.IX Item "-fno-cx-limited-range"
+.PD
+When enabled, this option states that a range reduction step is not
+needed when performing complex division. The default is
+\&\fB\-fno\-cx\-limited\-range\fR, but is enabled by \fB\-ffast\-math\fR.
+.Sp
+This option controls the default setting of the \s-1ISO\s0 C99
+\&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to
+all languages.
.PP
The following options control optimizations that may improve
performance, but are not enabled by any \fB\-O\fR options. This
@@ -4143,6 +5381,8 @@ data about values of expressions in the program is gathered.
With \fB\-fbranch\-probabilities\fR, it reads back the data gathered
from profiling values of expressions and adds \fB\s-1REG_VALUE_PROFILE\s0\fR
notes to instructions for their later usage in optimizations.
+.Sp
+Enabled with \fB\-fprofile\-generate\fR and \fB\-fprofile\-use\fR.
.IP "\fB\-fvpt\fR" 4
.IX Item "-fvpt"
If combined with \fB\-fprofile\-arcs\fR, it instructs the compiler to add
@@ -4152,28 +5392,33 @@ With \fB\-fbranch\-probabilities\fR, it reads back the data gathered
and actually performs the optimizations based on them.
Currently the optimizations include specialization of division operation
using the knowledge about the value of the denominator.
-.IP "\fB\-fnew\-ra\fR" 4
-.IX Item "-fnew-ra"
-Use a graph coloring register allocator. Currently this option is meant
-for testing, so we are interested to hear about miscompilations with
-\&\fB\-fnew\-ra\fR.
+.IP "\fB\-frename\-registers\fR" 4
+.IX Item "-frename-registers"
+Attempt to avoid false dependencies in scheduled code by making use
+of registers left over after register allocation. This optimization
+will most benefit processors with lots of registers. Depending on the
+debug information format adopted by the target, however, it can
+make debugging impossible, since variables will no longer stay in
+a \*(L"home register\*(R".
+.Sp
+Enabled by default with \fB\-funroll\-loops\fR.
.IP "\fB\-ftracer\fR" 4
.IX Item "-ftracer"
-Perform tail duplication to enlarge superblock size. This transformation
+Perform tail duplication to enlarge superblock size. This transformation
simplifies the control flow of the function allowing other optimizations to do
better job.
-.IP "\fB\-funit\-at\-a\-time\fR" 4
-.IX Item "-funit-at-a-time"
-Parse the whole compilation unit before starting to produce code.
-This allows some extra optimizations to take place but consumes more
-memory.
+.Sp
+Enabled with \fB\-fprofile\-use\fR.
.IP "\fB\-funroll\-loops\fR" 4
.IX Item "-funroll-loops"
Unroll loops whose number of iterations can be determined at compile time or
upon entry to the loop. \fB\-funroll\-loops\fR implies
-\&\fB\-frerun\-cse\-after\-loop\fR. It also turns on complete loop peeling
-(i.e. complete removal of loops with small constant number of iterations).
-This option makes code larger, and may or may not make it run faster.
+\&\fB\-frerun\-cse\-after\-loop\fR, \fB\-fweb\fR and \fB\-frename\-registers\fR.
+It also turns on complete loop peeling (i.e. complete removal of loops with
+small constant number of iterations). This option makes code larger, and may
+or may not make it run faster.
+.Sp
+Enabled with \fB\-fprofile\-use\fR.
.IP "\fB\-funroll\-all\-loops\fR" 4
.IX Item "-funroll-all-loops"
Unroll all loops, even if their number of iterations is uncertain when
@@ -4185,38 +5430,16 @@ the loop is entered. This usually makes programs run more slowly.
Peels the loops for that there is enough information that they do not
roll much (from profile feedback). It also turns on complete loop peeling
(i.e. complete removal of loops with small constant number of iterations).
+.Sp
+Enabled with \fB\-fprofile\-use\fR.
+.IP "\fB\-fmove\-loop\-invariants\fR" 4
+.IX Item "-fmove-loop-invariants"
+Enables the loop invariant motion pass in the \s-1RTL\s0 loop optimizer. Enabled
+at level \fB\-O1\fR
.IP "\fB\-funswitch\-loops\fR" 4
.IX Item "-funswitch-loops"
Move branches with loop invariant conditions out of the loop, with duplicates
of the loop on both branches (modified according to result of the condition).
-.IP "\fB\-fold\-unroll\-loops\fR" 4
-.IX Item "-fold-unroll-loops"
-Unroll loops whose number of iterations can be determined at compile
-time or upon entry to the loop, using the old loop unroller whose loop
-recognition is based on notes from frontend. \fB\-fold\-unroll\-loops\fR implies
-both \fB\-fstrength\-reduce\fR and \fB\-frerun\-cse\-after\-loop\fR. This
-option makes code larger, and may or may not make it run faster.
-.IP "\fB\-fold\-unroll\-all\-loops\fR" 4
-.IX Item "-fold-unroll-all-loops"
-Unroll all loops, even if their number of iterations is uncertain when
-the loop is entered. This is done using the old loop unroller whose loop
-recognition is based on notes from frontend. This usually makes programs run more slowly.
-\&\fB\-fold\-unroll\-all\-loops\fR implies the same options as
-\&\fB\-fold\-unroll\-loops\fR.
-.IP "\fB\-funswitch\-loops\fR" 4
-.IX Item "-funswitch-loops"
-Move branches with loop invariant conditions out of the loop, with duplicates
-of the loop on both branches (modified according to result of the condition).
-.IP "\fB\-funswitch\-loops\fR" 4
-.IX Item "-funswitch-loops"
-Move branches with loop invariant conditions out of the loop, with duplicates
-of the loop on both branches (modified according to result of the condition).
-.IP "\fB\-fprefetch\-loop\-arrays\fR" 4
-.IX Item "-fprefetch-loop-arrays"
-If supported by the target machine, generate instructions to prefetch
-memory to improve the performance of loops that access large arrays.
-.Sp
-Disabled at level \fB\-Os\fR.
.IP "\fB\-ffunction\-sections\fR" 4
.IX Item "-ffunction-sections"
.PD 0
@@ -4251,6 +5474,49 @@ a separate optimization pass.
.IX Item "-fbranch-target-load-optimize2"
Perform branch target register load optimization after prologue / epilogue
threading.
+.IP "\fB\-fbtr\-bb\-exclusive\fR" 4
+.IX Item "-fbtr-bb-exclusive"
+When performing branch target register load optimization, don't reuse
+branch target registers in within any basic block.
+.IP "\fB\-fstack\-protector\fR" 4
+.IX Item "-fstack-protector"
+Emit extra code to check for buffer overflows, such as stack smashing
+attacks. This is done by adding a guard variable to functions with
+vulnerable objects. This includes functions that call alloca, and
+functions with buffers larger than 8 bytes. The guards are initialized
+when a function is entered and then checked when the function exits.
+If a guard check fails, an error message is printed and the program exits.
+.IP "\fB\-fstack\-protector\-all\fR" 4
+.IX Item "-fstack-protector-all"
+Like \fB\-fstack\-protector\fR except that all functions are protected.
+.IP "\fB\-fsection\-anchors\fR" 4
+.IX Item "-fsection-anchors"
+Try to reduce the number of symbolic address calculations by using
+shared \*(L"anchor\*(R" symbols to address nearby objects. This transformation
+can help to reduce the number of \s-1GOT\s0 entries and \s-1GOT\s0 accesses on some
+targets.
+.Sp
+For example, the implementation of the following function \f(CW\*(C`foo\*(C'\fR:
+.Sp
+.Vb 2
+\& static int a, b, c;
+\& int foo (void) { return a + b + c; }
+.Ve
+.Sp
+would usually calculate the addresses of all three variables, but if you
+compile it with \fB\-fsection\-anchors\fR, it will access the variables
+from a common anchor point instead. The effect is similar to the
+following pseudocode (which isn't valid C):
+.Sp
+.Vb 5
+\& int foo (void)
+\& {
+\& register int *xr = &x;
+\& return xr[&a - &x] + xr[&b - &x] + xr[&c - &x];
+\& }
+.Ve
+.Sp
+Not all targets support this option.
.IP "\fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR" 4
.IX Item "--param name=value"
In some places, \s-1GCC\s0 uses various constants to control the amount of
@@ -4266,6 +5532,28 @@ without notice in future releases.
In each case, the \fIvalue\fR is an integer. The allowable choices for
\&\fIname\fR are given in the following table:
.RS 4
+.IP "\fBsalias-max-implicit-fields\fR" 4
+.IX Item "salias-max-implicit-fields"
+The maximum number of fields in a variable without direct
+structure accesses for which structure aliasing will consider trying
+to track each field. The default is 5
+.IP "\fBsalias-max-array-elements\fR" 4
+.IX Item "salias-max-array-elements"
+The maximum number of elements an array can have and its elements
+still be tracked individually by structure aliasing. The default is 4
+.IP "\fBsra-max-structure-size\fR" 4
+.IX Item "sra-max-structure-size"
+The maximum structure size, in bytes, at which the scalar replacement
+of aggregates (\s-1SRA\s0) optimization will perform block copies. The
+default value, 0, implies that \s-1GCC\s0 will select the most appropriate
+size itself.
+.IP "\fBsra-field-structure-ratio\fR" 4
+.IX Item "sra-field-structure-ratio"
+The threshold ratio (as a percentage) between instantiated fields and
+the complete structure size. We say that if the ratio of the number
+of bytes in instantiated fields to the number of bytes in the complete
+structure exceeds this parameter, then block copies are not used. The
+default is 75.
.IP "\fBmax-crossjump-edges\fR" 4
.IX Item "max-crossjump-edges"
The maximum number of incoming edges to consider for crossjumping.
@@ -4273,6 +5561,25 @@ The algorithm used by \fB\-fcrossjumping\fR is O(N^2) in
the number of edges incoming to each block. Increasing values mean
more aggressive optimization, making the compile time increase with
probably small improvement in executable size.
+.IP "\fBmin-crossjump-insns\fR" 4
+.IX Item "min-crossjump-insns"
+The minimum number of instructions which must be matched at the end
+of two blocks before crossjumping will be performed on them. This
+value is ignored in the case where all instructions in the block being
+crossjumped from are matched. The default value is 5.
+.IP "\fBmax-grow-copy-bb-insns\fR" 4
+.IX Item "max-grow-copy-bb-insns"
+The maximum code size expansion factor when copying basic blocks
+instead of jumping. The expansion is relative to a jump instruction.
+The default value is 8.
+.IP "\fBmax-goto-duplication-insns\fR" 4
+.IX Item "max-goto-duplication-insns"
+The maximum number of instructions to duplicate to a block that jumps
+to a computed goto. To avoid O(N^2) behavior in a number of
+passes, \s-1GCC\s0 factors computed gotos early in the compilation process,
+and unfactors them as late as possible. Only computed jumps at the
+end of a basic blocks with no more than max-goto-duplication-insns are
+unfactored. The default value is 8.
.IP "\fBmax-delay-slot-insn-search\fR" 4
.IX Item "max-delay-slot-insn-search"
The maximum number of instructions to consider when looking for an
@@ -4297,7 +5604,7 @@ optimization. If more memory than specified is required, the
optimization will not be done.
.IP "\fBmax-gcse-passes\fR" 4
.IX Item "max-gcse-passes"
-The maximum number of passes of \s-1GCSE\s0 to run.
+The maximum number of passes of \s-1GCSE\s0 to run. The default is 1.
.IP "\fBmax-pending-list-length\fR" 4
.IX Item "max-pending-list-length"
The maximum number of pending dependencies scheduling will allow
@@ -4311,7 +5618,7 @@ This number sets the maximum number of instructions (counted in \s-1GCC\s0's
internal representation) in a single function that the tree inliner
will consider for inlining. This only affects functions declared
inline and methods implemented in a class declaration (\*(C+).
-The default value is 500.
+The default value is 450.
.IP "\fBmax-inline-insns-auto\fR" 4
.IX Item "max-inline-insns-auto"
When you use \fB\-finline\-functions\fR (included in \fB\-O3\fR),
@@ -4319,31 +5626,87 @@ a lot of functions that would otherwise not be considered for inlining
by the compiler will be investigated. To those functions, a different
(more restrictive) limit compared to functions declared inline can
be applied.
-The default value is 100.
+The default value is 90.
.IP "\fBlarge-function-insns\fR" 4
.IX Item "large-function-insns"
-The limit specifying really large functions. For functions greater than this
-limit inlining is constrained by \fB\-\-param large-function-growth\fR.
-This parameter is useful primarily to avoid extreme compilation time caused by non-linear
-algorithms used by the backend.
+The limit specifying really large functions. For functions larger than this
+limit after inlining inlining is constrained by
+\&\fB\-\-param large-function-growth\fR. This parameter is useful primarily
+to avoid extreme compilation time caused by non-linear algorithms used by the
+backend.
This parameter is ignored when \fB\-funit\-at\-a\-time\fR is not used.
-The default value is 3000.
+The default value is 2700.
.IP "\fBlarge-function-growth\fR" 4
.IX Item "large-function-growth"
Specifies maximal growth of large function caused by inlining in percents.
This parameter is ignored when \fB\-funit\-at\-a\-time\fR is not used.
-The default value is 200.
+The default value is 100 which limits large function growth to 2.0 times
+the original size.
+.IP "\fBlarge-unit-insns\fR" 4
+.IX Item "large-unit-insns"
+The limit specifying large translation unit. Growth caused by inlining of
+units larger than this limit is limited by \fB\-\-param inline-unit-growth\fR.
+For small units this might be too tight (consider unit consisting of function A
+that is inline and B that just calls A three time. If B is small relative to
+A, the growth of unit is 300\e% and yet such inlining is very sane. For very
+large units consisting of small inlininable functions however the overall unit
+growth limit is needed to avoid exponential explosion of code size. Thus for
+smaller units, the size is increased to \fB\-\-param large-unit-insns\fR
+before applying \fB\-\-param inline-unit-growth\fR. The default is 10000
.IP "\fBinline-unit-growth\fR" 4
.IX Item "inline-unit-growth"
Specifies maximal overall growth of the compilation unit caused by inlining.
This parameter is ignored when \fB\-funit\-at\-a\-time\fR is not used.
-The default value is 150.
-.IP "\fBmax-inline-insns-rtl\fR" 4
-.IX Item "max-inline-insns-rtl"
-For languages that use the \s-1RTL\s0 inliner (this happens at a later stage
-than tree inlining), you can set the maximum allowable size (counted
-in \s-1RTL\s0 instructions) for the \s-1RTL\s0 inliner with this parameter.
-The default value is 600.
+The default value is 50 which limits unit growth to 1.5 times the original
+size.
+.IP "\fBmax-inline-insns-recursive\fR" 4
+.IX Item "max-inline-insns-recursive"
+.PD 0
+.IP "\fBmax-inline-insns-recursive-auto\fR" 4
+.IX Item "max-inline-insns-recursive-auto"
+.PD
+Specifies maximum number of instructions out-of-line copy of self recursive inline
+function can grow into by performing recursive inlining.
+.Sp
+For functions declared inline \fB\-\-param max-inline-insns-recursive\fR is
+taken into account. For function not declared inline, recursive inlining
+happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is
+enabled and \fB\-\-param max-inline-insns-recursive-auto\fR is used. The
+default value is 450.
+.IP "\fBmax-inline-recursive-depth\fR" 4
+.IX Item "max-inline-recursive-depth"
+.PD 0
+.IP "\fBmax-inline-recursive-depth-auto\fR" 4
+.IX Item "max-inline-recursive-depth-auto"
+.PD
+Specifies maximum recursion depth used by the recursive inlining.
+.Sp
+For functions declared inline \fB\-\-param max-inline-recursive-depth\fR is
+taken into account. For function not declared inline, recursive inlining
+happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is
+enabled and \fB\-\-param max-inline-recursive-depth-auto\fR is used. The
+default value is 450.
+.IP "\fBmin-inline-recursive-probability\fR" 4
+.IX Item "min-inline-recursive-probability"
+Recursive inlining is profitable only for function having deep recursion
+in average and can hurt for function having little recursion depth by
+increasing the prologue size or complexity of function body to other
+optimizers.
+.Sp
+When profile feedback is available (see \fB\-fprofile\-generate\fR) the actual
+recursion depth can be guessed from probability that function will recurse via
+given call expression. This parameter limits inlining only to call expression
+whose probability exceeds given threshold (in percents). The default value is
+10.
+.IP "\fBinline-call-cost\fR" 4
+.IX Item "inline-call-cost"
+Specify cost of call instruction relative to simple arithmetics operations
+(having cost of 1). Increasing this cost disqualifies inlining of non-leaf
+functions and at the same time increases size of leaf function that is believed to
+reduce function size by being inlined. In effect it increases amount of
+inlining for code having large abstraction penalty (many functions that just
+pass the arguments to other functions) and decrease inlining for code with low
+abstraction penalty. The default value is 16.
.IP "\fBmax-unrolled-insns\fR" 4
.IX Item "max-unrolled-insns"
The maximum number of instructions that a loop should have if that loop
@@ -4377,6 +5740,37 @@ The maximum number of insns of an unswitched loop.
.IP "\fBmax-unswitch-level\fR" 4
.IX Item "max-unswitch-level"
The maximum number of branches unswitched in a single loop.
+.IP "\fBlim-expensive\fR" 4
+.IX Item "lim-expensive"
+The minimum cost of an expensive expression in the loop invariant motion.
+.IP "\fBiv-consider-all-candidates-bound\fR" 4
+.IX Item "iv-consider-all-candidates-bound"
+Bound on number of candidates for induction variables below that
+all candidates are considered for each use in induction variable
+optimizations. Only the most relevant candidates are considered
+if there are more candidates, to avoid quadratic time complexity.
+.IP "\fBiv-max-considered-uses\fR" 4
+.IX Item "iv-max-considered-uses"
+The induction variable optimizations give up on loops that contain more
+induction variable uses.
+.IP "\fBiv-always-prune-cand-set-bound\fR" 4
+.IX Item "iv-always-prune-cand-set-bound"
+If number of candidates in the set is smaller than this value,
+we always try to remove unnecessary ivs from the set during its
+optimization when a new iv is added to the set.
+.IP "\fBscev-max-expr-size\fR" 4
+.IX Item "scev-max-expr-size"
+Bound on size of expressions used in the scalar evolutions analyzer.
+Large expressions slow the analyzer.
+.IP "\fBvect-max-version-checks\fR" 4
+.IX Item "vect-max-version-checks"
+The maximum number of runtime checks that can be performed when doing
+loop versioning in the vectorizer. See option ftree-vect-loop-version
+for more information.
+.IP "\fBmax-iterations-to-track\fR" 4
+.IX Item "max-iterations-to-track"
+The maximum number of iterations of a loop the brute force algorithm
+for analysis of # of iterations of the loop tries to evaluate.
.IP "\fBhot-bb-count-fraction\fR" 4
.IX Item "hot-bb-count-fraction"
Select fraction of the maximal count of repetitions of basic block in program
@@ -4385,6 +5779,13 @@ given basic block needs to have to be considered hot.
.IX Item "hot-bb-frequency-fraction"
Select fraction of the maximal frequency of executions of basic block in
function given basic block needs to have to be considered hot
+.IP "\fBmax-predicted-iterations\fR" 4
+.IX Item "max-predicted-iterations"
+The maximum number of loop iterations we predict statically. This is useful
+in cases where function contain single loop with known bound and other loop
+with unknown. We predict the known number of iterations correctly, while
+the unknown number of iterations average to roughly 10. This means that the
+loop without bounds would appear artificially cold relative to the other one.
.IP "\fBtracer-dynamic-coverage\fR" 4
.IX Item "tracer-dynamic-coverage"
.PD 0
@@ -4423,12 +5824,24 @@ for compilation with profile feedback needs to be more conservative (higher) in
order to make tracer effective.
.IP "\fBmax-cse-path-length\fR" 4
.IX Item "max-cse-path-length"
-Maximum number of basic blocks on path that cse considers.
-.IP "\fBmax-last-value-rtl\fR" 4
-.IX Item "max-last-value-rtl"
-The maximum size measured as number of RTLs that can be recorded in an
-expression in combiner for a pseudo register as last known value of that
-register. The default is 10000.
+Maximum number of basic blocks on path that cse considers. The default is 10.
+.IP "\fBmax-cse-insns\fR" 4
+.IX Item "max-cse-insns"
+The maximum instructions \s-1CSE\s0 process before flushing. The default is 1000.
+.IP "\fBglobal-var-threshold\fR" 4
+.IX Item "global-var-threshold"
+Counts the number of function calls (\fIn\fR) and the number of
+call-clobbered variables (\fIv\fR). If \fIn\fRx\fIv\fR is larger than this limit, a
+single artificial variable will be created to represent all the
+call-clobbered variables at function call sites. This artificial
+variable will then be made to alias every call-clobbered variable.
+(done as \f(CW\*(C`int * size_t\*(C'\fR on the host machine; beware overflow).
+.IP "\fBmax-aliased-vops\fR" 4
+.IX Item "max-aliased-vops"
+Maximum number of virtual operands allowed to represent aliases
+before triggering the alias grouping heuristic. Alias grouping
+reduces compile times and memory consumption needed for aliasing at
+the expense of precision loss in alias information.
.IP "\fBggc-min-expand\fR" 4
.IX Item "ggc-min-expand"
\&\s-1GCC\s0 uses a garbage collector to manage its own memory allocation. This
@@ -4439,7 +5852,7 @@ generation.
.Sp
The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when
\&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\s0\*(R" is
-the smallest of actual \s-1RAM\s0, \s-1RLIMIT_RSS\s0, \s-1RLIMIT_DATA\s0 and \s-1RLIMIT_AS\s0. If
+the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If
\&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower
bound of 30% is used. Setting this parameter and
\&\fBggc-min-heapsize\fR to zero causes a full collection to occur at
@@ -4453,25 +5866,29 @@ by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR. Again,
tuning this may improve compilation speed, and has no effect on code
generation.
.Sp
-The default is \s-1RAM/8\s0, with a lower bound of 4096 (four megabytes) and an
-upper bound of 131072 (128 megabytes). If \f(CW\*(C`getrlimit\*(C'\fR is
-available, the notion of \*(L"\s-1RAM\s0\*(R" is the smallest of actual \s-1RAM\s0,
-\&\s-1RLIMIT_RSS\s0, \s-1RLIMIT_DATA\s0 and \s-1RLIMIT_AS\s0. If \s-1GCC\s0 is not able to calculate
-\&\s-1RAM\s0 on a particular platform, the lower bound is used. Setting this
-parameter very large effectively disables garbage collection. Setting
-this parameter and \fBggc-min-expand\fR to zero causes a full
-collection to occur at every opportunity.
+The default is the smaller of \s-1RAM/8\s0, \s-1RLIMIT_RSS\s0, or a limit which
+tries to ensure that \s-1RLIMIT_DATA\s0 or \s-1RLIMIT_AS\s0 are not exceeded, but
+with a lower bound of 4096 (four megabytes) and an upper bound of
+131072 (128 megabytes). If \s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a
+particular platform, the lower bound is used. Setting this parameter
+very large effectively disables garbage collection. Setting this
+parameter and \fBggc-min-expand\fR to zero causes a full collection
+to occur at every opportunity.
.IP "\fBmax-reload-search-insns\fR" 4
.IX Item "max-reload-search-insns"
The maximum number of instruction reload should look backward for equivalent
register. Increasing values mean more aggressive optimization, making the
compile time increase with probably slightly better performance. The default
value is 100.
-.IP "\fBmax-cselib-memory-location\fR" 4
-.IX Item "max-cselib-memory-location"
-The maximum number of memory locations cselib should take into acount.
+.IP "\fBmax-cselib-memory-locations\fR" 4
+.IX Item "max-cselib-memory-locations"
+The maximum number of memory locations cselib should take into account.
Increasing values mean more aggressive optimization, making the compile time
increase with probably slightly better performance. The default value is 500.
+.IP "\fBmax-flow-memory-locations\fR" 4
+.IX Item "max-flow-memory-locations"
+Similar as \fBmax-cselib-memory-locations\fR but for dataflow liveness.
+The default value is 100.
.IP "\fBreorder-blocks-duplicate\fR" 4
.IX Item "reorder-blocks-duplicate"
.PD 0
@@ -4487,6 +5904,73 @@ The \fBreorder-block-duplicate-feedback\fR is used only when profile
feedback is available and may be set to higher values than
\&\fBreorder-block-duplicate\fR since information about the hot spots is more
accurate.
+.IP "\fBmax-sched-ready-insns\fR" 4
+.IX Item "max-sched-ready-insns"
+The maximum number of instructions ready to be issued the scheduler should
+consider at any given time during the first scheduling pass. Increasing
+values mean more thorough searches, making the compilation time increase
+with probably little benefit. The default value is 100.
+.IP "\fBmax-sched-region-blocks\fR" 4
+.IX Item "max-sched-region-blocks"
+The maximum number of blocks in a region to be considered for
+interblock scheduling. The default value is 10.
+.IP "\fBmax-sched-region-insns\fR" 4
+.IX Item "max-sched-region-insns"
+The maximum number of insns in a region to be considered for
+interblock scheduling. The default value is 100.
+.IP "\fBmin-spec-prob\fR" 4
+.IX Item "min-spec-prob"
+The minimum probability (in percents) of reaching a source block
+for interblock speculative scheduling. The default value is 40.
+.IP "\fBmax-sched-extend-regions-iters\fR" 4
+.IX Item "max-sched-extend-regions-iters"
+The maximum number of iterations through \s-1CFG\s0 to extend regions.
+0 \- disable region extension,
+N \- do at most N iterations.
+The default value is 0.
+.IP "\fBmax-sched-insn-conflict-delay\fR" 4
+.IX Item "max-sched-insn-conflict-delay"
+The maximum conflict delay for an insn to be considered for speculative motion.
+The default value is 3.
+.IP "\fBsched-spec-prob-cutoff\fR" 4
+.IX Item "sched-spec-prob-cutoff"
+The minimal probability of speculation success (in percents), so that
+speculative insn will be scheduled.
+The default value is 40.
+.IP "\fBmax-last-value-rtl\fR" 4
+.IX Item "max-last-value-rtl"
+The maximum size measured as number of RTLs that can be recorded in an expression
+in combiner for a pseudo register as last known value of that register. The default
+is 10000.
+.IP "\fBinteger-share-limit\fR" 4
+.IX Item "integer-share-limit"
+Small integer constants can use a shared data structure, reducing the
+compiler's memory usage and increasing its speed. This sets the maximum
+value of a shared integer constant's. The default value is 256.
+.IP "\fBmin-virtual-mappings\fR" 4
+.IX Item "min-virtual-mappings"
+Specifies the minimum number of virtual mappings in the incremental
+\&\s-1SSA\s0 updater that should be registered to trigger the virtual mappings
+heuristic defined by virtual\-mappings\-ratio. The default value is
+100.
+.IP "\fBvirtual-mappings-ratio\fR" 4
+.IX Item "virtual-mappings-ratio"
+If the number of virtual mappings is virtual-mappings-ratio bigger
+than the number of virtual symbols to be updated, then the incremental
+\&\s-1SSA\s0 updater switches to a full update for those symbols. The default
+ratio is 3.
+.IP "\fBssp-buffer-size\fR" 4
+.IX Item "ssp-buffer-size"
+The minimum size of buffers (i.e. arrays) that will receive stack smashing
+protection when \fB\-fstack\-protection\fR is used.
+.IP "\fBmax-jump-thread-duplication-stmts\fR" 4
+.IX Item "max-jump-thread-duplication-stmts"
+Maximum number of statements allowed in a block that needs to be
+duplicated when threading jumps.
+.IP "\fBmax-fields-for-field-sensitive\fR" 4
+.IX Item "max-fields-for-field-sensitive"
+Maximum number of fields in a structure we will treat in
+a field sensitive manner during pointer analysis.
.RE
.RS 4
.RE
@@ -4524,7 +6008,6 @@ If you want to pass an option that takes an argument, you must use
Predefine \fIname\fR as a macro, with definition \f(CW1\fR.
.IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4
.IX Item "-D name=definition"
-Predefine \fIname\fR as a macro, with definition \fIdefinition\fR.
The contents of \fIdefinition\fR are tokenized and processed as if
they appeared during translation phase three in a \fB#define\fR
directive. In particular, the definition will be truncated by
@@ -4587,7 +6070,6 @@ comment, or whenever a backslash-newline appears in a \fB//\fR comment.
(Both forms have the same effect.)
.IP "\fB\-Wtrigraphs\fR" 4
.IX Item "-Wtrigraphs"
-@anchor{Wtrigraphs}
Most trigraphs in comments cannot affect the meaning of the program.
However, a trigraph that would form an escaped newline (\fB??/\fR at
the end of a line) can, by changing where the comment begins or ends.
@@ -4621,7 +6103,7 @@ time it is redefined or undefined.
Built-in macros, macros defined on the command line, and macros
defined in include files are not warned about.
.Sp
-\&\fBNote:\fR If a macro is actually used, but only used in skipped
+\&\fINote:\fR If a macro is actually used, but only used in skipped
conditional blocks, then \s-1CPP\s0 will report it as unused. To avoid the
warning in such a case, you might improve the scope of the macro's
definition by, for example, moving it into the first skipped block.
@@ -4702,8 +6184,6 @@ This implies that the choice of angle brackets or double quotes in an
\&\fB#include\fR directive does not in itself determine whether that
header will appear in \fB\-MM\fR dependency output. This is a
slight change in semantics from \s-1GCC\s0 versions 3.0 and earlier.
-.Sp
-@anchor{dashMF}
.IP "\fB\-MF\fR \fIfile\fR" 4
.IX Item "-MF file"
When used with \fB\-M\fR or \fB\-MM\fR, specifies a
@@ -4776,8 +6256,7 @@ argument but with a suffix of \fI.d\fR, otherwise it take the
basename of the input file and applies a \fI.d\fR suffix.
.Sp
If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any
-\&\fB\-o\fR switch is understood to specify the dependency output file
-(but \f(CW@pxref\fR{dashMF,,\-MF}), but if used without \fB\-E\fR, each \fB\-o\fR
+\&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR
is understood to specify a target object file.
.Sp
Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate
@@ -4785,7 +6264,7 @@ a dependency output file as a side-effect of the compilation process.
.IP "\fB\-MMD\fR" 4
.IX Item "-MMD"
Like \fB\-MD\fR except mention only user header files, not system
-\&\-header files.
+header files.
.IP "\fB\-fpch\-deps\fR" 4
.IX Item "-fpch-deps"
When using precompiled headers, this flag
@@ -4794,6 +6273,22 @@ precompiled header's dependencies. If not specified only the
precompiled header would be listed and not the files that were used to
create it because those files are not consulted when a precompiled
header is used.
+.IP "\fB\-fpch\-preprocess\fR" 4
+.IX Item "-fpch-preprocess"
+This option allows use of a precompiled header together with \fB\-E\fR. It inserts a special \f(CW\*(C`#pragma\*(C'\fR,
+\&\f(CW\*(C`#pragma GCC pch_preprocess "<filename>"\*(C'\fR in the output to mark
+the place where the precompiled header was found, and its filename. When
+\&\fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#pragma\*(C'\fR and
+loads the \s-1PCH\s0.
+.Sp
+This option is off by default, because the resulting preprocessed output
+is only really suitable as input to \s-1GCC\s0. It is switched on by
+\&\fB\-save\-temps\fR.
+.Sp
+You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is
+safe to edit the filename if the \s-1PCH\s0 file is available in a different
+location. The filename may be absolute or it may be relative to \s-1GCC\s0's
+current directory.
.IP "\fB\-x c\fR" 4
.IX Item "-x c"
.PD 0
@@ -4813,7 +6308,7 @@ extensions for \*(C+ and assembly are also recognized. If cpp does not
recognize the extension, it will treat the file as C; this is the most
generic mode.
.Sp
-\&\fBNote:\fR Previous versions of cpp accepted a \fB\-lang\fR option
+\&\fINote:\fR Previous versions of cpp accepted a \fB\-lang\fR option
which selected both the language and the standards conformance level.
This option has been removed, because it conflicts with the \fB\-l\fR
option.
@@ -4897,6 +6392,7 @@ directories are searched for all \fB#include\fR directives.
.Sp
In addition, \fB\-I\-\fR inhibits the use of the directory of the current
file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR.
+This option has been deprecated.
.IP "\fB\-nostdinc\fR" 4
.IX Item "-nostdinc"
Do not search the standard system directories for header files.
@@ -4947,16 +6443,34 @@ Append \fIdir\fR to the prefix specified previously with
\&\fB\-iprefix\fR, and add the resulting directory to the include search
path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR
would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would.
+.IP "\fB\-isysroot\fR \fIdir\fR" 4
+.IX Item "-isysroot dir"
+This option is like the \fB\-\-sysroot\fR option, but applies only to
+header files. See the \fB\-\-sysroot\fR option for more information.
+.IP "\fB\-imultilib\fR \fIdir\fR" 4
+.IX Item "-imultilib dir"
+Use \fIdir\fR as a subdirectory of the directory containing
+target-specific \*(C+ headers.
.IP "\fB\-isystem\fR \fIdir\fR" 4
.IX Item "-isystem dir"
Search \fIdir\fR for header files, after all directories specified by
\&\fB\-I\fR but before the standard system directories. Mark it
as a system directory, so that it gets the same special treatment as
is applied to the standard system directories.
+.IP "\fB\-iquote\fR \fIdir\fR" 4
+.IX Item "-iquote dir"
+Search \fIdir\fR only for header files requested with
+\&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for
+\&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR, before all directories specified by
+\&\fB\-I\fR and before the standard system directories.
.IP "\fB\-fdollars\-in\-identifiers\fR" 4
.IX Item "-fdollars-in-identifiers"
-@anchor{fdollars\-in\-identifiers}
Accept \fB$\fR in identifiers.
+.IP "\fB\-fextended\-identifiers\fR" 4
+.IX Item "-fextended-identifiers"
+Accept universal character names in identifiers. This option is
+experimental; in a future version of \s-1GCC\s0, it will be enabled by
+default for C99 and \*(C+.
.IP "\fB\-fpreprocessed\fR" 4
.IX Item "-fpreprocessed"
Indicate to the preprocessor that the input file has already been
@@ -4987,17 +6501,17 @@ supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine.
Set the wide execution character set, used for wide string and
character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever
corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with
-\&\fB\-ftarget\-charset\fR, \fIcharset\fR can be any encoding supported
+\&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported
by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have
problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR.
.IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4
.IX Item "-finput-charset=charset"
Set the input character set, used for translation from the character
-set of the input file to the source character set used by \s-1GCC\s0. If the
+set of the input file to the source character set used by \s-1GCC\s0. If the
locale does not specify, or \s-1GCC\s0 cannot get this information from the
-locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale
-or this command line option. Currently the command line option takes
-precedence if there's a conflict. \fIcharset\fR can be any encoding
+locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale
+or this command line option. Currently the command line option takes
+precedence if there's a conflict. \fIcharset\fR can be any encoding
supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine.
.IP "\fB\-fworking\-directory\fR" 4
.IX Item "-fworking-directory"
@@ -5217,7 +6731,7 @@ and searches several directories.
.IP "\fB\-lobjc\fR" 4
.IX Item "-lobjc"
You need this special case of the \fB\-l\fR option in order to
-link an Objective-C program.
+link an Objective-C or Objective\-\*(C+ program.
.IP "\fB\-nostartfiles\fR" 4
.IX Item "-nostartfiles"
Do not use the standard system startup files when linking.
@@ -5228,18 +6742,18 @@ or \fB\-nodefaultlibs\fR is used.
Do not use the standard system libraries when linking.
Only the libraries you specify will be passed to the linker.
The standard startup files are used normally, unless \fB\-nostartfiles\fR
-is used. The compiler may generate calls to memcmp, memset, and memcpy
-for System V (and \s-1ISO\s0 C) environments or to bcopy and bzero for
-\&\s-1BSD\s0 environments. These entries are usually resolved by entries in
+is used. The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR,
+\&\f(CW\*(C`memset\*(C'\fR, \f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR.
+These entries are usually resolved by entries in
libc. These entry points should be supplied through some other
mechanism when this option is specified.
.IP "\fB\-nostdlib\fR" 4
.IX Item "-nostdlib"
Do not use the standard system startup files or libraries when linking.
No startup files and only the libraries you specify will be passed to
-the linker. The compiler may generate calls to memcmp, memset, and memcpy
-for System V (and \s-1ISO\s0 C) environments or to bcopy and bzero for
-\&\s-1BSD\s0 environments. These entries are usually resolved by entries in
+the linker. The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, \f(CW\*(C`memset\*(C'\fR,
+\&\f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR.
+These entries are usually resolved by entries in
libc. These entry points should be supplied through some other
mechanism when this option is specified.
.Sp
@@ -5260,6 +6774,13 @@ Produce a position independent executable on targets which support it.
For predictable results, you must also specify the same set of options
that were used to generate code (\fB\-fpie\fR, \fB\-fPIE\fR,
or model suboptions) when you specify this option.
+.IP "\fB\-rdynamic\fR" 4
+.IX Item "-rdynamic"
+Pass the flag \fB\-export\-dynamic\fR to the \s-1ELF\s0 linker, on targets
+that support it. This instructs the linker to add all symbols, not
+only used ones, to the dynamic symbol table. This option is needed
+for some uses of \f(CW\*(C`dlopen\*(C'\fR or to allow obtaining backtraces
+from within a program.
.IP "\fB\-s\fR" 4
.IX Item "-s"
Remove all symbol table and relocation information from the executable.
@@ -5362,28 +6883,12 @@ This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and
the ordering for the include_next directive are not inadvertently changed.
If you really need to change the search order for system directories,
use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options.
-.IP "\fB\-I\-\fR" 4
-.IX Item "-I-"
-Any directories you specify with \fB\-I\fR options before the \fB\-I\-\fR
-option are searched only for the case of \fB#include "\fR\fIfile\fR\fB"\fR;
-they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR.
-.Sp
-If additional directories are specified with \fB\-I\fR options after
-the \fB\-I\-\fR, these directories are searched for all \fB#include\fR
-directives. (Ordinarily \fIall\fR \fB\-I\fR directories are used
-this way.)
-.Sp
-In addition, the \fB\-I\-\fR option inhibits the use of the current
-directory (where the current input file came from) as the first search
-directory for \fB#include "\fR\fIfile\fR\fB"\fR. There is no way to
-override this effect of \fB\-I\-\fR. With \fB\-I.\fR you can specify
-searching the directory which was current when the compiler was
-invoked. That is not exactly the same as what the preprocessor does
-by default, but it is often satisfactory.
-.Sp
-\&\fB\-I\-\fR does not inhibit the use of the standard system directories
-for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are
-independent.
+.IP "\fB\-iquote\fR\fIdir\fR" 4
+.IX Item "-iquotedir"
+Add the directory \fIdir\fR to the head of the list of directories to
+be searched for header files only for the case of \fB#include
+"\fR\fIfile\fR\fB"\fR; they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR,
+otherwise just like \fB\-I\fR.
.IP "\fB\-L\fR\fIdir\fR" 4
.IX Item "-Ldir"
Add directory \fIdir\fR to the list of directories to be searched
@@ -5437,6 +6942,45 @@ program uses when determining what switches to pass to \fIcc1\fR,
\&\fIcc1plus\fR, \fIas\fR, \fIld\fR, etc. More than one
\&\fB\-specs=\fR\fIfile\fR can be specified on the command line, and they
are processed in order, from left to right.
+.IP "\fB\-\-sysroot=\fR\fIdir\fR" 4
+.IX Item "--sysroot=dir"
+Use \fIdir\fR as the logical root directory for headers and libraries.
+For example, if the compiler would normally search for headers in
+\&\fI/usr/include\fR and libraries in \fI/usr/lib\fR, it will instead
+search \fI\fIdir\fI/usr/include\fR and \fI\fIdir\fI/usr/lib\fR.
+.Sp
+If you use both this option and the \fB\-isysroot\fR option, then
+the \fB\-\-sysroot\fR option will apply to libraries, but the
+\&\fB\-isysroot\fR option will apply to header files.
+.Sp
+The \s-1GNU\s0 linker (beginning with version 2.16) has the necessary support
+for this option. If your linker does not support this option, the
+header file aspect of \fB\-\-sysroot\fR will still work, but the
+library aspect will not.
+.IP "\fB\-I\-\fR" 4
+.IX Item "-I-"
+This option has been deprecated. Please use \fB\-iquote\fR instead for
+\&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR.
+Any directories you specify with \fB\-I\fR options before the \fB\-I\-\fR
+option are searched only for the case of \fB#include "\fR\fIfile\fR\fB"\fR;
+they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR.
+.Sp
+If additional directories are specified with \fB\-I\fR options after
+the \fB\-I\-\fR, these directories are searched for all \fB#include\fR
+directives. (Ordinarily \fIall\fR \fB\-I\fR directories are used
+this way.)
+.Sp
+In addition, the \fB\-I\-\fR option inhibits the use of the current
+directory (where the current input file came from) as the first search
+directory for \fB#include "\fR\fIfile\fR\fB"\fR. There is no way to
+override this effect of \fB\-I\-\fR. With \fB\-I.\fR you can specify
+searching the directory which was current when the compiler was
+invoked. That is not exactly the same as what the preprocessor does
+by default, but it is often satisfactory.
+.Sp
+\&\fB\-I\-\fR does not inhibit the use of the standard system directories
+for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are
+independent.
.Sh "Specifying Target Machine and Compiler Version"
.IX Subsection "Specifying Target Machine and Compiler Version"
The usual way to run \s-1GCC\s0 is to run the executable called \fIgcc\fR, or
@@ -5451,13 +6995,15 @@ The argument \fImachine\fR specifies the target machine for compilation.
The value to use for \fImachine\fR is the same as was specified as the
machine type when configuring \s-1GCC\s0 as a cross\-compiler. For
example, if a cross-compiler was configured with \fBconfigure
-i386v\fR, meaning to compile for an 80386 running System V, then you
-would specify \fB\-b i386v\fR to run that cross compiler.
+arm-elf\fR, meaning to compile for an arm processor with elf binaries,
+then you would specify \fB\-b arm-elf\fR to run that cross compiler.
+Because there are other options beginning with \fB\-b\fR, the
+configuration must contain a hyphen.
.IP "\fB\-V\fR \fIversion\fR" 4
.IX Item "-V version"
The argument \fIversion\fR specifies which version of \s-1GCC\s0 to run.
This is useful when multiple versions are installed. For example,
-\&\fIversion\fR might be \fB2.0\fR, meaning to run \s-1GCC\s0 version 2.0.
+\&\fIversion\fR might be \fB4.0\fR, meaning to run \s-1GCC\s0 version 4.0.
.PP
The \fB\-V\fR and \fB\-b\fR options work by running the
\&\fI<machine>\-gcc\-<version>\fR executable, so there's no real reason to
@@ -5479,565 +7025,50 @@ Some configurations of the compiler also support additional special
options, usually for compatibility with other compilers on the same
platform.
.PP
-These options are defined by the macro \f(CW\*(C`TARGET_SWITCHES\*(C'\fR in the
-machine description. The default for the options is also defined by
-that macro, which enables you to change the defaults.
-.PP
-\fIM680x0 Options\fR
-.IX Subsection "M680x0 Options"
-.PP
-These are the \fB\-m\fR options defined for the 68000 series. The default
-values for these options depends on which style of 68000 was selected when
-the compiler was configured; the defaults for the most common choices are
-given below.
-.IP "\fB\-m68000\fR" 4
-.IX Item "-m68000"
-.PD 0
-.IP "\fB\-mc68000\fR" 4
-.IX Item "-mc68000"
-.PD
-Generate output for a 68000. This is the default
-when the compiler is configured for 68000\-based systems.
-.Sp
-Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core,
-including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
-.IP "\fB\-m68020\fR" 4
-.IX Item "-m68020"
-.PD 0
-.IP "\fB\-mc68020\fR" 4
-.IX Item "-mc68020"
-.PD
-Generate output for a 68020. This is the default
-when the compiler is configured for 68020\-based systems.
-.IP "\fB\-m68881\fR" 4
-.IX Item "-m68881"
-Generate output containing 68881 instructions for floating point.
-This is the default for most 68020 systems unless \fB\-\-nfp\fR was
-specified when the compiler was configured.
-.IP "\fB\-m68030\fR" 4
-.IX Item "-m68030"
-Generate output for a 68030. This is the default when the compiler is
-configured for 68030\-based systems.
-.IP "\fB\-m68040\fR" 4
-.IX Item "-m68040"
-Generate output for a 68040. This is the default when the compiler is
-configured for 68040\-based systems.
-.Sp
-This option inhibits the use of 68881/68882 instructions that have to be
-emulated by software on the 68040. Use this option if your 68040 does not
-have code to emulate those instructions.
-.IP "\fB\-m68060\fR" 4
-.IX Item "-m68060"
-Generate output for a 68060. This is the default when the compiler is
-configured for 68060\-based systems.
-.Sp
-This option inhibits the use of 68020 and 68881/68882 instructions that
-have to be emulated by software on the 68060. Use this option if your 68060
-does not have code to emulate those instructions.
-.IP "\fB\-mcpu32\fR" 4
-.IX Item "-mcpu32"
-Generate output for a \s-1CPU32\s0. This is the default
-when the compiler is configured for CPU32\-based systems.
-.Sp
-Use this option for microcontrollers with a
-\&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334,
-68336, 68340, 68341, 68349 and 68360.
-.IP "\fB\-m5200\fR" 4
-.IX Item "-m5200"
-Generate output for a 520X ``coldfire'' family cpu. This is the default
-when the compiler is configured for 520X\-based systems.
-.Sp
-Use this option for microcontroller with a 5200 core, including
-the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5202\s0.
-.IP "\fB\-m68020\-40\fR" 4
-.IX Item "-m68020-40"
-Generate output for a 68040, without using any of the new instructions.
-This results in code which can run relatively efficiently on either a
-68020/68881 or a 68030 or a 68040. The generated code does use the
-68881 instructions that are emulated on the 68040.
-.IP "\fB\-m68020\-60\fR" 4
-.IX Item "-m68020-60"
-Generate output for a 68060, without using any of the new instructions.
-This results in code which can run relatively efficiently on either a
-68020/68881 or a 68030 or a 68040. The generated code does use the
-68881 instructions that are emulated on the 68060.
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-Generate output containing library calls for floating point.
-\&\fBWarning:\fR the requisite libraries are not available for all m68k
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this can't be done directly in cross\-compilation. You must
-make your own arrangements to provide suitable library functions for
-cross\-compilation. The embedded targets \fBm68k\-*\-aout\fR and
-\&\fBm68k\-*\-coff\fR do provide software floating point support.
-.IP "\fB\-mshort\fR" 4
-.IX Item "-mshort"
-Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
-.IP "\fB\-mnobitfield\fR" 4
-.IX Item "-mnobitfield"
-Do not use the bit-field instructions. The \fB\-m68000\fR, \fB\-mcpu32\fR
-and \fB\-m5200\fR options imply \fB\-mnobitfield\fR.
-.IP "\fB\-mbitfield\fR" 4
-.IX Item "-mbitfield"
-Do use the bit-field instructions. The \fB\-m68020\fR option implies
-\&\fB\-mbitfield\fR. This is the default if you use a configuration
-designed for a 68020.
-.IP "\fB\-mrtd\fR" 4
-.IX Item "-mrtd"
-Use a different function-calling convention, in which functions
-that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR
-instruction, which pops their arguments while returning. This
-saves one instruction in the caller since there is no need to pop
-the arguments there.
-.Sp
-This calling convention is incompatible with the one normally
-used on Unix, so you cannot use it if you need to call libraries
-compiled with the Unix compiler.
-.Sp
-Also, you must provide function prototypes for all functions that
-take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
-otherwise incorrect code will be generated for calls to those
-functions.
-.Sp
-In addition, seriously incorrect code will result if you call a
-function with too many arguments. (Normally, extra arguments are
-harmlessly ignored.)
-.Sp
-The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030,
-68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200.
-.IP "\fB\-malign\-int\fR" 4
-.IX Item "-malign-int"
-.PD 0
-.IP "\fB\-mno\-align\-int\fR" 4
-.IX Item "-mno-align-int"
-.PD
-Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR,
-\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit
-boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR).
-Aligning variables on 32\-bit boundaries produces code that runs somewhat
-faster on processors with 32\-bit busses at the expense of more memory.
-.Sp
-\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 will
-align structures containing the above types differently than
-most published application binary interface specifications for the m68k.
-.IP "\fB\-mpcrel\fR" 4
-.IX Item "-mpcrel"
-Use the pc-relative addressing mode of the 68000 directly, instead of
-using a global offset table. At present, this option implies \fB\-fpic\fR,
-allowing at most a 16\-bit offset for pc-relative addressing. \fB\-fPIC\fR is
-not presently supported with \fB\-mpcrel\fR, though this could be supported for
-68020 and higher processors.
-.IP "\fB\-mno\-strict\-align\fR" 4
-.IX Item "-mno-strict-align"
-.PD 0
-.IP "\fB\-mstrict\-align\fR" 4
-.IX Item "-mstrict-align"
-.PD
-Do not (do) assume that unaligned memory references will be handled by
-the system.
-.IP "\fB\-msep\-data\fR" 4
-.IX Item "-msep-data"
-Generate code that allows the data segment to be located in a different
-area of memory from the text segment. This allows for execute in place in
-an environment without virtual memory management. This option implies \-fPIC.
-.IP "\fB\-mno\-sep\-data\fR" 4
-.IX Item "-mno-sep-data"
-Generate code that assumes that the data segment follows the text segment.
-This is the default.
-.IP "\fB\-mid\-shared\-library\fR" 4
-.IX Item "-mid-shared-library"
-Generate code that supports shared libraries via the library \s-1ID\s0 method.
-This allows for execute in place and shared libraries in an environment
-without virtual memory management. This option implies \-fPIC.
-.IP "\fB\-mno\-id\-shared\-library\fR" 4
-.IX Item "-mno-id-shared-library"
-Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
-This is the default.
-.IP "\fB\-mshared\-library\-id=n\fR" 4
-.IX Item "-mshared-library-id=n"
-Specified the identification number of the \s-1ID\s0 based shared library being
-compiled. Specifying a value of 0 will generate more compact code, specifying
-other values will force the allocation of that number to the current
-library but is no more space or time efficient than omitting this option.
-.PP
-\fIM68hc1x Options\fR
-.IX Subsection "M68hc1x Options"
-.PP
-These are the \fB\-m\fR options defined for the 68hc11 and 68hc12
-microcontrollers. The default values for these options depends on
-which style of microcontroller was selected when the compiler was configured;
-the defaults for the most common choices are given below.
-.IP "\fB\-m6811\fR" 4
-.IX Item "-m6811"
-.PD 0
-.IP "\fB\-m68hc11\fR" 4
-.IX Item "-m68hc11"
-.PD
-Generate output for a 68HC11. This is the default
-when the compiler is configured for 68HC11\-based systems.
-.IP "\fB\-m6812\fR" 4
-.IX Item "-m6812"
-.PD 0
-.IP "\fB\-m68hc12\fR" 4
-.IX Item "-m68hc12"
-.PD
-Generate output for a 68HC12. This is the default
-when the compiler is configured for 68HC12\-based systems.
-.IP "\fB\-m68S12\fR" 4
-.IX Item "-m68S12"
-.PD 0
-.IP "\fB\-m68hcs12\fR" 4
-.IX Item "-m68hcs12"
-.PD
-Generate output for a 68HCS12.
-.IP "\fB\-mauto\-incdec\fR" 4
-.IX Item "-mauto-incdec"
-Enable the use of 68HC12 pre and post auto-increment and auto-decrement
-addressing modes.
-.IP "\fB\-minmax\fR" 4
-.IX Item "-minmax"
-.PD 0
-.IP "\fB\-nominmax\fR" 4
-.IX Item "-nominmax"
-.PD
-Enable the use of 68HC12 min and max instructions.
-.IP "\fB\-mlong\-calls\fR" 4
-.IX Item "-mlong-calls"
-.PD 0
-.IP "\fB\-mno\-long\-calls\fR" 4
-.IX Item "-mno-long-calls"
-.PD
-Treat all calls as being far away (near). If calls are assumed to be
-far away, the compiler will use the \f(CW\*(C`call\*(C'\fR instruction to
-call a function and the \f(CW\*(C`rtc\*(C'\fR instruction for returning.
-.IP "\fB\-mshort\fR" 4
-.IX Item "-mshort"
-Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
-.IP "\fB\-msoft\-reg\-count=\fR\fIcount\fR" 4
-.IX Item "-msoft-reg-count=count"
-Specify the number of pseudo-soft registers which are used for the
-code generation. The maximum number is 32. Using more pseudo-soft
-register may or may not result in better code depending on the program.
-The default is 4 for 68HC11 and 2 for 68HC12.
-.PP
-\fI\s-1VAX\s0 Options\fR
-.IX Subsection "VAX Options"
-.PP
-These \fB\-m\fR options are defined for the \s-1VAX:\s0
-.IP "\fB\-munix\fR" 4
-.IX Item "-munix"
-Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on)
-that the Unix assembler for the \s-1VAX\s0 cannot handle across long
-ranges.
-.IP "\fB\-mgnu\fR" 4
-.IX Item "-mgnu"
-Do output those jump instructions, on the assumption that you
-will assemble with the \s-1GNU\s0 assembler.
-.IP "\fB\-mg\fR" 4
-.IX Item "-mg"
-Output code for g\-format floating point numbers instead of d\-format.
-.PP
-\fI\s-1SPARC\s0 Options\fR
-.IX Subsection "SPARC Options"
-.PP
-These \fB\-m\fR options are supported on the \s-1SPARC:\s0
-.IP "\fB\-mno\-app\-regs\fR" 4
-.IX Item "-mno-app-regs"
-.PD 0
-.IP "\fB\-mapp\-regs\fR" 4
-.IX Item "-mapp-regs"
-.PD
-Specify \fB\-mapp\-regs\fR to generate output using the global registers
-2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This
-is the default, except on Solaris.
-.Sp
-To be fully \s-1SVR4\s0 \s-1ABI\s0 compliant at the cost of some performance loss,
-specify \fB\-mno\-app\-regs\fR. You should compile libraries and system
-software with this option.
-.IP "\fB\-mfpu\fR" 4
-.IX Item "-mfpu"
-.PD 0
-.IP "\fB\-mhard\-float\fR" 4
-.IX Item "-mhard-float"
-.PD
-Generate output containing floating point instructions. This is the
-default.
-.IP "\fB\-mno\-fpu\fR" 4
-.IX Item "-mno-fpu"
-.PD 0
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-.PD
-Generate output containing library calls for floating point.
-\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross\-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross\-compilation. The embedded targets \fBsparc\-*\-aout\fR and
-\&\fBsparclite\-*\-*\fR do provide software floating point support.
-.Sp
-\&\fB\-msoft\-float\fR changes the calling convention in the output file;
-therefore, it is only useful if you compile \fIall\fR of a program with
-this option. In particular, you need to compile \fIlibgcc.a\fR, the
-library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for
-this to work.
-.IP "\fB\-mhard\-quad\-float\fR" 4
-.IX Item "-mhard-quad-float"
-Generate output containing quad-word (long double) floating point
-instructions.
-.IP "\fB\-msoft\-quad\-float\fR" 4
-.IX Item "-msoft-quad-float"
-Generate output containing library calls for quad-word (long double)
-floating point instructions. The functions called are those specified
-in the \s-1SPARC\s0 \s-1ABI\s0. This is the default.
-.Sp
-As of this writing, there are no \s-1SPARC\s0 implementations that have hardware
-support for the quad-word floating point instructions. They all invoke
-a trap handler for one of these instructions, and then the trap handler
-emulates the effect of the instruction. Because of the trap handler overhead,
-this is much slower than calling the \s-1ABI\s0 library routines. Thus the
-\&\fB\-msoft\-quad\-float\fR option is the default.
-.IP "\fB\-mno\-flat\fR" 4
-.IX Item "-mno-flat"
-.PD 0
-.IP "\fB\-mflat\fR" 4
-.IX Item "-mflat"
-.PD
-With \fB\-mflat\fR, the compiler does not generate save/restore instructions
-and will use a ``flat'' or single register window calling convention.
-This model uses \f(CW%i7\fR as the frame pointer and is compatible with the normal
-register window model. Code from either may be intermixed.
-The local registers and the input registers (0\-\-5) are still treated as
-``call saved'' registers and will be saved on the stack as necessary.
-.Sp
-With \fB\-mno\-flat\fR (the default), the compiler emits save/restore
-instructions (except for leaf functions) and is the normal mode of operation.
-.Sp
-These options are deprecated and will be deleted in a future \s-1GCC\s0 release.
-.IP "\fB\-mno\-unaligned\-doubles\fR" 4
-.IX Item "-mno-unaligned-doubles"
-.PD 0
-.IP "\fB\-munaligned\-doubles\fR" 4
-.IX Item "-munaligned-doubles"
-.PD
-Assume that doubles have 8 byte alignment. This is the default.
-.Sp
-With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8 byte
-alignment only if they are contained in another type, or if they have an
-absolute address. Otherwise, it assumes they have 4 byte alignment.
-Specifying this option avoids some rare compatibility problems with code
-generated by other compilers. It is not the default because it results
-in a performance loss, especially for floating point code.
-.IP "\fB\-mno\-faster\-structs\fR" 4
-.IX Item "-mno-faster-structs"
-.PD 0
-.IP "\fB\-mfaster\-structs\fR" 4
-.IX Item "-mfaster-structs"
-.PD
-With \fB\-mfaster\-structs\fR, the compiler assumes that structures
-should have 8 byte alignment. This enables the use of pairs of
-\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure
-assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs.
-However, the use of this changed alignment directly violates the \s-1SPARC\s0
-\&\s-1ABI\s0. Thus, it's intended only for use on targets where the developer
-acknowledges that their resulting code will not be directly in line with
-the rules of the \s-1ABI\s0.
-.IP "\fB\-mimpure\-text\fR" 4
-.IX Item "-mimpure-text"
-\&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells
-the compiler to not pass \fB\-z text\fR to the linker when linking a
-shared object. Using this option, you can link position-dependent
-code into a shared object.
-.Sp
-\&\fB\-mimpure\-text\fR suppresses the ``relocations remain against
-allocatable but non-writable sections'' linker error message.
-However, the necessary relocations will trigger copy\-on\-write, and the
-shared object is not actually shared across processes. Instead of
-using \fB\-mimpure\-text\fR, you should compile all source code with
-\&\fB\-fpic\fR or \fB\-fPIC\fR.
-.Sp
-This option is only available on SunOS and Solaris.
-.IP "\fB\-mv8\fR" 4
-.IX Item "-mv8"
-.PD 0
-.IP "\fB\-msparclite\fR" 4
-.IX Item "-msparclite"
-.PD
-These two options select variations on the \s-1SPARC\s0 architecture.
-These options are deprecated and will be deleted in a future \s-1GCC\s0 release.
-They have been replaced with \fB\-mcpu=xxx\fR.
-.IP "\fB\-mcypress\fR" 4
-.IX Item "-mcypress"
-.PD 0
-.IP "\fB\-msupersparc\fR" 4
-.IX Item "-msupersparc"
-.IP "\fB\-mf930\fR" 4
-.IX Item "-mf930"
-.IP "\fB\-mf934\fR" 4
-.IX Item "-mf934"
-.PD
-These four options select the processor for which the code is optimized.
-These options are deprecated and will be deleted in a future \s-1GCC\s0 release.
-They have been replaced with \fB\-mcpu=xxx\fR.
-.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
-.IX Item "-mcpu=cpu_type"
-Set the instruction set, register set, and instruction scheduling parameters
-for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are
-\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBsparclite\fR,
-\&\fBf930\fR, \fBf934\fR, \fBhypersparc\fR, \fBsparclite86x\fR,
-\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, and
-\&\fBultrasparc3\fR.
-.Sp
-Default instruction scheduling parameters are used for values that select
-an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR,
-\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR.
-.Sp
-Here is a list of each supported architecture and their supported
-implementations.
-.Sp
-.Vb 5
-\& v7: cypress
-\& v8: supersparc, hypersparc
-\& sparclite: f930, f934, sparclite86x
-\& sparclet: tsc701
-\& v9: ultrasparc, ultrasparc3
-.Ve
-.Sp
-By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7
-variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler
-additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the
-SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
-SPARCStation 1, 2, \s-1IPX\s0 etc.
-.Sp
-With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0
-architecture. The only difference from V7 code is that the compiler emits
-the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0
-but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=supersparc\fR, the compiler additionally
-optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
-2000 series.
-.Sp
-With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of
-the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step
-and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7\s0.
-With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the
-Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU\s0. With
-\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu
-\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU\s0.
-.Sp
-With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of
-the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate,
-integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet
-but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=tsc701\fR, the compiler additionally
-optimizes it for the \s-1TEMIC\s0 SPARClet chip.
-.Sp
-With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0
-architecture. This adds 64\-bit integer and floating-point move instructions,
-3 additional floating-point condition code registers and conditional move
-instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally
-optimizes it for the Sun UltraSPARC I/II chips. With
-\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the
-Sun UltraSPARC \s-1III\s0 chip.
-.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
-.IX Item "-mtune=cpu_type"
-Set the instruction scheduling parameters for machine type
-\&\fIcpu_type\fR, but do not set the instruction set or register set that the
-option \fB\-mcpu=\fR\fIcpu_type\fR would.
-.Sp
-The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for
-\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those
-that select a particular cpu implementation. Those are \fBcypress\fR,
-\&\fBsupersparc\fR, \fBhypersparc\fR, \fBf930\fR, \fBf934\fR,
-\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, and
-\&\fBultrasparc3\fR.
-.IP "\fB\-mv8plus\fR" 4
-.IX Item "-mv8plus"
-.PD 0
-.IP "\fB\-mno\-v8plus\fR" 4
-.IX Item "-mno-v8plus"
-.PD
-With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+\s0 \s-1ABI\s0. The
-difference from the V8 \s-1ABI\s0 is that the global and out registers are
-considered 64\-bit wide. This is enabled by default on Solaris in 32\-bit
-mode for all \s-1SPARC\-V9\s0 processors.
-.IP "\fB\-mvis\fR" 4
-.IX Item "-mvis"
-.PD 0
-.IP "\fB\-mno\-vis\fR" 4
-.IX Item "-mno-vis"
-.PD
-With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC
-Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR.
+\fI\s-1ARC\s0 Options\fR
+.IX Subsection "ARC Options"
.PP
-These \fB\-m\fR options are supported in addition to the above
-on \s-1SPARC\-V9\s0 processors in 64\-bit environments:
-.IP "\fB\-mlittle\-endian\fR" 4
-.IX Item "-mlittle-endian"
-Generate code for a processor running in little-endian mode. It is only
-available for a few configurations and most notably not on Solaris and Linux.
-.IP "\fB\-m32\fR" 4
-.IX Item "-m32"
-.PD 0
-.IP "\fB\-m64\fR" 4
-.IX Item "-m64"
-.PD
-Generate code for a 32\-bit or 64\-bit environment.
-The 32\-bit environment sets int, long and pointer to 32 bits.
-The 64\-bit environment sets int to 32 bits and long and pointer
-to 64 bits.
-.IP "\fB\-mcmodel=medlow\fR" 4
-.IX Item "-mcmodel=medlow"
-Generate code for the Medium/Low code model: 64\-bit addresses, programs
-must be linked in the low 32 bits of memory. Programs can be statically
-or dynamically linked.
-.IP "\fB\-mcmodel=medmid\fR" 4
-.IX Item "-mcmodel=medmid"
-Generate code for the Medium/Middle code model: 64\-bit addresses, programs
-must be linked in the low 44 bits of memory, the text and data segments must
-be less than 2GB in size and the data segment must be located within 2GB of
-the text segment.
-.IP "\fB\-mcmodel=medany\fR" 4
-.IX Item "-mcmodel=medany"
-Generate code for the Medium/Anywhere code model: 64\-bit addresses, programs
-may be linked anywhere in memory, the text and data segments must be less
-than 2GB in size and the data segment must be located within 2GB of the
-text segment.
-.IP "\fB\-mcmodel=embmedany\fR" 4
-.IX Item "-mcmodel=embmedany"
-Generate code for the Medium/Anywhere code model for embedded systems:
-64\-bit addresses, the text and data segments must be less than 2GB in
-size, both starting anywhere in memory (determined at link time). The
-global register \f(CW%g4\fR points to the base of the data segment. Programs
-are statically linked and \s-1PIC\s0 is not supported.
-.IP "\fB\-mstack\-bias\fR" 4
-.IX Item "-mstack-bias"
+These options are defined for \s-1ARC\s0 implementations:
+.IP "\fB\-EL\fR" 4
+.IX Item "-EL"
+Compile code for little endian mode. This is the default.
+.IP "\fB\-EB\fR" 4
+.IX Item "-EB"
+Compile code for big endian mode.
+.IP "\fB\-mmangle\-cpu\fR" 4
+.IX Item "-mmangle-cpu"
+Prepend the name of the cpu to all public symbol names.
+In multiple-processor systems, there are many \s-1ARC\s0 variants with different
+instruction and register set characteristics. This flag prevents code
+compiled for one cpu to be linked with code compiled for another.
+No facility exists for handling variants that are \*(L"almost identical\*(R".
+This is an all or nothing option.
+.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
+.IX Item "-mcpu=cpu"
+Compile code for \s-1ARC\s0 variant \fIcpu\fR.
+Which variants are supported depend on the configuration.
+All variants support \fB\-mcpu=base\fR, this is the default.
+.IP "\fB\-mtext=\fR\fItext-section\fR" 4
+.IX Item "-mtext=text-section"
.PD 0
-.IP "\fB\-mno\-stack\-bias\fR" 4
-.IX Item "-mno-stack-bias"
+.IP "\fB\-mdata=\fR\fIdata-section\fR" 4
+.IX Item "-mdata=data-section"
+.IP "\fB\-mrodata=\fR\fIreadonly-data-section\fR" 4
+.IX Item "-mrodata=readonly-data-section"
.PD
-With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and
-frame pointer if present, are offset by \-2047 which must be added back
-when making stack frame references. This is the default in 64\-bit mode.
-Otherwise, assume no such offset is present.
-.PP
-These switches are supported in addition to the above on Solaris:
-.IP "\fB\-threads\fR" 4
-.IX Item "-threads"
-Add support for multithreading using the Solaris threads library. This
-option sets flags for both the preprocessor and linker. This option does
-not affect the thread safety of object code produced by the compiler or
-that of libraries supplied with it.
-.IP "\fB\-pthreads\fR" 4
-.IX Item "-pthreads"
-Add support for multithreading using the \s-1POSIX\s0 threads library. This
-option sets flags for both the preprocessor and linker. This option does
-not affect the thread safety of object code produced by the compiler or
-that of libraries supplied with it.
+Put functions, data, and readonly data in \fItext-section\fR,
+\&\fIdata-section\fR, and \fIreadonly-data-section\fR respectively
+by default. This can be overridden with the \f(CW\*(C`section\*(C'\fR attribute.
.PP
\fI\s-1ARM\s0 Options\fR
.IX Subsection "ARM Options"
.PP
These \fB\-m\fR options are defined for Advanced \s-1RISC\s0 Machines (\s-1ARM\s0)
architectures:
+.IP "\fB\-mabi=\fR\fIname\fR" 4
+.IX Item "-mabi=name"
+Generate code for the specified \s-1ABI\s0. Permissible values are: \fBapcs-gnu\fR,
+\&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR.
.IP "\fB\-mapcs\-frame\fR" 4
.IX Item "-mapcs-frame"
Generate a stack frame that is compliant with the \s-1ARM\s0 Procedure Call
@@ -6048,22 +7079,6 @@ leaf functions. The default is \fB\-mno\-apcs\-frame\fR.
.IP "\fB\-mapcs\fR" 4
.IX Item "-mapcs"
This is a synonym for \fB\-mapcs\-frame\fR.
-.IP "\fB\-mapcs\-26\fR" 4
-.IX Item "-mapcs-26"
-Generate code for a processor running with a 26\-bit program counter,
-and conforming to the function calling standards for the \s-1APCS\s0 26\-bit
-option.
-.Sp
-This option is deprecated. Future releases of the \s-1GCC\s0 will only support
-generating code that runs in apcs\-32 mode.
-.IP "\fB\-mapcs\-32\fR" 4
-.IX Item "-mapcs-32"
-Generate code for a processor running with a 32\-bit program counter,
-and conforming to the function calling standards for the \s-1APCS\s0 32\-bit
-option.
-.Sp
-This flag is deprecated. Future releases of \s-1GCC\s0 will make this flag
-unconditional.
.IP "\fB\-mthumb\-interwork\fR" 4
.IX Item "-mthumb-interwork"
Generate code which supports calling between the \s-1ARM\s0 and Thumb
@@ -6098,6 +7113,15 @@ therefore, it is only useful if you compile \fIall\fR of a program with
this option. In particular, you need to compile \fIlibgcc.a\fR, the
library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for
this to work.
+.IP "\fB\-mfloat\-abi=\fR\fIname\fR" 4
+.IX Item "-mfloat-abi=name"
+Specifies which \s-1ABI\s0 to use for floating point values. Permissible values
+are: \fBsoft\fR, \fBsoftfp\fR and \fBhard\fR.
+.Sp
+\&\fBsoft\fR and \fBhard\fR are equivalent to \fB\-msoft\-float\fR
+and \fB\-mhard\-float\fR respectively. \fBsoftfp\fR allows the generation
+of floating point instructions, but still uses the soft-float calling
+conventions.
.IP "\fB\-mlittle\-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a processor running in little-endian mode. This is
@@ -6114,38 +7138,6 @@ order. That is, a byte order of the form \fB32107654\fR. Note: this
option should only be used if you require compatibility with code for
big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to
2.8.
-.IP "\fB\-malignment\-traps\fR" 4
-.IX Item "-malignment-traps"
-Generate code that will not trap if the \s-1MMU\s0 has alignment traps enabled.
-On \s-1ARM\s0 architectures prior to ARMv4, there were no instructions to
-access half-word objects stored in memory. However, when reading from
-memory a feature of the \s-1ARM\s0 architecture allows a word load to be used,
-even if the address is unaligned, and the processor core will rotate the
-data as it is being loaded. This option tells the compiler that such
-misaligned accesses will cause a \s-1MMU\s0 trap and that it should instead
-synthesize the access as a series of byte accesses. The compiler can
-still use word accesses to load half-word data if it knows that the
-address is aligned to a word boundary.
-.Sp
-This option has no effect when compiling for \s-1ARM\s0 architecture 4 or later,
-since these processors have instructions to directly access half-word
-objects in memory.
-.IP "\fB\-mno\-alignment\-traps\fR" 4
-.IX Item "-mno-alignment-traps"
-Generate code that assumes that the \s-1MMU\s0 will not trap unaligned
-accesses. This produces better code when the target instruction set
-does not have half-word memory operations (i.e. implementations prior to
-ARMv4).
-.Sp
-Note that you cannot use this option to access unaligned word objects,
-since the processor will only fetch one 32\-bit aligned object from
-memory.
-.Sp
-The default setting is \fB\-malignment\-traps\fR, since this produces
-code that will also run on processors implementing \s-1ARM\s0 architecture
-version 6 or later.
-.Sp
-This option is deprecated and will be removed in the next release of \s-1GCC\s0.
.IP "\fB\-mcpu=\fR\fIname\fR" 4
.IX Item "-mcpu=name"
This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name
@@ -6155,12 +7147,15 @@ assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR,
\&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR,
\&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR,
\&\fBarm700i\fR, \fBarm710\fR, \fBarm710c\fR, \fBarm7100\fR,
-\&\fBarm7500\fR, \fBarm7500fe\fR, \fBarm7tdmi\fR, \fBarm8\fR,
-\&\fBstrongarm\fR, \fBstrongarm110\fR, \fBstrongarm1100\fR,
+\&\fBarm7500\fR, \fBarm7500fe\fR, \fBarm7tdmi\fR, \fBarm7tdmi\-s\fR,
+\&\fBarm8\fR, \fBstrongarm\fR, \fBstrongarm110\fR, \fBstrongarm1100\fR,
\&\fBarm8\fR, \fBarm810\fR, \fBarm9\fR, \fBarm9e\fR, \fBarm920\fR,
-\&\fBarm920t\fR, \fBarm926ejs\fR, \fBarm940t\fR, \fBarm9tdmi\fR,
-\&\fBarm10tdmi\fR, \fBarm1020t\fR, \fBarm1026ejs\fR,
-\&\fBarm1136js\fR, \fBarm1136jfs\fR ,\fBxscale\fR, \fBiwmmxt\fR,
+\&\fBarm920t\fR, \fBarm922t\fR, \fBarm946e\-s\fR, \fBarm966e\-s\fR,
+\&\fBarm968e\-s\fR, \fBarm926ej\-s\fR, \fBarm940t\fR, \fBarm9tdmi\fR,
+\&\fBarm10tdmi\fR, \fBarm1020t\fR, \fBarm1026ej\-s\fR,
+\&\fBarm10e\fR, \fBarm1020e\fR, \fBarm1022e\fR,
+\&\fBarm1136j\-s\fR, \fBarm1136jf\-s\fR, \fBmpcore\fR, \fBmpcorenovfp\fR,
+\&\fBarm1176jz\-s\fR, \fBarm1176jzf\-s\fR, \fBxscale\fR, \fBiwmmxt\fR,
\&\fBep9312\fR.
.IP "\fB\-mtune=\fR\fIname\fR" 4
.IX Item "-mtune=name"
@@ -6179,28 +7174,37 @@ name to determine what kind of instructions it can emit when generating
assembly code. This option can be used in conjunction with or instead
of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR,
\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR,
-\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5te\fR, \fBarmv6j\fR,
+\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5te\fR, \fBarmv6\fR, \fBarmv6j\fR,
\&\fBiwmmxt\fR, \fBep9312\fR.
+.IP "\fB\-mfpu=\fR\fIname\fR" 4
+.IX Item "-mfpu=name"
+.PD 0
.IP "\fB\-mfpe=\fR\fInumber\fR" 4
.IX Item "-mfpe=number"
-.PD 0
.IP "\fB\-mfp=\fR\fInumber\fR" 4
.IX Item "-mfp=number"
.PD
-This specifies the version of the floating point emulation available on
-the target. Permissible values are 2 and 3. \fB\-mfp=\fR is a synonym
-for \fB\-mfpe=\fR, for compatibility with older versions of \s-1GCC\s0.
+This specifies what floating point hardware (or hardware emulation) is
+available on the target. Permissible names are: \fBfpa\fR, \fBfpe2\fR,
+\&\fBfpe3\fR, \fBmaverick\fR, \fBvfp\fR. \fB\-mfp\fR and \fB\-mfpe\fR
+are synonyms for \fB\-mfpu\fR=\fBfpe\fR\fInumber\fR, for compatibility
+with older versions of \s-1GCC\s0.
+.Sp
+If \fB\-msoft\-float\fR is specified this specifies the format of
+floating point values.
.IP "\fB\-mstructure\-size\-boundary=\fR\fIn\fR" 4
.IX Item "-mstructure-size-boundary=n"
The size of all structures and unions will be rounded up to a multiple
-of the number of bits set by this option. Permissible values are 8 and
-32. The default value varies for different toolchains. For the \s-1COFF\s0
-targeted toolchain the default value is 8. Specifying the larger number
-can produce faster, more efficient code, but can also increase the size
-of the program. The two values are potentially incompatible. Code
-compiled with one value cannot necessarily expect to work with code or
-libraries compiled with the other value, if they exchange information
-using structures or unions.
+of the number of bits set by this option. Permissible values are 8, 32
+and 64. The default value varies for different toolchains. For the \s-1COFF\s0
+targeted toolchain the default value is 8. A value of 64 is only allowed
+if the underlying \s-1ABI\s0 supports it.
+.Sp
+Specifying the larger number can produce faster, more efficient code, but
+can also increase the size of the program. Different values are potentially
+incompatible. Code compiled with one value cannot necessarily expect to
+work with code or libraries compiled with another value, if they exchange
+information using structures or unions.
.IP "\fB\-mabort\-on\-noreturn\fR" 4
.IX Item "-mabort-on-noreturn"
Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a
@@ -6306,36 +7310,2145 @@ Allows calls via function pointers (including virtual functions) to
execute correctly regardless of whether the target code has been
compiled for interworking or not. There is a small overhead in the cost
of executing a function pointer if this option is enabled.
+.IP "\fB\-mtp=\fR\fIname\fR" 4
+.IX Item "-mtp=name"
+Specify the access model for the thread local storage pointer. The valid
+models are \fBsoft\fR, which generates calls to \f(CW\*(C`_\|_aeabi_read_tp\*(C'\fR,
+\&\fBcp15\fR, which fetches the thread pointer from \f(CW\*(C`cp15\*(C'\fR directly
+(supported in the arm6k architecture), and \fBauto\fR, which uses the
+best available method for the selected processor. The default setting is
+\&\fBauto\fR.
.PP
-\fI\s-1MN10300\s0 Options\fR
-.IX Subsection "MN10300 Options"
+\fI\s-1AVR\s0 Options\fR
+.IX Subsection "AVR Options"
.PP
-These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures:
-.IP "\fB\-mmult\-bug\fR" 4
-.IX Item "-mmult-bug"
-Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0
-processors. This is the default.
-.IP "\fB\-mno\-mult\-bug\fR" 4
-.IX Item "-mno-mult-bug"
-Do not generate code to avoid bugs in the multiply instructions for the
-\&\s-1MN10300\s0 processors.
-.IP "\fB\-mam33\fR" 4
-.IX Item "-mam33"
-Generate code which uses features specific to the \s-1AM33\s0 processor.
-.IP "\fB\-mno\-am33\fR" 4
-.IX Item "-mno-am33"
-Do not generate code which uses features specific to the \s-1AM33\s0 processor. This
-is the default.
-.IP "\fB\-mno\-crt0\fR" 4
-.IX Item "-mno-crt0"
-Do not link in the C run-time initialization object file.
+These options are defined for \s-1AVR\s0 implementations:
+.IP "\fB\-mmcu=\fR\fImcu\fR" 4
+.IX Item "-mmcu=mcu"
+Specify \s-1ATMEL\s0 \s-1AVR\s0 instruction set or \s-1MCU\s0 type.
+.Sp
+Instruction set avr1 is for the minimal \s-1AVR\s0 core, not supported by the C
+compiler, only for assembler programs (\s-1MCU\s0 types: at90s1200, attiny10,
+attiny11, attiny12, attiny15, attiny28).
+.Sp
+Instruction set avr2 (default) is for the classic \s-1AVR\s0 core with up to
+8K program memory space (\s-1MCU\s0 types: at90s2313, at90s2323, attiny22,
+at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
+at90c8534, at90s8535).
+.Sp
+Instruction set avr3 is for the classic \s-1AVR\s0 core with up to 128K program
+memory space (\s-1MCU\s0 types: atmega103, atmega603, at43usb320, at76c711).
+.Sp
+Instruction set avr4 is for the enhanced \s-1AVR\s0 core with up to 8K program
+memory space (\s-1MCU\s0 types: atmega8, atmega83, atmega85).
+.Sp
+Instruction set avr5 is for the enhanced \s-1AVR\s0 core with up to 128K program
+memory space (\s-1MCU\s0 types: atmega16, atmega161, atmega163, atmega32, atmega323,
+atmega64, atmega128, at43usb355, at94k).
+.IP "\fB\-msize\fR" 4
+.IX Item "-msize"
+Output instruction sizes to the asm file.
+.IP "\fB\-minit\-stack=\fR\fIN\fR" 4
+.IX Item "-minit-stack=N"
+Specify the initial stack address, which may be a symbol or numeric value,
+\&\fB_\|_stack\fR is the default.
+.IP "\fB\-mno\-interrupts\fR" 4
+.IX Item "-mno-interrupts"
+Generated code is not compatible with hardware interrupts.
+Code size will be smaller.
+.IP "\fB\-mcall\-prologues\fR" 4
+.IX Item "-mcall-prologues"
+Functions prologues/epilogues expanded as call to appropriate
+subroutines. Code size will be smaller.
+.IP "\fB\-mno\-tablejump\fR" 4
+.IX Item "-mno-tablejump"
+Do not generate tablejump insns which sometimes increase code size.
+.IP "\fB\-mtiny\-stack\fR" 4
+.IX Item "-mtiny-stack"
+Change only the low 8 bits of the stack pointer.
+.IP "\fB\-mint8\fR" 4
+.IX Item "-mint8"
+Assume int to be 8 bit integer. This affects the sizes of all types: A
+char will be 1 byte, an int will be 1 byte, an long will be 2 bytes
+and long long will be 4 bytes. Please note that this option does not
+comply to the C standards, but it will provide you with smaller code
+size.
+.PP
+\fIBlackfin Options\fR
+.IX Subsection "Blackfin Options"
+.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4
+.IX Item "-momit-leaf-frame-pointer"
+Don't keep the frame pointer in a register for leaf functions. This
+avoids the instructions to save, set up and restore frame pointers and
+makes an extra register available in leaf functions. The option
+\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions
+which might make debugging harder.
+.IP "\fB\-mspecld\-anomaly\fR" 4
+.IX Item "-mspecld-anomaly"
+When enabled, the compiler will ensure that the generated code does not
+contain speculative loads after jump instructions. This option is enabled
+by default.
+.IP "\fB\-mno\-specld\-anomaly\fR" 4
+.IX Item "-mno-specld-anomaly"
+Don't generate extra code to prevent speculative loads from occurring.
+.IP "\fB\-mcsync\-anomaly\fR" 4
+.IX Item "-mcsync-anomaly"
+When enabled, the compiler will ensure that the generated code does not
+contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches.
+This option is enabled by default.
+.IP "\fB\-mno\-csync\-anomaly\fR" 4
+.IX Item "-mno-csync-anomaly"
+Don't generate extra code to prevent \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions from
+occurring too soon after a conditional branch.
+.IP "\fB\-mlow\-64k\fR" 4
+.IX Item "-mlow-64k"
+When enabled, the compiler is free to take advantage of the knowledge that
+the entire program fits into the low 64k of memory.
+.IP "\fB\-mno\-low\-64k\fR" 4
+.IX Item "-mno-low-64k"
+Assume that the program is arbitrarily large. This is the default.
+.IP "\fB\-mid\-shared\-library\fR" 4
+.IX Item "-mid-shared-library"
+Generate code that supports shared libraries via the library \s-1ID\s0 method.
+This allows for execute in place and shared libraries in an environment
+without virtual memory management. This option implies \fB\-fPIC\fR.
+.IP "\fB\-mno\-id\-shared\-library\fR" 4
+.IX Item "-mno-id-shared-library"
+Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
+This is the default.
+.IP "\fB\-mshared\-library\-id=n\fR" 4
+.IX Item "-mshared-library-id=n"
+Specified the identification number of the \s-1ID\s0 based shared library being
+compiled. Specifying a value of 0 will generate more compact code, specifying
+other values will force the allocation of that number to the current
+library but is no more space or time efficient than omitting this option.
+.IP "\fB\-mlong\-calls\fR" 4
+.IX Item "-mlong-calls"
+.PD 0
+.IP "\fB\-mno\-long\-calls\fR" 4
+.IX Item "-mno-long-calls"
+.PD
+Tells the compiler to perform function calls by first loading the
+address of the function into a register and then performing a subroutine
+call on this register. This switch is needed if the target function
+will lie outside of the 24 bit addressing range of the offset based
+version of subroutine call instruction.
+.Sp
+This feature is not enabled by default. Specifying
+\&\fB\-mno\-long\-calls\fR will restore the default behavior. Note these
+switches have no effect on how the compiler generates code to handle
+function calls via function pointers.
+.PP
+\fI\s-1CRIS\s0 Options\fR
+.IX Subsection "CRIS Options"
+.PP
+These options are defined specifically for the \s-1CRIS\s0 ports.
+.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4
+.IX Item "-march=architecture-type"
+.PD 0
+.IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4
+.IX Item "-mcpu=architecture-type"
+.PD
+Generate code for the specified architecture. The choices for
+\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for
+respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0.
+Default is \fBv0\fR except for cris\-axis\-linux\-gnu, where the default is
+\&\fBv10\fR.
+.IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4
+.IX Item "-mtune=architecture-type"
+Tune to \fIarchitecture-type\fR everything applicable about the generated
+code, except for the \s-1ABI\s0 and the set of available instructions. The
+choices for \fIarchitecture-type\fR are the same as for
+\&\fB\-march=\fR\fIarchitecture-type\fR.
+.IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4
+.IX Item "-mmax-stack-frame=n"
+Warn when the stack frame of a function exceeds \fIn\fR bytes.
+.IP "\fB\-melinux\-stacksize=\fR\fIn\fR" 4
+.IX Item "-melinux-stacksize=n"
+Only available with the \fBcris-axis-aout\fR target. Arranges for
+indications in the program to the kernel loader that the stack of the
+program should be set to \fIn\fR bytes.
+.IP "\fB\-metrax4\fR" 4
+.IX Item "-metrax4"
+.PD 0
+.IP "\fB\-metrax100\fR" 4
+.IX Item "-metrax100"
+.PD
+The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for
+\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively.
+.IP "\fB\-mmul\-bug\-workaround\fR" 4
+.IX Item "-mmul-bug-workaround"
+.PD 0
+.IP "\fB\-mno\-mul\-bug\-workaround\fR" 4
+.IX Item "-mno-mul-bug-workaround"
+.PD
+Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0
+models where it applies. This option is active by default.
+.IP "\fB\-mpdebug\fR" 4
+.IX Item "-mpdebug"
+Enable CRIS-specific verbose debug-related information in the assembly
+code. This option also has the effect to turn off the \fB#NO_APP\fR
+formatted-code indicator to the assembler at the beginning of the
+assembly file.
+.IP "\fB\-mcc\-init\fR" 4
+.IX Item "-mcc-init"
+Do not use condition-code results from previous instruction; always emit
+compare and test instructions before use of condition codes.
+.IP "\fB\-mno\-side\-effects\fR" 4
+.IX Item "-mno-side-effects"
+Do not emit instructions with side-effects in addressing modes other than
+post\-increment.
+.IP "\fB\-mstack\-align\fR" 4
+.IX Item "-mstack-align"
+.PD 0
+.IP "\fB\-mno\-stack\-align\fR" 4
+.IX Item "-mno-stack-align"
+.IP "\fB\-mdata\-align\fR" 4
+.IX Item "-mdata-align"
+.IP "\fB\-mno\-data\-align\fR" 4
+.IX Item "-mno-data-align"
+.IP "\fB\-mconst\-align\fR" 4
+.IX Item "-mconst-align"
+.IP "\fB\-mno\-const\-align\fR" 4
+.IX Item "-mno-const-align"
+.PD
+These options (no\-options) arranges (eliminate arrangements) for the
+stack\-frame, individual data and constants to be aligned for the maximum
+single data access size for the chosen \s-1CPU\s0 model. The default is to
+arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are
+not affected by these options.
+.IP "\fB\-m32\-bit\fR" 4
+.IX Item "-m32-bit"
+.PD 0
+.IP "\fB\-m16\-bit\fR" 4
+.IX Item "-m16-bit"
+.IP "\fB\-m8\-bit\fR" 4
+.IX Item "-m8-bit"
+.PD
+Similar to the stack\- data\- and const-align options above, these options
+arrange for stack\-frame, writable data and constants to all be 32\-bit,
+16\-bit or 8\-bit aligned. The default is 32\-bit alignment.
+.IP "\fB\-mno\-prologue\-epilogue\fR" 4
+.IX Item "-mno-prologue-epilogue"
+.PD 0
+.IP "\fB\-mprologue\-epilogue\fR" 4
+.IX Item "-mprologue-epilogue"
+.PD
+With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and
+epilogue that sets up the stack-frame are omitted and no return
+instructions or return sequences are generated in the code. Use this
+option only together with visual inspection of the compiled code: no
+warnings or errors are generated when call-saved registers must be saved,
+or storage for local variable needs to be allocated.
+.IP "\fB\-mno\-gotplt\fR" 4
+.IX Item "-mno-gotplt"
+.PD 0
+.IP "\fB\-mgotplt\fR" 4
+.IX Item "-mgotplt"
+.PD
+With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate)
+instruction sequences that load addresses for functions from the \s-1PLT\s0 part
+of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the
+\&\s-1PLT\s0. The default is \fB\-mgotplt\fR.
+.IP "\fB\-maout\fR" 4
+.IX Item "-maout"
+Legacy no-op option only recognized with the cris-axis-aout target.
+.IP "\fB\-melf\fR" 4
+.IX Item "-melf"
+Legacy no-op option only recognized with the cris-axis-elf and
+cris-axis-linux-gnu targets.
+.IP "\fB\-melinux\fR" 4
+.IX Item "-melinux"
+Only recognized with the cris-axis-aout target, where it selects a
+GNU/linux\-like multilib, include files and instruction set for
+\&\fB\-march=v8\fR.
+.IP "\fB\-mlinux\fR" 4
+.IX Item "-mlinux"
+Legacy no-op option only recognized with the cris-axis-linux-gnu target.
+.IP "\fB\-sim\fR" 4
+.IX Item "-sim"
+This option, recognized for the cris-axis-aout and cris-axis-elf arranges
+to link with input-output functions from a simulator library. Code,
+initialized data and zero-initialized data are allocated consecutively.
+.IP "\fB\-sim2\fR" 4
+.IX Item "-sim2"
+Like \fB\-sim\fR, but pass linker options to locate initialized data at
+0x40000000 and zero-initialized data at 0x80000000.
+.PP
+\fI\s-1CRX\s0 Options\fR
+.IX Subsection "CRX Options"
+.PP
+These options are defined specifically for the \s-1CRX\s0 ports.
+.IP "\fB\-mmac\fR" 4
+.IX Item "-mmac"
+Enable the use of multiply-accumulate instructions. Disabled by default.
+.IP "\fB\-mpush\-args\fR" 4
+.IX Item "-mpush-args"
+Push instructions will be used to pass outgoing arguments when functions
+are called. Enabled by default.
+.PP
+\fIDarwin Options\fR
+.IX Subsection "Darwin Options"
+.PP
+These options are defined for all architectures running the Darwin operating
+system.
+.PP
+\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it will create
+an object file for the single architecture that it was built to
+target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple
+\&\fB\-arch\fR options are used; it does so by running the compiler or
+linker multiple times and joining the results together with
+\&\fIlipo\fR.
+.PP
+The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or
+\&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0
+that \s-1GCC\s0 is targetting, like \fB\-mcpu\fR or \fB\-march\fR. The
+\&\fB\-force_cpusubtype_ALL\fR option can be used to override this.
+.PP
+The Darwin tools vary in their behavior when presented with an \s-1ISA\s0
+mismatch. The assembler, \fIas\fR, will only permit instructions to
+be used that are valid for the subtype of the file it is generating,
+so you cannot put 64\-bit instructions in an \fBppc750\fR object file.
+The linker for shared libraries, \fI/usr/bin/libtool\fR, will fail
+and print an error if asked to create a shared library with a less
+restrictive subtype than its input files (for instance, trying to put
+a \fBppc970\fR object file in a \fBppc7400\fR library). The linker
+for executables, \fIld\fR, will quietly give the executable the most
+restrictive subtype of any of its input files.
+.IP "\fB\-F\fR\fIdir\fR" 4
+.IX Item "-Fdir"
+Add the framework directory \fIdir\fR to the head of the list of
+directories to be searched for header files. These directories are
+interleaved with those specified by \fB\-I\fR options and are
+scanned in a left-to-right order.
+.Sp
+A framework directory is a directory with frameworks in it. A
+framework is a directory with a \fB\*(L"Headers\*(R"\fR and/or
+\&\fB\*(L"PrivateHeaders\*(R"\fR directory contained directly in it that ends
+in \fB\*(L".framework\*(R"\fR. The name of a framework is the name of this
+directory excluding the \fB\*(L".framework\*(R"\fR. Headers associated with
+the framework are found in one of those two directories, with
+\&\fB\*(L"Headers\*(R"\fR being searched first. A subframework is a framework
+directory that is in a framework's \fB\*(L"Frameworks\*(R"\fR directory.
+Includes of subframework headers can only appear in a header of a
+framework that contains the subframework, or in a sibling subframework
+header. Two subframeworks are siblings if they occur in the same
+framework. A subframework should not have the same name as a
+framework, a warning will be issued if this is violated. Currently a
+subframework cannot have subframeworks, in the future, the mechanism
+may be extended to support this. The standard frameworks can be found
+in \fB\*(L"/System/Library/Frameworks\*(R"\fR and
+\&\fB\*(L"/Library/Frameworks\*(R"\fR. An example include looks like
+\&\f(CW\*(C`#include <Framework/header.h>\*(C'\fR, where \fBFramework\fR denotes
+the name of the framework and header.h is found in the
+\&\fB\*(L"PrivateHeaders\*(R"\fR or \fB\*(L"Headers\*(R"\fR directory.
+.IP "\fB\-gused\fR" 4
+.IX Item "-gused"
+Emit debugging information for symbols that are used. For \s-1STABS\s0
+debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR.
+This is by default \s-1ON\s0.
+.IP "\fB\-gfull\fR" 4
+.IX Item "-gfull"
+Emit debugging information for all symbols and types.
+.IP "\fB\-mmacosx\-version\-min=\fR\fIversion\fR" 4
+.IX Item "-mmacosx-version-min=version"
+The earliest version of MacOS X that this executable will run on
+is \fIversion\fR. Typical values of \fIversion\fR include \f(CW10.1\fR,
+\&\f(CW10.2\fR, and \f(CW10.3.9\fR.
+.Sp
+The default for this option is to make choices that seem to be most
+useful.
+.IP "\fB\-mkernel\fR" 4
+.IX Item "-mkernel"
+Enable kernel development mode. The \fB\-mkernel\fR option sets
+\&\fB\-static\fR, \fB\-fno\-common\fR, \fB\-fno\-cxa\-atexit\fR,
+\&\fB\-fno\-exceptions\fR, \fB\-fno\-non\-call\-exceptions\fR,
+\&\fB\-fapple\-kext\fR, \fB\-fno\-weak\fR and \fB\-fno\-rtti\fR where
+applicable. This mode also sets \fB\-mno\-altivec\fR,
+\&\fB\-msoft\-float\fR, \fB\-fno\-builtin\fR and
+\&\fB\-mlong\-branch\fR for PowerPC targets.
+.IP "\fB\-mone\-byte\-bool\fR" 4
+.IX Item "-mone-byte-bool"
+Override the defaults for \fBbool\fR so that \fBsizeof(bool)==1\fR.
+By default \fBsizeof(bool)\fR is \fB4\fR when compiling for
+Darwin/PowerPC and \fB1\fR when compiling for Darwin/x86, so this
+option has no effect on x86.
+.Sp
+\&\fBWarning:\fR The \fB\-mone\-byte\-bool\fR switch causes \s-1GCC\s0
+to generate code that is not binary compatible with code generated
+without that switch. Using this switch may require recompiling all
+other modules in a program, including system libraries. Use this
+switch to conform to a non-default data model.
+.IP "\fB\-mfix\-and\-continue\fR" 4
+.IX Item "-mfix-and-continue"
+.PD 0
+.IP "\fB\-ffix\-and\-continue\fR" 4
+.IX Item "-ffix-and-continue"
+.IP "\fB\-findirect\-data\fR" 4
+.IX Item "-findirect-data"
+.PD
+Generate code suitable for fast turn around development. Needed to
+enable gdb to dynamically load \f(CW\*(C`.o\*(C'\fR files into already running
+programs. \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR
+are provided for backwards compatibility.
+.IP "\fB\-all_load\fR" 4
+.IX Item "-all_load"
+Loads all members of static archive libraries.
+See man \fIld\fR\|(1) for more information.
+.IP "\fB\-arch_errors_fatal\fR" 4
+.IX Item "-arch_errors_fatal"
+Cause the errors having to do with files that have the wrong architecture
+to be fatal.
+.IP "\fB\-bind_at_load\fR" 4
+.IX Item "-bind_at_load"
+Causes the output file to be marked such that the dynamic linker will
+bind all undefined references when the file is loaded or launched.
+.IP "\fB\-bundle\fR" 4
+.IX Item "-bundle"
+Produce a Mach-o bundle format file.
+See man \fIld\fR\|(1) for more information.
+.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4
+.IX Item "-bundle_loader executable"
+This option specifies the \fIexecutable\fR that will be loading the build
+output file being linked. See man \fIld\fR\|(1) for more information.
+.IP "\fB\-dynamiclib\fR" 4
+.IX Item "-dynamiclib"
+When passed this option, \s-1GCC\s0 will produce a dynamic library instead of
+an executable when linking, using the Darwin \fIlibtool\fR command.
+.IP "\fB\-force_cpusubtype_ALL\fR" 4
+.IX Item "-force_cpusubtype_ALL"
+This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of
+one controlled by the \fB\-mcpu\fR or \fB\-march\fR option.
+.IP "\fB\-allowable_client\fR \fIclient_name\fR" 4
+.IX Item "-allowable_client client_name"
+.PD 0
+.IP "\fB\-client_name\fR" 4
+.IX Item "-client_name"
+.IP "\fB\-compatibility_version\fR" 4
+.IX Item "-compatibility_version"
+.IP "\fB\-current_version\fR" 4
+.IX Item "-current_version"
+.IP "\fB\-dead_strip\fR" 4
+.IX Item "-dead_strip"
+.IP "\fB\-dependency\-file\fR" 4
+.IX Item "-dependency-file"
+.IP "\fB\-dylib_file\fR" 4
+.IX Item "-dylib_file"
+.IP "\fB\-dylinker_install_name\fR" 4
+.IX Item "-dylinker_install_name"
+.IP "\fB\-dynamic\fR" 4
+.IX Item "-dynamic"
+.IP "\fB\-exported_symbols_list\fR" 4
+.IX Item "-exported_symbols_list"
+.IP "\fB\-filelist\fR" 4
+.IX Item "-filelist"
+.IP "\fB\-flat_namespace\fR" 4
+.IX Item "-flat_namespace"
+.IP "\fB\-force_flat_namespace\fR" 4
+.IX Item "-force_flat_namespace"
+.IP "\fB\-headerpad_max_install_names\fR" 4
+.IX Item "-headerpad_max_install_names"
+.IP "\fB\-image_base\fR" 4
+.IX Item "-image_base"
+.IP "\fB\-init\fR" 4
+.IX Item "-init"
+.IP "\fB\-install_name\fR" 4
+.IX Item "-install_name"
+.IP "\fB\-keep_private_externs\fR" 4
+.IX Item "-keep_private_externs"
+.IP "\fB\-multi_module\fR" 4
+.IX Item "-multi_module"
+.IP "\fB\-multiply_defined\fR" 4
+.IX Item "-multiply_defined"
+.IP "\fB\-multiply_defined_unused\fR" 4
+.IX Item "-multiply_defined_unused"
+.IP "\fB\-noall_load\fR" 4
+.IX Item "-noall_load"
+.IP "\fB\-no_dead_strip_inits_and_terms\fR" 4
+.IX Item "-no_dead_strip_inits_and_terms"
+.IP "\fB\-nofixprebinding\fR" 4
+.IX Item "-nofixprebinding"
+.IP "\fB\-nomultidefs\fR" 4
+.IX Item "-nomultidefs"
+.IP "\fB\-noprebind\fR" 4
+.IX Item "-noprebind"
+.IP "\fB\-noseglinkedit\fR" 4
+.IX Item "-noseglinkedit"
+.IP "\fB\-pagezero_size\fR" 4
+.IX Item "-pagezero_size"
+.IP "\fB\-prebind\fR" 4
+.IX Item "-prebind"
+.IP "\fB\-prebind_all_twolevel_modules\fR" 4
+.IX Item "-prebind_all_twolevel_modules"
+.IP "\fB\-private_bundle\fR" 4
+.IX Item "-private_bundle"
+.IP "\fB\-read_only_relocs\fR" 4
+.IX Item "-read_only_relocs"
+.IP "\fB\-sectalign\fR" 4
+.IX Item "-sectalign"
+.IP "\fB\-sectobjectsymbols\fR" 4
+.IX Item "-sectobjectsymbols"
+.IP "\fB\-whyload\fR" 4
+.IX Item "-whyload"
+.IP "\fB\-seg1addr\fR" 4
+.IX Item "-seg1addr"
+.IP "\fB\-sectcreate\fR" 4
+.IX Item "-sectcreate"
+.IP "\fB\-sectobjectsymbols\fR" 4
+.IX Item "-sectobjectsymbols"
+.IP "\fB\-sectorder\fR" 4
+.IX Item "-sectorder"
+.IP "\fB\-segaddr\fR" 4
+.IX Item "-segaddr"
+.IP "\fB\-segs_read_only_addr\fR" 4
+.IX Item "-segs_read_only_addr"
+.IP "\fB\-segs_read_write_addr\fR" 4
+.IX Item "-segs_read_write_addr"
+.IP "\fB\-seg_addr_table\fR" 4
+.IX Item "-seg_addr_table"
+.IP "\fB\-seg_addr_table_filename\fR" 4
+.IX Item "-seg_addr_table_filename"
+.IP "\fB\-seglinkedit\fR" 4
+.IX Item "-seglinkedit"
+.IP "\fB\-segprot\fR" 4
+.IX Item "-segprot"
+.IP "\fB\-segs_read_only_addr\fR" 4
+.IX Item "-segs_read_only_addr"
+.IP "\fB\-segs_read_write_addr\fR" 4
+.IX Item "-segs_read_write_addr"
+.IP "\fB\-single_module\fR" 4
+.IX Item "-single_module"
+.IP "\fB\-static\fR" 4
+.IX Item "-static"
+.IP "\fB\-sub_library\fR" 4
+.IX Item "-sub_library"
+.IP "\fB\-sub_umbrella\fR" 4
+.IX Item "-sub_umbrella"
+.IP "\fB\-twolevel_namespace\fR" 4
+.IX Item "-twolevel_namespace"
+.IP "\fB\-umbrella\fR" 4
+.IX Item "-umbrella"
+.IP "\fB\-undefined\fR" 4
+.IX Item "-undefined"
+.IP "\fB\-unexported_symbols_list\fR" 4
+.IX Item "-unexported_symbols_list"
+.IP "\fB\-weak_reference_mismatches\fR" 4
+.IX Item "-weak_reference_mismatches"
+.IP "\fB\-whatsloaded\fR" 4
+.IX Item "-whatsloaded"
+.PD
+These options are passed to the Darwin linker. The Darwin linker man page
+describes them in detail.
+.PP
+\fI\s-1DEC\s0 Alpha Options\fR
+.IX Subsection "DEC Alpha Options"
+.PP
+These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations:
+.IP "\fB\-mno\-soft\-float\fR" 4
+.IX Item "-mno-soft-float"
+.PD 0
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+.PD
+Use (do not use) the hardware floating-point instructions for
+floating-point operations. When \fB\-msoft\-float\fR is specified,
+functions in \fIlibgcc.a\fR will be used to perform floating-point
+operations. Unless they are replaced by routines that emulate the
+floating-point operations, or compiled in such a way as to call such
+emulations routines, these routines will issue floating-point
+operations. If you are compiling for an Alpha without floating-point
+operations, you must ensure that the library is built so as not to call
+them.
+.Sp
+Note that Alpha implementations without floating-point operations are
+required to have floating-point registers.
+.IP "\fB\-mfp\-reg\fR" 4
+.IX Item "-mfp-reg"
+.PD 0
+.IP "\fB\-mno\-fp\-regs\fR" 4
+.IX Item "-mno-fp-regs"
+.PD
+Generate code that uses (does not use) the floating-point register set.
+\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR. If the floating-point
+register set is not used, floating point operands are passed in integer
+registers as if they were integers and floating-point results are passed
+in \f(CW$0\fR instead of \f(CW$f0\fR. This is a non-standard calling sequence,
+so any function with a floating-point argument or return value called by code
+compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that
+option.
+.Sp
+A typical use of this option is building a kernel that does not use,
+and hence need not save and restore, any floating-point registers.
+.IP "\fB\-mieee\fR" 4
+.IX Item "-mieee"
+The Alpha architecture implements floating-point hardware optimized for
+maximum performance. It is mostly compliant with the \s-1IEEE\s0 floating
+point standard. However, for full compliance, software assistance is
+required. This option generates code fully \s-1IEEE\s0 compliant code
+\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below).
+If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is
+defined during compilation. The resulting code is less efficient but is
+able to correctly support denormalized numbers and exceptional \s-1IEEE\s0
+values such as not-a-number and plus/minus infinity. Other Alpha
+compilers call this option \fB\-ieee_with_no_inexact\fR.
+.IP "\fB\-mieee\-with\-inexact\fR" 4
+.IX Item "-mieee-with-inexact"
+This is like \fB\-mieee\fR except the generated code also maintains
+the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the
+generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to
+\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor
+macro. On some Alpha implementations the resulting code may execute
+significantly slower than the code generated by default. Since there is
+very little code that depends on the \fIinexact-flag\fR, you should
+normally not specify this option. Other Alpha compilers call this
+option \fB\-ieee_with_inexact\fR.
+.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4
+.IX Item "-mfp-trap-mode=trap-mode"
+This option controls what floating-point related traps are enabled.
+Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR.
+The trap mode can be set to one of four values:
+.RS 4
+.IP "\fBn\fR" 4
+.IX Item "n"
+This is the default (normal) setting. The only traps that are enabled
+are the ones that cannot be disabled in software (e.g., division by zero
+trap).
+.IP "\fBu\fR" 4
+.IX Item "u"
+In addition to the traps enabled by \fBn\fR, underflow traps are enabled
+as well.
+.IP "\fBsu\fR" 4
+.IX Item "su"
+Like \fBu\fR, but the instructions are marked to be safe for software
+completion (see Alpha architecture manual for details).
+.IP "\fBsui\fR" 4
+.IX Item "sui"
+Like \fBsu\fR, but inexact traps are enabled as well.
+.RE
+.RS 4
+.RE
+.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4
+.IX Item "-mfp-rounding-mode=rounding-mode"
+Selects the \s-1IEEE\s0 rounding mode. Other Alpha compilers call this option
+\&\fB\-fprm\fR \fIrounding-mode\fR. The \fIrounding-mode\fR can be one
+of:
+.RS 4
+.IP "\fBn\fR" 4
+.IX Item "n"
+Normal \s-1IEEE\s0 rounding mode. Floating point numbers are rounded towards
+the nearest machine number or towards the even machine number in case
+of a tie.
+.IP "\fBm\fR" 4
+.IX Item "m"
+Round towards minus infinity.
+.IP "\fBc\fR" 4
+.IX Item "c"
+Chopped rounding mode. Floating point numbers are rounded towards zero.
+.IP "\fBd\fR" 4
+.IX Item "d"
+Dynamic rounding mode. A field in the floating point control register
+(\fIfpcr\fR, see Alpha architecture reference manual) controls the
+rounding mode in effect. The C library initializes this register for
+rounding towards plus infinity. Thus, unless your program modifies the
+\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity.
+.RE
+.RS 4
+.RE
+.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4
+.IX Item "-mtrap-precision=trap-precision"
+In the Alpha architecture, floating point traps are imprecise. This
+means without software assistance it is impossible to recover from a
+floating trap and program execution normally needs to be terminated.
+\&\s-1GCC\s0 can generate code that can assist operating system trap handlers
+in determining the exact location that caused a floating point trap.
+Depending on the requirements of an application, different levels of
+precisions can be selected:
+.RS 4
+.IP "\fBp\fR" 4
+.IX Item "p"
+Program precision. This option is the default and means a trap handler
+can only identify which program caused a floating point exception.
+.IP "\fBf\fR" 4
+.IX Item "f"
+Function precision. The trap handler can determine the function that
+caused a floating point exception.
+.IP "\fBi\fR" 4
+.IX Item "i"
+Instruction precision. The trap handler can determine the exact
+instruction that caused a floating point exception.
+.RE
+.RS 4
+.Sp
+Other Alpha compilers provide the equivalent options called
+\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR.
+.RE
+.IP "\fB\-mieee\-conformant\fR" 4
+.IX Item "-mieee-conformant"
+This option marks the generated code as \s-1IEEE\s0 conformant. You must not
+use this option unless you also specify \fB\-mtrap\-precision=i\fR and either
+\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR. Its only effect
+is to emit the line \fB.eflag 48\fR in the function prologue of the
+generated assembly file. Under \s-1DEC\s0 Unix, this has the effect that
+IEEE-conformant math library routines will be linked in.
+.IP "\fB\-mbuild\-constants\fR" 4
+.IX Item "-mbuild-constants"
+Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to
+see if it can construct it from smaller constants in two or three
+instructions. If it cannot, it will output the constant as a literal and
+generate code to load it from the data segment at runtime.
+.Sp
+Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants
+using code, even if it takes more instructions (the maximum is six).
+.Sp
+You would typically use this option to build a shared library dynamic
+loader. Itself a shared library, it must relocate itself in memory
+before it can find the variables and constants in its own data segment.
+.IP "\fB\-malpha\-as\fR" 4
+.IX Item "-malpha-as"
+.PD 0
+.IP "\fB\-mgas\fR" 4
+.IX Item "-mgas"
+.PD
+Select whether to generate code to be assembled by the vendor-supplied
+assembler (\fB\-malpha\-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR.
+.IP "\fB\-mbwx\fR" 4
+.IX Item "-mbwx"
+.PD 0
+.IP "\fB\-mno\-bwx\fR" 4
+.IX Item "-mno-bwx"
+.IP "\fB\-mcix\fR" 4
+.IX Item "-mcix"
+.IP "\fB\-mno\-cix\fR" 4
+.IX Item "-mno-cix"
+.IP "\fB\-mfix\fR" 4
+.IX Item "-mfix"
+.IP "\fB\-mno\-fix\fR" 4
+.IX Item "-mno-fix"
+.IP "\fB\-mmax\fR" 4
+.IX Item "-mmax"
+.IP "\fB\-mno\-max\fR" 4
+.IX Item "-mno-max"
+.PD
+Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0,
+\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction
+sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that
+of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified.
+.IP "\fB\-mfloat\-vax\fR" 4
+.IX Item "-mfloat-vax"
+.PD 0
+.IP "\fB\-mfloat\-ieee\fR" 4
+.IX Item "-mfloat-ieee"
+.PD
+Generate code that uses (does not use) \s-1VAX\s0 F and G floating point
+arithmetic instead of \s-1IEEE\s0 single and double precision.
+.IP "\fB\-mexplicit\-relocs\fR" 4
+.IX Item "-mexplicit-relocs"
+.PD 0
+.IP "\fB\-mno\-explicit\-relocs\fR" 4
+.IX Item "-mno-explicit-relocs"
+.PD
+Older Alpha assemblers provided no way to generate symbol relocations
+except via assembler macros. Use of these macros does not allow
+optimal instruction scheduling. \s-1GNU\s0 binutils as of version 2.12
+supports a new syntax that allows the compiler to explicitly mark
+which relocations should apply to which instructions. This option
+is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of
+the assembler when it is built and sets the default accordingly.
+.IP "\fB\-msmall\-data\fR" 4
+.IX Item "-msmall-data"
+.PD 0
+.IP "\fB\-mlarge\-data\fR" 4
+.IX Item "-mlarge-data"
+.PD
+When \fB\-mexplicit\-relocs\fR is in effect, static data is
+accessed via \fIgp-relative\fR relocations. When \fB\-msmall\-data\fR
+is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR
+(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via
+16\-bit relocations off of the \f(CW$gp\fR register. This limits the
+size of the small data area to 64KB, but allows the variables to be
+directly accessed via a single instruction.
+.Sp
+The default is \fB\-mlarge\-data\fR. With this option the data area
+is limited to just below 2GB. Programs that require more than 2GB of
+data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the
+heap instead of in the program's data segment.
+.Sp
+When generating code for shared libraries, \fB\-fpic\fR implies
+\&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR.
+.IP "\fB\-msmall\-text\fR" 4
+.IX Item "-msmall-text"
+.PD 0
+.IP "\fB\-mlarge\-text\fR" 4
+.IX Item "-mlarge-text"
+.PD
+When \fB\-msmall\-text\fR is used, the compiler assumes that the
+code of the entire program (or shared library) fits in 4MB, and is
+thus reachable with a branch instruction. When \fB\-msmall\-data\fR
+is used, the compiler can assume that all local symbols share the
+same \f(CW$gp\fR value, and thus reduce the number of instructions
+required for a function call from 4 to 1.
+.Sp
+The default is \fB\-mlarge\-text\fR.
+.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
+.IX Item "-mcpu=cpu_type"
+Set the instruction set and instruction scheduling parameters for
+machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR
+style name or the corresponding chip number. \s-1GCC\s0 supports scheduling
+parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will
+choose the default values for the instruction set from the processor
+you specify. If you do not specify a processor type, \s-1GCC\s0 will default
+to the processor on which the compiler was built.
+.Sp
+Supported values for \fIcpu_type\fR are
+.RS 4
+.IP "\fBev4\fR" 4
+.IX Item "ev4"
+.PD 0
+.IP "\fBev45\fR" 4
+.IX Item "ev45"
+.IP "\fB21064\fR" 4
+.IX Item "21064"
+.PD
+Schedules as an \s-1EV4\s0 and has no instruction set extensions.
+.IP "\fBev5\fR" 4
+.IX Item "ev5"
+.PD 0
+.IP "\fB21164\fR" 4
+.IX Item "21164"
+.PD
+Schedules as an \s-1EV5\s0 and has no instruction set extensions.
+.IP "\fBev56\fR" 4
+.IX Item "ev56"
+.PD 0
+.IP "\fB21164a\fR" 4
+.IX Item "21164a"
+.PD
+Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension.
+.IP "\fBpca56\fR" 4
+.IX Item "pca56"
+.PD 0
+.IP "\fB21164pc\fR" 4
+.IX Item "21164pc"
+.IP "\fB21164PC\fR" 4
+.IX Item "21164PC"
+.PD
+Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions.
+.IP "\fBev6\fR" 4
+.IX Item "ev6"
+.PD 0
+.IP "\fB21264\fR" 4
+.IX Item "21264"
+.PD
+Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
+.IP "\fBev67\fR" 4
+.IX Item "ev67"
+.PD 0
+.IP "\fB21264a\fR" 4
+.IX Item "21264a"
+.PD
+Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
+.RE
+.RS 4
+.RE
+.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
+.IX Item "-mtune=cpu_type"
+Set only the instruction scheduling parameters for machine type
+\&\fIcpu_type\fR. The instruction set is not changed.
+.IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4
+.IX Item "-mmemory-latency=time"
+Sets the latency the scheduler should assume for typical memory
+references as seen by the application. This number is highly
+dependent on the memory access patterns used by the application
+and the size of the external cache on the machine.
+.Sp
+Valid options for \fItime\fR are
+.RS 4
+.IP "\fInumber\fR" 4
+.IX Item "number"
+A decimal number representing clock cycles.
+.IP "\fBL1\fR" 4
+.IX Item "L1"
+.PD 0
+.IP "\fBL2\fR" 4
+.IX Item "L2"
+.IP "\fBL3\fR" 4
+.IX Item "L3"
+.IP "\fBmain\fR" 4
+.IX Item "main"
+.PD
+The compiler contains estimates of the number of clock cycles for
+\&\*(L"typical\*(R" \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches
+(also called Dcache, Scache, and Bcache), as well as to main memory.
+Note that L3 is only valid for \s-1EV5\s0.
+.RE
+.RS 4
+.RE
+.PP
+\fI\s-1DEC\s0 Alpha/VMS Options\fR
+.IX Subsection "DEC Alpha/VMS Options"
+.PP
+These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations:
+.IP "\fB\-mvms\-return\-codes\fR" 4
+.IX Item "-mvms-return-codes"
+Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0
+style condition (e.g. error) codes.
+.PP
+\fI\s-1FRV\s0 Options\fR
+.IX Subsection "FRV Options"
+.IP "\fB\-mgpr\-32\fR" 4
+.IX Item "-mgpr-32"
+Only use the first 32 general purpose registers.
+.IP "\fB\-mgpr\-64\fR" 4
+.IX Item "-mgpr-64"
+Use all 64 general purpose registers.
+.IP "\fB\-mfpr\-32\fR" 4
+.IX Item "-mfpr-32"
+Use only the first 32 floating point registers.
+.IP "\fB\-mfpr\-64\fR" 4
+.IX Item "-mfpr-64"
+Use all 64 floating point registers
+.IP "\fB\-mhard\-float\fR" 4
+.IX Item "-mhard-float"
+Use hardware instructions for floating point operations.
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+Use library routines for floating point operations.
+.IP "\fB\-malloc\-cc\fR" 4
+.IX Item "-malloc-cc"
+Dynamically allocate condition code registers.
+.IP "\fB\-mfixed\-cc\fR" 4
+.IX Item "-mfixed-cc"
+Do not try to dynamically allocate condition code registers, only
+use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR.
+.IP "\fB\-mdword\fR" 4
+.IX Item "-mdword"
+Change \s-1ABI\s0 to use double word insns.
+.IP "\fB\-mno\-dword\fR" 4
+.IX Item "-mno-dword"
+Do not use double word instructions.
+.IP "\fB\-mdouble\fR" 4
+.IX Item "-mdouble"
+Use floating point double instructions.
+.IP "\fB\-mno\-double\fR" 4
+.IX Item "-mno-double"
+Do not use floating point double instructions.
+.IP "\fB\-mmedia\fR" 4
+.IX Item "-mmedia"
+Use media instructions.
+.IP "\fB\-mno\-media\fR" 4
+.IX Item "-mno-media"
+Do not use media instructions.
+.IP "\fB\-mmuladd\fR" 4
+.IX Item "-mmuladd"
+Use multiply and add/subtract instructions.
+.IP "\fB\-mno\-muladd\fR" 4
+.IX Item "-mno-muladd"
+Do not use multiply and add/subtract instructions.
+.IP "\fB\-mfdpic\fR" 4
+.IX Item "-mfdpic"
+Select the \s-1FDPIC\s0 \s-1ABI\s0, that uses function descriptors to represent
+pointers to functions. Without any PIC/PIE\-related options, it
+implies \fB\-fPIE\fR. With \fB\-fpic\fR or \fB\-fpie\fR, it
+assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the
+\&\s-1GOT\s0 base address; with \fB\-fPIC\fR or \fB\-fPIE\fR, \s-1GOT\s0 offsets
+are computed with 32 bits.
+.IP "\fB\-minline\-plt\fR" 4
+.IX Item "-minline-plt"
+Enable inlining of \s-1PLT\s0 entries in function calls to functions that are
+not known to bind locally. It has no effect without \fB\-mfdpic\fR.
+It's enabled by default if optimizing for speed and compiling for
+shared libraries (i.e., \fB\-fPIC\fR or \fB\-fpic\fR), or when an
+optimization option such as \fB\-O3\fR or above is present in the
+command line.
+.IP "\fB\-mTLS\fR" 4
+.IX Item "-mTLS"
+Assume a large \s-1TLS\s0 segment when generating thread-local code.
+.IP "\fB\-mtls\fR" 4
+.IX Item "-mtls"
+Do not assume a large \s-1TLS\s0 segment when generating thread-local code.
+.IP "\fB\-mgprel\-ro\fR" 4
+.IX Item "-mgprel-ro"
+Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC\s0 \s-1ABI\s0 for data
+that is known to be in read-only sections. It's enabled by default,
+except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help
+make the global offset table smaller, it trades 1 instruction for 4.
+With \fB\-fPIC\fR or \fB\-fPIE\fR, it trades 3 instructions for 4,
+one of which may be shared by multiple symbols, and it avoids the need
+for a \s-1GOT\s0 entry for the referenced symbol, so it's more likely to be a
+win. If it is not, \fB\-mno\-gprel\-ro\fR can be used to disable it.
+.IP "\fB\-multilib\-library\-pic\fR" 4
+.IX Item "-multilib-library-pic"
+Link with the (library, not \s-1FD\s0) pic libraries. It's implied by
+\&\fB\-mlibrary\-pic\fR, as well as by \fB\-fPIC\fR and
+\&\fB\-fpic\fR without \fB\-mfdpic\fR. You should never have to use
+it explicitly.
+.IP "\fB\-mlinked\-fp\fR" 4
+.IX Item "-mlinked-fp"
+Follow the \s-1EABI\s0 requirement of always creating a frame pointer whenever
+a stack frame is allocated. This option is enabled by default and can
+be disabled with \fB\-mno\-linked\-fp\fR.
+.IP "\fB\-mlong\-calls\fR" 4
+.IX Item "-mlong-calls"
+Use indirect addressing to call functions outside the current
+compilation unit. This allows the functions to be placed anywhere
+within the 32\-bit address space.
+.IP "\fB\-malign\-labels\fR" 4
+.IX Item "-malign-labels"
+Try to align labels to an 8\-byte boundary by inserting nops into the
+previous packet. This option only has an effect when \s-1VLIW\s0 packing
+is enabled. It doesn't create new packets; it merely adds nops to
+existing ones.
+.IP "\fB\-mlibrary\-pic\fR" 4
+.IX Item "-mlibrary-pic"
+Generate position-independent \s-1EABI\s0 code.
+.IP "\fB\-macc\-4\fR" 4
+.IX Item "-macc-4"
+Use only the first four media accumulator registers.
+.IP "\fB\-macc\-8\fR" 4
+.IX Item "-macc-8"
+Use all eight media accumulator registers.
+.IP "\fB\-mpack\fR" 4
+.IX Item "-mpack"
+Pack \s-1VLIW\s0 instructions.
+.IP "\fB\-mno\-pack\fR" 4
+.IX Item "-mno-pack"
+Do not pack \s-1VLIW\s0 instructions.
+.IP "\fB\-mno\-eflags\fR" 4
+.IX Item "-mno-eflags"
+Do not mark \s-1ABI\s0 switches in e_flags.
+.IP "\fB\-mcond\-move\fR" 4
+.IX Item "-mcond-move"
+Enable the use of conditional-move instructions (default).
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mno\-cond\-move\fR" 4
+.IX Item "-mno-cond-move"
+Disable the use of conditional-move instructions.
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mscc\fR" 4
+.IX Item "-mscc"
+Enable the use of conditional set instructions (default).
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mno\-scc\fR" 4
+.IX Item "-mno-scc"
+Disable the use of conditional set instructions.
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mcond\-exec\fR" 4
+.IX Item "-mcond-exec"
+Enable the use of conditional execution (default).
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mno\-cond\-exec\fR" 4
+.IX Item "-mno-cond-exec"
+Disable the use of conditional execution.
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mvliw\-branch\fR" 4
+.IX Item "-mvliw-branch"
+Run a pass to pack branches into \s-1VLIW\s0 instructions (default).
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mno\-vliw\-branch\fR" 4
+.IX Item "-mno-vliw-branch"
+Do not run a pass to pack branches into \s-1VLIW\s0 instructions.
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mmulti\-cond\-exec\fR" 4
+.IX Item "-mmulti-cond-exec"
+Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution
+(default).
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mno\-multi\-cond\-exec\fR" 4
+.IX Item "-mno-multi-cond-exec"
+Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution.
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mnested\-cond\-exec\fR" 4
+.IX Item "-mnested-cond-exec"
+Enable nested conditional execution optimizations (default).
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-mno\-nested\-cond\-exec\fR" 4
+.IX Item "-mno-nested-cond-exec"
+Disable nested conditional execution optimizations.
+.Sp
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+.IP "\fB\-moptimize\-membar\fR" 4
+.IX Item "-moptimize-membar"
+This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the
+compiler generated code. It is enabled by default.
+.IP "\fB\-mno\-optimize\-membar\fR" 4
+.IX Item "-mno-optimize-membar"
+This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR
+instructions from the generated code.
+.IP "\fB\-mtomcat\-stats\fR" 4
+.IX Item "-mtomcat-stats"
+Cause gas to print out tomcat statistics.
+.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
+.IX Item "-mcpu=cpu"
+Select the processor type for which to generate code. Possible values are
+\&\fBfrv\fR, \fBfr550\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr450\fR,
+\&\fBfr405\fR, \fBfr400\fR, \fBfr300\fR and \fBsimple\fR.
+.PP
+\fIGNU/Linux Options\fR
+.IX Subsection "GNU/Linux Options"
+.PP
+These \fB\-m\fR options are defined for GNU/Linux targets:
+.IP "\fB\-mglibc\fR" 4
+.IX Item "-mglibc"
+Use the \s-1GNU\s0 C library instead of uClibc. This is the default except
+on \fB*\-*\-linux\-*uclibc*\fR targets.
+.IP "\fB\-muclibc\fR" 4
+.IX Item "-muclibc"
+Use uClibc instead of the \s-1GNU\s0 C library. This is the default on
+\&\fB*\-*\-linux\-*uclibc*\fR targets.
+.PP
+\fIH8/300 Options\fR
+.IX Subsection "H8/300 Options"
+.PP
+These \fB\-m\fR options are defined for the H8/300 implementations:
.IP "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
-Indicate to the linker that it should perform a relaxation optimization pass
-to shorten branches, calls and absolute memory addresses. This option only
-has an effect when used on the command line for the final link step.
+Shorten some address references at link time, when possible; uses the
+linker option \fB\-relax\fR.
+.IP "\fB\-mh\fR" 4
+.IX Item "-mh"
+Generate code for the H8/300H.
+.IP "\fB\-ms\fR" 4
+.IX Item "-ms"
+Generate code for the H8S.
+.IP "\fB\-mn\fR" 4
+.IX Item "-mn"
+Generate code for the H8S and H8/300H in the normal mode. This switch
+must be used either with \fB\-mh\fR or \fB\-ms\fR.
+.IP "\fB\-ms2600\fR" 4
+.IX Item "-ms2600"
+Generate code for the H8S/2600. This switch must be used with \fB\-ms\fR.
+.IP "\fB\-mint32\fR" 4
+.IX Item "-mint32"
+Make \f(CW\*(C`int\*(C'\fR data 32 bits by default.
+.IP "\fB\-malign\-300\fR" 4
+.IX Item "-malign-300"
+On the H8/300H and H8S, use the same alignment rules as for the H8/300.
+The default for the H8/300H and H8S is to align longs and floats on 4
+byte boundaries.
+\&\fB\-malign\-300\fR causes them to be aligned on 2 byte boundaries.
+This option has no effect on the H8/300.
+.PP
+\fI\s-1HPPA\s0 Options\fR
+.IX Subsection "HPPA Options"
+.PP
+These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers:
+.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4
+.IX Item "-march=architecture-type"
+Generate code for the specified architecture. The choices for
+\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0
+1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors. Refer to
+\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper
+architecture option for your machine. Code compiled for lower numbered
+architectures will run on higher numbered architectures, but not the
+other way around.
+.IP "\fB\-mpa\-risc\-1\-0\fR" 4
+.IX Item "-mpa-risc-1-0"
+.PD 0
+.IP "\fB\-mpa\-risc\-1\-1\fR" 4
+.IX Item "-mpa-risc-1-1"
+.IP "\fB\-mpa\-risc\-2\-0\fR" 4
+.IX Item "-mpa-risc-2-0"
+.PD
+Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively.
+.IP "\fB\-mbig\-switch\fR" 4
+.IX Item "-mbig-switch"
+Generate code suitable for big switch tables. Use this option only if
+the assembler/linker complain about out of range branches within a switch
+table.
+.IP "\fB\-mjump\-in\-delay\fR" 4
+.IX Item "-mjump-in-delay"
+Fill delay slots of function calls with unconditional jump instructions
+by modifying the return pointer for the function call to be the target
+of the conditional jump.
+.IP "\fB\-mdisable\-fpregs\fR" 4
+.IX Item "-mdisable-fpregs"
+Prevent floating point registers from being used in any manner. This is
+necessary for compiling kernels which perform lazy context switching of
+floating point registers. If you use this option and attempt to perform
+floating point operations, the compiler will abort.
+.IP "\fB\-mdisable\-indexing\fR" 4
+.IX Item "-mdisable-indexing"
+Prevent the compiler from using indexing address modes. This avoids some
+rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0.
+.IP "\fB\-mno\-space\-regs\fR" 4
+.IX Item "-mno-space-regs"
+Generate code that assumes the target has no space registers. This allows
+\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes.
.Sp
-This option makes symbolic debugging impossible.
+Such code is suitable for level 0 \s-1PA\s0 systems and kernels.
+.IP "\fB\-mfast\-indirect\-calls\fR" 4
+.IX Item "-mfast-indirect-calls"
+Generate code that assumes calls never cross space boundaries. This
+allows \s-1GCC\s0 to emit code which performs faster indirect calls.
+.Sp
+This option will not work in the presence of shared libraries or nested
+functions.
+.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
+.IX Item "-mfixed-range=register-range"
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator can not use. This is
+useful when compiling kernel code. A register range is specified as
+two registers separated by a dash. Multiple register ranges can be
+specified separated by a comma.
+.IP "\fB\-mlong\-load\-store\fR" 4
+.IX Item "-mlong-load-store"
+Generate 3\-instruction load and store sequences as sometimes required by
+the HP-UX 10 linker. This is equivalent to the \fB+k\fR option to
+the \s-1HP\s0 compilers.
+.IP "\fB\-mportable\-runtime\fR" 4
+.IX Item "-mportable-runtime"
+Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems.
+.IP "\fB\-mgas\fR" 4
+.IX Item "-mgas"
+Enable the use of assembler directives only \s-1GAS\s0 understands.
+.IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4
+.IX Item "-mschedule=cpu-type"
+Schedule code according to the constraints for the machine type
+\&\fIcpu-type\fR. The choices for \fIcpu-type\fR are \fB700\fR
+\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR. Refer
+to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the
+proper scheduling option for your machine. The default scheduling is
+\&\fB8000\fR.
+.IP "\fB\-mlinker\-opt\fR" 4
+.IX Item "-mlinker-opt"
+Enable the optimization pass in the HP-UX linker. Note this makes symbolic
+debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
+linkers in which they give bogus error messages when linking some programs.
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+Generate output containing library calls for floating point.
+\&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0
+targets. Normally the facilities of the machine's usual C compiler are
+used, but this cannot be done directly in cross\-compilation. You must make
+your own arrangements to provide suitable library functions for
+cross\-compilation. The embedded target \fBhppa1.1\-*\-pro\fR
+does provide software floating point support.
+.Sp
+\&\fB\-msoft\-float\fR changes the calling convention in the output file;
+therefore, it is only useful if you compile \fIall\fR of a program with
+this option. In particular, you need to compile \fIlibgcc.a\fR, the
+library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for
+this to work.
+.IP "\fB\-msio\fR" 4
+.IX Item "-msio"
+Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0. The default is
+\&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR,
+\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0. These
+options are available under HP-UX and \s-1HI\-UX\s0.
+.IP "\fB\-mgnu\-ld\fR" 4
+.IX Item "-mgnu-ld"
+Use \s-1GNU\s0 ld specific options. This passes \fB\-shared\fR to ld when
+building a shared library. It is the default when \s-1GCC\s0 is configured,
+explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not
+have any affect on which ld is called, it only changes what parameters
+are passed to that ld. The ld that is called is determined by the
+\&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and
+finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed
+using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available
+on the 64 bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR.
+.IP "\fB\-mhp\-ld\fR" 4
+.IX Item "-mhp-ld"
+Use \s-1HP\s0 ld specific options. This passes \fB\-b\fR to ld when building
+a shared library and passes \fB+Accept TypeMismatch\fR to ld on all
+links. It is the default when \s-1GCC\s0 is configured, explicitly or
+implicitly, with the \s-1HP\s0 linker. This option does not have any affect on
+which ld is called, it only changes what parameters are passed to that
+ld. The ld that is called is determined by the \fB\-\-with\-ld\fR
+configure option, \s-1GCC\s0's program search path, and finally by the user's
+\&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich
+`gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64 bit
+HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR.
+.IP "\fB\-mlong\-calls\fR" 4
+.IX Item "-mlong-calls"
+Generate code that uses long call sequences. This ensures that a call
+is always able to reach linker generated stubs. The default is to generate
+long calls only when the distance from the call site to the beginning
+of the function or translation unit, as the case may be, exceeds a
+predefined limit set by the branch type being used. The limits for
+normal calls are 7,600,000 and 240,000 bytes, respectively for the
+\&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures. Sibcalls are always limited at
+240,000 bytes.
+.Sp
+Distances are measured from the beginning of functions when using the
+\&\fB\-ffunction\-sections\fR option, or when using the \fB\-mgas\fR
+and \fB\-mno\-portable\-runtime\fR options together under HP-UX with
+the \s-1SOM\s0 linker.
+.Sp
+It is normally not desirable to use this option as it will degrade
+performance. However, it may be useful in large applications,
+particularly when partial linking is used to build the application.
+.Sp
+The types of long calls used depends on the capabilities of the
+assembler and linker, and the type of code being generated. The
+impact on systems that support long absolute calls, and long pic
+symbol-difference or pc-relative calls should be relatively small.
+However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code
+and it is quite long.
+.IP "\fB\-munix=\fR\fIunix-std\fR" 4
+.IX Item "-munix=unix-std"
+Generate compiler predefines and select a startfile for the specified
+\&\s-1UNIX\s0 standard. The choices for \fIunix-std\fR are \fB93\fR, \fB95\fR
+and \fB98\fR. \fB93\fR is supported on all HP-UX versions. \fB95\fR
+is available on HP-UX 10.10 and later. \fB98\fR is available on HP-UX
+11.11 and later. The default values are \fB93\fR for HP-UX 10.00,
+\&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11
+and later.
+.Sp
+\&\fB\-munix=93\fR provides the same predefines as \s-1GCC\s0 3.3 and 3.4.
+\&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR
+and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR.
+\&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR,
+\&\f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, \f(CW\*(C`_INCLUDE_\|_STDC_A1_SOURCE\*(C'\fR and
+\&\f(CW\*(C`_INCLUDE_XOPEN_SOURCE_500\*(C'\fR, and the startfile \fIunix98.o\fR.
+.Sp
+It is \fIimportant\fR to note that this option changes the interfaces
+for various library routines. It also affects the operational behavior
+of the C library. Thus, \fIextreme\fR care is needed in using this
+option.
+.Sp
+Library code that is intended to operate with more than one \s-1UNIX\s0
+standard must test, set and restore the variable \fI_\|_xpg4_extended_mask\fR
+as appropriate. Most \s-1GNU\s0 software doesn't provide this capability.
+.IP "\fB\-nolibdld\fR" 4
+.IX Item "-nolibdld"
+Suppress the generation of link options to search libdld.sl when the
+\&\fB\-static\fR option is specified on HP-UX 10 and later.
+.IP "\fB\-static\fR" 4
+.IX Item "-static"
+The HP-UX implementation of setlocale in libc has a dependency on
+libdld.sl. There isn't an archive version of libdld.sl. Thus,
+when the \fB\-static\fR option is specified, special link options
+are needed to resolve this dependency.
+.Sp
+On HP-UX 10 and later, the \s-1GCC\s0 driver adds the necessary options to
+link with libdld.sl when the \fB\-static\fR option is specified.
+This causes the resulting binary to be dynamic. On the 64\-bit port,
+the linkers generate dynamic binaries by default in any case. The
+\&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from
+adding these link options.
+.IP "\fB\-threads\fR" 4
+.IX Item "-threads"
+Add support for multithreading with the \fIdce thread\fR library
+under \s-1HP\-UX\s0. This option sets flags for both the preprocessor and
+linker.
+.PP
+\fIIntel 386 and \s-1AMD\s0 x86\-64 Options\fR
+.IX Subsection "Intel 386 and AMD x86-64 Options"
+.PP
+These \fB\-m\fR options are defined for the i386 and x86\-64 family of
+computers:
+.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
+.IX Item "-mtune=cpu-type"
+Tune to \fIcpu-type\fR everything applicable about the generated code, except
+for the \s-1ABI\s0 and the set of available instructions. The choices for
+\&\fIcpu-type\fR are:
+.RS 4
+.IP "\fIgeneric\fR" 4
+.IX Item "generic"
+Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors.
+If you know the \s-1CPU\s0 on which your code will run, then you should use
+the corresponding \fB\-mtune\fR option instead of
+\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users
+of your application will have, then you should use this option.
+.Sp
+As new processors are deployed in the marketplace, the behavior of this
+option will change. Therefore, if you upgrade to a newer version of
+\&\s-1GCC\s0, the code generated option will change to reflect the processors
+that were most common when that version of \s-1GCC\s0 was released.
+.Sp
+There is no \fB\-march=generic\fR option because \fB\-march\fR
+indicates the instruction set the compiler can use, and there is no
+generic instruction set applicable to all processors. In contrast,
+\&\fB\-mtune\fR indicates the processor (or, in this case, collection of
+processors) for which the code is optimized.
+.IP "\fInative\fR" 4
+.IX Item "native"
+This selects the \s-1CPU\s0 to tune for at compilation time by determining
+the processor type of the compiling machine. Using \fB\-mtune=native\fR
+will produce code optimized for the local machine under the constraints
+of the selected instruction set. Using \fB\-march=native\fR will
+enable all instruction subsets supported by the local machine (hence
+the result might not run on different machines).
+.IP "\fIi386\fR" 4
+.IX Item "i386"
+Original Intel's i386 \s-1CPU\s0.
+.IP "\fIi486\fR" 4
+.IX Item "i486"
+Intel's i486 \s-1CPU\s0. (No scheduling is implemented for this chip.)
+.IP "\fIi586, pentium\fR" 4
+.IX Item "i586, pentium"
+Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support.
+.IP "\fIpentium-mmx\fR" 4
+.IX Item "pentium-mmx"
+Intel PentiumMMX \s-1CPU\s0 based on Pentium core with \s-1MMX\s0 instruction set support.
+.IP "\fIpentiumpro\fR" 4
+.IX Item "pentiumpro"
+Intel PentiumPro \s-1CPU\s0.
+.IP "\fIi686\fR" 4
+.IX Item "i686"
+Same as \f(CW\*(C`generic\*(C'\fR, but when used as \f(CW\*(C`march\*(C'\fR option, PentiumPro
+instruction set will be used, so the code will run on all i686 family chips.
+.IP "\fIpentium2\fR" 4
+.IX Item "pentium2"
+Intel Pentium2 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 instruction set support.
+.IP "\fIpentium3, pentium3m\fR" 4
+.IX Item "pentium3, pentium3m"
+Intel Pentium3 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set
+support.
+.IP "\fIpentium-m\fR" 4
+.IX Item "pentium-m"
+Low power version of Intel Pentium3 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set
+support. Used by Centrino notebooks.
+.IP "\fIpentium4, pentium4m\fR" 4
+.IX Item "pentium4, pentium4m"
+Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support.
+.IP "\fIprescott\fR" 4
+.IX Item "prescott"
+Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction
+set support.
+.IP "\fInocona\fR" 4
+.IX Item "nocona"
+Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0,
+\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support.
+.IP "\fIk6\fR" 4
+.IX Item "k6"
+\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support.
+.IP "\fIk6\-2, k6\-3\fR" 4
+.IX Item "k6-2, k6-3"
+Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support.
+.IP "\fIathlon, athlon-tbird\fR" 4
+.IX Item "athlon, athlon-tbird"
+\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3dNOW! and \s-1SSE\s0 prefetch instructions
+support.
+.IP "\fIathlon\-4, athlon\-xp, athlon-mp\fR" 4
+.IX Item "athlon-4, athlon-xp, athlon-mp"
+Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3dNOW! and full \s-1SSE\s0
+instruction set support.
+.IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4
+.IX Item "k8, opteron, athlon64, athlon-fx"
+\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support. (This supersets
+\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
+.IP "\fIwinchip\-c6\fR" 4
+.IX Item "winchip-c6"
+\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
+set support.
+.IP "\fIwinchip2\fR" 4
+.IX Item "winchip2"
+\&\s-1IDT\s0 Winchip2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3dNOW!
+instruction set support.
+.IP "\fIc3\fR" 4
+.IX Item "c3"
+Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. (No scheduling is
+implemented for this chip.)
+.IP "\fIc3\-2\fR" 4
+.IX Item "c3-2"
+Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is
+implemented for this chip.)
+.RE
+.RS 4
+.Sp
+While picking a specific \fIcpu-type\fR will schedule things appropriately
+for that particular chip, the compiler will not generate any code that
+does not run on the i386 without the \fB\-march=\fR\fIcpu-type\fR option
+being used.
+.RE
+.IP "\fB\-march=\fR\fIcpu-type\fR" 4
+.IX Item "-march=cpu-type"
+Generate instructions for the machine type \fIcpu-type\fR. The choices
+for \fIcpu-type\fR are the same as for \fB\-mtune\fR. Moreover,
+specifying \fB\-march=\fR\fIcpu-type\fR implies \fB\-mtune=\fR\fIcpu-type\fR.
+.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4
+.IX Item "-mcpu=cpu-type"
+A deprecated synonym for \fB\-mtune\fR.
+.IP "\fB\-m386\fR" 4
+.IX Item "-m386"
+.PD 0
+.IP "\fB\-m486\fR" 4
+.IX Item "-m486"
+.IP "\fB\-mpentium\fR" 4
+.IX Item "-mpentium"
+.IP "\fB\-mpentiumpro\fR" 4
+.IX Item "-mpentiumpro"
+.PD
+These options are synonyms for \fB\-mtune=i386\fR, \fB\-mtune=i486\fR,
+\&\fB\-mtune=pentium\fR, and \fB\-mtune=pentiumpro\fR respectively.
+These synonyms are deprecated.
+.IP "\fB\-mfpmath=\fR\fIunit\fR" 4
+.IX Item "-mfpmath=unit"
+Generate floating point arithmetics for selected unit \fIunit\fR. The choices
+for \fIunit\fR are:
+.RS 4
+.IP "\fB387\fR" 4
+.IX Item "387"
+Use the standard 387 floating point coprocessor present majority of chips and
+emulated otherwise. Code compiled with this option will run almost everywhere.
+The temporary results are computed in 80bit precision instead of precision
+specified by the type resulting in slightly different results compared to most
+of other chips. See \fB\-ffloat\-store\fR for more detailed description.
+.Sp
+This is the default choice for i386 compiler.
+.IP "\fBsse\fR" 4
+.IX Item "sse"
+Use scalar floating point instructions present in the \s-1SSE\s0 instruction set.
+This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line
+by Athlon\-4, Athlon-xp and Athlon-mp chips. The earlier version of \s-1SSE\s0
+instruction set supports only single precision arithmetics, thus the double and
+extended precision arithmetics is still done using 387. Later version, present
+only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips supports double precision
+arithmetics too.
+.Sp
+For the i386 compiler, you need to use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR
+or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option
+effective. For the x86\-64 compiler, these extensions are enabled by default.
+.Sp
+The resulting code should be considerably faster in the majority of cases and avoid
+the numerical instability problems of 387 code, but may break some existing
+code that expects temporaries to be 80bit.
+.Sp
+This is the default choice for the x86\-64 compiler.
+.IP "\fBsse,387\fR" 4
+.IX Item "sse,387"
+Attempt to utilize both instruction sets at once. This effectively double the
+amount of available registers and on chips with separate execution units for
+387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is
+still experimental, because the \s-1GCC\s0 register allocator does not model separate
+functional units well resulting in instable performance.
+.RE
+.RS 4
+.RE
+.IP "\fB\-masm=\fR\fIdialect\fR" 4
+.IX Item "-masm=dialect"
+Output asm instructions using selected \fIdialect\fR. Supported
+choices are \fBintel\fR or \fBatt\fR (the default one). Darwin does
+not support \fBintel\fR.
+.IP "\fB\-mieee\-fp\fR" 4
+.IX Item "-mieee-fp"
+.PD 0
+.IP "\fB\-mno\-ieee\-fp\fR" 4
+.IX Item "-mno-ieee-fp"
+.PD
+Control whether or not the compiler uses \s-1IEEE\s0 floating point
+comparisons. These handle correctly the case where the result of a
+comparison is unordered.
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+Generate output containing library calls for floating point.
+\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0.
+Normally the facilities of the machine's usual C compiler are used, but
+this can't be done directly in cross\-compilation. You must make your
+own arrangements to provide suitable library functions for
+cross\-compilation.
+.Sp
+On machines where a function returns floating point results in the 80387
+register stack, some floating point opcodes may be emitted even if
+\&\fB\-msoft\-float\fR is used.
+.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4
+.IX Item "-mno-fp-ret-in-387"
+Do not use the \s-1FPU\s0 registers for return values of functions.
+.Sp
+The usual calling convention has functions return values of types
+\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there
+is no \s-1FPU\s0. The idea is that the operating system should emulate
+an \s-1FPU\s0.
+.Sp
+The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned
+in ordinary \s-1CPU\s0 registers instead.
+.IP "\fB\-mno\-fancy\-math\-387\fR" 4
+.IX Item "-mno-fancy-math-387"
+Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and
+\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid
+generating those instructions. This option is the default on FreeBSD,
+OpenBSD and NetBSD. This option is overridden when \fB\-march\fR
+indicates that the target cpu will always have an \s-1FPU\s0 and so the
+instruction will not need emulation. As of revision 2.6.1, these
+instructions are not generated unless you also use the
+\&\fB\-funsafe\-math\-optimizations\fR switch.
+.IP "\fB\-malign\-double\fR" 4
+.IX Item "-malign-double"
+.PD 0
+.IP "\fB\-mno\-align\-double\fR" 4
+.IX Item "-mno-align-double"
+.PD
+Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and
+\&\f(CW\*(C`long long\*(C'\fR variables on a two word boundary or a one word
+boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two word boundary will
+produce code that runs somewhat faster on a \fBPentium\fR at the
+expense of more memory.
+.Sp
+On x86\-64, \fB\-malign\-double\fR is enabled by default.
+.Sp
+\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch,
+structures containing the above types will be aligned differently than
+the published application binary interface specifications for the 386
+and will not be binary compatible with structures in code compiled
+without that switch.
+.IP "\fB\-m96bit\-long\-double\fR" 4
+.IX Item "-m96bit-long-double"
+.PD 0
+.IP "\fB\-m128bit\-long\-double\fR" 4
+.IX Item "-m128bit-long-double"
+.PD
+These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The i386
+application binary interface specifies the size to be 96 bits,
+so \fB\-m96bit\-long\-double\fR is the default in 32 bit mode.
+.Sp
+Modern architectures (Pentium and newer) would prefer \f(CW\*(C`long double\*(C'\fR
+to be aligned to an 8 or 16 byte boundary. In arrays or structures
+conforming to the \s-1ABI\s0, this would not be possible. So specifying a
+\&\fB\-m128bit\-long\-double\fR will align \f(CW\*(C`long double\*(C'\fR
+to a 16 byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional
+32 bit zero.
+.Sp
+In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as
+its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is to be aligned on 16 byte boundary.
+.Sp
+Notice that neither of these options enable any extra precision over the x87
+standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR.
+.Sp
+\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, the
+structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables will change
+their size as well as function calling convention for function taking
+\&\f(CW\*(C`long double\*(C'\fR will be modified. Hence they will not be binary
+compatible with arrays or structures in code compiled without that switch.
+.IP "\fB\-mmlarge\-data\-threshold=\fR\fInumber\fR" 4
+.IX Item "-mmlarge-data-threshold=number"
+When \fB\-mcmodel=medium\fR is specified, the data greater than
+\&\fIthreshold\fR are placed in large data section. This value must be the
+same across all object linked into the binary and defaults to 65535.
+.IP "\fB\-msvr3\-shlib\fR" 4
+.IX Item "-msvr3-shlib"
+.PD 0
+.IP "\fB\-mno\-svr3\-shlib\fR" 4
+.IX Item "-mno-svr3-shlib"
+.PD
+Control whether \s-1GCC\s0 places uninitialized local variables into the
+\&\f(CW\*(C`bss\*(C'\fR or \f(CW\*(C`data\*(C'\fR segments. \fB\-msvr3\-shlib\fR places them
+into \f(CW\*(C`bss\*(C'\fR. These options are meaningful only on System V Release 3.
+.IP "\fB\-mrtd\fR" 4
+.IX Item "-mrtd"
+Use a different function-calling convention, in which functions that
+take a fixed number of arguments return with the \f(CW\*(C`ret\*(C'\fR \fInum\fR
+instruction, which pops their arguments while returning. This saves one
+instruction in the caller since there is no need to pop the arguments
+there.
+.Sp
+You can specify that an individual function is called with this calling
+sequence with the function attribute \fBstdcall\fR. You can also
+override the \fB\-mrtd\fR option by using the function attribute
+\&\fBcdecl\fR.
+.Sp
+\&\fBWarning:\fR this calling convention is incompatible with the one
+normally used on Unix, so you cannot use it if you need to call
+libraries compiled with the Unix compiler.
+.Sp
+Also, you must provide function prototypes for all functions that
+take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
+otherwise incorrect code will be generated for calls to those
+functions.
+.Sp
+In addition, seriously incorrect code will result if you call a
+function with too many arguments. (Normally, extra arguments are
+harmlessly ignored.)
+.IP "\fB\-mregparm=\fR\fInum\fR" 4
+.IX Item "-mregparm=num"
+Control how many registers are used to pass integer arguments. By
+default, no registers are used to pass arguments, and at most 3
+registers can be used. You can control this behavior for a specific
+function by using the function attribute \fBregparm\fR.
+.Sp
+\&\fBWarning:\fR if you use this switch, and
+\&\fInum\fR is nonzero, then you must build all modules with the same
+value, including any libraries. This includes the system libraries and
+startup modules.
+.IP "\fB\-msseregparm\fR" 4
+.IX Item "-msseregparm"
+Use \s-1SSE\s0 register passing conventions for float and double arguments
+and return values. You can control this behavior for a specific
+function by using the function attribute \fBsseregparm\fR.
+.Sp
+\&\fBWarning:\fR if you use this switch then you must build all
+modules with the same value, including any libraries. This includes
+the system libraries and startup modules.
+.IP "\fB\-mstackrealign\fR" 4
+.IX Item "-mstackrealign"
+Realign the stack at entry. On the Intel x86, the
+\&\fB\-mstackrealign\fR option will generate an alternate prologue and
+epilogue that realigns the runtime stack. This supports mixing legacy
+codes that keep a 4\-byte aligned stack with modern codes that keep a
+16\-byte stack for \s-1SSE\s0 compatibility. The alternate prologue and
+epilogue are slower and bigger than the regular ones, and the
+alternate prologue requires an extra scratch register; this lowers the
+number of registers available if used in conjunction with the
+\&\f(CW\*(C`regparm\*(C'\fR attribute. The \fB\-mstackrealign\fR option is
+incompatible with the nested function prologue; this is considered a
+hard error. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR,
+applicable to individual functions.
+.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4
+.IX Item "-mpreferred-stack-boundary=num"
+Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR
+byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified,
+the default is 4 (16 bytes or 128 bits).
+.Sp
+On Pentium and PentiumPro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values
+should be aligned to an 8 byte boundary (see \fB\-malign\-double\fR) or
+suffer significant run time performance penalties. On Pentium \s-1III\s0, the
+Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work
+properly if it is not 16 byte aligned.
+.Sp
+To ensure proper alignment of this values on the stack, the stack boundary
+must be as aligned as that required by any value stored on the stack.
+Further, every function must be generated such that it keeps the stack
+aligned. Thus calling a function compiled with a higher preferred
+stack boundary from a function compiled with a lower preferred stack
+boundary will most likely misalign the stack. It is recommended that
+libraries that use callbacks always use the default setting.
+.Sp
+This extra alignment does consume extra stack space, and generally
+increases code size. Code that is sensitive to stack space usage, such
+as embedded systems and operating system kernels, may want to reduce the
+preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR.
+.IP "\fB\-mmmx\fR" 4
+.IX Item "-mmmx"
+.PD 0
+.IP "\fB\-mno\-mmx\fR" 4
+.IX Item "-mno-mmx"
+.IP "\fB\-msse\fR" 4
+.IX Item "-msse"
+.IP "\fB\-mno\-sse\fR" 4
+.IX Item "-mno-sse"
+.IP "\fB\-msse2\fR" 4
+.IX Item "-msse2"
+.IP "\fB\-mno\-sse2\fR" 4
+.IX Item "-mno-sse2"
+.IP "\fB\-msse3\fR" 4
+.IX Item "-msse3"
+.IP "\fB\-mno\-sse3\fR" 4
+.IX Item "-mno-sse3"
+.IP "\fB\-m3dnow\fR" 4
+.IX Item "-m3dnow"
+.IP "\fB\-mno\-3dnow\fR" 4
+.IX Item "-mno-3dnow"
+.PD
+These switches enable or disable the use of instructions in the \s-1MMX\s0,
+\&\s-1SSE\s0, \s-1SSE2\s0 or 3DNow! extended instruction sets. These extensions are
+also available as built-in functions: see \fBX86 Built-in Functions\fR,
+for details of the functions enabled and disabled by these switches.
+.Sp
+To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point
+code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR.
+.Sp
+These options will enable \s-1GCC\s0 to use these extended instructions in
+generated code, even without \fB\-mfpmath=sse\fR. Applications which
+perform runtime \s-1CPU\s0 detection must compile separate files for each
+supported architecture, using the appropriate flags. In particular,
+the file containing the \s-1CPU\s0 detection code should be compiled without
+these options.
+.IP "\fB\-mpush\-args\fR" 4
+.IX Item "-mpush-args"
+.PD 0
+.IP "\fB\-mno\-push\-args\fR" 4
+.IX Item "-mno-push-args"
+.PD
+Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter
+and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled
+by default. In some cases disabling it may improve performance because of
+improved scheduling and reduced dependencies.
+.IP "\fB\-maccumulate\-outgoing\-args\fR" 4
+.IX Item "-maccumulate-outgoing-args"
+If enabled, the maximum amount of space required for outgoing arguments will be
+computed in the function prologue. This is faster on most modern CPUs
+because of reduced dependencies, improved scheduling and reduced stack usage
+when preferred stack boundary is not equal to 2. The drawback is a notable
+increase in code size. This switch implies \fB\-mno\-push\-args\fR.
+.IP "\fB\-mthreads\fR" 4
+.IX Item "-mthreads"
+Support thread-safe exception handling on \fBMingw32\fR. Code that relies
+on thread-safe exception handling must compile and link all code with the
+\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines
+\&\fB\-D_MT\fR; when linking, it links in a special thread helper library
+\&\fB\-lmingwthrd\fR which cleans up per thread exception handling data.
+.IP "\fB\-mno\-align\-stringops\fR" 4
+.IX Item "-mno-align-stringops"
+Do not align destination of inlined string operations. This switch reduces
+code size and improves performance in case the destination is already aligned,
+but \s-1GCC\s0 doesn't know about it.
+.IP "\fB\-minline\-all\-stringops\fR" 4
+.IX Item "-minline-all-stringops"
+By default \s-1GCC\s0 inlines string operations only when destination is known to be
+aligned at least to 4 byte boundary. This enables more inlining, increase code
+size, but may improve performance of code that depends on fast memcpy, strlen
+and memset for short lengths.
+.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4
+.IX Item "-momit-leaf-frame-pointer"
+Don't keep the frame pointer in a register for leaf functions. This
+avoids the instructions to save, set up and restore frame pointers and
+makes an extra register available in leaf functions. The option
+\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions
+which might make debugging harder.
+.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4
+.IX Item "-mtls-direct-seg-refs"
+.PD 0
+.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4
+.IX Item "-mno-tls-direct-seg-refs"
+.PD
+Controls whether \s-1TLS\s0 variables may be accessed with offsets from the
+\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit),
+or whether the thread base pointer must be added. Whether or not this
+is legal depends on the operating system, and whether it maps the
+segment to cover the entire \s-1TLS\s0 area.
+.Sp
+For systems that use \s-1GNU\s0 libc, the default is on.
+.PP
+These \fB\-m\fR switches are supported in addition to the above
+on \s-1AMD\s0 x86\-64 processors in 64\-bit environments.
+.IP "\fB\-m32\fR" 4
+.IX Item "-m32"
+.PD 0
+.IP "\fB\-m64\fR" 4
+.IX Item "-m64"
+.PD
+Generate code for a 32\-bit or 64\-bit environment.
+The 32\-bit environment sets int, long and pointer to 32 bits and
+generates code that runs on any i386 system.
+The 64\-bit environment sets int to 32 bits and long and pointer
+to 64 bits and generates code for \s-1AMD\s0's x86\-64 architecture. For
+darwin only the \-m64 option turns off the \fB\-fno\-pic\fR and
+\&\fB\-mdynamic\-no\-pic\fR options.
+.IP "\fB\-mno\-red\-zone\fR" 4
+.IX Item "-mno-red-zone"
+Do not use a so called red zone for x86\-64 code. The red zone is mandated
+by the x86\-64 \s-1ABI\s0, it is a 128\-byte area beyond the location of the
+stack pointer that will not be modified by signal or interrupt handlers
+and therefore can be used for temporary data without adjusting the stack
+pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone.
+.IP "\fB\-mcmodel=small\fR" 4
+.IX Item "-mcmodel=small"
+Generate code for the small code model: the program and its symbols must
+be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits.
+Programs can be statically or dynamically linked. This is the default
+code model.
+.IP "\fB\-mcmodel=kernel\fR" 4
+.IX Item "-mcmodel=kernel"
+Generate code for the kernel code model. The kernel runs in the
+negative 2 \s-1GB\s0 of the address space.
+This model has to be used for Linux kernel code.
+.IP "\fB\-mcmodel=medium\fR" 4
+.IX Item "-mcmodel=medium"
+Generate code for the medium model: The program is linked in the lower 2
+\&\s-1GB\s0 of the address space but symbols can be located anywhere in the
+address space. Programs can be statically or dynamically linked, but
+building of shared libraries are not supported with the medium model.
+.IP "\fB\-mcmodel=large\fR" 4
+.IX Item "-mcmodel=large"
+Generate code for the large model: This model makes no assumptions
+about addresses and sizes of sections. Currently \s-1GCC\s0 does not implement
+this model.
+.PP
+\fI\s-1IA\-64\s0 Options\fR
+.IX Subsection "IA-64 Options"
+.PP
+These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture.
+.IP "\fB\-mbig\-endian\fR" 4
+.IX Item "-mbig-endian"
+Generate code for a big endian target. This is the default for \s-1HP\-UX\s0.
+.IP "\fB\-mlittle\-endian\fR" 4
+.IX Item "-mlittle-endian"
+Generate code for a little endian target. This is the default for \s-1AIX5\s0
+and GNU/Linux.
+.IP "\fB\-mgnu\-as\fR" 4
+.IX Item "-mgnu-as"
+.PD 0
+.IP "\fB\-mno\-gnu\-as\fR" 4
+.IX Item "-mno-gnu-as"
+.PD
+Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default.
+.IP "\fB\-mgnu\-ld\fR" 4
+.IX Item "-mgnu-ld"
+.PD 0
+.IP "\fB\-mno\-gnu\-ld\fR" 4
+.IX Item "-mno-gnu-ld"
+.PD
+Generate (or don't) code for the \s-1GNU\s0 linker. This is the default.
+.IP "\fB\-mno\-pic\fR" 4
+.IX Item "-mno-pic"
+Generate code that does not use a global pointer register. The result
+is not position independent code, and violates the \s-1IA\-64\s0 \s-1ABI\s0.
+.IP "\fB\-mvolatile\-asm\-stop\fR" 4
+.IX Item "-mvolatile-asm-stop"
+.PD 0
+.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4
+.IX Item "-mno-volatile-asm-stop"
+.PD
+Generate (or don't) a stop bit immediately before and after volatile asm
+statements.
+.IP "\fB\-mregister\-names\fR" 4
+.IX Item "-mregister-names"
+.PD 0
+.IP "\fB\-mno\-register\-names\fR" 4
+.IX Item "-mno-register-names"
+.PD
+Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for
+the stacked registers. This may make assembler output more readable.
+.IP "\fB\-mno\-sdata\fR" 4
+.IX Item "-mno-sdata"
+.PD 0
+.IP "\fB\-msdata\fR" 4
+.IX Item "-msdata"
+.PD
+Disable (or enable) optimizations that use the small data section. This may
+be useful for working around optimizer bugs.
+.IP "\fB\-mconstant\-gp\fR" 4
+.IX Item "-mconstant-gp"
+Generate code that uses a single constant global pointer value. This is
+useful when compiling kernel code.
+.IP "\fB\-mauto\-pic\fR" 4
+.IX Item "-mauto-pic"
+Generate code that is self\-relocatable. This implies \fB\-mconstant\-gp\fR.
+This is useful when compiling firmware code.
+.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4
+.IX Item "-minline-float-divide-min-latency"
+Generate code for inline divides of floating point values
+using the minimum latency algorithm.
+.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4
+.IX Item "-minline-float-divide-max-throughput"
+Generate code for inline divides of floating point values
+using the maximum throughput algorithm.
+.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4
+.IX Item "-minline-int-divide-min-latency"
+Generate code for inline divides of integer values
+using the minimum latency algorithm.
+.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4
+.IX Item "-minline-int-divide-max-throughput"
+Generate code for inline divides of integer values
+using the maximum throughput algorithm.
+.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4
+.IX Item "-minline-sqrt-min-latency"
+Generate code for inline square roots
+using the minimum latency algorithm.
+.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4
+.IX Item "-minline-sqrt-max-throughput"
+Generate code for inline square roots
+using the maximum throughput algorithm.
+.IP "\fB\-mno\-dwarf2\-asm\fR" 4
+.IX Item "-mno-dwarf2-asm"
+.PD 0
+.IP "\fB\-mdwarf2\-asm\fR" 4
+.IX Item "-mdwarf2-asm"
+.PD
+Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging
+info. This may be useful when not using the \s-1GNU\s0 assembler.
+.IP "\fB\-mearly\-stop\-bits\fR" 4
+.IX Item "-mearly-stop-bits"
+.PD 0
+.IP "\fB\-mno\-early\-stop\-bits\fR" 4
+.IX Item "-mno-early-stop-bits"
+.PD
+Allow stop bits to be placed earlier than immediately preceding the
+instruction that triggered the stop bit. This can improve instruction
+scheduling, but does not always do so.
+.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
+.IX Item "-mfixed-range=register-range"
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator can not use. This is
+useful when compiling kernel code. A register range is specified as
+two registers separated by a dash. Multiple register ranges can be
+specified separated by a comma.
+.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4
+.IX Item "-mtls-size=tls-size"
+Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and
+64.
+.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
+.IX Item "-mtune=cpu-type"
+Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are
+itanium, itanium1, merced, itanium2, and mckinley.
+.IP "\fB\-mt\fR" 4
+.IX Item "-mt"
+.PD 0
+.IP "\fB\-pthread\fR" 4
+.IX Item "-pthread"
+.PD
+Add support for multithreading using the \s-1POSIX\s0 threads library. This
+option sets flags for both the preprocessor and linker. It does
+not affect the thread safety of object code produced by the compiler or
+that of libraries supplied with it. These are HP-UX specific flags.
+.IP "\fB\-milp32\fR" 4
+.IX Item "-milp32"
+.PD 0
+.IP "\fB\-mlp64\fR" 4
+.IX Item "-mlp64"
+.PD
+Generate code for a 32\-bit or 64\-bit environment.
+The 32\-bit environment sets int, long and pointer to 32 bits.
+The 64\-bit environment sets int to 32 bits and long and pointer
+to 64 bits. These are HP-UX specific flags.
+.IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4
+.IX Item "-mno-sched-br-data-spec"
+.PD 0
+.IP "\fB\-msched\-br\-data\-spec\fR" 4
+.IX Item "-msched-br-data-spec"
+.PD
+(Dis/En)able data speculative scheduling before reload.
+This will result in generation of the ld.a instructions and
+the corresponding check instructions (ld.c / chk.a).
+The default is 'disable'.
+.IP "\fB\-msched\-ar\-data\-spec\fR" 4
+.IX Item "-msched-ar-data-spec"
+.PD 0
+.IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4
+.IX Item "-mno-sched-ar-data-spec"
+.PD
+(En/Dis)able data speculative scheduling after reload.
+This will result in generation of the ld.a instructions and
+the corresponding check instructions (ld.c / chk.a).
+The default is 'enable'.
+.IP "\fB\-mno\-sched\-control\-spec\fR" 4
+.IX Item "-mno-sched-control-spec"
+.PD 0
+.IP "\fB\-msched\-control\-spec\fR" 4
+.IX Item "-msched-control-spec"
+.PD
+(Dis/En)able control speculative scheduling. This feature is
+available only during region scheduling (i.e. before reload).
+This will result in generation of the ld.s instructions and
+the corresponding check instructions chk.s .
+The default is 'disable'.
+.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4
+.IX Item "-msched-br-in-data-spec"
+.PD 0
+.IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4
+.IX Item "-mno-sched-br-in-data-spec"
+.PD
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the data speculative loads before reload.
+This is effective only with \fB\-msched\-br\-data\-spec\fR enabled.
+The default is 'enable'.
+.IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4
+.IX Item "-msched-ar-in-data-spec"
+.PD 0
+.IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4
+.IX Item "-mno-sched-ar-in-data-spec"
+.PD
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the data speculative loads after reload.
+This is effective only with \fB\-msched\-ar\-data\-spec\fR enabled.
+The default is 'enable'.
+.IP "\fB\-msched\-in\-control\-spec\fR" 4
+.IX Item "-msched-in-control-spec"
+.PD 0
+.IP "\fB\-mno\-sched\-in\-control\-spec\fR" 4
+.IX Item "-mno-sched-in-control-spec"
+.PD
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the control speculative loads.
+This is effective only with \fB\-msched\-control\-spec\fR enabled.
+The default is 'enable'.
+.IP "\fB\-msched\-ldc\fR" 4
+.IX Item "-msched-ldc"
+.PD 0
+.IP "\fB\-mno\-sched\-ldc\fR" 4
+.IX Item "-mno-sched-ldc"
+.PD
+(En/Dis)able use of simple data speculation checks ld.c .
+If disabled, only chk.a instructions will be emitted to check
+data speculative loads.
+The default is 'enable'.
+.IP "\fB\-mno\-sched\-control\-ldc\fR" 4
+.IX Item "-mno-sched-control-ldc"
+.PD 0
+.IP "\fB\-msched\-control\-ldc\fR" 4
+.IX Item "-msched-control-ldc"
+.PD
+(Dis/En)able use of ld.c instructions to check control speculative loads.
+If enabled, in case of control speculative load with no speculatively
+scheduled dependent instructions this load will be emitted as ld.sa and
+ld.c will be used to check it.
+The default is 'disable'.
+.IP "\fB\-mno\-sched\-spec\-verbose\fR" 4
+.IX Item "-mno-sched-spec-verbose"
+.PD 0
+.IP "\fB\-msched\-spec\-verbose\fR" 4
+.IX Item "-msched-spec-verbose"
+.PD
+(Dis/En)able printing of the information about speculative motions.
+.IP "\fB\-mno\-sched\-prefer\-non\-data\-spec\-insns\fR" 4
+.IX Item "-mno-sched-prefer-non-data-spec-insns"
+.PD 0
+.IP "\fB\-msched\-prefer\-non\-data\-spec\-insns\fR" 4
+.IX Item "-msched-prefer-non-data-spec-insns"
+.PD
+If enabled, data speculative instructions will be chosen for schedule
+only if there are no other choices at the moment. This will make
+the use of the data speculation much more conservative.
+The default is 'disable'.
+.IP "\fB\-mno\-sched\-prefer\-non\-control\-spec\-insns\fR" 4
+.IX Item "-mno-sched-prefer-non-control-spec-insns"
+.PD 0
+.IP "\fB\-msched\-prefer\-non\-control\-spec\-insns\fR" 4
+.IX Item "-msched-prefer-non-control-spec-insns"
+.PD
+If enabled, control speculative instructions will be chosen for schedule
+only if there are no other choices at the moment. This will make
+the use of the control speculation much more conservative.
+The default is 'disable'.
+.IP "\fB\-mno\-sched\-count\-spec\-in\-critical\-path\fR" 4
+.IX Item "-mno-sched-count-spec-in-critical-path"
+.PD 0
+.IP "\fB\-msched\-count\-spec\-in\-critical\-path\fR" 4
+.IX Item "-msched-count-spec-in-critical-path"
+.PD
+If enabled, speculative dependencies will be considered during
+computation of the instructions priorities. This will make the use of the
+speculation a bit more conservative.
+The default is 'disable'.
+.PP
+\fIM32C Options\fR
+.IX Subsection "M32C Options"
+.IP "\fB\-mcpu=\fR\fIname\fR" 4
+.IX Item "-mcpu=name"
+Select the \s-1CPU\s0 for which code is generated. \fIname\fR may be one of
+\&\fBr8c\fR for the R8C/Tiny series, \fBm16c\fR for the M16C (up to
+/60) series, \fBm32cm\fR for the M16C/80 series, or \fBm32c\fR for
+the M32C/80 series.
+.IP "\fB\-msim\fR" 4
+.IX Item "-msim"
+Specifies that the program will be run on the simulator. This causes
+an alternate runtime library to be linked in which supports, for
+example, file I/O. You must not use this option when generating
+programs that will run on real hardware; you must provide your own
+runtime library for whatever I/O functions are needed.
+.IP "\fB\-memregs=\fR\fInumber\fR" 4
+.IX Item "-memregs=number"
+Specifies the number of memory-based pseudo-registers \s-1GCC\s0 will use
+during code generation. These pseudo-registers will be used like real
+registers, so there is a tradeoff between \s-1GCC\s0's ability to fit the
+code into available registers, and the performance penalty of using
+memory instead of registers. Note that all modules in a program must
+be compiled with the same value for this option. Because of that, you
+must not use this option with the default runtime libraries gcc
+builds.
.PP
\fIM32R/D Options\fR
.IX Subsection "M32R/D Options"
@@ -6436,6 +9549,1071 @@ will only be used if a trap is not available.
.IX Item "-mno-flush-func"
Indicates that there is no \s-1OS\s0 function for flushing the cache.
.PP
+\fIM680x0 Options\fR
+.IX Subsection "M680x0 Options"
+.PP
+These are the \fB\-m\fR options defined for the 68000 series. The default
+values for these options depends on which style of 68000 was selected when
+the compiler was configured; the defaults for the most common choices are
+given below.
+.IP "\fB\-m68000\fR" 4
+.IX Item "-m68000"
+.PD 0
+.IP "\fB\-mc68000\fR" 4
+.IX Item "-mc68000"
+.PD
+Generate output for a 68000. This is the default
+when the compiler is configured for 68000\-based systems.
+.Sp
+Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core,
+including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
+.IP "\fB\-m68020\fR" 4
+.IX Item "-m68020"
+.PD 0
+.IP "\fB\-mc68020\fR" 4
+.IX Item "-mc68020"
+.PD
+Generate output for a 68020. This is the default
+when the compiler is configured for 68020\-based systems.
+.IP "\fB\-m68881\fR" 4
+.IX Item "-m68881"
+Generate output containing 68881 instructions for floating point.
+This is the default for most 68020 systems unless \fB\-\-nfp\fR was
+specified when the compiler was configured.
+.IP "\fB\-m68030\fR" 4
+.IX Item "-m68030"
+Generate output for a 68030. This is the default when the compiler is
+configured for 68030\-based systems.
+.IP "\fB\-m68040\fR" 4
+.IX Item "-m68040"
+Generate output for a 68040. This is the default when the compiler is
+configured for 68040\-based systems.
+.Sp
+This option inhibits the use of 68881/68882 instructions that have to be
+emulated by software on the 68040. Use this option if your 68040 does not
+have code to emulate those instructions.
+.IP "\fB\-m68060\fR" 4
+.IX Item "-m68060"
+Generate output for a 68060. This is the default when the compiler is
+configured for 68060\-based systems.
+.Sp
+This option inhibits the use of 68020 and 68881/68882 instructions that
+have to be emulated by software on the 68060. Use this option if your 68060
+does not have code to emulate those instructions.
+.IP "\fB\-mcpu32\fR" 4
+.IX Item "-mcpu32"
+Generate output for a \s-1CPU32\s0. This is the default
+when the compiler is configured for CPU32\-based systems.
+.Sp
+Use this option for microcontrollers with a
+\&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334,
+68336, 68340, 68341, 68349 and 68360.
+.IP "\fB\-m5200\fR" 4
+.IX Item "-m5200"
+Generate output for a 520X \*(L"coldfire\*(R" family cpu. This is the default
+when the compiler is configured for 520X\-based systems.
+.Sp
+Use this option for microcontroller with a 5200 core, including
+the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5202\s0.
+.IP "\fB\-mcfv4e\fR" 4
+.IX Item "-mcfv4e"
+Generate output for a ColdFire V4e family cpu (e.g. 547x/548x).
+This includes use of hardware floating point instructions.
+.IP "\fB\-m68020\-40\fR" 4
+.IX Item "-m68020-40"
+Generate output for a 68040, without using any of the new instructions.
+This results in code which can run relatively efficiently on either a
+68020/68881 or a 68030 or a 68040. The generated code does use the
+68881 instructions that are emulated on the 68040.
+.IP "\fB\-m68020\-60\fR" 4
+.IX Item "-m68020-60"
+Generate output for a 68060, without using any of the new instructions.
+This results in code which can run relatively efficiently on either a
+68020/68881 or a 68030 or a 68040. The generated code does use the
+68881 instructions that are emulated on the 68060.
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+Generate output containing library calls for floating point.
+\&\fBWarning:\fR the requisite libraries are not available for all m68k
+targets. Normally the facilities of the machine's usual C compiler are
+used, but this can't be done directly in cross\-compilation. You must
+make your own arrangements to provide suitable library functions for
+cross\-compilation. The embedded targets \fBm68k\-*\-aout\fR and
+\&\fBm68k\-*\-coff\fR do provide software floating point support.
+.IP "\fB\-mshort\fR" 4
+.IX Item "-mshort"
+Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
+Additionally, parameters passed on the stack are also aligned to a
+16\-bit boundary even on targets whose \s-1API\s0 mandates promotion to 32\-bit.
+.IP "\fB\-mnobitfield\fR" 4
+.IX Item "-mnobitfield"
+Do not use the bit-field instructions. The \fB\-m68000\fR, \fB\-mcpu32\fR
+and \fB\-m5200\fR options imply \fB\-mnobitfield\fR.
+.IP "\fB\-mbitfield\fR" 4
+.IX Item "-mbitfield"
+Do use the bit-field instructions. The \fB\-m68020\fR option implies
+\&\fB\-mbitfield\fR. This is the default if you use a configuration
+designed for a 68020.
+.IP "\fB\-mrtd\fR" 4
+.IX Item "-mrtd"
+Use a different function-calling convention, in which functions
+that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR
+instruction, which pops their arguments while returning. This
+saves one instruction in the caller since there is no need to pop
+the arguments there.
+.Sp
+This calling convention is incompatible with the one normally
+used on Unix, so you cannot use it if you need to call libraries
+compiled with the Unix compiler.
+.Sp
+Also, you must provide function prototypes for all functions that
+take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
+otherwise incorrect code will be generated for calls to those
+functions.
+.Sp
+In addition, seriously incorrect code will result if you call a
+function with too many arguments. (Normally, extra arguments are
+harmlessly ignored.)
+.Sp
+The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030,
+68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200.
+.IP "\fB\-malign\-int\fR" 4
+.IX Item "-malign-int"
+.PD 0
+.IP "\fB\-mno\-align\-int\fR" 4
+.IX Item "-mno-align-int"
+.PD
+Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR,
+\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit
+boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR).
+Aligning variables on 32\-bit boundaries produces code that runs somewhat
+faster on processors with 32\-bit busses at the expense of more memory.
+.Sp
+\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 will
+align structures containing the above types differently than
+most published application binary interface specifications for the m68k.
+.IP "\fB\-mpcrel\fR" 4
+.IX Item "-mpcrel"
+Use the pc-relative addressing mode of the 68000 directly, instead of
+using a global offset table. At present, this option implies \fB\-fpic\fR,
+allowing at most a 16\-bit offset for pc-relative addressing. \fB\-fPIC\fR is
+not presently supported with \fB\-mpcrel\fR, though this could be supported for
+68020 and higher processors.
+.IP "\fB\-mno\-strict\-align\fR" 4
+.IX Item "-mno-strict-align"
+.PD 0
+.IP "\fB\-mstrict\-align\fR" 4
+.IX Item "-mstrict-align"
+.PD
+Do not (do) assume that unaligned memory references will be handled by
+the system.
+.IP "\fB\-msep\-data\fR" 4
+.IX Item "-msep-data"
+Generate code that allows the data segment to be located in a different
+area of memory from the text segment. This allows for execute in place in
+an environment without virtual memory management. This option implies
+\&\fB\-fPIC\fR.
+.IP "\fB\-mno\-sep\-data\fR" 4
+.IX Item "-mno-sep-data"
+Generate code that assumes that the data segment follows the text segment.
+This is the default.
+.IP "\fB\-mid\-shared\-library\fR" 4
+.IX Item "-mid-shared-library"
+Generate code that supports shared libraries via the library \s-1ID\s0 method.
+This allows for execute in place and shared libraries in an environment
+without virtual memory management. This option implies \fB\-fPIC\fR.
+.IP "\fB\-mno\-id\-shared\-library\fR" 4
+.IX Item "-mno-id-shared-library"
+Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
+This is the default.
+.IP "\fB\-mshared\-library\-id=n\fR" 4
+.IX Item "-mshared-library-id=n"
+Specified the identification number of the \s-1ID\s0 based shared library being
+compiled. Specifying a value of 0 will generate more compact code, specifying
+other values will force the allocation of that number to the current
+library but is no more space or time efficient than omitting this option.
+.PP
+\fIM68hc1x Options\fR
+.IX Subsection "M68hc1x Options"
+.PP
+These are the \fB\-m\fR options defined for the 68hc11 and 68hc12
+microcontrollers. The default values for these options depends on
+which style of microcontroller was selected when the compiler was configured;
+the defaults for the most common choices are given below.
+.IP "\fB\-m6811\fR" 4
+.IX Item "-m6811"
+.PD 0
+.IP "\fB\-m68hc11\fR" 4
+.IX Item "-m68hc11"
+.PD
+Generate output for a 68HC11. This is the default
+when the compiler is configured for 68HC11\-based systems.
+.IP "\fB\-m6812\fR" 4
+.IX Item "-m6812"
+.PD 0
+.IP "\fB\-m68hc12\fR" 4
+.IX Item "-m68hc12"
+.PD
+Generate output for a 68HC12. This is the default
+when the compiler is configured for 68HC12\-based systems.
+.IP "\fB\-m68S12\fR" 4
+.IX Item "-m68S12"
+.PD 0
+.IP "\fB\-m68hcs12\fR" 4
+.IX Item "-m68hcs12"
+.PD
+Generate output for a 68HCS12.
+.IP "\fB\-mauto\-incdec\fR" 4
+.IX Item "-mauto-incdec"
+Enable the use of 68HC12 pre and post auto-increment and auto-decrement
+addressing modes.
+.IP "\fB\-minmax\fR" 4
+.IX Item "-minmax"
+.PD 0
+.IP "\fB\-nominmax\fR" 4
+.IX Item "-nominmax"
+.PD
+Enable the use of 68HC12 min and max instructions.
+.IP "\fB\-mlong\-calls\fR" 4
+.IX Item "-mlong-calls"
+.PD 0
+.IP "\fB\-mno\-long\-calls\fR" 4
+.IX Item "-mno-long-calls"
+.PD
+Treat all calls as being far away (near). If calls are assumed to be
+far away, the compiler will use the \f(CW\*(C`call\*(C'\fR instruction to
+call a function and the \f(CW\*(C`rtc\*(C'\fR instruction for returning.
+.IP "\fB\-mshort\fR" 4
+.IX Item "-mshort"
+Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
+.IP "\fB\-msoft\-reg\-count=\fR\fIcount\fR" 4
+.IX Item "-msoft-reg-count=count"
+Specify the number of pseudo-soft registers which are used for the
+code generation. The maximum number is 32. Using more pseudo-soft
+register may or may not result in better code depending on the program.
+The default is 4 for 68HC11 and 2 for 68HC12.
+.PP
+\fIMCore Options\fR
+.IX Subsection "MCore Options"
+.PP
+These are the \fB\-m\fR options defined for the Motorola M*Core
+processors.
+.IP "\fB\-mhardlit\fR" 4
+.IX Item "-mhardlit"
+.PD 0
+.IP "\fB\-mno\-hardlit\fR" 4
+.IX Item "-mno-hardlit"
+.PD
+Inline constants into the code stream if it can be done in two
+instructions or less.
+.IP "\fB\-mdiv\fR" 4
+.IX Item "-mdiv"
+.PD 0
+.IP "\fB\-mno\-div\fR" 4
+.IX Item "-mno-div"
+.PD
+Use the divide instruction. (Enabled by default).
+.IP "\fB\-mrelax\-immediate\fR" 4
+.IX Item "-mrelax-immediate"
+.PD 0
+.IP "\fB\-mno\-relax\-immediate\fR" 4
+.IX Item "-mno-relax-immediate"
+.PD
+Allow arbitrary sized immediates in bit operations.
+.IP "\fB\-mwide\-bitfields\fR" 4
+.IX Item "-mwide-bitfields"
+.PD 0
+.IP "\fB\-mno\-wide\-bitfields\fR" 4
+.IX Item "-mno-wide-bitfields"
+.PD
+Always treat bit-fields as int\-sized.
+.IP "\fB\-m4byte\-functions\fR" 4
+.IX Item "-m4byte-functions"
+.PD 0
+.IP "\fB\-mno\-4byte\-functions\fR" 4
+.IX Item "-mno-4byte-functions"
+.PD
+Force all functions to be aligned to a four byte boundary.
+.IP "\fB\-mcallgraph\-data\fR" 4
+.IX Item "-mcallgraph-data"
+.PD 0
+.IP "\fB\-mno\-callgraph\-data\fR" 4
+.IX Item "-mno-callgraph-data"
+.PD
+Emit callgraph information.
+.IP "\fB\-mslow\-bytes\fR" 4
+.IX Item "-mslow-bytes"
+.PD 0
+.IP "\fB\-mno\-slow\-bytes\fR" 4
+.IX Item "-mno-slow-bytes"
+.PD
+Prefer word access when reading byte quantities.
+.IP "\fB\-mlittle\-endian\fR" 4
+.IX Item "-mlittle-endian"
+.PD 0
+.IP "\fB\-mbig\-endian\fR" 4
+.IX Item "-mbig-endian"
+.PD
+Generate code for a little endian target.
+.IP "\fB\-m210\fR" 4
+.IX Item "-m210"
+.PD 0
+.IP "\fB\-m340\fR" 4
+.IX Item "-m340"
+.PD
+Generate code for the 210 processor.
+.PP
+\fI\s-1MIPS\s0 Options\fR
+.IX Subsection "MIPS Options"
+.IP "\fB\-EB\fR" 4
+.IX Item "-EB"
+Generate big-endian code.
+.IP "\fB\-EL\fR" 4
+.IX Item "-EL"
+Generate little-endian code. This is the default for \fBmips*el\-*\-*\fR
+configurations.
+.IP "\fB\-march=\fR\fIarch\fR" 4
+.IX Item "-march=arch"
+Generate code that will run on \fIarch\fR, which can be the name of a
+generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor.
+The \s-1ISA\s0 names are:
+\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR,
+\&\fBmips32\fR, \fBmips32r2\fR, and \fBmips64\fR.
+The processor names are:
+\&\fB4kc\fR, \fB4km\fR, \fB4kp\fR,
+\&\fB5kc\fR, \fB5kf\fR,
+\&\fB20kc\fR,
+\&\fB24k\fR, \fB24kc\fR, \fB24kf\fR, \fB24kx\fR,
+\&\fBm4k\fR,
+\&\fBorion\fR,
+\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR,
+\&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR,
+\&\fBrm7000\fR, \fBrm9000\fR,
+\&\fBsb1\fR,
+\&\fBsr71000\fR,
+\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR,
+\&\fBvr5000\fR, \fBvr5400\fR and \fBvr5500\fR.
+The special value \fBfrom-abi\fR selects the
+most compatible architecture for the selected \s-1ABI\s0 (that is,
+\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs).
+.Sp
+In processor names, a final \fB000\fR can be abbreviated as \fBk\fR
+(for example, \fB\-march=r2k\fR). Prefixes are optional, and
+\&\fBvr\fR may be written \fBr\fR.
+.Sp
+\&\s-1GCC\s0 defines two macros based on the value of this option. The first
+is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as
+a string. The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR,
+where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR.
+For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR
+to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR.
+.Sp
+Note that the \fB_MIPS_ARCH\fR macro uses the processor names given
+above. In other words, it will have the full prefix and will not
+abbreviate \fB000\fR as \fBk\fR. In the case of \fBfrom-abi\fR,
+the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or
+\&\fB\*(L"mips3\*(R"\fR). It names the default architecture when no
+\&\fB\-march\fR option is given.
+.IP "\fB\-mtune=\fR\fIarch\fR" 4
+.IX Item "-mtune=arch"
+Optimize for \fIarch\fR. Among other things, this option controls
+the way instructions are scheduled, and the perceived cost of arithmetic
+operations. The list of \fIarch\fR values is the same as for
+\&\fB\-march\fR.
+.Sp
+When this option is not used, \s-1GCC\s0 will optimize for the processor
+specified by \fB\-march\fR. By using \fB\-march\fR and
+\&\fB\-mtune\fR together, it is possible to generate code that will
+run on a family of processors, but optimize the code for one
+particular member of that family.
+.Sp
+\&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and
+\&\fB_MIPS_TUNE_\fR\fIfoo\fR, which work in the same way as the
+\&\fB\-march\fR ones described above.
+.IP "\fB\-mips1\fR" 4
+.IX Item "-mips1"
+Equivalent to \fB\-march=mips1\fR.
+.IP "\fB\-mips2\fR" 4
+.IX Item "-mips2"
+Equivalent to \fB\-march=mips2\fR.
+.IP "\fB\-mips3\fR" 4
+.IX Item "-mips3"
+Equivalent to \fB\-march=mips3\fR.
+.IP "\fB\-mips4\fR" 4
+.IX Item "-mips4"
+Equivalent to \fB\-march=mips4\fR.
+.IP "\fB\-mips32\fR" 4
+.IX Item "-mips32"
+Equivalent to \fB\-march=mips32\fR.
+.IP "\fB\-mips32r2\fR" 4
+.IX Item "-mips32r2"
+Equivalent to \fB\-march=mips32r2\fR.
+.IP "\fB\-mips64\fR" 4
+.IX Item "-mips64"
+Equivalent to \fB\-march=mips64\fR.
+.IP "\fB\-mips16\fR" 4
+.IX Item "-mips16"
+.PD 0
+.IP "\fB\-mno\-mips16\fR" 4
+.IX Item "-mno-mips16"
+.PD
+Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targetting a
+\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it will make use of the MIPS16e \s-1ASE\s0.
+.IP "\fB\-mabi=32\fR" 4
+.IX Item "-mabi=32"
+.PD 0
+.IP "\fB\-mabi=o64\fR" 4
+.IX Item "-mabi=o64"
+.IP "\fB\-mabi=n32\fR" 4
+.IX Item "-mabi=n32"
+.IP "\fB\-mabi=64\fR" 4
+.IX Item "-mabi=64"
+.IP "\fB\-mabi=eabi\fR" 4
+.IX Item "-mabi=eabi"
+.PD
+Generate code for the given \s-1ABI\s0.
+.Sp
+Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally
+generates 64\-bit code when you select a 64\-bit architecture, but you
+can use \fB\-mgp32\fR to get 32\-bit code instead.
+.Sp
+For information about the O64 \s-1ABI\s0, see
+<\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>.
+.IP "\fB\-mabicalls\fR" 4
+.IX Item "-mabicalls"
+.PD 0
+.IP "\fB\-mno\-abicalls\fR" 4
+.IX Item "-mno-abicalls"
+.PD
+Generate (do not generate) code that is suitable for SVR4\-style
+dynamic objects. \fB\-mabicalls\fR is the default for SVR4\-based
+systems.
+.IP "\fB\-mshared\fR" 4
+.IX Item "-mshared"
+.PD 0
+.IP "\fB\-mno\-shared\fR" 4
+.IX Item "-mno-shared"
+.PD
+Generate (do not generate) code that is fully position\-independent,
+and that can therefore be linked into shared libraries. This option
+only affects \fB\-mabicalls\fR.
+.Sp
+All \fB\-mabicalls\fR code has traditionally been position\-independent,
+regardless of options like \fB\-fPIC\fR and \fB\-fpic\fR. However,
+as an extension, the \s-1GNU\s0 toolchain allows executables to use absolute
+accesses for locally-binding symbols. It can also use shorter \s-1GP\s0
+initialization sequences and generate direct calls to locally-defined
+functions. This mode is selected by \fB\-mno\-shared\fR.
+.Sp
+\&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates
+objects that can only be linked by the \s-1GNU\s0 linker. However, the option
+does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0
+of relocatable objects. Using \fB\-mno\-shared\fR will generally make
+executables both smaller and quicker.
+.Sp
+\&\fB\-mshared\fR is the default.
+.IP "\fB\-mxgot\fR" 4
+.IX Item "-mxgot"
+.PD 0
+.IP "\fB\-mno\-xgot\fR" 4
+.IX Item "-mno-xgot"
+.PD
+Lift (do not lift) the usual restrictions on the size of the global
+offset table.
+.Sp
+\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0.
+While this is relatively efficient, it will only work if the \s-1GOT\s0
+is smaller than about 64k. Anything larger will cause the linker
+to report an error such as:
+.Sp
+.Vb 1
+\& relocation truncated to fit: R_MIPS_GOT16 foobar
+.Ve
+.Sp
+If this happens, you should recompile your code with \fB\-mxgot\fR.
+It should then work with very large GOTs, although it will also be
+less efficient, since it will take three instructions to fetch the
+value of a global symbol.
+.Sp
+Note that some linkers can create multiple GOTs. If you have such a
+linker, you should only need to use \fB\-mxgot\fR when a single object
+file accesses more than 64k's worth of \s-1GOT\s0 entries. Very few do.
+.Sp
+These options have no effect unless \s-1GCC\s0 is generating position
+independent code.
+.IP "\fB\-mgp32\fR" 4
+.IX Item "-mgp32"
+Assume that general-purpose registers are 32 bits wide.
+.IP "\fB\-mgp64\fR" 4
+.IX Item "-mgp64"
+Assume that general-purpose registers are 64 bits wide.
+.IP "\fB\-mfp32\fR" 4
+.IX Item "-mfp32"
+Assume that floating-point registers are 32 bits wide.
+.IP "\fB\-mfp64\fR" 4
+.IX Item "-mfp64"
+Assume that floating-point registers are 64 bits wide.
+.IP "\fB\-mhard\-float\fR" 4
+.IX Item "-mhard-float"
+Use floating-point coprocessor instructions.
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+Do not use floating-point coprocessor instructions. Implement
+floating-point calculations using library calls instead.
+.IP "\fB\-msingle\-float\fR" 4
+.IX Item "-msingle-float"
+Assume that the floating-point coprocessor only supports single-precision
+operations.
+.IP "\fB\-mdouble\-float\fR" 4
+.IX Item "-mdouble-float"
+Assume that the floating-point coprocessor supports double-precision
+operations. This is the default.
+.IP "\fB\-mdsp\fR" 4
+.IX Item "-mdsp"
+.PD 0
+.IP "\fB\-mno\-dsp\fR" 4
+.IX Item "-mno-dsp"
+.PD
+Use (do not use) the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0.
+.IP "\fB\-mpaired\-single\fR" 4
+.IX Item "-mpaired-single"
+.PD 0
+.IP "\fB\-mno\-paired\-single\fR" 4
+.IX Item "-mno-paired-single"
+.PD
+Use (do not use) paired-single floating-point instructions.
+ This option can only be used
+when generating 64\-bit code and requires hardware floating-point
+support to be enabled.
+.IP "\fB\-mips3d\fR" 4
+.IX Item "-mips3d"
+.PD 0
+.IP "\fB\-mno\-mips3d\fR" 4
+.IX Item "-mno-mips3d"
+.PD
+Use (do not use) the \s-1MIPS\-3D\s0 \s-1ASE\s0.
+The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR.
+.IP "\fB\-mlong64\fR" 4
+.IX Item "-mlong64"
+Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See \fB\-mlong32\fR for
+an explanation of the default and the way that the pointer size is
+determined.
+.IP "\fB\-mlong32\fR" 4
+.IX Item "-mlong32"
+Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide.
+.Sp
+The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on
+the \s-1ABI\s0. All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0
+uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use
+32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs,
+or the same size as integer registers, whichever is smaller.
+.IP "\fB\-msym32\fR" 4
+.IX Item "-msym32"
+.PD 0
+.IP "\fB\-mno\-sym32\fR" 4
+.IX Item "-mno-sym32"
+.PD
+Assume (do not assume) that all symbols have 32\-bit values, regardless
+of the selected \s-1ABI\s0. This option is useful in combination with
+\&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0
+to generate shorter and faster references to symbolic addresses.
+.IP "\fB\-G\fR \fInum\fR" 4
+.IX Item "-G num"
+Put global and static items less than or equal to \fInum\fR bytes into
+the small data or bss section instead of the normal data or bss section.
+This allows the data to be accessed using a single instruction.
+.Sp
+All modules should be compiled with the same \fB\-G\fR \fInum\fR
+value.
+.IP "\fB\-membedded\-data\fR" 4
+.IX Item "-membedded-data"
+.PD 0
+.IP "\fB\-mno\-embedded\-data\fR" 4
+.IX Item "-mno-embedded-data"
+.PD
+Allocate variables to the read-only data section first if possible, then
+next in the small data section if possible, otherwise in data. This gives
+slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required
+when executing, and thus may be preferred for some embedded systems.
+.IP "\fB\-muninit\-const\-in\-rodata\fR" 4
+.IX Item "-muninit-const-in-rodata"
+.PD 0
+.IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4
+.IX Item "-mno-uninit-const-in-rodata"
+.PD
+Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section.
+This option is only meaningful in conjunction with \fB\-membedded\-data\fR.
+.IP "\fB\-msplit\-addresses\fR" 4
+.IX Item "-msplit-addresses"
+.PD 0
+.IP "\fB\-mno\-split\-addresses\fR" 4
+.IX Item "-mno-split-addresses"
+.PD
+Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler
+relocation operators. This option has been superseded by
+\&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility.
+.IP "\fB\-mexplicit\-relocs\fR" 4
+.IX Item "-mexplicit-relocs"
+.PD 0
+.IP "\fB\-mno\-explicit\-relocs\fR" 4
+.IX Item "-mno-explicit-relocs"
+.PD
+Use (do not use) assembler relocation operators when dealing with symbolic
+addresses. The alternative, selected by \fB\-mno\-explicit\-relocs\fR,
+is to use assembler macros instead.
+.Sp
+\&\fB\-mexplicit\-relocs\fR is the default if \s-1GCC\s0 was configured
+to use an assembler that supports relocation operators.
+.IP "\fB\-mcheck\-zero\-division\fR" 4
+.IX Item "-mcheck-zero-division"
+.PD 0
+.IP "\fB\-mno\-check\-zero\-division\fR" 4
+.IX Item "-mno-check-zero-division"
+.PD
+Trap (do not trap) on integer division by zero. The default is
+\&\fB\-mcheck\-zero\-division\fR.
+.IP "\fB\-mdivide\-traps\fR" 4
+.IX Item "-mdivide-traps"
+.PD 0
+.IP "\fB\-mdivide\-breaks\fR" 4
+.IX Item "-mdivide-breaks"
+.PD
+\&\s-1MIPS\s0 systems check for division by zero by generating either a
+conditional trap or a break instruction. Using traps results in
+smaller code, but is only supported on \s-1MIPS\s0 \s-1II\s0 and later. Also, some
+versions of the Linux kernel have a bug that prevents trap from
+generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR). Use \fB\-mdivide\-traps\fR to
+allow conditional traps on architectures that support them and
+\&\fB\-mdivide\-breaks\fR to force the use of breaks.
+.Sp
+The default is usually \fB\-mdivide\-traps\fR, but this can be
+overridden at configure time using \fB\-\-with\-divide=breaks\fR.
+Divide-by-zero checks can be completely disabled using
+\&\fB\-mno\-check\-zero\-division\fR.
+.IP "\fB\-mmemcpy\fR" 4
+.IX Item "-mmemcpy"
+.PD 0
+.IP "\fB\-mno\-memcpy\fR" 4
+.IX Item "-mno-memcpy"
+.PD
+Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block
+moves. The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline
+most constant-sized copies.
+.IP "\fB\-mlong\-calls\fR" 4
+.IX Item "-mlong-calls"
+.PD 0
+.IP "\fB\-mno\-long\-calls\fR" 4
+.IX Item "-mno-long-calls"
+.PD
+Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction. Calling
+functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller
+and callee to be in the same 256 megabyte segment.
+.Sp
+This option has no effect on abicalls code. The default is
+\&\fB\-mno\-long\-calls\fR.
+.IP "\fB\-mmad\fR" 4
+.IX Item "-mmad"
+.PD 0
+.IP "\fB\-mno\-mad\fR" 4
+.IX Item "-mno-mad"
+.PD
+Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR
+instructions, as provided by the R4650 \s-1ISA\s0.
+.IP "\fB\-mfused\-madd\fR" 4
+.IX Item "-mfused-madd"
+.PD 0
+.IP "\fB\-mno\-fused\-madd\fR" 4
+.IX Item "-mno-fused-madd"
+.PD
+Enable (disable) use of the floating point multiply-accumulate
+instructions, when they are available. The default is
+\&\fB\-mfused\-madd\fR.
+.Sp
+When multiply-accumulate instructions are used, the intermediate
+product is calculated to infinite precision and is not subject to
+the \s-1FCSR\s0 Flush to Zero bit. This may be undesirable in some
+circumstances.
+.IP "\fB\-nocpp\fR" 4
+.IX Item "-nocpp"
+Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user
+assembler files (with a \fB.s\fR suffix) when assembling them.
+.IP "\fB\-mfix\-r4000\fR" 4
+.IX Item "-mfix-r4000"
+.PD 0
+.IP "\fB\-mno\-fix\-r4000\fR" 4
+.IX Item "-mno-fix-r4000"
+.PD
+Work around certain R4000 \s-1CPU\s0 errata:
+.RS 4
+.IP "\-" 4
+A double-word or a variable shift may give an incorrect result if executed
+immediately after starting an integer division.
+.IP "\-" 4
+A double-word or a variable shift may give an incorrect result if executed
+while an integer multiplication is in progress.
+.IP "\-" 4
+An integer division may give an incorrect result if started in a delay slot
+of a taken branch or a jump.
+.RE
+.RS 4
+.RE
+.IP "\fB\-mfix\-r4400\fR" 4
+.IX Item "-mfix-r4400"
+.PD 0
+.IP "\fB\-mno\-fix\-r4400\fR" 4
+.IX Item "-mno-fix-r4400"
+.PD
+Work around certain R4400 \s-1CPU\s0 errata:
+.RS 4
+.IP "\-" 4
+A double-word or a variable shift may give an incorrect result if executed
+immediately after starting an integer division.
+.RE
+.RS 4
+.RE
+.IP "\fB\-mfix\-vr4120\fR" 4
+.IX Item "-mfix-vr4120"
+.PD 0
+.IP "\fB\-mno\-fix\-vr4120\fR" 4
+.IX Item "-mno-fix-vr4120"
+.PD
+Work around certain \s-1VR4120\s0 errata:
+.RS 4
+.IP "\-" 4
+\&\f(CW\*(C`dmultu\*(C'\fR does not always produce the correct result.
+.IP "\-" 4
+\&\f(CW\*(C`div\*(C'\fR and \f(CW\*(C`ddiv\*(C'\fR do not always produce the correct result if one
+of the operands is negative.
+.RE
+.RS 4
+.Sp
+The workarounds for the division errata rely on special functions in
+\&\fIlibgcc.a\fR. At present, these functions are only provided by
+the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations.
+.Sp
+Other \s-1VR4120\s0 errata require a nop to be inserted between certain pairs of
+instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itself.
+.RE
+.IP "\fB\-mfix\-vr4130\fR" 4
+.IX Item "-mfix-vr4130"
+Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The
+workarounds are implemented by the assembler rather than by \s-1GCC\s0,
+although \s-1GCC\s0 will avoid using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the
+\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR
+instructions are available instead.
+.IP "\fB\-mfix\-sb1\fR" 4
+.IX Item "-mfix-sb1"
+.PD 0
+.IP "\fB\-mno\-fix\-sb1\fR" 4
+.IX Item "-mno-fix-sb1"
+.PD
+Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata.
+(This flag currently works around the \s-1SB\-1\s0 revision 2
+\&\*(L"F1\*(R" and \*(L"F2\*(R" floating point errata.)
+.IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4
+.IX Item "-mflush-func=func"
+.PD 0
+.IP "\fB\-mno\-flush\-func\fR" 4
+.IX Item "-mno-flush-func"
+.PD
+Specifies the function to call to flush the I and D caches, or to not
+call any such function. If called, the function must take the same
+arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the
+memory range for which the cache is being flushed, the size of the
+memory range, and the number 3 (to flush both caches). The default
+depends on the target \s-1GCC\s0 was configured for, but commonly is either
+\&\fB_flush_func\fR or \fB_\|_cpu_flush\fR.
+.IP "\fB\-mbranch\-likely\fR" 4
+.IX Item "-mbranch-likely"
+.PD 0
+.IP "\fB\-mno\-branch\-likely\fR" 4
+.IX Item "-mno-branch-likely"
+.PD
+Enable or disable use of Branch Likely instructions, regardless of the
+default for the selected architecture. By default, Branch Likely
+instructions may be generated if they are supported by the selected
+architecture. An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures
+and processors which implement those architectures; for those, Branch
+Likely instructions will not be generated by default because the \s-1MIPS32\s0
+and \s-1MIPS64\s0 architectures specifically deprecate their use.
+.IP "\fB\-mfp\-exceptions\fR" 4
+.IX Item "-mfp-exceptions"
+.PD 0
+.IP "\fB\-mno\-fp\-exceptions\fR" 4
+.IX Item "-mno-fp-exceptions"
+.PD
+Specifies whether \s-1FP\s0 exceptions are enabled. This affects how we schedule
+\&\s-1FP\s0 instructions for some processors. The default is that \s-1FP\s0 exceptions are
+enabled.
+.Sp
+For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting
+64\-bit code, then we can use both \s-1FP\s0 pipes. Otherwise, we can only use one
+\&\s-1FP\s0 pipe.
+.IP "\fB\-mvr4130\-align\fR" 4
+.IX Item "-mvr4130-align"
+.PD 0
+.IP "\fB\-mno\-vr4130\-align\fR" 4
+.IX Item "-mno-vr4130-align"
+.PD
+The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two
+instructions together if the first one is 8\-byte aligned. When this
+option is enabled, \s-1GCC\s0 will align pairs of instructions that it
+thinks should execute in parallel.
+.Sp
+This option only has an effect when optimizing for the \s-1VR4130\s0.
+It normally makes code faster, but at the expense of making it bigger.
+It is enabled by default at optimization level \fB\-O3\fR.
+.PP
+\fI\s-1MMIX\s0 Options\fR
+.IX Subsection "MMIX Options"
+.PP
+These options are defined for the \s-1MMIX:\s0
+.IP "\fB\-mlibfuncs\fR" 4
+.IX Item "-mlibfuncs"
+.PD 0
+.IP "\fB\-mno\-libfuncs\fR" 4
+.IX Item "-mno-libfuncs"
+.PD
+Specify that intrinsic library functions are being compiled, passing all
+values in registers, no matter the size.
+.IP "\fB\-mepsilon\fR" 4
+.IX Item "-mepsilon"
+.PD 0
+.IP "\fB\-mno\-epsilon\fR" 4
+.IX Item "-mno-epsilon"
+.PD
+Generate floating-point comparison instructions that compare with respect
+to the \f(CW\*(C`rE\*(C'\fR epsilon register.
+.IP "\fB\-mabi=mmixware\fR" 4
+.IX Item "-mabi=mmixware"
+.PD 0
+.IP "\fB\-mabi=gnu\fR" 4
+.IX Item "-mabi=gnu"
+.PD
+Generate code that passes function parameters and return values that (in
+the called function) are seen as registers \f(CW$0\fR and up, as opposed to
+the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up.
+.IP "\fB\-mzero\-extend\fR" 4
+.IX Item "-mzero-extend"
+.PD 0
+.IP "\fB\-mno\-zero\-extend\fR" 4
+.IX Item "-mno-zero-extend"
+.PD
+When reading data from memory in sizes shorter than 64 bits, use (do not
+use) zero-extending load instructions by default, rather than
+sign-extending ones.
+.IP "\fB\-mknuthdiv\fR" 4
+.IX Item "-mknuthdiv"
+.PD 0
+.IP "\fB\-mno\-knuthdiv\fR" 4
+.IX Item "-mno-knuthdiv"
+.PD
+Make the result of a division yielding a remainder have the same sign as
+the divisor. With the default, \fB\-mno\-knuthdiv\fR, the sign of the
+remainder follows the sign of the dividend. Both methods are
+arithmetically valid, the latter being almost exclusively used.
+.IP "\fB\-mtoplevel\-symbols\fR" 4
+.IX Item "-mtoplevel-symbols"
+.PD 0
+.IP "\fB\-mno\-toplevel\-symbols\fR" 4
+.IX Item "-mno-toplevel-symbols"
+.PD
+Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly
+code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive.
+.IP "\fB\-melf\fR" 4
+.IX Item "-melf"
+Generate an executable in the \s-1ELF\s0 format, rather than the default
+\&\fBmmo\fR format used by the \fBmmix\fR simulator.
+.IP "\fB\-mbranch\-predict\fR" 4
+.IX Item "-mbranch-predict"
+.PD 0
+.IP "\fB\-mno\-branch\-predict\fR" 4
+.IX Item "-mno-branch-predict"
+.PD
+Use (do not use) the probable-branch instructions, when static branch
+prediction indicates a probable branch.
+.IP "\fB\-mbase\-addresses\fR" 4
+.IX Item "-mbase-addresses"
+.PD 0
+.IP "\fB\-mno\-base\-addresses\fR" 4
+.IX Item "-mno-base-addresses"
+.PD
+Generate (do not generate) code that uses \fIbase addresses\fR. Using a
+base address automatically generates a request (handled by the assembler
+and the linker) for a constant to be set up in a global register. The
+register is used for one or more base address requests within the range 0
+to 255 from the value held in the register. The generally leads to short
+and fast code, but the number of different data items that can be
+addressed is limited. This means that a program that uses lots of static
+data may require \fB\-mno\-base\-addresses\fR.
+.IP "\fB\-msingle\-exit\fR" 4
+.IX Item "-msingle-exit"
+.PD 0
+.IP "\fB\-mno\-single\-exit\fR" 4
+.IX Item "-mno-single-exit"
+.PD
+Force (do not force) generated code to have a single exit point in each
+function.
+.PP
+\fI\s-1MN10300\s0 Options\fR
+.IX Subsection "MN10300 Options"
+.PP
+These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures:
+.IP "\fB\-mmult\-bug\fR" 4
+.IX Item "-mmult-bug"
+Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0
+processors. This is the default.
+.IP "\fB\-mno\-mult\-bug\fR" 4
+.IX Item "-mno-mult-bug"
+Do not generate code to avoid bugs in the multiply instructions for the
+\&\s-1MN10300\s0 processors.
+.IP "\fB\-mam33\fR" 4
+.IX Item "-mam33"
+Generate code which uses features specific to the \s-1AM33\s0 processor.
+.IP "\fB\-mno\-am33\fR" 4
+.IX Item "-mno-am33"
+Do not generate code which uses features specific to the \s-1AM33\s0 processor. This
+is the default.
+.IP "\fB\-mreturn\-pointer\-on\-d0\fR" 4
+.IX Item "-mreturn-pointer-on-d0"
+When generating a function which returns a pointer, return the pointer
+in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR. Otherwise, the pointer is returned
+only in a0, and attempts to call such functions without a prototype
+would result in errors. Note that this option is on by default; use
+\&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it.
+.IP "\fB\-mno\-crt0\fR" 4
+.IX Item "-mno-crt0"
+Do not link in the C run-time initialization object file.
+.IP "\fB\-mrelax\fR" 4
+.IX Item "-mrelax"
+Indicate to the linker that it should perform a relaxation optimization pass
+to shorten branches, calls and absolute memory addresses. This option only
+has an effect when used on the command line for the final link step.
+.Sp
+This option makes symbolic debugging impossible.
+.PP
+\fI\s-1MT\s0 Options\fR
+.IX Subsection "MT Options"
+.PP
+These \fB\-m\fR options are defined for Morpho \s-1MT\s0 architectures:
+.IP "\fB\-march=\fR\fIcpu-type\fR" 4
+.IX Item "-march=cpu-type"
+Generate code that will run on \fIcpu-type\fR, which is the name of a system
+representing a certain processor type. Possible values for
+\&\fIcpu-type\fR are \fBms1\-64\-001\fR, \fBms1\-16\-002\fR,
+\&\fBms1\-16\-003\fR and \fBms2\fR.
+.Sp
+When this option is not used, the default is \fB\-march=ms1\-16\-002\fR.
+.IP "\fB\-mbacc\fR" 4
+.IX Item "-mbacc"
+Use byte loads and stores when generating code.
+.IP "\fB\-mno\-bacc\fR" 4
+.IX Item "-mno-bacc"
+Do not use byte loads and stores when generating code.
+.IP "\fB\-msim\fR" 4
+.IX Item "-msim"
+Use simulator runtime
+.IP "\fB\-mno\-crt0\fR" 4
+.IX Item "-mno-crt0"
+Do not link in the C run-time initialization object file
+\&\fIcrti.o\fR. Other run-time initialization and termination files
+such as \fIstartup.o\fR and \fIexit.o\fR are still included on the
+linker command line.
+.PP
+\fI\s-1PDP\-11\s0 Options\fR
+.IX Subsection "PDP-11 Options"
+.PP
+These options are defined for the \s-1PDP\-11:\s0
+.IP "\fB\-mfpu\fR" 4
+.IX Item "-mfpu"
+Use hardware \s-1FPP\s0 floating point. This is the default. (\s-1FIS\s0 floating
+point on the \s-1PDP\-11/40\s0 is not supported.)
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+Do not use hardware floating point.
+.IP "\fB\-mac0\fR" 4
+.IX Item "-mac0"
+Return floating-point results in ac0 (fr0 in Unix assembler syntax).
+.IP "\fB\-mno\-ac0\fR" 4
+.IX Item "-mno-ac0"
+Return floating-point results in memory. This is the default.
+.IP "\fB\-m40\fR" 4
+.IX Item "-m40"
+Generate code for a \s-1PDP\-11/40\s0.
+.IP "\fB\-m45\fR" 4
+.IX Item "-m45"
+Generate code for a \s-1PDP\-11/45\s0. This is the default.
+.IP "\fB\-m10\fR" 4
+.IX Item "-m10"
+Generate code for a \s-1PDP\-11/10\s0.
+.IP "\fB\-mbcopy\-builtin\fR" 4
+.IX Item "-mbcopy-builtin"
+Use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. This is the
+default.
+.IP "\fB\-mbcopy\fR" 4
+.IX Item "-mbcopy"
+Do not use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory.
+.IP "\fB\-mint16\fR" 4
+.IX Item "-mint16"
+.PD 0
+.IP "\fB\-mno\-int32\fR" 4
+.IX Item "-mno-int32"
+.PD
+Use 16\-bit \f(CW\*(C`int\*(C'\fR. This is the default.
+.IP "\fB\-mint32\fR" 4
+.IX Item "-mint32"
+.PD 0
+.IP "\fB\-mno\-int16\fR" 4
+.IX Item "-mno-int16"
+.PD
+Use 32\-bit \f(CW\*(C`int\*(C'\fR.
+.IP "\fB\-mfloat64\fR" 4
+.IX Item "-mfloat64"
+.PD 0
+.IP "\fB\-mno\-float32\fR" 4
+.IX Item "-mno-float32"
+.PD
+Use 64\-bit \f(CW\*(C`float\*(C'\fR. This is the default.
+.IP "\fB\-mfloat32\fR" 4
+.IX Item "-mfloat32"
+.PD 0
+.IP "\fB\-mno\-float64\fR" 4
+.IX Item "-mno-float64"
+.PD
+Use 32\-bit \f(CW\*(C`float\*(C'\fR.
+.IP "\fB\-mabshi\fR" 4
+.IX Item "-mabshi"
+Use \f(CW\*(C`abshi2\*(C'\fR pattern. This is the default.
+.IP "\fB\-mno\-abshi\fR" 4
+.IX Item "-mno-abshi"
+Do not use \f(CW\*(C`abshi2\*(C'\fR pattern.
+.IP "\fB\-mbranch\-expensive\fR" 4
+.IX Item "-mbranch-expensive"
+Pretend that branches are expensive. This is for experimenting with
+code generation only.
+.IP "\fB\-mbranch\-cheap\fR" 4
+.IX Item "-mbranch-cheap"
+Do not pretend that branches are expensive. This is the default.
+.IP "\fB\-msplit\fR" 4
+.IX Item "-msplit"
+Generate code for a system with split I&D.
+.IP "\fB\-mno\-split\fR" 4
+.IX Item "-mno-split"
+Generate code for a system without split I&D. This is the default.
+.IP "\fB\-munix\-asm\fR" 4
+.IX Item "-munix-asm"
+Use Unix assembler syntax. This is the default when configured for
+\&\fBpdp11\-*\-bsd\fR.
+.IP "\fB\-mdec\-asm\fR" 4
+.IX Item "-mdec-asm"
+Use \s-1DEC\s0 assembler syntax. This is the default when configured for any
+\&\s-1PDP\-11\s0 target other than \fBpdp11\-*\-bsd\fR.
+.PP
+\fIPowerPC Options\fR
+.IX Subsection "PowerPC Options"
+.PP
+These are listed under
+.PP
\fI\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options\fR
.IX Subsection "IBM RS/6000 and PowerPC Options"
.PP
@@ -6465,13 +10643,25 @@ These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerP
.IX Item "-mpowerpc64"
.IP "\fB\-mno\-powerpc64\fR" 4
.IX Item "-mno-powerpc64"
+.IP "\fB\-mmfcrf\fR" 4
+.IX Item "-mmfcrf"
+.IP "\fB\-mno\-mfcrf\fR" 4
+.IX Item "-mno-mfcrf"
+.IP "\fB\-mpopcntb\fR" 4
+.IX Item "-mpopcntb"
+.IP "\fB\-mno\-popcntb\fR" 4
+.IX Item "-mno-popcntb"
+.IP "\fB\-mfprnd\fR" 4
+.IX Item "-mfprnd"
+.IP "\fB\-mno\-fprnd\fR" 4
+.IX Item "-mno-fprnd"
.PD
\&\s-1GCC\s0 supports two related instruction set architectures for the
\&\s-1RS/6000\s0 and PowerPC. The \fI\s-1POWER\s0\fR instruction set are those
instructions supported by the \fBrios\fR chip set used in the original
\&\s-1RS/6000\s0 systems and the \fIPowerPC\fR instruction set is the
-architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
-the \s-1IBM\s0 4xx microprocessors.
+architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and
+the \s-1IBM\s0 4xx, 6xx, and follow-on microprocessors.
.Sp
Neither architecture is a subset of the other. However there is a
large common subset of instructions supported by both. An \s-1MQ\s0
@@ -6499,6 +10689,18 @@ General Purpose group, including floating-point square root. Specifying
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
.Sp
+The \fB\-mmfcrf\fR option allows \s-1GCC\s0 to generate the move from
+condition register field instruction implemented on the \s-1POWER4\s0
+processor and other processors that support the PowerPC V2.01
+architecture.
+The \fB\-mpopcntb\fR option allows \s-1GCC\s0 to generate the popcount and
+double precision \s-1FP\s0 reciprocal estimate instruction implemented on the
+\&\s-1POWER5\s0 processor and other processors that support the PowerPC V2.02
+architecture.
+The \fB\-mfprnd\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 round to
+integer instructions implemented on the \s-1POWER5+\s0 processor and other
+processors that support the PowerPC V2.03 architecture.
+.Sp
The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional
64\-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64\-bit, doubleword quantities. \s-1GCC\s0 defaults to
@@ -6537,10 +10739,11 @@ Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR,
\&\fB601\fR, \fB602\fR, \fB603\fR, \fB603e\fR, \fB604\fR,
\&\fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, \fB7400\fR,
\&\fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR,
-\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBcommon\fR, \fBec603e\fR, \fBG3\fR,
+\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBec603e\fR, \fBG3\fR,
\&\fBG4\fR, \fBG5\fR, \fBpower\fR, \fBpower2\fR, \fBpower3\fR,
-\&\fBpower4\fR, \fBpower5\fR, \fBpowerpc\fR, \fBpowerpc64\fR,
-\&\fBrios\fR, \fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64a\fR.
+\&\fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, \fBpower6\fR,
+\&\fBcommon\fR, \fBpowerpc\fR, \fBpowerpc64\fR,
+\&\fBrios\fR, \fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64\fR.
.Sp
\&\fB\-mcpu=common\fR selects a completely generic processor. Code
generated under this option will run on any \s-1POWER\s0 or PowerPC processor.
@@ -6559,19 +10762,21 @@ those options will run best on that processor, and may not run at all on
others.
.Sp
The \fB\-mcpu\fR options automatically enable or disable the
-following options: \fB\-maltivec\fR, \fB\-mhard\-float\fR,
-\&\fB\-mmfcrf\fR, \fB\-mmultiple\fR, \fB\-mnew\-mnemonics\fR,
-\&\fB\-mpower\fR, \fB\-mpower2\fR, \fB\-mpowerpc64\fR,
-\&\fB\-mpowerpc\-gpopt\fR, \fB\-mpowerpc\-gfxopt\fR,
-\&\fB\-mstring\fR. The particular options set for any particular \s-1CPU\s0
-will vary between compiler versions, depending on what setting seems
-to produce optimal code for that \s-1CPU\s0; it doesn't necessarily reflect
-the actual hardware's capabilities. If you wish to set an individual
-option to a particular value, you may specify it after the
-\&\fB\-mcpu\fR option, like \fB\-mcpu=970 \-mno\-altivec\fR.
+following options: \fB\-maltivec\fR, \fB\-mfprnd\fR,
+\&\fB\-mhard\-float\fR, \fB\-mmfcrf\fR, \fB\-mmultiple\fR,
+\&\fB\-mnew\-mnemonics\fR, \fB\-mpopcntb\fR, \fB\-mpower\fR,
+\&\fB\-mpower2\fR, \fB\-mpowerpc64\fR, \fB\-mpowerpc\-gpopt\fR,
+\&\fB\-mpowerpc\-gfxopt\fR, \fB\-mstring\fR, \fB\-mmulhw\fR, \fB\-mdlmzb\fR.
+The particular options
+set for any particular \s-1CPU\s0 will vary between compiler versions,
+depending on what setting seems to produce optimal code for that \s-1CPU\s0;
+it doesn't necessarily reflect the actual hardware's capabilities. If
+you wish to set an individual option to a particular value, you may
+specify it after the \fB\-mcpu\fR option, like \fB\-mcpu=970
+\&\-mno\-altivec\fR.
.Sp
On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are
-not enabled or disabled by the \fB\-mcpu\fR option at present, since
+not enabled or disabled by the \fB\-mcpu\fR option at present because
\&\s-1AIX\s0 does not have full support for these options. You may still
enable or disable them individually if you're sure it'll work in your
environment.
@@ -6584,48 +10789,101 @@ values for \fIcpu_type\fR are used for \fB\-mtune\fR as for
\&\fB\-mcpu\fR. If both are specified, the code generated will use the
architecture, registers, and mnemonics set by \fB\-mcpu\fR, but the
scheduling parameters set by \fB\-mtune\fR.
+.IP "\fB\-mswdiv\fR" 4
+.IX Item "-mswdiv"
+.PD 0
+.IP "\fB\-mno\-swdiv\fR" 4
+.IX Item "-mno-swdiv"
+.PD
+Generate code to compute division as reciprocal estimate and iterative
+refinement, creating opportunities for increased throughput. This
+feature requires: optional PowerPC Graphics instruction set for single
+precision and \s-1FRE\s0 instruction for double precision, assuming divides
+cannot generate user-visible traps, and the domain values not include
+Infinities, denormals or zero denominator.
.IP "\fB\-maltivec\fR" 4
.IX Item "-maltivec"
.PD 0
.IP "\fB\-mno\-altivec\fR" 4
.IX Item "-mno-altivec"
.PD
-These switches enable or disable the use of built-in functions that
-allow access to the AltiVec instruction set. You may also need to set
+Generate code that uses (does not use) AltiVec instructions, and also
+enable the use of built-in functions that allow more direct access to
+the AltiVec instruction set. You may also need to set
\&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0
enhancements.
-.IP "\fB\-mabi=spe\fR" 4
-.IX Item "-mabi=spe"
-Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change
-the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current
-\&\s-1ABI\s0.
-.IP "\fB\-mabi=no\-spe\fR" 4
-.IX Item "-mabi=no-spe"
-Disable Booke \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0.
-.IP "\fB\-misel=\fR\fIyes/no\fR" 4
-.IX Item "-misel=yes/no"
-.PD 0
+.IP "\fB\-mvrsave\fR" 4
+.IX Item "-mvrsave"
+.PD 0
+.IP "\fB\-mno\-vrsave\fR" 4
+.IX Item "-mno-vrsave"
+.PD
+Generate \s-1VRSAVE\s0 instructions when generating AltiVec code.
+.IP "\fB\-msecure\-plt\fR" 4
+.IX Item "-msecure-plt"
+Generate code that allows ld and ld.so to build executables and shared
+libraries with non-exec .plt and .got sections. This is a PowerPC
+32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
+.IP "\fB\-mbss\-plt\fR" 4
+.IX Item "-mbss-plt"
+Generate code that uses a \s-1BSS\s0 .plt section that ld.so fills in, and
+requires .plt and .got sections that are both writable and executable.
+This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
.IP "\fB\-misel\fR" 4
.IX Item "-misel"
+.PD 0
+.IP "\fB\-mno\-isel\fR" 4
+.IX Item "-mno-isel"
.PD
This switch enables or disables the generation of \s-1ISEL\s0 instructions.
-.IP "\fB\-mspe=\fR\fIyes/no\fR" 4
-.IX Item "-mspe=yes/no"
-.PD 0
+.IP "\fB\-misel=\fR\fIyes/no\fR" 4
+.IX Item "-misel=yes/no"
+This switch has been deprecated. Use \fB\-misel\fR and
+\&\fB\-mno\-isel\fR instead.
.IP "\fB\-mspe\fR" 4
.IX Item "-mspe"
+.PD 0
+.IP "\fB\-mno\-spe\fR" 4
+.IX Item "-mno-spe"
.PD
This switch enables or disables the generation of \s-1SPE\s0 simd
instructions.
-.IP "\fB\-mfloat\-gprs=\fR\fIyes/no\fR" 4
-.IX Item "-mfloat-gprs=yes/no"
+.IP "\fB\-mspe=\fR\fIyes/no\fR" 4
+.IX Item "-mspe=yes/no"
+This option has been deprecated. Use \fB\-mspe\fR and
+\&\fB\-mno\-spe\fR instead.
+.IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4
+.IX Item "-mfloat-gprs=yes/single/double/no"
.PD 0
.IP "\fB\-mfloat\-gprs\fR" 4
.IX Item "-mfloat-gprs"
.PD
This switch enables or disables the generation of floating point
operations on the general purpose registers for architectures that
-support it. This option is currently only available on the \s-1MPC8540\s0.
+support it.
+.Sp
+The argument \fIyes\fR or \fIsingle\fR enables the use of
+single-precision floating point operations.
+.Sp
+The argument \fIdouble\fR enables the use of single and
+double-precision floating point operations.
+.Sp
+The argument \fIno\fR disables floating point operations on the
+general purpose registers.
+.Sp
+This option is currently only available on the MPC854x.
+.IP "\fB\-m32\fR" 4
+.IX Item "-m32"
+.PD 0
+.IP "\fB\-m64\fR" 4
+.IX Item "-m64"
+.PD
+Generate code for 32\-bit or 64\-bit environments of Darwin and \s-1SVR4\s0
+targets (including GNU/Linux). The 32\-bit environment sets int, long
+and pointer to 32 bits and generates code that runs on any PowerPC
+variant. The 64\-bit environment sets int to 32 bits and long and
+pointer to 64 bits, and generates code for PowerPC64, as for
+\&\fB\-mpowerpc64\fR.
.IP "\fB\-mfull\-toc\fR" 4
.IX Item "-mfull-toc"
.PD 0
@@ -6676,20 +10934,22 @@ implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR.
.IP "\fB\-mno\-xl\-compat\fR" 4
.IX Item "-mno-xl-compat"
.PD
-Produce code that conforms more closely to \s-1IBM\s0 \s-1XLC\s0 semantics when using
-AIX-compatible \s-1ABI\s0. Pass floating-point arguments to prototyped
-functions beyond the register save area (\s-1RSA\s0) on the stack in addition
-to argument FPRs. Do not assume that most significant double in 128
-bit long double value is properly rounded when comparing values.
+Produce code that conforms more closely to \s-1IBM\s0 \s-1XL\s0 compiler semantics
+when using AIX-compatible \s-1ABI\s0. Pass floating-point arguments to
+prototyped functions beyond the register save area (\s-1RSA\s0) on the stack
+in addition to argument FPRs. Do not assume that most significant
+double in 128\-bit long double value is properly rounded when comparing
+values and converting to double. Use \s-1XL\s0 symbol names for long double
+support routines.
.Sp
The \s-1AIX\s0 calling convention was extended but not initially documented to
handle an obscure K&R C case of calling a function that takes the
-address of its arguments with fewer arguments than declared. \s-1AIX\s0 \s-1XL\s0
+address of its arguments with fewer arguments than declared. \s-1IBM\s0 \s-1XL\s0
compilers access floating point arguments which do not fit in the
\&\s-1RSA\s0 from the stack when a subroutine is compiled without
optimization. Because always storing floating-point arguments on the
stack is inefficient and rarely needed, this option is not enabled by
-default and only is necessary when calling subroutines compiled by \s-1AIX\s0
+default and only is necessary when calling subroutines compiled by \s-1IBM\s0
\&\s-1XL\s0 compilers without optimization.
.IP "\fB\-mpe\fR" 4
.IX Item "-mpe"
@@ -6707,11 +10967,14 @@ option are incompatible.
.IP "\fB\-malign\-power\fR" 4
.IX Item "-malign-power"
.PD
-On \s-1AIX\s0, Darwin, and 64\-bit PowerPC GNU/Linux, the option
+On \s-1AIX\s0, 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option
\&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger
types, such as floating-point doubles, on their natural size-based boundary.
The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified
alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0.
+.Sp
+On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR
+is not supported.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
.PD 0
@@ -6770,6 +11033,25 @@ signals may get corrupted data.
Generate code that uses (does not use) the floating point multiply and
accumulate instructions. These instructions are generated by default if
hardware floating is used.
+.IP "\fB\-mmulhw\fR" 4
+.IX Item "-mmulhw"
+.PD 0
+.IP "\fB\-mno\-mulhw\fR" 4
+.IX Item "-mno-mulhw"
+.PD
+Generate code that uses (does not use) the half-word multiply and
+multiply-accumulate instructions on the \s-1IBM\s0 405 and 440 processors.
+These instructions are generated by default when targetting those
+processors.
+.IP "\fB\-mdlmzb\fR" 4
+.IX Item "-mdlmzb"
+.PD 0
+.IP "\fB\-mno\-dlmzb\fR" 4
+.IX Item "-mno-dlmzb"
+.PD
+Generate code that uses (does not use) the string-search \fBdlmzb\fR
+instruction on the \s-1IBM\s0 405 and 440 processors. This instruction is
+generated by default when targetting those processors.
.IP "\fB\-mno\-bit\-align\fR" 4
.IX Item "-mno-bit-align"
.PD 0
@@ -6867,7 +11149,7 @@ by the target during instruction scheduling. The argument
.IP "\fB\-minsert\-sched\-nops=\fR\fIscheme\fR" 4
.IX Item "-minsert-sched-nops=scheme"
This option controls which nop insertion scheme will be used during
-the second scheduling pass. The argument \fIscheme\fR takes one of the
+the second scheduling pass. The argument \fIscheme\fR takes one of the
following values:
\&\fIno\fR: Don't insert nops.
\&\fIpad\fR: Pad with nops any dispatch group which has vacant issue slots,
@@ -6912,14 +11194,27 @@ Return all structures in memory (as specified by the \s-1AIX\s0 \s-1ABI\s0).
.IX Item "-msvr4-struct-return"
Return structures smaller than 8 bytes in registers (as specified by the
\&\s-1SVR4\s0 \s-1ABI\s0).
-.IP "\fB\-mabi=altivec\fR" 4
-.IX Item "-mabi=altivec"
-Extend the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 extensions. This does not
-change the default \s-1ABI\s0, instead it adds the AltiVec \s-1ABI\s0 extensions to
-the current \s-1ABI\s0.
-.IP "\fB\-mabi=no\-altivec\fR" 4
-.IX Item "-mabi=no-altivec"
-Disable AltiVec \s-1ABI\s0 extensions for the current \s-1ABI\s0.
+.IP "\fB\-mabi=\fR\fIabi-type\fR" 4
+.IX Item "-mabi=abi-type"
+Extend the current \s-1ABI\s0 with a particular extension, or remove such extension.
+Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR,
+\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR.
+.IP "\fB\-mabi=spe\fR" 4
+.IX Item "-mabi=spe"
+Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change
+the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current
+\&\s-1ABI\s0.
+.IP "\fB\-mabi=no\-spe\fR" 4
+.IX Item "-mabi=no-spe"
+Disable Booke \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0.
+.IP "\fB\-mabi=ibmlongdouble\fR" 4
+.IX Item "-mabi=ibmlongdouble"
+Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended precision long double.
+This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
+.IP "\fB\-mabi=ieeelongdouble\fR" 4
+.IX Item "-mabi=ieeelongdouble"
+Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended precision long double.
+This is a PowerPC 32\-bit Linux \s-1ABI\s0 option.
.IP "\fB\-mprototype\fR" 4
.IX Item "-mprototype"
.PD 0
@@ -7014,9 +11309,9 @@ compile code the same as \fB\-msdata=eabi\fR, otherwise compile code the
same as \fB\-msdata=sysv\fR.
.IP "\fB\-msdata\-data\fR" 4
.IX Item "-msdata-data"
-On System V.4 and embedded PowerPC systems, put small global and static
-data in the \fB.sdata\fR section. Put small uninitialized global and
-static data in the \fB.sbss\fR section. Do not use register \f(CW\*(C`r13\*(C'\fR
+On System V.4 and embedded PowerPC systems, put small global
+data in the \fB.sdata\fR section. Put small uninitialized global
+data in the \fB.sbss\fR section. Do not use register \f(CW\*(C`r13\*(C'\fR
to address small data however. This is the default behavior unless
other \fB\-msdata\fR options are used.
.IP "\fB\-msdata=none\fR" 4
@@ -7049,10 +11344,13 @@ names in the assembly language output using symbolic forms.
.IP "\fB\-mno\-longcall\fR" 4
.IX Item "-mno-longcall"
.PD
-Default to making all function calls via pointers, so that functions
-which reside further than 64 megabytes (67,108,864 bytes) from the
-current location can be called. This setting can be overridden by the
-\&\f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma longcall(0)\*(C'\fR.
+By default assume that all calls are far away so that a longer more
+expensive calling sequence is required. This is required for calls
+further than 32 megabytes (33,554,432 bytes) from the current location.
+A short call will be generated if the compiler knows
+the call cannot be that far away. This setting can be overridden by
+the \f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma
+longcall(0)\*(C'\fR.
.Sp
Some linkers are capable of detecting out-of-range calls and generating
glue code on the fly. On these systems, long calls are unnecessary and
@@ -7060,6 +11358,16 @@ generate slower code. As of this writing, the \s-1AIX\s0 linker can do this,
as can the \s-1GNU\s0 linker for PowerPC/64. It is planned to add this feature
to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well.
.Sp
+On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR will generate \*(L"jbsr
+callee, L42\*(R", plus a \*(L"branch island\*(R" (glue code). The two target
+addresses represent the callee and the \*(L"branch island\*(R". The
+Darwin/PPC linker will prefer the first address and generate a \*(L"bl
+callee\*(R" if the \s-1PPC\s0 \*(L"bl\*(R" instruction will reach the callee directly;
+otherwise, the linker will generate \*(L"bl L42\*(R" to call the \*(L"branch
+island\*(R". The \*(L"branch island\*(R" is appended to the body of the
+calling function; it computes the full 32\-bit address of the callee
+and jumps to it.
+.Sp
On Mach-O (Darwin) systems, this option directs the compiler emit to
the glue for every direct call, and the Darwin linker decides whether
to use or discard it.
@@ -7071,1618 +11379,227 @@ when the linker is known to generate glue.
Adds support for multithreading with the \fIpthreads\fR library.
This option sets flags for both the preprocessor and linker.
.PP
-\fIDarwin Options\fR
-.IX Subsection "Darwin Options"
-.PP
-These options are defined for all architectures running the Darwin operating
-system. They are useful for compatibility with other Mac \s-1OS\s0 compilers.
-.IP "\fB\-all_load\fR" 4
-.IX Item "-all_load"
-Loads all members of static archive libraries.
-See man \fIld\fR\|(1) for more information.
-.IP "\fB\-arch_errors_fatal\fR" 4
-.IX Item "-arch_errors_fatal"
-Cause the errors having to do with files that have the wrong architecture
-to be fatal.
-.IP "\fB\-bind_at_load\fR" 4
-.IX Item "-bind_at_load"
-Causes the output file to be marked such that the dynamic linker will
-bind all undefined references when the file is loaded or launched.
-.IP "\fB\-bundle\fR" 4
-.IX Item "-bundle"
-Produce a Mach-o bundle format file.
-See man \fIld\fR\|(1) for more information.
-.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4
-.IX Item "-bundle_loader executable"
-This specifies the \fIexecutable\fR that will be loading the build
-output file being linked. See man \fIld\fR\|(1) for more information.
-.IP "\fB\-allowable_client\fR \fIclient_name\fR" 4
-.IX Item "-allowable_client client_name"
-.PD 0
-.IP "\fB\-arch_only\fR" 4
-.IX Item "-arch_only"
-.IP "\fB\-client_name\fR" 4
-.IX Item "-client_name"
-.IP "\fB\-compatibility_version\fR" 4
-.IX Item "-compatibility_version"
-.IP "\fB\-current_version\fR" 4
-.IX Item "-current_version"
-.IP "\fB\-dependency\-file\fR" 4
-.IX Item "-dependency-file"
-.IP "\fB\-dylib_file\fR" 4
-.IX Item "-dylib_file"
-.IP "\fB\-dylinker_install_name\fR" 4
-.IX Item "-dylinker_install_name"
-.IP "\fB\-dynamic\fR" 4
-.IX Item "-dynamic"
-.IP "\fB\-dynamiclib\fR" 4
-.IX Item "-dynamiclib"
-.IP "\fB\-exported_symbols_list\fR" 4
-.IX Item "-exported_symbols_list"
-.IP "\fB\-filelist\fR" 4
-.IX Item "-filelist"
-.IP "\fB\-flat_namespace\fR" 4
-.IX Item "-flat_namespace"
-.IP "\fB\-force_cpusubtype_ALL\fR" 4
-.IX Item "-force_cpusubtype_ALL"
-.IP "\fB\-force_flat_namespace\fR" 4
-.IX Item "-force_flat_namespace"
-.IP "\fB\-headerpad_max_install_names\fR" 4
-.IX Item "-headerpad_max_install_names"
-.IP "\fB\-image_base\fR" 4
-.IX Item "-image_base"
-.IP "\fB\-init\fR" 4
-.IX Item "-init"
-.IP "\fB\-install_name\fR" 4
-.IX Item "-install_name"
-.IP "\fB\-keep_private_externs\fR" 4
-.IX Item "-keep_private_externs"
-.IP "\fB\-multi_module\fR" 4
-.IX Item "-multi_module"
-.IP "\fB\-multiply_defined\fR" 4
-.IX Item "-multiply_defined"
-.IP "\fB\-multiply_defined_unused\fR" 4
-.IX Item "-multiply_defined_unused"
-.IP "\fB\-noall_load\fR" 4
-.IX Item "-noall_load"
-.IP "\fB\-nofixprebinding\fR" 4
-.IX Item "-nofixprebinding"
-.IP "\fB\-nomultidefs\fR" 4
-.IX Item "-nomultidefs"
-.IP "\fB\-noprebind\fR" 4
-.IX Item "-noprebind"
-.IP "\fB\-noseglinkedit\fR" 4
-.IX Item "-noseglinkedit"
-.IP "\fB\-pagezero_size\fR" 4
-.IX Item "-pagezero_size"
-.IP "\fB\-prebind\fR" 4
-.IX Item "-prebind"
-.IP "\fB\-prebind_all_twolevel_modules\fR" 4
-.IX Item "-prebind_all_twolevel_modules"
-.IP "\fB\-private_bundle\fR" 4
-.IX Item "-private_bundle"
-.IP "\fB\-read_only_relocs\fR" 4
-.IX Item "-read_only_relocs"
-.IP "\fB\-sectalign\fR" 4
-.IX Item "-sectalign"
-.IP "\fB\-sectobjectsymbols\fR" 4
-.IX Item "-sectobjectsymbols"
-.IP "\fB\-whyload\fR" 4
-.IX Item "-whyload"
-.IP "\fB\-seg1addr\fR" 4
-.IX Item "-seg1addr"
-.IP "\fB\-sectcreate\fR" 4
-.IX Item "-sectcreate"
-.IP "\fB\-sectobjectsymbols\fR" 4
-.IX Item "-sectobjectsymbols"
-.IP "\fB\-sectorder\fR" 4
-.IX Item "-sectorder"
-.IP "\fB\-seg_addr_table\fR" 4
-.IX Item "-seg_addr_table"
-.IP "\fB\-seg_addr_table_filename\fR" 4
-.IX Item "-seg_addr_table_filename"
-.IP "\fB\-seglinkedit\fR" 4
-.IX Item "-seglinkedit"
-.IP "\fB\-segprot\fR" 4
-.IX Item "-segprot"
-.IP "\fB\-segs_read_only_addr\fR" 4
-.IX Item "-segs_read_only_addr"
-.IP "\fB\-segs_read_write_addr\fR" 4
-.IX Item "-segs_read_write_addr"
-.IP "\fB\-single_module\fR" 4
-.IX Item "-single_module"
-.IP "\fB\-static\fR" 4
-.IX Item "-static"
-.IP "\fB\-sub_library\fR" 4
-.IX Item "-sub_library"
-.IP "\fB\-sub_umbrella\fR" 4
-.IX Item "-sub_umbrella"
-.IP "\fB\-twolevel_namespace\fR" 4
-.IX Item "-twolevel_namespace"
-.IP "\fB\-umbrella\fR" 4
-.IX Item "-umbrella"
-.IP "\fB\-undefined\fR" 4
-.IX Item "-undefined"
-.IP "\fB\-unexported_symbols_list\fR" 4
-.IX Item "-unexported_symbols_list"
-.IP "\fB\-weak_reference_mismatches\fR" 4
-.IX Item "-weak_reference_mismatches"
-.IP "\fB\-whatsloaded\fR" 4
-.IX Item "-whatsloaded"
-.PD
-These options are available for Darwin linker. Darwin linker man page
-describes them in detail.
+\fIS/390 and zSeries Options\fR
+.IX Subsection "S/390 and zSeries Options"
.PP
-\fI\s-1MIPS\s0 Options\fR
-.IX Subsection "MIPS Options"
-.IP "\fB\-EB\fR" 4
-.IX Item "-EB"
-Generate big-endian code.
-.IP "\fB\-EL\fR" 4
-.IX Item "-EL"
-Generate little-endian code. This is the default for \fBmips*el\-*\-*\fR
-configurations.
-.IP "\fB\-march=\fR\fIarch\fR" 4
-.IX Item "-march=arch"
-Generate code that will run on \fIarch\fR, which can be the name of a
-generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor.
-The \s-1ISA\s0 names are:
-\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR,
-\&\fBmips32\fR, \fBmips32r2\fR, and \fBmips64\fR.
-The processor names are:
-\&\fB4kc\fR, \fB4kp\fR, \fB5kc\fR, \fB20kc\fR,
-\&\fBm4k\fR,
-\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR,
-\&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR, \fBrm7000\fR,
-\&\fBrm9000\fR,
-\&\fBorion\fR,
-\&\fBsb1\fR,
-\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4300\fR,
-\&\fBvr5000\fR, \fBvr5400\fR and \fBvr5500\fR.
-The special value \fBfrom-abi\fR selects the
-most compatible architecture for the selected \s-1ABI\s0 (that is,
-\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs).
-.Sp
-In processor names, a final \fB000\fR can be abbreviated as \fBk\fR
-(for example, \fB\-march=r2k\fR). Prefixes are optional, and
-\&\fBvr\fR may be written \fBr\fR.
-.Sp
-\&\s-1GCC\s0 defines two macros based on the value of this option. The first
-is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as
-a string. The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR,
-where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR.
-For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR
-to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR.
-.Sp
-Note that the \fB_MIPS_ARCH\fR macro uses the processor names given
-above. In other words, it will have the full prefix and will not
-abbreviate \fB000\fR as \fBk\fR. In the case of \fBfrom-abi\fR,
-the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or
-\&\fB\*(L"mips3\*(R"\fR). It names the default architecture when no
-\&\fB\-march\fR option is given.
-.IP "\fB\-mtune=\fR\fIarch\fR" 4
-.IX Item "-mtune=arch"
-Optimize for \fIarch\fR. Among other things, this option controls
-the way instructions are scheduled, and the perceived cost of arithmetic
-operations. The list of \fIarch\fR values is the same as for
-\&\fB\-march\fR.
-.Sp
-When this option is not used, \s-1GCC\s0 will optimize for the processor
-specified by \fB\-march\fR. By using \fB\-march\fR and
-\&\fB\-mtune\fR together, it is possible to generate code that will
-run on a family of processors, but optimize the code for one
-particular member of that family.
-.Sp
-\&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and
-\&\fB_MIPS_TUNE_\fR\fIfoo\fR, which work in the same way as the
-\&\fB\-march\fR ones described above.
-.IP "\fB\-mips1\fR" 4
-.IX Item "-mips1"
-Equivalent to \fB\-march=mips1\fR.
-.IP "\fB\-mips2\fR" 4
-.IX Item "-mips2"
-Equivalent to \fB\-march=mips2\fR.
-.IP "\fB\-mips3\fR" 4
-.IX Item "-mips3"
-Equivalent to \fB\-march=mips3\fR.
-.IP "\fB\-mips4\fR" 4
-.IX Item "-mips4"
-Equivalent to \fB\-march=mips4\fR.
-.IP "\fB\-mips32\fR" 4
-.IX Item "-mips32"
-Equivalent to \fB\-march=mips32\fR.
-.IP "\fB\-mips32r2\fR" 4
-.IX Item "-mips32r2"
-Equivalent to \fB\-march=mips32r2\fR.
-.IP "\fB\-mips64\fR" 4
-.IX Item "-mips64"
-Equivalent to \fB\-march=mips64\fR.
-.IP "\fB\-mips16\fR" 4
-.IX Item "-mips16"
-.PD 0
-.IP "\fB\-mno\-mips16\fR" 4
-.IX Item "-mno-mips16"
-.PD
-Use (do not use) the \s-1MIPS16\s0 \s-1ISA\s0.
-.IP "\fB\-mabi=32\fR" 4
-.IX Item "-mabi=32"
-.PD 0
-.IP "\fB\-mabi=o64\fR" 4
-.IX Item "-mabi=o64"
-.IP "\fB\-mabi=n32\fR" 4
-.IX Item "-mabi=n32"
-.IP "\fB\-mabi=64\fR" 4
-.IX Item "-mabi=64"
-.IP "\fB\-mabi=eabi\fR" 4
-.IX Item "-mabi=eabi"
-.PD
-Generate code for the given \s-1ABI\s0.
-.Sp
-Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally
-generates 64\-bit code when you select a 64\-bit architecture, but you
-can use \fB\-mgp32\fR to get 32\-bit code instead.
-.IP "\fB\-mabicalls\fR" 4
-.IX Item "-mabicalls"
-.PD 0
-.IP "\fB\-mno\-abicalls\fR" 4
-.IX Item "-mno-abicalls"
-.PD
-Generate (do not generate) SVR4\-style position-independent code.
-\&\fB\-mabicalls\fR is the default for SVR4\-based systems.
-.IP "\fB\-mxgot\fR" 4
-.IX Item "-mxgot"
-.PD 0
-.IP "\fB\-mno\-xgot\fR" 4
-.IX Item "-mno-xgot"
-.PD
-Lift (do not lift) the usual restrictions on the size of the global
-offset table.
-.Sp
-\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0.
-While this is relatively efficient, it will only work if the \s-1GOT\s0
-is smaller than about 64k. Anything larger will cause the linker
-to report an error such as:
-.Sp
-.Vb 1
-\& relocation truncated to fit: R_MIPS_GOT16 foobar
-.Ve
-.Sp
-If this happens, you should recompile your code with \fB\-mxgot\fR.
-It should then work with very large GOTs, although it will also be
-less efficient, since it will take three instructions to fetch the
-value of a global symbol.
-.Sp
-Note that some linkers can create multiple GOTs. If you have such a
-linker, you should only need to use \fB\-mxgot\fR when a single object
-file accesses more than 64k's worth of \s-1GOT\s0 entries. Very few do.
-.Sp
-These options have no effect unless \s-1GCC\s0 is generating position
-independent code.
-.IP "\fB\-membedded\-pic\fR" 4
-.IX Item "-membedded-pic"
-.PD 0
-.IP "\fB\-mno\-embedded\-pic\fR" 4
-.IX Item "-mno-embedded-pic"
-.PD
-Generate (do not generate) position-independent code suitable for some
-embedded systems. All calls are made using \s-1PC\s0 relative addresses, and
-all data is addressed using the \f(CW$gp\fR register. No more than 65536
-bytes of global data may be used. This requires \s-1GNU\s0 as and \s-1GNU\s0 ld,
-which do most of the work.
-.IP "\fB\-mgp32\fR" 4
-.IX Item "-mgp32"
-Assume that general-purpose registers are 32 bits wide.
-.IP "\fB\-mgp64\fR" 4
-.IX Item "-mgp64"
-Assume that general-purpose registers are 64 bits wide.
-.IP "\fB\-mfp32\fR" 4
-.IX Item "-mfp32"
-Assume that floating-point registers are 32 bits wide.
-.IP "\fB\-mfp64\fR" 4
-.IX Item "-mfp64"
-Assume that floating-point registers are 64 bits wide.
+These are the \fB\-m\fR options defined for the S/390 and zSeries architecture.
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
-Use floating-point coprocessor instructions.
+.PD 0
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
-Do not use floating-point coprocessor instructions. Implement
-floating-point calculations using library calls instead.
-.IP "\fB\-msingle\-float\fR" 4
-.IX Item "-msingle-float"
-Assume that the floating-point coprocessor only supports single-precision
-operations.
-.IP "\fB\-mdouble\-float\fR" 4
-.IX Item "-mdouble-float"
-Assume that the floating-point coprocessor supports double-precision
-operations. This is the default.
-.IP "\fB\-mint64\fR" 4
-.IX Item "-mint64"
-Force \f(CW\*(C`int\*(C'\fR and \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See
-\&\fB\-mlong32\fR for an explanation of the default and the way
-that the pointer size is determined.
-.IP "\fB\-mlong64\fR" 4
-.IX Item "-mlong64"
-Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See \fB\-mlong32\fR for
-an explanation of the default and the way that the pointer size is
-determined.
-.IP "\fB\-mlong32\fR" 4
-.IX Item "-mlong32"
-Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide.
-.Sp
-The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on
-the \s-1ABI\s0. All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0
-uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use
-32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs,
-or the same size as integer registers, whichever is smaller.
-.IP "\fB\-G\fR \fInum\fR" 4
-.IX Item "-G num"
-Put global and static items less than or equal to \fInum\fR bytes into
-the small data or bss section instead of the normal data or bss section.
-This allows the data to be accessed using a single instruction.
-.Sp
-All modules should be compiled with the same \fB\-G\fR \fInum\fR
-value.
-.IP "\fB\-membedded\-data\fR" 4
-.IX Item "-membedded-data"
-.PD 0
-.IP "\fB\-mno\-embedded\-data\fR" 4
-.IX Item "-mno-embedded-data"
.PD
-Allocate variables to the read-only data section first if possible, then
-next in the small data section if possible, otherwise in data. This gives
-slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required
-when executing, and thus may be preferred for some embedded systems.
-.IP "\fB\-muninit\-const\-in\-rodata\fR" 4
-.IX Item "-muninit-const-in-rodata"
+Use (do not use) the hardware floating-point instructions and registers
+for floating-point operations. When \fB\-msoft\-float\fR is specified,
+functions in \fIlibgcc.a\fR will be used to perform floating-point
+operations. When \fB\-mhard\-float\fR is specified, the compiler
+generates \s-1IEEE\s0 floating-point instructions. This is the default.
+.IP "\fB\-mlong\-double\-64\fR" 4
+.IX Item "-mlong-double-64"
.PD 0
-.IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4
-.IX Item "-mno-uninit-const-in-rodata"
+.IP "\fB\-mlong\-double\-128\fR" 4
+.IX Item "-mlong-double-128"
.PD
-Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section.
-This option is only meaningful in conjunction with \fB\-membedded\-data\fR.
-.IP "\fB\-msplit\-addresses\fR" 4
-.IX Item "-msplit-addresses"
+These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size
+of 64bit makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR
+type. This is the default.
+.IP "\fB\-mbackchain\fR" 4
+.IX Item "-mbackchain"
.PD 0
-.IP "\fB\-mno\-split\-addresses\fR" 4
-.IX Item "-mno-split-addresses"
+.IP "\fB\-mno\-backchain\fR" 4
+.IX Item "-mno-backchain"
.PD
-Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler
-relocation operators. This option has been superceded by
-\&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility.
-.IP "\fB\-mexplicit\-relocs\fR" 4
-.IX Item "-mexplicit-relocs"
+Store (do not store) the address of the caller's frame as backchain pointer
+into the callee's stack frame.
+A backchain may be needed to allow debugging using tools that do not understand
+\&\s-1DWARF\-2\s0 call frame information.
+When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored
+at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect,
+the backchain is placed into the topmost word of the 96/160 byte register
+save area.
+.Sp
+In general, code compiled with \fB\-mbackchain\fR is call-compatible with
+code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain
+for debugging purposes usually requires that the whole binary is built with
+\&\fB\-mbackchain\fR. Note that the combination of \fB\-mbackchain\fR,
+\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order
+to build a linux kernel use \fB\-msoft\-float\fR.
+.Sp
+The default is to not maintain the backchain.
+.IP "\fB\-mpacked\-stack\fR" 4
+.IX Item "-mpacked-stack"
+.PD 0
+.IP "\fB\-mno\-packed\-stack\fR" 4
+.IX Item "-mno-packed-stack"
+.PD
+Use (do not use) the packed stack layout. When \fB\-mno\-packed\-stack\fR is
+specified, the compiler uses the all fields of the 96/160 byte register save
+area only for their default purpose; unused fields still take up stack space.
+When \fB\-mpacked\-stack\fR is specified, register save slots are densely
+packed at the top of the register save area; unused space is reused for other
+purposes, allowing for more efficient use of the available stack space.
+However, when \fB\-mbackchain\fR is also in effect, the topmost word of
+the save area is always used to store the backchain, and the return address
+register is always saved two words below the backchain.
+.Sp
+As long as the stack frame backchain is not used, code generated with
+\&\fB\-mpacked\-stack\fR is call-compatible with code generated with
+\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC\s0 2.95 for
+S/390 or zSeries generated code that uses the stack frame backchain at run
+time, not just for debugging purposes. Such code is not call-compatible
+with code compiled with \fB\-mpacked\-stack\fR. Also, note that the
+combination of \fB\-mbackchain\fR,
+\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order
+to build a linux kernel use \fB\-msoft\-float\fR.
+.Sp
+The default is to not use the packed stack layout.
+.IP "\fB\-msmall\-exec\fR" 4
+.IX Item "-msmall-exec"
.PD 0
-.IP "\fB\-mno\-explicit\-relocs\fR" 4
-.IX Item "-mno-explicit-relocs"
+.IP "\fB\-mno\-small\-exec\fR" 4
+.IX Item "-mno-small-exec"
.PD
-Use (do not use) assembler relocation operators when dealing with symbolic
-addresses. The alternative, selected by \fB\-mno\-explicit\-relocs\fR,
-is to use assembler macros instead.
-.Sp
-\&\fB\-mexplicit\-relocs\fR is usually the default if \s-1GCC\s0 was
-configured to use an assembler that supports relocation operators.
-However, there are two exceptions:
-.RS 4
-.IP "*" 4
-\&\s-1GCC\s0 is not yet able to generate explicit relocations for the combination
-of \fB\-mabi=64\fR and \fB\-mno\-abicalls\fR. This will be addressed
-in a future release.
-.IP "*" 4
-The combination of \fB\-mabicalls\fR and \fB\-fno\-unit\-at\-a\-time\fR
-implies \fB\-mno\-explicit\-relocs\fR unless explicitly overridden.
-This is because, when generating abicalls, the choice of relocation
-depends on whether a symbol is local or global. In some rare cases,
-\&\s-1GCC\s0 will not be able to decide this until the whole compilation unit
-has been read.
-.RE
-.RS 4
-.RE
-.IP "\fB\-mrnames\fR" 4
-.IX Item "-mrnames"
+Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction
+to do subroutine calls.
+This only works reliably if the total executable size does not
+exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead,
+which does not have this limitation.
+.IP "\fB\-m64\fR" 4
+.IX Item "-m64"
.PD 0
-.IP "\fB\-mno\-rnames\fR" 4
-.IX Item "-mno-rnames"
+.IP "\fB\-m31\fR" 4
+.IX Item "-m31"
.PD
-Generate (do not generate) code that refers to registers using their
-software names. The default is \fB\-mno\-rnames\fR, which tells \s-1GCC\s0
-to use hardware names like \fB$4\fR instead of software names like
-\&\fBa0\fR. The only assembler known to support \fB\-rnames\fR is
-the Algorithmics assembler.
-.IP "\fB\-mcheck\-zero\-division\fR" 4
-.IX Item "-mcheck-zero-division"
+When \fB\-m31\fR is specified, generate code compliant to the
+GNU/Linux for S/390 \s-1ABI\s0. When \fB\-m64\fR is specified, generate
+code compliant to the GNU/Linux for zSeries \s-1ABI\s0. This allows \s-1GCC\s0 in
+particular to generate 64\-bit instructions. For the \fBs390\fR
+targets, the default is \fB\-m31\fR, while the \fBs390x\fR
+targets default to \fB\-m64\fR.
+.IP "\fB\-mzarch\fR" 4
+.IX Item "-mzarch"
.PD 0
-.IP "\fB\-mno\-check\-zero\-division\fR" 4
-.IX Item "-mno-check-zero-division"
+.IP "\fB\-mesa\fR" 4
+.IX Item "-mesa"
.PD
-Trap (do not trap) on integer division by zero. The default is
-\&\fB\-mcheck\-zero\-division\fR.
-.IP "\fB\-mmemcpy\fR" 4
-.IX Item "-mmemcpy"
+When \fB\-mzarch\fR is specified, generate code using the
+instructions available on z/Architecture.
+When \fB\-mesa\fR is specified, generate code using the
+instructions available on \s-1ESA/390\s0. Note that \fB\-mesa\fR is
+not possible with \fB\-m64\fR.
+When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0,
+the default is \fB\-mesa\fR. When generating code compliant
+to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR.
+.IP "\fB\-mmvcle\fR" 4
+.IX Item "-mmvcle"
.PD 0
-.IP "\fB\-mno\-memcpy\fR" 4
-.IX Item "-mno-memcpy"
+.IP "\fB\-mno\-mvcle\fR" 4
+.IX Item "-mno-mvcle"
.PD
-Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block
-moves. The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline
-most constant-sized copies.
-.IP "\fB\-mlong\-calls\fR" 4
-.IX Item "-mlong-calls"
+Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction
+to perform block moves. When \fB\-mno\-mvcle\fR is specified,
+use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default unless optimizing for
+size.
+.IP "\fB\-mdebug\fR" 4
+.IX Item "-mdebug"
.PD 0
-.IP "\fB\-mno\-long\-calls\fR" 4
-.IX Item "-mno-long-calls"
+.IP "\fB\-mno\-debug\fR" 4
+.IX Item "-mno-debug"
.PD
-Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction. Calling
-functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller
-and callee to be in the same 256 megabyte segment.
-.Sp
-This option has no effect on abicalls code. The default is
-\&\fB\-mno\-long\-calls\fR.
-.IP "\fB\-mmad\fR" 4
-.IX Item "-mmad"
+Print (or do not print) additional debug information when compiling.
+The default is to not print debug information.
+.IP "\fB\-march=\fR\fIcpu-type\fR" 4
+.IX Item "-march=cpu-type"
+Generate code that will run on \fIcpu-type\fR, which is the name of a system
+representing a certain processor type. Possible values for
+\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, and \fBz990\fR.
+When generating code using the instructions available on z/Architecture,
+the default is \fB\-march=z900\fR. Otherwise, the default is
+\&\fB\-march=g5\fR.
+.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
+.IX Item "-mtune=cpu-type"
+Tune to \fIcpu-type\fR everything applicable about the generated code,
+except for the \s-1ABI\s0 and the set of available instructions.
+The list of \fIcpu-type\fR values is the same as for \fB\-march\fR.
+The default is the value used for \fB\-march\fR.
+.IP "\fB\-mtpf\-trace\fR" 4
+.IX Item "-mtpf-trace"
.PD 0
-.IP "\fB\-mno\-mad\fR" 4
-.IX Item "-mno-mad"
+.IP "\fB\-mno\-tpf\-trace\fR" 4
+.IX Item "-mno-tpf-trace"
.PD
-Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR
-instructions, as provided by the R4650 \s-1ISA\s0.
+Generate code that adds (does not add) in \s-1TPF\s0 \s-1OS\s0 specific branches to trace
+routines in the operating system. This option is off by default, even
+when compiling for the \s-1TPF\s0 \s-1OS\s0.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.IP "\fB\-mno\-fused\-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
-Enable (disable) use of the floating point multiply-accumulate
-instructions, when they are available. The default is
-\&\fB\-mfused\-madd\fR.
-.Sp
-When multiply-accumulate instructions are used, the intermediate
-product is calculated to infinite precision and is not subject to
-the \s-1FCSR\s0 Flush to Zero bit. This may be undesirable in some
-circumstances.
-.IP "\fB\-nocpp\fR" 4
-.IX Item "-nocpp"
-Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user
-assembler files (with a \fB.s\fR suffix) when assembling them.
-.IP "\fB\-mfix\-sb1\fR" 4
-.IX Item "-mfix-sb1"
-.PD 0
-.IP "\fB\-mno\-fix\-sb1\fR" 4
-.IX Item "-mno-fix-sb1"
-.PD
-Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata.
-(This flag currently works around the \s-1SB\-1\s0 revision 2
-``F1'' and ``F2'' floating point errata.)
-.IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4
-.IX Item "-mflush-func=func"
-.PD 0
-.IP "\fB\-mno\-flush\-func\fR" 4
-.IX Item "-mno-flush-func"
-.PD
-Specifies the function to call to flush the I and D caches, or to not
-call any such function. If called, the function must take the same
-arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the
-memory range for which the cache is being flushed, the size of the
-memory range, and the number 3 (to flush both caches). The default
-depends on the target \s-1GCC\s0 was configured for, but commonly is either
-\&\fB_flush_func\fR or \fB_\|_cpu_flush\fR.
-.IP "\fB\-mbranch\-likely\fR" 4
-.IX Item "-mbranch-likely"
-.PD 0
-.IP "\fB\-mno\-branch\-likely\fR" 4
-.IX Item "-mno-branch-likely"
-.PD
-Enable or disable use of Branch Likely instructions, regardless of the
-default for the selected architecture. By default, Branch Likely
-instructions may be generated if they are supported by the selected
-architecture. An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures
-and processors which implement those architectures; for those, Branch
-Likely instructions will not be generated by default because the \s-1MIPS32\s0
-and \s-1MIPS64\s0 architectures specifically deprecate their use.
-.PP
-\fIIntel 386 and \s-1AMD\s0 x86\-64 Options\fR
-.IX Subsection "Intel 386 and AMD x86-64 Options"
-.PP
-These \fB\-m\fR options are defined for the i386 and x86\-64 family of
-computers:
-.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
-.IX Item "-mtune=cpu-type"
-Tune to \fIcpu-type\fR everything applicable about the generated code, except
-for the \s-1ABI\s0 and the set of available instructions. The choices for
-\&\fIcpu-type\fR are:
-.RS 4
-.IP "\fIi386\fR" 4
-.IX Item "i386"
-Original Intel's i386 \s-1CPU\s0.
-.IP "\fIi486\fR" 4
-.IX Item "i486"
-Intel's i486 \s-1CPU\s0. (No scheduling is implemented for this chip.)
-.IP "\fIi586, pentium\fR" 4
-.IX Item "i586, pentium"
-Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support.
-.IP "\fIpentium-mmx\fR" 4
-.IX Item "pentium-mmx"
-Intel PentiumMMX \s-1CPU\s0 based on Pentium core with \s-1MMX\s0 instruction set support.
-.IP "\fIi686, pentiumpro\fR" 4
-.IX Item "i686, pentiumpro"
-Intel PentiumPro \s-1CPU\s0.
-.IP "\fIpentium2\fR" 4
-.IX Item "pentium2"
-Intel Pentium2 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 instruction set support.
-.IP "\fIpentium3, pentium3m\fR" 4
-.IX Item "pentium3, pentium3m"
-Intel Pentium3 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set
-support.
-.IP "\fIpentium-m\fR" 4
-.IX Item "pentium-m"
-Low power version of Intel Pentium3 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set
-support. Used by Centrino notebooks.
-.IP "\fIpentium4, pentium4m\fR" 4
-.IX Item "pentium4, pentium4m"
-Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support.
-.IP "\fIprescott\fR" 4
-.IX Item "prescott"
-Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction
-set support.
-.IP "\fInocona\fR" 4
-.IX Item "nocona"
-Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0,
-\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support.
-.IP "\fIk6\fR" 4
-.IX Item "k6"
-\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support.
-.IP "\fIk6\-2, k6\-3\fR" 4
-.IX Item "k6-2, k6-3"
-Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support.
-.IP "\fIathlon, athlon-tbird\fR" 4
-.IX Item "athlon, athlon-tbird"
-\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3dNOW! and \s-1SSE\s0 prefetch instructions
-support.
-.IP "\fIathlon\-4, athlon\-xp, athlon-mp\fR" 4
-.IX Item "athlon-4, athlon-xp, athlon-mp"
-Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3dNOW! and full \s-1SSE\s0
-instruction set support.
-.IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4
-.IX Item "k8, opteron, athlon64, athlon-fx"
-\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support. (This supersets
-\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
-.IP "\fIwinchip\-c6\fR" 4
-.IX Item "winchip-c6"
-\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
-set support.
-.IP "\fIwinchip2\fR" 4
-.IX Item "winchip2"
-\&\s-1IDT\s0 Winchip2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3dNOW!
-instruction set support.
-.IP "\fIc3\fR" 4
-.IX Item "c3"
-Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support. (No scheduling is
-implemented for this chip.)
-.IP "\fIc3\-2\fR" 4
-.IX Item "c3-2"
-Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is
-implemented for this chip.)
-.RE
-.RS 4
-.Sp
-While picking a specific \fIcpu-type\fR will schedule things appropriately
-for that particular chip, the compiler will not generate any code that
-does not run on the i386 without the \fB\-march=\fR\fIcpu-type\fR option
-being used.
-.RE
-.IP "\fB\-march=\fR\fIcpu-type\fR" 4
-.IX Item "-march=cpu-type"
-Generate instructions for the machine type \fIcpu-type\fR. The choices
-for \fIcpu-type\fR are the same as for \fB\-mtune\fR. Moreover,
-specifying \fB\-march=\fR\fIcpu-type\fR implies \fB\-mtune=\fR\fIcpu-type\fR.
-.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4
-.IX Item "-mcpu=cpu-type"
-A deprecated synonym for \fB\-mtune\fR.
-.IP "\fB\-m386\fR" 4
-.IX Item "-m386"
-.PD 0
-.IP "\fB\-m486\fR" 4
-.IX Item "-m486"
-.IP "\fB\-mpentium\fR" 4
-.IX Item "-mpentium"
-.IP "\fB\-mpentiumpro\fR" 4
-.IX Item "-mpentiumpro"
-.PD
-These options are synonyms for \fB\-mtune=i386\fR, \fB\-mtune=i486\fR,
-\&\fB\-mtune=pentium\fR, and \fB\-mtune=pentiumpro\fR respectively.
-These synonyms are deprecated.
-.IP "\fB\-mfpmath=\fR\fIunit\fR" 4
-.IX Item "-mfpmath=unit"
-Generate floating point arithmetics for selected unit \fIunit\fR. The choices
-for \fIunit\fR are:
-.RS 4
-.IP "\fB387\fR" 4
-.IX Item "387"
-Use the standard 387 floating point coprocessor present majority of chips and
-emulated otherwise. Code compiled with this option will run almost everywhere.
-The temporary results are computed in 80bit precision instead of precision
-specified by the type resulting in slightly different results compared to most
-of other chips. See \fB\-ffloat\-store\fR for more detailed description.
-.Sp
-This is the default choice for i386 compiler.
-.IP "\fBsse\fR" 4
-.IX Item "sse"
-Use scalar floating point instructions present in the \s-1SSE\s0 instruction set.
-This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line
-by Athlon\-4, Athlon-xp and Athlon-mp chips. The earlier version of \s-1SSE\s0
-instruction set supports only single precision arithmetics, thus the double and
-extended precision arithmetics is still done using 387. Later version, present
-only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips supports double precision
-arithmetics too.
-.Sp
-For i387 you need to use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR or
-\&\fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option
-effective. For x86\-64 compiler, these extensions are enabled by default.
-.Sp
-The resulting code should be considerably faster in the majority of cases and avoid
-the numerical instability problems of 387 code, but may break some existing
-code that expects temporaries to be 80bit.
-.Sp
-This is the default choice for the x86\-64 compiler.
-.IP "\fBsse,387\fR" 4
-.IX Item "sse,387"
-Attempt to utilize both instruction sets at once. This effectively double the
-amount of available registers and on chips with separate execution units for
-387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is
-still experimental, because the \s-1GCC\s0 register allocator does not model separate
-functional units well resulting in instable performance.
-.RE
-.RS 4
-.RE
-.IP "\fB\-masm=\fR\fIdialect\fR" 4
-.IX Item "-masm=dialect"
-Output asm instructions using selected \fIdialect\fR. Supported choices are
-\&\fBintel\fR or \fBatt\fR (the default one).
-.IP "\fB\-mieee\-fp\fR" 4
-.IX Item "-mieee-fp"
-.PD 0
-.IP "\fB\-mno\-ieee\-fp\fR" 4
-.IX Item "-mno-ieee-fp"
-.PD
-Control whether or not the compiler uses \s-1IEEE\s0 floating point
-comparisons. These handle correctly the case where the result of a
-comparison is unordered.
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-Generate output containing library calls for floating point.
-\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0.
-Normally the facilities of the machine's usual C compiler are used, but
-this can't be done directly in cross\-compilation. You must make your
-own arrangements to provide suitable library functions for
-cross\-compilation.
-.Sp
-On machines where a function returns floating point results in the 80387
-register stack, some floating point opcodes may be emitted even if
-\&\fB\-msoft\-float\fR is used.
-.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4
-.IX Item "-mno-fp-ret-in-387"
-Do not use the \s-1FPU\s0 registers for return values of functions.
-.Sp
-The usual calling convention has functions return values of types
-\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there
-is no \s-1FPU\s0. The idea is that the operating system should emulate
-an \s-1FPU\s0.
-.Sp
-The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned
-in ordinary \s-1CPU\s0 registers instead.
-.IP "\fB\-mno\-fancy\-math\-387\fR" 4
-.IX Item "-mno-fancy-math-387"
-Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and
-\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid
-generating those instructions. This option is the default on FreeBSD,
-OpenBSD and NetBSD. This option is overridden when \fB\-march\fR
-indicates that the target cpu will always have an \s-1FPU\s0 and so the
-instruction will not need emulation. As of revision 2.6.1, these
-instructions are not generated unless you also use the
-\&\fB\-funsafe\-math\-optimizations\fR switch.
-.IP "\fB\-malign\-double\fR" 4
-.IX Item "-malign-double"
-.PD 0
-.IP "\fB\-mno\-align\-double\fR" 4
-.IX Item "-mno-align-double"
-.PD
-Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and
-\&\f(CW\*(C`long long\*(C'\fR variables on a two word boundary or a one word
-boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two word boundary will
-produce code that runs somewhat faster on a \fBPentium\fR at the
-expense of more memory.
-.Sp
-\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch,
-structures containing the above types will be aligned differently than
-the published application binary interface specifications for the 386
-and will not be binary compatible with structures in code compiled
-without that switch.
-.IP "\fB\-m96bit\-long\-double\fR" 4
-.IX Item "-m96bit-long-double"
-.PD 0
-.IP "\fB\-m128bit\-long\-double\fR" 4
-.IX Item "-m128bit-long-double"
-.PD
-These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The i386
-application binary interface specifies the size to be 96 bits,
-so \fB\-m96bit\-long\-double\fR is the default in 32 bit mode.
-.Sp
-Modern architectures (Pentium and newer) would prefer \f(CW\*(C`long double\*(C'\fR
-to be aligned to an 8 or 16 byte boundary. In arrays or structures
-conforming to the \s-1ABI\s0, this would not be possible. So specifying a
-\&\fB\-m128bit\-long\-double\fR will align \f(CW\*(C`long double\*(C'\fR
-to a 16 byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional
-32 bit zero.
-.Sp
-In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as
-its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is to be aligned on 16 byte boundary.
-.Sp
-Notice that neither of these options enable any extra precision over the x87
-standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR.
-.Sp
-\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, the
-structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables will change
-their size as well as function calling convention for function taking
-\&\f(CW\*(C`long double\*(C'\fR will be modified. Hence they will not be binary
-compatible with arrays or structures in code compiled without that switch.
-.IP "\fB\-msvr3\-shlib\fR" 4
-.IX Item "-msvr3-shlib"
-.PD 0
-.IP "\fB\-mno\-svr3\-shlib\fR" 4
-.IX Item "-mno-svr3-shlib"
-.PD
-Control whether \s-1GCC\s0 places uninitialized local variables into the
-\&\f(CW\*(C`bss\*(C'\fR or \f(CW\*(C`data\*(C'\fR segments. \fB\-msvr3\-shlib\fR places them
-into \f(CW\*(C`bss\*(C'\fR. These options are meaningful only on System V Release 3.
-.IP "\fB\-mrtd\fR" 4
-.IX Item "-mrtd"
-Use a different function-calling convention, in which functions that
-take a fixed number of arguments return with the \f(CW\*(C`ret\*(C'\fR \fInum\fR
-instruction, which pops their arguments while returning. This saves one
-instruction in the caller since there is no need to pop the arguments
-there.
-.Sp
-You can specify that an individual function is called with this calling
-sequence with the function attribute \fBstdcall\fR. You can also
-override the \fB\-mrtd\fR option by using the function attribute
-\&\fBcdecl\fR.
-.Sp
-\&\fBWarning:\fR this calling convention is incompatible with the one
-normally used on Unix, so you cannot use it if you need to call
-libraries compiled with the Unix compiler.
-.Sp
-Also, you must provide function prototypes for all functions that
-take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
-otherwise incorrect code will be generated for calls to those
-functions.
-.Sp
-In addition, seriously incorrect code will result if you call a
-function with too many arguments. (Normally, extra arguments are
-harmlessly ignored.)
-.IP "\fB\-mregparm=\fR\fInum\fR" 4
-.IX Item "-mregparm=num"
-Control how many registers are used to pass integer arguments. By
-default, no registers are used to pass arguments, and at most 3
-registers can be used. You can control this behavior for a specific
-function by using the function attribute \fBregparm\fR.
-.Sp
-\&\fBWarning:\fR if you use this switch, and
-\&\fInum\fR is nonzero, then you must build all modules with the same
-value, including any libraries. This includes the system libraries and
-startup modules.
-.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4
-.IX Item "-mpreferred-stack-boundary=num"
-Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR
-byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified,
-the default is 4 (16 bytes or 128 bits), except when optimizing for code
-size (\fB\-Os\fR), in which case the default is the minimum correct
-alignment (4 bytes for x86, and 8 bytes for x86\-64).
-.Sp
-On Pentium and PentiumPro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values
-should be aligned to an 8 byte boundary (see \fB\-malign\-double\fR) or
-suffer significant run time performance penalties. On Pentium \s-1III\s0, the
-Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR suffers similar
-penalties if it is not 16 byte aligned.
-.Sp
-To ensure proper alignment of this values on the stack, the stack boundary
-must be as aligned as that required by any value stored on the stack.
-Further, every function must be generated such that it keeps the stack
-aligned. Thus calling a function compiled with a higher preferred
-stack boundary from a function compiled with a lower preferred stack
-boundary will most likely misalign the stack. It is recommended that
-libraries that use callbacks always use the default setting.
-.Sp
-This extra alignment does consume extra stack space, and generally
-increases code size. Code that is sensitive to stack space usage, such
-as embedded systems and operating system kernels, may want to reduce the
-preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR.
-.IP "\fB\-mmmx\fR" 4
-.IX Item "-mmmx"
-.PD 0
-.IP "\fB\-mno\-mmx\fR" 4
-.IX Item "-mno-mmx"
-.IP "\fB\-msse\fR" 4
-.IX Item "-msse"
-.IP "\fB\-mno\-sse\fR" 4
-.IX Item "-mno-sse"
-.IP "\fB\-msse2\fR" 4
-.IX Item "-msse2"
-.IP "\fB\-mno\-sse2\fR" 4
-.IX Item "-mno-sse2"
-.IP "\fB\-msse3\fR" 4
-.IX Item "-msse3"
-.IP "\fB\-mno\-sse3\fR" 4
-.IX Item "-mno-sse3"
-.IP "\fB\-m3dnow\fR" 4
-.IX Item "-m3dnow"
-.IP "\fB\-mno\-3dnow\fR" 4
-.IX Item "-mno-3dnow"
-.PD
-These switches enable or disable the use of built-in functions that allow
-direct access to the \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and 3Dnow extensions of the
-instruction set.
-.Sp
-To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point
-code, see \fB\-mfpmath=sse\fR.
-.IP "\fB\-mpush\-args\fR" 4
-.IX Item "-mpush-args"
-.PD 0
-.IP "\fB\-mno\-push\-args\fR" 4
-.IX Item "-mno-push-args"
-.PD
-Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter
-and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled
-by default. In some cases disabling it may improve performance because of
-improved scheduling and reduced dependencies.
-.IP "\fB\-maccumulate\-outgoing\-args\fR" 4
-.IX Item "-maccumulate-outgoing-args"
-If enabled, the maximum amount of space required for outgoing arguments will be
-computed in the function prologue. This is faster on most modern CPUs
-because of reduced dependencies, improved scheduling and reduced stack usage
-when preferred stack boundary is not equal to 2. The drawback is a notable
-increase in code size. This switch implies \fB\-mno\-push\-args\fR.
-.IP "\fB\-mthreads\fR" 4
-.IX Item "-mthreads"
-Support thread-safe exception handling on \fBMingw32\fR. Code that relies
-on thread-safe exception handling must compile and link all code with the
-\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines
-\&\fB\-D_MT\fR; when linking, it links in a special thread helper library
-\&\fB\-lmingwthrd\fR which cleans up per thread exception handling data.
-.IP "\fB\-mno\-align\-stringops\fR" 4
-.IX Item "-mno-align-stringops"
-Do not align destination of inlined string operations. This switch reduces
-code size and improves performance in case the destination is already aligned,
-but \s-1GCC\s0 doesn't know about it.
-.IP "\fB\-minline\-all\-stringops\fR" 4
-.IX Item "-minline-all-stringops"
-By default \s-1GCC\s0 inlines string operations only when destination is known to be
-aligned at least to 4 byte boundary. This enables more inlining, increase code
-size, but may improve performance of code that depends on fast memcpy, strlen
-and memset for short lengths.
-.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4
-.IX Item "-momit-leaf-frame-pointer"
-Don't keep the frame pointer in a register for leaf functions. This
-avoids the instructions to save, set up and restore frame pointers and
-makes an extra register available in leaf functions. The option
-\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions
-which might make debugging harder.
-.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4
-.IX Item "-mtls-direct-seg-refs"
-.PD 0
-.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4
-.IX Item "-mno-tls-direct-seg-refs"
-.PD
-Controls whether \s-1TLS\s0 variables may be accessed with offsets from the
-\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit),
-or whether the thread base pointer must be added. Whether or not this
-is legal depends on the operating system, and whether it maps the
-segment to cover the entire \s-1TLS\s0 area.
-.Sp
-For systems that use \s-1GNU\s0 libc, the default is on.
-.PP
-These \fB\-m\fR switches are supported in addition to the above
-on \s-1AMD\s0 x86\-64 processors in 64\-bit environments.
-.IP "\fB\-m32\fR" 4
-.IX Item "-m32"
-.PD 0
-.IP "\fB\-m64\fR" 4
-.IX Item "-m64"
-.PD
-Generate code for a 32\-bit or 64\-bit environment.
-The 32\-bit environment sets int, long and pointer to 32 bits and
-generates code that runs on any i386 system.
-The 64\-bit environment sets int to 32 bits and long and pointer
-to 64 bits and generates code for \s-1AMD\s0's x86\-64 architecture.
-.IP "\fB\-mno\-red\-zone\fR" 4
-.IX Item "-mno-red-zone"
-Do not use a so called red zone for x86\-64 code. The red zone is mandated
-by the x86\-64 \s-1ABI\s0, it is a 128\-byte area beyond the location of the
-stack pointer that will not be modified by signal or interrupt handlers
-and therefore can be used for temporary data without adjusting the stack
-pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone.
-.IP "\fB\-mcmodel=small\fR" 4
-.IX Item "-mcmodel=small"
-Generate code for the small code model: the program and its symbols must
-be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits.
-Programs can be statically or dynamically linked. This is the default
-code model.
-.IP "\fB\-mcmodel=kernel\fR" 4
-.IX Item "-mcmodel=kernel"
-Generate code for the kernel code model. The kernel runs in the
-negative 2 \s-1GB\s0 of the address space.
-This model has to be used for Linux kernel code.
-.IP "\fB\-mcmodel=medium\fR" 4
-.IX Item "-mcmodel=medium"
-Generate code for the medium model: The program is linked in the lower 2
-\&\s-1GB\s0 of the address space but symbols can be located anywhere in the
-address space. Programs can be statically or dynamically linked, but
-building of shared libraries are not supported with the medium model.
-.IP "\fB\-mcmodel=large\fR" 4
-.IX Item "-mcmodel=large"
-Generate code for the large model: This model makes no assumptions
-about addresses and sizes of sections. Currently \s-1GCC\s0 does not implement
-this model.
-.PP
-\fI\s-1HPPA\s0 Options\fR
-.IX Subsection "HPPA Options"
-.PP
-These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers:
-.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4
-.IX Item "-march=architecture-type"
-Generate code for the specified architecture. The choices for
-\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0
-1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors. Refer to
-\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper
-architecture option for your machine. Code compiled for lower numbered
-architectures will run on higher numbered architectures, but not the
-other way around.
-.Sp
-\&\s-1PA\s0 2.0 support currently requires gas snapshot 19990413 or later. The
-next release of binutils (current is 2.9.1) will probably contain \s-1PA\s0 2.0
-support.
-.IP "\fB\-mpa\-risc\-1\-0\fR" 4
-.IX Item "-mpa-risc-1-0"
-.PD 0
-.IP "\fB\-mpa\-risc\-1\-1\fR" 4
-.IX Item "-mpa-risc-1-1"
-.IP "\fB\-mpa\-risc\-2\-0\fR" 4
-.IX Item "-mpa-risc-2-0"
-.PD
-Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively.
-.IP "\fB\-mbig\-switch\fR" 4
-.IX Item "-mbig-switch"
-Generate code suitable for big switch tables. Use this option only if
-the assembler/linker complain about out of range branches within a switch
-table.
-.IP "\fB\-mjump\-in\-delay\fR" 4
-.IX Item "-mjump-in-delay"
-Fill delay slots of function calls with unconditional jump instructions
-by modifying the return pointer for the function call to be the target
-of the conditional jump.
-.IP "\fB\-mdisable\-fpregs\fR" 4
-.IX Item "-mdisable-fpregs"
-Prevent floating point registers from being used in any manner. This is
-necessary for compiling kernels which perform lazy context switching of
-floating point registers. If you use this option and attempt to perform
-floating point operations, the compiler will abort.
-.IP "\fB\-mdisable\-indexing\fR" 4
-.IX Item "-mdisable-indexing"
-Prevent the compiler from using indexing address modes. This avoids some
-rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0.
-.IP "\fB\-mno\-space\-regs\fR" 4
-.IX Item "-mno-space-regs"
-Generate code that assumes the target has no space registers. This allows
-\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes.
-.Sp
-Such code is suitable for level 0 \s-1PA\s0 systems and kernels.
-.IP "\fB\-mfast\-indirect\-calls\fR" 4
-.IX Item "-mfast-indirect-calls"
-Generate code that assumes calls never cross space boundaries. This
-allows \s-1GCC\s0 to emit code which performs faster indirect calls.
-.Sp
-This option will not work in the presence of shared libraries or nested
-functions.
-.IP "\fB\-mlong\-load\-store\fR" 4
-.IX Item "-mlong-load-store"
-Generate 3\-instruction load and store sequences as sometimes required by
-the HP-UX 10 linker. This is equivalent to the \fB+k\fR option to
-the \s-1HP\s0 compilers.
-.IP "\fB\-mportable\-runtime\fR" 4
-.IX Item "-mportable-runtime"
-Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems.
-.IP "\fB\-mgas\fR" 4
-.IX Item "-mgas"
-Enable the use of assembler directives only \s-1GAS\s0 understands.
-.IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4
-.IX Item "-mschedule=cpu-type"
-Schedule code according to the constraints for the machine type
-\&\fIcpu-type\fR. The choices for \fIcpu-type\fR are \fB700\fR
-\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR. Refer
-to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the
-proper scheduling option for your machine. The default scheduling is
-\&\fB8000\fR.
-.IP "\fB\-mlinker\-opt\fR" 4
-.IX Item "-mlinker-opt"
-Enable the optimization pass in the HP-UX linker. Note this makes symbolic
-debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
-linkers in which they give bogus error messages when linking some programs.
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-Generate output containing library calls for floating point.
-\&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross\-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross\-compilation. The embedded target \fBhppa1.1\-*\-pro\fR
-does provide software floating point support.
-.Sp
-\&\fB\-msoft\-float\fR changes the calling convention in the output file;
-therefore, it is only useful if you compile \fIall\fR of a program with
-this option. In particular, you need to compile \fIlibgcc.a\fR, the
-library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for
-this to work.
-.IP "\fB\-msio\fR" 4
-.IX Item "-msio"
-Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0. The default is
-\&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR,
-\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0. These
-options are available under HP-UX and \s-1HI\-UX\s0.
-.IP "\fB\-mgnu\-ld\fR" 4
-.IX Item "-mgnu-ld"
-Use \s-1GNU\s0 ld specific options. This passes \fB\-shared\fR to ld when
-building a shared library. It is the default when \s-1GCC\s0 is configured,
-explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not
-have any affect on which ld is called, it only changes what parameters
-are passed to that ld. The ld that is called is determined by the
-\&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and
-finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed
-using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available
-on the 64 bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR.
-.IP "\fB\-mhp\-ld\fR" 4
-.IX Item "-mhp-ld"
-Use \s-1HP\s0 ld specific options. This passes \fB\-b\fR to ld when building
-a shared library and passes \fB+Accept TypeMismatch\fR to ld on all
-links. It is the default when \s-1GCC\s0 is configured, explicitly or
-implicitly, with the \s-1HP\s0 linker. This option does not have any affect on
-which ld is called, it only changes what parameters are passed to that
-ld. The ld that is called is determined by the \fB\-\-with\-ld\fR
-configure option, \s-1GCC\s0's program search path, and finally by the user's
-\&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich
-`gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64 bit
-HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR.
-.IP "\fB\-mlong\-calls\fR" 4
-.IX Item "-mlong-calls"
-Generate code that uses long call sequences. This ensures that a call
-is always able to reach linker generated stubs. The default is to generate
-long calls only when the distance from the call site to the beginning
-of the function or translation unit, as the case may be, exceeds a
-predefined limit set by the branch type being used. The limits for
-normal calls are 7,600,000 and 240,000 bytes, respectively for the
-\&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures. Sibcalls are always limited at
-240,000 bytes.
-.Sp
-Distances are measured from the beginning of functions when using the
-\&\fB\-ffunction\-sections\fR option, or when using the \fB\-mgas\fR
-and \fB\-mno\-portable\-runtime\fR options together under HP-UX with
-the \s-1SOM\s0 linker.
-.Sp
-It is normally not desirable to use this option as it will degrade
-performance. However, it may be useful in large applications,
-particularly when partial linking is used to build the application.
-.Sp
-The types of long calls used depends on the capabilities of the
-assembler and linker, and the type of code being generated. The
-impact on systems that support long absolute calls, and long pic
-symbol-difference or pc-relative calls should be relatively small.
-However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code
-and it is quite long.
-.IP "\fB\-nolibdld\fR" 4
-.IX Item "-nolibdld"
-Suppress the generation of link options to search libdld.sl when the
-\&\fB\-static\fR option is specified on HP-UX 10 and later.
-.IP "\fB\-static\fR" 4
-.IX Item "-static"
-The HP-UX implementation of setlocale in libc has a dependency on
-libdld.sl. There isn't an archive version of libdld.sl. Thus,
-when the \fB\-static\fR option is specified, special link options
-are needed to resolve this dependency.
-.Sp
-On HP-UX 10 and later, the \s-1GCC\s0 driver adds the necessary options to
-link with libdld.sl when the \fB\-static\fR option is specified.
-This causes the resulting binary to be dynamic. On the 64\-bit port,
-the linkers generate dynamic binaries by default in any case. The
-\&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from
-adding these link options.
-.IP "\fB\-threads\fR" 4
-.IX Item "-threads"
-Add support for multithreading with the \fIdce thread\fR library
-under \s-1HP\-UX\s0. This option sets flags for both the preprocessor and
-linker.
-.PP
-\fIIntel 960 Options\fR
-.IX Subsection "Intel 960 Options"
-.PP
-These \fB\-m\fR options are defined for the Intel 960 implementations:
-.IP "\fB\-m\fR\fIcpu-type\fR" 4
-.IX Item "-mcpu-type"
-Assume the defaults for the machine type \fIcpu-type\fR for some of
-the other options, including instruction scheduling, floating point
-support, and addressing modes. The choices for \fIcpu-type\fR are
-\&\fBka\fR, \fBkb\fR, \fBmc\fR, \fBca\fR, \fBcf\fR,
-\&\fBsa\fR, and \fBsb\fR.
-The default is
-\&\fBkb\fR.
-.IP "\fB\-mnumerics\fR" 4
-.IX Item "-mnumerics"
-.PD 0
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-.PD
-The \fB\-mnumerics\fR option indicates that the processor does support
-floating-point instructions. The \fB\-msoft\-float\fR option indicates
-that floating-point support should not be assumed.
-.IP "\fB\-mleaf\-procedures\fR" 4
-.IX Item "-mleaf-procedures"
-.PD 0
-.IP "\fB\-mno\-leaf\-procedures\fR" 4
-.IX Item "-mno-leaf-procedures"
-.PD
-Do (or do not) attempt to alter leaf procedures to be callable with the
-\&\f(CW\*(C`bal\*(C'\fR instruction as well as \f(CW\*(C`call\*(C'\fR. This will result in more
-efficient code for explicit calls when the \f(CW\*(C`bal\*(C'\fR instruction can be
-substituted by the assembler or linker, but less efficient code in other
-cases, such as calls via function pointers, or using a linker that doesn't
-support this optimization.
-.IP "\fB\-mtail\-call\fR" 4
-.IX Item "-mtail-call"
-.PD 0
-.IP "\fB\-mno\-tail\-call\fR" 4
-.IX Item "-mno-tail-call"
-.PD
-Do (or do not) make additional attempts (beyond those of the
-machine-independent portions of the compiler) to optimize tail-recursive
-calls into branches. You may not want to do this because the detection of
-cases where this is not valid is not totally complete. The default is
-\&\fB\-mno\-tail\-call\fR.
-.IP "\fB\-mcomplex\-addr\fR" 4
-.IX Item "-mcomplex-addr"
-.PD 0
-.IP "\fB\-mno\-complex\-addr\fR" 4
-.IX Item "-mno-complex-addr"
-.PD
-Assume (or do not assume) that the use of a complex addressing mode is a
-win on this implementation of the i960. Complex addressing modes may not
-be worthwhile on the K\-series, but they definitely are on the C\-series.
-The default is currently \fB\-mcomplex\-addr\fR for all processors except
-the \s-1CB\s0 and \s-1CC\s0.
-.IP "\fB\-mcode\-align\fR" 4
-.IX Item "-mcode-align"
-.PD 0
-.IP "\fB\-mno\-code\-align\fR" 4
-.IX Item "-mno-code-align"
-.PD
-Align code to 8\-byte boundaries for faster fetching (or don't bother).
-Currently turned on by default for C\-series implementations only.
-.IP "\fB\-mic\-compat\fR" 4
-.IX Item "-mic-compat"
-.PD 0
-.IP "\fB\-mic2.0\-compat\fR" 4
-.IX Item "-mic2.0-compat"
-.IP "\fB\-mic3.0\-compat\fR" 4
-.IX Item "-mic3.0-compat"
-.PD
-Enable compatibility with iC960 v2.0 or v3.0.
-.IP "\fB\-masm\-compat\fR" 4
-.IX Item "-masm-compat"
-.PD 0
-.IP "\fB\-mintel\-asm\fR" 4
-.IX Item "-mintel-asm"
-.PD
-Enable compatibility with the iC960 assembler.
-.IP "\fB\-mstrict\-align\fR" 4
-.IX Item "-mstrict-align"
-.PD 0
-.IP "\fB\-mno\-strict\-align\fR" 4
-.IX Item "-mno-strict-align"
-.PD
-Do not permit (do permit) unaligned accesses.
-.IP "\fB\-mold\-align\fR" 4
-.IX Item "-mold-align"
-Enable structure-alignment compatibility with Intel's gcc release version
-1.3 (based on gcc 1.37). This option implies \fB\-mstrict\-align\fR.
-.IP "\fB\-mlong\-double\-64\fR" 4
-.IX Item "-mlong-double-64"
-Implement type \fBlong double\fR as 64\-bit floating point numbers.
-Without the option \fBlong double\fR is implemented by 80\-bit
-floating point numbers. The only reason we have it because there is
-no 128\-bit \fBlong double\fR support in \fBfp\-bit.c\fR yet. So it
-is only useful for people using soft-float targets. Otherwise, we
-should recommend against use of it.
-.PP
-\fI\s-1DEC\s0 Alpha Options\fR
-.IX Subsection "DEC Alpha Options"
-.PP
-These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations:
-.IP "\fB\-mno\-soft\-float\fR" 4
-.IX Item "-mno-soft-float"
-.PD 0
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-.PD
-Use (do not use) the hardware floating-point instructions for
-floating-point operations. When \fB\-msoft\-float\fR is specified,
-functions in \fIlibgcc.a\fR will be used to perform floating-point
-operations. Unless they are replaced by routines that emulate the
-floating-point operations, or compiled in such a way as to call such
-emulations routines, these routines will issue floating-point
-operations. If you are compiling for an Alpha without floating-point
-operations, you must ensure that the library is built so as not to call
-them.
-.Sp
-Note that Alpha implementations without floating-point operations are
-required to have floating-point registers.
-.IP "\fB\-mfp\-reg\fR" 4
-.IX Item "-mfp-reg"
-.PD 0
-.IP "\fB\-mno\-fp\-regs\fR" 4
-.IX Item "-mno-fp-regs"
-.PD
-Generate code that uses (does not use) the floating-point register set.
-\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR. If the floating-point
-register set is not used, floating point operands are passed in integer
-registers as if they were integers and floating-point results are passed
-in \f(CW$0\fR instead of \f(CW$f0\fR. This is a non-standard calling sequence,
-so any function with a floating-point argument or return value called by code
-compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that
-option.
-.Sp
-A typical use of this option is building a kernel that does not use,
-and hence need not save and restore, any floating-point registers.
-.IP "\fB\-mieee\fR" 4
-.IX Item "-mieee"
-The Alpha architecture implements floating-point hardware optimized for
-maximum performance. It is mostly compliant with the \s-1IEEE\s0 floating
-point standard. However, for full compliance, software assistance is
-required. This option generates code fully \s-1IEEE\s0 compliant code
-\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below).
-If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is
-defined during compilation. The resulting code is less efficient but is
-able to correctly support denormalized numbers and exceptional \s-1IEEE\s0
-values such as not-a-number and plus/minus infinity. Other Alpha
-compilers call this option \fB\-ieee_with_no_inexact\fR.
-.IP "\fB\-mieee\-with\-inexact\fR" 4
-.IX Item "-mieee-with-inexact"
-This is like \fB\-mieee\fR except the generated code also maintains
-the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the
-generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to
-\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor
-macro. On some Alpha implementations the resulting code may execute
-significantly slower than the code generated by default. Since there is
-very little code that depends on the \fIinexact-flag\fR, you should
-normally not specify this option. Other Alpha compilers call this
-option \fB\-ieee_with_inexact\fR.
-.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4
-.IX Item "-mfp-trap-mode=trap-mode"
-This option controls what floating-point related traps are enabled.
-Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR.
-The trap mode can be set to one of four values:
-.RS 4
-.IP "\fBn\fR" 4
-.IX Item "n"
-This is the default (normal) setting. The only traps that are enabled
-are the ones that cannot be disabled in software (e.g., division by zero
-trap).
-.IP "\fBu\fR" 4
-.IX Item "u"
-In addition to the traps enabled by \fBn\fR, underflow traps are enabled
-as well.
-.IP "\fBsu\fR" 4
-.IX Item "su"
-Like \fBsu\fR, but the instructions are marked to be safe for software
-completion (see Alpha architecture manual for details).
-.IP "\fBsui\fR" 4
-.IX Item "sui"
-Like \fBsu\fR, but inexact traps are enabled as well.
-.RE
-.RS 4
-.RE
-.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4
-.IX Item "-mfp-rounding-mode=rounding-mode"
-Selects the \s-1IEEE\s0 rounding mode. Other Alpha compilers call this option
-\&\fB\-fprm\fR \fIrounding-mode\fR. The \fIrounding-mode\fR can be one
-of:
-.RS 4
-.IP "\fBn\fR" 4
-.IX Item "n"
-Normal \s-1IEEE\s0 rounding mode. Floating point numbers are rounded towards
-the nearest machine number or towards the even machine number in case
-of a tie.
-.IP "\fBm\fR" 4
-.IX Item "m"
-Round towards minus infinity.
-.IP "\fBc\fR" 4
-.IX Item "c"
-Chopped rounding mode. Floating point numbers are rounded towards zero.
-.IP "\fBd\fR" 4
-.IX Item "d"
-Dynamic rounding mode. A field in the floating point control register
-(\fIfpcr\fR, see Alpha architecture reference manual) controls the
-rounding mode in effect. The C library initializes this register for
-rounding towards plus infinity. Thus, unless your program modifies the
-\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity.
-.RE
-.RS 4
-.RE
-.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4
-.IX Item "-mtrap-precision=trap-precision"
-In the Alpha architecture, floating point traps are imprecise. This
-means without software assistance it is impossible to recover from a
-floating trap and program execution normally needs to be terminated.
-\&\s-1GCC\s0 can generate code that can assist operating system trap handlers
-in determining the exact location that caused a floating point trap.
-Depending on the requirements of an application, different levels of
-precisions can be selected:
-.RS 4
-.IP "\fBp\fR" 4
-.IX Item "p"
-Program precision. This option is the default and means a trap handler
-can only identify which program caused a floating point exception.
-.IP "\fBf\fR" 4
-.IX Item "f"
-Function precision. The trap handler can determine the function that
-caused a floating point exception.
-.IP "\fBi\fR" 4
-.IX Item "i"
-Instruction precision. The trap handler can determine the exact
-instruction that caused a floating point exception.
-.RE
-.RS 4
-.Sp
-Other Alpha compilers provide the equivalent options called
-\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR.
-.RE
-.IP "\fB\-mieee\-conformant\fR" 4
-.IX Item "-mieee-conformant"
-This option marks the generated code as \s-1IEEE\s0 conformant. You must not
-use this option unless you also specify \fB\-mtrap\-precision=i\fR and either
-\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR. Its only effect
-is to emit the line \fB.eflag 48\fR in the function prologue of the
-generated assembly file. Under \s-1DEC\s0 Unix, this has the effect that
-IEEE-conformant math library routines will be linked in.
-.IP "\fB\-mbuild\-constants\fR" 4
-.IX Item "-mbuild-constants"
-Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to
-see if it can construct it from smaller constants in two or three
-instructions. If it cannot, it will output the constant as a literal and
-generate code to load it from the data segment at runtime.
-.Sp
-Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants
-using code, even if it takes more instructions (the maximum is six).
-.Sp
-You would typically use this option to build a shared library dynamic
-loader. Itself a shared library, it must relocate itself in memory
-before it can find the variables and constants in its own data segment.
-.IP "\fB\-malpha\-as\fR" 4
-.IX Item "-malpha-as"
-.PD 0
-.IP "\fB\-mgas\fR" 4
-.IX Item "-mgas"
-.PD
-Select whether to generate code to be assembled by the vendor-supplied
-assembler (\fB\-malpha\-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR.
-.IP "\fB\-mbwx\fR" 4
-.IX Item "-mbwx"
-.PD 0
-.IP "\fB\-mno\-bwx\fR" 4
-.IX Item "-mno-bwx"
-.IP "\fB\-mcix\fR" 4
-.IX Item "-mcix"
-.IP "\fB\-mno\-cix\fR" 4
-.IX Item "-mno-cix"
-.IP "\fB\-mfix\fR" 4
-.IX Item "-mfix"
-.IP "\fB\-mno\-fix\fR" 4
-.IX Item "-mno-fix"
-.IP "\fB\-mmax\fR" 4
-.IX Item "-mmax"
-.IP "\fB\-mno\-max\fR" 4
-.IX Item "-mno-max"
-.PD
-Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0,
-\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction
-sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that
-of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified.
-.IP "\fB\-mfloat\-vax\fR" 4
-.IX Item "-mfloat-vax"
-.PD 0
-.IP "\fB\-mfloat\-ieee\fR" 4
-.IX Item "-mfloat-ieee"
-.PD
-Generate code that uses (does not use) \s-1VAX\s0 F and G floating point
-arithmetic instead of \s-1IEEE\s0 single and double precision.
-.IP "\fB\-mexplicit\-relocs\fR" 4
-.IX Item "-mexplicit-relocs"
-.PD 0
-.IP "\fB\-mno\-explicit\-relocs\fR" 4
-.IX Item "-mno-explicit-relocs"
-.PD
-Older Alpha assemblers provided no way to generate symbol relocations
-except via assembler macros. Use of these macros does not allow
-optimal instruction scheduling. \s-1GNU\s0 binutils as of version 2.12
-supports a new syntax that allows the compiler to explicitly mark
-which relocations should apply to which instructions. This option
-is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of
-the assembler when it is built and sets the default accordingly.
-.IP "\fB\-msmall\-data\fR" 4
-.IX Item "-msmall-data"
-.PD 0
-.IP "\fB\-mlarge\-data\fR" 4
-.IX Item "-mlarge-data"
-.PD
-When \fB\-mexplicit\-relocs\fR is in effect, static data is
-accessed via \fIgp-relative\fR relocations. When \fB\-msmall\-data\fR
-is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR
-(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via
-16\-bit relocations off of the \f(CW$gp\fR register. This limits the
-size of the small data area to 64KB, but allows the variables to be
-directly accessed via a single instruction.
-.Sp
-The default is \fB\-mlarge\-data\fR. With this option the data area
-is limited to just below 2GB. Programs that require more than 2GB of
-data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the
-heap instead of in the program's data segment.
-.Sp
-When generating code for shared libraries, \fB\-fpic\fR implies
-\&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR.
-.IP "\fB\-msmall\-text\fR" 4
-.IX Item "-msmall-text"
-.PD 0
-.IP "\fB\-mlarge\-text\fR" 4
-.IX Item "-mlarge-text"
-.PD
-When \fB\-msmall\-text\fR is used, the compiler assumes that the
-code of the entire program (or shared library) fits in 4MB, and is
-thus reachable with a branch instruction. When \fB\-msmall\-data\fR
-is used, the compiler can assume that all local symbols share the
-same \f(CW$gp\fR value, and thus reduce the number of instructions
-required for a function call from 4 to 1.
-.Sp
-The default is \fB\-mlarge\-text\fR.
-.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
-.IX Item "-mcpu=cpu_type"
-Set the instruction set and instruction scheduling parameters for
-machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR
-style name or the corresponding chip number. \s-1GCC\s0 supports scheduling
-parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will
-choose the default values for the instruction set from the processor
-you specify. If you do not specify a processor type, \s-1GCC\s0 will default
-to the processor on which the compiler was built.
-.Sp
-Supported values for \fIcpu_type\fR are
-.RS 4
-.IP "\fBev4\fR" 4
-.IX Item "ev4"
-.PD 0
-.IP "\fBev45\fR" 4
-.IX Item "ev45"
-.IP "\fB21064\fR" 4
-.IX Item "21064"
-.PD
-Schedules as an \s-1EV4\s0 and has no instruction set extensions.
-.IP "\fBev5\fR" 4
-.IX Item "ev5"
-.PD 0
-.IP "\fB21164\fR" 4
-.IX Item "21164"
-.PD
-Schedules as an \s-1EV5\s0 and has no instruction set extensions.
-.IP "\fBev56\fR" 4
-.IX Item "ev56"
-.PD 0
-.IP "\fB21164a\fR" 4
-.IX Item "21164a"
-.PD
-Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension.
-.IP "\fBpca56\fR" 4
-.IX Item "pca56"
-.PD 0
-.IP "\fB21164pc\fR" 4
-.IX Item "21164pc"
-.IP "\fB21164PC\fR" 4
-.IX Item "21164PC"
-.PD
-Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions.
-.IP "\fBev6\fR" 4
-.IX Item "ev6"
-.PD 0
-.IP "\fB21264\fR" 4
-.IX Item "21264"
-.PD
-Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
-.IP "\fBev67\fR" 4
-.IX Item "ev67"
-.PD 0
-.IP "\fB21264a\fR" 4
-.IX Item "21264a"
-.PD
-Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
-.RE
-.RS 4
-.RE
-.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
-.IX Item "-mtune=cpu_type"
-Set only the instruction scheduling parameters for machine type
-\&\fIcpu_type\fR. The instruction set is not changed.
-.IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4
-.IX Item "-mmemory-latency=time"
-Sets the latency the scheduler should assume for typical memory
-references as seen by the application. This number is highly
-dependent on the memory access patterns used by the application
-and the size of the external cache on the machine.
-.Sp
-Valid options for \fItime\fR are
-.RS 4
-.IP "\fInumber\fR" 4
-.IX Item "number"
-A decimal number representing clock cycles.
-.IP "\fBL1\fR" 4
-.IX Item "L1"
-.PD 0
-.IP "\fBL2\fR" 4
-.IX Item "L2"
-.IP "\fBL3\fR" 4
-.IX Item "L3"
-.IP "\fBmain\fR" 4
-.IX Item "main"
-.PD
-The compiler contains estimates of the number of clock cycles for
-``typical'' \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches
-(also called Dcache, Scache, and Bcache), as well as to main memory.
-Note that L3 is only valid for \s-1EV5\s0.
-.RE
-.RS 4
-.RE
+Generate code that uses (does not use) the floating point multiply and
+accumulate instructions. These instructions are generated by default if
+hardware floating point is used.
+.IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4
+.IX Item "-mwarn-framesize=framesize"
+Emit a warning if the current function exceeds the given frame size. Because
+this is a compile time check it doesn't need to be a real problem when the program
+runs. It is intended to identify functions which most probably cause
+a stack overflow. It is useful to be used in an environment with limited stack
+size e.g. the linux kernel.
+.IP "\fB\-mwarn\-dynamicstack\fR" 4
+.IX Item "-mwarn-dynamicstack"
+Emit a warning if the function calls alloca or uses dynamically
+sized arrays. This is generally a bad idea with a limited stack size.
+.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4
+.IX Item "-mstack-guard=stack-guard"
+.PD 0
+.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4
+.IX Item "-mstack-size=stack-size"
+.PD
+These arguments always have to be used in conjunction. If they are present the s390
+back end emits additional instructions in the function prologue which trigger a trap
+if the stack size is \fIstack-guard\fR bytes above the \fIstack-size\fR
+(remember that the stack on s390 grows downward). These options are intended to
+be used to help debugging stack overflow problems. The additionally emitted code
+causes only little overhead and hence can also be used in production like systems
+without greater performance degradation. The given values have to be exact
+powers of 2 and \fIstack-size\fR has to be greater than \fIstack-guard\fR without
+exceeding 64k.
+In order to be efficient the extra code makes the assumption that the stack starts
+at an address aligned to the value given by \fIstack-size\fR.
.PP
-\fI\s-1DEC\s0 Alpha/VMS Options\fR
-.IX Subsection "DEC Alpha/VMS Options"
+\fIScore Options\fR
+.IX Subsection "Score Options"
.PP
-These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations:
-.IP "\fB\-mvms\-return\-codes\fR" 4
-.IX Item "-mvms-return-codes"
-Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0
-style condition (e.g. error) codes.
-.PP
-\fIH8/300 Options\fR
-.IX Subsection "H8/300 Options"
-.PP
-These \fB\-m\fR options are defined for the H8/300 implementations:
-.IP "\fB\-mrelax\fR" 4
-.IX Item "-mrelax"
-Shorten some address references at link time, when possible; uses the
-linker option \fB\-relax\fR.
-.IP "\fB\-mh\fR" 4
-.IX Item "-mh"
-Generate code for the H8/300H.
-.IP "\fB\-ms\fR" 4
-.IX Item "-ms"
-Generate code for the H8S.
-.IP "\fB\-mn\fR" 4
-.IX Item "-mn"
-Generate code for the H8S and H8/300H in the normal mode. This switch
-must be used either with \-mh or \-ms.
-.IP "\fB\-ms2600\fR" 4
-.IX Item "-ms2600"
-Generate code for the H8S/2600. This switch must be used with \fB\-ms\fR.
-.IP "\fB\-mint32\fR" 4
-.IX Item "-mint32"
-Make \f(CW\*(C`int\*(C'\fR data 32 bits by default.
-.IP "\fB\-malign\-300\fR" 4
-.IX Item "-malign-300"
-On the H8/300H and H8S, use the same alignment rules as for the H8/300.
-The default for the H8/300H and H8S is to align longs and floats on 4
-byte boundaries.
-\&\fB\-malign\-300\fR causes them to be aligned on 2 byte boundaries.
-This option has no effect on the H8/300.
+These options are defined for Score implementations:
+.IP "\fB\-meb\fR" 4
+.IX Item "-meb"
+Compile code for big endian mode. This is the default.
+.IP "\fB\-mel\fR" 4
+.IX Item "-mel"
+Compile code for little endian mode.
+.IP "\fB\-mnhwloop\fR" 4
+.IX Item "-mnhwloop"
+Disable generate bcnz instruction.
+.IP "\fB\-muls\fR" 4
+.IX Item "-muls"
+Enable generate unaligned load and store instruction.
+.IP "\fB\-mmac\fR" 4
+.IX Item "-mmac"
+Enable the use of multiply-accumulate instructions. Disabled by default.
+.IP "\fB\-mscore5\fR" 4
+.IX Item "-mscore5"
+Specify the \s-1SCORE5\s0 as the target architecture.
+.IP "\fB\-mscore5u\fR" 4
+.IX Item "-mscore5u"
+Specify the \s-1SCORE5U\s0 of the target architecture.
+.IP "\fB\-mscore7\fR" 4
+.IX Item "-mscore7"
+Specify the \s-1SCORE7\s0 as the target architecture. This is the default.
+.IP "\fB\-mscore7d\fR" 4
+.IX Item "-mscore7d"
+Specify the \s-1SCORE7D\s0 as the target architecture.
.PP
\fI\s-1SH\s0 Options\fR
.IX Subsection "SH Options"
@@ -8717,6 +11634,26 @@ single-precision mode by default.
.IP "\fB\-m4\fR" 4
.IX Item "-m4"
Generate code for the \s-1SH4\s0.
+.IP "\fB\-m4a\-nofpu\fR" 4
+.IX Item "-m4a-nofpu"
+Generate code for the SH4al\-dsp, or for a SH4a in such a way that the
+floating-point unit is not used.
+.IP "\fB\-m4a\-single\-only\fR" 4
+.IX Item "-m4a-single-only"
+Generate code for the SH4a, in such a way that no double-precision
+floating point operations are used.
+.IP "\fB\-m4a\-single\fR" 4
+.IX Item "-m4a-single"
+Generate code for the SH4a assuming the floating-point unit is in
+single-precision mode by default.
+.IP "\fB\-m4a\fR" 4
+.IX Item "-m4a"
+Generate code for the SH4a.
+.IP "\fB\-m4al\fR" 4
+.IX Item "-m4al"
+Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes
+\&\fB\-dsp\fR to the assembler. \s-1GCC\s0 doesn't generate any \s-1DSP\s0
+instructions at the moment.
.IP "\fB\-mb\fR" 4
.IX Item "-mb"
Compile code for the processor in big endian mode.
@@ -8742,6 +11679,14 @@ Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR.
.IP "\fB\-mhitachi\fR" 4
.IX Item "-mhitachi"
Comply with the calling conventions defined by Renesas.
+.IP "\fB\-mrenesas\fR" 4
+.IX Item "-mrenesas"
+Comply with the calling conventions defined by Renesas.
+.IP "\fB\-mno\-renesas\fR" 4
+.IX Item "-mno-renesas"
+Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas
+conventions were available. This option is the default for all
+targets of the \s-1SH\s0 toolchain except for \fBsh-symbianelf\fR.
.IP "\fB\-mnomacsave\fR" 4
.IX Item "-mnomacsave"
Mark the \f(CW\*(C`MAC\*(C'\fR register as call\-clobbered, even if
@@ -8749,6 +11694,11 @@ Mark the \f(CW\*(C`MAC\*(C'\fR register as call\-clobbered, even if
.IP "\fB\-mieee\fR" 4
.IX Item "-mieee"
Increase IEEE-compliance of floating-point code.
+At the moment, this is equivalent to \fB\-fno\-finite\-math\-only\fR.
+When generating 16 bit \s-1SH\s0 opcodes, getting IEEE-conforming results for
+comparisons of NANs / infinities incurs extra overhead in every
+floating point comparison, therefore the default is set to
+\&\fB\-ffinite\-math\-only\fR.
.IP "\fB\-misize\fR" 4
.IX Item "-misize"
Dump instruction size and location in the assembly code.
@@ -8769,6 +11719,361 @@ Generate a library function call to invalidate instruction cache
entries, after fixing up a trampoline. This library function call
doesn't assume it can write to the whole memory address space. This
is the default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR.
+.IP "\fB\-multcost=\fR\fInumber\fR" 4
+.IX Item "-multcost=number"
+Set the cost to assume for a multiply insn.
+.IP "\fB\-mdiv=\fR\fIstrategy\fR" 4
+.IX Item "-mdiv=strategy"
+Set the division strategy to use for SHmedia code. \fIstrategy\fR must be
+one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call,
+inv:call2, inv:fp .
+\&\*(L"fp\*(R" performs the operation in floating point. This has a very high latency,
+but needs only a few instructions, so it might be a good choice if
+your code has enough easily exploitable \s-1ILP\s0 to allow the compiler to
+schedule the floating point instructions together with other instructions.
+Division by zero causes a floating point exception.
+\&\*(L"inv\*(R" uses integer operations to calculate the inverse of the divisor,
+and then multiplies the dividend with the inverse. This strategy allows
+cse and hoisting of the inverse calculation. Division by zero calculates
+an unspecified result, but does not trap.
+\&\*(L"inv:minlat\*(R" is a variant of \*(L"inv\*(R" where if no cse / hoisting opportunities
+have been found, or if the entire operation has been hoisted to the same
+place, the last stages of the inverse calculation are intertwined with the
+final multiply to reduce the overall latency, at the expense of using a few
+more instructions, and thus offering fewer scheduling opportunities with
+other code.
+\&\*(L"call\*(R" calls a library function that usually implements the inv:minlat
+strategy.
+This gives high code density for m5\-*media\-nofpu compilations.
+\&\*(L"call2\*(R" uses a different entry point of the same library function, where it
+assumes that a pointer to a lookup table has already been set up, which
+exposes the pointer load to cse / code hoisting optimizations.
+\&\*(L"inv:call\*(R", \*(L"inv:call2\*(R" and \*(L"inv:fp\*(R" all use the \*(L"inv\*(R" algorithm for initial
+code generation, but if the code stays unoptimized, revert to the \*(L"call\*(R",
+\&\*(L"call2\*(R", or \*(L"fp\*(R" strategies, respectively. Note that the
+potentially-trapping side effect of division by zero is carried by a
+separate instruction, so it is possible that all the integer instructions
+are hoisted out, but the marker for the side effect stays where it is.
+A recombination to fp operations or a call is not possible in that case.
+\&\*(L"inv20u\*(R" and \*(L"inv20l\*(R" are variants of the \*(L"inv:minlat\*(R" strategy. In the case
+that the inverse calculation was nor separated from the multiply, they speed
+up division where the dividend fits into 20 bits (plus sign where applicable),
+by inserting a test to skip a number of operations in this case; this test
+slows down the case of larger dividends. inv20u assumes the case of a such
+a small dividend to be unlikely, and inv20l assumes it to be likely.
+.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4
+.IX Item "-mdivsi3_libfunc=name"
+Set the name of the library function used for 32 bit signed division to
+\&\fIname\fR. This only affect the name used in the call and inv:call
+division strategies, and the compiler will still expect the same
+sets of input/output/clobbered registers as if this option was not present.
+.IP "\fB\-madjust\-unroll\fR" 4
+.IX Item "-madjust-unroll"
+Throttle unrolling to avoid thrashing target registers.
+This option only has an effect if the gcc code base supports the
+\&\s-1TARGET_ADJUST_UNROLL_MAX\s0 target hook.
+.IP "\fB\-mindexed\-addressing\fR" 4
+.IX Item "-mindexed-addressing"
+Enable the use of the indexed addressing mode for SHmedia32/SHcompact.
+This is only safe if the hardware and/or \s-1OS\s0 implement 32 bit wrap-around
+semantics for the indexed addressing mode. The architecture allows the
+implementation of processors with 64 bit \s-1MMU\s0, which the \s-1OS\s0 could use to
+get 32 bit addressing, but since no current hardware implementation supports
+this or any other way to make the indexed addressing mode safe to use in
+the 32 bit \s-1ABI\s0, the default is \-mno\-indexed\-addressing.
+.IP "\fB\-mgettrcost=\fR\fInumber\fR" 4
+.IX Item "-mgettrcost=number"
+Set the cost assumed for the gettr instruction to \fInumber\fR.
+The default is 2 if \fB\-mpt\-fixed\fR is in effect, 100 otherwise.
+.IP "\fB\-mpt\-fixed\fR" 4
+.IX Item "-mpt-fixed"
+Assume pt* instructions won't trap. This will generally generate better
+scheduled code, but is unsafe on current hardware. The current architecture
+definition says that ptabs and ptrel trap when the target anded with 3 is 3.
+This has the unintentional effect of making it unsafe to schedule ptabs /
+ptrel before a branch, or hoist it out of a loop. For example,
+_\|_do_global_ctors, a part of libgcc that runs constructors at program
+startup, calls functions in a list which is delimited by \-1. With the
+\&\-mpt\-fixed option, the ptabs will be done before testing against \-1.
+That means that all the constructors will be run a bit quicker, but when
+the loop comes to the end of the list, the program crashes because ptabs
+loads \-1 into a target register. Since this option is unsafe for any
+hardware implementing the current architecture specification, the default
+is \-mno\-pt\-fixed. Unless the user specifies a specific cost with
+\&\fB\-mgettrcost\fR, \-mno\-pt\-fixed also implies \fB\-mgettrcost=100\fR;
+this deters register allocation using target registers for storing
+ordinary integers.
+.IP "\fB\-minvalid\-symbols\fR" 4
+.IX Item "-minvalid-symbols"
+Assume symbols might be invalid. Ordinary function symbols generated by
+the compiler will always be valid to load with movi/shori/ptabs or
+movi/shori/ptrel, but with assembler and/or linker tricks it is possible
+to generate symbols that will cause ptabs / ptrel to trap.
+This option is only meaningful when \fB\-mno\-pt\-fixed\fR is in effect.
+It will then prevent cross-basic-block cse, hoisting and most scheduling
+of symbol loads. The default is \fB\-mno\-invalid\-symbols\fR.
+.PP
+\fI\s-1SPARC\s0 Options\fR
+.IX Subsection "SPARC Options"
+.PP
+These \fB\-m\fR options are supported on the \s-1SPARC:\s0
+.IP "\fB\-mno\-app\-regs\fR" 4
+.IX Item "-mno-app-regs"
+.PD 0
+.IP "\fB\-mapp\-regs\fR" 4
+.IX Item "-mapp-regs"
+.PD
+Specify \fB\-mapp\-regs\fR to generate output using the global registers
+2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This
+is the default.
+.Sp
+To be fully \s-1SVR4\s0 \s-1ABI\s0 compliant at the cost of some performance loss,
+specify \fB\-mno\-app\-regs\fR. You should compile libraries and system
+software with this option.
+.IP "\fB\-mfpu\fR" 4
+.IX Item "-mfpu"
+.PD 0
+.IP "\fB\-mhard\-float\fR" 4
+.IX Item "-mhard-float"
+.PD
+Generate output containing floating point instructions. This is the
+default.
+.IP "\fB\-mno\-fpu\fR" 4
+.IX Item "-mno-fpu"
+.PD 0
+.IP "\fB\-msoft\-float\fR" 4
+.IX Item "-msoft-float"
+.PD
+Generate output containing library calls for floating point.
+\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0
+targets. Normally the facilities of the machine's usual C compiler are
+used, but this cannot be done directly in cross\-compilation. You must make
+your own arrangements to provide suitable library functions for
+cross\-compilation. The embedded targets \fBsparc\-*\-aout\fR and
+\&\fBsparclite\-*\-*\fR do provide software floating point support.
+.Sp
+\&\fB\-msoft\-float\fR changes the calling convention in the output file;
+therefore, it is only useful if you compile \fIall\fR of a program with
+this option. In particular, you need to compile \fIlibgcc.a\fR, the
+library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for
+this to work.
+.IP "\fB\-mhard\-quad\-float\fR" 4
+.IX Item "-mhard-quad-float"
+Generate output containing quad-word (long double) floating point
+instructions.
+.IP "\fB\-msoft\-quad\-float\fR" 4
+.IX Item "-msoft-quad-float"
+Generate output containing library calls for quad-word (long double)
+floating point instructions. The functions called are those specified
+in the \s-1SPARC\s0 \s-1ABI\s0. This is the default.
+.Sp
+As of this writing, there are no \s-1SPARC\s0 implementations that have hardware
+support for the quad-word floating point instructions. They all invoke
+a trap handler for one of these instructions, and then the trap handler
+emulates the effect of the instruction. Because of the trap handler overhead,
+this is much slower than calling the \s-1ABI\s0 library routines. Thus the
+\&\fB\-msoft\-quad\-float\fR option is the default.
+.IP "\fB\-mno\-unaligned\-doubles\fR" 4
+.IX Item "-mno-unaligned-doubles"
+.PD 0
+.IP "\fB\-munaligned\-doubles\fR" 4
+.IX Item "-munaligned-doubles"
+.PD
+Assume that doubles have 8 byte alignment. This is the default.
+.Sp
+With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8 byte
+alignment only if they are contained in another type, or if they have an
+absolute address. Otherwise, it assumes they have 4 byte alignment.
+Specifying this option avoids some rare compatibility problems with code
+generated by other compilers. It is not the default because it results
+in a performance loss, especially for floating point code.
+.IP "\fB\-mno\-faster\-structs\fR" 4
+.IX Item "-mno-faster-structs"
+.PD 0
+.IP "\fB\-mfaster\-structs\fR" 4
+.IX Item "-mfaster-structs"
+.PD
+With \fB\-mfaster\-structs\fR, the compiler assumes that structures
+should have 8 byte alignment. This enables the use of pairs of
+\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure
+assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs.
+However, the use of this changed alignment directly violates the \s-1SPARC\s0
+\&\s-1ABI\s0. Thus, it's intended only for use on targets where the developer
+acknowledges that their resulting code will not be directly in line with
+the rules of the \s-1ABI\s0.
+.IP "\fB\-mimpure\-text\fR" 4
+.IX Item "-mimpure-text"
+\&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells
+the compiler to not pass \fB\-z text\fR to the linker when linking a
+shared object. Using this option, you can link position-dependent
+code into a shared object.
+.Sp
+\&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against
+allocatable but non-writable sections\*(R" linker error message.
+However, the necessary relocations will trigger copy\-on\-write, and the
+shared object is not actually shared across processes. Instead of
+using \fB\-mimpure\-text\fR, you should compile all source code with
+\&\fB\-fpic\fR or \fB\-fPIC\fR.
+.Sp
+This option is only available on SunOS and Solaris.
+.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
+.IX Item "-mcpu=cpu_type"
+Set the instruction set, register set, and instruction scheduling parameters
+for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are
+\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBsparclite\fR,
+\&\fBf930\fR, \fBf934\fR, \fBhypersparc\fR, \fBsparclite86x\fR,
+\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR,
+\&\fBultrasparc3\fR, and \fBniagara\fR.
+.Sp
+Default instruction scheduling parameters are used for values that select
+an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR,
+\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR.
+.Sp
+Here is a list of each supported architecture and their supported
+implementations.
+.Sp
+.Vb 5
+\& v7: cypress
+\& v8: supersparc, hypersparc
+\& sparclite: f930, f934, sparclite86x
+\& sparclet: tsc701
+\& v9: ultrasparc, ultrasparc3, niagara
+.Ve
+.Sp
+By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7
+variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler
+additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the
+SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
+SPARCStation 1, 2, \s-1IPX\s0 etc.
+.Sp
+With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0
+architecture. The only difference from V7 code is that the compiler emits
+the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0
+but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=supersparc\fR, the compiler additionally
+optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
+2000 series.
+.Sp
+With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of
+the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step
+and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7\s0.
+With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the
+Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU\s0. With
+\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu
+\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU\s0.
+.Sp
+With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of
+the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate,
+integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet
+but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=tsc701\fR, the compiler additionally
+optimizes it for the \s-1TEMIC\s0 SPARClet chip.
+.Sp
+With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0
+architecture. This adds 64\-bit integer and floating-point move instructions,
+3 additional floating-point condition code registers and conditional move
+instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally
+optimizes it for the Sun UltraSPARC I/II/IIi chips. With
+\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the
+Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
+\&\fB\-mcpu=niagara\fR, the compiler additionally optimizes it for
+Sun UltraSPARC T1 chips.
+.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
+.IX Item "-mtune=cpu_type"
+Set the instruction scheduling parameters for machine type
+\&\fIcpu_type\fR, but do not set the instruction set or register set that the
+option \fB\-mcpu=\fR\fIcpu_type\fR would.
+.Sp
+The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for
+\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those
+that select a particular cpu implementation. Those are \fBcypress\fR,
+\&\fBsupersparc\fR, \fBhypersparc\fR, \fBf930\fR, \fBf934\fR,
+\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR,
+\&\fBultrasparc3\fR, and \fBniagara\fR.
+.IP "\fB\-mv8plus\fR" 4
+.IX Item "-mv8plus"
+.PD 0
+.IP "\fB\-mno\-v8plus\fR" 4
+.IX Item "-mno-v8plus"
+.PD
+With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+\s0 \s-1ABI\s0. The
+difference from the V8 \s-1ABI\s0 is that the global and out registers are
+considered 64\-bit wide. This is enabled by default on Solaris in 32\-bit
+mode for all \s-1SPARC\-V9\s0 processors.
+.IP "\fB\-mvis\fR" 4
+.IX Item "-mvis"
+.PD 0
+.IP "\fB\-mno\-vis\fR" 4
+.IX Item "-mno-vis"
+.PD
+With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC
+Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR.
+.PP
+These \fB\-m\fR options are supported in addition to the above
+on \s-1SPARC\-V9\s0 processors in 64\-bit environments:
+.IP "\fB\-mlittle\-endian\fR" 4
+.IX Item "-mlittle-endian"
+Generate code for a processor running in little-endian mode. It is only
+available for a few configurations and most notably not on Solaris and Linux.
+.IP "\fB\-m32\fR" 4
+.IX Item "-m32"
+.PD 0
+.IP "\fB\-m64\fR" 4
+.IX Item "-m64"
+.PD
+Generate code for a 32\-bit or 64\-bit environment.
+The 32\-bit environment sets int, long and pointer to 32 bits.
+The 64\-bit environment sets int to 32 bits and long and pointer
+to 64 bits.
+.IP "\fB\-mcmodel=medlow\fR" 4
+.IX Item "-mcmodel=medlow"
+Generate code for the Medium/Low code model: 64\-bit addresses, programs
+must be linked in the low 32 bits of memory. Programs can be statically
+or dynamically linked.
+.IP "\fB\-mcmodel=medmid\fR" 4
+.IX Item "-mcmodel=medmid"
+Generate code for the Medium/Middle code model: 64\-bit addresses, programs
+must be linked in the low 44 bits of memory, the text and data segments must
+be less than 2GB in size and the data segment must be located within 2GB of
+the text segment.
+.IP "\fB\-mcmodel=medany\fR" 4
+.IX Item "-mcmodel=medany"
+Generate code for the Medium/Anywhere code model: 64\-bit addresses, programs
+may be linked anywhere in memory, the text and data segments must be less
+than 2GB in size and the data segment must be located within 2GB of the
+text segment.
+.IP "\fB\-mcmodel=embmedany\fR" 4
+.IX Item "-mcmodel=embmedany"
+Generate code for the Medium/Anywhere code model for embedded systems:
+64\-bit addresses, the text and data segments must be less than 2GB in
+size, both starting anywhere in memory (determined at link time). The
+global register \f(CW%g4\fR points to the base of the data segment. Programs
+are statically linked and \s-1PIC\s0 is not supported.
+.IP "\fB\-mstack\-bias\fR" 4
+.IX Item "-mstack-bias"
+.PD 0
+.IP "\fB\-mno\-stack\-bias\fR" 4
+.IX Item "-mno-stack-bias"
+.PD
+With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and
+frame pointer if present, are offset by \-2047 which must be added back
+when making stack frame references. This is the default in 64\-bit mode.
+Otherwise, assume no such offset is present.
+.PP
+These switches are supported in addition to the above on Solaris:
+.IP "\fB\-threads\fR" 4
+.IX Item "-threads"
+Add support for multithreading using the Solaris threads library. This
+option sets flags for both the preprocessor and linker. This option does
+not affect the thread safety of object code produced by the compiler or
+that of libraries supplied with it.
+.IP "\fB\-pthreads\fR" 4
+.IX Item "-pthreads"
+Add support for multithreading using the \s-1POSIX\s0 threads library. This
+option sets flags for both the preprocessor and linker. This option does
+not affect the thread safety of object code produced by the compiler or
+that of libraries supplied with it.
+.IP "\fB\-pthread\fR" 4
+.IX Item "-pthread"
+This is a synonym for \fB\-pthreads\fR.
.PP
\fIOptions for System V\fR
.IX Subsection "Options for System V"
@@ -9042,883 +12347,27 @@ This option will suppress generation of the \s-1CALLT\s0 instruction for the
v850e and v850e1 flavors of the v850 architecture. The default is
\&\fB\-mno\-disable\-callt\fR which allows the \s-1CALLT\s0 instruction to be used.
.PP
-\fI\s-1ARC\s0 Options\fR
-.IX Subsection "ARC Options"
-.PP
-These options are defined for \s-1ARC\s0 implementations:
-.IP "\fB\-EL\fR" 4
-.IX Item "-EL"
-Compile code for little endian mode. This is the default.
-.IP "\fB\-EB\fR" 4
-.IX Item "-EB"
-Compile code for big endian mode.
-.IP "\fB\-mmangle\-cpu\fR" 4
-.IX Item "-mmangle-cpu"
-Prepend the name of the cpu to all public symbol names.
-In multiple-processor systems, there are many \s-1ARC\s0 variants with different
-instruction and register set characteristics. This flag prevents code
-compiled for one cpu to be linked with code compiled for another.
-No facility exists for handling variants that are ``almost identical''.
-This is an all or nothing option.
-.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
-.IX Item "-mcpu=cpu"
-Compile code for \s-1ARC\s0 variant \fIcpu\fR.
-Which variants are supported depend on the configuration.
-All variants support \fB\-mcpu=base\fR, this is the default.
-.IP "\fB\-mtext=\fR\fItext-section\fR" 4
-.IX Item "-mtext=text-section"
-.PD 0
-.IP "\fB\-mdata=\fR\fIdata-section\fR" 4
-.IX Item "-mdata=data-section"
-.IP "\fB\-mrodata=\fR\fIreadonly-data-section\fR" 4
-.IX Item "-mrodata=readonly-data-section"
-.PD
-Put functions, data, and readonly data in \fItext-section\fR,
-\&\fIdata-section\fR, and \fIreadonly-data-section\fR respectively
-by default. This can be overridden with the \f(CW\*(C`section\*(C'\fR attribute.
-.PP
-\fI\s-1NS32K\s0 Options\fR
-.IX Subsection "NS32K Options"
-.PP
-These are the \fB\-m\fR options defined for the 32000 series. The default
-values for these options depends on which style of 32000 was selected when
-the compiler was configured; the defaults for the most common choices are
-given below.
-.IP "\fB\-m32032\fR" 4
-.IX Item "-m32032"
-.PD 0
-.IP "\fB\-m32032\fR" 4
-.IX Item "-m32032"
-.PD
-Generate output for a 32032. This is the default
-when the compiler is configured for 32032 and 32016 based systems.
-.IP "\fB\-m32332\fR" 4
-.IX Item "-m32332"
-.PD 0
-.IP "\fB\-m32332\fR" 4
-.IX Item "-m32332"
-.PD
-Generate output for a 32332. This is the default
-when the compiler is configured for 32332\-based systems.
-.IP "\fB\-m32532\fR" 4
-.IX Item "-m32532"
-.PD 0
-.IP "\fB\-m32532\fR" 4
-.IX Item "-m32532"
-.PD
-Generate output for a 32532. This is the default
-when the compiler is configured for 32532\-based systems.
-.IP "\fB\-m32081\fR" 4
-.IX Item "-m32081"
-Generate output containing 32081 instructions for floating point.
-This is the default for all systems.
-.IP "\fB\-m32381\fR" 4
-.IX Item "-m32381"
-Generate output containing 32381 instructions for floating point. This
-also implies \fB\-m32081\fR. The 32381 is only compatible with the 32332
-and 32532 cpus. This is the default for the pc532\-netbsd configuration.
-.IP "\fB\-mmulti\-add\fR" 4
-.IX Item "-mmulti-add"
-Try and generate multiply-add floating point instructions \f(CW\*(C`polyF\*(C'\fR
-and \f(CW\*(C`dotF\*(C'\fR. This option is only available if the \fB\-m32381\fR
-option is in effect. Using these instructions requires changes to
-register allocation which generally has a negative impact on
-performance. This option should only be enabled when compiling code
-particularly likely to make heavy use of multiply-add instructions.
-.IP "\fB\-mnomulti\-add\fR" 4
-.IX Item "-mnomulti-add"
-Do not try and generate multiply-add floating point instructions
-\&\f(CW\*(C`polyF\*(C'\fR and \f(CW\*(C`dotF\*(C'\fR. This is the default on all platforms.
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-Generate output containing library calls for floating point.
-\&\fBWarning:\fR the requisite libraries may not be available.
-.IP "\fB\-mieee\-compare\fR" 4
-.IX Item "-mieee-compare"
-.PD 0
-.IP "\fB\-mno\-ieee\-compare\fR" 4
-.IX Item "-mno-ieee-compare"
-.PD
-Control whether or not the compiler uses \s-1IEEE\s0 floating point
-comparisons. These handle correctly the case where the result of a
-comparison is unordered.
-\&\fBWarning:\fR the requisite kernel support may not be available.
-.IP "\fB\-mnobitfield\fR" 4
-.IX Item "-mnobitfield"
-Do not use the bit-field instructions. On some machines it is faster to
-use shifting and masking operations. This is the default for the pc532.
-.IP "\fB\-mbitfield\fR" 4
-.IX Item "-mbitfield"
-Do use the bit-field instructions. This is the default for all platforms
-except the pc532.
-.IP "\fB\-mrtd\fR" 4
-.IX Item "-mrtd"
-Use a different function-calling convention, in which functions
-that take a fixed number of arguments return pop their
-arguments on return with the \f(CW\*(C`ret\*(C'\fR instruction.
-.Sp
-This calling convention is incompatible with the one normally
-used on Unix, so you cannot use it if you need to call libraries
-compiled with the Unix compiler.
-.Sp
-Also, you must provide function prototypes for all functions that
-take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
-otherwise incorrect code will be generated for calls to those
-functions.
-.Sp
-In addition, seriously incorrect code will result if you call a
-function with too many arguments. (Normally, extra arguments are
-harmlessly ignored.)
-.Sp
-This option takes its name from the 680x0 \f(CW\*(C`rtd\*(C'\fR instruction.
-.IP "\fB\-mregparam\fR" 4
-.IX Item "-mregparam"
-Use a different function-calling convention where the first two arguments
-are passed in registers.
-.Sp
-This calling convention is incompatible with the one normally
-used on Unix, so you cannot use it if you need to call libraries
-compiled with the Unix compiler.
-.IP "\fB\-mnoregparam\fR" 4
-.IX Item "-mnoregparam"
-Do not pass any arguments in registers. This is the default for all
-targets.
-.IP "\fB\-msb\fR" 4
-.IX Item "-msb"
-It is \s-1OK\s0 to use the sb as an index register which is always loaded with
-zero. This is the default for the pc532\-netbsd target.
-.IP "\fB\-mnosb\fR" 4
-.IX Item "-mnosb"
-The sb register is not available for use or has not been initialized to
-zero by the run time system. This is the default for all targets except
-the pc532\-netbsd. It is also implied whenever \fB\-mhimem\fR or
-\&\fB\-fpic\fR is set.
-.IP "\fB\-mhimem\fR" 4
-.IX Item "-mhimem"
-Many ns32000 series addressing modes use displacements of up to 512MB.
-If an address is above 512MB then displacements from zero can not be used.
-This option causes code to be generated which can be loaded above 512MB.
-This may be useful for operating systems or \s-1ROM\s0 code.
-.IP "\fB\-mnohimem\fR" 4
-.IX Item "-mnohimem"
-Assume code will be loaded in the first 512MB of virtual address space.
-This is the default for all platforms.
-.PP
-\fI\s-1AVR\s0 Options\fR
-.IX Subsection "AVR Options"
-.PP
-These options are defined for \s-1AVR\s0 implementations:
-.IP "\fB\-mmcu=\fR\fImcu\fR" 4
-.IX Item "-mmcu=mcu"
-Specify \s-1ATMEL\s0 \s-1AVR\s0 instruction set or \s-1MCU\s0 type.
-.Sp
-Instruction set avr1 is for the minimal \s-1AVR\s0 core, not supported by the C
-compiler, only for assembler programs (\s-1MCU\s0 types: at90s1200, attiny10,
-attiny11, attiny12, attiny15, attiny28).
-.Sp
-Instruction set avr2 (default) is for the classic \s-1AVR\s0 core with up to
-8K program memory space (\s-1MCU\s0 types: at90s2313, at90s2323, attiny22,
-at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
-at90c8534, at90s8535).
-.Sp
-Instruction set avr3 is for the classic \s-1AVR\s0 core with up to 128K program
-memory space (\s-1MCU\s0 types: atmega103, atmega603, at43usb320, at76c711).
-.Sp
-Instruction set avr4 is for the enhanced \s-1AVR\s0 core with up to 8K program
-memory space (\s-1MCU\s0 types: atmega8, atmega83, atmega85).
-.Sp
-Instruction set avr5 is for the enhanced \s-1AVR\s0 core with up to 128K program
-memory space (\s-1MCU\s0 types: atmega16, atmega161, atmega163, atmega32, atmega323,
-atmega64, atmega128, at43usb355, at94k).
-.IP "\fB\-msize\fR" 4
-.IX Item "-msize"
-Output instruction sizes to the asm file.
-.IP "\fB\-minit\-stack=\fR\fIN\fR" 4
-.IX Item "-minit-stack=N"
-Specify the initial stack address, which may be a symbol or numeric value,
-\&\fB_\|_stack\fR is the default.
-.IP "\fB\-mno\-interrupts\fR" 4
-.IX Item "-mno-interrupts"
-Generated code is not compatible with hardware interrupts.
-Code size will be smaller.
-.IP "\fB\-mcall\-prologues\fR" 4
-.IX Item "-mcall-prologues"
-Functions prologues/epilogues expanded as call to appropriate
-subroutines. Code size will be smaller.
-.IP "\fB\-mno\-tablejump\fR" 4
-.IX Item "-mno-tablejump"
-Do not generate tablejump insns which sometimes increase code size.
-.IP "\fB\-mtiny\-stack\fR" 4
-.IX Item "-mtiny-stack"
-Change only the low 8 bits of the stack pointer.
-.PP
-\fIMCore Options\fR
-.IX Subsection "MCore Options"
-.PP
-These are the \fB\-m\fR options defined for the Motorola M*Core
-processors.
-.IP "\fB\-mhardlit\fR" 4
-.IX Item "-mhardlit"
-.PD 0
-.IP "\fB\-mno\-hardlit\fR" 4
-.IX Item "-mno-hardlit"
-.PD
-Inline constants into the code stream if it can be done in two
-instructions or less.
-.IP "\fB\-mdiv\fR" 4
-.IX Item "-mdiv"
-.PD 0
-.IP "\fB\-mno\-div\fR" 4
-.IX Item "-mno-div"
-.PD
-Use the divide instruction. (Enabled by default).
-.IP "\fB\-mrelax\-immediate\fR" 4
-.IX Item "-mrelax-immediate"
-.PD 0
-.IP "\fB\-mno\-relax\-immediate\fR" 4
-.IX Item "-mno-relax-immediate"
-.PD
-Allow arbitrary sized immediates in bit operations.
-.IP "\fB\-mwide\-bitfields\fR" 4
-.IX Item "-mwide-bitfields"
-.PD 0
-.IP "\fB\-mno\-wide\-bitfields\fR" 4
-.IX Item "-mno-wide-bitfields"
-.PD
-Always treat bit-fields as int\-sized.
-.IP "\fB\-m4byte\-functions\fR" 4
-.IX Item "-m4byte-functions"
-.PD 0
-.IP "\fB\-mno\-4byte\-functions\fR" 4
-.IX Item "-mno-4byte-functions"
-.PD
-Force all functions to be aligned to a four byte boundary.
-.IP "\fB\-mcallgraph\-data\fR" 4
-.IX Item "-mcallgraph-data"
-.PD 0
-.IP "\fB\-mno\-callgraph\-data\fR" 4
-.IX Item "-mno-callgraph-data"
-.PD
-Emit callgraph information.
-.IP "\fB\-mslow\-bytes\fR" 4
-.IX Item "-mslow-bytes"
-.PD 0
-.IP "\fB\-mno\-slow\-bytes\fR" 4
-.IX Item "-mno-slow-bytes"
-.PD
-Prefer word access when reading byte quantities.
-.IP "\fB\-mlittle\-endian\fR" 4
-.IX Item "-mlittle-endian"
-.PD 0
-.IP "\fB\-mbig\-endian\fR" 4
-.IX Item "-mbig-endian"
-.PD
-Generate code for a little endian target.
-.IP "\fB\-m210\fR" 4
-.IX Item "-m210"
-.PD 0
-.IP "\fB\-m340\fR" 4
-.IX Item "-m340"
-.PD
-Generate code for the 210 processor.
-.PP
-\fI\s-1IA\-64\s0 Options\fR
-.IX Subsection "IA-64 Options"
-.PP
-These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture.
-.IP "\fB\-mbig\-endian\fR" 4
-.IX Item "-mbig-endian"
-Generate code for a big endian target. This is the default for \s-1HP\-UX\s0.
-.IP "\fB\-mlittle\-endian\fR" 4
-.IX Item "-mlittle-endian"
-Generate code for a little endian target. This is the default for \s-1AIX5\s0
-and GNU/Linux.
-.IP "\fB\-mgnu\-as\fR" 4
-.IX Item "-mgnu-as"
-.PD 0
-.IP "\fB\-mno\-gnu\-as\fR" 4
-.IX Item "-mno-gnu-as"
-.PD
-Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default.
-.IP "\fB\-mgnu\-ld\fR" 4
-.IX Item "-mgnu-ld"
-.PD 0
-.IP "\fB\-mno\-gnu\-ld\fR" 4
-.IX Item "-mno-gnu-ld"
-.PD
-Generate (or don't) code for the \s-1GNU\s0 linker. This is the default.
-.IP "\fB\-mno\-pic\fR" 4
-.IX Item "-mno-pic"
-Generate code that does not use a global pointer register. The result
-is not position independent code, and violates the \s-1IA\-64\s0 \s-1ABI\s0.
-.IP "\fB\-mvolatile\-asm\-stop\fR" 4
-.IX Item "-mvolatile-asm-stop"
-.PD 0
-.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4
-.IX Item "-mno-volatile-asm-stop"
-.PD
-Generate (or don't) a stop bit immediately before and after volatile asm
-statements.
-.IP "\fB\-mb\-step\fR" 4
-.IX Item "-mb-step"
-Generate code that works around Itanium B step errata.
-.IP "\fB\-mregister\-names\fR" 4
-.IX Item "-mregister-names"
-.PD 0
-.IP "\fB\-mno\-register\-names\fR" 4
-.IX Item "-mno-register-names"
-.PD
-Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for
-the stacked registers. This may make assembler output more readable.
-.IP "\fB\-mno\-sdata\fR" 4
-.IX Item "-mno-sdata"
-.PD 0
-.IP "\fB\-msdata\fR" 4
-.IX Item "-msdata"
-.PD
-Disable (or enable) optimizations that use the small data section. This may
-be useful for working around optimizer bugs.
-.IP "\fB\-mconstant\-gp\fR" 4
-.IX Item "-mconstant-gp"
-Generate code that uses a single constant global pointer value. This is
-useful when compiling kernel code.
-.IP "\fB\-mauto\-pic\fR" 4
-.IX Item "-mauto-pic"
-Generate code that is self\-relocatable. This implies \fB\-mconstant\-gp\fR.
-This is useful when compiling firmware code.
-.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4
-.IX Item "-minline-float-divide-min-latency"
-Generate code for inline divides of floating point values
-using the minimum latency algorithm.
-.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4
-.IX Item "-minline-float-divide-max-throughput"
-Generate code for inline divides of floating point values
-using the maximum throughput algorithm.
-.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4
-.IX Item "-minline-int-divide-min-latency"
-Generate code for inline divides of integer values
-using the minimum latency algorithm.
-.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4
-.IX Item "-minline-int-divide-max-throughput"
-Generate code for inline divides of integer values
-using the maximum throughput algorithm.
-.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4
-.IX Item "-minline-sqrt-min-latency"
-Generate code for inline square roots
-using the minimum latency algorithm.
-.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4
-.IX Item "-minline-sqrt-max-throughput"
-Generate code for inline square roots
-using the maximum throughput algorithm.
-.IP "\fB\-mno\-dwarf2\-asm\fR" 4
-.IX Item "-mno-dwarf2-asm"
-.PD 0
-.IP "\fB\-mdwarf2\-asm\fR" 4
-.IX Item "-mdwarf2-asm"
-.PD
-Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging
-info. This may be useful when not using the \s-1GNU\s0 assembler.
-.IP "\fB\-mearly\-stop\-bits\fR" 4
-.IX Item "-mearly-stop-bits"
-.PD 0
-.IP "\fB\-mno\-early\-stop\-bits\fR" 4
-.IX Item "-mno-early-stop-bits"
-.PD
-Allow stop bits to be placed earlier than immediately preceding the
-instruction that triggered the stop bit. This can improve instruction
-scheduling, but does not always do so.
-.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
-.IX Item "-mfixed-range=register-range"
-Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator can not use. This is
-useful when compiling kernel code. A register range is specified as
-two registers separated by a dash. Multiple register ranges can be
-specified separated by a comma.
-.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4
-.IX Item "-mtls-size=tls-size"
-Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and
-64.
-.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
-.IX Item "-mtune=cpu-type"
-Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are
-itanium, itanium1, merced, itanium2, and mckinley.
-.IP "\fB\-mt\fR" 4
-.IX Item "-mt"
-.PD 0
-.IP "\fB\-pthread\fR" 4
-.IX Item "-pthread"
-.PD
-Add support for multithreading using the \s-1POSIX\s0 threads library. This
-option sets flags for both the preprocessor and linker. It does
-not affect the thread safety of object code produced by the compiler or
-that of libraries supplied with it. These are HP-UX specific flags.
-.IP "\fB\-milp32\fR" 4
-.IX Item "-milp32"
-.PD 0
-.IP "\fB\-mlp64\fR" 4
-.IX Item "-mlp64"
-.PD
-Generate code for a 32\-bit or 64\-bit environment.
-The 32\-bit environment sets int, long and pointer to 32 bits.
-The 64\-bit environment sets int to 32 bits and long and pointer
-to 64 bits. These are HP-UX specific flags.
-.PP
-\fID30V Options\fR
-.IX Subsection "D30V Options"
-.PP
-These \fB\-m\fR options are defined for D30V implementations:
-.IP "\fB\-mextmem\fR" 4
-.IX Item "-mextmem"
-Link the \fB.text\fR, \fB.data\fR, \fB.bss\fR, \fB.strings\fR,
-\&\fB.rodata\fR, \fB.rodata1\fR, \fB.data1\fR sections into external
-memory, which starts at location \f(CW0x80000000\fR.
-.IP "\fB\-mextmemory\fR" 4
-.IX Item "-mextmemory"
-Same as the \fB\-mextmem\fR switch.
-.IP "\fB\-monchip\fR" 4
-.IX Item "-monchip"
-Link the \fB.text\fR section into onchip text memory, which starts at
-location \f(CW0x0\fR. Also link \fB.data\fR, \fB.bss\fR,
-\&\fB.strings\fR, \fB.rodata\fR, \fB.rodata1\fR, \fB.data1\fR sections
-into onchip data memory, which starts at location \f(CW0x20000000\fR.
-.IP "\fB\-mno\-asm\-optimize\fR" 4
-.IX Item "-mno-asm-optimize"
-.PD 0
-.IP "\fB\-masm\-optimize\fR" 4
-.IX Item "-masm-optimize"
-.PD
-Disable (enable) passing \fB\-O\fR to the assembler when optimizing.
-The assembler uses the \fB\-O\fR option to automatically parallelize
-adjacent short instructions where possible.
-.IP "\fB\-mbranch\-cost=\fR\fIn\fR" 4
-.IX Item "-mbranch-cost=n"
-Increase the internal costs of branches to \fIn\fR. Higher costs means
-that the compiler will issue more instructions to avoid doing a branch.
-The default is 2.
-.IP "\fB\-mcond\-exec=\fR\fIn\fR" 4
-.IX Item "-mcond-exec=n"
-Specify the maximum number of conditionally executed instructions that
-replace a branch. The default is 4.
-.PP
-\fIS/390 and zSeries Options\fR
-.IX Subsection "S/390 and zSeries Options"
-.PP
-These are the \fB\-m\fR options defined for the S/390 and zSeries architecture.
-.IP "\fB\-mhard\-float\fR" 4
-.IX Item "-mhard-float"
-.PD 0
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-.PD
-Use (do not use) the hardware floating-point instructions and registers
-for floating-point operations. When \fB\-msoft\-float\fR is specified,
-functions in \fIlibgcc.a\fR will be used to perform floating-point
-operations. When \fB\-mhard\-float\fR is specified, the compiler
-generates \s-1IEEE\s0 floating-point instructions. This is the default.
-.IP "\fB\-mbackchain\fR" 4
-.IX Item "-mbackchain"
-.PD 0
-.IP "\fB\-mno\-backchain\fR" 4
-.IX Item "-mno-backchain"
-.PD
-Generate (or do not generate) code which maintains an explicit
-backchain within the stack frame that points to the caller's frame.
-This may be needed to allow debugging using tools that do not understand
-\&\s-1DWARF\-2\s0 call frame information. The default is not to generate the
-backchain.
-.IP "\fB\-msmall\-exec\fR" 4
-.IX Item "-msmall-exec"
-.PD 0
-.IP "\fB\-mno\-small\-exec\fR" 4
-.IX Item "-mno-small-exec"
-.PD
-Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction
-to do subroutine calls.
-This only works reliably if the total executable size does not
-exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead,
-which does not have this limitation.
-.IP "\fB\-m64\fR" 4
-.IX Item "-m64"
-.PD 0
-.IP "\fB\-m31\fR" 4
-.IX Item "-m31"
-.PD
-When \fB\-m31\fR is specified, generate code compliant to the
-GNU/Linux for S/390 \s-1ABI\s0. When \fB\-m64\fR is specified, generate
-code compliant to the GNU/Linux for zSeries \s-1ABI\s0. This allows \s-1GCC\s0 in
-particular to generate 64\-bit instructions. For the \fBs390\fR
-targets, the default is \fB\-m31\fR, while the \fBs390x\fR
-targets default to \fB\-m64\fR.
-.IP "\fB\-mzarch\fR" 4
-.IX Item "-mzarch"
-.PD 0
-.IP "\fB\-mesa\fR" 4
-.IX Item "-mesa"
-.PD
-When \fB\-mzarch\fR is specified, generate code using the
-instructions available on z/Architecture.
-When \fB\-mesa\fR is specified, generate code using the
-instructions available on \s-1ESA/390\s0. Note that \fB\-mesa\fR is
-not possible with \fB\-m64\fR.
-When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0,
-the default is \fB\-mesa\fR. When generating code compliant
-to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR.
-.IP "\fB\-mmvcle\fR" 4
-.IX Item "-mmvcle"
-.PD 0
-.IP "\fB\-mno\-mvcle\fR" 4
-.IX Item "-mno-mvcle"
-.PD
-Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction
-to perform block moves. When \fB\-mno\-mvcle\fR is specified,
-use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default.
-.IP "\fB\-mdebug\fR" 4
-.IX Item "-mdebug"
-.PD 0
-.IP "\fB\-mno\-debug\fR" 4
-.IX Item "-mno-debug"
-.PD
-Print (or do not print) additional debug information when compiling.
-The default is to not print debug information.
-.IP "\fB\-march=\fR\fIcpu-type\fR" 4
-.IX Item "-march=cpu-type"
-Generate code that will run on \fIcpu-type\fR, which is the name of a system
-representing a certain processor type. Possible values for
-\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, and \fBz990\fR.
-When generating code using the instructions available on z/Architecture,
-the default is \fB\-march=z900\fR. Otherwise, the default is
-\&\fB\-march=g5\fR.
-.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
-.IX Item "-mtune=cpu-type"
-Tune to \fIcpu-type\fR everything applicable about the generated code,
-except for the \s-1ABI\s0 and the set of available instructions.
-The list of \fIcpu-type\fR values is the same as for \fB\-march\fR.
-The default is the value used for \fB\-march\fR.
-.IP "\fB\-mfused\-madd\fR" 4
-.IX Item "-mfused-madd"
-.PD 0
-.IP "\fB\-mno\-fused\-madd\fR" 4
-.IX Item "-mno-fused-madd"
-.PD
-Generate code that uses (does not use) the floating point multiply and
-accumulate instructions. These instructions are generated by default if
-hardware floating point is used.
-.PP
-\fI\s-1CRIS\s0 Options\fR
-.IX Subsection "CRIS Options"
-.PP
-These options are defined specifically for the \s-1CRIS\s0 ports.
-.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4
-.IX Item "-march=architecture-type"
-.PD 0
-.IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4
-.IX Item "-mcpu=architecture-type"
-.PD
-Generate code for the specified architecture. The choices for
-\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for
-respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0.
-Default is \fBv0\fR except for cris\-axis\-linux\-gnu, where the default is
-\&\fBv10\fR.
-.IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4
-.IX Item "-mtune=architecture-type"
-Tune to \fIarchitecture-type\fR everything applicable about the generated
-code, except for the \s-1ABI\s0 and the set of available instructions. The
-choices for \fIarchitecture-type\fR are the same as for
-\&\fB\-march=\fR\fIarchitecture-type\fR.
-.IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4
-.IX Item "-mmax-stack-frame=n"
-Warn when the stack frame of a function exceeds \fIn\fR bytes.
-.IP "\fB\-melinux\-stacksize=\fR\fIn\fR" 4
-.IX Item "-melinux-stacksize=n"
-Only available with the \fBcris-axis-aout\fR target. Arranges for
-indications in the program to the kernel loader that the stack of the
-program should be set to \fIn\fR bytes.
-.IP "\fB\-metrax4\fR" 4
-.IX Item "-metrax4"
-.PD 0
-.IP "\fB\-metrax100\fR" 4
-.IX Item "-metrax100"
-.PD
-The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for
-\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively.
-.IP "\fB\-mmul\-bug\-workaround\fR" 4
-.IX Item "-mmul-bug-workaround"
-.PD 0
-.IP "\fB\-mno\-mul\-bug\-workaround\fR" 4
-.IX Item "-mno-mul-bug-workaround"
-.PD
-Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0
-models where it applies. This option is active by default.
-.IP "\fB\-mpdebug\fR" 4
-.IX Item "-mpdebug"
-Enable CRIS-specific verbose debug-related information in the assembly
-code. This option also has the effect to turn off the \fB#NO_APP\fR
-formatted-code indicator to the assembler at the beginning of the
-assembly file.
-.IP "\fB\-mcc\-init\fR" 4
-.IX Item "-mcc-init"
-Do not use condition-code results from previous instruction; always emit
-compare and test instructions before use of condition codes.
-.IP "\fB\-mno\-side\-effects\fR" 4
-.IX Item "-mno-side-effects"
-Do not emit instructions with side-effects in addressing modes other than
-post\-increment.
-.IP "\fB\-mstack\-align\fR" 4
-.IX Item "-mstack-align"
-.PD 0
-.IP "\fB\-mno\-stack\-align\fR" 4
-.IX Item "-mno-stack-align"
-.IP "\fB\-mdata\-align\fR" 4
-.IX Item "-mdata-align"
-.IP "\fB\-mno\-data\-align\fR" 4
-.IX Item "-mno-data-align"
-.IP "\fB\-mconst\-align\fR" 4
-.IX Item "-mconst-align"
-.IP "\fB\-mno\-const\-align\fR" 4
-.IX Item "-mno-const-align"
-.PD
-These options (no\-options) arranges (eliminate arrangements) for the
-stack\-frame, individual data and constants to be aligned for the maximum
-single data access size for the chosen \s-1CPU\s0 model. The default is to
-arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are
-not affected by these options.
-.IP "\fB\-m32\-bit\fR" 4
-.IX Item "-m32-bit"
-.PD 0
-.IP "\fB\-m16\-bit\fR" 4
-.IX Item "-m16-bit"
-.IP "\fB\-m8\-bit\fR" 4
-.IX Item "-m8-bit"
-.PD
-Similar to the stack\- data\- and const-align options above, these options
-arrange for stack\-frame, writable data and constants to all be 32\-bit,
-16\-bit or 8\-bit aligned. The default is 32\-bit alignment.
-.IP "\fB\-mno\-prologue\-epilogue\fR" 4
-.IX Item "-mno-prologue-epilogue"
-.PD 0
-.IP "\fB\-mprologue\-epilogue\fR" 4
-.IX Item "-mprologue-epilogue"
-.PD
-With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and
-epilogue that sets up the stack-frame are omitted and no return
-instructions or return sequences are generated in the code. Use this
-option only together with visual inspection of the compiled code: no
-warnings or errors are generated when call-saved registers must be saved,
-or storage for local variable needs to be allocated.
-.IP "\fB\-mno\-gotplt\fR" 4
-.IX Item "-mno-gotplt"
-.PD 0
-.IP "\fB\-mgotplt\fR" 4
-.IX Item "-mgotplt"
-.PD
-With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate)
-instruction sequences that load addresses for functions from the \s-1PLT\s0 part
-of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the
-\&\s-1PLT\s0. The default is \fB\-mgotplt\fR.
-.IP "\fB\-maout\fR" 4
-.IX Item "-maout"
-Legacy no-op option only recognized with the cris-axis-aout target.
-.IP "\fB\-melf\fR" 4
-.IX Item "-melf"
-Legacy no-op option only recognized with the cris-axis-elf and
-cris-axis-linux-gnu targets.
-.IP "\fB\-melinux\fR" 4
-.IX Item "-melinux"
-Only recognized with the cris-axis-aout target, where it selects a
-GNU/linux\-like multilib, include files and instruction set for
-\&\fB\-march=v8\fR.
-.IP "\fB\-mlinux\fR" 4
-.IX Item "-mlinux"
-Legacy no-op option only recognized with the cris-axis-linux-gnu target.
-.IP "\fB\-sim\fR" 4
-.IX Item "-sim"
-This option, recognized for the cris-axis-aout and cris-axis-elf arranges
-to link with input-output functions from a simulator library. Code,
-initialized data and zero-initialized data are allocated consecutively.
-.IP "\fB\-sim2\fR" 4
-.IX Item "-sim2"
-Like \fB\-sim\fR, but pass linker options to locate initialized data at
-0x40000000 and zero-initialized data at 0x80000000.
+\fI\s-1VAX\s0 Options\fR
+.IX Subsection "VAX Options"
.PP
-\fI\s-1MMIX\s0 Options\fR
-.IX Subsection "MMIX Options"
+These \fB\-m\fR options are defined for the \s-1VAX:\s0
+.IP "\fB\-munix\fR" 4
+.IX Item "-munix"
+Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on)
+that the Unix assembler for the \s-1VAX\s0 cannot handle across long
+ranges.
+.IP "\fB\-mgnu\fR" 4
+.IX Item "-mgnu"
+Do output those jump instructions, on the assumption that you
+will assemble with the \s-1GNU\s0 assembler.
+.IP "\fB\-mg\fR" 4
+.IX Item "-mg"
+Output code for g\-format floating point numbers instead of d\-format.
.PP
-These options are defined for the \s-1MMIX:\s0
-.IP "\fB\-mlibfuncs\fR" 4
-.IX Item "-mlibfuncs"
-.PD 0
-.IP "\fB\-mno\-libfuncs\fR" 4
-.IX Item "-mno-libfuncs"
-.PD
-Specify that intrinsic library functions are being compiled, passing all
-values in registers, no matter the size.
-.IP "\fB\-mepsilon\fR" 4
-.IX Item "-mepsilon"
-.PD 0
-.IP "\fB\-mno\-epsilon\fR" 4
-.IX Item "-mno-epsilon"
-.PD
-Generate floating-point comparison instructions that compare with respect
-to the \f(CW\*(C`rE\*(C'\fR epsilon register.
-.IP "\fB\-mabi=mmixware\fR" 4
-.IX Item "-mabi=mmixware"
-.PD 0
-.IP "\fB\-mabi=gnu\fR" 4
-.IX Item "-mabi=gnu"
-.PD
-Generate code that passes function parameters and return values that (in
-the called function) are seen as registers \f(CW$0\fR and up, as opposed to
-the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up.
-.IP "\fB\-mzero\-extend\fR" 4
-.IX Item "-mzero-extend"
-.PD 0
-.IP "\fB\-mno\-zero\-extend\fR" 4
-.IX Item "-mno-zero-extend"
-.PD
-When reading data from memory in sizes shorter than 64 bits, use (do not
-use) zero-extending load instructions by default, rather than
-sign-extending ones.
-.IP "\fB\-mknuthdiv\fR" 4
-.IX Item "-mknuthdiv"
-.PD 0
-.IP "\fB\-mno\-knuthdiv\fR" 4
-.IX Item "-mno-knuthdiv"
-.PD
-Make the result of a division yielding a remainder have the same sign as
-the divisor. With the default, \fB\-mno\-knuthdiv\fR, the sign of the
-remainder follows the sign of the dividend. Both methods are
-arithmetically valid, the latter being almost exclusively used.
-.IP "\fB\-mtoplevel\-symbols\fR" 4
-.IX Item "-mtoplevel-symbols"
-.PD 0
-.IP "\fB\-mno\-toplevel\-symbols\fR" 4
-.IX Item "-mno-toplevel-symbols"
-.PD
-Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly
-code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive.
-.IP "\fB\-melf\fR" 4
-.IX Item "-melf"
-Generate an executable in the \s-1ELF\s0 format, rather than the default
-\&\fBmmo\fR format used by the \fBmmix\fR simulator.
-.IP "\fB\-mbranch\-predict\fR" 4
-.IX Item "-mbranch-predict"
-.PD 0
-.IP "\fB\-mno\-branch\-predict\fR" 4
-.IX Item "-mno-branch-predict"
-.PD
-Use (do not use) the probable-branch instructions, when static branch
-prediction indicates a probable branch.
-.IP "\fB\-mbase\-addresses\fR" 4
-.IX Item "-mbase-addresses"
-.PD 0
-.IP "\fB\-mno\-base\-addresses\fR" 4
-.IX Item "-mno-base-addresses"
-.PD
-Generate (do not generate) code that uses \fIbase addresses\fR. Using a
-base address automatically generates a request (handled by the assembler
-and the linker) for a constant to be set up in a global register. The
-register is used for one or more base address requests within the range 0
-to 255 from the value held in the register. The generally leads to short
-and fast code, but the number of different data items that can be
-addressed is limited. This means that a program that uses lots of static
-data may require \fB\-mno\-base\-addresses\fR.
-.IP "\fB\-msingle\-exit\fR" 4
-.IX Item "-msingle-exit"
-.PD 0
-.IP "\fB\-mno\-single\-exit\fR" 4
-.IX Item "-mno-single-exit"
-.PD
-Force (do not force) generated code to have a single exit point in each
-function.
+\fIx86\-64 Options\fR
+.IX Subsection "x86-64 Options"
.PP
-\fI\s-1PDP\-11\s0 Options\fR
-.IX Subsection "PDP-11 Options"
-.PP
-These options are defined for the \s-1PDP\-11:\s0
-.IP "\fB\-mfpu\fR" 4
-.IX Item "-mfpu"
-Use hardware \s-1FPP\s0 floating point. This is the default. (\s-1FIS\s0 floating
-point on the \s-1PDP\-11/40\s0 is not supported.)
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-Do not use hardware floating point.
-.IP "\fB\-mac0\fR" 4
-.IX Item "-mac0"
-Return floating-point results in ac0 (fr0 in Unix assembler syntax).
-.IP "\fB\-mno\-ac0\fR" 4
-.IX Item "-mno-ac0"
-Return floating-point results in memory. This is the default.
-.IP "\fB\-m40\fR" 4
-.IX Item "-m40"
-Generate code for a \s-1PDP\-11/40\s0.
-.IP "\fB\-m45\fR" 4
-.IX Item "-m45"
-Generate code for a \s-1PDP\-11/45\s0. This is the default.
-.IP "\fB\-m10\fR" 4
-.IX Item "-m10"
-Generate code for a \s-1PDP\-11/10\s0.
-.IP "\fB\-mbcopy\-builtin\fR" 4
-.IX Item "-mbcopy-builtin"
-Use inline \f(CW\*(C`movstrhi\*(C'\fR patterns for copying memory. This is the
-default.
-.IP "\fB\-mbcopy\fR" 4
-.IX Item "-mbcopy"
-Do not use inline \f(CW\*(C`movstrhi\*(C'\fR patterns for copying memory.
-.IP "\fB\-mint16\fR" 4
-.IX Item "-mint16"
-.PD 0
-.IP "\fB\-mno\-int32\fR" 4
-.IX Item "-mno-int32"
-.PD
-Use 16\-bit \f(CW\*(C`int\*(C'\fR. This is the default.
-.IP "\fB\-mint32\fR" 4
-.IX Item "-mint32"
-.PD 0
-.IP "\fB\-mno\-int16\fR" 4
-.IX Item "-mno-int16"
-.PD
-Use 32\-bit \f(CW\*(C`int\*(C'\fR.
-.IP "\fB\-mfloat64\fR" 4
-.IX Item "-mfloat64"
-.PD 0
-.IP "\fB\-mno\-float32\fR" 4
-.IX Item "-mno-float32"
-.PD
-Use 64\-bit \f(CW\*(C`float\*(C'\fR. This is the default.
-.IP "\fB\-mfloat32\fR" 4
-.IX Item "-mfloat32"
-.PD 0
-.IP "\fB\-mno\-float64\fR" 4
-.IX Item "-mno-float64"
-.PD
-Use 32\-bit \f(CW\*(C`float\*(C'\fR.
-.IP "\fB\-mabshi\fR" 4
-.IX Item "-mabshi"
-Use \f(CW\*(C`abshi2\*(C'\fR pattern. This is the default.
-.IP "\fB\-mno\-abshi\fR" 4
-.IX Item "-mno-abshi"
-Do not use \f(CW\*(C`abshi2\*(C'\fR pattern.
-.IP "\fB\-mbranch\-expensive\fR" 4
-.IX Item "-mbranch-expensive"
-Pretend that branches are expensive. This is for experimenting with
-code generation only.
-.IP "\fB\-mbranch\-cheap\fR" 4
-.IX Item "-mbranch-cheap"
-Do not pretend that branches are expensive. This is the default.
-.IP "\fB\-msplit\fR" 4
-.IX Item "-msplit"
-Generate code for a system with split I&D.
-.IP "\fB\-mno\-split\fR" 4
-.IX Item "-mno-split"
-Generate code for a system without split I&D. This is the default.
-.IP "\fB\-munix\-asm\fR" 4
-.IX Item "-munix-asm"
-Use Unix assembler syntax. This is the default when configured for
-\&\fBpdp11\-*\-bsd\fR.
-.IP "\fB\-mdec\-asm\fR" 4
-.IX Item "-mdec-asm"
-Use \s-1DEC\s0 assembler syntax. This is the default when configured for any
-\&\s-1PDP\-11\s0 target other than \fBpdp11\-*\-bsd\fR.
+These are listed under
.PP
\fIXstormy16 Options\fR
.IX Subsection "Xstormy16 Options"
@@ -9928,157 +12377,6 @@ These options are defined for Xstormy16:
.IX Item "-msim"
Choose startup files and linker script suitable for the simulator.
.PP
-\fI\s-1FRV\s0 Options\fR
-.IX Subsection "FRV Options"
-.IP "\fB\-mgpr\-32\fR" 4
-.IX Item "-mgpr-32"
-Only use the first 32 general purpose registers.
-.IP "\fB\-mgpr\-64\fR" 4
-.IX Item "-mgpr-64"
-Use all 64 general purpose registers.
-.IP "\fB\-mfpr\-32\fR" 4
-.IX Item "-mfpr-32"
-Use only the first 32 floating point registers.
-.IP "\fB\-mfpr\-64\fR" 4
-.IX Item "-mfpr-64"
-Use all 64 floating point registers
-.IP "\fB\-mhard\-float\fR" 4
-.IX Item "-mhard-float"
-Use hardware instructions for floating point operations.
-.IP "\fB\-msoft\-float\fR" 4
-.IX Item "-msoft-float"
-Use library routines for floating point operations.
-.IP "\fB\-malloc\-cc\fR" 4
-.IX Item "-malloc-cc"
-Dynamically allocate condition code registers.
-.IP "\fB\-mfixed\-cc\fR" 4
-.IX Item "-mfixed-cc"
-Do not try to dynamically allocate condition code registers, only
-use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR.
-.IP "\fB\-mdword\fR" 4
-.IX Item "-mdword"
-Change \s-1ABI\s0 to use double word insns.
-.IP "\fB\-mno\-dword\fR" 4
-.IX Item "-mno-dword"
-Do not use double word instructions.
-.IP "\fB\-mdouble\fR" 4
-.IX Item "-mdouble"
-Use floating point double instructions.
-.IP "\fB\-mno\-double\fR" 4
-.IX Item "-mno-double"
-Do not use floating point double instructions.
-.IP "\fB\-mmedia\fR" 4
-.IX Item "-mmedia"
-Use media instructions.
-.IP "\fB\-mno\-media\fR" 4
-.IX Item "-mno-media"
-Do not use media instructions.
-.IP "\fB\-mmuladd\fR" 4
-.IX Item "-mmuladd"
-Use multiply and add/subtract instructions.
-.IP "\fB\-mno\-muladd\fR" 4
-.IX Item "-mno-muladd"
-Do not use multiply and add/subtract instructions.
-.IP "\fB\-mlibrary\-pic\fR" 4
-.IX Item "-mlibrary-pic"
-Enable \s-1PIC\s0 support for building libraries
-.IP "\fB\-macc\-4\fR" 4
-.IX Item "-macc-4"
-Use only the first four media accumulator registers.
-.IP "\fB\-macc\-8\fR" 4
-.IX Item "-macc-8"
-Use all eight media accumulator registers.
-.IP "\fB\-mpack\fR" 4
-.IX Item "-mpack"
-Pack \s-1VLIW\s0 instructions.
-.IP "\fB\-mno\-pack\fR" 4
-.IX Item "-mno-pack"
-Do not pack \s-1VLIW\s0 instructions.
-.IP "\fB\-mno\-eflags\fR" 4
-.IX Item "-mno-eflags"
-Do not mark \s-1ABI\s0 switches in e_flags.
-.IP "\fB\-mcond\-move\fR" 4
-.IX Item "-mcond-move"
-Enable the use of conditional-move instructions (default).
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mno\-cond\-move\fR" 4
-.IX Item "-mno-cond-move"
-Disable the use of conditional-move instructions.
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mscc\fR" 4
-.IX Item "-mscc"
-Enable the use of conditional set instructions (default).
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mno\-scc\fR" 4
-.IX Item "-mno-scc"
-Disable the use of conditional set instructions.
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mcond\-exec\fR" 4
-.IX Item "-mcond-exec"
-Enable the use of conditional execution (default).
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mno\-cond\-exec\fR" 4
-.IX Item "-mno-cond-exec"
-Disable the use of conditional execution.
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mvliw\-branch\fR" 4
-.IX Item "-mvliw-branch"
-Run a pass to pack branches into \s-1VLIW\s0 instructions (default).
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mno\-vliw\-branch\fR" 4
-.IX Item "-mno-vliw-branch"
-Do not run a pass to pack branches into \s-1VLIW\s0 instructions.
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mmulti\-cond\-exec\fR" 4
-.IX Item "-mmulti-cond-exec"
-Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution
-(default).
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mno\-multi\-cond\-exec\fR" 4
-.IX Item "-mno-multi-cond-exec"
-Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution.
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mnested\-cond\-exec\fR" 4
-.IX Item "-mnested-cond-exec"
-Enable nested conditional execution optimizations (default).
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mno\-nested\-cond\-exec\fR" 4
-.IX Item "-mno-nested-cond-exec"
-Disable nested conditional execution optimizations.
-.Sp
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-.IP "\fB\-mtomcat\-stats\fR" 4
-.IX Item "-mtomcat-stats"
-Cause gas to print out tomcat statistics.
-.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
-.IX Item "-mcpu=cpu"
-Select the processor type for which to generate code. Possible values are
-\&\fBsimple\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr400\fR, \fBfr300\fR,
-\&\fBfrv\fR.
-.PP
\fIXtensa Options\fR
.IX Subsection "Xtensa Options"
.PP
@@ -10163,6 +12461,11 @@ assembly code generated by \s-1GCC\s0 will still show direct call
instructions\-\-\-look at the disassembled object code to see the actual
instructions. Note that the assembler will use an indirect call for
every cross-file call, not just those that really will be out of range.
+.PP
+\fIzSeries Options\fR
+.IX Subsection "zSeries Options"
+.PP
+These are listed under
.Sh "Options for Code Generation Conventions"
.IX Subsection "Options for Code Generation Conventions"
These machine-independent options control the interface conventions
@@ -10177,7 +12480,7 @@ it.
.IX Item "-fbounds-check"
For front-ends that support it, generate additional code to check that
indices used to access arrays are within the declared range. This is
-currently only supported by the Java and Fortran 77 front\-ends, where
+currently only supported by the Java and Fortran front\-ends, where
this option defaults to true and false respectively.
.IP "\fB\-ftrapv\fR" 4
.IX Item "-ftrapv"
@@ -10188,7 +12491,7 @@ multiplication operations.
This option instructs the compiler to assume that signed arithmetic
overflow of addition, subtraction and multiplication wraps around
using twos-complement representation. This flag enables some optimizations
-and disables other. This option is enabled by default for the Java
+and disables others. This option is enabled by default for the Java
front\-end, as required by the Java language specification.
.IP "\fB\-fexceptions\fR" 4
.IX Item "-fexceptions"
@@ -10224,7 +12527,7 @@ table is exact at each instruction boundary, so it can be used for stack
unwinding from asynchronous events (such as debugger or garbage collector).
.IP "\fB\-fpcc\-struct\-return\fR" 4
.IX Item "-fpcc-struct-return"
-Return ``short'' \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in memory like
+Return \*(L"short\*(R" \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in memory like
longer ones, rather than in registers. This convention is less
efficient, but it has the advantage of allowing intercallability between
GCC-compiled files and files compiled with other compilers, particularly
@@ -10282,13 +12585,6 @@ useful for building programs to run under \s-1WINE\s0.
\&\fBWarning:\fR the \fB\-fshort\-wchar\fR switch causes \s-1GCC\s0 to generate
code that is not binary compatible with code generated without that switch.
Use it to conform to a non-default application binary interface.
-.IP "\fB\-fshared\-data\fR" 4
-.IX Item "-fshared-data"
-Requests that the data and non\-\f(CW\*(C`const\*(C'\fR variables of this
-compilation be shared data rather than private data. The distinction
-makes sense only on certain operating systems, where shared data is
-shared between processes running the same program, while private data
-exists in one copy per process.
.IP "\fB\-fno\-common\fR" 4
.IX Item "-fno-common"
In C, allocate even uninitialized global variables in the data section of the
@@ -10334,15 +12630,21 @@ Position-independent code requires special support, and therefore works
only on certain machines. For the 386, \s-1GCC\s0 supports \s-1PIC\s0 for System V
but not for the Sun 386i. Code generated for the \s-1IBM\s0 \s-1RS/6000\s0 is always
position\-independent.
+.Sp
+When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR
+are defined to 1.
.IP "\fB\-fPIC\fR" 4
.IX Item "-fPIC"
If supported for the target machine, emit position-independent code,
suitable for dynamic linking and avoiding any limit on the size of the
-global offset table. This option makes a difference on the m68k
-and the \s-1SPARC\s0.
+global offset table. This option makes a difference on the m68k,
+PowerPC and \s-1SPARC\s0.
.Sp
Position-independent code requires special support, and therefore works
only on certain machines.
+.Sp
+When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR
+are defined to 2.
.IP "\fB\-fpie\fR" 4
.IX Item "-fpie"
.PD 0
@@ -10353,6 +12655,14 @@ These options are similar to \fB\-fpic\fR and \fB\-fPIC\fR, but
generated position independent code can be only linked into executables.
Usually these options are used when \fB\-pie\fR \s-1GCC\s0 option will be
used during linking.
+.IP "\fB\-fno\-jump\-tables\fR" 4
+.IX Item "-fno-jump-tables"
+Do not use jump tables for switch statements even where it would be
+more efficient than other code generation strategies. This option is
+of use in conjunction with \fB\-fpic\fR or \fB\-fPIC\fR for
+building code which forms part of a dynamic linker and cannot
+reference the address of a jump table. On some targets, jump tables
+do not require a \s-1GOT\s0 and this option is not needed.
.IP "\fB\-ffixed\-\fR\fIreg\fR" 4
.IX Item "-ffixed-reg"
Treat the register named \fIreg\fR as a fixed register; generated code
@@ -10394,9 +12704,13 @@ a register in which function values may be returned.
.Sp
This flag does not have a negative form, because it specifies a
three-way choice.
-.IP "\fB\-fpack\-struct\fR" 4
-.IX Item "-fpack-struct"
-Pack all structure members together without holes.
+.IP "\fB\-fpack\-struct[=\fR\fIn\fR\fB]\fR" 4
+.IX Item "-fpack-struct[=n]"
+Without a value specified, pack all structure members together without
+holes. When a value is specified (which must be a small power of two), pack
+structure members according to this value, representing the maximum
+alignment (that is, objects with default alignment requirements larger than
+this will be output potentially unaligned at the next fitting location.
.Sp
\&\fBWarning:\fR the \fB\-fpack\-struct\fR switch causes \s-1GCC\s0 to generate
code that is not binary compatible with code generated without that switch.
@@ -10422,8 +12736,16 @@ profiling functions otherwise.)
The first argument is the address of the start of the current function,
which may be looked up exactly in the symbol table.
.Sp
-This currently disables function inlining. This restriction is
-expected to be removed in future releases.
+This instrumentation is also done for functions expanded inline in other
+functions. The profiling calls will indicate where, conceptually, the
+inline function is entered and exited. This means that addressable
+versions of such functions must be available. If all your uses of a
+function are expanded inline, this may mean an additional expansion of
+code size. If you use \fBextern inline\fR in your C code, an
+addressable version of such functions must be provided. (This is
+normally the case anyways, but if you get lucky and the optimizer always
+expands the functions inline, you might have gotten away without
+providing static copies.)
.Sp
A function may be given the attribute \f(CW\*(C`no_instrument_function\*(C'\fR, in
which case this instrumentation will not be done. This can be used, for
@@ -10468,6 +12790,8 @@ of 128KB. Note that this may only work with the \s-1GNU\s0 linker.
.IX Item "-fargument-noalias"
.IP "\fB\-fargument\-noalias\-global\fR" 4
.IX Item "-fargument-noalias-global"
+.IP "\fB\-fargument\-noalias\-anything\fR" 4
+.IX Item "-fargument-noalias-anything"
.PD
Specify the possible relationships among parameters and between
parameters and global data.
@@ -10476,6 +12800,8 @@ parameters and global data.
alias each other and may alias global storage.\fB\-fargument\-noalias\fR specifies that arguments do not alias
each other, but may alias global storage.\fB\-fargument\-noalias\-global\fR specifies that arguments do not
alias each other and do not alias global storage.
+\&\fB\-fargument\-noalias\-anything\fR specifies that arguments do not
+alias any other storage.
.Sp
Each language will automatically use whatever option is required by
the language standard. You should not need to use these options yourself.
@@ -10497,6 +12823,73 @@ The \fImodel\fR argument should be one of \f(CW\*(C`global\-dynamic\*(C'\fR,
.Sp
The default without \fB\-fpic\fR is \f(CW\*(C`initial\-exec\*(C'\fR; with
\&\fB\-fpic\fR the default is \f(CW\*(C`global\-dynamic\*(C'\fR.
+.IP "\fB\-fvisibility=\fR\fIdefault|internal|hidden|protected\fR" 4
+.IX Item "-fvisibility=default|internal|hidden|protected"
+Set the default \s-1ELF\s0 image symbol visibility to the specified option\-\-\-all
+symbols will be marked with this unless overridden within the code.
+Using this feature can very substantially improve linking and
+load times of shared object libraries, produce more optimized
+code, provide near-perfect \s-1API\s0 export and prevent symbol clashes.
+It is \fBstrongly\fR recommended that you use this in any shared objects
+you distribute.
+.Sp
+Despite the nomenclature, \f(CW\*(C`default\*(C'\fR always means public ie;
+available to be linked against from outside the shared object.
+\&\f(CW\*(C`protected\*(C'\fR and \f(CW\*(C`internal\*(C'\fR are pretty useless in real-world
+usage so the only other commonly used option will be \f(CW\*(C`hidden\*(C'\fR.
+The default if \fB\-fvisibility\fR isn't specified is
+\&\f(CW\*(C`default\*(C'\fR, i.e., make every
+symbol public\-\-\-this causes the same behavior as previous versions of
+\&\s-1GCC\s0.
+.Sp
+A good explanation of the benefits offered by ensuring \s-1ELF\s0
+symbols have the correct visibility is given by \*(L"How To Write
+Shared Libraries\*(R" by Ulrich Drepper (which can be found at
+<\fBhttp://people.redhat.com/~drepper/\fR>)\-\-\-however a superior
+solution made possible by this option to marking things hidden when
+the default is public is to make the default hidden and mark things
+public. This is the norm with \s-1DLL\s0's on Windows and with \fB\-fvisibility=hidden\fR
+and \f(CW\*(C`_\|_attribute_\|_ ((visibility("default")))\*(C'\fR instead of
+\&\f(CW\*(C`_\|_declspec(dllexport)\*(C'\fR you get almost identical semantics with
+identical syntax. This is a great boon to those working with
+cross-platform projects.
+.Sp
+For those adding visibility support to existing code, you may find
+\&\fB#pragma \s-1GCC\s0 visibility\fR of use. This works by you enclosing
+the declarations you wish to set visibility for with (for example)
+\&\fB#pragma \s-1GCC\s0 visibility push(hidden)\fR and
+\&\fB#pragma \s-1GCC\s0 visibility pop\fR.
+Bear in mind that symbol visibility should be viewed \fBas
+part of the \s-1API\s0 interface contract\fR and thus all new code should
+always specify visibility when it is not the default ie; declarations
+only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly
+as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this
+abundantly clear also aids readability and self-documentation of the code.
+Note that due to \s-1ISO\s0 \*(C+ specification requirements, operator new and
+operator delete must always be of default visibility.
+.Sp
+Be aware that headers from outside your project, in particular system
+headers and headers from any other library you use, may not be
+expecting to be compiled with visibility other than the default. You
+may need to explicitly say \fB#pragma \s-1GCC\s0 visibility push(default)\fR
+before including any such headers.
+.Sp
+\&\fBextern\fR declarations are not affected by \fB\-fvisibility\fR, so
+a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with
+no modifications. However, this means that calls to \fBextern\fR
+functions with no explicit visibility will use the \s-1PLT\s0, so it is more
+effective to use \fB_\|_attribute ((visibility))\fR and/or
+\&\fB#pragma \s-1GCC\s0 visibility\fR to tell the compiler which \fBextern\fR
+declarations should be treated as hidden.
+.Sp
+Note that \fB\-fvisibility\fR does affect \*(C+ vague linkage
+entities. This means that, for instance, an exception class that will
+be thrown between DSOs must be explicitly marked with default
+visibility so that the \fBtype_info\fR nodes will be unified between
+the DSOs.
+.Sp
+An overview of these techniques, their benefits and how to use them
+is at <\fBhttp://gcc.gnu.org/wiki/Visibility\fR>.
.SH "ENVIRONMENT"
.IX Header "ENVIRONMENT"
This section describes several environment variables that affect how \s-1GCC\s0
@@ -10676,8 +13069,7 @@ main input file is omitted.
.SH "BUGS"
.IX Header "BUGS"
For instructions on reporting bugs, see
-<\fBhttp://gcc.gnu.org/bugs.html\fR>. Use of the \fBgccbug\fR
-script to report bugs is recommended.
+<\fBhttp://gcc.gnu.org/bugs.html\fR>.
.SH "FOOTNOTES"
.IX Header "FOOTNOTES"
.IP "1." 4
@@ -10690,8 +13082,8 @@ is innocuous.
.SH "SEE ALSO"
.IX Header "SEE ALSO"
\&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7),
-\&\fIcpp\fR\|(1), \fIgcov\fR\|(1), \fIg77\fR\|(1), \fIas\fR\|(1), \fIld\fR\|(1), \fIgdb\fR\|(1), \fIadb\fR\|(1), \fIdbx\fR\|(1), \fIsdb\fR\|(1)
-and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIg77\fR, \fIas\fR,
+\&\fIcpp\fR\|(1), \fIgcov\fR\|(1), \fIas\fR\|(1), \fIld\fR\|(1), \fIgdb\fR\|(1), \fIadb\fR\|(1), \fIdbx\fR\|(1), \fIsdb\fR\|(1)
+and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR,
\&\fIld\fR, \fIbinutils\fR and \fIgdb\fR.
.SH "AUTHOR"
.IX Header "AUTHOR"
@@ -10700,14 +13092,14 @@ See the Info entry for \fBgcc\fR, or
for contributors to \s-1GCC\s0.
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
-Copyright (c) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
-1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+Copyright (c) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
+1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.2 or
any later version published by the Free Software Foundation; with the
-Invariant Sections being ``\s-1GNU\s0 General Public License'' and ``Funding
-Free Software'', the Front-Cover texts being (a) (see below), and with
+Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding
+Free Software\*(R", the Front-Cover texts being (a) (see below), and with
the Back-Cover Texts being (b) (see below). A copy of the license is
included in the \fIgfdl\fR\|(7) man page.
.PP
diff --git a/contrib/gcc/doc/gcov.1 b/contrib/gcc/doc/gcov.1
index d0abb46aeb88..ac3b0c4765a5 100644
--- a/contrib/gcc/doc/gcov.1
+++ b/contrib/gcc/doc/gcov.1
@@ -129,7 +129,7 @@
.\" ========================================================================
.\"
.IX Title "GCOV 1"
-.TH GCOV 1 "2006-03-06" "gcc-3.4.6" "GNU"
+.TH GCOV 1 "2007-07-19" "gcc-4.2.1" "GNU"
.SH "NAME"
gcov \- coverage testing tool
.SH "SYNOPSIS"
@@ -222,8 +222,8 @@ and exit without doing any further processing.
.IP "\fB\-\-all\-blocks\fR" 4
.IX Item "--all-blocks"
.PD
-Write individual execution counts for every basic block. Normally gcov
-outputs execution counts only for the main blocks of a line. With this
+Write individual execution counts for every basic block. Normally gcov
+outputs execution counts only for the main blocks of a line. With this
option you can determine if blocks within a single line are not being
executed.
.IP "\fB\-b\fR" 4
@@ -234,7 +234,7 @@ executed.
.PD
Write branch frequencies to the output file, and write branch summary
info to the standard output. This option allows you to see how often
-each branch in your program was taken. Unconditional branches will not
+each branch in your program was taken. Unconditional branches will not
be shown, unless the \fB\-u\fR option is given.
.IP "\fB\-c\fR" 4
.IX Item "-c"
@@ -262,7 +262,7 @@ header file \fIx.h\fR contains code, and was included in the file
\&\fIa.c\fR, then running \fBgcov\fR on the file \fIa.c\fR will produce
an output file called \fIa.c##x.h.gcov\fR instead of \fIx.h.gcov\fR.
This can be useful if \fIx.h\fR is included in multiple source
-files. If you uses the \fB\-p\fR option, both the including and
+files. If you use the \fB\-p\fR option, both the including and
included file names will be complete path names.
.IP "\fB\-p\fR" 4
.IX Item "-p"
@@ -271,11 +271,12 @@ included file names will be complete path names.
.IX Item "--preserve-paths"
.PD
Preserve complete path information in the names of generated