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authorWojciech Macek <wma@FreeBSD.org>2016-09-06 14:26:41 +0000
committerWojciech Macek <wma@FreeBSD.org>2016-09-06 14:26:41 +0000
commit25208b899945183857da501a98d924798de07b26 (patch)
tree4cdf79e141852397df4fb66f91838c4a3a86985b
parent3098c7f4883d83f28e887bc376250a6d2806ab20 (diff)
downloadsrc-25208b899945183857da501a98d924798de07b26.tar.gz
src-25208b899945183857da501a98d924798de07b26.zip
Update Annapurna Alpine HAL to a newer version.
HAL version: 2.7a
Notes
Notes: svn path=/vendor-sys/alpine-hal/dist/; revision=305475
-rw-r--r--al_hal_iofic.c18
-rw-r--r--al_hal_iofic.h10
-rw-r--r--al_hal_iofic_regs.h14
-rw-r--r--al_hal_nb_regs.h33
-rw-r--r--al_hal_pbs_regs.h133
-rw-r--r--al_hal_pcie.c606
-rw-r--r--al_hal_pcie.h417
-rw-r--r--al_hal_pcie_axi_reg.h60
-rw-r--r--al_hal_pcie_interrupts.h10
-rw-r--r--al_hal_pcie_regs.h36
-rw-r--r--al_hal_pcie_w_reg.h2
-rw-r--r--al_hal_plat_services.h138
-rw-r--r--al_hal_plat_types.h18
-rw-r--r--al_hal_reg_utils.h1
-rw-r--r--al_hal_serdes.c1868
-rw-r--r--al_hal_serdes.h1125
-rw-r--r--al_hal_serdes_25g.c1951
-rw-r--r--al_hal_serdes_25g.h74
-rw-r--r--al_hal_serdes_25g_internal_regs.h4205
-rw-r--r--al_hal_serdes_25g_regs.h434
-rw-r--r--al_hal_serdes_hssp.h87
-rw-r--r--al_hal_serdes_hssp_internal_regs.h749
-rw-r--r--al_hal_serdes_hssp_regs.h494
-rw-r--r--al_hal_serdes_interface.h875
-rw-r--r--al_hal_udma.h11
-rw-r--r--al_hal_udma_config.c323
-rw-r--r--al_hal_udma_config.h265
-rw-r--r--al_hal_udma_debug.c8
-rw-r--r--al_hal_udma_iofic.h18
-rw-r--r--al_hal_udma_main.c26
-rw-r--r--al_hal_udma_regs_gen.h335
-rw-r--r--al_hal_unit_adapter_regs.h14
-rw-r--r--al_serdes.c59
-rw-r--r--al_serdes.h78
-rw-r--r--eth/al_hal_eth.h82
-rw-r--r--eth/al_hal_eth_mac_regs.h297
-rw-r--r--eth/al_hal_eth_main.c1014
37 files changed, 12337 insertions, 3551 deletions
diff --git a/al_hal_iofic.c b/al_hal_iofic.c
index 28467f2e3b87..b60a45f3002e 100644
--- a/al_hal_iofic.c
+++ b/al_hal_iofic.c
@@ -129,10 +129,10 @@ int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
}
/*
- * configure the vmid attributes for a given msix vector.
+ * configure the target-id attributes for a given msix vector.
*/
-int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
- uint8_t vector, uint32_t vmid, uint8_t vmid_en)
+int al_iofic_msix_tgtid_attributes_config(void __iomem *regs_base, int group,
+ uint8_t vector, uint32_t tgtid, uint8_t tgtid_en)
{
struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
uint32_t reg = 0;
@@ -141,14 +141,14 @@ int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
al_assert(group < AL_IOFIC_MAX_GROUPS);
AL_REG_FIELD_SET(reg,
- INT_MSIX_VMID_MASK,
- INT_MSIX_VMID_SHIFT,
- vmid);
+ INT_MSIX_TGTID_MASK,
+ INT_MSIX_TGTID_SHIFT,
+ tgtid);
AL_REG_BIT_VAL_SET(reg,
- INT_MSIX_VMID_EN_SHIFT,
- vmid_en);
+ INT_MSIX_TGTID_EN_SHIFT,
+ tgtid_en);
- al_reg_write32(&regs->grp_int_mod[group][vector].grp_int_vmid_reg, reg);
+ al_reg_write32(&regs->grp_int_mod[group][vector].grp_int_tgtid_reg, reg);
return 0;
}
diff --git a/al_hal_iofic.h b/al_hal_iofic.h
index 5c19e0a12606..5b4a1dffb0e7 100644
--- a/al_hal_iofic.h
+++ b/al_hal_iofic.h
@@ -117,17 +117,17 @@ int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
uint8_t vector, uint8_t interval);
/**
-* configure the vmid attributes for a given msix vector.
+* configure the tgtid attributes for a given msix vector.
*
* @param group the interrupt group
* @param vector index
-* @param vmid the vmid value
-* @param vmid_en take vmid from the intc
+* @param tgtid the target-id value
+* @param tgtid_en take target-id from the intc
*
* @return 0 on success. -EINVAL otherwise.
*/
-int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
- uint8_t vector, uint32_t vmid, uint8_t vmid_en);
+int al_iofic_msix_tgtid_attributes_config(void __iomem *regs_base, int group,
+ uint8_t vector, uint32_t tgtid, uint8_t tgtid_en);
/**
* return the offset of the unmask register for a given group.
diff --git a/al_hal_iofic_regs.h b/al_hal_iofic_regs.h
index 81ba20fc9676..3f1b5f88660a 100644
--- a/al_hal_iofic_regs.h
+++ b/al_hal_iofic_regs.h
@@ -66,7 +66,7 @@ struct al_iofic_grp_ctrl {
struct al_iofic_grp_mod {
uint32_t grp_int_mod_reg; /* Interrupt moderation registerDedicated moderation in ... */
- uint32_t grp_int_vmid_reg;
+ uint32_t grp_int_tgtid_reg;
};
struct al_iofic_regs {
@@ -109,12 +109,12 @@ struct al_iofic_regs {
#define INT_MOD_INTV_MASK 0x000000FF
#define INT_MOD_INTV_SHIFT 0
-/**** grp_int_vmid_reg register ****/
-/* Interrupt vmid value registerDedicated reg ... */
-#define INT_MSIX_VMID_MASK 0x0000FFFF
-#define INT_MSIX_VMID_SHIFT 0
-/* Interrupt vmid_en value registerDedicated reg ... */
-#define INT_MSIX_VMID_EN_SHIFT 31
+/**** grp_int_tgtid_reg register ****/
+/* Interrupt tgtid value registerDedicated reg ... */
+#define INT_MSIX_TGTID_MASK 0x0000FFFF
+#define INT_MSIX_TGTID_SHIFT 0
+/* Interrupt tgtid_en value registerDedicated reg ... */
+#define INT_MSIX_TGTID_EN_SHIFT 31
#ifdef __cplusplus
}
diff --git a/al_hal_nb_regs.h b/al_hal_nb_regs.h
index 9de3bd246865..29c5060d007b 100644
--- a/al_hal_nb_regs.h
+++ b/al_hal_nb_regs.h
@@ -355,7 +355,7 @@ struct al_nb_nb_version {
};
struct al_nb_sriov {
/* [0x0] */
- uint32_t cpu_vmid[4];
+ uint32_t cpu_tgtid[4];
uint32_t rsrvd[4];
};
struct al_nb_dram_channels {
@@ -403,7 +403,7 @@ struct al_nb_push_packet {
uint32_t pp_config;
uint32_t rsrvd_0[3];
/* [0x10] */
- uint32_t pp_ext_awuser;
+ uint32_t pp_ext_attr;
uint32_t rsrvd_1[3];
/* [0x20] */
uint32_t pp_base_low;
@@ -411,7 +411,7 @@ struct al_nb_push_packet {
uint32_t pp_base_high;
uint32_t rsrvd_2[2];
/* [0x30] */
- uint32_t pp_sel_awuser;
+ uint32_t pp_sel_attr;
uint32_t rsrvd[51];
};
@@ -853,8 +853,8 @@ Enables 4k hazard of post-barrier vs pre-barrier transactions. Otherwise, 64B ha
This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset. */
#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF
#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_SHIFT 0
-#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_MASK_PKR 0x00000FFF
-#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_SHIFT_PKR 0
+#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_MASK_ALPINE_V2 0x00000FFF
+#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_SHIFT_ALPINE_V2 0
/* GIC registers base [31:15].
This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset */
#define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
@@ -1055,9 +1055,9 @@ Other access types are hazard check against the pre-barrier requests. */
/* Disable counter (wait 1000 NB cycles) before applying PoS enable/disable configuration */
#define NB_GLOBAL_ACF_MISC_POS_CONFIG_CNT_DIS (1 << 14)
/* Disable wr spliter A0 bug fixes */
-#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_M0_MODE (1 << 16)
-/* Disable wr spliter PKR bug fixes */
-#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_A0_MODE (1 << 17)
+#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_V1_M0_MODE (1 << 16)
+/* Disable wr spliter ALPINE_V2 bug fixes */
+#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_V1_A0_MODE (1 << 17)
/* Override the address parity calucation for write transactions going to IO-fabric */
#define NB_GLOBAL_ACF_MISC_NB_NIC_AWADDR_PAR_OVRD (1 << 18)
/* Override the data parity calucation for write transactions going to IO-fabric */
@@ -1074,7 +1074,7 @@ Other access types are hazard check against the pre-barrier requests. */
#define NB_GLOBAL_ACF_MISC_CPU_DSB_FLUSH_DIS (1 << 26)
/* Enable DMB flush request to NB to SB PoS when barrier is terminted inside the processor cluster */
#define NB_GLOBAL_ACF_MISC_CPU_DMB_FLUSH_DIS (1 << 27)
-/* Peakrock only: remap CPU address above 40 bits to Slave Error
+/* Alpine V2 only: remap CPU address above 40 bits to Slave Error
INTERNAL */
#define NB_GLOBAL_ACF_MISC_ADDR43_40_REMAP_DIS (1 << 28)
/* Enable CPU WriteUnique to WriteNoSnoop trasform */
@@ -1586,7 +1586,7 @@ enable - 0x1: Enable interrupt on overflow. */
/* Number of monitored events supported by the PMU. */
#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_MASK 0x00FC0000
#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT 18
-#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT_ALPINE 19
+#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT_ALPINE_V1 19
/* Number of counters implemented by PMU. */
#define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_MASK 0x0F000000
#define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_SHIFT 24
@@ -1659,6 +1659,9 @@ Note: This field must be changed for larger counters. */
/* Revision number (Major) */
#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
+#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V1 2
+#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V2 3
+#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V3 4
/* Date of release */
#define NB_NB_VERSION_VERSION_DATE_DAY_MASK 0x001F0000
#define NB_NB_VERSION_VERSION_DATE_DAY_SHIFT 16
@@ -1672,10 +1675,10 @@ Note: This field must be changed for larger counters. */
#define NB_NB_VERSION_VERSION_RESERVED_MASK 0xC0000000
#define NB_NB_VERSION_VERSION_RESERVED_SHIFT 30
-/**** cpu_vmid register ****/
-/* Target VMID */
-#define NB_SRIOV_CPU_VMID_VAL_MASK 0x000000FF
-#define NB_SRIOV_CPU_VMID_VAL_SHIFT 0
+/**** cpu_tgtid register ****/
+/* Target-ID */
+#define NB_SRIOV_CPU_TGTID_VAL_MASK 0x000000FF
+#define NB_SRIOV_CPU_TGTID_VAL_SHIFT 0
/**** DRAM_0_Control register ****/
/* Controller Idle
@@ -1807,7 +1810,7 @@ Parity bits are still generated per transaction */
#define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_SHIFT 0
/**** pp_sel_awuser register ****/
-/* Select whether to use addr[63:48] or PP awmisc as vmid.
+/* Select whether to use addr[63:48] or PP awmisc as tgtid.
Each bit if set to 1 selects the corresponding address bit. Otherwise, selects the corersponding awmis bit. */
#define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_MASK 0x0000FFFF
#define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_SHIFT 0
diff --git a/al_hal_pbs_regs.h b/al_hal_pbs_regs.h
index b1f9c4f44d93..c8100e1ff1ec 100644
--- a/al_hal_pbs_regs.h
+++ b/al_hal_pbs_regs.h
@@ -447,11 +447,12 @@ struct al_pbs_target_id_enforcement {
};
struct al_pbs_regs {
- struct al_pbs_unit unit; /* [0x0] */
-struct al_pbs_low_latency_sram_remap low_latency_sram_remap;
-/* [0x250] */
- uint32_t rsrvd_0[88];
- struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */
+ struct al_pbs_unit unit; /* [0x0] */
+ struct al_pbs_low_latency_sram_remap low_latency_sram_remap; /* [0x250] */
+ uint32_t rsrvd_0[24];
+ uint32_t iofic_base; /* [0x300] */
+ uint32_t rsrvd_1[63];
+ struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */
};
@@ -849,50 +850,50 @@ struct al_pbs_low_latency_sram_remap low_latency_sram_remap;
* 2'b01 - select pcie_b[0]
* 2'b10 - select pcie_a[2]
*/
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_SHIFT 0
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_2_MASK 0x00000003
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_2_SHIFT 0
/*
* 2'b01 - select pcie_b[1]
* 2'b10 - select pcie_a[3]
*/
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_MASK 0x00000030
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_SHIFT 4
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_3_MASK 0x00000030
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_3_SHIFT 4
/*
* 2'b01 - select pcie_b[0]
* 2'b10 - select pcie_a[4]
*/
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_MASK 0x00000300
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_SHIFT 8
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_4_MASK 0x00000300
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_4_SHIFT 8
/*
* 2'b01 - select pcie_b[1]
* 2'b10 - select pcie_a[5]
*/
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_MASK 0x00003000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_SHIFT 12
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_5_MASK 0x00003000
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_5_SHIFT 12
/*
* 2'b01 - select pcie_b[2]
* 2'b10 - select pcie_a[6]
*/
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_MASK 0x00030000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_SHIFT 16
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_6_MASK 0x00030000
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_6_SHIFT 16
/*
* 2'b01 - select pcie_b[3]
* 2'b10 - select pcie_a[7]
*/
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_MASK 0x00300000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_SHIFT 20
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_7_MASK 0x00300000
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_7_SHIFT 20
/*
* 2'b01 - select pcie_d[0]
* 2'b10 - select pcie_c[2]
*/
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_MASK 0x03000000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_SHIFT 24
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_10_MASK 0x03000000
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_10_SHIFT 24
/*
* 2'b01 - select pcie_d[1]
* 2'b10 - select pcie_c[3]
*/
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_MASK 0x30000000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_SHIFT 28
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_11_MASK 0x30000000
+#define PBS_UNIT_SERDES_MUX_PIPE_ALPINE_V2_SELECT_OH_SERDES_11_SHIFT 28
/**** dma_io_master_map register ****/
/*
@@ -978,6 +979,14 @@ struct al_pbs_low_latency_sram_remap low_latency_sram_remap;
#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_MASK 0x3C000000
#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_SHIFT 26
+/**** cfg_axi_conf_3 register ****/
+#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_LOW_MASK 0xFFFF
+#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_LOW_SHIFT 0
+#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_HI_MASK 0xFF0000
+#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_HI_SHIFT 16
+#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_SPI_HI_MASK 0xFF000000
+#define PBS_UNIT_CFG_AXI_CONF_3_TIMEOUT_SPI_HI_SHIFT 24
+
/**** spi_mst_conf_0 register ****/
/*
* Sets the SPI master Configuration. For details see the SPI section in the
@@ -1137,9 +1146,9 @@ struct al_pbs_low_latency_sram_remap low_latency_sram_remap;
#define PBS_UNIT_CHIP_ID_DEV_ID_MASK 0xFFFF0000
#define PBS_UNIT_CHIP_ID_DEV_ID_SHIFT 16
-#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE 0
-#define PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK 1
-#define PBS_UNIT_CHIP_ID_DEV_ID_COYOTE 2
+#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V1 0
+#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V2 1
+#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V3 2
/**** uart0_conf_status register ****/
/*
@@ -1420,56 +1429,56 @@ struct al_pbs_low_latency_sram_remap low_latency_sram_remap;
* 2'b01 - select sata_b[0]
* 2'b10 - select eth_a[0]
*/
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_SHIFT 0
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_8_MASK 0x00000003
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_8_SHIFT 0
/*
* 3'b001 - select sata_b[1]
* 3'b010 - select eth_b[0]
* 3'b100 - select eth_a[1]
*/
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_MASK 0x00000070
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_SHIFT 4
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_9_MASK 0x00000070
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_9_SHIFT 4
/*
* 3'b001 - select sata_b[2]
* 3'b010 - select eth_c[0]
* 3'b100 - select eth_a[2]
*/
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_MASK 0x00000700
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_SHIFT 8
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_10_MASK 0x00000700
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_10_SHIFT 8
/*
* 3'b001 - select sata_b[3]
* 3'b010 - select eth_d[0]
* 3'b100 - select eth_a[3]
*/
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_MASK 0x00007000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_SHIFT 12
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_11_MASK 0x00007000
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_11_SHIFT 12
/*
* 2'b01 - select eth_a[0]
* 2'b10 - select sata_a[0]
*/
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_MASK 0x00030000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_SHIFT 16
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_12_MASK 0x00030000
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_12_SHIFT 16
/*
* 3'b001 - select eth_b[0]
* 3'b010 - select eth_c[1]
* 3'b100 - select sata_a[1]
*/
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_MASK 0x00700000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_SHIFT 20
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_13_MASK 0x00700000
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_13_SHIFT 20
/*
* 3'b001 - select eth_a[0]
* 3'b010 - select eth_c[2]
* 3'b100 - select sata_a[2]
*/
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_MASK 0x07000000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_SHIFT 24
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_14_MASK 0x07000000
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_14_SHIFT 24
/*
* 3'b001 - select eth_d[0]
* 3'b010 - select eth_c[3]
* 3'b100 - select sata_a[3]
*/
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_MASK 0x70000000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_SHIFT 28
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_15_MASK 0x70000000
+#define PBS_UNIT_SERDES_MUX_MULTI_0_ALPINE_V2_SELECT_OH_SERDES_15_SHIFT 28
/**** serdes_mux_multi_1 register ****/
/* SerDes one hot mux control. For details see datasheet. */
@@ -1632,62 +1641,62 @@ struct al_pbs_low_latency_sram_remap low_latency_sram_remap;
* 2'b01 - eth_a[0] from serdes_8
* 2'b10 - eth_a[0] from serdes_14
*/
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_SHIFT 0
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_0_MASK 0x00000003
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_0_SHIFT 0
/*
* 2'b01 - eth_b[0] from serdes_9
* 2'b10 - eth_b[0] from serdes_13
*/
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_MASK 0x00000030
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_SHIFT 4
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_B_0_MASK 0x00000030
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_B_0_SHIFT 4
/*
* 2'b01 - eth_c[0] from serdes_10
* 2'b10 - eth_c[0] from serdes_12
*/
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_MASK 0x00000300
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_SHIFT 8
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_0_MASK 0x00000300
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_0_SHIFT 8
/*
* 2'b01 - eth_d[0] from serdes_11
* 2'b10 - eth_d[0] from serdes_15
*/
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_MASK 0x00003000
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_SHIFT 12
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_D_0_MASK 0x00003000
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_D_0_SHIFT 12
/* which lane's is master clk */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16
/* which lane's is master clk */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20
/* enable xlaui on eth a */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24)
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24)
/* enable xlaui on eth c */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28)
+#define PBS_UNIT_SERDES_MUX_ETH_ALPINE_V2_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28)
/**** serdes_mux_pcie register ****/
/*
* 2'b01 - select pcie_b[0] from serdes 2
* 2'b10 - select pcie_b[0] from serdes 4
*/
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_SHIFT 0
+#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_0_MASK 0x00000003
+#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_0_SHIFT 0
/*
* 2'b01 - select pcie_b[1] from serdes 3
* 2'b10 - select pcie_b[1] from serdes 5
*/
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_MASK 0x00000030
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_SHIFT 4
+#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_1_MASK 0x00000030
+#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_B_1_SHIFT 4
/*
* 2'b01 - select pcie_d[0] from serdes 10
* 2'b10 - select pcie_d[0] from serdes 12
*/
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_MASK 0x00000300
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_SHIFT 8
+#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_0_MASK 0x00000300
+#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_0_SHIFT 8
/*
* 2'b01 - select pcie_d[1] from serdes 11
* 2'b10 - select pcie_d[1] from serdes 13
*/
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_MASK 0x00003000
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_SHIFT 12
+#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_1_MASK 0x00003000
+#define PBS_UNIT_SERDES_MUX_PCIE_ALPINE_V2_SELECT_OH_PCIE_D_1_SHIFT 12
/**** serdes_mux_sata register ****/
/*
diff --git a/al_hal_pcie.c b/al_hal_pcie.c
index 3a221d365732..0ef7bc01d76b 100644
--- a/al_hal_pcie.c
+++ b/al_hal_pcie.c
@@ -96,6 +96,8 @@ __FBSDID("$FreeBSD$");
#define AL_PCIE_PARSE_LANES(v) (((1 << v) - 1) << \
PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT)
+#define AL_PCIE_FLR_DONE_INTERVAL 10
+
/**
* Static functions
*/
@@ -183,10 +185,6 @@ al_pcie_port_link_config(
return -EINVAL;
}
- al_dbg("PCIe %d: link config: max speed gen %d, max lanes %d, reversal %s\n",
- pcie_port->port_id, link_params->max_speed,
- pcie_port->max_lanes, link_params->enable_reversal? "enable" : "disable");
-
al_pcie_port_link_speed_ctrl_set(pcie_port, link_params->max_speed);
/* Change Max Payload Size, if needed.
@@ -220,12 +218,6 @@ al_pcie_port_link_config(
(max_lanes + (max_lanes-1))
<< PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT);
- /* TODO: add support for reversal mode */
- if (link_params->enable_reversal) {
- al_err("PCIe %d: enabling reversal mode not implemented\n",
- pcie_port->port_id);
- return -ENOSYS;
- }
return 0;
}
@@ -364,12 +356,9 @@ al_pcie_rev_id_get(
PBS_UNIT_CHIP_ID_DEV_ID_MASK,
PBS_UNIT_CHIP_ID_DEV_ID_SHIFT);
- if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_ALPINE) {
- rev_id = AL_REG_FIELD_GET(
- chip_id,
- PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK,
- PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT);
- } else if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK) {
+ if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V1) {
+ rev_id = AL_PCIE_REV_ID_1;
+ } else if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_ALPINE_V2) {
struct al_pcie_revx_regs __iomem *regs =
(struct al_pcie_revx_regs __iomem *)pcie_reg_base;
uint32_t dev_id;
@@ -469,20 +458,6 @@ al_pcie_ib_hcrd_os_ob_reads_config_default(
al_pcie_port_ib_hcrd_os_ob_reads_config(pcie_port, &ib_hcrd_os_ob_reads_config);
};
-/** return AL_TRUE is link started (LTSSM enabled) and AL_FALSE otherwise */
-static al_bool
-al_pcie_is_link_started(struct al_pcie_port *pcie_port)
-{
- struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;
-
- uint32_t port_init = al_reg_read32(regs->app.global_ctrl.port_init);
- uint8_t ltssm_en = AL_REG_FIELD_GET(port_init,
- PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK,
- PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT);
-
- return ltssm_en;
-}
-
/** return AL_TRUE if link is up, AL_FALSE otherwise */
static al_bool
al_pcie_check_link(
@@ -651,18 +626,6 @@ al_pcie_port_gen3_params_config(struct al_pcie_port *pcie_port,
}
static int
-al_pcie_port_tl_credits_config(
- struct al_pcie_port *pcie_port,
- const struct al_pcie_tl_credits_params *tl_credits __attribute__((__unused__)))
-{
- al_err("PCIe %d: transport layer credits config not implemented\n",
- pcie_port->port_id);
-
- return -ENOSYS;
-
-}
-
-static int
al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
const struct al_pcie_pf_config_params *pf_params)
{
@@ -680,22 +643,21 @@ al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
regs->core_space[pf_num].pcie_pm_cap_base,
AL_FIELD_MASK(26, 25) | AL_FIELD_MASK(31, 28), 0);
- /* Disable FLR capability */
+ /* Set/Clear FLR bit */
if (pf_params->cap_flr_dis)
al_reg_write32_masked(
regs->core_space[pf_num].pcie_dev_cap_base,
- AL_BIT(28), 0);
+ AL_PCI_EXP_DEVCAP_FLR, 0);
+ else
+ al_reg_write32_masked(
+ regs->core_space[pcie_pf->pf_num].pcie_dev_cap_base,
+ AL_PCI_EXP_DEVCAP_FLR, AL_PCI_EXP_DEVCAP_FLR);
/* Disable ASPM capability */
if (pf_params->cap_aspm_dis) {
al_reg_write32_masked(
regs->core_space[pf_num].pcie_cap_base + (AL_PCI_EXP_LNKCAP >> 2),
AL_PCI_EXP_LNKCAP_ASPMS, 0);
- } else if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
- al_warn("%s: ASPM support is enabled, please disable it\n",
- __func__);
- ret = -EINVAL;
- goto done;
}
if (!pf_params->bar_params_valid) {
@@ -743,8 +705,9 @@ al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
if (params->memory_space) {
if (size < AL_PCIE_MIN_MEMORY_BAR_SIZE) {
- al_err("PCIe %d: memory BAR %d: size (0x%llx) less that minimal allowed value\n",
- pcie_port->port_id, bar_idx, size);
+ al_err("PCIe %d: memory BAR %d: size (0x%jx) less that minimal allowed value\n",
+ pcie_port->port_id, bar_idx,
+ (uintmax_t)size);
ret = -EINVAL;
goto done;
}
@@ -756,8 +719,9 @@ al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
}
if (size < AL_PCIE_MIN_IO_BAR_SIZE) {
- al_err("PCIe %d: IO BAR %d: size (0x%llx) less that minimal allowed value\n",
- pcie_port->port_id, bar_idx, size);
+ al_err("PCIe %d: IO BAR %d: size (0x%jx) less that minimal allowed value\n",
+ pcie_port->port_id, bar_idx,
+ (uintmax_t)size);
ret = -EINVAL;
goto done;
}
@@ -765,9 +729,9 @@ al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
/* size must be power of 2 */
if (size & (size - 1)) {
- al_err("PCIe %d: BAR %d:size (0x%llx) must be "
+ al_err("PCIe %d: BAR %d:size (0x%jx) must be "
"power of 2\n",
- pcie_port->port_id, bar_idx, size);
+ pcie_port->port_id, bar_idx, (uintmax_t)size);
ret = -EINVAL;
goto done;
}
@@ -826,8 +790,7 @@ al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
}
/* Open CPU generated msi and legacy interrupts in pcie wrapper logic */
- if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) ||
- (pcie_port->rev_id == AL_PCIE_REV_ID_1)) {
+ if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {
al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_0, (1 << 21));
} else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) ||
(pcie_port->rev_id == AL_PCIE_REV_ID_3)) {
@@ -853,13 +816,7 @@ al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
* Restore the original value after the write to app.soc.mask_msi_leg_0
* register.
*/
- if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
- uint32_t backup;
-
- backup = al_reg_read32(&regs->app.int_grp_a->mask);
- al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));
- al_reg_write32(&regs->app.int_grp_a->mask, backup);
- } else if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {
+ if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {
al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));
} else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) ||
(pcie_port->rev_id == AL_PCIE_REV_ID_3)) {
@@ -878,22 +835,6 @@ done:
return ret;
}
-static void
-al_pcie_port_features_config(
- struct al_pcie_port *pcie_port,
- const struct al_pcie_features *features)
-{
- struct al_pcie_regs *regs = pcie_port->regs;
-
- al_assert(pcie_port->rev_id > AL_PCIE_REV_ID_0);
-
- al_reg_write32_masked(
- &regs->app.ctrl_gen->features,
- PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX,
- features->sata_ep_msi_fix ?
- PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX : 0);
-}
-
static int
al_pcie_port_sris_config(
struct al_pcie_port *pcie_port,
@@ -916,6 +857,9 @@ al_pcie_port_sris_config(
switch (pcie_port->rev_id) {
case AL_PCIE_REV_ID_3:
+ al_reg_write32_masked(&regs->app.cfg_func_ext->cfg,
+ PCIE_W_CFG_FUNC_EXT_CFG_APP_SRIS_MODE,
+ PCIE_W_CFG_FUNC_EXT_CFG_APP_SRIS_MODE);
case AL_PCIE_REV_ID_2:
al_reg_write32_masked(regs->app.global_ctrl.sris_kp_counter,
PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_MASK |
@@ -989,6 +933,34 @@ al_pcie_port_max_num_of_pfs_get(struct al_pcie_port *pcie_port)
return 1;
}
+/** Enable ecrc generation in outbound atu (Addressing RMN: 5119) */
+static void al_pcie_ecrc_gen_ob_atu_enable(struct al_pcie_port *pcie_port, unsigned int pf_num)
+{
+ struct al_pcie_regs *regs = pcie_port->regs;
+ int max_ob_atu = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
+ AL_PCIE_REV_3_ATU_NUM_OUTBOUND_REGIONS : AL_PCIE_REV_1_2_ATU_NUM_OUTBOUND_REGIONS;
+ int i;
+ for (i = 0; i < max_ob_atu; i++) {
+ al_bool enable = 0;
+ uint32_t reg = 0;
+ unsigned int func_num;
+ AL_REG_FIELD_SET(reg, 0xF, 0, i);
+ AL_REG_BIT_VAL_SET(reg, 31, AL_PCIE_ATU_DIR_OUTBOUND);
+ al_reg_write32(&regs->port_regs->iatu.index, reg);
+ reg = al_reg_read32(&regs->port_regs->iatu.cr2);
+ enable = AL_REG_BIT_GET(reg, 31) ? AL_TRUE : AL_FALSE;
+ reg = al_reg_read32(&regs->port_regs->iatu.cr1);
+ func_num = AL_REG_FIELD_GET(reg,
+ PCIE_IATU_CR1_FUNC_NUM_MASK,
+ PCIE_IATU_CR1_FUNC_NUM_SHIFT);
+ if ((enable == AL_TRUE) && (pf_num == func_num)) {
+ /* Set TD bit */
+ AL_REG_BIT_SET(reg, 8);
+ al_reg_write32(&regs->port_regs->iatu.cr1, reg);
+ }
+ }
+}
+
/******************************************************************************/
/***************************** API Implementation *****************************/
/******************************************************************************/
@@ -1025,12 +997,13 @@ al_pcie_port_handle_init(
/* Zero all regs */
al_memset(pcie_port->regs, 0, sizeof(struct al_pcie_regs));
- if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) ||
- (pcie_port->rev_id == AL_PCIE_REV_ID_1)) {
+ if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {
struct al_pcie_rev1_regs __iomem *regs =
(struct al_pcie_rev1_regs __iomem *)pcie_reg_base;
pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
+ pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;
+ pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;
pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
@@ -1059,20 +1032,21 @@ al_pcie_port_handle_init(
pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;
pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;
pcie_port->regs->app.debug = &regs->app.debug;
+ pcie_port->regs->app.soc_int[0].status_0 = &regs->app.soc_int.status_0;
+ pcie_port->regs->app.soc_int[0].status_1 = &regs->app.soc_int.status_1;
+ pcie_port->regs->app.soc_int[0].status_2 = &regs->app.soc_int.status_2;
pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;
+ pcie_port->regs->app.soc_int[0].mask_inta_leg_1 = &regs->app.soc_int.mask_inta_leg_1;
+ pcie_port->regs->app.soc_int[0].mask_inta_leg_2 = &regs->app.soc_int.mask_inta_leg_2;
pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;
+ pcie_port->regs->app.soc_int[0].mask_msi_leg_1 = &regs->app.soc_int.mask_msi_leg_1;
+ pcie_port->regs->app.soc_int[0].mask_msi_leg_2 = &regs->app.soc_int.mask_msi_leg_2;
pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;
pcie_port->regs->app.parity = &regs->app.parity;
pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
-
- if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
- pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a_m0;
- pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b_m0;
- } else {
- pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;
- pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;
- }
+ pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;
+ pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;
pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;
pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;
@@ -1091,6 +1065,8 @@ al_pcie_port_handle_init(
(struct al_pcie_rev2_regs __iomem *)pcie_reg_base;
pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
+ pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;
+ pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;
pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
@@ -1100,6 +1076,10 @@ al_pcie_port_handle_init(
pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;
pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;
pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;
+ pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = &regs->axi.ob_ctrl.tgtid_reg_ovrd;
+ pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = &regs->axi.ob_ctrl.addr_high_reg_ovrd_sel;
+ pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = &regs->axi.ob_ctrl.addr_high_reg_ovrd_value;
+ pcie_port->regs->axi.ob_ctrl.addr_size_replace = &regs->axi.ob_ctrl.addr_size_replace;
pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;
pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;
pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;
@@ -1120,11 +1100,20 @@ al_pcie_port_handle_init(
pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;
pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;
pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts_int;
+ pcie_port->regs->app.global_ctrl.sris_kp_counter = &regs->app.global_ctrl.sris_kp_counter_value;
pcie_port->regs->app.debug = &regs->app.debug;
pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;
+ pcie_port->regs->app.soc_int[0].status_0 = &regs->app.soc_int.status_0;
+ pcie_port->regs->app.soc_int[0].status_1 = &regs->app.soc_int.status_1;
+ pcie_port->regs->app.soc_int[0].status_2 = &regs->app.soc_int.status_2;
+ pcie_port->regs->app.soc_int[0].status_3 = &regs->app.soc_int.status_3;
pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;
+ pcie_port->regs->app.soc_int[0].mask_inta_leg_1 = &regs->app.soc_int.mask_inta_leg_1;
+ pcie_port->regs->app.soc_int[0].mask_inta_leg_2 = &regs->app.soc_int.mask_inta_leg_2;
pcie_port->regs->app.soc_int[0].mask_inta_leg_3 = &regs->app.soc_int.mask_inta_leg_3;
pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;
+ pcie_port->regs->app.soc_int[0].mask_msi_leg_1 = &regs->app.soc_int.mask_msi_leg_1;
+ pcie_port->regs->app.soc_int[0].mask_msi_leg_2 = &regs->app.soc_int.mask_msi_leg_2;
pcie_port->regs->app.soc_int[0].mask_msi_leg_3 = &regs->app.soc_int.mask_msi_leg_3;
pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;
pcie_port->regs->app.parity = &regs->app.parity;
@@ -1150,6 +1139,8 @@ al_pcie_port_handle_init(
struct al_pcie_rev3_regs __iomem *regs =
(struct al_pcie_rev3_regs __iomem *)pcie_reg_base;
pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
+ pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;
+ pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;
pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
@@ -1159,6 +1150,13 @@ al_pcie_port_handle_init(
pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;
pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;
pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;
+ pcie_port->regs->axi.ob_ctrl.io_addr_mask_h = &regs->axi.ob_ctrl.io_addr_mask_h;
+ pcie_port->regs->axi.ob_ctrl.ar_msg_addr_mask_h = &regs->axi.ob_ctrl.ar_msg_addr_mask_h;
+ pcie_port->regs->axi.ob_ctrl.aw_msg_addr_mask_h = &regs->axi.ob_ctrl.aw_msg_addr_mask_h;
+ pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = &regs->axi.ob_ctrl.tgtid_reg_ovrd;
+ pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = &regs->axi.ob_ctrl.addr_high_reg_ovrd_sel;
+ pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = &regs->axi.ob_ctrl.addr_high_reg_ovrd_value;
+ pcie_port->regs->axi.ob_ctrl.addr_size_replace = &regs->axi.ob_ctrl.addr_size_replace;
pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;
pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;
pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;
@@ -1213,9 +1211,17 @@ al_pcie_port_handle_init(
pcie_port->regs->app.debug = &regs->app.debug;
for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
+ pcie_port->regs->app.soc_int[i].status_0 = &regs->app.soc_int_per_func[i].status_0;
+ pcie_port->regs->app.soc_int[i].status_1 = &regs->app.soc_int_per_func[i].status_1;
+ pcie_port->regs->app.soc_int[i].status_2 = &regs->app.soc_int_per_func[i].status_2;
+ pcie_port->regs->app.soc_int[i].status_3 = &regs->app.soc_int_per_func[i].status_3;
pcie_port->regs->app.soc_int[i].mask_inta_leg_0 = &regs->app.soc_int_per_func[i].mask_inta_leg_0;
+ pcie_port->regs->app.soc_int[i].mask_inta_leg_1 = &regs->app.soc_int_per_func[i].mask_inta_leg_1;
+ pcie_port->regs->app.soc_int[i].mask_inta_leg_2 = &regs->app.soc_int_per_func[i].mask_inta_leg_2;
pcie_port->regs->app.soc_int[i].mask_inta_leg_3 = &regs->app.soc_int_per_func[i].mask_inta_leg_3;
pcie_port->regs->app.soc_int[i].mask_msi_leg_0 = &regs->app.soc_int_per_func[i].mask_msi_leg_0;
+ pcie_port->regs->app.soc_int[i].mask_msi_leg_1 = &regs->app.soc_int_per_func[i].mask_msi_leg_1;
+ pcie_port->regs->app.soc_int[i].mask_msi_leg_2 = &regs->app.soc_int_per_func[i].mask_msi_leg_2;
pcie_port->regs->app.soc_int[i].mask_msi_leg_3 = &regs->app.soc_int_per_func[i].mask_msi_leg_3;
}
@@ -1224,6 +1230,7 @@ al_pcie_port_handle_init(
pcie_port->regs->app.parity = &regs->app.parity;
pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
+ pcie_port->regs->app.cfg_func_ext = &regs->app.cfg_func_ext;
for (i = 0; i < AL_MAX_NUM_OF_PFS; i++)
pcie_port->regs->app.status_per_func[i] = &regs->app.status_per_func[i];
@@ -1260,6 +1267,10 @@ al_pcie_port_handle_init(
/* set maximum number of physical functions */
pcie_port->max_num_of_pfs = al_pcie_port_max_num_of_pfs_get(pcie_port);
+ /* Clear 'nof_p_hdr' & 'nof_np_hdr' to later know if they where changed by the user */
+ pcie_port->ib_hcrd_config.nof_np_hdr = 0;
+ pcie_port->ib_hcrd_config.nof_p_hdr = 0;
+
al_dbg("pcie port handle initialized. port id: %d, rev_id %d, regs base %p\n",
port_id, pcie_port->rev_id, pcie_reg_base);
return 0;
@@ -1294,6 +1305,12 @@ al_pcie_pf_handle_init(
return 0;
}
+/** Get port revision ID */
+int al_pcie_port_rev_id_get(struct al_pcie_port *pcie_port)
+{
+ return pcie_port->rev_id;
+}
+
/************************** Pre PCIe Port Enable API **************************/
/** configure pcie operating mode (root complex or endpoint) */
@@ -1346,7 +1363,7 @@ al_pcie_port_operating_mode_config(
"EndPoint" : "Root Complex");
return 0;
}
- al_info("PCIe %d: set operating mode to %s\n",
+ al_dbg("PCIe %d: set operating mode to %s\n",
pcie_port->port_id, (mode == AL_PCIE_OPERATING_MODE_EP) ?
"EndPoint" : "Root Complex");
AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
@@ -1362,6 +1379,7 @@ int
al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes)
{
struct al_pcie_regs *regs = pcie_port->regs;
+ uint32_t active_lanes_val;
if (al_pcie_port_is_enabled(pcie_port)) {
al_err("PCIe %d: already enabled, cannot set max lanes\n",
@@ -1370,7 +1388,7 @@ al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes)
}
/* convert to bitmask format (4 ->'b1111, 2 ->'b11, 1 -> 'b1) */
- uint32_t active_lanes_val = AL_PCIE_PARSE_LANES(lanes);
+ active_lanes_val = AL_PCIE_PARSE_LANES(lanes);
al_reg_write32_masked(regs->axi.pcie_global.conf,
(pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
@@ -1387,11 +1405,7 @@ al_pcie_port_max_num_of_pfs_set(
struct al_pcie_port *pcie_port,
uint8_t max_num_of_pfs)
{
- if (al_pcie_port_is_enabled(pcie_port)) {
- al_err("PCIe %d: already enabled, cannot set max num of PFs\n",
- pcie_port->port_id);
- return -EINVAL;
- }
+ struct al_pcie_regs *regs = pcie_port->regs;
if (pcie_port->rev_id == AL_PCIE_REV_ID_3)
al_assert(max_num_of_pfs <= REV3_MAX_NUM_OF_PFS);
@@ -1400,6 +1414,33 @@ al_pcie_port_max_num_of_pfs_set(
pcie_port->max_num_of_pfs = max_num_of_pfs;
+ if (al_pcie_port_is_enabled(pcie_port) && (pcie_port->rev_id == AL_PCIE_REV_ID_3)) {
+ enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
+
+ al_bool is_multi_pf =
+ ((op_mode == AL_PCIE_OPERATING_MODE_EP) && (pcie_port->max_num_of_pfs > 1));
+
+ /* Set maximum physical function numbers */
+ al_reg_write32_masked(
+ &regs->port_regs->timer_ctrl_max_func_num,
+ PCIE_PORT_GEN3_MAX_FUNC_NUM,
+ pcie_port->max_num_of_pfs - 1);
+
+ al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
+
+ /**
+ * in EP mode, when we have more than 1 PF we need to assert
+ * multi-pf support so the host scan all PFs
+ */
+ al_reg_write32_masked((uint32_t __iomem *)
+ (&regs->core_space[0].config_header[0] +
+ (PCIE_BIST_HEADER_TYPE_BASE >> 2)),
+ PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK,
+ is_multi_pf ? PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK : 0);
+
+ al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
+ }
+
return 0;
}
@@ -1503,6 +1544,28 @@ al_pcie_operating_mode_get(
return AL_PCIE_OPERATING_MODE_UNKNOWN;
}
+/* PCIe AXI quality of service configuration */
+void al_pcie_axi_qos_config(
+ struct al_pcie_port *pcie_port,
+ unsigned int arqos,
+ unsigned int awqos)
+{
+ struct al_pcie_regs *regs = pcie_port->regs;
+
+ al_assert(pcie_port);
+ al_assert(arqos <= PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_VAL_MAX);
+ al_assert(awqos <= PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_VAL_MAX);
+
+ al_reg_write32_masked(
+ regs->axi.ctrl.master_arctl,
+ PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_MASK,
+ arqos << PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_SHIFT);
+ al_reg_write32_masked(
+ regs->axi.ctrl.master_awctl,
+ PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_MASK,
+ awqos << PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_SHIFT);
+}
+
/**************************** PCIe Port Enable API ****************************/
/** Enable PCIe port (deassert reset) */
@@ -1518,17 +1581,19 @@ al_pcie_port_enable(struct al_pcie_port *pcie_port)
/**
* Set inbound header credit and outstanding outbound reads defaults
+ * if the port initiator doesn't set it.
* Must be called before port enable (PCIE_EXIST)
*/
- al_pcie_ib_hcrd_os_ob_reads_config_default(pcie_port);
+ if ((pcie_port->ib_hcrd_config.nof_np_hdr == 0) ||
+ (pcie_port->ib_hcrd_config.nof_p_hdr == 0))
+ al_pcie_ib_hcrd_os_ob_reads_config_default(pcie_port);
/*
* Disable ATS capability
* - must be done before core reset deasserted
* - rev_id 0 - no effect, but no harm
*/
- if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) ||
- (pcie_port->rev_id == AL_PCIE_REV_ID_1) ||
+ if ((pcie_port->rev_id == AL_PCIE_REV_ID_1) ||
(pcie_port->rev_id == AL_PCIE_REV_ID_2)) {
al_reg_write32_masked(
regs->axi.ordering.pos_cntl,
@@ -1679,26 +1744,8 @@ al_pcie_port_config(struct al_pcie_port *pcie_port,
}
if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
- /* Set maximum physical function numbers */
- al_reg_write32_masked(
- &regs->port_regs->timer_ctrl_max_func_num,
- PCIE_PORT_GEN3_MAX_FUNC_NUM,
- pcie_port->max_num_of_pfs - 1);
-
al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
- /**
- * in EP mode, when we have more than 1 PF we need to assert
- * multi-pf support so the host scan all PFs
- */
- if ((op_mode == AL_PCIE_OPERATING_MODE_EP) && (pcie_port->max_num_of_pfs > 1)) {
- al_reg_write32_masked((uint32_t __iomem *)
- (&regs->core_space[0].config_header[0] +
- (PCIE_BIST_HEADER_TYPE_BASE >> 2)),
- PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK,
- PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK);
- }
-
/* Disable TPH next pointer */
for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
al_reg_write32_masked(regs->core_space[i].tph_cap_base,
@@ -1713,6 +1760,8 @@ al_pcie_port_config(struct al_pcie_port *pcie_port,
if (status)
goto done;
+ al_pcie_port_max_num_of_pfs_set(pcie_port, pcie_port->max_num_of_pfs);
+
al_pcie_port_ram_parity_int_config(pcie_port, params->enable_ram_parity_int);
al_pcie_port_axi_parity_int_config(pcie_port, params->enable_axi_parity_int);
@@ -1734,14 +1783,6 @@ al_pcie_port_config(struct al_pcie_port *pcie_port,
if (status)
goto done;
- if (params->tl_credits)
- status = al_pcie_port_tl_credits_config(pcie_port, params->tl_credits);
- if (status)
- goto done;
-
- if (params->features)
- al_pcie_port_features_config(pcie_port, params->features);
-
if (params->sris_params)
status = al_pcie_port_sris_config(pcie_port, params->sris_params,
params->link_params->max_speed);
@@ -1904,6 +1945,19 @@ al_pcie_link_stop(struct al_pcie_port *pcie_port)
return 0;
}
+/** return AL_TRUE is link started (LTSSM enabled) and AL_FALSE otherwise */
+al_bool al_pcie_is_link_started(struct al_pcie_port *pcie_port)
+{
+ struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;
+
+ uint32_t port_init = al_reg_read32(regs->app.global_ctrl.port_init);
+ uint8_t ltssm_en = AL_REG_FIELD_GET(port_init,
+ PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK,
+ PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT);
+
+ return ltssm_en;
+}
+
/* wait for link up indication */
int
al_pcie_link_up_wait(struct al_pcie_port *pcie_port, uint32_t timeout_ms)
@@ -1912,7 +1966,7 @@ al_pcie_link_up_wait(struct al_pcie_port *pcie_port, uint32_t timeout_ms)
while (wait_count-- > 0) {
if (al_pcie_check_link(pcie_port, NULL)) {
- al_info("PCIe_%d: <<<<<<<<< Link up >>>>>>>>>\n", pcie_port->port_id);
+ al_dbg("PCIe_%d: <<<<<<<<< Link up >>>>>>>>>\n", pcie_port->port_id);
return 0;
} else
al_dbg("PCIe_%d: No link up, %d attempts remaining\n",
@@ -1920,7 +1974,7 @@ al_pcie_link_up_wait(struct al_pcie_port *pcie_port, uint32_t timeout_ms)
al_udelay(AL_PCIE_LINKUP_WAIT_INTERVAL);
}
- al_info("PCIE_%d: link is not established in time\n",
+ al_dbg("PCIE_%d: link is not established in time\n",
pcie_port->port_id);
return ETIMEDOUT;
@@ -1936,6 +1990,15 @@ al_pcie_link_status(struct al_pcie_port *pcie_port,
al_assert(status);
+ if (!al_pcie_port_is_enabled(pcie_port)) {
+ al_dbg("PCIe %d: port not enabled, no link.\n", pcie_port->port_id);
+ status->link_up = AL_FALSE;
+ status->speed = AL_PCIE_LINK_SPEED_DEFAULT;
+ status->lanes = 0;
+ status->ltssm_state = 0;
+ return 0;
+ }
+
status->link_up = al_pcie_check_link(pcie_port, &status->ltssm_state);
if (!status->link_up) {
@@ -1962,7 +2025,7 @@ al_pcie_link_status(struct al_pcie_port *pcie_port,
pcie_port->port_id, pcie_lnksta);
}
status->lanes = (pcie_lnksta & AL_PCI_EXP_LNKSTA_NLW) >> AL_PCI_EXP_LNKSTA_NLW_SHIFT;
- al_info("PCIe %d: Link up. speed gen%d negotiated width %d\n",
+ al_dbg("PCIe %d: Link up. speed gen%d negotiated width %d\n",
pcie_port->port_id, status->speed, status->lanes);
return 0;
@@ -2143,7 +2206,7 @@ al_pcie_port_snoop_config(struct al_pcie_port *pcie_port, al_bool enable_axi_sno
struct al_pcie_regs *regs = pcie_port->regs;
/* Set snoop mode */
- al_info("PCIE_%d: snoop mode %s\n",
+ al_dbg("PCIE_%d: snoop mode %s\n",
pcie_port->port_id, enable_axi_snoop ? "enable" : "disable");
if (enable_axi_snoop) {
@@ -2311,6 +2374,19 @@ al_pcie_app_req_retry_set(
mask, (en == AL_TRUE) ? mask : 0);
}
+/* Check if deferring incoming configuration requests is enabled or not */
+al_bool al_pcie_app_req_retry_get_status(struct al_pcie_port *pcie_port)
+{
+ struct al_pcie_regs *regs = pcie_port->regs;
+ uint32_t pm_control;
+ uint32_t mask = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
+ PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN :
+ PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN;
+
+ pm_control = al_reg_read32(regs->app.global_ctrl.pm_control);
+ return (pm_control & mask) ? AL_TRUE : AL_FALSE;
+}
+
/*************** Internal Address Translation Unit (ATU) API ******************/
/** program internal ATU region entry */
@@ -2345,6 +2421,7 @@ al_pcie_atu_region_set(
if (!atu_region->enforce_ob_atu_region_set) {
al_err("PCIe %d: setting OB iATU after link is started is not allowed\n",
pcie_port->port_id);
+ al_assert(AL_FALSE);
return -EINVAL;
} else {
al_info("PCIe %d: setting OB iATU even after link is started\n",
@@ -2369,7 +2446,63 @@ al_pcie_atu_region_set(
/* configure the limit, not needed when working in BAR match mode */
if (atu_region->match_mode == 0) {
uint32_t limit_reg_val;
- if (pcie_port->rev_id > AL_PCIE_REV_ID_0) {
+ uint32_t *limit_ext_reg =
+ (atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND) ?
+ &regs->app.atu.out_mask_pair[atu_region->index / 2] :
+ &regs->app.atu.in_mask_pair[atu_region->index / 2];
+ uint32_t limit_ext_reg_mask =
+ (atu_region->index % 2) ?
+ PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_MASK :
+ PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_MASK;
+ unsigned int limit_ext_reg_shift =
+ (atu_region->index % 2) ?
+ PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_SHIFT :
+ PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_SHIFT;
+ uint64_t limit_sz_msk =
+ atu_region->limit - atu_region->base_addr;
+ uint32_t limit_ext_reg_val = (uint32_t)(((limit_sz_msk) >>
+ 32) & 0xFFFFFFFF);
+
+ if (limit_ext_reg_val) {
+ limit_reg_val = (uint32_t)((limit_sz_msk) & 0xFFFFFFFF);
+ al_assert(limit_reg_val == 0xFFFFFFFF);
+ } else {
+ limit_reg_val = (uint32_t)(atu_region->limit &
+ 0xFFFFFFFF);
+ }
+
+ al_reg_write32_masked(
+ limit_ext_reg,
+ limit_ext_reg_mask,
+ limit_ext_reg_val << limit_ext_reg_shift);
+
+ al_reg_write32(&regs->port_regs->iatu.limit_addr,
+ limit_reg_val);
+ }
+
+
+ /**
+ * Addressing RMN: 3186
+ *
+ * RMN description:
+ * Bug in SNPS IP (versions 4.21 , 4.10a-ea02)
+ * In CFG request created via outbound atu (shift mode) bits [27:12] go to
+ * [31:16] , the shifting is correct , however the ATU leaves bit [15:12]
+ * to their original values, this is then transmited in the tlp .
+ * Those bits are currently reserved ,bit might be non-resv. in future generations .
+ *
+ * Software flow:
+ * Enable HW fix
+ * rev=REV1,REV2 set bit 15 in corresponding app_reg.atu.out_mask
+ * rev>REV2 set corresponding bit is app_reg.atu.reg_out_mask
+ */
+ if ((atu_region->cfg_shift_mode == AL_TRUE) &&
+ (atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND)) {
+ if (pcie_port->rev_id > AL_PCIE_REV_ID_2) {
+ al_reg_write32_masked(regs->app.atu.reg_out_mask,
+ 1 << (atu_region->index) ,
+ 1 << (atu_region->index));
+ } else {
uint32_t *limit_ext_reg =
(atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND) ?
&regs->app.atu.out_mask_pair[atu_region->index / 2] :
@@ -2382,29 +2515,12 @@ al_pcie_atu_region_set(
(atu_region->index % 2) ?
PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_SHIFT :
PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_SHIFT;
- uint64_t limit_sz_msk =
- atu_region->limit - atu_region->base_addr;
- uint32_t limit_ext_reg_val = (uint32_t)(((limit_sz_msk) >>
- 32) & 0xFFFFFFFF);
-
- if (limit_ext_reg_val) {
- limit_reg_val = (uint32_t)((limit_sz_msk) & 0xFFFFFFFF);
- al_assert(limit_reg_val == 0xFFFFFFFF);
- } else {
- limit_reg_val = (uint32_t)(atu_region->limit &
- 0xFFFFFFFF);
- }
al_reg_write32_masked(
- limit_ext_reg,
- limit_ext_reg_mask,
- limit_ext_reg_val << limit_ext_reg_shift);
- } else {
- limit_reg_val = (uint32_t)(atu_region->limit & 0xFFFFFFFF);
+ limit_ext_reg,
+ limit_ext_reg_mask,
+ (AL_BIT(15)) << limit_ext_reg_shift);
}
-
- al_reg_write32(&regs->port_regs->iatu.limit_addr,
- limit_reg_val);
}
reg = 0;
@@ -2505,7 +2621,22 @@ al_pcie_axi_io_config(
PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN);
}
-/************** Interrupt generation (Endpoint mode Only) API *****************/
+/************** Interrupt and Event generation (Endpoint mode Only) API *****************/
+
+int al_pcie_pf_flr_done_gen(struct al_pcie_pf *pcie_pf)
+{
+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
+ unsigned int pf_num = pcie_pf->pf_num;
+
+ al_reg_write32_masked(regs->app.global_ctrl.events_gen[pf_num],
+ PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE,
+ PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE);
+ al_udelay(AL_PCIE_FLR_DONE_INTERVAL);
+ al_reg_write32_masked(regs->app.global_ctrl.events_gen[pf_num],
+ PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE, 0);
+ return 0;
+}
+
/** generate INTx Assert/DeAssert Message */
int
@@ -2607,15 +2738,16 @@ al_pcie_msix_masked(struct al_pcie_pf *pcie_pf)
}
/******************** Advanced Error Reporting (AER) API **********************/
-
-/** configure AER capability */
-int
-al_pcie_aer_config(
- struct al_pcie_pf *pcie_pf,
- struct al_pcie_aer_params *params)
+/************************* Auxiliary functions ********************************/
+/* configure AER capability */
+static int
+al_pcie_aer_config_aux(
+ struct al_pcie_port *pcie_port,
+ unsigned int pf_num,
+ struct al_pcie_aer_params *params)
{
- struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
- struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
+ struct al_pcie_regs *regs = pcie_port->regs;
+ struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;
uint32_t reg_val;
reg_val = al_reg_read32(&aer_regs->header);
@@ -2641,8 +2773,22 @@ al_pcie_aer_config(
(params->ecrc_gen_en ? PCIE_AER_CTRL_STAT_ECRC_GEN_EN : 0) |
(params->ecrc_chk_en ? PCIE_AER_CTRL_STAT_ECRC_CHK_EN : 0));
+ /**
+ * Addressing RMN: 5119
+ *
+ * RMN description:
+ * ECRC generation for outbound request translated by iATU is effected
+ * by iATU setting instead of ecrc_gen_bit in AER
+ *
+ * Software flow:
+ * When enabling ECRC generation, set the outbound iATU to generate ECRC
+ */
+ if (params->ecrc_gen_en == AL_TRUE) {
+ al_pcie_ecrc_gen_ob_atu_enable(pcie_port, pf_num);
+ }
+
al_reg_write32_masked(
- regs->core_space[pcie_pf->pf_num].pcie_dev_ctrl_status,
+ regs->core_space[pf_num].pcie_dev_ctrl_status,
PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN |
PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN |
PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN |
@@ -2663,12 +2809,14 @@ al_pcie_aer_config(
return 0;
}
-/** AER uncorretable errors get and clear */
-unsigned int
-al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf *pcie_pf)
+/** AER uncorrectable errors get and clear */
+static unsigned int
+al_pcie_aer_uncorr_get_and_clear_aux(
+ struct al_pcie_port *pcie_port,
+ unsigned int pf_num)
{
- struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
- struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
+ struct al_pcie_regs *regs = pcie_port->regs;
+ struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;
uint32_t reg_val;
reg_val = al_reg_read32(&aer_regs->uncorr_err_stat);
@@ -2677,12 +2825,14 @@ al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf *pcie_pf)
return reg_val;
}
-/** AER corretable errors get and clear */
-unsigned int
-al_pcie_aer_corr_get_and_clear(struct al_pcie_pf *pcie_pf)
+/** AER correctable errors get and clear */
+static unsigned int
+al_pcie_aer_corr_get_and_clear_aux(
+ struct al_pcie_port *pcie_port,
+ unsigned int pf_num)
{
- struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
- struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
+ struct al_pcie_regs *regs = pcie_port->regs;
+ struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;
uint32_t reg_val;
reg_val = al_reg_read32(&aer_regs->corr_err_stat);
@@ -2696,19 +2846,123 @@ al_pcie_aer_corr_get_and_clear(struct al_pcie_pf *pcie_pf)
#endif
/** AER get the header for the TLP corresponding to a detected error */
-void
-al_pcie_aer_err_tlp_hdr_get(
- struct al_pcie_pf *pcie_pf,
+static void
+al_pcie_aer_err_tlp_hdr_get_aux(
+ struct al_pcie_port *pcie_port,
+ unsigned int pf_num,
uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS])
{
- struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
- struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
+ struct al_pcie_regs *regs = pcie_port->regs;
+ struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pf_num].aer;
int i;
for (i = 0; i < AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS; i++)
hdr[i] = al_reg_read32(&aer_regs->header_log[i]);
}
+/******************** EP AER functions **********************/
+/** configure EP physical function AER capability */
+int al_pcie_aer_config(
+ struct al_pcie_pf *pcie_pf,
+ struct al_pcie_aer_params *params)
+{
+ al_assert(pcie_pf);
+ al_assert(params);
+
+ return al_pcie_aer_config_aux(
+ pcie_pf->pcie_port, pcie_pf->pf_num, params);
+}
+
+/** EP physical function AER uncorrectable errors get and clear */
+unsigned int al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf *pcie_pf)
+{
+ al_assert(pcie_pf);
+
+ return al_pcie_aer_uncorr_get_and_clear_aux(
+ pcie_pf->pcie_port, pcie_pf->pf_num);
+}
+
+/** EP physical function AER correctable errors get and clear */
+unsigned int al_pcie_aer_corr_get_and_clear(struct al_pcie_pf *pcie_pf)
+{
+ al_assert(pcie_pf);
+
+ return al_pcie_aer_corr_get_and_clear_aux(
+ pcie_pf->pcie_port, pcie_pf->pf_num);
+}
+
+/**
+ * EP physical function AER get the header for
+ * the TLP corresponding to a detected error
+ * */
+void al_pcie_aer_err_tlp_hdr_get(
+ struct al_pcie_pf *pcie_pf,
+ uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS])
+{
+ al_assert(pcie_pf);
+ al_assert(hdr);
+
+ al_pcie_aer_err_tlp_hdr_get_aux(
+ pcie_pf->pcie_port, pcie_pf->pf_num, hdr);
+}
+
+/******************** RC AER functions **********************/
+/** configure RC port AER capability */
+int al_pcie_port_aer_config(
+ struct al_pcie_port *pcie_port,
+ struct al_pcie_aer_params *params)
+{
+ al_assert(pcie_port);
+ al_assert(params);
+
+ /**
+ * For RC mode there's no PFs (neither PF handles),
+ * therefore PF#0 is used
+ * */
+ return al_pcie_aer_config_aux(pcie_port, 0, params);
+}
+
+/** RC port AER uncorrectable errors get and clear */
+unsigned int al_pcie_port_aer_uncorr_get_and_clear(
+ struct al_pcie_port *pcie_port)
+{
+ al_assert(pcie_port);
+
+ /**
+ * For RC mode there's no PFs (neither PF handles),
+ * therefore PF#0 is used
+ * */
+ return al_pcie_aer_uncorr_get_and_clear_aux(pcie_port, 0);
+}
+
+/** RC port AER correctable errors get and clear */
+unsigned int al_pcie_port_aer_corr_get_and_clear(
+ struct al_pcie_port *pcie_port)
+{
+ al_assert(pcie_port);
+
+ /**
+ * For RC mode there's no PFs (neither PF handles),
+ * therefore PF#0 is used
+ * */
+ return al_pcie_aer_corr_get_and_clear_aux(pcie_port, 0);
+}
+
+/** RC port AER get the header for the TLP corresponding to a detected error */
+void al_pcie_port_aer_err_tlp_hdr_get(
+ struct al_pcie_port *pcie_port,
+ uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS])
+{
+ al_assert(pcie_port);
+ al_assert(hdr);
+
+ /**
+ * For RC mode there's no PFs (neither PF handles),
+ * therefore PF#0 is used
+ * */
+ al_pcie_aer_err_tlp_hdr_get_aux(pcie_port, 0, hdr);
+}
+
/********************** Loopback mode (RC and Endpoint modes) ************/
/** enter local pipe loopback mode */
diff --git a/al_hal_pcie.h b/al_hal_pcie.h
index 1ddc8eb70749..a5db654e1829 100644
--- a/al_hal_pcie.h
+++ b/al_hal_pcie.h
@@ -85,7 +85,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* - Root Complex mode
* - Set the Max Link Speed to Gen2
* - Set the max lanes width to 2 (x2)
- * - Disable reversal mode
* - Enable Snoops to support I/O Hardware cache coherency
* - Enable pcie core RAM parity
* - Enable pcie core AXI parity
@@ -97,7 +96,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* @code
* - struct al_pcie_link_params link_params = {
* AL_PCIE_LINK_SPEED_GEN2,
- * AL_FALSE, // disable reversal mode
* AL_PCIE_MPS_DEFAULT};
*
* - struct al_pcie_port_config_params config_params = {
@@ -162,15 +160,30 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
/********************************* Constants **********************************/
/******************************************************************************/
-/** Inbound header credits sum - rev 0/1/2 */
-#define AL_PCIE_REV_1_2_IB_HCRD_SUM 97
-/** Inbound header credits sum - rev 3 */
-#define AL_PCIE_REV3_IB_HCRD_SUM 259
+/**
+ * PCIe Core revision IDs:
+ * ID_1: Alpine V1
+ * ID_2: Alpine V2 x4
+ * ID_3: Alpine V2 x8
+ */
+#define AL_PCIE_REV_ID_1 1
+#define AL_PCIE_REV_ID_2 2
+#define AL_PCIE_REV_ID_3 3
/** Number of extended registers */
#define AL_PCIE_EX_REGS_NUM 40
/*******************************************************************************
+ * The inbound flow control for headers is programmable per P, NP and CPL
+ * transactions types. The following parameters define the total number of
+ * available header flow controls for all types.
+ ******************************************************************************/
+/** Inbound header credits sum - rev1/2 */
+#define AL_PCIE_REV_1_2_IB_HCRD_SUM 97
+/** Inbound header credits sum - rev3 */
+#define AL_PCIE_REV3_IB_HCRD_SUM 259
+
+/*******************************************************************************
* PCIe AER uncorrectable error bits
* To be used with the following functions:
* - al_pcie_aer_config
@@ -232,9 +245,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
/**
* al_pcie_ib_hcrd_config: data structure internally used in order to config
* inbound posted/non-posted parameters.
- * Note: it's required to have this structure in pcie_port handle since it has
- * a state (required/not-required) which is determined by outbound
- * outstanding configuration
+ * Note: this is a private member in pcie_port handle and MUST NOT be modified
+ * by the user.
*/
struct al_pcie_ib_hcrd_config {
/* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
@@ -251,10 +263,6 @@ enum al_pcie_max_payload_size {
AL_PCIE_MPS_DEFAULT,
AL_PCIE_MPS_128 = 0,
AL_PCIE_MPS_256 = 1,
- AL_PCIE_MPS_512 = 2,
- AL_PCIE_MPS_1024 = 3,
- AL_PCIE_MPS_2048 = 4,
- AL_PCIE_MPS_4096 = 5,
};
/**
@@ -271,10 +279,12 @@ struct al_pcie_port {
void *ex_regs;
void __iomem *pbs_regs;
- /* Revision ID */
+ /* Rev ID */
uint8_t rev_id;
unsigned int port_id;
uint8_t max_lanes;
+
+ /* For EP mode only */
uint8_t max_num_of_pfs;
/* Internally used */
@@ -284,6 +294,8 @@ struct al_pcie_port {
/**
* al_pcie_pf: the pf handle, a data structure used to handle PF specific
* functionality. Initialized using "al_pcie_pf_handle_init()"
+ *
+ * Note: This structure should be used for EP mode only
*/
struct al_pcie_pf {
unsigned int pf_num;
@@ -318,15 +330,13 @@ struct al_pcie_max_capability {
al_bool root_complex_mode_supported;
enum al_pcie_link_speed max_speed;
uint8_t max_lanes;
- al_bool reversal_supported;
uint8_t atu_regions_num;
- uint32_t atu_min_size;
+ uint32_t atu_min_size; /* Size granularity: 4 Kbytes */
};
/** PCIe link related parameters */
struct al_pcie_link_params {
- enum al_pcie_link_speed max_speed;
- al_bool enable_reversal;
+ enum al_pcie_link_speed max_speed;
enum al_pcie_max_payload_size max_payload_size;
};
@@ -362,22 +372,22 @@ struct al_pcie_gen3_params {
uint8_t local_fs; /* Low Frequency (LF) Value for Gen3 Transmit Equalization */
};
-/** Transport Layer credits parameters */
-struct al_pcie_tl_credits_params {
-};
-
-/** Various configuration features */
-struct al_pcie_features {
- /**
- * Enable MSI fix from the SATA to the PCIe EP
- * Only valid for port 0, when enabled as EP
- */
- al_bool sata_ep_msi_fix;
-};
-
/**
* Inbound posted/non-posted header credits and outstanding outbound reads
- * completion header configuration
+ * completion header configuration.
+ *
+ * This structure controls the resource partitioning of an important resource in
+ * the PCIe port. This resource includes the PCIe TLP headers coming on the PCIe
+ * port, and is shared between three types:
+ * - Inbound Non-posted, which are PCIe Reads as well as PCIe Config Cycles
+ * - Inbound Posted, i.e. PCIe Writes
+ * - Inbound Read-completion, which are the completions matching and outbound
+ * reads issued previously by the same core.
+ * The programmer need to take into consideration that a given outbound read
+ * request could be split on the return path into Ceiling[MPS_Size / 64] + 1
+ * of Read Completions.
+ * Programmers are not expected to modify these setting except for rare cases,
+ * where a different ratio between Posted-Writes and Read-Completions is desired
*
* Constraints:
* - nof_cpl_hdr + nof_np_hdr + nof_p_hdr ==
@@ -411,13 +421,26 @@ struct al_pcie_ib_hcrd_os_ob_reads_config {
unsigned int nof_p_hdr;
};
-/** PCIe Ack/Nak Latency and Replay timers */
+/**
+ * PCIe Ack/Nak Latency and Replay timers
+ *
+ * Note: Programmer is not expected to modify these values unless working in
+ * very slow external devices like low-end FPGA or hardware devices
+ * emulated in software
+ */
struct al_pcie_latency_replay_timers {
uint16_t round_trip_lat_limit;
uint16_t replay_timer_limit;
};
-/* SRIS KP counter values */
+/**
+ * SRIS KP counter values
+ *
+ * Description: SRIS is PCI SIG ECN, that enables the two peers on a given PCIe
+ * link to run with Separate Reference clock with Independent Spread spectrum
+ * clock and requires inserting PCIe SKP symbols on the link in faster frequency
+ * that original PCIe spec
+ */
struct al_pcie_sris_params {
/** set to AL_TRUE to use defaults and ignore the other parameters */
al_bool use_defaults;
@@ -425,7 +448,23 @@ struct al_pcie_sris_params {
uint16_t kp_counter_gen21;
};
-/** Relaxed ordering params */
+/**
+ * Relaxed ordering params
+ * Enable ordering relaxations for applications that does not require
+ * enforcement of 'completion must not bypass posted' ordering rule.
+ *
+ * Recommendation:
+ * - For downstream port, set enable_tx_relaxed_ordering
+ * - For upstream port
+ * - set enable_rx_relaxed_ordering
+ * - set enable tx_relaxed_ordering for emulated EP.
+ *
+ * Defaults:
+ * - For Root-Complex:
+ * - tx_relaxed_ordering = AL_FALSE, rx_relaxed_ordering = AL_TRUE
+ * - For End-Point:
+ * - tx_relaxed_ordering = AL_TRUE, rx_relaxed_ordering = AL_FALSE
+ */
struct al_pcie_relaxed_ordering_params {
al_bool enable_tx_relaxed_ordering;
al_bool enable_rx_relaxed_ordering;
@@ -445,20 +484,26 @@ struct al_pcie_port_config_params {
struct al_pcie_latency_replay_timers *lat_rply_timers;
struct al_pcie_gen2_params *gen2_params;
struct al_pcie_gen3_params *gen3_params;
- struct al_pcie_tl_credits_params *tl_credits;
- struct al_pcie_features *features;
- /* Sets all internal timers to Fast Mode for speeding up simulation.*/
+ /*
+ * Sets all internal timers to Fast Mode for speeding up simulation.
+ * this varible should be set always to AL_FALSE unless user is running
+ * on simulation setup
+ */
al_bool fast_link_mode;
/*
- * when true, the PCI unit will return Slave Error/Decoding Error to the master unit in case
- * of error. when false, the value 0xFFFFFFFF will be returned without error indication.
+ * when true, the PCI unit will return Slave Error/Decoding Error to any
+ * I/O Fabric master or Internal Processors in case of error.
+ * when false, the value 0xFFFFFFFF will be returned without error indication.
*/
al_bool enable_axi_slave_err_resp;
struct al_pcie_sris_params *sris_params;
struct al_pcie_relaxed_ordering_params *relaxed_ordering_params;
};
-/** BAR register configuration parameters (Endpoint Mode only) */
+/**
+ * BAR register configuration parameters
+ * Note: This structure should be used for EP mode only
+ */
struct al_pcie_ep_bar_params {
al_bool enable;
al_bool memory_space; /**< memory or io */
@@ -467,12 +512,30 @@ struct al_pcie_ep_bar_params {
uint64_t size; /* the bar size in bytes */
};
-/** PF config params (EP mode only) */
+/**
+ * PF config params (EP mode only)
+ * Note: This structure should be used for EP mode only
+ */
struct al_pcie_pf_config_params {
+ /**
+ * disable advertising D1 and D3hot state
+ * Recommended to be AL_TRUE
+ */
al_bool cap_d1_d3hot_dis;
+ /**
+ * disable advertising support for Function-Level-Reset
+ * Recommended to be AL_FALSE
+ */
al_bool cap_flr_dis;
+ /*
+ * disable advertising Advanced power management states
+ */
al_bool cap_aspm_dis;
al_bool bar_params_valid;
+ /*
+ * Note: only bar_params[0], [2] and [4] can have memory_64_bit enabled
+ * and in such case, the next bar ([1], [3], or [5] respectively) is not used
+ */
struct al_pcie_ep_bar_params bar_params[6];
struct al_pcie_ep_bar_params exp_bar_params;/* expansion ROM BAR*/
};
@@ -481,7 +544,7 @@ struct al_pcie_pf_config_params {
struct al_pcie_link_status {
al_bool link_up;
enum al_pcie_link_speed speed;
- uint8_t lanes;
+ uint8_t lanes; /* Number of lanes */
uint8_t ltssm_state;
};
@@ -491,18 +554,26 @@ struct al_pcie_lane_status {
enum al_pcie_link_speed requested_speed;
};
-/** PCIe MSIX capability configuration parameters */
+/**
+ * PCIe MSIX capability configuration parameters
+ * Note: This structure should be used for EP mode only
+ */
struct al_pcie_msix_params {
+ /* Number of entries - size can be up to: 2024 */
uint16_t table_size;
uint16_t table_offset;
uint8_t table_bar;
uint16_t pba_offset;
+ /* which bar to use when calculating the PBA table address and adding offset to */
uint16_t pba_bar;
};
/** PCIE AER capability parameters */
struct al_pcie_aer_params {
- /** ECRC Generation Enable */
+ /** ECRC Generation Enable
+ * while this feature is powerful, all known Chip-sets and processors
+ * do not support it as of 2015
+ */
al_bool ecrc_gen_en;
/** ECRC Check Enable */
al_bool ecrc_chk_en;
@@ -562,6 +633,13 @@ int al_pcie_pf_handle_init(
struct al_pcie_port *pcie_port,
unsigned int pf_num);
+/**
+ * Get port revision ID
+ * @param pcie_port pcie port handle
+ * @return Port rev_id
+ */
+int al_pcie_port_rev_id_get(struct al_pcie_port *pcie_port);
+
/************************** Pre PCIe Port Enable API **************************/
/**
@@ -582,7 +660,8 @@ int al_pcie_port_operating_mode_config(struct al_pcie_port *pcie_port,
* This function can be called only before enabling the controller using al_pcie_port_enable().
*
* @param pcie_port pcie port handle
- * @param lanes number of lanes
+ * @param lanes number of lanes (must be 1,2,4,8,16 and not any other value)
+ *
* Note: this function must be called before any al_pcie_port_config() calls
*
* @return 0 if no error found.
@@ -593,7 +672,12 @@ int al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes);
* Set maximum physical function numbers
* @param pcie_port pcie port handle
* @param max_num_of_pfs number of physical functions
- * Note: this function must be called before any al_pcie_pf_config() calls
+ *
+ * Notes:
+ * - this function must be called before any al_pcie_pf_config() calls
+ * - exposed on a given PCIe Endpoint port
+ * - PCIe rev1/rev2 supports only single Endpoint
+ * - PCIe rev3 can support up to 4
*/
int al_pcie_port_max_num_of_pfs_set(
struct al_pcie_port *pcie_port,
@@ -619,9 +703,27 @@ int al_pcie_port_ib_hcrd_os_ob_reads_config(
enum al_pcie_operating_mode al_pcie_operating_mode_get(
struct al_pcie_port *pcie_port);
+/**
+ * PCIe AXI quality of service configuration
+ *
+ * @param pcie_port
+ * Initialized PCIe port handle
+ * @param arqos
+ * AXI read quality of service (0 - 15)
+ * @param awqos
+ * AXI write quality of service (0 - 15)
+ */
+void al_pcie_axi_qos_config(
+ struct al_pcie_port *pcie_port,
+ unsigned int arqos,
+ unsigned int awqos);
+
/**************************** PCIe Port Enable API ****************************/
-/** Enable PCIe unit (deassert reset)
+/**
+ * Enable PCIe unit (deassert reset)
+ * This function only enables the port, without any configuration/link
+ * functionality. Should be called before starting any configuration/link API
*
* @param pcie_port pcie port handle
*
@@ -637,6 +739,8 @@ void al_pcie_port_disable(struct al_pcie_port *pcie_port);
/**
* Port memory shutdown/up
+ * Memory shutdown should be called for an unused ports for power-saving
+ *
* Caution: This function can be called only when the controller is disabled
*
* @param pcie_port pcie port handle
@@ -669,7 +773,7 @@ int al_pcie_port_config(struct al_pcie_port *pcie_port,
const struct al_pcie_port_config_params *params);
/**
- * @brief Configure a specific PF (EP params, sriov params, ...)
+ * @brief Configure a specific PF
* this function must be called before any datapath transactions
*
* @param pcie_pf pcie pf handle
@@ -685,7 +789,8 @@ int al_pcie_pf_config(
/**
* @brief start pcie link
- *
+ * This function starts the link and should be called only after port is enabled
+ * and pre port-enable and configurations are done
* @param pcie_port pcie port handle
*
* @return 0 if no error found
@@ -702,6 +807,14 @@ int al_pcie_link_start(struct al_pcie_port *pcie_port);
int al_pcie_link_stop(struct al_pcie_port *pcie_port);
/**
+ * @brief check if pcie link is started
+ * Note that this function checks if link is started rather than link is up
+ * @param pcie_port pcie port handle
+ * @return AL_TRUE if link is started and AL_FALSE otherwise
+ */
+al_bool al_pcie_is_link_started(struct al_pcie_port *pcie_port);
+
+/**
* @brief trigger link-disable
*
* @param pcie_port pcie port handle
@@ -753,6 +866,10 @@ void al_pcie_lane_status_get(
/**
* @brief trigger hot reset
+ * this function initiates In-Band reset while link is up.
+ * to initiate hot reset: call this function with AL_TRUE
+ * to exit from hos reset: call this function with AL_FALSE
+ * Note: This function should be called in RC mode only
*
* @param pcie_port pcie port handle
* @param enable AL_TRUE to enable hot-reset and AL_FALSE to disable it
@@ -766,6 +883,7 @@ int al_pcie_link_hot_reset(struct al_pcie_port *pcie_port, al_bool enable);
* this function initiates Link retraining by directing the Physical Layer LTSSM
* to the Recovery state. If the LTSSM is already in Recovery or Configuration,
* re-entering Recovery is permitted but not required.
+ * Note: This function should be called in RC mode only
* @param pcie_port pcie port handle
*
@@ -793,7 +911,9 @@ int al_pcie_link_change_width(struct al_pcie_port *pcie_port, uint8_t width);
/************************** Snoop Configuration API ***************************/
/**
- * @brief configure pcie port axi snoop
+ * @brief configure pcie port axi snoop
+ * This enable the inbound PCIe posted write data or the Read completion data to
+ * snoop the internal processor caches for I/O cache coherency
*
* @param pcie_port pcie port handle
* @param enable_axi_snoop enable snoop.
@@ -807,7 +927,10 @@ int al_pcie_port_snoop_config(struct al_pcie_port *pcie_port,
/************************** Configuration Space API ***************************/
/**
- * Configuration Space Access Through PCI-E_ECAM_Ext PASW (RC mode only)
+ * Configuration Space Access Through PCI-E_ECAM_Ext PASW
+ * This feature enables the internal processors to generate configuration cycles
+ * on the PCIe ports by writing to part of the processor memory space marked by
+ * the PCI-E_EXCAM_Ext address window
*/
/**
@@ -852,6 +975,11 @@ void al_pcie_local_cfg_space_write(
/**
* @brief set target_bus and mask_target_bus
+ *
+ * Call this function with target_bus set to the required bus of the next
+ * outbound config access to be issued. No need to call that function if the
+ * next config access bus equals to the last one.
+ *
* @param pcie_port pcie port handle
* @param target_bus
* @param mask_target_bus
@@ -875,6 +1003,8 @@ int al_pcie_target_bus_get(struct al_pcie_port *pcie_port,
/**
* Set secondary bus number
*
+ * Same as al_pcie_target_bus_set but with secondary bus
+ *
* @param pcie_port pcie port handle
* @param secbus pci secondary bus number
*
@@ -885,6 +1015,8 @@ int al_pcie_secondary_bus_set(struct al_pcie_port *pcie_port, uint8_t secbus);
/**
* Set subordinary bus number
*
+ * Same as al_pcie_target_bus_set but with subordinary bus
+ *
* @param pcie_port pcie port handle
* @param subbus the highest bus number of all of the buses that can be reached
* downstream of the PCIE instance.
@@ -897,13 +1029,22 @@ int al_pcie_subordinary_bus_set(struct al_pcie_port *pcie_port,uint8_t subbus);
* @brief Enable/disable deferring incoming configuration requests until
* initialization is complete. When enabled, the core completes incoming
* configuration requests with a Configuration Request Retry Status.
- * Other incoming Requests complete with Unsupported Request status.
+ * Other incoming non-configuration Requests complete with Unsupported Request status.
+ *
+ * Note: This function should be used for EP mode only
*
* @param pcie_port pcie port handle
* @param en enable/disable
*/
void al_pcie_app_req_retry_set(struct al_pcie_port *pcie_port, al_bool en);
+/**
+ * @brief Check if deferring incoming configuration requests is enabled or not
+ * @param pcie_port pcie port handle
+ * @return AL_TRUE is it's enabled and AL_FALSE otherwise
+ */
+al_bool al_pcie_app_req_retry_get_status(struct al_pcie_port *pcie_port);
+
/*************** Internal Address Translation Unit (ATU) API ******************/
enum al_pcie_atu_dir {
@@ -911,6 +1052,7 @@ enum al_pcie_atu_dir {
AL_PCIE_ATU_DIR_INBOUND = 1,
};
+/** decoding of the PCIe TLP Type as appears on the wire */
enum al_pcie_atu_tlp {
AL_PCIE_TLP_TYPE_MEM = 0,
AL_PCIE_TLP_TYPE_IO = 2,
@@ -920,57 +1062,134 @@ enum al_pcie_atu_tlp {
AL_PCIE_TLP_TYPE_RESERVED = 0x1f
};
+/** default response types */
enum al_pcie_atu_response {
AL_PCIE_RESPONSE_NORMAL = 0,
- AL_PCIE_RESPONSE_UR = 1,
- AL_PCIE_RESPONSE_CA = 2
+ AL_PCIE_RESPONSE_UR = 1, /* UR == Unsupported Request */
+ AL_PCIE_RESPONSE_CA = 2 /* CA == Completion Abort */
};
struct al_pcie_atu_region {
+
+ /**********************************************************************
+ * General Parameters *
+ **********************************************************************/
+
al_bool enable;
/* outbound or inbound */
enum al_pcie_atu_dir direction;
/* region index */
uint8_t index;
+ /* the 64-bit address that get matched with the 64-bit address incoming
+ * on the PCIe TLP
+ */
uint64_t base_addr;
- /** limit marks the region's end address. only bits [39:0] are valid
- * given the Alpine PoC maximum physical address space
+ /**
+ * limit marks the region's end address.
+ * For Alpine V1 (PCIe rev1): only bits [39:0] are valid
+ * For Alpine V2 (PCIe rev2/rev3): only bits [47:0] are valid
+ * an access is a hit in iATU if the:
+ * - address >= base_addr
+ * - address <= base_addr + limit
*/
uint64_t limit;
- /** the address that matches will be translated to this address + offset
+ /**
+ * the address that matches (hit) will be translated to:
+ * target_addr + offset
+ *
+ * Exmaple: accessing (base_addr + 0x1000) will be translated to:
+ * (target_addr + 0x1000) in case limit >= 0x1000
*/
uint64_t target_addr;
+ /**
+ * When the Invert feature is activated, an address match occurs when
+ * the untranslated address is not in the region bounded by the Base
+ * address and Limit address. Match occurs when the untranslated address
+ * is not in the region bounded by the base address and limit address
+ */
al_bool invert_matching;
- /* pcie tlp type*/
+ /**
+ * PCIe TLP type
+ * Can be: Mem, IO, CGF0, CFG1 or MSG
+ */
enum al_pcie_atu_tlp tlp_type;
- /* pcie frame header attr field*/
+ /**
+ * PCIe frame header attr field.
+ * When the address of a TLP is matched to this region, then the ATTR
+ * field of the TLP is changed to the value in this register.
+ */
uint8_t attr;
+
+ /**********************************************************************
+ * Outbound specific Parameters *
+ **********************************************************************/
+
/**
- * outbound specific params
+ * PCIe Message code
+ * MSG TLPs (Message Code). When the address of an outbound TLP is
+ * matched to this region, and the translated TLP TYPE field is Msg
+ * then the message field of the TLP is changed to the value in this
+ * register.
*/
- /* pcie message code */
uint8_t msg_code;
- al_bool cfg_shift_mode;
/**
- * inbound specific params
+ * CFG Shift Mode. This is useful for CFG transactions where the PCIe
+ * configuration mechanism maps bits [27:12] of the address to the
+ * bus/device and function number. This allows a CFG configuration space
+ * to be located in any 256MB window of your application memory space
+ * using a 28-bit effective address.Shifts bits [27:12] of the
+ * untranslated address to form bits [31:16] of the translated address.
*/
+ al_bool cfg_shift_mode;
+
+ /**********************************************************************
+ * Inbound specific Parameters *
+ **********************************************************************/
+
uint8_t bar_number;
- /* BAR match mode, used in EP for MEM and IO tlps*/
+ /**
+ * Match Mode. Determines Inbound matching mode for TLPs. The mode
+ * depends on the type of TLP that is received as follows:
+ * MEM-I/O: 0 = Address Match Mode
+ * 1 = BAR Match Mode
+ * CFG0 : 0 = Routing ID Match Mode
+ * 1 = Accept Mode
+ * MSG : 0 = Address Match Mode
+ * 1 = Vendor ID Match Mode
+ */
uint8_t match_mode;
/**
- * For outbound: enables taking the function number of the translated
- * TLP from the PCIe core. For inbound: enables ATU function match mode
+ * For outbound:
+ * - AL_TRUE : enables taking the function number of the translated TLP
+ * from the PCIe core
+ * - AL_FALSE: no function number is taken from PCIe core
+ * For inbound:
+ * - AL_TRUE : enables ATU function match mode
+ * - AL_FALSE: no function match mode applied to transactions
+ *
* Note: this boolean is ignored in RC mode
*/
al_bool function_match_bypass_mode;
/**
* The function number to match/bypass (see previous parameter)
- * Note: this parameter is ignored when previous param is FALSE
+ * Note: this parameter is ignored when previous parameter is AL_FALSE
*/
uint8_t function_match_bypass_mode_number;
- /* response code */
+ /**
+ * setting up what is the default response for an inbound transaction
+ * that matches the iATU
+ */
enum al_pcie_atu_response response;
+ /**
+ * Attr Match Enable. Ensures that a successful AT TLP field comparison
+ * match (see attr above) occurs for address translation to proceed
+ */
al_bool enable_attr_match_mode;
+ /**
+ * Message Code Match Enable(Msg TLPS). Ensures that a successful
+ * message Code TLP field comparison match (see Message msg_code)occurs
+ * (in MSG transactions) for address translation to proceed.
+ */
al_bool enable_msg_match_mode;
/**
* USE WITH CAUTION: setting this boolean to AL_TRUE allows setting the
@@ -1008,7 +1227,11 @@ void al_pcie_atu_region_get_fields(
/**
* @brief Configure axi io bar.
- * every hit to this bar will override size to 4 bytes.
+ *
+ * This is an EP feature, enabling PCIe IO transaction to be captured if it fits
+ * within start and end address, and then mapped to internal 4-byte
+ * memRead/memWrite. Every hit to this bar will override size to 4 bytes.
+ *
* @param pcie_port pcie port handle
* @param start the first address of the memory
* @param end the last address of the memory
@@ -1028,6 +1251,13 @@ enum al_pcie_legacy_int_type{
AL_PCIE_LEGACY_INTD
};
+
+/* @brief generate FLR_PF_DONE message
+ * @param pcie_pf pcie pf handle
+ * @return 0 if no error found
+ */
+int al_pcie_pf_flr_done_gen(struct al_pcie_pf *pcie_pf);
+
/**
* @brief generate INTx Assert/DeAssert Message
* @param pcie_pf pcie pf handle
@@ -1075,7 +1305,7 @@ al_bool al_pcie_msix_masked(struct al_pcie_pf *pcie_pf);
/******************** Advanced Error Reporting (AER) API **********************/
/**
- * @brief configure AER capability
+ * @brief configure EP physical function AER capability
* @param pcie_pf pcie pf handle
* @param params AER capability configuration parameters
* @return 0 if no error found
@@ -1085,7 +1315,7 @@ int al_pcie_aer_config(
struct al_pcie_aer_params *params);
/**
- * @brief AER uncorretable errors get and clear
+ * @brief EP physical function AER uncorrectable errors get and clear
* @param pcie_pf pcie pf handle
* @return bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for
* details
@@ -1093,7 +1323,7 @@ int al_pcie_aer_config(
unsigned int al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf *pcie_pf);
/**
- * @brief AER corretable errors get and clear
+ * @brief EP physical function AER correctable errors get and clear
* @param pcie_pf pcie pf handle
* @return bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for
* details
@@ -1101,7 +1331,8 @@ unsigned int al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf *pcie_pf);
unsigned int al_pcie_aer_corr_get_and_clear(struct al_pcie_pf *pcie_pf);
/**
- * @brief AER get the header for the TLP corresponding to a detected error
+ * @brief EP physical function AER get the header for
+ * the TLP corresponding to a detected error
* @param pcie_pf pcie pf handle
* @param hdr pointer to an array for getting the header
*/
@@ -1109,6 +1340,44 @@ void al_pcie_aer_err_tlp_hdr_get(
struct al_pcie_pf *pcie_pf,
uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS]);
+/**
+ * @brief configure RC port AER capability
+ * @param pcie_port pcie port handle
+ * @param params AER capability configuration parameters
+ * @return 0 if no error found
+ */
+int al_pcie_port_aer_config(
+ struct al_pcie_port *pcie_port,
+ struct al_pcie_aer_params *params);
+
+/**
+ * @brief RC port AER uncorrectable errors get and clear
+ * @param pcie_port pcie port handle
+ * @return bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for
+ * details
+ */
+unsigned int al_pcie_port_aer_uncorr_get_and_clear(
+ struct al_pcie_port *pcie_port);
+
+/**
+ * @brief RC port AER correctable errors get and clear
+ * @param pcie_port pcie port handle
+ * @return bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for
+ * details
+ */
+unsigned int al_pcie_port_aer_corr_get_and_clear(
+ struct al_pcie_port *pcie_port);
+
+/**
+ * @brief RC port AER get the header for
+ * the TLP corresponding to a detected error
+ * @param pcie_port pcie port handle
+ * @param hdr pointer to an array for getting the header
+ */
+void al_pcie_port_aer_err_tlp_hdr_get(
+ struct al_pcie_port *pcie_port,
+ uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS]);
+
/******************** Loop-Back mode (RC and Endpoint modes) ******************/
/**
diff --git a/al_hal_pcie_axi_reg.h b/al_hal_pcie_axi_reg.h
index 04d4bfdbca3f..b8e11645edda 100644
--- a/al_hal_pcie_axi_reg.h
+++ b/al_hal_pcie_axi_reg.h
@@ -72,7 +72,7 @@ struct al_pcie_rev1_2_axi_ctrl {
/* [0x28] */
uint32_t dbi_ctl;
/* [0x2c] */
- uint32_t vmid_mask;
+ uint32_t tgtid_mask;
uint32_t rsrvd[4];
};
struct al_pcie_rev3_axi_ctrl {
@@ -98,7 +98,7 @@ struct al_pcie_rev3_axi_ctrl {
/* [0x28] */
uint32_t dbi_ctl;
/* [0x2c] */
- uint32_t vmid_mask;
+ uint32_t tgtid_mask;
};
struct al_pcie_rev1_axi_ob_ctrl {
/* [0x0] */
@@ -145,10 +145,10 @@ struct al_pcie_rev2_axi_ob_ctrl {
/* [0x24] */
uint32_t msg_limit_h;
/*
- * [0x28] this register override the VMID field in the AXUSER [19:4],
+ * [0x28] this register override the Target-ID field in the AXUSER [19:4],
* for the AXI master port.
*/
- uint32_t vmid_reg_ovrd;
+ uint32_t tgtid_reg_ovrd;
/* [0x2c] this register override the ADDR[63:32] AXI master port. */
uint32_t addr_high_reg_ovrd_value;
/* [0x30] this register override the ADDR[63:32] AXI master port. */
@@ -196,10 +196,10 @@ struct al_pcie_rev3_axi_ob_ctrl {
/* [0x40] */
uint32_t aw_msg_addr_mask_h;
/*
- * [0x44] this register override the VMID field in the AXUSER [19:4],
+ * [0x44] this register override the Target-ID field in the AXUSER [19:4],
* for the AXI master port.
*/
- uint32_t vmid_reg_ovrd;
+ uint32_t tgtid_reg_ovrd;
/* [0x48] this register override the ADDR[63:32] AXI master port. */
uint32_t addr_high_reg_ovrd_value;
/* [0x4c] this register override the ADDR[63:32] AXI master port. */
@@ -783,9 +783,9 @@ struct al_pcie_rev3_axi_regs {
/* arprot value */
#define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_MASK 0x000001C0
#define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_SHIFT 6
-/* vmid val */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_VMID_VAL_MASK 0x01FFFE00
-#define PCIE_AXI_CTRL_MASTER_ARCTL_VMID_VAL_SHIFT 9
+/* tgtid val */
+#define PCIE_AXI_CTRL_MASTER_ARCTL_TGTID_VAL_MASK 0x01FFFE00
+#define PCIE_AXI_CTRL_MASTER_ARCTL_TGTID_VAL_SHIFT 9
/* IPA value */
#define PCIE_AXI_CTRL_MASTER_ARCTL_IPA_VAL (1 << 25)
/* overide snoop inidcation, if not set take it from mstr_armisc ... */
@@ -797,6 +797,7 @@ snoop indication value when override */
arqos value */
#define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_MASK 0xF0000000
#define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_SHIFT 28
+#define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_VAL_MAX 15
/**** Master_Awctl register ****/
/* override arcache */
@@ -809,9 +810,9 @@ arqos value */
/* awprot value */
#define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_MASK 0x000001C0
#define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_SHIFT 6
-/* vmid val */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_VMID_VAL_MASK 0x01FFFE00
-#define PCIE_AXI_CTRL_MASTER_AWCTL_VMID_VAL_SHIFT 9
+/* tgtid val */
+#define PCIE_AXI_CTRL_MASTER_AWCTL_TGTID_VAL_MASK 0x01FFFE00
+#define PCIE_AXI_CTRL_MASTER_AWCTL_TGTID_VAL_SHIFT 9
/* IPA value */
#define PCIE_AXI_CTRL_MASTER_AWCTL_IPA_VAL (1 << 25)
/* overide snoop inidcation, if not set take it from mstr_armisc ... */
@@ -823,6 +824,7 @@ snoop indication value when override */
awqos value */
#define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_MASK 0xF0000000
#define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_SHIFT 28
+#define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_VAL_MAX 15
/**** slv_ctl register ****/
#define PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN (1 << 6)
@@ -888,17 +890,17 @@ awqos value */
#define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_MASK 0x000003FF
#define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_SHIFT 0
-/**** vmid_reg_ovrd register ****/
+/**** tgtid_reg_ovrd register ****/
/*
* select if to take the value from register or from address[63:48]:
* 1'b1: register value.
* 1'b0: from address[63:48]
*/
-#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_SEL_MASK 0x0000FFFF
-#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_SEL_SHIFT 0
-/* vmid override value. */
-#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_VALUE_MASK 0xFFFF0000
-#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_VALUE_SHIFT 16
+#define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_SEL_MASK 0x0000FFFF
+#define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_SEL_SHIFT 0
+/* tgtid override value. */
+#define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_VALUE_MASK 0xFFFF0000
+#define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_VALUE_SHIFT 16
/**** addr_size_replace register ****/
/*
@@ -1255,17 +1257,17 @@ awqos value */
#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_MASK 0x0000C000
#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_SHIFT 14
/* choose the field from the axuser */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_AXUSER_MASK 0x00030000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_AXUSER_SHIFT 16
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_AXUSER_MASK 0x00030000
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_AXUSER_SHIFT 16
/* choose the field from register */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_REG_MASK 0x000C0000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_REG_SHIFT 18
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_REG_MASK 0x000C0000
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_REG_SHIFT 18
/* in case the field take from the address, offset field for each bit. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_ADDR_OFFSET_MASK 0x0FF00000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_ADDR_OFFSET_SHIFT 20
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_ADDR_OFFSET_MASK 0x0FF00000
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_ADDR_OFFSET_SHIFT 20
/* register value override */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_VMID89_VEC_OVRD_MASK 0x30000000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_VMID89_VEC_OVRD_SHIFT 28
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_TGTID89_VEC_OVRD_MASK 0x30000000
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_TGTID89_VEC_OVRD_SHIFT 28
/* Rsrvd */
#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_MASK 0xC0000000
#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_SHIFT 30
@@ -1291,9 +1293,9 @@ awqos value */
#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_RSRVD_SHIFT 30
/**** func_ctrl_4 register ****/
-/* When set take the corresponding bit address from vmid value. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_VMID_MASK 0x000003FF
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_VMID_SHIFT 0
+/* When set take the corresponding bit address from tgtid value. */
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK 0x000003FF
+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_SHIFT 0
/* override value. */
#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_MASK 0x000FFC00
#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_SHIFT 10
diff --git a/al_hal_pcie_interrupts.h b/al_hal_pcie_interrupts.h
index 357971ca63cb..41e6496d2fe1 100644
--- a/al_hal_pcie_interrupts.h
+++ b/al_hal_pcie_interrupts.h
@@ -81,7 +81,7 @@ enum al_pcie_app_int_grp_a {
/** [RC only] Deassert_INTB received */
AL_PCIE_APP_INT_DEASSERT_INTB = AL_BIT(2),
/**
- * [RC only] Deassert_INTA received - there's a didcated GIC interrupt
+ * [RC only] Deassert_INTA received - there's a dedicated GIC interrupt
* line that reflects the status of ASSERT/DEASSERT of INTA
*/
AL_PCIE_APP_INT_DEASSERT_INTA = AL_BIT(3),
@@ -92,7 +92,7 @@ enum al_pcie_app_int_grp_a {
/** [RC only] Assert_INTB received */
AL_PCIE_APP_INT_ASSERT_INTB = AL_BIT(6),
/**
- * [RC only] Assert_INTA received - there's a didcated GIC interrupt
+ * [RC only] Assert_INTA received - there's a dedicated GIC interrupt
* line that reflects the status of ASSERT/DEASSERT of INTA
*/
AL_PCIE_APP_INT_ASSERT_INTA = AL_BIT(7),
@@ -150,13 +150,13 @@ enum al_pcie_app_int_grp_b {
AL_PCIE_APP_INT_GRP_B_FTL_ERR_MSG_RCVD = AL_BIT(5),
/**
* [RC/EP] Vendor Defined Message received
- * Asserted when a vevdor message is received (with no data), buffers 2
+ * Asserted when a vendor message is received (with no data), buffers 2
* messages only, and latch the headers in registers
*/
AL_PCIE_APP_INT_GRP_B_VNDR_MSG_A_RCVD = AL_BIT(6),
/**
* [RC/EP] Vendor Defined Message received
- * Asserted when a vevdor message is received (with no data), buffers 2
+ * Asserted when a vendor message is received (with no data), buffers 2
* messages only, and latch the headers in registers
*/
AL_PCIE_APP_INT_GRP_B_VNDR_MSG_B_RCVD = AL_BIT(7),
@@ -166,7 +166,7 @@ enum al_pcie_app_int_grp_b {
AL_PCIE_APP_INT_GRP_B_LNK_EQ_REQ = AL_BIT(13),
/** [RC/EP] OB Vendor message request is granted by the PCIe core */
AL_PCIE_APP_INT_GRP_B_OB_VNDR_MSG_REQ_GRNT = AL_BIT(14),
- /** [RC only] CPL timeout from the PCIe core indiication */
+ /** [RC only] CPL timeout from the PCIe core indication */
AL_PCIE_APP_INT_GRP_B_CPL_TO = AL_BIT(15),
/** [RC/EP] Slave Response Composer Lookup Error */
AL_PCIE_APP_INT_GRP_B_SLV_RESP_COMP_LKUP_ERR = AL_BIT(16),
diff --git a/al_hal_pcie_regs.h b/al_hal_pcie_regs.h
index 15c5735e279f..09b99c5b9055 100644
--- a/al_hal_pcie_regs.h
+++ b/al_hal_pcie_regs.h
@@ -51,18 +51,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include "al_hal_pcie_w_reg_ex.h"
#endif
-/**
- * Revision IDs:
- * ID_0: SlickRock M0
- * ID_1: SlickRock A0
- * ID_2: PeakRock x4
- * ID_3: PeakRock x8
- */
-#define AL_PCIE_REV_ID_0 0
-#define AL_PCIE_REV_ID_1 1
-#define AL_PCIE_REV_ID_2 2
-#define AL_PCIE_REV_ID_3 3
-
#define AL_PCIE_AXI_REGS_OFFSET 0x0
#define AL_PCIE_REV_1_2_APP_REGS_OFFSET 0x1000
#define AL_PCIE_REV_3_APP_REGS_OFFSET 0x2000
@@ -74,6 +62,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define REV3_MAX_NUM_LANES 8
#define AL_MAX_NUM_OF_LANES 8 /* the maximum between all Revisions */
+/** Number of outbound atu regions - rev 1/2 */
+#define AL_PCIE_REV_1_2_ATU_NUM_OUTBOUND_REGIONS 12
+/** Number of outbound atu regions - rev 3 */
+#define AL_PCIE_REV_3_ATU_NUM_OUTBOUND_REGIONS 16
+
struct al_pcie_core_iatu_regs {
uint32_t index;
uint32_t cr1;
@@ -253,8 +246,10 @@ struct al_pcie_rev3_regs {
struct al_pcie_axi_ctrl {
uint32_t *global;
+ uint32_t *master_rctl;
uint32_t *master_arctl;
uint32_t *master_awctl;
+ uint32_t *master_ctl;
uint32_t *slv_ctl;
};
@@ -265,6 +260,13 @@ struct al_pcie_axi_ob_ctrl {
uint32_t *io_start_h;
uint32_t *io_limit_l;
uint32_t *io_limit_h;
+ uint32_t *io_addr_mask_h; /* Rev 3 only */
+ uint32_t *ar_msg_addr_mask_h; /* Rev 3 only */
+ uint32_t *aw_msg_addr_mask_h; /* Rev 3 only */
+ uint32_t *tgtid_reg_ovrd; /* Rev 2/3 only */
+ uint32_t *addr_high_reg_ovrd_value; /* Rev 2/3 only */
+ uint32_t *addr_high_reg_ovrd_sel; /* Rev 2/3 only */
+ uint32_t *addr_size_replace; /* Rev 2/3 only */
};
struct al_pcie_axi_pcie_global {
@@ -352,14 +354,23 @@ struct al_pcie_w_global_ctrl {
};
struct al_pcie_w_soc_int {
+ uint32_t *status_0;
+ uint32_t *status_1;
+ uint32_t *status_2;
+ uint32_t *status_3; /* Rev 2/3 only */
uint32_t *mask_inta_leg_0;
+ uint32_t *mask_inta_leg_1;
+ uint32_t *mask_inta_leg_2;
uint32_t *mask_inta_leg_3; /* Rev 2/3 only */
uint32_t *mask_msi_leg_0;
+ uint32_t *mask_msi_leg_1;
+ uint32_t *mask_msi_leg_2;
uint32_t *mask_msi_leg_3; /* Rev 2/3 only */
};
struct al_pcie_w_atu {
uint32_t *in_mask_pair;
uint32_t *out_mask_pair;
+ uint32_t *reg_out_mask; /* Rev 3 only */
};
struct al_pcie_w_regs {
@@ -375,6 +386,7 @@ struct al_pcie_w_regs {
struct al_pcie_revx_w_int_grp *int_grp_b;
struct al_pcie_revx_w_int_grp *int_grp_c;
struct al_pcie_revx_w_int_grp *int_grp_d;
+ struct al_pcie_rev3_w_cfg_func_ext *cfg_func_ext; /* Rev 3 only */
};
struct al_pcie_regs {
diff --git a/al_hal_pcie_w_reg.h b/al_hal_pcie_w_reg.h
index 44e9d952655d..137dfbde13ea 100644
--- a/al_hal_pcie_w_reg.h
+++ b/al_hal_pcie_w_reg.h
@@ -1498,7 +1498,7 @@ struct al_pcie_rev3_w_regs {
}
#endif
-#endif /* __AL_HAL_PCIE_W_REG_H */
+#endif /* __AL_HAL_pcie_w_REG_H */
/** @} end of ... group */
diff --git a/al_hal_plat_services.h b/al_hal_plat_services.h
index 217bb927f69f..278a8fa71dda 100644
--- a/al_hal_plat_services.h
+++ b/al_hal_plat_services.h
@@ -66,10 +66,29 @@ __FBSDID("$FreeBSD$");
#include <sys/errno.h>
#include <sys/lock.h>
#include <sys/mutex.h>
+#include <machine/bus.h>
/* Prototypes for all the bus_space structure functions */
-bs_protos(generic);
-bs_protos(generic_armv4);
+uint8_t generic_bs_r_1(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t offset);
+
+uint16_t generic_bs_r_2(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t offset);
+
+uint32_t generic_bs_r_4(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t offset);
+
+void generic_bs_w_1(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t offset, uint8_t value);
+
+void generic_bs_w_2(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t offset, uint16_t value);
+
+void generic_bs_w_4(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t offset, uint32_t value);
+
+void generic_bs_w_8(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t offset, uint64_t value);
#define __UNUSED __attribute__((unused))
@@ -79,6 +98,52 @@ extern "C" {
#endif
/* *INDENT-ON* */
+/**
+ * Make sure data will be visible by other masters (other CPUS and DMA).
+ * usually this is achieved by the ARM DMB instruction.
+ */
+static void al_data_memory_barrier(void);
+static void al_smp_data_memory_barrier(void);
+
+/**
+ * Make sure data will be visible by DMA masters, no restriction for other cpus
+ */
+static inline void
+al_data_memory_barrier(void)
+{
+#ifndef __aarch64__
+ dsb();
+#else
+ dsb(sy);
+#endif
+}
+
+/**
+ * Make sure data will be visible in order by other cpus masters.
+ */
+static inline void
+al_smp_data_memory_barrier(void)
+{
+#ifndef __aarch64__
+ dmb();
+#else
+ dmb(ish);
+#endif
+}
+
+/**
+ * Make sure write data will be visible in order by other cpus masters.
+ */
+static inline void
+al_local_data_memory_barrier(void)
+{
+#ifndef __aarch64__
+ dsb();
+#else
+ dsb(sy);
+#endif
+}
+
/*
* WMA: This is a hack which allows not modifying the __iomem accessing HAL code.
* On ARMv7, bus_handle holds the information about VA of accessed memory. It
@@ -168,50 +233,66 @@ uint64_t al_reg_read64(uint64_t * offset);
* @param offset register offset
* @param val value to write to the register
*/
-#define al_reg_write8(l,v) do { dsb(); generic_bs_w_1(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
+#define al_reg_write8(l, v) do { \
+ al_data_memory_barrier(); \
+ generic_bs_w_1(NULL, (bus_space_handle_t)l, 0, v); \
+ al_smp_data_memory_barrier(); \
+} while (0)
/**
* Write to MMIO 16 bits register
* @param offset register offset
* @param val value to write to the register
*/
-#define al_reg_write16(l,v) do { dsb(); generic_bs_w_2(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
+#define al_reg_write16(l, v) do { \
+ al_data_memory_barrier(); \
+ generic_bs_w_2(NULL, (bus_space_handle_t)l, 0, v); \
+ al_smp_data_memory_barrier(); \
+} while (0)
/**
* Write to MMIO 32 bits register
* @param offset register offset
* @param val value to write to the register
*/
-#define al_reg_write32(l,v) do { dsb(); generic_bs_w_4(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
+#define al_reg_write32(l, v) do { \
+ al_data_memory_barrier(); \
+ generic_bs_w_4(NULL, (bus_space_handle_t)l, 0, v); \
+ al_smp_data_memory_barrier(); \
+} while (0)
/**
* Write to MMIO 64 bits register
* @param offset register offset
* @param val value to write to the register
*/
-#define al_reg_write64(l,v) do { dsb(); generic_bs_w_8(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
+#define al_reg_write64(l, v) do { \
+ al_data_memory_barrier(); \
+ generic_bs_w_8(NULL, (bus_space_handle_t)l, 0, v); \
+ al_smp_data_memory_barrier(); \
+} while (0)
static inline uint8_t
al_reg_read8(uint8_t *l)
{
- dsb();
+ al_data_memory_barrier();
return (generic_bs_r_1(NULL, (bus_space_handle_t)l, 0));
}
static inline uint16_t
al_reg_read16(uint16_t *l)
{
- dsb();
+ al_data_memory_barrier();
return (generic_bs_r_2(NULL, (bus_space_handle_t)l, 0));
}
static inline uint32_t
al_reg_read32(uint32_t *l)
{
- dsb();
+ al_data_memory_barrier();
return (generic_bs_r_4(NULL, (bus_space_handle_t)l, 0));
}
@@ -223,10 +304,8 @@ al_reg_read32(uint32_t *l)
#define AL_DBG_LEVEL AL_DBG_LEVEL_ERR
-extern struct mtx al_dbg_lock;
-
-#define AL_DBG_LOCK() mtx_lock_spin(&al_dbg_lock)
-#define AL_DBG_UNLOCK() mtx_unlock_spin(&al_dbg_lock)
+#define AL_DBG_LOCK()
+#define AL_DBG_UNLOCK()
/**
* print message
@@ -278,39 +357,6 @@ extern struct mtx al_dbg_lock;
} while(AL_FALSE)
/**
- * Make sure data will be visible by other masters (other CPUS and DMA).
- * usually this is achieved by the ARM DMB instruction.
- */
-static void al_data_memory_barrier(void);
-
-/**
- * Make sure data will be visible by DMA masters, no restriction for other cpus
- */
-static inline void
-al_data_memory_barrier(void)
-{
- dsb();
-}
-
-/**
- * Make sure data will be visible in order by other cpus masters.
- */
-static inline void
-al_smp_data_memory_barrier(void)
-{
- dsb();
-}
-
-/**
- * Make sure write data will be visible in order by other cpus masters.
- */
-static inline void
-al_local_data_memory_barrier(void)
-{
- dsb();
-}
-
-/**
* al_udelay - micro sec delay
*/
#define al_udelay(u) DELAY(u)
diff --git a/al_hal_plat_types.h b/al_hal_plat_types.h
index 43896ae08f71..293fc3d703dd 100644
--- a/al_hal_plat_types.h
+++ b/al_hal_plat_types.h
@@ -60,24 +60,6 @@ typedef int al_bool; /** boolean */
#define AL_TRUE 1
#define AL_FALSE 0
-
-/* define types */
-#ifndef AL_HAVE_TYPES
-typedef unsigned char uint8_t; /** unsigned 8 bits */
-typedef unsigned short uint16_t; /** unsigned 16 bits */
-typedef unsigned int uint32_t; /** unsigned 32 bits */
-typedef unsigned long long uint64_t; /** unsigned 64 bits */
-
-typedef signed char int8_t; /** signed 8 bits */
-typedef short int int16_t; /** signed 16 bits */
-typedef signed int int32_t; /** signed 32 bits */
-
-/** An unsigned int that is guaranteed to be the same size as a pointer */
-/** C99 standard */
-typedef unsigned long uintptr_t;
-#endif
-
-
/** in LPAE mode, the address address is 40 bit, we extend it to 64 bit */
typedef uint64_t al_phys_addr_t;
diff --git a/al_hal_reg_utils.h b/al_hal_reg_utils.h
index f29c3c5247b5..42934ad35f4e 100644
--- a/al_hal_reg_utils.h
+++ b/al_hal_reg_utils.h
@@ -57,6 +57,7 @@ extern "C" {
/* *INDENT-ON* */
#define AL_BIT(b) (1UL << (b))
+#define AL_BIT_64(b) (1ULL << (b))
#define AL_ADDR_LOW(x) ((uint32_t)((al_phys_addr_t)(x)))
#define AL_ADDR_HIGH(x) ((uint32_t)((((al_phys_addr_t)(x)) >> 16) >> 16))
diff --git a/al_hal_serdes.c b/al_hal_serdes.c
index bb34d13c765f..d45a9438eeb4 100644
--- a/al_hal_serdes.c
+++ b/al_hal_serdes.c
@@ -1,5 +1,4 @@
-/*-
-*******************************************************************************
+/*******************************************************************************
Copyright (C) 2015 Annapurna Labs Ltd.
This file may be licensed under the terms of the Annapurna Labs Commercial
@@ -34,9 +33,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
-#include "al_hal_serdes.h"
-#include "al_hal_serdes_regs.h"
-#include "al_hal_serdes_internal_regs.h"
+#include "al_hal_serdes_hssp.h"
+#include "al_hal_serdes_hssp_regs.h"
+#include "al_hal_serdes_hssp_internal_regs.h"
#define SRDS_CORE_REG_ADDR(page, type, offset)\
(((page) << 13) | ((type) << 12) | (offset))
@@ -67,64 +66,41 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define AL_SERDES_RX_EYE_CAL_MDELAY 50
#define AL_SERDES_RX_EYE_CAL_TRIES 70
+#if (!defined(AL_SERDES_BASIC_SERVICES_ONLY)) || (AL_SERDES_BASIC_SERVICES_ONLY == 0)
+#define AL_SRDS_ADV_SRVC(func) func
+#else
+static void al_serdes_hssp_stub_func(void)
+{
+ al_err("%s: not implemented service called!\n", __func__);
+}
-/**
- * Prototypes for _lane_ compatibility
- */
-int al_serdes_lane_read(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t *data);
-
-int al_serdes_lane_write(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t data);
-
+#define AL_SRDS_ADV_SRVC(func) ((typeof(func) *)al_serdes_hssp_stub_func)
+#endif
/**
- * SERDES core reg/lane read
+ * SERDES core reg read
*/
static inline uint8_t al_serdes_grp_reg_read(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_reg_page page,
enum al_serdes_reg_type type,
uint16_t offset);
-static inline uint8_t al_serdes_grp_lane_read(
- struct al_serdes_group_info *grp_info,
- enum al_serdes_lane page,
- enum al_serdes_reg_type type,
- uint16_t offset);
-
/**
- * SERDES core reg/lane write
+ * SERDES core reg write
*/
static inline void al_serdes_grp_reg_write(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_reg_page page,
enum al_serdes_reg_type type,
uint16_t offset,
uint8_t data);
-static inline void al_serdes_grp_lane_write(
- struct al_serdes_group_info *grp_info,
- enum al_serdes_lane lane,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t data);
-
/**
- * SERDES core masked reg/lane write
+ * SERDES core masked reg write
*/
static inline void al_serdes_grp_reg_masked_write(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_reg_page page,
enum al_serdes_reg_type type,
uint16_t offset,
@@ -135,95 +111,63 @@ static inline void al_serdes_grp_reg_masked_write(
* Lane Rx rate change software flow disable
*/
static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane);
/**
* Group Rx rate change software flow enable if all conditions met
*/
static void al_serdes_group_rx_rate_change_sw_flow_dis(
- struct al_serdes_group_info *grp_info);
+ struct al_serdes_grp_obj *obj);
/**
* Lane Rx rate change software flow enable if all conditions met
*/
static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane);
/**
* Group Rx rate change software flow enable if all conditions met
*/
static void al_serdes_group_rx_rate_change_sw_flow_en_cond(
- struct al_serdes_group_info *grp_info);
-
-
-static inline void al_serdes_grp_lane_masked_write(
- struct al_serdes_group_info *grp_info,
- enum al_serdes_lane lane,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t mask,
- uint8_t data);
+ struct al_serdes_grp_obj *obj);
/******************************************************************************/
/******************************************************************************/
-int al_serdes_handle_init(
- void __iomem *serdes_regs_base,
- struct al_serdes_obj *obj)
+static enum al_serdes_type al_serdes_hssp_type_get(void)
{
- int i;
-
- al_dbg(
- "%s(%p, %p)\n",
- __func__,
- serdes_regs_base,
- obj);
-
- al_assert(serdes_regs_base);
-
- for (i = 0; i < AL_SRDS_NUM_GROUPS; i++) {
- obj->grp_info[i].pobj = obj;
-
- obj->grp_info[i].regs_base =
- &((struct al_serdes_regs *)serdes_regs_base)[i];
- }
-
- return 0;
+ return AL_SRDS_TYPE_HSSP;
}
/******************************************************************************/
/******************************************************************************/
-int al_serdes_reg_read(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_reg_page page,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t *data)
+static int al_serdes_reg_read(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_reg_page page,
+ enum al_serdes_reg_type type,
+ uint16_t offset,
+ uint8_t *data)
{
int status = 0;
al_dbg(
- "%s(%p, %d, %d, %d, %u)\n",
+ "%s(%p, %d, %d, %u)\n",
__func__,
obj,
- grp,
page,
type,
offset);
al_assert(obj);
al_assert(data);
- al_assert(((int)grp) >= AL_SRDS_GRP_A);
- al_assert(((int)grp) <= AL_SRDS_GRP_D);
al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
al_assert(((int)page) <= AL_SRDS_REG_PAGE_4_COMMON);
al_assert(((int)type) >= AL_SRDS_REG_TYPE_PMA);
al_assert(((int)type) <= AL_SRDS_REG_TYPE_PCS);
*data = al_serdes_grp_reg_read(
- &obj->grp_info[grp],
+ obj,
page,
type,
offset);
@@ -236,49 +180,34 @@ int al_serdes_reg_read(
return status;
}
-int al_serdes_lane_read(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t *data)
-{
- return al_serdes_reg_read(obj, grp, (enum al_serdes_reg_page)lane, type,
- offset, data);
-}
/******************************************************************************/
/******************************************************************************/
-int al_serdes_reg_write(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_reg_page page,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t data)
+static int al_serdes_reg_write(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_reg_page page,
+ enum al_serdes_reg_type type,
+ uint16_t offset,
+ uint8_t data)
{
int status = 0;
al_dbg(
- "%s(%p, %d, %d, %d, %u, %u)\n",
+ "%s(%p, %d, %d, %u, %u)\n",
__func__,
obj,
- grp,
page,
type,
offset,
data);
al_assert(obj);
- al_assert(((int)grp) >= AL_SRDS_GRP_A);
- al_assert(((int)grp) <= AL_SRDS_GRP_D);
al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
al_assert(((int)page) <= AL_SRDS_REG_PAGE_0123_LANES_0123);
al_assert(((int)type) >= AL_SRDS_REG_TYPE_PMA);
al_assert(((int)type) <= AL_SRDS_REG_TYPE_PCS);
al_serdes_grp_reg_write(
- &obj->grp_info[grp],
+ obj,
page,
type,
offset,
@@ -287,17 +216,6 @@ int al_serdes_reg_write(
return status;
}
-int al_serdes_lane_write(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t data)
-{
- return al_serdes_reg_write(obj, grp, (enum al_serdes_reg_page)lane,
- type, offset, data);
-}
/******************************************************************************/
/******************************************************************************/
#if (SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM != SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM)
@@ -330,12 +248,10 @@ int al_serdes_lane_write(
#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM)
#error "Wrong assumption!"
#endif
-void al_serdes_bist_overrides_enable(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_rate rate)
+static void al_serdes_bist_overrides_enable(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_rate rate)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
int i;
uint8_t rx_rate_val;
@@ -367,7 +283,7 @@ void al_serdes_bist_overrides_enable(
for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM,
@@ -377,7 +293,7 @@ void al_serdes_bist_overrides_enable(
SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM,
@@ -387,7 +303,7 @@ void al_serdes_bist_overrides_enable(
}
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
@@ -398,7 +314,7 @@ void al_serdes_bist_overrides_enable(
0);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
@@ -409,7 +325,7 @@ void al_serdes_bist_overrides_enable(
0);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM,
@@ -417,7 +333,7 @@ void al_serdes_bist_overrides_enable(
0);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM,
@@ -426,7 +342,7 @@ void al_serdes_bist_overrides_enable(
for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM,
@@ -439,7 +355,7 @@ void al_serdes_bist_overrides_enable(
0);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM,
@@ -447,7 +363,7 @@ void al_serdes_bist_overrides_enable(
0);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
@@ -455,7 +371,7 @@ void al_serdes_bist_overrides_enable(
0);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
@@ -466,15 +382,13 @@ void al_serdes_bist_overrides_enable(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_bist_overrides_disable(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp)
+static void al_serdes_bist_overrides_disable(
+ struct al_serdes_grp_obj *obj)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
int i;
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
@@ -483,7 +397,7 @@ void al_serdes_bist_overrides_disable(
for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM,
@@ -493,7 +407,7 @@ void al_serdes_bist_overrides_disable(
SERDES_IREG_FLD_PCSRXBIST_LOCWREN);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM,
@@ -504,12 +418,10 @@ void al_serdes_bist_overrides_disable(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_rx_rate_change(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_rate rate)
+static void al_serdes_rx_rate_change(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_rate rate)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
int i;
uint8_t rx_rate_val;
@@ -535,7 +447,7 @@ void al_serdes_rx_rate_change(
for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM,
@@ -546,13 +458,10 @@ void al_serdes_rx_rate_change(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_group_pm_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_pm pm)
+static void al_serdes_group_pm_set(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_pm pm)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
uint8_t pm_val;
switch (pm) {
@@ -578,10 +487,10 @@ void al_serdes_group_pm_set(
}
if (pm == AL_SRDS_PM_PD)
- al_serdes_group_rx_rate_change_sw_flow_dis(grp_info);
+ al_serdes_group_rx_rate_change_sw_flow_dis(obj);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM,
@@ -589,46 +498,41 @@ void al_serdes_group_pm_set(
pm_val);
if (pm != AL_SRDS_PM_PD)
- al_serdes_group_rx_rate_change_sw_flow_en_cond(grp_info);
+ al_serdes_group_rx_rate_change_sw_flow_en_cond(obj);
}
/******************************************************************************/
/******************************************************************************/
-void al_serdes_lane_rx_rate_change_sw_flow_en(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
+static void al_serdes_lane_rx_rate_change_sw_flow_en(
+ struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane)
{
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 203, 0xff);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 204, 0xff);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0xff);
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc);
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff);
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 203, 0xff);
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 204, 0xff);
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f);
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 205, 0xff);
}
/******************************************************************************/
/******************************************************************************/
-void al_serdes_lane_rx_rate_change_sw_flow_dis(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane)
+static void al_serdes_lane_rx_rate_change_sw_flow_dis(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
{
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f);
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f);
}
/******************************************************************************/
/******************************************************************************/
-void al_serdes_lane_pcie_rate_override_enable_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
+static void al_serdes_lane_pcie_rate_override_enable_set(
+ struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane,
al_bool en)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PCS,
SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM,
@@ -638,16 +542,13 @@ void al_serdes_lane_pcie_rate_override_enable_set(
/******************************************************************************/
/******************************************************************************/
-al_bool al_serdes_lane_pcie_rate_override_is_enabled(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
+static al_bool al_serdes_lane_pcie_rate_override_is_enabled(
+ struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
- return (al_serdes_grp_lane_read(
- grp_info,
- lane,
+ return (al_serdes_grp_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PCS,
SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM) &
SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA) ? AL_TRUE : AL_FALSE;
@@ -655,15 +556,12 @@ al_bool al_serdes_lane_pcie_rate_override_is_enabled(
/******************************************************************************/
/******************************************************************************/
-enum al_serdes_pcie_rate al_serdes_lane_pcie_rate_get(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane)
+static enum al_serdes_pcie_rate al_serdes_lane_pcie_rate_get(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
return (al_serdes_grp_reg_read(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PCS,
SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM) &
@@ -673,16 +571,13 @@ enum al_serdes_pcie_rate al_serdes_lane_pcie_rate_get(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_lane_pcie_rate_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
+static void al_serdes_lane_pcie_rate_set(
+ struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane,
enum al_serdes_pcie_rate rate)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PCS,
SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM,
@@ -692,15 +587,12 @@ void al_serdes_lane_pcie_rate_set(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_lane_pm_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_pm rx_pm,
- enum al_serdes_pm tx_pm)
+static void al_serdes_lane_pm_set(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ enum al_serdes_pm rx_pm,
+ enum al_serdes_pm tx_pm)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
uint8_t rx_pm_val;
uint8_t tx_pm_val;
@@ -749,10 +641,10 @@ void al_serdes_lane_pm_set(
}
if (rx_pm == AL_SRDS_PM_PD)
- _al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
+ _al_serdes_lane_rx_rate_change_sw_flow_dis(obj, lane);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM,
@@ -760,7 +652,7 @@ void al_serdes_lane_pm_set(
rx_pm_val);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM,
@@ -768,24 +660,21 @@ void al_serdes_lane_pm_set(
tx_pm_val);
if (rx_pm != AL_SRDS_PM_PD)
- _al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
+ _al_serdes_lane_rx_rate_change_sw_flow_en_cond(obj, lane);
}
/******************************************************************************/
/******************************************************************************/
-void al_serdes_pma_hard_reset_group(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- al_bool enable)
+static void al_serdes_pma_hard_reset_group(
+ struct al_serdes_grp_obj *obj,
+ al_bool enable)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
if (enable)
- al_serdes_group_rx_rate_change_sw_flow_dis(grp_info);
+ al_serdes_group_rx_rate_change_sw_flow_dis(obj);
/* Enable Hard Reset Override */
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM,
@@ -794,7 +683,7 @@ void al_serdes_pma_hard_reset_group(
/* Assert/Deassert Hard Reset Override */
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM,
@@ -804,25 +693,22 @@ void al_serdes_pma_hard_reset_group(
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT);
if (!enable)
- al_serdes_group_rx_rate_change_sw_flow_en_cond(grp_info);
+ al_serdes_group_rx_rate_change_sw_flow_en_cond(obj);
}
/******************************************************************************/
/******************************************************************************/
-void al_serdes_pma_hard_reset_lane(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool enable)
+static void al_serdes_pma_hard_reset_lane(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ al_bool enable)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
if (enable)
- _al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
+ _al_serdes_lane_rx_rate_change_sw_flow_dis(obj, lane);
/* Enable Hard Reset Override */
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM,
@@ -831,7 +717,7 @@ void al_serdes_pma_hard_reset_lane(
/* Assert/Deassert Hard Reset Override */
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM,
@@ -841,7 +727,7 @@ void al_serdes_pma_hard_reset_lane(
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT);
if (!enable)
- _al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
+ _al_serdes_lane_rx_rate_change_sw_flow_en_cond(obj, lane);
}
/******************************************************************************/
@@ -857,13 +743,11 @@ void al_serdes_pma_hard_reset_lane(
#error Wrong assumption
#endif
-void al_serdes_loopback_control(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_lb_mode mode)
+static void al_serdes_loopback_control(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ enum al_serdes_lb_mode mode)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
uint8_t val = 0;
switch (mode) {
@@ -888,7 +772,7 @@ void al_serdes_loopback_control(
}
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM,
@@ -902,13 +786,11 @@ void al_serdes_loopback_control(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_bist_pattern_select(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
+static void al_serdes_bist_pattern_select(
+ struct al_serdes_grp_obj *obj,
enum al_serdes_bist_pattern pattern,
uint8_t *user_data)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
uint8_t val = 0;
switch (pattern) {
@@ -938,7 +820,7 @@ void al_serdes_bist_pattern_select(
for (i = 0; i < SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES; i++)
al_serdes_grp_reg_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(i),
@@ -946,7 +828,7 @@ void al_serdes_bist_pattern_select(
}
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM,
@@ -956,16 +838,13 @@ void al_serdes_bist_pattern_select(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_bist_tx_enable(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool enable)
+static void al_serdes_bist_tx_enable(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ al_bool enable)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM,
@@ -975,14 +854,11 @@ void al_serdes_bist_tx_enable(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_bist_tx_err_inject(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp)
+static void al_serdes_bist_tx_err_inject(
+ struct al_serdes_grp_obj *obj)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM,
@@ -990,7 +866,7 @@ void al_serdes_bist_tx_err_inject(
SERDES_IREG_FLD_TXBIST_BITERROR_EN);
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM,
@@ -1000,16 +876,13 @@ void al_serdes_bist_tx_err_inject(
/******************************************************************************/
/******************************************************************************/
-void al_serdes_bist_rx_enable(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool enable)
+static void al_serdes_bist_rx_enable(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ al_bool enable)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM,
@@ -1024,33 +897,31 @@ void al_serdes_bist_rx_enable(
#error Wrong assumption
#endif
-void al_serdes_bist_rx_status(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool *is_locked,
- al_bool *err_cnt_overflow,
- uint16_t *err_cnt)
+static void al_serdes_bist_rx_status(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ al_bool *is_locked,
+ al_bool *err_cnt_overflow,
+ uint32_t *err_cnt)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
uint8_t status_reg_val;
uint16_t err_cnt_msb_reg_val;
uint16_t err_cnt_lsb_reg_val;
status_reg_val = al_serdes_grp_reg_read(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM);
err_cnt_msb_reg_val = al_serdes_grp_reg_read(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM);
err_cnt_lsb_reg_val = al_serdes_grp_reg_read(
- grp_info,
+ obj,
(enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM);
@@ -1069,54 +940,36 @@ void al_serdes_bist_rx_status(
/******************************************************************************/
/******************************************************************************/
static inline uint8_t al_serdes_grp_reg_read(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_reg_page page,
enum al_serdes_reg_type type,
uint16_t offset)
{
+ struct al_serdes_regs __iomem *regs_base = obj->regs_base;
+
al_reg_write32(
- &grp_info->regs_base->gen.reg_addr,
+ &regs_base->gen.reg_addr,
SRDS_CORE_REG_ADDR(page, type, offset));
- return al_reg_read32(&grp_info->regs_base->gen.reg_data);
-}
-
-static inline uint8_t al_serdes_grp_lane_read(
- struct al_serdes_group_info *grp_info,
- enum al_serdes_lane page,
- enum al_serdes_reg_type type,
- uint16_t offset)
-{
- return al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)page,
- type, offset);
+ return al_reg_read32(&regs_base->gen.reg_data);
}
/******************************************************************************/
/******************************************************************************/
static inline void al_serdes_grp_reg_write(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_reg_page page,
enum al_serdes_reg_type type,
uint16_t offset,
uint8_t data)
{
+ struct al_serdes_regs __iomem *regs_base = obj->regs_base;
+
al_reg_write32(
- &grp_info->regs_base->gen.reg_addr,
+ &regs_base->gen.reg_addr,
SRDS_CORE_REG_ADDR(page, type, offset));
- al_reg_write32(&grp_info->regs_base->gen.reg_data, data);
-}
-
-
-static inline void al_serdes_grp_lane_write(
- struct al_serdes_group_info *grp_info,
- enum al_serdes_lane lane,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t data)
-{
- al_serdes_grp_reg_write(grp_info, (enum al_serdes_reg_page)lane,
- type, offset, data);
+ al_reg_write32(&regs_base->gen.reg_data, data);
}
/******************************************************************************/
@@ -1129,7 +982,7 @@ static inline void al_serdes_ns_delay(int cnt)
/******************************************************************************/
/******************************************************************************/
static inline void al_serdes_grp_reg_masked_write(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_reg_page page,
enum al_serdes_reg_type type,
uint16_t offset,
@@ -1146,30 +999,18 @@ static inline void al_serdes_grp_reg_masked_write(
end_page = AL_SRDS_REG_PAGE_3_LANE_3;
}
- for(iter_page = start_page; iter_page <= end_page; ++iter_page) {
- val = al_serdes_grp_reg_read(grp_info, iter_page, type, offset);
+ for (iter_page = start_page; iter_page <= end_page; ++iter_page) {
+ val = al_serdes_grp_reg_read(obj, iter_page, type, offset);
val &= ~mask;
val |= data;
- al_serdes_grp_reg_write(grp_info, iter_page, type, offset, val);
+ al_serdes_grp_reg_write(obj, iter_page, type, offset, val);
}
}
-static inline void al_serdes_grp_lane_masked_write(
- struct al_serdes_group_info *grp_info,
- enum al_serdes_lane lane,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t mask,
- uint8_t data)
-{
- al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
- type, offset, mask, data);
-}
-
/******************************************************************************/
/******************************************************************************/
static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane)
{
al_bool lane_sw_flow_enabled;
@@ -1177,15 +1018,15 @@ static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
al_assert(lane != AL_SRDS_LANES_0123);
lane_sw_flow_enabled =
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 201) == 0xfc) &&
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 202) == 0xff) &&
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 203) == 0xff) &&
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 204) == 0xff) &&
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 205) == 0xff);
/**
@@ -1194,7 +1035,7 @@ static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
*/
if (lane_sw_flow_enabled) {
al_dbg("%s(%d): actually disabling\n", __func__, lane);
- al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
+ al_serdes_grp_reg_masked_write(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 205, 0x80, 0x00);
}
}
@@ -1202,18 +1043,18 @@ static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
/******************************************************************************/
/******************************************************************************/
static void al_serdes_group_rx_rate_change_sw_flow_dis(
- struct al_serdes_group_info *grp_info)
+ struct al_serdes_grp_obj *obj)
{
int lane;
for (lane = AL_SRDS_LANE_0; lane < AL_SRDS_NUM_LANES; lane++)
- _al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
+ _al_serdes_lane_rx_rate_change_sw_flow_dis(obj, lane);
}
/******************************************************************************/
/******************************************************************************/
static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane)
{
al_bool lane_sw_flow_almost_enabled;
@@ -1225,51 +1066,51 @@ static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
al_assert(lane != AL_SRDS_LANES_0123);
lane_sw_flow_almost_enabled =
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 201) == 0xfc) &&
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 202) == 0xff) &&
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 203) == 0xff) &&
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 204) == 0xff) &&
- (al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+ (al_serdes_grp_reg_read(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 205) == 0x7f);
group_reset_enabled =
((al_serdes_grp_reg_read(
- grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM) &
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK) ==
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS) &&
((al_serdes_grp_reg_read(
- grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM) &
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK) ==
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT);
lane_reset_enabled =
((al_serdes_grp_reg_read(
- grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
+ obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM) &
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK) ==
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS) &&
((al_serdes_grp_reg_read(
- grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
+ obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM) &
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK) ==
SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT);
group_pd_enabled =
(al_serdes_grp_reg_read(
- grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM) &
SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK) ==
SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD;
lane_pd_enabled =
(al_serdes_grp_reg_read(
- grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
+ obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM) &
SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK) ==
SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD;
@@ -1283,7 +1124,7 @@ static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
al_dbg("%s(%d): actually enabling\n", __func__, lane);
al_serdes_ns_delay(500);
- al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
+ al_serdes_grp_reg_masked_write(obj, (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA, 205, 0x80, 0x80);
}
}
@@ -1291,33 +1132,34 @@ static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
/******************************************************************************/
/******************************************************************************/
static void al_serdes_group_rx_rate_change_sw_flow_en_cond(
- struct al_serdes_group_info *grp_info)
+ struct al_serdes_grp_obj *obj)
{
int lane;
for (lane = AL_SRDS_LANE_0; lane < AL_SRDS_NUM_LANES; lane++)
- _al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
+ _al_serdes_lane_rx_rate_change_sw_flow_en_cond(obj, lane);
}
/******************************************************************************/
/******************************************************************************/
-int al_serdes_eye_measure_run(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- uint32_t timeout,
- unsigned int *value)
+static int al_serdes_eye_measure_run(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ uint32_t timeout,
+ unsigned int *value)
{
+ struct al_serdes_grp_obj *grp_obj = obj;
+ struct al_serdes_regs __iomem *regs_base = grp_obj->regs_base;
uint32_t reg = 0;
uint32_t i;
struct serdes_lane *lane_regs;
- lane_regs = &obj->grp_info[grp].regs_base->lane[lane];
+ lane_regs = &regs_base->lane[lane];
al_reg_write32(&lane_regs->ictl_multi_rxeq,
SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A);
- for (i = 0 ; i < timeout ; i++) {
+ for (i = 0; i < timeout; i++) {
reg = al_reg_read32(&lane_regs->octl_multi);
if (reg & SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A)
@@ -1340,83 +1182,77 @@ int al_serdes_eye_measure_run(
/******************************************************************************/
/******************************************************************************/
-int al_serdes_eye_diag_sample(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- unsigned int x,
- int y,
- unsigned int timeout,
- unsigned int *value)
+static int al_serdes_eye_diag_sample(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ unsigned int x,
+ int y,
+ unsigned int timeout,
+ unsigned int *value)
{
enum al_serdes_reg_page page = (enum al_serdes_reg_page)lane;
- struct al_serdes_group_info *grp_info;
uint32_t i;
uint8_t sample_count_orig_msb;
uint8_t sample_count_orig_lsb;
al_assert(obj);
- al_assert(((int)grp) >= AL_SRDS_GRP_A);
- al_assert(((int)grp) <= AL_SRDS_GRP_D);
al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
al_assert(((int)page) <= AL_SRDS_REG_PAGE_0123_LANES_0123);
- grp_info = &obj->grp_info[grp];
-
/* Obtain sample count by reading RXCALROAMEYEMEAS_COUNT */
- sample_count_orig_msb = al_serdes_grp_reg_read(grp_info,
+ sample_count_orig_msb = al_serdes_grp_reg_read(obj,
AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM);
- sample_count_orig_lsb = al_serdes_grp_reg_read(grp_info,
+ sample_count_orig_lsb = al_serdes_grp_reg_read(obj,
AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM);
/* Set sample count to ~100000 samples */
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM, 0x13);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM, 0x88);
/* BER Contour Overwrite */
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
0);
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN,
0);
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
0);
/* RXROAM_XORBITSEL = 0x1 or 0x0 */
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
SERDES_IREG_FLD_RXROAM_XORBITSEL,
SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND);
/* Set X */
- al_serdes_grp_reg_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM, x);
/* Set Y */
- al_serdes_grp_reg_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM,
y < 32 ? 31 - y : y + 1);
/* Start Measurement by setting RXCALROAMEYEMEASIN_CYCLEEN = 0x1 */
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START);
/* Check RXCALROAMEYEMEASDONE Signal (Polling Until 0x1) */
- for (i = 0 ; i < timeout ; i++) {
- if (al_serdes_grp_reg_read(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ for (i = 0; i < timeout; i++) {
+ if (al_serdes_grp_reg_read(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM) &
SERDES_IREG_FLD_RXCALROAMEYEMEASDONE)
break;
@@ -1428,38 +1264,38 @@ int al_serdes_eye_diag_sample(
}
/* Stop Measurement by setting RXCALROAMEYEMEASIN_CYCLEEN = 0x0 */
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START,
0);
/* Obtain Error Counts by reading RXCALROAMEYEMEAS_ACC */
- *value = ((unsigned int)al_serdes_grp_reg_read(grp_info, page,
+ *value = ((unsigned int)al_serdes_grp_reg_read(obj, page,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM)) << 8 |
- al_serdes_grp_reg_read(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_read(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM);
/* BER Contour Overwrite */
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN);
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN,
SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN);
- al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_grp_reg_masked_write(obj, page, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN);
/* Restore sample count */
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM,
sample_count_orig_msb);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM,
sample_count_orig_lsb);
@@ -1470,33 +1306,32 @@ int al_serdes_eye_diag_sample(
/******************************************************************************/
/******************************************************************************/
static void al_serdes_tx_deemph_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- uint32_t c_zero,
- uint32_t c_plus_1,
- uint32_t c_minus_1)
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ uint32_t c_zero,
+ uint32_t c_plus_1,
+ uint32_t c_minus_1)
{
- al_serdes_grp_lane_masked_write(
- &obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_1_REG_NUM,
SERDES_IREG_TX_DRV_1_LEVN_MASK,
((c_zero + c_plus_1 + c_minus_1)
<< SERDES_IREG_TX_DRV_1_LEVN_SHIFT));
- al_serdes_grp_lane_masked_write(
- &obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_2_REG_NUM,
SERDES_IREG_TX_DRV_2_LEVNM1_MASK,
(c_plus_1 << SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT));
- al_serdes_grp_lane_masked_write(
- &obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_3_REG_NUM,
SERDES_IREG_TX_DRV_3_LEVNP1_MASK,
@@ -1504,36 +1339,35 @@ static void al_serdes_tx_deemph_set(
}
static void al_serdes_tx_deemph_get(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- uint32_t *c_zero,
- uint32_t *c_plus_1,
- uint32_t *c_minus_1)
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ uint32_t *c_zero,
+ uint32_t *c_plus_1,
+ uint32_t *c_minus_1)
{
uint32_t reg = 0;
- reg = al_serdes_grp_lane_read(
- &obj->grp_info[grp],
- lane,
+ reg = al_serdes_grp_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_2_REG_NUM);
*c_plus_1 = ((reg & SERDES_IREG_TX_DRV_2_LEVNM1_MASK) >>
SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT);
- reg = al_serdes_grp_lane_read(
- &obj->grp_info[grp],
- lane,
+ reg = al_serdes_grp_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_3_REG_NUM);
*c_minus_1 = ((reg & SERDES_IREG_TX_DRV_3_LEVNP1_MASK) >>
SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT);
- reg = al_serdes_grp_lane_read(
- &obj->grp_info[grp],
- lane,
+ reg = al_serdes_grp_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_1_REG_NUM);
@@ -1541,18 +1375,17 @@ static void al_serdes_tx_deemph_get(
SERDES_IREG_TX_DRV_1_LEVN_SHIFT) - *c_plus_1 - *c_minus_1);
}
-al_bool al_serdes_tx_deemph_inc(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_tx_deemph_param param)
+static al_bool al_serdes_tx_deemph_inc(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ enum al_serdes_tx_deemph_param param)
{
al_bool ret = AL_TRUE;
uint32_t c0;
uint32_t c1;
uint32_t c_1;
- al_serdes_tx_deemph_get(obj, grp, lane, &c0, &c1, &c_1);
+ al_serdes_tx_deemph_get(obj, lane, &c0, &c1, &c_1);
al_dbg("%s: current txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
__func__, c0, c1, c_1);
@@ -1594,23 +1427,22 @@ al_bool al_serdes_tx_deemph_inc(
al_dbg("%s: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
__func__, c0, c1, c_1);
- al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
+ al_serdes_tx_deemph_set(obj, lane, c0, c1, c_1);
return ret;
}
-al_bool al_serdes_tx_deemph_dec(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_tx_deemph_param param)
+static al_bool al_serdes_tx_deemph_dec(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ enum al_serdes_tx_deemph_param param)
{
al_bool ret = AL_TRUE;
uint32_t c0;
uint32_t c1;
uint32_t c_1;
- al_serdes_tx_deemph_get(obj, grp, lane, &c0, &c1, &c_1);
+ al_serdes_tx_deemph_get(obj, lane, &c0, &c1, &c_1);
al_dbg("%s: current txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
__func__, c0, c1, c_1);
@@ -1645,15 +1477,14 @@ al_bool al_serdes_tx_deemph_dec(
al_dbg("%s: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
__func__, c0, c1, c_1);
- al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
+ al_serdes_tx_deemph_set(obj, lane, c0, c1, c_1);
return ret;
}
-void al_serdes_tx_deemph_preset(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane)
+static void al_serdes_tx_deemph_preset(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
{
uint32_t c0;
uint32_t c1;
@@ -1668,35 +1499,34 @@ void al_serdes_tx_deemph_preset(
al_dbg("preset: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
c0, c1, c_1);
- al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
+ al_serdes_tx_deemph_set(obj, lane, c0, c1, c_1);
}
-al_bool al_serdes_signal_is_detected(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane)
+static al_bool al_serdes_signal_is_detected(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
{
uint32_t reg = 0;
- reg = al_serdes_grp_lane_read(
- &obj->grp_info[grp],
- lane,
+ reg = al_serdes_grp_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXRANDET_REG_NUM);
return ((reg & SERDES_IREG_FLD_RXRANDET_STAT) ? AL_TRUE : AL_FALSE);
}
-void al_serdes_tx_advanced_params_set(struct al_serdes_obj *obj,
- enum al_serdes_group grp,
+static void al_serdes_tx_advanced_params_set(struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane,
- struct al_serdes_adv_tx_params *params)
+ void *tx_params)
{
uint8_t reg = 0;
+ struct al_serdes_adv_tx_params *params = tx_params;
- if(!params->override) {
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ if (!params->override) {
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN,
@@ -1705,8 +1535,8 @@ void al_serdes_tx_advanced_params_set(struct al_serdes_obj *obj,
return;
}
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN,
@@ -1722,8 +1552,8 @@ void al_serdes_tx_advanced_params_set(struct al_serdes_obj *obj,
SERDES_IREG_TX_DRV_1_LEVN_SHIFT,
params->total_driver_units);
- al_serdes_grp_lane_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_1_REG_NUM,
reg);
@@ -1739,8 +1569,8 @@ void al_serdes_tx_advanced_params_set(struct al_serdes_obj *obj,
SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT,
params->c_plus_2);
- al_serdes_grp_lane_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_2_REG_NUM,
reg);
@@ -1756,63 +1586,67 @@ void al_serdes_tx_advanced_params_set(struct al_serdes_obj *obj,
SERDES_IREG_TX_DRV_3_SLEW_SHIFT,
params->slew_rate);
- al_serdes_grp_lane_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_3_REG_NUM,
reg);
}
-void al_serdes_tx_advanced_params_get(struct al_serdes_obj *obj,
- enum al_serdes_group grp,
+static void al_serdes_tx_advanced_params_get(struct al_serdes_grp_obj *obj,
enum al_serdes_lane lane,
- struct al_serdes_adv_tx_params *tx_params)
+ void *tx_params)
{
+ struct al_serdes_adv_tx_params *params = tx_params;
uint8_t reg_val = 0;
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_1_REG_NUM,
&reg_val);
- tx_params->amp = (reg_val & SERDES_IREG_TX_DRV_1_HLEV_MASK) >>
+ params->amp = (reg_val & SERDES_IREG_TX_DRV_1_HLEV_MASK) >>
SERDES_IREG_TX_DRV_1_HLEV_SHIFT;
- tx_params->total_driver_units = (reg_val &
+ params->total_driver_units = (reg_val &
SERDES_IREG_TX_DRV_1_LEVN_MASK) >>
SERDES_IREG_TX_DRV_1_LEVN_SHIFT;
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_2_REG_NUM,
&reg_val);
- tx_params->c_plus_1 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM1_MASK) >>
+ params->c_plus_1 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM1_MASK) >>
SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT;
- tx_params->c_plus_2 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM2_MASK) >>
+ params->c_plus_2 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM2_MASK) >>
SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT;
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_TX_DRV_3_REG_NUM,
&reg_val);
- tx_params->c_minus_1 = (reg_val & SERDES_IREG_TX_DRV_3_LEVNP1_MASK) >>
+ params->c_minus_1 = (reg_val & SERDES_IREG_TX_DRV_3_LEVNP1_MASK) >>
SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT;
- tx_params->slew_rate = (reg_val & SERDES_IREG_TX_DRV_3_SLEW_MASK) >>
+ params->slew_rate = (reg_val & SERDES_IREG_TX_DRV_3_SLEW_MASK) >>
SERDES_IREG_TX_DRV_3_SLEW_SHIFT;
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
&reg_val);
- tx_params->override = ((reg_val & SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN) == 0);
+ params->override = ((reg_val & SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN) == 0);
}
-void al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- struct al_serdes_adv_rx_params *params)
+static void al_serdes_rx_advanced_params_set(struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ void *rx_params)
{
+ struct al_serdes_adv_rx_params *params = rx_params;
uint8_t reg = 0;
- if(!params->override) {
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ if (!params->override) {
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN,
@@ -1821,8 +1655,8 @@ void al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj,
return;
}
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN,
@@ -1838,8 +1672,8 @@ void al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj,
SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT,
params->dfe_3db_freq);
- al_serdes_grp_lane_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_1_REG_NUM,
reg);
@@ -1855,8 +1689,8 @@ void al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj,
SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT,
params->dfe_first_tap_ctrl);
- al_serdes_grp_lane_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_2_REG_NUM,
reg);
@@ -1872,8 +1706,8 @@ void al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj,
SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT,
params->dfe_third_tap_ctrl);
- al_serdes_grp_lane_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_3_REG_NUM,
reg);
@@ -1889,8 +1723,8 @@ void al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj,
SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT,
params->low_freq_agc_gain);
- al_serdes_grp_lane_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_4_REG_NUM,
reg);
@@ -1906,17 +1740,17 @@ void al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj,
SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT,
params->high_freq_agc_boost);
- al_serdes_grp_lane_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_5_REG_NUM,
reg);
}
-static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_info)
+static inline void al_serdes_common_cfg_eth(struct al_serdes_grp_obj *obj)
{
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM,
@@ -1924,7 +1758,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0x1 << SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM,
@@ -1932,7 +1766,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0 << SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM,
@@ -1940,7 +1774,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0x2 << SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM,
@@ -1948,7 +1782,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0 << SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM,
@@ -1956,7 +1790,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0x1 << SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM,
@@ -1964,7 +1798,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0x1 << SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM,
@@ -1972,7 +1806,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0xf0 << SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM,
@@ -1980,7 +1814,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0 << SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM,
@@ -1988,7 +1822,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(1 << SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM,
@@ -1996,7 +1830,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0x8 << SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM,
@@ -2004,7 +1838,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM,
@@ -2012,7 +1846,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0x64 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
@@ -2020,7 +1854,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0x3 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
@@ -2028,7 +1862,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0x1 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
@@ -2036,7 +1870,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(3 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
@@ -2044,7 +1878,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(1 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM,
@@ -2052,7 +1886,7 @@ static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_inf
(0xc << SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT));
al_serdes_grp_reg_masked_write(
- grp_info,
+ obj,
AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM,
@@ -2068,23 +1902,25 @@ struct al_serdes_mode_rx_tx_inv_state {
};
static void al_serdes_mode_rx_tx_inv_state_save(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
struct al_serdes_mode_rx_tx_inv_state *state)
{
- if (al_reg_read32(&grp_info->regs_base->gen.irst) & SERDES_GEN_IRST_POR_B_A) {
+ struct al_serdes_regs __iomem *regs_base = obj->regs_base;
+
+ if (al_reg_read32(&regs_base->gen.irst) & SERDES_GEN_IRST_POR_B_A) {
int i;
state->restore = AL_TRUE;
- state->pipe_rst = al_reg_read32(&grp_info->regs_base->gen.irst);
+ state->pipe_rst = al_reg_read32(&regs_base->gen.irst);
for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
state->inv_value[i] = al_serdes_grp_reg_read(
- grp_info,
+ obj,
i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_POLARITY_RX_REG_NUM);
state->ipd_multi[i] =
- al_reg_read32(&grp_info->regs_base->lane[i].ipd_multi);
+ al_reg_read32(&regs_base->lane[i].ipd_multi);
}
} else {
state->restore = AL_FALSE;
@@ -2092,23 +1928,25 @@ static void al_serdes_mode_rx_tx_inv_state_save(
}
static void al_serdes_mode_rx_tx_inv_state_restore(
- struct al_serdes_group_info *grp_info,
+ struct al_serdes_grp_obj *obj,
struct al_serdes_mode_rx_tx_inv_state *state)
{
+ struct al_serdes_regs __iomem *regs_base = obj->regs_base;
+
if (state->restore) {
int i;
for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
al_serdes_grp_reg_write(
- grp_info,
+ obj,
i,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_POLARITY_RX_REG_NUM,
state->inv_value[i]);
al_reg_write32(
- &grp_info->regs_base->lane[i].ipd_multi, state->ipd_multi[i]);
+ &regs_base->lane[i].ipd_multi, state->ipd_multi[i]);
al_reg_write32_masked(
- &grp_info->regs_base->gen.irst,
+ &regs_base->gen.irst,
(SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL >> i) |
(SERDES_GEN_IRST_PIPE_RST_L0_B_A >> i),
state->pipe_rst);
@@ -2116,543 +1954,539 @@ static void al_serdes_mode_rx_tx_inv_state_restore(
}
}
-void al_serdes_mode_set_sgmii(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp)
+static void al_serdes_mode_set_sgmii(
+ struct al_serdes_grp_obj *obj)
{
- struct al_serdes_group_info *grp_info;
+ struct al_serdes_grp_obj *grp_obj = obj;
+ struct al_serdes_regs __iomem *regs_base = grp_obj->regs_base;
struct al_serdes_mode_rx_tx_inv_state rx_tx_inv_state;
al_assert(obj);
- al_assert(((int)grp) >= AL_SRDS_GRP_A);
- al_assert(((int)grp) <= AL_SRDS_GRP_D);
-
- grp_info = &obj->grp_info[grp];
-
- al_serdes_mode_rx_tx_inv_state_save(grp_info, &rx_tx_inv_state);
-
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
- al_reg_write32(&grp_info->regs_base->lane[0].ictl_multi, 0x10110010);
- al_reg_write32(&grp_info->regs_base->lane[1].ictl_multi, 0x10110010);
- al_reg_write32(&grp_info->regs_base->lane[2].ictl_multi, 0x10110010);
- al_reg_write32(&grp_info->regs_base->lane[3].ictl_multi, 0x10110010);
- al_reg_write32(&grp_info->regs_base->gen.ipd_multi_synth , 0x0001);
- al_reg_write32(&grp_info->regs_base->lane[0].ipd_multi, 0x0003);
- al_reg_write32(&grp_info->regs_base->lane[1].ipd_multi, 0x0003);
- al_reg_write32(&grp_info->regs_base->lane[2].ipd_multi, 0x0003);
- al_reg_write32(&grp_info->regs_base->lane[3].ipd_multi, 0x0003);
- al_reg_write32(&grp_info->regs_base->gen.ictl_pcs , 0);
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
+
+ al_serdes_mode_rx_tx_inv_state_save(grp_obj, &rx_tx_inv_state);
+
+ al_reg_write32(&regs_base->gen.irst, 0x000000);
+ al_reg_write32(&regs_base->lane[0].ictl_multi, 0x10110010);
+ al_reg_write32(&regs_base->lane[1].ictl_multi, 0x10110010);
+ al_reg_write32(&regs_base->lane[2].ictl_multi, 0x10110010);
+ al_reg_write32(&regs_base->lane[3].ictl_multi, 0x10110010);
+ al_reg_write32(&regs_base->gen.ipd_multi_synth , 0x0001);
+ al_reg_write32(&regs_base->lane[0].ipd_multi, 0x0003);
+ al_reg_write32(&regs_base->lane[1].ipd_multi, 0x0003);
+ al_reg_write32(&regs_base->lane[2].ipd_multi, 0x0003);
+ al_reg_write32(&regs_base->lane[3].ipd_multi, 0x0003);
+ al_reg_write32(&regs_base->gen.ictl_pcs , 0);
+ al_reg_write32(&regs_base->gen.irst, 0x001000);
al_serdes_ns_delay(800);
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
+ al_reg_write32(&regs_base->gen.irst, 0x000000);
al_serdes_ns_delay(500);
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
+ al_reg_write32(&regs_base->gen.irst, 0x001000);
al_serdes_ns_delay(500);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 101, 183);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 102, 183);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 103, 12);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 104, 12);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 105, 26);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 106, 26);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 107, 2);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 108, 2);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 109, 17);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 110, 13);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 101, 153);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 102, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 103, 108);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 104, 183);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 105, 183);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 106, 12);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 107, 12);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 108, 26);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 109, 26);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 110, 7);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 111, 12);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 112, 8);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 113, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 114, 8);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 115, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 116, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 117, 179);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 118, 246);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 119, 208);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 120, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 121, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 122, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 123, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 124, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 125, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 126, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 127, 211);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 128, 211);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 129, 226);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 130, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 131, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 132, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 133, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 134, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 135, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 136, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 137, 211);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 138, 211);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 139, 226);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 140, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 141, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 142, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 143, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 144, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 145, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 146, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 147, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 148, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 149, 63);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 150, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 151, 100);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 152, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 153, 4);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 154, 2);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 155, 5);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 156, 5);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 157, 4);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 158, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 159, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 160, 8);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 161, 4);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 162, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 163, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 164, 4);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0_LANE_0,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0_LANE_0,
AL_SRDS_REG_TYPE_PMA, 7, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_1_LANE_1,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_1_LANE_1,
AL_SRDS_REG_TYPE_PMA, 7, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_2_LANE_2,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_2_LANE_2,
AL_SRDS_REG_TYPE_PMA, 7, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_3_LANE_3,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_3_LANE_3,
AL_SRDS_REG_TYPE_PMA, 7, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 13, 16);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 48, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 49, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 54, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 55, 180);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 93, 2);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 165, 3);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 41, 6);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 354, 3);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 355, 58);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 356, 9);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 357, 3);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 358, 62);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 359, 12);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 701, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 87, 0x1f);
- al_serdes_common_cfg_eth(grp_info);
+ al_serdes_common_cfg_eth(obj);
- al_serdes_mode_rx_tx_inv_state_restore(grp_info, &rx_tx_inv_state);
+ al_serdes_mode_rx_tx_inv_state_restore(grp_obj, &rx_tx_inv_state);
+ al_reg_write32(&regs_base->gen.irst, 0x0011F0);
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x0011F0);
al_serdes_ns_delay(500);
}
-void al_serdes_mode_set_kr(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp)
+static void al_serdes_mode_set_kr(
+ struct al_serdes_grp_obj *obj)
{
- struct al_serdes_group_info *grp_info;
+ struct al_serdes_grp_obj *grp_obj = obj;
+ struct al_serdes_regs __iomem *regs_base = grp_obj->regs_base;
struct al_serdes_mode_rx_tx_inv_state rx_tx_inv_state;
al_assert(obj);
- al_assert(((int)grp) >= AL_SRDS_GRP_A);
- al_assert(((int)grp) <= AL_SRDS_GRP_D);
-
- grp_info = &obj->grp_info[grp];
-
- al_serdes_mode_rx_tx_inv_state_save(grp_info, &rx_tx_inv_state);
-
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
- al_reg_write32(&grp_info->regs_base->lane[0].ictl_multi, 0x30330030);
- al_reg_write32(&grp_info->regs_base->lane[1].ictl_multi, 0x30330030);
- al_reg_write32(&grp_info->regs_base->lane[2].ictl_multi, 0x30330030);
- al_reg_write32(&grp_info->regs_base->lane[3].ictl_multi, 0x30330030);
- al_reg_write32(&grp_info->regs_base->gen.ipd_multi_synth , 0x0001);
- al_reg_write32(&grp_info->regs_base->lane[0].ipd_multi, 0x0003);
- al_reg_write32(&grp_info->regs_base->lane[1].ipd_multi, 0x0003);
- al_reg_write32(&grp_info->regs_base->lane[2].ipd_multi, 0x0003);
- al_reg_write32(&grp_info->regs_base->lane[3].ipd_multi, 0x0003);
- al_reg_write32(&grp_info->regs_base->gen.ictl_pcs , 0);
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
+ al_serdes_mode_rx_tx_inv_state_save(grp_obj, &rx_tx_inv_state);
+
+ al_reg_write32(&regs_base->gen.irst, 0x000000);
+ al_reg_write32(&regs_base->lane[0].ictl_multi, 0x30330030);
+ al_reg_write32(&regs_base->lane[1].ictl_multi, 0x30330030);
+ al_reg_write32(&regs_base->lane[2].ictl_multi, 0x30330030);
+ al_reg_write32(&regs_base->lane[3].ictl_multi, 0x30330030);
+ al_reg_write32(&regs_base->gen.ipd_multi_synth , 0x0001);
+ al_reg_write32(&regs_base->lane[0].ipd_multi, 0x0003);
+ al_reg_write32(&regs_base->lane[1].ipd_multi, 0x0003);
+ al_reg_write32(&regs_base->lane[2].ipd_multi, 0x0003);
+ al_reg_write32(&regs_base->lane[3].ipd_multi, 0x0003);
+ al_reg_write32(&regs_base->gen.ictl_pcs , 0);
+ al_reg_write32(&regs_base->gen.irst, 0x001000);
al_serdes_ns_delay(800);
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
+ al_reg_write32(&regs_base->gen.irst, 0x000000);
al_serdes_ns_delay(500);
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
+ al_reg_write32(&regs_base->gen.irst, 0x001000);
al_serdes_ns_delay(500);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 101, 189);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 102, 189);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 103, 6);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 104, 6);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 105, 27);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 106, 27);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 107, 1);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 108, 1);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 109, 119);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 110, 5);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 101, 170);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 102, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 103, 108);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 104, 189);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 105, 189);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 106, 6);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 107, 6);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 108, 27);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 109, 27);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 110, 7);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 111, 12);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 112, 16);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 113, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 114, 16);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 115, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 116, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 117, 179);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 118, 246);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 119, 208);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 120, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 121, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 122, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 123, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 124, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 125, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 126, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 127, 211);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 128, 211);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 129, 226);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 130, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 131, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 132, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 133, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 134, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 135, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 136, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 137, 211);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 138, 211);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 139, 226);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 140, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 141, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 142, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 143, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 144, 239);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 145, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 146, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 147, 251);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 148, 255);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 149, 63);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 150, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 151, 50);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 152, 17);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 153, 2);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 154, 1);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 155, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 156, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 157, 4);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 158, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 159, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 160, 8);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 161, 4);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 162, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 163, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 164, 4);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0_LANE_0,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0_LANE_0,
AL_SRDS_REG_TYPE_PMA, 7, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_1_LANE_1,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_1_LANE_1,
AL_SRDS_REG_TYPE_PMA, 7, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_2_LANE_2,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_2_LANE_2,
AL_SRDS_REG_TYPE_PMA, 7, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_3_LANE_3,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_3_LANE_3,
AL_SRDS_REG_TYPE_PMA, 7, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 13, 16);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 48, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 49, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 54, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 55, 149); /*Was 182*/
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 93, 2);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 165, 3);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 41, 6);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 354, 3);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 355, 58);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 356, 9);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 357, 3);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 358, 62);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA, 359, 12);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 701, 0);
- al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+ al_serdes_grp_reg_write(obj, AL_SRDS_REG_PAGE_0123_LANES_0123,
AL_SRDS_REG_TYPE_PMA, 87, 0x1f);
- al_serdes_common_cfg_eth(grp_info);
+ al_serdes_common_cfg_eth(obj);
- al_serdes_mode_rx_tx_inv_state_restore(grp_info, &rx_tx_inv_state);
+ al_serdes_mode_rx_tx_inv_state_restore(grp_obj, &rx_tx_inv_state);
- al_reg_write32(&grp_info->regs_base->gen.irst, 0x0011F0);
+ al_reg_write32(&regs_base->gen.irst, 0x0011F0);
al_serdes_ns_delay(500);
}
-void al_serdes_rx_advanced_params_get(struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- struct al_serdes_adv_rx_params* rx_params)
+static void al_serdes_rx_advanced_params_get(struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ void *rx_params)
{
+ struct al_serdes_adv_rx_params *params = rx_params;
uint8_t temp_val;
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_1_REG_NUM,
&temp_val);
- rx_params->dcgain = (temp_val & SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK) >>
+ params->dcgain = (temp_val & SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK) >>
SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT;
- rx_params->dfe_3db_freq = (temp_val &
+ params->dfe_3db_freq = (temp_val &
SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK) >>
SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT;
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_2_REG_NUM,
&temp_val);
- rx_params->dfe_gain = (temp_val &
+ params->dfe_gain = (temp_val &
SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK) >>
SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT;
- rx_params->dfe_first_tap_ctrl = (temp_val &
+ params->dfe_first_tap_ctrl = (temp_val &
SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK) >>
SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT;
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_3_REG_NUM,
&temp_val);
- rx_params->dfe_secound_tap_ctrl = (temp_val &
+ params->dfe_secound_tap_ctrl = (temp_val &
SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK) >>
SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT;
- rx_params->dfe_third_tap_ctrl = (temp_val &
+ params->dfe_third_tap_ctrl = (temp_val &
SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK) >>
SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT;
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_4_REG_NUM,
&temp_val);
- rx_params->dfe_fourth_tap_ctrl = (temp_val &
+ params->dfe_fourth_tap_ctrl = (temp_val &
SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK) >>
SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT;
- rx_params->low_freq_agc_gain = (temp_val &
+ params->low_freq_agc_gain = (temp_val &
SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK) >>
SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT;
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RX_CALEQ_5_REG_NUM,
&temp_val);
- rx_params->precal_code_sel = (temp_val &
+ params->precal_code_sel = (temp_val &
SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK) >>
SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT;
- rx_params->high_freq_agc_boost = (temp_val &
+ params->high_freq_agc_boost = (temp_val &
SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK) >>
SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT;
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
&temp_val);
- rx_params->override = ((temp_val & SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN) == 0);
+ params->override = ((temp_val & SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN) == 0);
}
-#if ( SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM != \
+#if (SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM != \
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM || \
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM != \
SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM)
#error Wrong assumption
#endif
-int al_serdes_rx_equalization(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane)
+static int al_serdes_rx_equalization(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
{
uint8_t serdes_ireg_fld_rxcalroamyadjust_locwren_val;
uint8_t serdes_ireg_fld_rxroam_xorbitsel_val;
@@ -2667,39 +2501,43 @@ int al_serdes_rx_equalization(
/*
* Make sure Roam Eye mechanism is not overridden
* Lane SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN = 1,
- * so Rx 4-Point Eye process is not overridden
+ * so Rx 4-Point Eye process is not overridden
* Lane SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN = 1,
- * so Eye Roam latch is not overridden
+ * so Eye Roam latch is not overridden
* Lane SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN = 1,
- * so Eye Roam latch 'X adjust' is not overridden
+ * so Eye Roam latch 'X adjust' is not overridden
* Lane SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN = 1,
- * so Eye Roam latch 'Y adjust' is not overridden
+ * so Eye Roam latch 'Y adjust' is not overridden
* Lane SERDES_IREG_FLD_RXROAM_XORBITSEL = 0/1,
- * so Eye Roamlatch works on the right Eye position (XORBITSEL)
- * For most cases 0 is needed, but sometimes 1 is needed.
- * I couldn't sort out why is this so the code uses a global
+ * so Eye Roamlatch works on the right Eye position (XORBITSEL)
+ * For most cases 0 is needed, but sometimes 1 is needed.
+ * I couldn't sort out why is this so the code uses a global
* XORBITSELmode variable, set by the user (GUI). Default is 0.
* control must be internal. At the end we restore original setting
*/
/* save current values for restoring them later in the end */
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
&serdes_ireg_fld_rxcal_locwren_val);
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
- &serdes_ireg_fld_rxcalroamyadjust_locwren_val );
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ &serdes_ireg_fld_rxcalroamyadjust_locwren_val);
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
- &serdes_ireg_fld_rxroam_xorbitsel_val );
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ &serdes_ireg_fld_rxroam_xorbitsel_val);
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
- &serdes_ireg_fld_pcsrxeq_locwren_val );
+ &serdes_ireg_fld_pcsrxeq_locwren_val);
/*
* Set Bits:
@@ -2717,10 +2555,11 @@ int al_serdes_rx_equalization(
temp_val |= SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN;
temp_val |= SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN;
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
- temp_val );
+ temp_val);
/*
* Set bit SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN
@@ -2728,10 +2567,11 @@ int al_serdes_rx_equalization(
*/
temp_val = serdes_ireg_fld_rxcalroamyadjust_locwren_val |
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN;
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
- temp_val );
+ temp_val);
/*
* Clear Bit: SERDES_IREG_FLD_RXROAM_XORBITSEL
@@ -2739,10 +2579,11 @@ int al_serdes_rx_equalization(
*/
temp_val = serdes_ireg_fld_rxroam_xorbitsel_val &
~SERDES_IREG_FLD_RXROAM_XORBITSEL;
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
- temp_val );
+ temp_val);
/*
* Take Control from int.pin over RxEQ process.
@@ -2751,10 +2592,11 @@ int al_serdes_rx_equalization(
*/
temp_val = serdes_ireg_fld_pcsrxeq_locwren_val &
~SERDES_IREG_FLD_PCSRXEQ_LOCWREN;
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
- temp_val );
+ temp_val);
/*
@@ -2762,30 +2604,34 @@ int al_serdes_rx_equalization(
* Clear Bit SERDES_IREG_FLD_PCSRXEQ_START
* to start fresh from Stop
*/
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
- &temp_val );
+ &temp_val);
temp_val &= ~SERDES_IREG_FLD_PCSRXEQ_START;
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
- temp_val );
+ temp_val);
/* Set Bit SERDES_IREG_FLD_PCSRXEQ_START
* to begin Rx Eq Cal */
temp_val |= SERDES_IREG_FLD_PCSRXEQ_START;
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
- temp_val );
+ temp_val);
/* Poll on RxEq Cal completion. SERDES_IREG_FLD_RXEQ_DONE. 1=Done. */
- for( i = 0; i < AL_SERDES_RX_EQUAL_TRIES; ++i ) {
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ for (i = 0; i < AL_SERDES_RX_EQUAL_TRIES; ++i) {
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM,
- &done );
+ &done);
done &= SERDES_IREG_FLD_RXEQ_DONE;
/* Check if RxEQ Cal is done */
@@ -2801,44 +2647,51 @@ int al_serdes_rx_equalization(
/* Stop the RxEQ process. */
temp_val &= ~SERDES_IREG_FLD_PCSRXEQ_START;
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
- temp_val );
+ temp_val);
/* Get score */
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM,
- &temp_val );
- test_score = (int)( (temp_val & 0xFF) << 6 );
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ &temp_val);
+ test_score = (int)((temp_val & 0xFF) << 6);
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM,
- &temp_val );
+ &temp_val);
test_score += (int)(temp_val & SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK);
/* Restore start values */
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
serdes_ireg_fld_rxcal_locwren_val);
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
- serdes_ireg_fld_rxcalroamyadjust_locwren_val );
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ serdes_ireg_fld_rxcalroamyadjust_locwren_val);
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
- serdes_ireg_fld_rxroam_xorbitsel_val );
- al_serdes_lane_write(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ serdes_ireg_fld_rxroam_xorbitsel_val);
+ al_serdes_reg_write(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
- serdes_ireg_fld_pcsrxeq_locwren_val );
+ serdes_ireg_fld_pcsrxeq_locwren_val);
return test_score;
}
-#if ( SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
+#if (SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM || \
SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM || \
@@ -2846,12 +2699,11 @@ int al_serdes_rx_equalization(
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM)
#error Wrong assumption
#endif
-int al_serdes_calc_eye_size(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- int* width,
- int* height)
+static int al_serdes_calc_eye_size(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ int *width,
+ int *height)
{
uint8_t rxcaleyediagfsm_x_y_valweight_val;
uint8_t rxcaleyediagfsm_xvalcoarse_val;
@@ -2868,51 +2720,55 @@ int al_serdes_calc_eye_size(
uint8_t reg_value;
/* Save Registers */
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
&rxlock2ref_locwren_val);
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
&rxcal_locwren_val);
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
&rxcalroamyadjust_locwren_val);
- al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
&rxlock2ref_ovren_val);
- al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_read(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
&rxcaleyediagfsm_x_y_valweight_val);
- al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_read(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
&rxcaleyediagfsm_xvalcoarse_val);
- al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_read(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
&rxcaleyediagfsm_xvalfine_val);
- al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_read(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
&rxcaleyediagfsm_yvalcoarse_val);
- al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_read(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
&rxcaleyediagfsm_yvalfine_val);
/*
* Clear Bit:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN
- * to override RxEQ via PMA
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN
+ * to override RxEQ via PMA
* Set Bits:
- * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
- * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
- * to keep Eye Diag Roam controlled internally
+ * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
+ * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
+ * to keep Eye Diag Roam controlled internally
*/
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN |
@@ -2922,11 +2778,11 @@ int al_serdes_calc_eye_size(
SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN);
/*
* Set Bit:
- * SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN
- * to keep Eye Diag Roam controlled internally
+ * SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN
+ * to keep Eye Diag Roam controlled internally
*/
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
@@ -2934,14 +2790,14 @@ int al_serdes_calc_eye_size(
/*
* Clear Bit:
- * SERDES_IREG_FLD_RXROAM_XORBITSEL,
- * so XORBITSEL=0, needed for the Eye mapping
+ * SERDES_IREG_FLD_RXROAM_XORBITSEL,
+ * so XORBITSEL=0, needed for the Eye mapping
* Set Bit:
* SERDES_IREG_FLD_RXLOCK2REF_OVREN,
* so RXLOCK2REF_OVREN=1, keeping lock to data, preventing data hit
*/
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
SERDES_IREG_FLD_RXLOCK2REF_OVREN |
@@ -2951,11 +2807,11 @@ int al_serdes_calc_eye_size(
/*
* Clear Bit:
- * SERDES_IREG_FLD_RXLOCK2REF_LOCWREN,
- * so RXLOCK2REF_LOCWREN=0, to override control
+ * SERDES_IREG_FLD_RXLOCK2REF_LOCWREN,
+ * so RXLOCK2REF_LOCWREN=0, to override control
*/
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
SERDES_IREG_FLD_RXLOCK2REF_LOCWREN,
@@ -2964,49 +2820,50 @@ int al_serdes_calc_eye_size(
/* Width Calculation */
/* Return Value = 0*Y + 1*X */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
0x01);
/* X coarse scan step = 3 */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
0x03);
/* X fine scan step = 1 */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
0x01);
/* Y coarse scan step = 0 */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
0x00);
/* Y fine scan step = 0 */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
0x00);
/*
* Set Bit:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
- * to start Eye measurement
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+ * to start Eye measurement
*/
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START);
- for( i = 0; i < AL_SERDES_RX_EYE_CAL_TRIES; ++i ) {
+ for(i = 0; i < AL_SERDES_RX_EYE_CAL_TRIES; ++i) {
/* Check if RxEQ Cal is done */
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM,
- &status );
+ &status);
if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)
break;
al_msleep(AL_SERDES_RX_EYE_CAL_MDELAY);
@@ -3023,27 +2880,29 @@ int al_serdes_calc_eye_size(
}
/* Read Eye Opening Metrics, Bits:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB,
- * SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB,
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB
*/
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM,
- &reg_value );
+ &reg_value);
*width = reg_value << 6;
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM,
- &reg_value );
+ &reg_value);
*width =+ reg_value & SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE;
/*
* Clear Bit:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
- * to stop Eye measurement
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+ * to stop Eye measurement
*/
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
@@ -3052,38 +2911,38 @@ int al_serdes_calc_eye_size(
/* Height Calculation */
/* Return Value = 1*Y + 0*X */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
0x10);
/* X coarse scan step = 0 */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
0x00);
/* X fine scan step = 0 */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
0x00);
/* Y coarse scan step = 3 */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
0x03);
/* Y fine scan step = 1 */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
0x01);
/*
* Set Bit:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
- * to start Eye measurement
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+ * to start Eye measurement
*/
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
@@ -3091,8 +2950,9 @@ int al_serdes_calc_eye_size(
for( i = 0; i < AL_SERDES_RX_EYE_CAL_TRIES; ++i ) {
/* Check if RxEQ Cal is done */
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM,
&status );
if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)
@@ -3111,118 +2971,194 @@ int al_serdes_calc_eye_size(
}
/* Read Eye Opening Metrics, Bits:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB,
- * SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB,
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB
*/
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM,
&reg_value );
*height = reg_value << 6;
- al_serdes_lane_read(
- obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_read(
+ obj, (enum al_serdes_reg_page)lane,
+ AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM,
&reg_value );
*height =+ reg_value & SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE;
/*
* Clear Bit:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
- * to stop Eye measurement
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+ * to stop Eye measurement
*/
- al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
- lane,
+ al_serdes_grp_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
0);
/* Restore Registers */
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
rxcaleyediagfsm_x_y_valweight_val);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
rxcaleyediagfsm_xvalcoarse_val);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
rxcaleyediagfsm_xvalfine_val);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
rxcaleyediagfsm_yvalcoarse_val);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON,
AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
rxcaleyediagfsm_yvalfine_val);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
rxlock2ref_locwren_val);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
rxcal_locwren_val);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
rxcalroamyadjust_locwren_val);
- al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
rxlock2ref_ovren_val);
return 0;
}
-void al_serdes_sris_config(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- struct al_serdes_sris_params *params)
+static void al_serdes_sris_config(
+ struct al_serdes_grp_obj *obj,
+ void *sris_params)
{
- struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+ struct al_serdes_sris_params *params = sris_params;
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM,
(params->ppm_drift_count & AL_FIELD_MASK(7, 0)) >> 0);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM,
(params->ppm_drift_count & AL_FIELD_MASK(15, 8)) >> 8);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM,
(params->ppm_drift_max & AL_FIELD_MASK(7, 0)) >> 0);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM,
(params->ppm_drift_max & AL_FIELD_MASK(15, 8)) >> 8);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM,
(params->synth_ppm_drift_max & AL_FIELD_MASK(7, 0)) >> 0);
- al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+ al_serdes_reg_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM,
(params->synth_ppm_drift_max & AL_FIELD_MASK(15, 8)) >> 8);
- al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
+ al_serdes_grp_reg_masked_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM,
SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK,
(params->full_d2r1)
<< SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT);
- al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
+ al_serdes_grp_reg_masked_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM,
SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK,
(params->full_pcie_g3)
<< SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT);
- al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
+ al_serdes_grp_reg_masked_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM,
SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK,
(params->rd_threshold_d2r1)
<< SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT);
- al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
+ al_serdes_grp_reg_masked_write(obj, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM,
SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK,
(params->rd_threshold_pcie_g3)
<< SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT);
}
+
+/******************************************************************************/
+/******************************************************************************/
+static void al_serdes_dcgain_set(
+ struct al_serdes_grp_obj *obj,
+ uint8_t dcgain)
+{
+ al_serdes_grp_reg_masked_write(obj,
+ AL_SRDS_REG_PAGE_4_COMMON,
+ AL_SRDS_REG_TYPE_PMA,
+ SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM,
+ SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK,
+ (dcgain << SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT));
+}
+
+
+/******************************************************************************/
+/******************************************************************************/
+int al_serdes_hssp_handle_init(
+ void __iomem *serdes_regs_base,
+ struct al_serdes_grp_obj *obj)
+{
+ al_dbg(
+ "%s(%p, %p)\n",
+ __func__,
+ serdes_regs_base,
+ obj);
+
+ al_memset(obj, 0, sizeof(struct al_serdes_grp_obj));
+
+ obj->regs_base = (struct al_serdes_regs *)serdes_regs_base;
+ obj->type_get = al_serdes_hssp_type_get;
+ obj->reg_read = al_serdes_reg_read;
+ obj->reg_write = al_serdes_reg_write;
+ obj->bist_overrides_enable = AL_SRDS_ADV_SRVC(al_serdes_bist_overrides_enable);
+ obj->bist_overrides_disable = AL_SRDS_ADV_SRVC(al_serdes_bist_overrides_disable);
+ obj->rx_rate_change = AL_SRDS_ADV_SRVC(al_serdes_rx_rate_change);
+ obj->rx_rate_change_sw_flow_en = AL_SRDS_ADV_SRVC(al_serdes_lane_rx_rate_change_sw_flow_en);
+ obj->rx_rate_change_sw_flow_dis =
+ AL_SRDS_ADV_SRVC(al_serdes_lane_rx_rate_change_sw_flow_dis);
+ obj->pcie_rate_override_is_enabled =
+ AL_SRDS_ADV_SRVC(al_serdes_lane_pcie_rate_override_is_enabled);
+ obj->pcie_rate_override_enable_set =
+ AL_SRDS_ADV_SRVC(al_serdes_lane_pcie_rate_override_enable_set);
+ obj->pcie_rate_get = AL_SRDS_ADV_SRVC(al_serdes_lane_pcie_rate_get);
+ obj->pcie_rate_set = AL_SRDS_ADV_SRVC(al_serdes_lane_pcie_rate_set);
+ obj->group_pm_set = AL_SRDS_ADV_SRVC(al_serdes_group_pm_set);
+ obj->lane_pm_set = AL_SRDS_ADV_SRVC(al_serdes_lane_pm_set);
+ obj->pma_hard_reset_group = AL_SRDS_ADV_SRVC(al_serdes_pma_hard_reset_group);
+ obj->pma_hard_reset_lane = AL_SRDS_ADV_SRVC(al_serdes_pma_hard_reset_lane);
+ obj->loopback_control = AL_SRDS_ADV_SRVC(al_serdes_loopback_control);
+ obj->bist_pattern_select = AL_SRDS_ADV_SRVC(al_serdes_bist_pattern_select);
+ obj->bist_tx_enable = AL_SRDS_ADV_SRVC(al_serdes_bist_tx_enable);
+ obj->bist_tx_err_inject = AL_SRDS_ADV_SRVC(al_serdes_bist_tx_err_inject);
+ obj->bist_rx_enable = AL_SRDS_ADV_SRVC(al_serdes_bist_rx_enable);
+ obj->bist_rx_status = AL_SRDS_ADV_SRVC(al_serdes_bist_rx_status);
+ obj->tx_deemph_preset = AL_SRDS_ADV_SRVC(al_serdes_tx_deemph_preset);
+ obj->tx_deemph_inc = AL_SRDS_ADV_SRVC(al_serdes_tx_deemph_inc);
+ obj->tx_deemph_dec = AL_SRDS_ADV_SRVC(al_serdes_tx_deemph_dec);
+ obj->eye_measure_run = AL_SRDS_ADV_SRVC(al_serdes_eye_measure_run);
+ obj->eye_diag_sample = AL_SRDS_ADV_SRVC(al_serdes_eye_diag_sample);
+ obj->signal_is_detected = AL_SRDS_ADV_SRVC(al_serdes_signal_is_detected);
+ obj->tx_advanced_params_set = AL_SRDS_ADV_SRVC(al_serdes_tx_advanced_params_set);
+ obj->tx_advanced_params_get = AL_SRDS_ADV_SRVC(al_serdes_tx_advanced_params_get);
+ obj->rx_advanced_params_set = AL_SRDS_ADV_SRVC(al_serdes_rx_advanced_params_set);
+ obj->rx_advanced_params_get = AL_SRDS_ADV_SRVC(al_serdes_rx_advanced_params_get);
+ obj->mode_set_sgmii = AL_SRDS_ADV_SRVC(al_serdes_mode_set_sgmii);
+ obj->mode_set_kr = AL_SRDS_ADV_SRVC(al_serdes_mode_set_kr);
+ obj->rx_equalization = AL_SRDS_ADV_SRVC(al_serdes_rx_equalization);
+ obj->calc_eye_size = AL_SRDS_ADV_SRVC(al_serdes_calc_eye_size);
+ obj->sris_config = AL_SRDS_ADV_SRVC(al_serdes_sris_config);
+ obj->dcgain_set = AL_SRDS_ADV_SRVC(al_serdes_dcgain_set);
+
+ return 0;
+}
diff --git a/al_hal_serdes.h b/al_hal_serdes.h
index 37aec839b2f2..e69de29bb2d1 100644
--- a/al_hal_serdes.h
+++ b/al_hal_serdes.h
@@ -1,1125 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
- * Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_serdes_api API
- * SerDes HAL driver API
- * @ingroup group_serdes SerDes
- * @{
- *
- * @file al_hal_serdes.h
- *
- * @brief Header file for the SerDes HAL driver
- *
- */
-
-#ifndef __AL_HAL_SERDES_H__
-#define __AL_HAL_SERDES_H__
-
-#include "al_hal_common.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-struct al_serdes_obj;
-
-enum al_serdes_group {
- AL_SRDS_GRP_A = 0,
- AL_SRDS_GRP_B,
- AL_SRDS_GRP_C,
- AL_SRDS_GRP_D,
-
- AL_SRDS_NUM_GROUPS,
-};
-
-struct al_serdes_group_info {
- /*
- * Group parent object - filled automatically by al_serdes_handle_init
- */
- struct al_serdes_obj *pobj;
-
- /*
- * Group specific register base - filled automatically by
- * al_sedres_handle_init
- */
- struct al_serdes_regs __iomem *regs_base;
-};
-
-struct al_serdes_obj {
- struct al_serdes_group_info grp_info[AL_SRDS_NUM_GROUPS];
-};
-
-enum al_serdes_reg_page {
- AL_SRDS_REG_PAGE_0_LANE_0 = 0,
- AL_SRDS_REG_PAGE_1_LANE_1,
- AL_SRDS_REG_PAGE_2_LANE_2,
- AL_SRDS_REG_PAGE_3_LANE_3,
- AL_SRDS_REG_PAGE_4_COMMON,
- AL_SRDS_REG_PAGE_0123_LANES_0123 = 7,
-};
-
-enum al_serdes_reg_type {
- AL_SRDS_REG_TYPE_PMA = 0,
- AL_SRDS_REG_TYPE_PCS,
-};
-
-enum al_serdes_lane {
- AL_SRDS_LANE_0 = AL_SRDS_REG_PAGE_0_LANE_0,
- AL_SRDS_LANE_1 = AL_SRDS_REG_PAGE_1_LANE_1,
- AL_SRDS_LANE_2 = AL_SRDS_REG_PAGE_2_LANE_2,
- AL_SRDS_LANE_3 = AL_SRDS_REG_PAGE_3_LANE_3,
-
- AL_SRDS_NUM_LANES,
- AL_SRDS_LANES_0123 = AL_SRDS_REG_PAGE_0123_LANES_0123,
-};
-
-/** Serdes loopback mode */
-enum al_serdes_lb_mode {
- /** No loopback */
- AL_SRDS_LB_MODE_OFF,
-
- /**
- * Transmits the untimed, partial equalized RX signal out the transmit
- * IO pins.
- * No clock used (untimed)
- */
- AL_SRDS_LB_MODE_PMA_IO_UN_TIMED_RX_TO_TX,
-
- /**
- * Loops back the TX serializer output into the CDR.
- * CDR recovered bit clock used (without attenuation)
- */
- AL_SRDS_LB_MODE_PMA_INTERNALLY_BUFFERED_SERIAL_TX_TO_RX,
-
- /**
- * Loops back the TX driver IO signal to the RX IO pins
- * CDR recovered bit clock used (only through IO)
- */
- AL_SRDS_LB_MODE_PMA_SERIAL_TX_IO_TO_RX_IO,
-
- /**
- * Parallel loopback from the PMA receive lane data ports, to the
- * transmit lane data ports
- * CDR recovered bit clock used
- */
- AL_SRDS_LB_MODE_PMA_PARALLEL_RX_TO_TX,
-
- /** Loops received data after elastic buffer to transmit path */
- AL_SRDS_LB_MODE_PCS_PIPE,
-
- /** Loops TX data (to PMA) to RX path (instead of PMA data) */
- AL_SRDS_LB_MODE_PCS_NEAR_END,
-
- /** Loops receive data prior to interface block to transmit path */
- AL_SRDS_LB_MODE_PCS_FAR_END,
-};
-
-/** Serdes BIST pattern */
-enum al_serdes_bist_pattern {
- AL_SRDS_BIST_PATTERN_USER,
- AL_SRDS_BIST_PATTERN_PRBS7,
- AL_SRDS_BIST_PATTERN_PRBS23,
- AL_SRDS_BIST_PATTERN_PRBS31,
- AL_SRDS_BIST_PATTERN_CLK1010,
-};
-
-/** SerDes group rate */
-enum al_serdes_rate {
- AL_SRDS_RATE_1_8,
- AL_SRDS_RATE_1_4,
- AL_SRDS_RATE_1_2,
- AL_SRDS_RATE_FULL,
-};
-
-/** SerDes power mode */
-enum al_serdes_pm {
- AL_SRDS_PM_PD,
- AL_SRDS_PM_P2,
- AL_SRDS_PM_P1,
- AL_SRDS_PM_P0S,
- AL_SRDS_PM_P0,
-};
-
-/** SerDes PCIe Rate - values are important for proper behavior */
-enum al_serdes_pcie_rate {
- AL_SRDS_PCIE_RATE_GEN1 = 0,
- AL_SRDS_PCIE_RATE_GEN2,
- AL_SRDS_PCIE_RATE_GEN3,
-};
-
-/**
- * Initializes a SERDES object
- *
- * @param serdes_regs_base
- * The SERDES register file base pointer
- *
- * @param obj
- * An allocated, non initialized object context
- *
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_handle_init(
- void __iomem *serdes_regs_base,
- struct al_serdes_obj *obj);
-
-/**
- * SERDES register read
- *
- * Reads a SERDES register
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param page
- * The SERDES register page within the group
- *
- * @param type
- * The SERDES register type (PMA /PCS)
- *
- * @param offset
- * The SERDES register offset (0 - 4095)
- *
- * @param data
- * The read data
- *
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_reg_read(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_reg_page page,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t *data);
-
-/**
- * SERDES register write
- *
- * Writes a SERDES register
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param page
- * The SERDES register page within the group
- *
- * @param type
- * The SERDES register type (PMA /PCS)
- *
- * @param offset
- * The SERDES register offset (0 - 4095)
- *
- * @param data
- * The data to write
- *
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_reg_write(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_reg_page page,
- enum al_serdes_reg_type type,
- uint16_t offset,
- uint8_t data);
-
-/**
- * Enable BIST required overrides
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param rate
- * The required speed rate
- */
-void al_serdes_bist_overrides_enable(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_rate rate);
-
-/**
- * Disable BIST required overrides
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param rate
- * The required speed rate
- */
-void al_serdes_bist_overrides_disable(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp);
-
-/**
- * Rx rate change
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param rate
- * The Rx required rate
- */
-void al_serdes_rx_rate_change(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_rate rate);
-
-/**
- * SERDES lane Rx rate change software flow enable
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param lane
- * The SERDES lane within the group
- */
-void al_serdes_lane_rx_rate_change_sw_flow_en(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane);
-
-/**
- * SERDES lane Rx rate change software flow disable
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param lane
- * The SERDES lane within the group
- */
-void al_serdes_lane_rx_rate_change_sw_flow_dis(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane);
-
-/**
- * PCIe lane rate override check
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param lane
- * The SERDES lane within the group
- * @returns AL_TRUE if the override is enabled
- */
-al_bool al_serdes_lane_pcie_rate_override_is_enabled(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane);
-
-/**
- * PCIe lane rate override control
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param lane
- * The SERDES lane within the group
- * @param en
- * Enable/disable
- */
-void al_serdes_lane_pcie_rate_override_enable_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool en);
-
-/**
- * PCIe lane rate get
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param lane
- * The SERDES lane within the group
- */
-enum al_serdes_pcie_rate al_serdes_lane_pcie_rate_get(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane);
-
-/**
- * PCIe lane rate set
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param lane
- * The SERDES lane within the group
- * @param rate
- * The required rate
- */
-void al_serdes_lane_pcie_rate_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_pcie_rate rate);
-
-/**
- * SERDES group power mode control
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param pm
- * The required power mode
- */
-void al_serdes_group_pm_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_pm pm);
-
-/**
- * SERDES lane power mode control
- *
- * @param obj
- * The object context
- * @param grp
- * The SERDES group
- * @param lane
- * The SERDES lane within the group
- * @param rx_pm
- * The required RX power mode
- * @param tx_pm
- * The required TX power mode
- */
-void al_serdes_lane_pm_set(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_pm rx_pm,
- enum al_serdes_pm tx_pm);
-
-/**
- * SERDES group PMA hard reset
- *
- * Controls Serdes group PMA hard reset
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param enable
- * Enable/disable hard reset
- */
-void al_serdes_pma_hard_reset_group(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- al_bool enable);
-
-/**
- * SERDES lane PMA hard reset
- *
- * Controls Serdes lane PMA hard reset
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param lane
- * The SERDES lane within the group
- *
- * @param enable
- * Enable/disable hard reset
- */
-void al_serdes_pma_hard_reset_lane(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool enable);
-
-/**
- * SERDES loopback control
- *
- * Controls the loopback
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param lane
- * The SERDES lane within the group
- *
- * @param mode
- * The requested loopback mode
- *
- */
-void al_serdes_loopback_control(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_lb_mode mode);
-
-/**
- * SERDES BIST pattern selection
- *
- * Selects the BIST pattern to be used
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param pattern
- * The pattern to set
- *
- * @param user_data
- * The pattern user data (when pattern == AL_SRDS_BIST_PATTERN_USER)
- * 80 bits (8 bytes array)
- *
- */
-void al_serdes_bist_pattern_select(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_bist_pattern pattern,
- uint8_t *user_data);
-
-/**
- * SERDES BIST TX Enable
- *
- * Enables/disables TX BIST per lane
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param lane
- * The SERDES lane within the group
- *
- * @param enable
- * Enable or disable TX BIST
- */
-void al_serdes_bist_tx_enable(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool enable);
-
-/**
- * SERDES BIST TX single bit error injection
- *
- * Injects single bit error during a TX BIST
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- */
-void al_serdes_bist_tx_err_inject(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp);
-
-/**
- * SERDES BIST RX Enable
- *
- * Enables/disables RX BIST per lane
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param lane
- * The SERDES lane within the group
- *
- * @param enable
- * Enable or disable TX BIST
- */
-void al_serdes_bist_rx_enable(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool enable);
-
-/**
- * SERDES BIST RX status
- *
- * Checks the RX BIST status for a specific SERDES lane
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param lane
- * The SERDES lane within the group
- *
- * @param is_locked
- * An indication whether RX BIST is locked
- *
- * @param err_cnt_overflow
- * An indication whether error count overflow occured
- *
- * @param err_cnt
- * Current bit error count
- */
-void al_serdes_bist_rx_status(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- al_bool *is_locked,
- al_bool *err_cnt_overflow,
- uint16_t *err_cnt);
-
-/**
- * SERDES Digital Test Bus
- *
- * Samples the digital test bus of a specific SERDES lane
- *
- * @param obj
- * The object context
- *
- * @param grp
- * The SERDES group
- *
- * @param lane
- * The SERDES lane within the group
- *
- * @param sel
- * The selected sampling group (0 - 31)
- *
- * @param sampled_data
- * The sampled data (5 bytes array)
- *
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_digital_test_bus(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- uint8_t sel,
- uint8_t *sampled_data);
-
-
-/* KR link training */
-/**
- * Set the tx de-emphasis to preset values
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- */
-void al_serdes_tx_deemph_preset(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane);
-
-/**
- * Tx de-emphasis parameters
- */
-enum al_serdes_tx_deemph_param {
- AL_SERDES_TX_DEEMP_C_ZERO, /*< c(0) */
- AL_SERDES_TX_DEEMP_C_PLUS, /*< c(1) */
- AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
-};
-
-/**
- * Increase tx de-emphasis param.
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param param which tx de-emphasis to change
- *
- * @return false in case max is reached. true otherwise.
- */
-al_bool al_serdes_tx_deemph_inc(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_tx_deemph_param param);
-
-/**
- * Decrease tx de-emphasis param.
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param param which tx de-emphasis to change
- *
- * @return false in case min is reached. true otherwise.
- */
-al_bool al_serdes_tx_deemph_dec(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- enum al_serdes_tx_deemph_param param);
-
-/**
- * run Rx eye measurement.
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param timeout timeout in uSec
- *
- * @param value Rx eye measurement value
- * (0 - completely closed eye, 0xffff - completely open eye).
- *
- * @return 0 if no error found.
- */
-int al_serdes_eye_measure_run(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- uint32_t timeout,
- unsigned int *value);
-
-/**
- * Eye diagram single sampling
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param x Sampling X position (0 - 63 --> -1.00 UI ... 1.00 UI)
- *
- * @param y Sampling Y position (0 - 62 --> 500mV ... -500mV)
- *
- * @param timeout timeout in uSec
- *
- * @param value Eye diagram sample value (BER - 0x0000 - 0xffff)
- *
- * @return 0 if no error found.
- */
-int al_serdes_eye_diag_sample(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- unsigned int x,
- int y,
- unsigned int timeout,
- unsigned int *value);
-
-/**
- * Check if signal is detected
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @return true if signal is detected. false otherwise.
- */
-al_bool al_serdes_signal_is_detected(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane);
-
-
-struct al_serdes_adv_tx_params {
- /*
- * select the input values location.
- * When set to true the values will be taken from the internal registers
- * that will be override with the next following parameters.
- * When set to false the values will be taken from external pins (the
- * other parameters in this case is not needed)
- */
- al_bool override;
- /*
- * Transmit Amplitude control signal. Used to define the full-scale
- * maximum swing of the driver.
- * 000 - Not Supported
- * 001 - 952mVdiff-pkpk
- * 010 - 1024mVdiff-pkpk
- * 011 - 1094mVdiff-pkpk
- * 100 - 1163mVdiff-pkpk
- * 101 - 1227mVdiff-pkpk
- * 110 - 1283mVdiff-pkpk
- * 111 - 1331mVdiff-pkpk
- */
- uint8_t amp;
- /* Defines the total number of driver units allocated in the driver */
- uint8_t total_driver_units;
- /* Defines the total number of driver units allocated to the
- * first post-cursor (C+1) tap. */
- uint8_t c_plus_1;
- /* Defines the total number of driver units allocated to the
- * second post-cursor (C+2) tap. */
- uint8_t c_plus_2;
- /* Defines the total number of driver units allocated to the
- * first pre-cursor (C-1) tap. */
- uint8_t c_minus_1;
- /* TX driver Slew Rate control:
- * 00 - 31ps
- * 01 - 33ps
- * 10 - 68ps
- * 11 - 170ps
- */
- uint8_t slew_rate;
-};
-
-struct al_serdes_adv_rx_params {
- /*
- * select the input values location.
- * When set to true the values will be taken from the internal registers
- * that will be override with the next following parameters.
- * When set to false the values will be taken based in the equalization
- * results (the other parameters in this case is not needed)
- */
- al_bool override;
- /* RX agc high frequency dc gain:
- * -3'b000: -3dB
- * -3'b001: -2.5dB
- * -3'b010: -2dB
- * -3'b011: -1.5dB
- * -3'b100: -1dB
- * -3'b101: -0.5dB
- * -3'b110: -0dB
- * -3'b111: 0.5dB
- */
- uint8_t dcgain;
- /* DFE post-shaping tap 3dB frequency
- * -3'b000: 684MHz
- * -3'b001: 576MHz
- * -3'b010: 514MHz
- * -3'b011: 435MHz
- * -3'b100: 354MHz
- * -3'b101: 281MHz
- * -3'b110: 199MHz
- * -3'b111: 125MHz
- */
- uint8_t dfe_3db_freq;
- /* DFE post-shaping tap gain
- * 0: no pulse shaping tap
- * 1: -24mVpeak
- * 2: -45mVpeak
- * 3: -64mVpeak
- * 4: -80mVpeak
- * 5: -93mVpeak
- * 6: -101mVpeak
- * 7: -105mVpeak
- */
- uint8_t dfe_gain;
- /* DFE first tap gain control
- * -4'b0000: +1mVpeak
- * -4'b0001: +10mVpeak
- * ....
- * -4'b0110: +55mVpeak
- * -4'b0111: +64mVpeak
- * -4'b1000: -1mVpeak
- * -4'b1001: -10mVpeak
- * ....
- * -4'b1110: -55mVpeak
- * -4'b1111: -64mVpeak
- */
- uint8_t dfe_first_tap_ctrl;
- /* DFE second tap gain control
- * -4'b0000: +0mVpeak
- * -4'b0001: +9mVpeak
- * ....
- * -4'b0110: +46mVpeak
- * -4'b0111: +53mVpeak
- * -4'b1000: -0mVpeak
- * -4'b1001: -9mVpeak
- * ....
- * -4'b1110: -46mVpeak
- * -4'b1111: -53mVpeak
- */
- uint8_t dfe_secound_tap_ctrl;
- /* DFE third tap gain control
- * -4'b0000: +0mVpeak
- * -4'b0001: +7mVpeak
- * ....
- * -4'b0110: +38mVpeak
- * -4'b0111: +44mVpeak
- * -4'b1000: -0mVpeak
- * -4'b1001: -7mVpeak
- * ....
- * -4'b1110: -38mVpeak
- * -4'b1111: -44mVpeak
- */
- uint8_t dfe_third_tap_ctrl;
- /* DFE fourth tap gain control
- * -4'b0000: +0mVpeak
- * -4'b0001: +6mVpeak
- * ....
- * -4'b0110: +29mVpeak
- * -4'b0111: +33mVpeak
- * -4'b1000: -0mVpeak
- * -4'b1001: -6mVpeak
- * ....
- * -4'b1110: -29mVpeak
- * -4'b1111: -33mVpeak
- */
- uint8_t dfe_fourth_tap_ctrl;
- /* Low frequency agc gain (att) select
- * -3'b000: Disconnected
- * -3'b001: -18.5dB
- * -3'b010: -12.5dB
- * -3'b011: -9dB
- * -3'b100: -6.5dB
- * -3'b101: -4.5dB
- * -3'b110: -2.9dB
- * -3'b111: -1.6dB
- */
- uint8_t low_freq_agc_gain;
- /* Provides a RX Equalizer pre-hint, prior to beginning
- * adaptive equalization */
- uint8_t precal_code_sel;
- /* High frequency agc boost control
- * Min d0: Boost ~4dB
- * Max d31: Boost ~20dB
- */
- uint8_t high_freq_agc_boost;
-};
-
-/**
- * configure tx advanced parameters
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param params pointer to the tx parameters
- */
-void al_serdes_tx_advanced_params_set(struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- struct al_serdes_adv_tx_params *params);
-
-/**
- * read tx advanced parameters
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param params pointer to the tx parameters
- */
-void al_serdes_tx_advanced_params_get(struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- struct al_serdes_adv_tx_params *params);
-
-/**
- * configure rx advanced parameters
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param params pointer to the rx parameters
- */
-void al_serdes_rx_advanced_params_set(struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- struct al_serdes_adv_rx_params *params);
-
-/**
- * read rx advanced parameters
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param params pointer to the rx parameters
- */
-void al_serdes_rx_advanced_params_get(struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- struct al_serdes_adv_rx_params* params);
-
-/**
- * Switch entire SerDes group to SGMII mode based on 156.25 Mhz reference clock
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- */
-void al_serdes_mode_set_sgmii(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp);
-
-/**
- * Switch entire SerDes group to KR mode based on 156.25 Mhz reference clock
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- */
-void al_serdes_mode_set_kr(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp);
-
-/**
- * performs SerDes HW equalization test and update equalization parameters
- *
- * @param obj the object context
- *
- * @param grp the SERDES group
- *
- * @param lane The SERDES lane within the group
- */
-int al_serdes_rx_equalization(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane);
-
-/**
- * performs Rx equalization and compute the width and height of the eye
- *
- * @param obj the object context
- *
- * @param grp the SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param width the output width of the eye
- *
- * @param height the output height of the eye
- */
-int al_serdes_calc_eye_size(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- enum al_serdes_lane lane,
- int* width,
- int* height);
-
-/**
- * SRIS parameters
- */
-struct al_serdes_sris_params {
- /* Controls the frequency accuracy threshold (ppm) for lock detection CDR */
- uint16_t ppm_drift_count;
- /* Controls the frequency accuracy threshold (ppm) for lock detection in the CDR */
- uint16_t ppm_drift_max;
- /* Controls the frequency accuracy threshold (ppm) for lock detection in PLL */
- uint16_t synth_ppm_drift_max;
- /* Elastic buffer full threshold for PCIE modes: GEN1/GEN2 */
- uint8_t full_d2r1;
- /* Elastic buffer full threshold for PCIE modes: GEN3 */
- uint8_t full_pcie_g3;
- /* Elastic buffer midpoint threshold.
- * Sets the depth of the buffer while in PCIE mode, GEN1/GEN2
- */
- uint8_t rd_threshold_d2r1;
- /* Elastic buffer midpoint threshold.
- * Sets the depth of the buffer while in PCIE mode, GEN3
- */
- uint8_t rd_threshold_pcie_g3;
-};
-
-/**
- * SRIS: Separate Refclk Independent SSC (Spread Spectrum Clocking)
- * Currently available only for PCIe interfaces.
- * When working with local Refclk, same SRIS configuration in both serdes sides
- * (EP and RC in PCIe interface) is required.
- *
- * performs SRIS configuration according to params
- *
- * @param obj the object context
- *
- * @param grp the SERDES group
- *
- * @param params the SRIS parameters
- */
-void al_serdes_sris_config(
- struct al_serdes_obj *obj,
- enum al_serdes_group grp,
- struct al_serdes_sris_params *params);
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-
-/* *INDENT-ON* */
-#endif /* __AL_SRDS__ */
-
-/** @} end of SERDES group */
-
diff --git a/al_hal_serdes_25g.c b/al_hal_serdes_25g.c
new file mode 100644
index 000000000000..68767e557fd1
--- /dev/null
+++ b/al_hal_serdes_25g.c
@@ -0,0 +1,1951 @@
+/*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "al_hal_serdes_25g.h"
+#include "al_hal_serdes_25g_regs.h"
+#include "al_hal_serdes_25g_internal_regs.h"
+
+#define AL_SERDES_MB_MAX_DATA_LEN 8
+
+#define AL_SERDES_25G_WAIT_FOR_READY_TO 200
+#define AL_SERDES_25G_RESET_TO 100
+#define AL_SERDES_25G_RESET_NUM_RETRIES 5
+
+#if (!defined(AL_SERDES_BASIC_SERVICES_ONLY)) || (AL_SERDES_BASIC_SERVICES_ONLY == 0)
+#define AL_SRDS_ADV_SRVC(func) func
+#else
+static void al_serdes_hssp_stub_func(void)
+{
+ al_err("%s: not implemented service called!\n", __func__);
+}
+
+#define AL_SRDS_ADV_SRVC(func) ((typeof(func) *)al_serdes_hssp_stub_func)
+#endif
+
+/******************************************************************************/
+/******************************************************************************/
+static enum al_serdes_type al_serdes_25g_type_get(void)
+{
+ return AL_SRDS_TYPE_25G;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static int al_serdes_25g_reg_read(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_reg_page page,
+ enum al_serdes_reg_type type,
+ uint16_t offset,
+ uint8_t *data)
+{
+ struct al_serdes_c_regs __iomem *regs_base = obj->regs_base;
+ uint32_t addr = 0;
+
+ al_dbg("%s(%p, %d, %d, %u)\n", __func__, obj, page, type, offset);
+
+ al_assert(obj);
+ al_assert(data);
+
+ switch (page) {
+ case AL_SRDS_REG_PAGE_TOP:
+ addr = (SERDES_25G_TOP_BASE + offset);
+ break;
+ case AL_SRDS_REG_PAGE_4_COMMON:
+ addr = (SERDES_25G_CM_BASE + offset);
+ break;
+ case AL_SRDS_REG_PAGE_0_LANE_0:
+ case AL_SRDS_REG_PAGE_1_LANE_1:
+ addr = (SERDES_25G_LANE_BASE + (page * SERDES_25G_LANE_SIZE) + offset);
+ break;
+ default:
+ al_err("%s: wrong serdes type %d\n", __func__, type);
+ return -1;
+ }
+
+ al_reg_write32(&regs_base->gen.reg_addr, addr);
+ *data = al_reg_read32(&regs_base->gen.reg_data);
+
+ al_dbg("%s: return(%u)\n", __func__, *data);
+
+ return 0;
+}
+
+static int al_serdes_25g_reg_write(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_reg_page page,
+ enum al_serdes_reg_type type,
+ uint16_t offset,
+ uint8_t data)
+{
+ struct al_serdes_c_regs __iomem *regs_base = obj->regs_base;
+ uint32_t addr = 0;
+
+ al_dbg("%s(%p, %d, %d, %u)\n", __func__, obj, page, type, offset);
+
+ al_assert(obj);
+
+ switch (page) {
+ case AL_SRDS_REG_PAGE_TOP:
+ addr = (SERDES_25G_TOP_BASE + offset);
+ break;
+ case AL_SRDS_REG_PAGE_4_COMMON:
+ addr = (SERDES_25G_CM_BASE + offset);
+ break;
+ case AL_SRDS_REG_PAGE_0_LANE_0:
+ case AL_SRDS_REG_PAGE_1_LANE_1:
+ addr = (SERDES_25G_LANE_BASE + (page * SERDES_25G_LANE_SIZE) + offset);
+ break;
+ default:
+ al_err("%s: wrong serdes type %d\n", __func__, type);
+ return -1;
+ }
+
+ al_reg_write32(&regs_base->gen.reg_addr, addr);
+ al_reg_write32(&regs_base->gen.reg_data, (data | SERDES_C_GEN_REG_DATA_STRB_MASK));
+
+ al_dbg("%s: write(%u)\n", __func__, data);
+
+ return 0;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static int al_serdes_25g_reg_masked_read(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_reg_page page,
+ uint16_t offset,
+ uint8_t mask,
+ uint8_t shift,
+ uint8_t *data)
+{
+ uint8_t val;
+ int status = 0;
+
+ status = al_serdes_25g_reg_read(obj, page, 0, offset, &val);
+ if (status)
+ return status;
+
+ *data = AL_REG_FIELD_GET(val, mask, shift);
+
+ return 0;
+}
+
+static int al_serdes_25g_reg_masked_write(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_reg_page page,
+ uint16_t offset,
+ uint8_t mask,
+ uint8_t shift,
+ uint8_t data)
+{
+ uint8_t val;
+ int status = 0;
+
+ status = al_serdes_25g_reg_read(obj, page, 0, offset, &val);
+ if (status)
+ return status;
+
+ val &= (~mask);
+ val |= (data << shift);
+ return al_serdes_25g_reg_write(obj, page, 0, offset, val);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+#define SERDES_25G_MB_RESP_BYTES 16
+#define SERDES_25G_MB_TIMEOUT 5000000 /* uSec */
+
+static int al_serdes_25g_mailbox_send_cmd(
+ struct al_serdes_grp_obj *obj,
+ uint8_t cmd,
+ uint8_t *data,
+ uint8_t data_len)
+{
+ uint8_t val;
+ int i;
+ uint32_t timeout = SERDES_25G_MB_TIMEOUT;
+
+ if (data_len > AL_SERDES_MB_MAX_DATA_LEN) {
+ al_err("Cannot send command, data too long\n");
+ return -1;
+ }
+
+ /* Wait for CMD_FLAG to clear */
+ while(1) {
+ al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
+ SERDES_25G_TOP_CMD_FLAG_ADDR, &val);
+ if (val == 0)
+ break;
+
+ if (timeout == 0) {
+ al_err("%s: timeout occurred waiting to CMD_FLAG\n", __func__);
+ return -1;
+ }
+
+ timeout--;
+ al_udelay(1);
+ }
+
+ for (i = 0; i < data_len; i++) {
+ al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0,
+ (SERDES_25G_TOP_CMD_DATA0_ADDR + i), data[i]);
+ }
+
+ /* this write will set CMD_FLAG automatically */
+ al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0, SERDES_25G_TOP_CMD_ADDR, cmd);
+
+ return 0;
+}
+
+static int al_serdes_25g_mailbox_recv_rsp(
+ struct al_serdes_grp_obj *obj,
+ uint8_t *rsp_code,
+ uint8_t *data,
+ uint8_t *data_len)
+{
+ uint8_t val;
+ int i;
+ uint32_t timeout = SERDES_25G_MB_TIMEOUT;
+
+ /* wait for RSP_FLAG to set */
+ while(1) {
+ al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
+ SERDES_25G_TOP_RSP_FLAG_ADDR, &val);
+ if (val == 0x1)
+ break;
+
+ if (timeout == 0) {
+ al_err("%s: timeout occurred waiting to RSP_FLAG\n", __func__);
+ *data_len = 0;
+ return -1;
+ }
+
+ timeout--;
+ al_udelay(1);
+ }
+
+ /* Grab the response code and data */
+ al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
+ SERDES_25G_TOP_RSP_ADDR, rsp_code);
+
+ for (i = 0; i < SERDES_25G_MB_RESP_BYTES; i++) {
+ al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
+ (SERDES_25G_TOP_RSP_DATA0_ADDR + i), &data[i]);
+ }
+
+ /* clear the RSP_FLAG (write 1 to clear) */
+ al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0,
+ SERDES_25G_TOP_RSP_FLAG_ADDR, 0x1);
+
+ *data_len = SERDES_25G_MB_RESP_BYTES;
+
+ return 0;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static void al_serdes_25g_bist_rx_enable(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ al_bool enable)
+{
+ if (enable) {
+ switch (lane) {
+ case 0:
+ al_serdes_25g_reg_masked_write(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_MASK,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_SHIFT,
+ 0x1);
+ al_serdes_25g_reg_masked_write(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_MASK,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_SHIFT,
+ 0x1);
+ break;
+ case 1:
+ al_serdes_25g_reg_masked_write(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_MASK,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_SHIFT,
+ 0x1);
+
+ al_serdes_25g_reg_masked_write(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_MASK,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_SHIFT,
+ 0x1);
+ break;
+ default:
+ al_err("%s: Wrong serdes lane %d\n", __func__, lane);
+ return;
+ }
+
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_ADDR,
+ SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_MASK,
+ SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT,
+ 0);
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
+ SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK,
+ SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT,
+ 1);
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
+ SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_MASK,
+ SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_SHIFT,
+ 6);
+ } else {
+ /* clear counters */
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
+ SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK,
+ SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT,
+ 1);
+
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
+ SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK,
+ SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT,
+ 0);
+
+ al_msleep(AL_SERDES_25G_WAIT_FOR_READY_TO);
+
+ /* disable */
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
+ SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK,
+ SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT,
+ 0);
+ }
+}
+
+// TODO: [Guy] change API to be per lane.
+static void al_serdes_25g_bist_pattern_select(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_bist_pattern pattern,
+ uint8_t *user_data)
+{
+ enum al_serdes_lane lane;
+ uint8_t val = 0;
+
+ switch (pattern) {
+ case AL_SRDS_BIST_PATTERN_USER:
+ al_assert(user_data);
+ val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS_USER;
+ break;
+ case AL_SRDS_BIST_PATTERN_PRBS7:
+ val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS7;
+ break;
+ case AL_SRDS_BIST_PATTERN_PRBS23:
+ val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS23;
+ break;
+ case AL_SRDS_BIST_PATTERN_PRBS31:
+ val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS31;
+ break;
+ case AL_SRDS_BIST_PATTERN_CLK1010:
+ default:
+ al_err("%s: invalid pattern (%d)\n", __func__, pattern);
+ al_assert(0);
+ }
+
+ for (lane = AL_SRDS_LANE_0; lane <= AL_SRDS_LANE_1; lane++) {
+ if (pattern == AL_SRDS_BIST_PATTERN_USER) {
+ int i;
+
+ for (i = 0; i < SERDES_25G_LANE_TX_BIST_UDP_NUM_BYTES; i++)
+ al_serdes_25g_reg_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_TX_BIST_UDP_ADDR(i),
+ user_data[i]);
+ }
+
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
+ SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_MASK,
+ SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_SHIFT,
+ val);
+ }
+}
+
+static void al_serdes_25g_bist_tx_enable(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ al_bool enable)
+{
+ if (enable) {
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
+ SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK,
+ SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT,
+ 0x1);
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR,
+ SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK,
+ SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT,
+ 0x2);
+
+ switch (lane) {
+ case AL_SRDS_LANE_0:
+ al_serdes_25g_reg_masked_write(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_TX_ADDR,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_MASK,
+ SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_SHIFT,
+ 0x1);
+ break;
+ case AL_SRDS_LANE_1:
+ al_serdes_25g_reg_masked_write(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_TX_ADDR,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_MASK,
+ SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_SHIFT,
+ 0x1);
+ break;
+ default:
+ al_err("%s: Wrong serdes lane %d\n", __func__, lane);
+ return;
+ }
+ } else {
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
+ SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK,
+ SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT,
+ 0);
+ }
+
+}
+
+static void al_serdes_25g_bist_rx_status(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ al_bool *is_locked,
+ al_bool *err_cnt_overflow,
+ uint32_t *err_cnt)
+{
+ uint8_t status;
+ uint8_t err1;
+ uint8_t err2;
+ uint8_t err3;
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_STATUS_ADDR,
+ SERDES_25G_LANE_RX_BIST_STATUS_STATE_MASK,
+ SERDES_25G_LANE_RX_BIST_STATUS_STATE_SHIFT,
+ &status);
+
+ if (status != 3) {
+ *is_locked = AL_FALSE;
+ return;
+ }
+
+ *is_locked = AL_TRUE;
+ *err_cnt_overflow = AL_FALSE;
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS0_ADDR,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_MASK,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_SHIFT,
+ &err1);
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS1_ADDR,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_MASK,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_SHIFT,
+ &err2);
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS2_ADDR,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_MASK,
+ SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_SHIFT,
+ &err3);
+
+ *err_cnt = (err1 + (err2 << 8) + (err3 << 16));
+}
+
+#define SERDES_MB_CMD_SWING_CFG 0x83
+#define SERDES_MB_CMD_SAMPLES_COUNT 0x84
+#define SERDES_MB_CMD_START_MEASURE 0x82
+
+#define SERDES_MB_RSP_CODE_0 0
+#define SERDES_MB_RSP_CODE_1 1
+#define SERDES_MB_RSP_CODE_2 2
+
+static int al_serdes_25g_eye_diag_run(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ int x_start,
+ int x_stop,
+ unsigned int x_step,
+ int y_start,
+ int y_stop,
+ unsigned int y_step,
+ uint64_t ber_target,
+ uint64_t *buf,
+ uint32_t buf_size)
+{
+ int rc;
+ uint8_t rsp_code;
+ uint8_t data[16];
+ uint8_t data_len;
+ uint32_t total_bits;
+ uint8_t bits_left_curr_sample;
+ uint8_t bits_left_curr_byte;
+ uint32_t byte = 0;
+ uint32_t x = 0;
+ uint32_t x_samples = (((x_stop - x_start) / x_step) + 1);
+ uint32_t y = 0;
+ uint32_t y_samples = (((y_stop - y_start) / y_step) + 1);
+ uint8_t sample_width = (64 - __builtin_clzl(ber_target));
+ uint8_t msb;
+ uint8_t lsb;
+ uint32_t samples_left = ((x_samples * y_samples));
+ uint8_t sign = 0;
+
+ al_assert(buf_size == (samples_left * sizeof(uint64_t)));
+
+ al_memset(buf, 0, buf_size);
+
+ if (y_start < 0) {
+ y_start *= -1;
+ sign |= 0x1;
+ }
+
+ if (y_stop < 0) {
+ y_stop *= -1;
+ sign |= 0x2;
+ }
+
+ data[0] = lane;
+ data[1] = x_start;
+ data[2] = x_stop;
+ data[3] = x_step;
+ data[4] = y_start;
+ data[5] = y_stop;
+ data[6] = sign;
+ data[7] = y_step;
+
+ rc = al_serdes_25g_mailbox_send_cmd(
+ obj,
+ SERDES_MB_CMD_SWING_CFG,
+ data,
+ 8);
+
+ if (rc) {
+ al_err("%s: Failed to send command %d to mailbox.\n",
+ __func__, SERDES_MB_CMD_SWING_CFG);
+ return rc;
+ }
+
+ rc = al_serdes_25g_mailbox_recv_rsp(
+ obj,
+ &rsp_code,
+ data,
+ &data_len);
+
+ if ((rc) || (rsp_code != SERDES_MB_RSP_CODE_0)) {
+ al_err("%s: Failed to send command %d to mailbox. rsp_code %d\n",
+ __func__, SERDES_MB_CMD_SWING_CFG, rsp_code);
+
+ return (ETIMEDOUT);
+ }
+
+ al_assert(sample_width <= 40);
+
+ data[0] = lane;
+ data[1] = ((ber_target >> 32) & 0xFF);
+ data[2] = ((ber_target >> 24) & 0xFF);
+ data[3] = ((ber_target >> 16) & 0xFF);
+ data[4] = ((ber_target >> 8) & 0xFF);
+ data[5] = (ber_target & 0xFF);
+
+ rc = al_serdes_25g_mailbox_send_cmd(
+ obj,
+ SERDES_MB_CMD_SAMPLES_COUNT,
+ data,
+ 6);
+
+ if (rc) {
+ al_err("%s: Failed to send command %d to mailbox.\n",
+ __func__, SERDES_MB_CMD_SAMPLES_COUNT);
+ return rc;
+ }
+
+ rc = al_serdes_25g_mailbox_recv_rsp(
+ obj,
+ &rsp_code,
+ data,
+ &data_len);
+
+ if ((rc) || (rsp_code != SERDES_MB_RSP_CODE_0)) {
+ al_err("%s: Failed to send command %d to mailbox. rsp_code %d\n",
+ __func__, SERDES_MB_CMD_SAMPLES_COUNT, rsp_code);
+
+ return (ETIMEDOUT);
+ }
+
+ rc = al_serdes_25g_mailbox_send_cmd(
+ obj,
+ SERDES_MB_CMD_START_MEASURE,
+ data,
+ 0);
+
+ bits_left_curr_sample = sample_width;
+
+ while (rsp_code != SERDES_MB_RSP_CODE_1) {
+ uint8_t num_bits = 0;
+
+ rc = al_serdes_25g_mailbox_recv_rsp(
+ obj,
+ &rsp_code,
+ data,
+ &data_len);
+
+ if ((rc != 0) || (rsp_code > SERDES_MB_RSP_CODE_2)) {
+ al_err("%s: command %d return failure. rsp_code %d\n",
+ __func__, SERDES_MB_CMD_START_MEASURE, rsp_code);
+
+ return (ETIMEDOUT);
+ }
+ byte = 0;
+ total_bits = data_len * 8;
+ bits_left_curr_byte = 8;
+ while (total_bits > 0) {
+ num_bits = al_min_t(uint8_t, bits_left_curr_sample, bits_left_curr_byte);
+
+ buf[(y * x_samples) + x] <<= num_bits;
+ msb = bits_left_curr_byte - 1;
+ lsb = msb - num_bits + 1;
+ buf[(y * x_samples) + x] |= (data[byte] & AL_FIELD_MASK(msb, lsb) >> lsb);
+
+ total_bits -= num_bits;
+
+ bits_left_curr_byte -= num_bits;
+ if (!bits_left_curr_byte) {
+ bits_left_curr_byte = 8;
+ byte++;
+ }
+
+ bits_left_curr_sample -= num_bits;
+ if (!bits_left_curr_sample) {
+ y++;
+ if (y == y_samples) {
+ y = 0;
+ x++;
+ }
+
+ samples_left--;
+ bits_left_curr_sample = sample_width;
+ }
+
+ if (samples_left == 0)
+ break;
+ }
+
+ if ((samples_left == 0) && (rsp_code != SERDES_MB_RSP_CODE_1)) {
+ rc = al_serdes_25g_mailbox_recv_rsp(
+ obj,
+ &rsp_code,
+ data,
+ &data_len);
+ if ((rc) || (rsp_code == SERDES_MB_RSP_CODE_0)) {
+ al_err("%s: Parsed enough samples but f/w is still sending more\n",
+ __func__);
+
+ return -EIO;
+ }
+ break;
+ }
+ }
+
+ if (samples_left > 0) {
+ al_err("%s: Still need more samples but f/w has stopped sending them!?!?!?\n",
+ __func__);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+#define SERDES_25G_EYE_X_MIN 1
+#define SERDES_25G_EYE_X_MAX 127
+#define SERDES_25G_EYE_Y_MIN -200
+#define SERDES_25G_EYE_Y_MAX 200
+#define SERDES_25G_EYE_SIZE_MAX_SAMPLES 401
+#define SERDES_25G_EYE_SIZE_BER_TARGET 0xffff
+#define SERDES_25G_EYE_SIZE_ERR_TH 10
+
+static int al_serdes_25g_calc_eye_size(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ int *width,
+ int *height)
+{
+ uint64_t samples[SERDES_25G_EYE_SIZE_MAX_SAMPLES];
+ int i;
+ int _width = 0;
+ int _height = 0;
+ int rc;
+ int mid_x = ((SERDES_25G_EYE_X_MIN + SERDES_25G_EYE_X_MAX) / 2);
+ int mid_y = ((SERDES_25G_EYE_Y_MIN + SERDES_25G_EYE_Y_MAX) / 2);
+
+ *height = 0;
+ *width = 0;
+
+ rc = al_serdes_25g_eye_diag_run(obj,
+ lane,
+ mid_x,
+ mid_x,
+ 1,
+ SERDES_25G_EYE_Y_MIN,
+ SERDES_25G_EYE_Y_MAX,
+ 1,
+ SERDES_25G_EYE_SIZE_BER_TARGET,
+ samples,
+ ((SERDES_25G_EYE_Y_MAX - SERDES_25G_EYE_Y_MIN + 1) *
+ sizeof(uint64_t)));
+
+ if (rc) {
+ al_err("%s: failed to run eye_diag\n", __func__);
+ return rc;
+ }
+
+ for (i = (mid_y - SERDES_25G_EYE_Y_MIN);
+ ((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) &&
+ (i < (SERDES_25G_EYE_Y_MAX - SERDES_25G_EYE_Y_MIN + 1)));
+ i++, (_height)++)
+ ;
+ for (i = (mid_y - SERDES_25G_EYE_Y_MIN);
+ ((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) && (i >= 0));
+ i--, (_height)++)
+ ;
+
+ rc = al_serdes_25g_eye_diag_run(obj,
+ lane,
+ SERDES_25G_EYE_X_MIN,
+ SERDES_25G_EYE_X_MAX,
+ 1,
+ mid_y,
+ mid_y,
+ 1,
+ SERDES_25G_EYE_SIZE_BER_TARGET,
+ samples,
+ ((SERDES_25G_EYE_X_MAX - SERDES_25G_EYE_X_MIN + 1) *
+ sizeof(uint64_t)));
+
+ if (rc) {
+ al_err("%s: failed to run eye_diag\n", __func__);
+ return rc;
+ }
+
+ for (i = (mid_x - SERDES_25G_EYE_X_MIN);
+ ((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) &&
+ (i < (SERDES_25G_EYE_X_MAX - SERDES_25G_EYE_X_MIN + 1)));
+ i++, (_width)++)
+ ;
+ for (i = (mid_x - SERDES_25G_EYE_X_MIN);
+ ((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) && (i >= 0));
+ i--, (_width)++)
+ ;
+
+ *height = _height;
+ *width = _width;
+
+ return 0;
+}
+
+
+static void al_serdes_25g_tx_advanced_params_set(struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ void *tx_params)
+{
+ struct al_serdes_adv_tx_params *params = tx_params;
+ uint32_t timeout = 5000;
+ uint8_t val = 0;
+
+ al_serdes_25g_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT,
+ params->c_minus_1);
+
+ al_serdes_25g_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT,
+ params->c_plus_1);
+
+ al_serdes_25g_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT,
+ params->total_driver_units);
+
+ al_serdes_25g_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT,
+ 1);
+
+
+ /* wait for acknowledge */
+ while (1) {
+ al_serdes_25g_reg_masked_read(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_STATUS0_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_SHIFT,
+ &val);
+ if (val == 1)
+ break;
+
+ if (timeout == 0) {
+ al_err("%s: timeout occurred waiting to FW ack\n", __func__);
+ break;
+ }
+
+ timeout--;
+ al_udelay(1);
+ }
+
+ al_serdes_25g_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT,
+ 0);
+}
+
+static void al_serdes_25g_tx_advanced_params_get(struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ void *tx_params)
+{
+ struct al_serdes_adv_tx_params *params = tx_params;
+
+ al_serdes_25g_reg_masked_read(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT,
+ &params->c_minus_1);
+
+ al_serdes_25g_reg_masked_read(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT,
+ &params->c_plus_1);
+
+ al_serdes_25g_reg_masked_read(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK,
+ SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT,
+ &params->total_driver_units);
+}
+
+static al_bool al_serdes_25g_cdr_is_locked(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
+{
+ uint8_t reg;
+
+ al_serdes_25g_reg_masked_read(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_ADDR,
+ SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_MASK,
+ SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT,
+ &reg);
+
+ return !!reg;
+
+}
+
+static al_bool al_serdes_25g_rx_valid(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
+{
+ uint8_t reg;
+
+ al_serdes_25g_reg_masked_read(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR,
+ SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK,
+ SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT,
+ &reg);
+
+ return !!reg;
+
+}
+
+static al_bool al_serdes_25g_signal_is_detected(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
+{
+ struct al_serdes_c_regs __iomem *regs_base = obj->regs_base;
+ uint32_t reg;
+ al_bool signal_detect = AL_FALSE;
+
+ reg = al_reg_read32(&regs_base->lane[lane].stat);
+
+ signal_detect = ((reg & (SERDES_C_LANE_STAT_LN_STAT_LOS |
+ SERDES_C_LANE_STAT_LN_STAT_LOS_DEGLITCH)) ?
+ AL_FALSE : AL_TRUE);
+
+ return signal_detect;
+
+}
+
+static int al_serdes_25g_rx_equalization(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane)
+{
+ struct al_serdes_c_regs __iomem *regs_base = obj->regs_base;
+ uint32_t ready_mask = (SERDES_C_GEN_STATUS_CM0_RST_PD_READY | SERDES_C_GEN_STATUS_CM0_OK_O);
+ uint32_t reset_mask;
+ uint32_t timeout;
+ uint32_t reg_val;
+ uint32_t retries = AL_SERDES_25G_RESET_NUM_RETRIES;
+ int status = 0;
+
+ if (lane == 0) {
+ ready_mask |= SERDES_C_GEN_STATUS_LN0_RST_PD_READY;
+ reset_mask = SERDES_C_GEN_RST_LN0_RST_N;
+ } else {
+ ready_mask |= SERDES_C_GEN_STATUS_LN1_RST_PD_READY;
+ reset_mask = SERDES_C_GEN_RST_LN1_RST_N;
+ }
+
+ while (retries > 0) {
+ timeout = AL_SERDES_25G_WAIT_FOR_READY_TO;
+ status = 0;
+
+ al_reg_write32_masked(&regs_base->gen.rst, reset_mask, 0);
+
+ al_msleep(AL_SERDES_25G_RESET_TO);
+
+ al_serdes_25g_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_ADDR,
+ SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_MASK,
+ SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT,
+ 0);
+
+ al_serdes_25g_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR,
+ SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_MASK,
+ SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT,
+ 7);
+
+ al_serdes_25g_reg_masked_write(obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR,
+ SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_MASK,
+ SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT,
+ 15);
+
+ al_msleep(AL_SERDES_25G_RESET_TO);
+
+ al_reg_write32_masked(&regs_base->gen.rst, reset_mask, reset_mask);
+
+ while (1) {
+ reg_val = al_reg_read32(&regs_base->gen.status);
+ if ((reg_val & ready_mask) == ready_mask)
+ break;
+
+ al_udelay(1);
+ timeout--;
+
+ if (timeout == 0) {
+ al_err("%s: Timeout waiting for serdes ready\n", __func__);
+ status = ETIMEDOUT;
+ retries--;
+ break;
+ }
+ }
+
+ if (status)
+ continue;
+
+ while (1) {
+ reg_val = al_reg_read32(&regs_base->lane[lane].stat);
+ reg_val &= (SERDES_C_LANE_STAT_LNX_STAT_OK |
+ SERDES_C_LANE_STAT_LN_STAT_RXVALID);
+ if (reg_val == (SERDES_C_LANE_STAT_LNX_STAT_OK |
+ SERDES_C_LANE_STAT_LN_STAT_RXVALID))
+ break;
+
+ al_udelay(1);
+ timeout--;
+
+ if (timeout == 0) {
+ al_err("%s: TO waiting for lane ready (%x)\n", __func__, reg_val);
+ status = ETIMEDOUT;
+ retries--;
+ break;
+ }
+ }
+
+ if (status)
+ continue;
+
+ break;
+ }
+
+ if (retries == 0) {
+ al_err("%s: Failed to run equalization\n", __func__);
+ status = ETIMEDOUT;
+ }
+
+ return status;
+
+}
+
+#define AL_SERDES_25G_GCFSM2_READ_TIMEOUT 2000000 /* uSec */
+
+static int al_serdes_25g_gcfsm2_read(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ uint8_t offset,
+ uint16_t *data)
+{
+ int status = 0;
+ uint32_t timeout = AL_SERDES_25G_GCFSM2_READ_TIMEOUT;
+ uint8_t ack = 0;
+ uint8_t data_low, data_high;
+
+ al_assert(data);
+
+ /* Make sure GCFSM2 REQuest is off */
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
+ 0);
+ /* Write GCFSM2 CMD; CMD=0 for Read Request */
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL1_ADDR,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_MASK,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_SHIFT,
+ 0);
+ /* Write GCFSM2 the Address we wish to read */
+ al_serdes_25g_reg_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR,
+ offset);
+ /* Issue a command REQuest */
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
+ 1);
+ /* Poll on GCFSM2 ACK */
+ while (1) {
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_GCFSM2_CMD_STATUS_ADDR,
+ SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_MASK,
+ SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_SHIFT,
+ &ack);
+
+ if (ack || (timeout == 0))
+ break;
+
+ timeout--;
+ al_udelay(1);
+ }
+
+ if (ack) {
+ /* Read 12bit of register value */
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_ADDR,
+ &data_low);
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_ADDR,
+ SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_MASK,
+ SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_SHIFT,
+ &data_high);
+ *data = (data_high << 8) | data_low;
+ } else {
+ al_err("%s: TO waiting for GCFSM2 req to complete (%x)\n", __func__, offset);
+ status = ETIMEDOUT;
+ }
+
+ /* Deassert the GCFSM2 REQuest */
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
+ SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
+ 0);
+
+ return status;
+}
+
+enum al_serdes_25g_rx_leq_fsm_opcode {
+ AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ = 0x1,
+ AL_SERDES_25G_RX_LEQ_FSM_OPCODE_WRITE = 0x2,
+};
+
+enum al_serdes_25g_rx_leq_fsm_target {
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_AGC_SOURCE = 0x1,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_PLE_ATT = 0x2,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_LFG = 0x3,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_GN_APG = 0x4,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_GNEQ_CCL_LFG = 0x5,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_HFG_SQL = 0x6,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBF = 0x8,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBG = 0x9,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_VSCAN = 0xA,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_HSCAN = 0xB,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_EYE_INTF = 0xC,
+};
+
+#define AL_SERDES_25G_RX_LEQ_FSM_TIMEOUT 2000000 /* uSec */
+
+static int al_serdes_25g_rx_leq_fsm_op(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ enum al_serdes_25g_rx_leq_fsm_opcode opcode,
+ enum al_serdes_25g_rx_leq_fsm_target target,
+ uint8_t val,
+ uint8_t *data,
+ uint8_t *err)
+{
+ uint32_t reg;
+ uint32_t timeout = AL_SERDES_25G_RX_LEQ_FSM_TIMEOUT;
+ uint8_t ack = 0;
+ int status = 0;
+
+ al_assert(data);
+ al_assert(err);
+
+ /* Write the OpCode & Target to LEQ FSM */
+ reg = (target << 4) | opcode;
+ al_serdes_25g_reg_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_ADDR,
+ reg);
+
+ /* Write 0 as MiscOption value to LEQ FSM */
+ al_serdes_25g_reg_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_ADDR,
+ 0);
+
+ /* Write the ArgumentValue to LEQ FSM if needed*/
+ if (opcode == AL_SERDES_25G_RX_LEQ_FSM_OPCODE_WRITE) {
+ al_serdes_25g_reg_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_ADDR,
+ val);
+ }
+
+ /* Issue an LEQ FSM Command Request */
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT,
+ 1);
+
+ /* Poll on LEQ FSM Command acknowledge */
+ while (1) {
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_ADDR,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_MASK,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_SHIFT,
+ &ack);
+
+ if (ack || (timeout == 0))
+ break;
+
+ timeout--;
+ al_udelay(1);
+ }
+
+ if (ack) {
+ uint8_t err1, err2;
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_ADDR,
+ err);
+
+ err1 = (*err &
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_MASK) >>
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_SHIFT;
+ err2 = (*err &
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_MASK) >>
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_SHIFT;
+
+ if (err1 || err2) {
+ al_err("%s: error in RX LEQ FSM req, err status 1=0x%x, err status 2=0x%x",
+ __func__, err1, err2);
+ status = -EIO;
+ }
+
+ /* Read LEQ FSM Command return Value */
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_ADDR,
+ data);
+
+ /* Clear an LEQ FSM Command Request */
+ al_serdes_25g_reg_masked_write(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK,
+ SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT,
+ 0);
+ } else {
+ al_err("%s: TO waiting for RX LEQ FSM req to complete (opcode %x, target %x, val %x)\n",
+ __func__, opcode, target, val);
+ status = ETIMEDOUT;
+ }
+
+ return status;
+}
+
+/* enum values correspond to HW values, don't change! */
+enum al_serdes_25g_tbus_obj {
+ AL_SERDES_25G_TBUS_OBJ_TOP = 0,
+ AL_SERDES_25G_TBUS_OBJ_CMU = 1,
+ AL_SERDES_25G_TBUS_OBJ_LANE = 2,
+};
+
+#define AL_SERDES_25G_TBUS_DELAY 1000 /* uSec */
+#define AL_SERDES_25G_TBUS_ADDR_HIGH_SHIFT 5
+
+static int al_serdes_25g_tbus_read(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ enum al_serdes_25g_tbus_obj tbus_obj,
+ uint8_t offset,
+ uint16_t *data)
+{
+ uint8_t addr_high, val_high, val_low;
+
+ al_assert(lane < AL_SRDS_NUM_LANES);
+
+ if (tbus_obj == AL_SERDES_25G_TBUS_OBJ_TOP)
+ addr_high = AL_SERDES_25G_TBUS_OBJ_TOP;
+ else if (tbus_obj == AL_SERDES_25G_TBUS_OBJ_CMU)
+ addr_high = AL_SERDES_25G_TBUS_OBJ_CMU;
+ else
+ addr_high = AL_SERDES_25G_TBUS_OBJ_LANE + lane;
+
+ addr_high <<= AL_SERDES_25G_TBUS_ADDR_HIGH_SHIFT;
+
+ al_serdes_25g_reg_write(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ 0,
+ SERDES_25G_TOP_TBUS_ADDR_7_0_ADDR,
+ offset);
+
+ al_serdes_25g_reg_write(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ 0,
+ SERDES_25G_TOP_TBUS_ADDR_15_8_ADDR,
+ addr_high);
+
+ al_udelay(AL_SERDES_25G_TBUS_DELAY);
+
+ al_serdes_25g_reg_read(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ 0,
+ SERDES_25G_TOP_TBUS_DATA_7_0_ADDR,
+ &val_low);
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ AL_SRDS_REG_PAGE_TOP,
+ SERDES_25G_TOP_TBUS_DATA_11_8_ADDR,
+ SERDES_25G_TOP_TBUS_DATA_11_8_MASK,
+ SERDES_25G_TOP_TBUS_DATA_11_8_SHIFT,
+ &val_high);
+
+ *data = (val_high << 8) | val_low;
+
+ return 0;
+}
+
+#define AL_SERDES_25G_RX_ADV_PARAMS_ATT_MASK 0x07
+#define AL_SERDES_25G_RX_ADV_PARAMS_APG_MASK 0x03
+#define AL_SERDES_25G_RX_ADV_PARAMS_LFG_MASK 0x1F
+#define AL_SERDES_25G_RX_ADV_PARAMS_HFG_MASK 0x1F
+#define AL_SERDES_25G_RX_ADV_PARAMS_MBG_MASK 0x0F
+#define AL_SERDES_25G_RX_ADV_PARAMS_MBF_MASK 0x0F
+#define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT 8
+#define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_MASK 0x1F
+#define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT 7
+
+static void al_serdes_25g_rx_advanced_params_get(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ void *rx_params)
+{
+ struct al_serdes_25g_adv_rx_params *params = rx_params;
+ uint8_t value, err;
+ int8_t tap_weight;
+ uint8_t tap_sign;
+ int8_t *tap_ptr_arr[AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT];
+ int rc;
+ int i;
+
+ rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_PLE_ATT, 0, &value, &err);
+ if (rc || err) {
+ al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read att, rc %d, err %d\n",
+ __func__, rc, err);
+ return;
+ }
+ params->att = value & AL_SERDES_25G_RX_ADV_PARAMS_ATT_MASK;
+
+ rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_GN_APG, 0, &value, &err);
+ if (rc || err) {
+ al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read apg, rc %d, err %d\n",
+ __func__, rc, err);
+ return;
+ }
+ params->apg = value & AL_SERDES_25G_RX_ADV_PARAMS_APG_MASK;
+
+ rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_LFG, 0, &value, &err);
+ if (rc || err) {
+ al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read lfg, rc %d, err %d\n",
+ __func__, rc, err);
+ return;
+ }
+ params->lfg = value & AL_SERDES_25G_RX_ADV_PARAMS_LFG_MASK;
+
+ rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_HFG_SQL, 0, &value, &err);
+ if (rc || err) {
+ al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read hfg, rc %d, err %d\n",
+ __func__, rc, err);
+ return;
+ }
+ params->hfg = value & AL_SERDES_25G_RX_ADV_PARAMS_HFG_MASK;
+
+ rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBG, 0, &value, &err);
+ if (rc || err) {
+ al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read mbg, rc %d, err %d\n",
+ __func__, rc, err);
+ return;
+ }
+ params->mbg = value & AL_SERDES_25G_RX_ADV_PARAMS_MBG_MASK;
+
+ rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
+ AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBF, 0, &value, &err);
+ if (rc || err) {
+ al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read mbf, rc %d, err %d\n",
+ __func__, rc, err);
+ return;
+ }
+ params->mbf = value & AL_SERDES_25G_RX_ADV_PARAMS_MBF_MASK;
+
+ tap_ptr_arr[0] = &params->dfe_first_tap_even0_ctrl;
+ tap_ptr_arr[1] = &params->dfe_first_tap_even1_ctrl;
+ tap_ptr_arr[2] = &params->dfe_first_tap_odd0_ctrl;
+ tap_ptr_arr[3] = &params->dfe_first_tap_odd1_ctrl;
+ tap_ptr_arr[4] = &params->dfe_second_tap_ctrl;
+ tap_ptr_arr[5] = &params->dfe_third_tap_ctrl;
+ tap_ptr_arr[6] = &params->dfe_fourth_tap_ctrl;
+ tap_ptr_arr[7] = &params->dfe_fifth_tap_ctrl;
+
+ for (i = 0; i < AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT; i++) {
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_ADDR + i,
+ &value);
+
+ tap_weight = value & AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_MASK;
+ tap_sign = (value & AL_BIT(AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT)) >>
+ AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT;
+ if (tap_sign == 0)
+ tap_weight = 0 - tap_weight;
+
+ *tap_ptr_arr[i] = tap_weight;
+ }
+}
+
+#define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_ADDR 0x0B
+#define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_MASK 0x3F
+#define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT 7
+#define AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_ADDR 0x0C
+#define AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_MASK 0xFFF
+
+static void al_serdes_25g_tx_diag_info_get(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ void *tx_info)
+{
+ struct al_serdes_25g_tx_diag_info *info = tx_info;
+ uint8_t cal_x1, cal_x1_fixed, cal_x2, cal_xp5_fixed;
+ uint16_t val16, sign;
+ uint8_t val8, abs;
+ int rc;
+
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR,
+ &val8);
+ info->regulated_supply = val8 & SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK;
+
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_ADDR,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read dcd_trim, rc %d\n",
+ __func__, rc);
+ return;
+ }
+
+ abs = val16 & AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_MASK;
+ sign = (val16 & AL_BIT(AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT)) >>
+ AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT;
+ if (sign)
+ info->dcd_trim = abs;
+ else
+ info->dcd_trim = 0 - abs;
+
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_ADDR,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read clk_delay, rc %d\n",
+ __func__, rc);
+ return;
+ }
+ info->clk_delay = val16 & AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_MASK;
+
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_CM_TOP_AFE_TXTC_CTRL2_ADDR,
+ &val8);
+ cal_x1 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_MASK) >>
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_SHIFT;
+ cal_x1_fixed = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_MASK) >>
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_SHIFT;
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_CM_TOP_AFE_TXTC_CTRL3_ADDR,
+ &val8);
+ cal_x2 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_MASK) >>
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_SHIFT;
+ cal_xp5_fixed = (val8 &
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_MASK) >>
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_SHIFT;
+ info->calp_multiplied_by_2 = 4 * cal_x2 + 2 * cal_x1 + 2 * cal_x1_fixed + cal_xp5_fixed;
+
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_CM_TOP_AFE_TXTC_CTRL0_ADDR,
+ &val8);
+ cal_x1 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_MASK) >>
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_SHIFT;
+ cal_x1_fixed = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_MASK) >>
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_SHIFT;
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_CM_TOP_AFE_TXTC_CTRL1_ADDR,
+ &val8);
+ cal_x2 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_MASK) >>
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_SHIFT;
+ cal_xp5_fixed = (val8 &
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_MASK) >>
+ SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_SHIFT;
+ info->caln_multiplied_by_2 = 4 * cal_x2 + 2 * cal_x1 + 2 * cal_x1_fixed + cal_xp5_fixed;
+}
+
+#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_ABS_MASK 0x1F
+#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK 0x3F
+#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT 5
+#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK 0xFC0
+#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT 6
+#define AL_SERDES_25G_RX_DIAG_LEQ_EQ_COUNT 5
+#define AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_EQ_ADDR 0
+#define AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_GAINSTAGE_ADDR 0x5
+#define AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_EVEN_ADDR 0x6
+#define AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_ODD_ADDR 0x7
+#define AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_EVEN_ADDR 0x8
+#define AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_ODD_ADDR 0x9
+#define AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_ADDR 0xF
+#define AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_MASK 0xFFF
+#define AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_EVEN_ADDR 0x11
+#define AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_ODD_ADDR 0x12
+#define AL_SERDES_25G_RX_DIAG_TBUS_EDGE_SLICER_ADDR 0x13
+#define AL_SERDES_25G_RX_DIAG_TBUS_EYE_SLICER_ADDR 0x23
+#define AL_SERDES_25G_RX_DIAG_TBUS_CDR_CLK_Q_ADDR 0x2
+#define AL_SERDES_25G_RX_DIAG_TBUS_CDR_CLK_I_ADDR 0x1
+#define AL_SERDES_25G_RX_DIAG_CDR_RXCLK_DLPF_L_ADDR 0x26
+#define AL_SERDES_25G_RX_DIAG_CDR_RXCLK_DLPF_H_ADDR 0x27
+
+static inline void al_serdes_25g_rx_diag_5bit_signed_set(uint8_t packed_val, int8_t *ptr)
+{
+ uint8_t abs, sign;
+
+ abs = packed_val & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_ABS_MASK;
+ sign = (packed_val & AL_BIT(AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT)) >>
+ AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT;
+ if (sign)
+ *ptr = abs;
+ else
+ *ptr = 0 - abs;
+}
+
+static void al_serdes_25g_rx_diag_info_get(
+ struct al_serdes_grp_obj *obj,
+ enum al_serdes_lane lane,
+ void *rx_info)
+{
+ struct al_serdes_25g_rx_diag_info *info = rx_info;
+ uint16_t val16;
+ uint8_t val8, val8_2;
+ int rc;
+ int i;
+
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_ADDR,
+ &val8);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->los_offset);
+
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_ADDR,
+ &val8);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->agc_offset);
+
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_GAINSTAGE_ADDR,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read leq_gainstage, rc %d\n",
+ __func__, rc);
+ return;
+ }
+ val8 = (uint8_t)val16;
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_gainstage_offset);
+
+ for (i = 0; i < AL_SERDES_25G_RX_DIAG_LEQ_EQ_COUNT; i++) {
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_EQ_ADDR + i,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read leq_eq %d, rc %d\n",
+ __func__, i, rc);
+ return;
+ }
+ val8 = (uint8_t)val16;
+
+ switch (i) {
+ case 0:
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq1_offset);
+ break;
+ case 1:
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq2_offset);
+ break;
+ case 2:
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq3_offset);
+ break;
+ case 3:
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq4_offset);
+ break;
+ case 4:
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq5_offset);
+ break;
+ default:
+ break;
+ }
+ }
+
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_EVEN_ADDR,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read summer_even_offset, rc %d\n",
+ __func__, rc);
+ return;
+ }
+ val8 = (uint8_t)val16;
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->summer_even_offset);
+
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_ODD_ADDR,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read summer_odd_offset, rc %d\n",
+ __func__, rc);
+ return;
+ }
+ val8 = (uint8_t)val16;
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->summer_odd_offset);
+
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_EVEN_ADDR,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read vscan_even_offset, rc %d\n",
+ __func__, rc);
+ return;
+ }
+ val8 = (uint8_t)val16;
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->vscan_even_offset);
+
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_ODD_ADDR,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read vscan_odd_offset, rc %d\n",
+ __func__, rc);
+ return;
+ }
+ val8 = (uint8_t)val16;
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->vscan_odd_offset);
+
+ al_serdes_25g_tbus_read(
+ obj,
+ lane,
+ AL_SERDES_25G_TBUS_OBJ_LANE,
+ AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_EVEN_ADDR,
+ &val16);
+ val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_even0_offset);
+ val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
+ AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_even1_offset);
+
+ al_serdes_25g_tbus_read(
+ obj,
+ lane,
+ AL_SERDES_25G_TBUS_OBJ_LANE,
+ AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_ODD_ADDR,
+ &val16);
+ val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_odd0_offset);
+ val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
+ AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_odd1_offset);
+
+ al_serdes_25g_tbus_read(
+ obj,
+ lane,
+ AL_SERDES_25G_TBUS_OBJ_LANE,
+ AL_SERDES_25G_RX_DIAG_TBUS_EDGE_SLICER_ADDR,
+ &val16);
+ val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->edge_slicer_even_offset);
+ val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
+ AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->edge_slicer_odd_offset);
+
+ al_serdes_25g_tbus_read(
+ obj,
+ lane,
+ AL_SERDES_25G_TBUS_OBJ_LANE,
+ AL_SERDES_25G_RX_DIAG_TBUS_EYE_SLICER_ADDR,
+ &val16);
+ val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->eye_slicer_even_offset);
+ val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
+ AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
+ al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->eye_slicer_odd_offset);
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_ADDR,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_MASK,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_SHIFT,
+ &info->cdr_clk_q);
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_ADDR,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_MASK,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_SHIFT,
+ &info->cdr_clk_i);
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_ADDR,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_MASK,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_SHIFT,
+ &info->cdr_dll);
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_ADDR,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_MASK,
+ SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_SHIFT,
+ &info->cdr_vco_dosc);
+
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_ADDR,
+ &val8_2);
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_ADDR,
+ &val8);
+ val8_2 &= SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_MASK;
+ info->cdr_dlpf = (uint16_t)val8_2 << 8 | val8;
+
+ rc = al_serdes_25g_gcfsm2_read(
+ obj,
+ lane,
+ AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_ADDR,
+ &val16);
+ if (rc) {
+ al_err("%s: al_serdes_25g_gcfsm2_read failed to read cdr_vco_fr, rc %d\n",
+ __func__, rc);
+ return;
+ }
+ info->cdr_vco_fr = val16 & AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_MASK;
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_ADDR,
+ SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_MASK,
+ SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_SHIFT,
+ &info->ple_resistance);
+
+ al_serdes_25g_reg_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ 0,
+ SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR,
+ &val8);
+
+ info->rx_term_mode = (val8 & SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK) >>
+ SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT;
+
+ info->rx_coupling = (val8 & SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK) >>
+ SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT;
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR,
+ SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK,
+ SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT,
+ &info->rx_term_cal_code);
+
+ al_serdes_25g_reg_masked_read(
+ obj,
+ (enum al_serdes_reg_page)lane,
+ SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_ADDR,
+ SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_MASK,
+ SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_SHIFT,
+ &info->rx_sheet_res_cal_code);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+int al_serdes_25g_handle_init(
+ void __iomem *serdes_regs_base,
+ struct al_serdes_grp_obj *obj)
+{
+ al_dbg(
+ "%s(%p, %p)\n",
+ __func__,
+ serdes_regs_base,
+ obj);
+
+ al_memset(obj, 0, sizeof(struct al_serdes_grp_obj));
+
+ obj->regs_base = (struct al_serdes_regs *)serdes_regs_base;
+ obj->type_get = al_serdes_25g_type_get;
+ obj->reg_read = al_serdes_25g_reg_read;
+ obj->reg_write = al_serdes_25g_reg_write;
+ obj->bist_overrides_enable = NULL;
+ obj->bist_overrides_disable = NULL;
+ obj->rx_rate_change = NULL;
+ obj->group_pm_set = NULL;
+ obj->lane_pm_set = NULL;
+ obj->pma_hard_reset_group = NULL;
+ obj->pma_hard_reset_lane = NULL;
+ obj->loopback_control = NULL;
+ obj->bist_pattern_select = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_pattern_select);
+ obj->bist_tx_enable = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_tx_enable);
+ obj->bist_tx_err_inject = NULL;
+ obj->bist_rx_enable = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_rx_enable);
+ obj->bist_rx_status = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_rx_status);
+ obj->tx_deemph_preset = NULL;
+ obj->tx_deemph_inc = NULL;
+ obj->tx_deemph_dec = NULL;
+ obj->eye_measure_run = NULL;
+ obj->eye_diag_sample = NULL;
+ obj->eye_diag_run = AL_SRDS_ADV_SRVC(al_serdes_25g_eye_diag_run);
+ obj->cdr_is_locked = AL_SRDS_ADV_SRVC(al_serdes_25g_cdr_is_locked);
+ obj->rx_valid = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_valid);
+ obj->signal_is_detected = AL_SRDS_ADV_SRVC(al_serdes_25g_signal_is_detected);
+ obj->tx_advanced_params_set = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_advanced_params_set);
+ obj->tx_advanced_params_get = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_advanced_params_get);
+ obj->rx_advanced_params_set = NULL;
+ obj->rx_advanced_params_get = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_advanced_params_get);
+ obj->tx_diag_info_get = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_diag_info_get);
+ obj->rx_diag_info_get = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_diag_info_get);
+ obj->mode_set_sgmii = NULL;
+ obj->mode_set_kr = NULL;
+ obj->rx_equalization = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_equalization);
+ obj->calc_eye_size = AL_SRDS_ADV_SRVC(al_serdes_25g_calc_eye_size);
+ obj->sris_config = NULL;
+
+ return 0;
+}
+
diff --git a/al_hal_serdes_25g.h b/al_hal_serdes_25g.h
new file mode 100644
index 000000000000..8865b7da94ff
--- /dev/null
+++ b/al_hal_serdes_25g.h
@@ -0,0 +1,74 @@
+/*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_serdes_api API
+ * SerDes HAL driver API
+ * @ingroup group_serdes SerDes
+ * @{
+ *
+ * @file al_hal_serdes_25g.h
+ *
+ * @brief Header file for the SerDes HAL driver
+ *
+ */
+
+#ifndef __AL_HAL_SERDES_25G_H__
+#define __AL_HAL_SERDES_25G_H__
+
+#include "al_hal_common.h"
+#include "al_hal_serdes_interface.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+int al_serdes_25g_handle_init(
+ void __iomem *serdes_regs_base,
+ struct al_serdes_grp_obj *obj);
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+}
+#endif
+
+/* *INDENT-ON* */
+#endif /* __AL_SRDS__ */
+
+/** @} end of SERDES group */
+
diff --git a/al_hal_serdes_25g_internal_regs.h b/al_hal_serdes_25g_internal_regs.h
new file mode 100644
index 000000000000..ff48f98a940f
--- /dev/null
+++ b/al_hal_serdes_25g_internal_regs.h
@@ -0,0 +1,4205 @@
+/*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef _AL_SERDES_25G_INTERNAL_REGS_H_
+#define _AL_SERDES_25G_INTERNAL_REGS_H_
+
+#ifdef _cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * TOP Registers
+ ******************************************************************************/
+#define SERDES_25G_TOP_BASE 0x00
+#define SERDES_25G_TOP_SIZE 0x200
+
+#define SERDES_25G_TOP_PHY_STAT0_ADDR 0x00
+#define SERDES_25G_TOP_PHY_CTRL0_ADDR 0x08
+#define SERDES_25G_TOP_PHY_CFG0_ADDR 0x09
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ADDR 0x30
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ADDR 0x31
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_ADDR 0x32
+#define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_ADDR 0x33
+#define SERDES_25G_TOP_AFE_ATEST_CTRL0_ADDR 0x38
+#define SERDES_25G_TOP_AFE_ATEST_CTRL1_ADDR 0x39
+#define SERDES_25G_TOP_RESET_CTRL_CM0_ADDR 0x50
+#define SERDES_25G_TOP_RESET_CTRL_LN0_ADDR 0x54
+#define SERDES_25G_TOP_RESET_CTRL_LN1_ADDR 0x55
+#define SERDES_25G_TOP_RESET_CTRL_LN2_ADDR 0x56
+#define SERDES_25G_TOP_RESET_CTRL_LN3_ADDR 0x57
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_ADDR 0x100
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_ADDR 0x101
+#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_ADDR 0x102
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_ADDR 0x103
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_ADDR 0x104
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_ADDR 0x105
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_ADDR 0x106
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_ADDR 0x107
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_ADDR 0x108
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_ADDR 0x109
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_ADDR 0x10A
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_ADDR 0x110
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_ADDR 0x111
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR 0x112
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_ADDR 0x113
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_ADDR 0x118
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_ADDR 0x119
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR 0x11A
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RXDIV_CORE_ADDR 0x11B
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_ADDR 0x120
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_ADDR 0x121
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_ADDR 0x122
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RXDIV_CORE_ADDR 0x123
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_ADDR 0x128
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_ADDR 0x129
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_ADDR 0x12A
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RXDIV_CORE_ADDR 0x12B
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_ADDR 0x130
+#define SERDES_25G_TOP_INT0_STATUS_ADDR 0x131
+#define SERDES_25G_TOP_REGBUS_TIMER_ADDR 0x170
+#define SERDES_25G_TOP_ERR_CTRL0_ADDR 0x180
+#define SERDES_25G_TOP_ERR_CTRL1_ADDR 0x181
+#define SERDES_25G_TOP_ERR_CTRL2_ADDR 0x182
+#define SERDES_25G_TOP_ERR_STATUS0_ADDR 0x185
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_ADDR 0x187
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ADDR 0x188
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_ADDR 0x189
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_ADDR 0x18A
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_ADDR 0x18B
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_ADDR 0x18C
+#define SERDES_25G_TOP_TBUS_ADDR_7_0_ADDR 0x1A0
+#define SERDES_25G_TOP_TBUS_ADDR_15_8_ADDR 0x1A1
+#define SERDES_25G_TOP_TBUS_CTRL0_ADDR 0x1A2
+#define SERDES_25G_TOP_TBUS_CTRL1_ADDR 0x1A3
+#define SERDES_25G_TOP_TBUS_DATA_7_0_ADDR 0x1B0
+#define SERDES_25G_TOP_TBUS_DATA_11_8_ADDR 0x1B1
+#define SERDES_25G_TOP_SIM_CTRL_ADDR 0x1C0
+
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_TOP_PHY_STAT0_PHY_CTRL_CFG_MASK 0x0F
+#define SERDES_25G_TOP_PHY_STAT0_PHY_CTRL_CFG_SHIFT 0
+
+#define SERDES_25G_TOP_PHY_CTRL0_PHY_CTRL_CFG_OVR_VAL_MASK 0x0F
+#define SERDES_25G_TOP_PHY_CTRL0_PHY_CTRL_CFG_OVR_VAL_SHIFT 0
+
+#define SERDES_25G_TOP_PHY_CTRL0_OVR_EN_MASK 0x80
+#define SERDES_25G_TOP_PHY_CTRL0_OVR_EN_SHIFT 7
+
+#define SERDES_25G_TOP_PHY_CFG0_CPU_CLK_FREQ_MASK 0xFF
+#define SERDES_25G_TOP_PHY_CFG0_CPU_CLK_FREQ_SHIFT 0
+
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ACAL_EN_MASK 0x0F
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ACAL_EN_SHIFT 0
+
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ACAL_SEL_MASK 0x1F
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ACAL_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_EN_MASK 0x01
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_EN_SHIFT 0
+
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_MUTE_MASK 0x02
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_MUTE_SHIFT 1
+
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SEL_MASK 0x04
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SEL_SHIFT 2
+
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SPARE_MASK 0xF0
+#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SPARE_SHIFT 4
+
+#define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_CALCOMP_OUT_MASK 0x01
+#define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_CALCOMP_OUT_SHIFT 0
+
+#define SERDES_25G_TOP_AFE_ATEST_CTRL0_ATEST_EN_MASK 0x0F
+#define SERDES_25G_TOP_AFE_ATEST_CTRL0_ATEST_EN_SHIFT 0
+
+#define SERDES_25G_TOP_AFE_ATEST_CTRL1_ATEST_SEL_MASK 0x3F
+#define SERDES_25G_TOP_AFE_ATEST_CTRL1_ATEST_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_RESET_CTRL_CM0_CORE_SW_RESET_MASK 0x01
+#define SERDES_25G_TOP_RESET_CTRL_CM0_CORE_SW_RESET_SHIFT 0
+
+#define SERDES_25G_TOP_RESET_CTRL_CM0_REG_SW_RESET_MASK 0x02
+#define SERDES_25G_TOP_RESET_CTRL_CM0_REG_SW_RESET_SHIFT 1
+
+#define SERDES_25G_TOP_RESET_CTRL_CM0_SUBCORE_SW_RESET_MASK 0x04
+#define SERDES_25G_TOP_RESET_CTRL_CM0_SUBCORE_SW_RESET_SHIFT 2
+
+#define SERDES_25G_TOP_RESET_CTRL_CM0_CAL_SW_RESET_MASK 0x40
+#define SERDES_25G_TOP_RESET_CTRL_CM0_CAL_SW_RESET_SHIFT 6
+
+#define SERDES_25G_TOP_RESET_CTRL_LN0_CORE_SW_RESET_MASK 0x01
+#define SERDES_25G_TOP_RESET_CTRL_LN0_CORE_SW_RESET_SHIFT 0
+
+#define SERDES_25G_TOP_RESET_CTRL_LN0_REG_SW_RESET_MASK 0x02
+#define SERDES_25G_TOP_RESET_CTRL_LN0_REG_SW_RESET_SHIFT 1
+
+#define SERDES_25G_TOP_RESET_CTRL_LN0_SUBCORE_SW_RESET_MASK 0x04
+#define SERDES_25G_TOP_RESET_CTRL_LN0_SUBCORE_SW_RESET_SHIFT 2
+
+#define SERDES_25G_TOP_RESET_CTRL_LN0_TXDP_SW_RESET_MASK 0x08
+#define SERDES_25G_TOP_RESET_CTRL_LN0_TXDP_SW_RESET_SHIFT 3
+
+#define SERDES_25G_TOP_RESET_CTRL_LN0_RXDP_SW_RESET_MASK 0x10
+#define SERDES_25G_TOP_RESET_CTRL_LN0_RXDP_SW_RESET_SHIFT 4
+
+#define SERDES_25G_TOP_RESET_CTRL_LN0_LOS_SW_RESET_MASK 0x20
+#define SERDES_25G_TOP_RESET_CTRL_LN0_LOS_SW_RESET_SHIFT 5
+
+#define SERDES_25G_TOP_RESET_CTRL_LN0_CAL_SW_RESET_MASK 0x40
+#define SERDES_25G_TOP_RESET_CTRL_LN0_CAL_SW_RESET_SHIFT 6
+
+#define SERDES_25G_TOP_RESET_CTRL_LN1_CORE_SW_RESET_MASK 0x01
+#define SERDES_25G_TOP_RESET_CTRL_LN1_CORE_SW_RESET_SHIFT 0
+
+#define SERDES_25G_TOP_RESET_CTRL_LN1_REG_SW_RESET_MASK 0x02
+#define SERDES_25G_TOP_RESET_CTRL_LN1_REG_SW_RESET_SHIFT 1
+
+#define SERDES_25G_TOP_RESET_CTRL_LN1_SUBCORE_SW_RESET_MASK 0x04
+#define SERDES_25G_TOP_RESET_CTRL_LN1_SUBCORE_SW_RESET_SHIFT 2
+
+#define SERDES_25G_TOP_RESET_CTRL_LN1_TXDP_SW_RESET_MASK 0x08
+#define SERDES_25G_TOP_RESET_CTRL_LN1_TXDP_SW_RESET_SHIFT 3
+
+#define SERDES_25G_TOP_RESET_CTRL_LN1_RXDP_SW_RESET_MASK 0x10
+#define SERDES_25G_TOP_RESET_CTRL_LN1_RXDP_SW_RESET_SHIFT 4
+
+#define SERDES_25G_TOP_RESET_CTRL_LN1_LOS_SW_RESET_MASK 0x20
+#define SERDES_25G_TOP_RESET_CTRL_LN1_LOS_SW_RESET_SHIFT 5
+
+#define SERDES_25G_TOP_RESET_CTRL_LN1_CAL_SW_RESET_MASK 0x40
+#define SERDES_25G_TOP_RESET_CTRL_LN1_CAL_SW_RESET_SHIFT 6
+
+#define SERDES_25G_TOP_RESET_CTRL_LN2_CORE_SW_RESET_MASK 0x01
+#define SERDES_25G_TOP_RESET_CTRL_LN2_CORE_SW_RESET_SHIFT 0
+
+#define SERDES_25G_TOP_RESET_CTRL_LN2_REG_SW_RESET_MASK 0x02
+#define SERDES_25G_TOP_RESET_CTRL_LN2_REG_SW_RESET_SHIFT 1
+
+#define SERDES_25G_TOP_RESET_CTRL_LN2_SUBCORE_SW_RESET_MASK 0x04
+#define SERDES_25G_TOP_RESET_CTRL_LN2_SUBCORE_SW_RESET_SHIFT 2
+
+#define SERDES_25G_TOP_RESET_CTRL_LN2_TXDP_SW_RESET_MASK 0x08
+#define SERDES_25G_TOP_RESET_CTRL_LN2_TXDP_SW_RESET_SHIFT 3
+
+#define SERDES_25G_TOP_RESET_CTRL_LN2_RXDP_SW_RESET_MASK 0x10
+#define SERDES_25G_TOP_RESET_CTRL_LN2_RXDP_SW_RESET_SHIFT 4
+
+#define SERDES_25G_TOP_RESET_CTRL_LN2_LOS_SW_RESET_MASK 0x20
+#define SERDES_25G_TOP_RESET_CTRL_LN2_LOS_SW_RESET_SHIFT 5
+
+#define SERDES_25G_TOP_RESET_CTRL_LN2_CAL_SW_RESET_MASK 0x40
+#define SERDES_25G_TOP_RESET_CTRL_LN2_CAL_SW_RESET_SHIFT 6
+
+#define SERDES_25G_TOP_RESET_CTRL_LN3_CORE_SW_RESET_MASK 0x01
+#define SERDES_25G_TOP_RESET_CTRL_LN3_CORE_SW_RESET_SHIFT 0
+
+#define SERDES_25G_TOP_RESET_CTRL_LN3_REG_SW_RESET_MASK 0x02
+#define SERDES_25G_TOP_RESET_CTRL_LN3_REG_SW_RESET_SHIFT 1
+
+#define SERDES_25G_TOP_RESET_CTRL_LN3_SUBCORE_SW_RESET_MASK 0x04
+#define SERDES_25G_TOP_RESET_CTRL_LN3_SUBCORE_SW_RESET_SHIFT 2
+
+#define SERDES_25G_TOP_RESET_CTRL_LN3_TXDP_SW_RESET_MASK 0x08
+#define SERDES_25G_TOP_RESET_CTRL_LN3_TXDP_SW_RESET_SHIFT 3
+
+#define SERDES_25G_TOP_RESET_CTRL_LN3_RXDP_SW_RESET_MASK 0x10
+#define SERDES_25G_TOP_RESET_CTRL_LN3_RXDP_SW_RESET_SHIFT 4
+
+#define SERDES_25G_TOP_RESET_CTRL_LN3_LOS_SW_RESET_MASK 0x20
+#define SERDES_25G_TOP_RESET_CTRL_LN3_LOS_SW_RESET_SHIFT 5
+
+#define SERDES_25G_TOP_RESET_CTRL_LN3_CAL_SW_RESET_MASK 0x40
+#define SERDES_25G_TOP_RESET_CTRL_LN3_CAL_SW_RESET_SHIFT 6
+
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_SRC_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_DEFAULT_CLK_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_DEFAULT_CLK_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_REF_CLK_EN_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_REF_CLK_EN_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_DIV_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_DIV_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_CG_EN_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_CG_EN_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_DIV_SEL_MASK 0x07
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_DIV_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_DIV_SEL_MASK 0x07
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_DIV_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_DIV_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_DIV_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_CG_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_CG_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_SRC_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_DEFAULT_CLK_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_DEFAULT_CLK_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_CMU_CLK_EN_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_CMU_CLK_EN_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_DIV_SEL_MASK 0xF8
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_DIV_SEL_SHIFT 3
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_SRC_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_DEFAULT_CLK_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_DEFAULT_CLK_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_CMUDIV_CLK_EN_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_CMUDIV_CLK_EN_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_DIV_SEL_MASK 0xF8
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_DIV_SEL_SHIFT 3
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_FRCDIV_MODE_EN_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_FRCDIV_MODE_EN_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_SRC_SEL_MASK 0x06
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_SRC_SEL_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_DIV_SEL_MASK 0x08
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_DIV_SEL_SHIFT 3
+
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_MASK 0x03
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_DIV_SEL_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_DIV_SEL_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4
+
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_SRC_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_RX_CLK_EN_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_RX_CLK_EN_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_SRC_SEL_MASK 0x03
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_MASK 0x10
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_SHIFT 4
+
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5
+
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_SRC_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_DEFAULT_CLK_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_DEFAULT_CLK_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_RX_CLKDIV_EN_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_RX_CLKDIV_EN_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_MASK 0x03
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_DIV_SEL_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_DIV_SEL_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4
+
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_SRC_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_RX_CLK_EN_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_RX_CLK_EN_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_SRC_SEL_MASK 0x03
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_MASK 0x10
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_SHIFT 4
+
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5
+
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_MASK 0x03
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_DIV_SEL_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_DIV_SEL_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4
+
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_SRC_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_RX_CLK_EN_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_RX_CLK_EN_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_SRC_SEL_MASK 0x03
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_MASK 0x10
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_SHIFT 4
+
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5
+
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_MASK 0x03
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_DIV_SEL_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_DIV_SEL_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4
+
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_SRC_SEL_MASK 0x01
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_RX_CLK_EN_MASK 0x04
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_RX_CLK_EN_SHIFT 2
+
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_SRC_SEL_MASK 0x03
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_MASK 0x10
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_SHIFT 4
+
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5
+
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80
+#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7
+
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN0_MASK 0x01
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN0_SHIFT 0
+
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN1_MASK 0x02
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN1_SHIFT 1
+
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN2_MASK 0x04
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN2_SHIFT 2
+
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN3_MASK 0x08
+#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN3_SHIFT 3
+
+#define SERDES_25G_TOP_REGBUS_TIMER_LOAD_VAL_MASK 0xFF
+#define SERDES_25G_TOP_REGBUS_TIMER_LOAD_VAL_SHIFT 0
+
+#define SERDES_25G_TOP_ERR_CTRL0_ERR_MASK 0x01
+#define SERDES_25G_TOP_ERR_CTRL0_ERR_SHIFT 0
+
+#define SERDES_25G_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF
+#define SERDES_25G_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0
+
+#define SERDES_25G_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF
+#define SERDES_25G_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0
+
+#define SERDES_25G_TOP_ERR_STATUS0_REGBUS_ERR_MASK 0x01
+#define SERDES_25G_TOP_ERR_STATUS0_REGBUS_ERR_SHIFT 0
+
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_CLR_MASK 0x01
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_CLR_SHIFT 0
+
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_MASK 0x03
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_SHIFT 0
+
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_MASK 0x04
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_SHIFT 2
+
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_TRANSFER_ADDR_LSB_MASK 0xFF
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_TRANSFER_ADDR_LSB_SHIFT 0
+
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_MASK 0x7F
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_SHIFT 0
+
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_TRANSFER_WD_MASK 0xFF
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_TRANSFER_WD_SHIFT 0
+
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_TRANSFER_WR_BIT_EN_MASK 0xFF
+#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_TRANSFER_WR_BIT_EN_SHIFT 0
+
+#define SERDES_25G_TOP_TBUS_ADDR_7_0_MASK 0xFF
+#define SERDES_25G_TOP_TBUS_ADDR_7_0_SHIFT 0
+
+#define SERDES_25G_TOP_TBUS_ADDR_15_8_MASK 0xFF
+#define SERDES_25G_TOP_TBUS_ADDR_15_8_SHIFT 0
+
+#define SERDES_25G_TOP_TBUS_CTRL0_CLOCK_GATE0_MASK 0xFF
+#define SERDES_25G_TOP_TBUS_CTRL0_CLOCK_GATE0_SHIFT 0
+
+#define SERDES_25G_TOP_TBUS_CTRL1_CLOCK_GATE1_MASK 0xFF
+#define SERDES_25G_TOP_TBUS_CTRL1_CLOCK_GATE1_SHIFT 0
+
+#define SERDES_25G_TOP_TBUS_DATA_7_0_MASK 0xFF
+#define SERDES_25G_TOP_TBUS_DATA_7_0_SHIFT 0
+
+#define SERDES_25G_TOP_TBUS_DATA_11_8_MASK 0x0F
+#define SERDES_25G_TOP_TBUS_DATA_11_8_SHIFT 0
+
+/*********************************** Mailbox **********************************/
+#define SERDES_25G_TOP_MB_BASE 0x200
+
+#define SERDES_25G_TOP_CMD_ADDR (SERDES_25G_TOP_MB_BASE + 0x00)
+#define SERDES_25G_TOP_CMD_FLAG_ADDR (SERDES_25G_TOP_MB_BASE + 0x02)
+#define SERDES_25G_TOP_CMD_DATA0_ADDR (SERDES_25G_TOP_MB_BASE + 0x03)
+#define SERDES_25G_TOP_CMD_DATA1_ADDR (SERDES_25G_TOP_MB_BASE + 0x04)
+#define SERDES_25G_TOP_CMD_DATA2_ADDR (SERDES_25G_TOP_MB_BASE + 0x05)
+#define SERDES_25G_TOP_CMD_DATA3_ADDR (SERDES_25G_TOP_MB_BASE + 0x06)
+#define SERDES_25G_TOP_CMD_DATA4_ADDR (SERDES_25G_TOP_MB_BASE + 0x07)
+#define SERDES_25G_TOP_CMD_DATA5_ADDR (SERDES_25G_TOP_MB_BASE + 0x08)
+#define SERDES_25G_TOP_CMD_DATA6_ADDR (SERDES_25G_TOP_MB_BASE + 0x09)
+#define SERDES_25G_TOP_CMD_DATA7_ADDR (SERDES_25G_TOP_MB_BASE + 0x0A)
+#define SERDES_25G_TOP_RSP_ADDR (SERDES_25G_TOP_MB_BASE + 0x10)
+#define SERDES_25G_TOP_RSP_FLAG_ADDR (SERDES_25G_TOP_MB_BASE + 0x12)
+#define SERDES_25G_TOP_RSP_DATA0_ADDR (SERDES_25G_TOP_MB_BASE + 0x13)
+#define SERDES_25G_TOP_RSP_DATA1_ADDR (SERDES_25G_TOP_MB_BASE + 0x14)
+#define SERDES_25G_TOP_RSP_DATA2_ADDR (SERDES_25G_TOP_MB_BASE + 0x15)
+#define SERDES_25G_TOP_RSP_DATA3_ADDR (SERDES_25G_TOP_MB_BASE + 0x16)
+#define SERDES_25G_TOP_RSP_DATA4_ADDR (SERDES_25G_TOP_MB_BASE + 0x17)
+#define SERDES_25G_TOP_RSP_DATA5_ADDR (SERDES_25G_TOP_MB_BASE + 0x18)
+#define SERDES_25G_TOP_RSP_DATA6_ADDR (SERDES_25G_TOP_MB_BASE + 0x19)
+#define SERDES_25G_TOP_RSP_DATA7_ADDR (SERDES_25G_TOP_MB_BASE + 0x1A)
+#define SERDES_25G_TOP_RSP_DATA8_ADDR (SERDES_25G_TOP_MB_BASE + 0x1B)
+#define SERDES_25G_TOP_RSP_DATA9_ADDR (SERDES_25G_TOP_MB_BASE + 0x1C)
+#define SERDES_25G_TOP_RSP_DATA10_ADDR (SERDES_25G_TOP_MB_BASE + 0x1D)
+#define SERDES_25G_TOP_RSP_DATA11_ADDR (SERDES_25G_TOP_MB_BASE + 0x1E)
+#define SERDES_25G_TOP_RSP_DATA12_ADDR (SERDES_25G_TOP_MB_BASE + 0x1F)
+#define SERDES_25G_TOP_RSP_DATA13_ADDR (SERDES_25G_TOP_MB_BASE + 0x20)
+#define SERDES_25G_TOP_RSP_DATA14_ADDR (SERDES_25G_TOP_MB_BASE + 0x21)
+#define SERDES_25G_TOP_RSP_DATA15_ADDR (SERDES_25G_TOP_MB_BASE + 0x22)
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_TOP_CMD_MASK 0xFF
+#define SERDES_25G_TOP_CMD_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_FLAG_MASK 0x01
+#define SERDES_25G_TOP_CMD_FLAG_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_DATA0_MASK 0xFF
+#define SERDES_25G_TOP_CMD_DATA0_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_DATA1_MASK 0xFF
+#define SERDES_25G_TOP_CMD_DATA1_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_DATA2_MASK 0xFF
+#define SERDES_25G_TOP_CMD_DATA2_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_DATA3_MASK 0xFF
+#define SERDES_25G_TOP_CMD_DATA3_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_DATA4_MASK 0xFF
+#define SERDES_25G_TOP_CMD_DATA4_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_DATA5_MASK 0xFF
+#define SERDES_25G_TOP_CMD_DATA5_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_DATA6_MASK 0xFF
+#define SERDES_25G_TOP_CMD_DATA6_SHIFT 0
+
+#define SERDES_25G_TOP_CMD_DATA7_MASK 0xFF
+#define SERDES_25G_TOP_CMD_DATA7_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_MASK 0xFF
+#define SERDES_25G_TOP_RSP_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_FLAG_MASK 0x01
+#define SERDES_25G_TOP_RSP_FLAG_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA0_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA0_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA1_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA1_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA2_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA2_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA3_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA3_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA4_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA4_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA5_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA5_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA6_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA6_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA7_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA7_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA8_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA8_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA9_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA9_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA10_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA10_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA11_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA11_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA12_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA12_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA13_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA13_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA14_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA14_SHIFT 0
+
+#define SERDES_25G_TOP_RSP_DATA15_MASK 0xFF
+#define SERDES_25G_TOP_RSP_DATA15_SHIFT 0
+
+/*******************************************************************************
+ * Common Registers
+ ******************************************************************************/
+#define SERDES_25G_CM_BASE 0xC00
+#define SERDES_25G_CM_SIZE 0x400
+
+#define SERDES_25G_CM_TOP_AFE_PD_CTRL0_ADDR 0x00
+#define SERDES_25G_CM_TOP_AFE_PD_CTRL1_ADDR 0x01
+#define SERDES_25G_CM_TOP_AFE_RST_CTRL0_ADDR 0x03
+#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL0_ADDR 0x05
+#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL1_ADDR 0x06
+#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL2_ADDR 0x07
+#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL3_ADDR 0x08
+#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL4_ADDR 0x09
+#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL5_ADDR 0x0A
+#define SERDES_25G_CM_TOP_AFE_REG_CTRL0_ADDR 0x0C
+#define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL0_ADDR 0x1A
+#define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL1_ADDR 0x1B
+#define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL2_ADDR 0x1F
+#define SERDES_25G_CM_TOP_AFE_CMCP_CTRL0_ADDR 0x20
+#define SERDES_25G_CM_TOP_AFE_CMCP_CTRL1_ADDR 0x21
+#define SERDES_25G_CM_TOP_AFE_CMCP_CTRL2_ADDR 0x22
+#define SERDES_25G_CM_TOP_AFE_MISC_CTRL0_ADDR 0x23
+#define SERDES_25G_CM_TOP_AFE_CMCP_STATUS_ADDR 0x24
+#define SERDES_25G_CM_TOP_AFE_TOGGLE_CTRL0_ADDR 0x25
+#define SERDES_25G_CM_TOP_AFE_TSTCLK_CTRL0_ADDR 0x28
+#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL0_ADDR 0x30
+#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL1_ADDR 0x31
+#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL2_ADDR 0x32
+#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL3_ADDR 0x33
+#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL4_ADDR 0x34
+#define SERDES_25G_CM_TOP_PWR_STATE_REQ_STATUS_ADDR 0x50
+#define SERDES_25G_CM_TOP_PWR_STATE_ACK_CTRL_ADDR 0x51
+#define SERDES_25G_CM_TOP_PHY_IF_STATUS_ADDR 0x52
+#define SERDES_25G_CM_TOP_CMU_TOP_SPARE0_ADDR 0x58
+#define SERDES_25G_CM_TOP_CMU_TOP_SPARE1_ADDR 0x59
+#define SERDES_25G_CM_TOP_ERR_CTRL1_ADDR 0x80
+#define SERDES_25G_CM_TOP_ERR_CTRL2_ADDR 0x81
+#define SERDES_25G_CM_TOP_ERR_CTRL3_ADDR 0x82
+#define SERDES_25G_CM_TOP_CMU_IF_OVR_CTRL0_ADDR 0x8A
+#define SERDES_25G_CM_TOP_CMU_IF_OVR_CTRL1_ADDR 0x8B
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_MASK 0x01
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICV_MASK 0x02
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICV_SHIFT 1
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICC_MASK 0x04
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICC_SHIFT 2
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_IPTAT_MASK 0x08
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_IPTAT_SHIFT 3
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SLAVE_MASK 0x10
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SLAVE_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REG_REF_MASK 0x20
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REG_REF_SHIFT 5
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REFCLK_MASK 0x40
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REFCLK_SHIFT 6
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_MASK 0x01
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_LEFT_MASK 0x02
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_LEFT_SHIFT 1
+
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_RIGHT_MASK 0x04
+#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_RIGHT_SHIFT 2
+
+#define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMU_N_MASK 0x01
+#define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMU_N_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMUDIV_N_MASK 0x02
+#define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMUDIV_N_SHIFT 1
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICV_TRIM_MASK 0x0F
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICV_TRIM_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICC_TRIM_MASK 0xF0
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICC_TRIM_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL1_BIAS_IPTAT_TRIM_MASK 0x0F
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL1_BIAS_IPTAT_TRIM_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_BGSTART_BYP_MASK 0x01
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_BGSTART_BYP_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_IPTATSTART_BYP_MASK 0x02
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_IPTATSTART_BYP_SHIFT 1
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_TERMCAL_EN_MASK 0x04
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_TERMCAL_EN_SHIFT 2
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_PTRIM_MASK 0x0F
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_PTRIM_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_NTRIM_MASK 0xF0
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_NTRIM_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL4_BIAS_SPARE_MASK 0x0F
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL4_BIAS_SPARE_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL5_BIAS_CALREF_TRIM_MASK 0x0F
+#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL5_BIAS_CALREF_TRIM_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_PASS_EN_MASK 0x01
+#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_PASS_EN_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRIM_MASK 0x0E
+#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRIM_SHIFT 1
+
+#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRICKLE_MASK 0x30
+#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRICKLE_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DIV_MASK 0x03
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DIV_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DPL_DIV_MASK 0x0C
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DPL_DIV_SHIFT 2
+
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DEGLITCH_OVR_MASK 0x10
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DEGLITCH_OVR_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL1_REFCLK_TERM_MASK 0x1F
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL1_REFCLK_TERM_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL2_REFCLK_SPARE_MASK 0x0F
+#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL2_REFCLK_SPARE_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_QSAMPLE_EN_MASK 0x01
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_QSAMPLE_EN_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_DCD_RANGE_MASK 0x02
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_DCD_RANGE_SHIFT 1
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUCLK_DIV_MASK 0x1C
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUCLK_DIV_SHIFT 2
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_MASK 0xE0
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_SHIFT 5
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CLKDIV_SWING_MASK 0x03
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CLKDIV_SWING_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_TXCLK_SWING_MASK 0x0C
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_TXCLK_SWING_SHIFT 2
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CMUCLK_DIV2_BYPASS_MASK 0x10
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CMUCLK_DIV2_BYPASS_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_CLKDIV_OVR_MASK 0x03
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_CLKDIV_OVR_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_BIASI_MASK 0x0C
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_BIASI_SHIFT 2
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_DIV_MASK 0x70
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_DIV_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_DIV1P5_DUMMY_EN_MASK 0x80
+#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_DIV1P5_DUMMY_EN_SHIFT 7
+
+#define SERDES_25G_CMU_TOP_AFE_MISC_CTRL0_CMCP_SPARE_MASK 0xFF
+#define SERDES_25G_CMU_TOP_AFE_MISC_CTRL0_CMCP_SPARE_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_CMCP_STATUS_CMCP_DIV1P5_QSAMPLE_MASK 0x0F
+#define SERDES_25G_CMU_TOP_AFE_CMCP_STATUS_CMCP_DIV1P5_QSAMPLE_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CLK_TOGGLE_EN_MASK 0x01
+#define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CLK_TOGGLE_EN_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CMCP_TOGGLE_EN_MASK 0x02
+#define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CMCP_TOGGLE_EN_SHIFT 1
+
+#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_MASK 0x03
+#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_MASK 0x1C
+#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_SHIFT 2
+
+#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_SWING_MASK 0x60
+#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_SWING_SHIFT 5
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_MASK 0x07
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_MASK 0x18
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_SHIFT 3
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_MASK 0x1F
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_MASK 0x60
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_SHIFT 5
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_MASK 0x07
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_MASK 0x18
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_SHIFT 3
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_MASK 0x1F
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_MASK 0x60
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_SHIFT 5
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_NEG_MASK 0x07
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_NEG_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_POS_MASK 0x70
+#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_POS_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07
+#define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08
+#define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3
+
+#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07
+#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08
+#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3
+
+#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70
+#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4
+
+#define SERDES_25G_CMU_TOP_PHY_IF_STATUS_CMU_OK_MASK 0x01
+#define SERDES_25G_CMU_TOP_PHY_IF_STATUS_CMU_OK_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_CMU_TOP_SPARE0_MASK 0xFF
+#define SERDES_25G_CMU_TOP_CMU_TOP_SPARE0_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_CMU_TOP_SPARE1_MASK 0xFF
+#define SERDES_25G_CMU_TOP_CMU_TOP_SPARE1_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF
+#define SERDES_25G_CMU_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF
+#define SERDES_25G_CMU_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_ERR_CTRL3_CMU_ERR__MASK 0x01
+#define SERDES_25G_CMU_TOP_ERR_CTRL3_CMU_ERR__SHIFT 0
+
+#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_EN_MASK 0x01
+#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_EN_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_VAL_MASK 0x06
+#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_VAL_SHIFT 1
+
+#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_EN_MASK 0x01
+#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_EN_SHIFT 0
+
+#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_VAL_MASK 0x02
+#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_VAL_SHIFT 1
+
+
+/*******************************************************************************
+ * Lane Registers
+ ******************************************************************************/
+#define SERDES_25G_LANE_BASE 0x1800
+#define SERDES_25G_LANE_SIZE 0x800
+
+/********************************** LANE_TOP **********************************/
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_ADDR 0x00
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_ADDR 0x01
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_ADDR 0x02
+#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_ADDR 0x03
+#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_ADDR 0x04
+#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_ADDR 0x05
+#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_ADDR 0x06
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR 0x10
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_ADDR 0x12
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_ADDR 0x13
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_ADDR 0x14
+#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_ADDR 0x16
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_ADDR 0x19
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR 0x1B
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR 0x1C
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR 0x22
+#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_ADDR 0x24
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_ADDR 0x25
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ADDR 0x26
+#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_ADDR 0x27
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_ADDR 0x30
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_ADDR 0x31
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR 0x38
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_ADDR 0x39
+#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_ADDR 0x3A
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_ADDR 0x3B
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_ADDR 0x3C
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_ADDR 0x3D
+#define SERDES_25G_LANE_TOP_ERR_CTRL1_ADDR 0x40
+#define SERDES_25G_LANE_TOP_ERR_CTRL2_ADDR 0x41
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_MASK 0x02
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_MASK 0x04
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_MASK 0x08
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_MASK 0x02
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_MASK 0x02
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_MASK 0x04
+#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_MASK 0x0F
+#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK 0x0F
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_MASK 0x30
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_MASK 0x40
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_SHIFT 6
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_MASK 0x06
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_MASK 0x0F
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_MASK 0x03
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_MASK 0x04
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_MASK 0xF0
+#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_MASK 0x07
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_MASK 0xF0
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_MASK 0x07
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK 0x08
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK 0x10
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK 0x1F
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK 0x03
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_MASK 0x04
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_MASK 0x10
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_MASK 0x01
+#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_MASK 0x01
+#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_MASK 0x07
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_MASK 0x38
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_MASK 0x07
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_MASK 0x38
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_MASK 0x02
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_MASK 0x02
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_MASK 0x04
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_MASK 0x08
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_MASK 0x10
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_MASK 0x20
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_SHIFT 5
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_MASK 0x40
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_SHIFT 6
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_MASK 0x06
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_MASK 0x08
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_MASK 0x02
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF
+#define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF
+#define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0
+
+/********************************* Lane CDR RXCLK ***************************/
+#define SERDES_25G_LANE_CDR_RXCLK_BASE 0x80
+
+#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x10)
+#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x11)
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x21)
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x22)
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x26)
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x27)
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x28)
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x29)
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2A)
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2B)
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2D)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x30)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x31)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x32)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x34)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x36)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x37)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x39)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3A)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3B)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3C)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3D)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3E)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3F)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x40)
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x41)
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x44)
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x45)
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x46)
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x48)
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x49)
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4A)
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4B)
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4C)
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4D)
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4E)
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4F)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x60)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x61)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x62)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x63)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x68)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x69)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6A)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6B)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6C)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6D)
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6E)
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_DLPF_SRC_SEL_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_DLPF_SRC_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_CFG_DOSC_MIN_MASK 0x07
+#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_CFG_DOSC_MIN_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DECIMATION_MODE_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DECIMATION_MODE_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DLPF_MODE_MASK 0x30
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DLPF_MODE_SHIFT 4
+
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_PD_OUT_MASK_MASK 0x03
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_PD_OUT_MASK_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_DLPF_VAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_DLPF_VAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_DLPF_DITHER_VAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_DLPF_DITHER_VAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_DLPF_DITHER_VAL_10_8_MASK 0x07
+#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_DLPF_DITHER_VAL_10_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_DLPF_VAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_DLPF_VAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_DLPF_VAL_8_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_DLPF_VAL_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_EN_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_EN_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_NUM_DITHER_BITS_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_NUM_DITHER_BITS_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_HIGH_THRESHOLD_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_HIGH_THRESHOLD_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_HIGH_THRESHOLD_8_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_HIGH_THRESHOLD_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_HIGH_COUNT_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_HIGH_COUNT_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_LOW_THRESHOLD_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_LOW_THRESHOLD_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_LOW_THRESHOLD_8_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_LOW_THRESHOLD_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_LOW_COUNT_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_LOW_COUNT_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCK_EN_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCK_EN_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCKL_EN_MASK 0x02
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCKL_EN_SHIFT 1
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_HIGH_EN_MASK 0x04
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_HIGH_EN_SHIFT 2
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOW_EN_MASK 0x08
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOW_EN_SHIFT 3
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_OUTPUT_SAMPLE_PERIOD_MASK 0x3F
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_OUTPUT_SAMPLE_PERIOD_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_GREY_VAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_GREY_VAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_GREY_VAL_8_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_GREY_VAL_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_BINARY_VAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_BINARY_VAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_MASK 0x02
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_SHIFT 1
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_MASK 0x04
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_SHIFT 2
+
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ACCUMULATOR_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ACCUMULATOR_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ACCUMULATOR_15_8_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ACCUMULATOR_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_DITHER_BITS_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_DITHER_BITS_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_SAMPLE_PERIOD_MASK 0xF0
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_SAMPLE_PERIOD_SHIFT 4
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_NUM_SAMPLES_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_NUM_SAMPLES_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_SLOPE_THRESHOLD_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_SLOPE_THRESHOLD_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_RANGE_THRESHOLD_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_RANGE_THRESHOLD_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_DITHER_BITS_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_DITHER_BITS_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_SAMPLE_PERIOD_MASK 0xF0
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_SAMPLE_PERIOD_SHIFT 4
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_NUM_SAMPLES_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_NUM_SAMPLES_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_SLOPE_THRESHOLD_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_SLOPE_THRESHOLD_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_RANGE_THRESHOLD_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_RANGE_THRESHOLD_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_EN_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_SAMPLE_DROP_BITS_MASK 0x07
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_SAMPLE_DROP_BITS_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_NUM_PEAKS_MASK 0xF0
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_NUM_PEAKS_SHIFT 4
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_PEAK2PEAK_PERIOD_MIN_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_PEAK2PEAK_PERIOD_MIN_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_PEAK2PEAK_PERIOD_MAX_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_PEAK2PEAK_PERIOD_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_DONE_MASK 0x01
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_DONE_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_NOISY_MASK 0x02
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_NOISY_SHIFT 1
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_SLOW_MASK 0x04
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_SLOW_SHIFT 2
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_VAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_VAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_VAL_15_8_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_VAL_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_VAL_19_16_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_VAL_19_16_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_VAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_VAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_VAL_15_8_MASK 0xFF
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_VAL_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_VAL_19_16_MASK 0x0F
+#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_VAL_19_16_SHIFT 0
+
+/********************************* Lane CDR_REFCLK ***************************/
+#define SERDES_25G_LANE_CDR_REFCLK_BASE 0x180
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x00)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x01)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x06)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0A)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0B)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0C)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x10)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x11)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x18)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x19)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x1A)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x1B)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x20)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x21)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x22)
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x24)
+#define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x30)
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_MASK 0x01
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_EYE_MASK 0x02
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_EYE_SHIFT 1
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_RXCDR_TOGGLE_EN_MASK 0x04
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_RXCDR_TOGGLE_EN_SHIFT 2
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_RXCDR_PHD_EN_MASK 0xFF
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_RXCDR_PHD_EN_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_PHD_N_MASK 0x01
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_PHD_N_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_CLKDIV_N_MASK 0x02
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_CLKDIV_N_SHIFT 1
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_RXCDR_VCO_KICK_MASK 0x01
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_RXCDR_VCO_KICK_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REGDAC_BANDWIDTH_MASK 0x01
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REGDAC_BANDWIDTH_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_SHORT_VOSC_PRP_MASK 0x02
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_SHORT_VOSC_PRP_SHIFT 1
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REFDAC_GAIN_MASK 0x0C
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REFDAC_GAIN_SHIFT 2
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_MASK 0x07
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_BBSTEP_MASK 0x1F
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_BBSTEP_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_CLKDIV_MASK 0x60
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_CLKDIV_SHIFT 5
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_CLKDIV_SWING_MASK 0x03
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_CLKDIV_SWING_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_SPARE_MASK 0x3C
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_SPARE_SHIFT 2
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_MASK 0x7F
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_SRC_SEL_MASK 0x80
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_SRC_SEL_SHIFT 7
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_MASK 0x7F
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_SRC_SEL_MASK 0x80
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_SRC_SEL_SHIFT 7
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_MASK 0x7F
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_CAP_MASK 0x07
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_CAP_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_SWING_MASK 0x18
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_SWING_SHIFT 3
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_CAL_EN_MASK 0x01
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_CAL_EN_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_VCOCAL_DIV4_MASK 0x02
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_VCOCAL_DIV4_SHIFT 1
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_RXCDR_VCOCAL_LOAD_VAL_11_8_MASK 0x0F
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_RXCDR_VCOCAL_LOAD_VAL_11_8_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_RXCDR_VCOCAL_LOAD_VAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_RXCDR_VCOCAL_LOAD_VAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_RXCDR_VCOCAL_UP_MASK 0x01
+#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_RXCDR_VCOCAL_UP_SHIFT 0
+
+#define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ZERO_PHASE_MASK 0x7F
+#define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ZERO_PHASE_SHIFT 0
+
+/********************************* Lane BIST *********************************/
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_ADDR 0x00
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_ADDR 0x01
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_ADDR 0x02
+#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_ADDR 0x03
+#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_ADDR 0x04
+#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_ADDR 0x05
+#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_ADDR 0x06
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR 0x10
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_ADDR 0x12
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_ADDR 0x13
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_ADDR 0x14
+#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_ADDR 0x16
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_ADDR 0x19
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR 0x1B
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR 0x1C
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR 0x22
+#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_ADDR 0x24
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_ADDR 0x25
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ADDR 0x26
+#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_ADDR 0x27
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_ADDR 0x30
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_ADDR 0x31
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR 0x38
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_ADDR 0x39
+#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_ADDR 0x3A
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_ADDR 0x3B
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_ADDR 0x3C
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_ADDR 0x3D
+#define SERDES_25G_LANE_TOP_ERR_CTRL1_ADDR 0x40
+#define SERDES_25G_LANE_TOP_ERR_CTRL2_ADDR 0x41
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_MASK 0x02
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_MASK 0x04
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_MASK 0x08
+#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_MASK 0x02
+#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_MASK 0x02
+#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_MASK 0x04
+#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_MASK 0x0F
+#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK 0x0F
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_MASK 0x30
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_MASK 0x40
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_SHIFT 6
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_MASK 0x06
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_MASK 0x0F
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_MASK 0x03
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_MASK 0x04
+#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_MASK 0xF0
+#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_MASK 0x07
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_MASK 0xF0
+#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_MASK 0x07
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK 0x08
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK 0x10
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK 0x1F
+#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK 0x03
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_MASK 0x04
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_MASK 0x10
+#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_MASK 0x01
+#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08
+#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70
+#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_MASK 0x01
+#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_MASK 0x07
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_MASK 0x38
+#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_MASK 0x07
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_MASK 0x38
+#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_MASK 0x02
+#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_MASK 0x02
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_MASK 0x04
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT 2
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_MASK 0x08
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_MASK 0x10
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_SHIFT 4
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_MASK 0x20
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_SHIFT 5
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_MASK 0x40
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_SHIFT 6
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_MASK 0x06
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_MASK 0x08
+#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_SHIFT 3
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_MASK 0x01
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_MASK 0x02
+#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_SHIFT 1
+
+#define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF
+#define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF
+#define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0
+
+/********************************* LEQ_REFCLK *********************************/
+#define SERDES_25G_LANE_LEQ_REFCLK_BASE 0x200
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x00)
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x02)
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x03)
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x05)
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x07)
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x09)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0A)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0B)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0C)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0E)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0F)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x10)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x11)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x20)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x21)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x22)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x23)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x24)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x25)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x26)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x27)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x28)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x29)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2A)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2B)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2C)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2E)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x30)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x31)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x32)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x33)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x34)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x35)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x36)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x37)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x38)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x39)
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3A)
+#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3D)
+#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3E)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x40)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x41)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x42)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x43)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x44)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x45)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x46)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x50)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x51)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x52)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x53)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x54)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x55)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x56)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x57)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x58)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x59)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5A)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5B)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5C)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5D)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5E)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5F)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x60)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x61)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x62)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x63)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x64)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x65)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x66)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x67)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x68)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x70)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x71)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x72)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x73)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x74)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x75)
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x76)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x80)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x81)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x82)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x83)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x84)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x85)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x86)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x87)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x88)
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x90)
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x91)
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x92)
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x93)
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x94)
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x95)
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x96)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x98)
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x99)
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9A)
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9B)
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9C)
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9D)
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA0)
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA1)
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA2)
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA3)
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA6)
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA7)
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA8)
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA9)
+#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAB)
+#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAC)
+#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAE)
+#define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAF)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xB8)
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xB9)
+
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_MASK 0x3F
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_BIASGEN_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_BIASGEN_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_RXLEQ_BIAS_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_RXLEQ_BIAS_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_VGSW_SEL_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_VGSW_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_MASK 0x18
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_MUTE_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_MUTE_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_MASK 0x06
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_PRECH_MASK 0x08
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_PRECH_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_RXLEQ_EQ_SQL_DIR_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_RXLEQ_EQ_SQL_DIR_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_RXLEQ_SPARE_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_RXLEQ_SPARE_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START1_MASK 0x38
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START1_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START3_MASK 0x38
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START3_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE0_MASK 0x03
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE1_MASK 0x0C
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE1_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE2_MASK 0x30
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE2_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE3_MASK 0xC0
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE3_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START1_MASK 0x38
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START1_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START3_MASK 0x38
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START3_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START1_MASK 0x38
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START1_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START3_MASK 0x38
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START3_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_STATE_RESET_MASK 0x04
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_STATE_RESET_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_OPCODE_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_OPCODE_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_TARGET_MASK 0xF0
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_TARGET_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_LEQ_FSM_CMD_SCRATCHPAD_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_LEQ_FSM_CMD_SCRATCHPAD_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_LEQ_FSM_CMD_MISC_OPTION_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_LEQ_FSM_CMD_MISC_OPTION_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_MASK 0x38
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MAX_CLAMP_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MAX_CLAMP_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MIN_CLAMP_MASK 0x80
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MIN_CLAMP_SHIFT 7
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_STATE_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_STATE_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_LAST_RESULT_MASK 0xF0
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_LAST_RESULT_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_LEQ_FSM_LAST_STEP_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_LEQ_FSM_LAST_STEP_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_LEQ_FSM_LAST_VALUE_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_LEQ_FSM_LAST_VALUE_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_OPCODE_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_OPCODE_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_TARGET_MASK 0xF0
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_TARGET_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_LEQ_FSM_TIMEOUT_LIMIT_7_0_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_LEQ_FSM_TIMEOUT_LIMIT_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_LEQ_FSM_TIMEOUT_LIMIT_15_8_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_LEQ_FSM_TIMEOUT_LIMIT_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_LEQ_FSM_2LST_VALUE_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_LEQ_FSM_2LST_VALUE_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_LEQ_OUTINTF_RDY_WAIT_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_LEQ_OUTINTF_RDY_WAIT_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_AGCLOS_VALUE_MAX_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_AGCLOS_VALUE_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_AGCLOS_VALUE_MIN_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_AGCLOS_VALUE_MIN_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_WRWAIT_TIME_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_WRWAIT_TIME_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_INIT_TIMEOUT_DISABLE_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_INIT_TIMEOUT_DISABLE_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_MEASURE_TIMEOUT_DISABLE_MASK 0x80
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_MEASURE_TIMEOUT_DISABLE_SHIFT 7
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_BY1_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_BY1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_ERROR_SIGN_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_ERROR_SIGN_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_SIZE_MASK 0x1C
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_SIZE_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_BOUNCE_LIMIT_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_BOUNCE_LIMIT_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_AVG_MASK 0x30
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_AVG_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_FLOOR_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_FLOOR_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_AGCLOS_LASTWR_ADJUST_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_AGCLOS_LASTWR_ADJUST_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_AGCLOS_PEAK_ACQ_TIME_7_0_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_AGCLOS_PEAK_ACQ_TIME_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_AGCLOS_PEAK_ACQ_TIME_15_8_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_AGCLOS_PEAK_ACQ_TIME_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_AGCLOS_PEAK_ACQ_TIME_23_16_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_AGCLOS_PEAK_ACQ_TIME_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_AGCLOS_PEAK_ACQ_TIME_25_24_MASK 0x03
+#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_AGCLOS_PEAK_ACQ_TIME_25_24_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_WRWAIT_TIME_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_WRWAIT_TIME_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_STEP_BY1_MASK 0x10
+#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_STEP_BY1_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_PLE_LFG_START_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_PLE_LFG_START_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_EQ_HFG_SQL_VALUE_MAX_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_EQ_HFG_SQL_VALUE_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_EQ_HFG_SQL_VALUE_MIN_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_EQ_HFG_SQL_VALUE_MIN_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_WRWAIT_TIME_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_WRWAIT_TIME_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_MEASURE_TIMEOUT_DISABLE_MASK 0x80
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_MEASURE_TIMEOUT_DISABLE_SHIFT 7
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_BY1_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_BY1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_ERROR_SIGN_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_ERROR_SIGN_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_SIZE_MASK 0x1C
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_SIZE_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_BOUNCE_LIMIT_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_BOUNCE_LIMIT_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_AVG_MASK 0x30
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_AVG_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_FLOOR_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_FLOOR_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_EQ_HFG_SQL_LASTWR_ADJUST_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_EQ_HFG_SQL_LASTWR_ADJUST_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE0_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE1_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE1_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE2_MASK 0x04
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE2_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE3_MASK 0x08
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE3_SHIFT 3
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP0_RATE0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP0_RATE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP1_RATE0_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP1_RATE0_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP2_RATE0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP2_RATE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP3_RATE0_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP3_RATE0_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP4_RATE0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP4_RATE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP5_RATE0_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP5_RATE0_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP6_RATE0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP6_RATE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP7_RATE0_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP7_RATE0_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP8_RATE0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP8_RATE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP9_RATE0_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP9_RATE0_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP10_RATE0_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP10_RATE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP11_RATE0_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP11_RATE0_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP0_RATE1_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP0_RATE1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP1_RATE1_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP1_RATE1_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP2_RATE1_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP2_RATE1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP3_RATE1_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP3_RATE1_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP4_RATE1_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP4_RATE1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP5_RATE1_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP5_RATE1_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP6_RATE1_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP6_RATE1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP7_RATE1_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP7_RATE1_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP8_RATE1_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP8_RATE1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP9_RATE1_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP9_RATE1_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP10_RATE1_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP10_RATE1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP11_RATE1_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP11_RATE1_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP0_RATE2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP0_RATE2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP1_RATE2_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP1_RATE2_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP2_RATE2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP2_RATE2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP3_RATE2_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP3_RATE2_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP4_RATE2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP4_RATE2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP5_RATE2_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP5_RATE2_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP6_RATE2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP6_RATE2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP7_RATE2_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP7_RATE2_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP8_RATE2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP8_RATE2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP9_RATE2_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP9_RATE2_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP10_RATE2_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP10_RATE2_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP11_RATE2_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP11_RATE2_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP0_RATE3_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP0_RATE3_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP1_RATE3_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP1_RATE3_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP2_RATE3_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP2_RATE3_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP3_RATE3_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP3_RATE3_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP4_RATE3_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP4_RATE3_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP5_RATE3_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP5_RATE3_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP6_RATE3_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP6_RATE3_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP7_RATE3_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP7_RATE3_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP8_RATE3_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP8_RATE3_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP9_RATE3_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP9_RATE3_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP10_RATE3_MASK 0x07
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP10_RATE3_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP11_RATE3_MASK 0x70
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP11_RATE3_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_MASK 0x03
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MAX_MASK 0x03
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MIN_MASK 0x0C
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MIN_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_WRWAIT_TIME_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_WRWAIT_TIME_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_MEASURE_TIMEOUT_DISABLE_MASK 0x80
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_MEASURE_TIMEOUT_DISABLE_SHIFT 7
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_BY1_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_BY1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_ERROR_SIGN_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_ERROR_SIGN_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_SIZE_MASK 0x0C
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_SIZE_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_BOUNCE_LIMIT_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_BOUNCE_LIMIT_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_AVG_MASK 0x30
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_AVG_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_FLOOR_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_FLOOR_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_GN_APG_LASTWR_ADJUST_MASK 0x03
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_GN_APG_LASTWR_ADJUST_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_DELTA_MASK 0x03
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_DELTA_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_MAX_MASK 0x0C
+#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_MAX_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_WRWAIT_TIME_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_WRWAIT_TIME_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_MEASURE_TIMEOUT_DISABLE_MASK 0x80
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_MEASURE_TIMEOUT_DISABLE_SHIFT 7
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_BY1_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_BY1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_ERROR_SIGN_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_ERROR_SIGN_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_SIZE_MASK 0x1C
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_SIZE_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_BOUNCE_LIMIT_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_BOUNCE_LIMIT_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_AVG_MASK 0x30
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_AVG_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_FLOOR_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_FLOOR_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_EQ_LFG_LASTWR_ADJUST_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_EQ_LFG_LASTWR_ADJUST_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_EQ_LFG_CCL_DELTA_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_EQ_LFG_CCL_DELTA_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_EQ_LFG_CCL_MAX_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_EQ_LFG_CCL_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_GNEQ_CCL_LFG_START_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_GNEQ_CCL_LFG_START_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_GNEQ_CCL_LFG_VALUE_MAX_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_GNEQ_CCL_LFG_VALUE_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_GNEQ_CCL_LFG_VALUE_MIN_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_GNEQ_CCL_LFG_VALUE_MIN_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_WRWAIT_TIME_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_WRWAIT_TIME_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_MEASURE_TIMEOUT_DISABLE_MASK 0x80
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_MEASURE_TIMEOUT_DISABLE_SHIFT 7
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_BY1_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_BY1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_ERROR_SIGN_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_ERROR_SIGN_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_SIZE_MASK 0x1C
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_SIZE_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_BOUNCE_LIMIT_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_BOUNCE_LIMIT_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_AVG_MASK 0x30
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_AVG_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_FLOOR_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_FLOOR_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_GNEQ_CCL_LFG_LASTWR_ADJUST_MASK 0x1F
+#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_GNEQ_CCL_LFG_LASTWR_ADJUST_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_WRWAIT_TIME_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_WRWAIT_TIME_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_STEP_BY1_MASK 0x10
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_STEP_BY1_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_MASK 0xF0
+#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_VSCAN_VALUE_MAX_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_VSCAN_VALUE_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_VSCAN_VALUE_MIN_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_VSCAN_VALUE_MIN_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_BY1_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_BY1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_ERROR_SIGN_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_ERROR_SIGN_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_SIZE_MASK 0x3C
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_SIZE_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_BOUNCE_LIMIT_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_BOUNCE_LIMIT_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_AVG_MASK 0x30
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_AVG_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_FLOOR_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_FLOOR_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_HSCAN_VALUE_MAX_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_HSCAN_VALUE_MAX_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_HSCAN_VALUE_MIN_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_HSCAN_VALUE_MIN_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_BY1_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_BY1_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_ERROR_SIGN_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_ERROR_SIGN_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_SIZE_MASK 0x3C
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_SIZE_SHIFT 2
+
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_BOUNCE_LIMIT_MASK 0x0F
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_BOUNCE_LIMIT_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_AVG_MASK 0x30
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_AVG_SHIFT 4
+
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_FLOOR_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_FLOOR_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_GN_APG_REF_N_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_GN_APG_REF_N_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_GN_APG_REF_P_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_GN_APG_REF_P_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_EQ_LFG_REF_N_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_EQ_LFG_REF_N_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_EQ_LFG_REF_P_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_EQ_LFG_REF_P_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_EYE_PHASE_7_0_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_EYE_PHASE_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_8_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_8_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_VALID_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_VALID_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_ODDEYE_MASK 0x01
+#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_ODDEYE_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_PATH1_MASK 0x02
+#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_PATH1_SHIFT 1
+
+#define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_EYEINTF_INIT_TIMEOUT_DISABLE_MASK 0x40
+#define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_EYEINTF_INIT_TIMEOUT_DISABLE_SHIFT 6
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_SHIFT 0
+
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_MASK 0xFF
+#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_SHIFT 0
+
+/********************************* DRV_REFCLK *********************************/
+#define SERDES_25G_LANE_DRV_REFCLK_BASE 0x380
+
+#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x00)
+#define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x01)
+#define SERDES_25G_LANE_DRV_AFE_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x03)
+#define SERDES_25G_LANE_DRV_AFE_CTRL2_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x04)
+#define SERDES_25G_LANE_DRV_AFE_CTRL3_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x05)
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x06)
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x08)
+#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x09)
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0A)
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0B)
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0C)
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0D)
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x10)
+#define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x11)
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x12)
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL2_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x13)
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x14)
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x15)
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x16)
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_PD_TXDRV_MASK 0x01
+#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_PD_TXDRV_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_TXDRV_LP_IDLE_MASK 0x02
+#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_TXDRV_LP_IDLE_SHIFT 1
+
+#define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_RST_TXDRV_DIV2_N_MASK 0x01
+#define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_RST_TXDRV_DIV2_N_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_CTRL1_TXDRV_SPARE_MASK 0xFF
+#define SERDES_25G_LANE_DRV_AFE_CTRL1_TXDRV_SPARE_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_TOGGLE_EN_MASK 0x01
+#define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_TOGGLE_EN_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_CLK_DELAY_MASK 0x3E
+#define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_CLK_DELAY_SHIFT 1
+
+#define SERDES_25G_LANE_DRV_AFE_CTRL3_TXDRV_CO_POL_MASK 0x07
+#define SERDES_25G_LANE_DRV_AFE_CTRL3_TXDRV_CO_POL_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_P5_MASK 0x01
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_P5_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X1_MASK 0x02
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X1_SHIFT 1
+
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X2_MASK 0x1C
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X2_SHIFT 2
+
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X1_MASK 0x20
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X1_SHIFT 5
+
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X2_MASK 0xC0
+#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X2_SHIFT 6
+
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_P5_MASK 0x01
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_P5_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X1_MASK 0x02
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X1_SHIFT 1
+
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X2_MASK 0x0C
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X2_SHIFT 2
+
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CXCM1_X2_MASK 0x10
+#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CXCM1_X2_SHIFT 4
+
+#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X1_MASK 0x07
+#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X1_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X2_MASK 0xF8
+#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X2_SHIFT 3
+
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_CXN_X1_MASK 0x07
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_CXN_X1_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_FIXEDCXN_X1_MASK 0x18
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_FIXEDCXN_X1_SHIFT 3
+
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_CXN_X2_MASK 0x1F
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_CXN_X2_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_FIXEDCXN_XP5_MASK 0x60
+#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_FIXEDCXN_XP5_SHIFT 5
+
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_CXP_X1_MASK 0x07
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_CXP_X1_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_FIXEDCXP_X1_MASK 0x18
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_FIXEDCXP_X1_SHIFT 3
+
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_CXP_X2_MASK 0x1F
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_CXP_X2_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_FIXEDCXP_XP5_MASK 0x60
+#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_FIXEDCXP_XP5_SHIFT 5
+
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK 0x01
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_MASK 0x01
+#define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK 0x1F
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL2_TXEQ_C2_MASK 0x03
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL2_TXEQ_C2_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK 0x0F
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_TXEQ_1LSB_MODE_MASK 0x01
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_TXEQ_1LSB_MODE_SHIFT 0
+
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_SWING_1LSB_MODE_MASK 0x02
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_SWING_1LSB_MODE_SHIFT 1
+
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK 0x0F
+#define SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT 0
+
+/********************************* DFE REFCLK *********************************/
+#define SERDES_25G_LANE_DFE_REFCLK_BASE 0x400
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x00)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x01)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x02)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x04)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x06)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0A)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0C)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0E)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x10)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x12)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x14)
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x16)
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x18)
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x19)
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x1B)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x20)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x21)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x22)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x23)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x24)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x25)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x26)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x27)
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x28)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2A)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2B)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2C)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2D)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2E)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2F)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x30)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x31)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x32)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x33)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x34)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x35)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x36)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x37)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x38)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x39)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3A)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3B)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3C)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3D)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3E)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3F)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x40)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x41)
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x42)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x50)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x51)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x52)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x53)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x54)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x55)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x56)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x57)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x58)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x59)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5A)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5B)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5C)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5D)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5E)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5F)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x60)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x61)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x62)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x63)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x64)
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x65)
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_TAP_MASK 0x3E
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_TAP_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_EVEN_PATH_MASK 0x03
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_EVEN_PATH_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_ODD_PATH_MASK 0x0C
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_ODD_PATH_SHIFT 2
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_EVEN_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_EVEN_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_ODD_MASK 0x38
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_ODD_SHIFT 3
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_RST_RXDFE_N_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_RST_RXDFE_N_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_RXDFE_TOGGLE_EN_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_RXDFE_TOGGLE_EN_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_EVEN_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_EVEN_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_ODD_MASK 0x02
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_ODD_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_EDGE_MUTE_MASK 0x0C
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_EDGE_MUTE_SHIFT 2
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLK_DELAY_MASK 0x0F
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLK_DELAY_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLKDIV_OVR_MASK 0x30
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLKDIV_OVR_SHIFT 4
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYECLK_DELAY_MASK 0x0F
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYECLK_DELAY_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_CLKDIVEYE_OVR_MASK 0x30
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_CLKDIVEYE_OVR_SHIFT 4
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYERESAMP_ADJ_MASK 0xC0
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYERESAMP_ADJ_SHIFT 6
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLI_MASK 0x0F
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLI_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_MASK 0x30
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_SHIFT 4
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_LTCH_MASK 0x40
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_LTCH_SHIFT 6
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_SUMGAIN_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_SUMGAIN_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_LDR_MASK 0x06
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_LDR_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_RXDFE_SPARE_MASK 0xFF
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_RXDFE_SPARE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIV_QSAMPLE_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIV_QSAMPLE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIVEYE_QSAMPLE_MASK 0x1E
+#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIVEYE_QSAMPLE_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_MAG_MASK 0xFF
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_MAG_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_POL_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_POL_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_MAG_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_MAG_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_POL_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_POL_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_REQ_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_REQ_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_CMD_MASK 0x3E
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_CMD_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_FINISH_MASK 0x40
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_FINISH_SHIFT 6
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_NEXT_STATE_MASK 0x0F
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_NEXT_STATE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_CTRL_EN_MASK 0x10
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_CTRL_EN_SHIFT 4
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_WAIT_1_TIMER7_0_MASK 0xFF
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_WAIT_1_TIMER7_0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_WAIT_1_TIMER9_8_MASK 0x03
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_WAIT_1_TIMER9_8_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_WAIT_2_TIMER7_0_MASK 0xFF
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_WAIT_2_TIMER7_0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_WAIT_2_TIMER9_8_MASK 0x03
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_WAIT_2_TIMER9_8_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_TAP_DELAY_7_0_MASK 0xFF
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_TAP_DELAY_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_TAP_DELAY_9_8_MASK 0x03
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_TAP_DELAY_9_8_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ACK_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ACK_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_SLICER_OFST_ACK_MASK 0x02
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_SLICER_OFST_ACK_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ERR_FUNC_ACK_MASK 0x04
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ERR_FUNC_ACK_SHIFT 2
+
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_AFE_DRV_ACK_MASK 0x08
+#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_AFE_DRV_ACK_SHIFT 3
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_MASK 0x02
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_MASK 0x04
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_SHIFT 2
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_MASK 0x08
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_SHIFT 3
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP2_EN_MASK 0x10
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP2_EN_SHIFT 4
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP3_EN_MASK 0x20
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP3_EN_SHIFT 5
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP4_EN_MASK 0x40
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP4_EN_SHIFT 6
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP5_EN_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP5_EN_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_MASK 0x0F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_MASK 0x0F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_MASK 0x0F
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_MASK 0x07
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN0_DATA_EN_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN0_DATA_EN_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN1_DATA_EN_MASK 0x02
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN1_DATA_EN_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD0_DATA_EN_MASK 0x04
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD0_DATA_EN_SHIFT 2
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD1_DATA_EN_MASK 0x08
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD1_DATA_EN_SHIFT 3
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EDGE_EN_MASK 0x10
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EDGE_EN_SHIFT 4
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EDGE_EN_MASK 0x20
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EDGE_EN_SHIFT 5
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EYE_EN_MASK 0x40
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EYE_EN_SHIFT 6
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EYE_EN_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EYE_EN_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_LIMIT_MASK 0x1F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_LIMIT_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_MAX_BOUNCES_MASK 0x0F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_MAX_BOUNCES_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_EVEN0_DATA_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_EVEN0_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_EVEN1_DATA_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_EVEN1_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ODD0_DATA_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ODD0_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ODD1_DATA_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ODD1_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_EVEN_EDGE_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_EVEN_EDGE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ODD_EDGE_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ODD_EDGE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_EVEN_EYE_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_EVEN_EYE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ODD_EYE_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ODD_EYE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_EVEN0_DATA_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_EVEN0_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_EVEN1_DATA_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_EVEN1_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ODD0_DATA_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ODD0_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ODD1_DATA_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ODD1_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_EVEN_EDGE_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_EVEN_EDGE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ODD_EDGE_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ODD_EDGE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_EVEN_EYE_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_EVEN_EYE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ODD_EYE_MASK 0x3F
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ODD_EYE_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN0_DATA_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN0_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN1_DATA_MASK 0x02
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN1_DATA_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD0_DATA_MASK 0x04
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD0_DATA_SHIFT 2
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD1_DATA_MASK 0x08
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD1_DATA_SHIFT 3
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EDGE_MASK 0x10
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EDGE_SHIFT 4
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EDGE_MASK 0x20
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EDGE_SHIFT 5
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EYE_MASK 0x40
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EYE_SHIFT 6
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EYE_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EYE_SHIFT 7
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ERR_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ERR_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_INC_MASK 0x02
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_INC_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_DEC_MASK 0x04
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_DEC_SHIFT 2
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN0_DATA_MASK 0x01
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN0_DATA_SHIFT 0
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN1_DATA_MASK 0x02
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN1_DATA_SHIFT 1
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD0_DATA_MASK 0x04
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD0_DATA_SHIFT 2
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD1_DATA_MASK 0x08
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD1_DATA_SHIFT 3
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EDGE_MASK 0x10
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EDGE_SHIFT 4
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EDGE_MASK 0x20
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EDGE_SHIFT 5
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EYE_MASK 0x40
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EYE_SHIFT 6
+
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EYE_MASK 0x80
+#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EYE_SHIFT 7
+
+/********************************** LOS REFCLK **********************************/
+#define SERDES_25G_LANE_LOS_REFCLK_BASE 0x500
+
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x00)
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x01)
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x02)
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x10)
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x11)
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x12)
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x13)
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x14)
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x15)
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x16)
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x20)
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x21)
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x22)
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x23)
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x24)
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x30)
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x31)
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x32)
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x33)
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x40)
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x41)
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x42)
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x43)
+#define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x46)
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x51)
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x59)
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x60)
+#define SERDES_25G_LANE_LOS_REFCLK_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x70)
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x71)
+#define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x72)
+#define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x73)
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ASSERT_THRESHOLD_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ASSERT_THRESHOLD_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_MASK 0x02
+#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_SHIFT 1
+
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ASSERT_THRESHOLD_7_0_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ASSERT_THRESHOLD_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ASSERT_THRESHOLD_15_8_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ASSERT_THRESHOLD_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_DEASSERT_THRESHOLD_7_0_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_DEASSERT_THRESHOLD_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_DEASSERT_THRESHOLD_15_8_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_DEASSERT_THRESHOLD_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_DEASSERT_THRESHOLD_23_16_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_DEASSERT_THRESHOLD_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_MASK 0x03
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_EN_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_EN_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_EN_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_PERIOD_7_0_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_PERIOD_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_PERIOD_15_8_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_PERIOD_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_PERIOD_23_16_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_PERIOD_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_PERIOD_25_24_MASK 0x03
+#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_PERIOD_25_24_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_MASK 0x10
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_SHIFT 4
+
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_EN_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_EN_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_VALUE_MASK 0x10
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_VALUE_SHIFT 4
+
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_VALUE_MASK 0x3F
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_VALUE_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_EN_MASK 0x40
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_EN_SHIFT 6
+
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_VALUE_MASK 0x3F
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_VALUE_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_EN_MASK 0x40
+#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_EN_SHIFT 6
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_BANDWIDTH_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_BANDWIDTH_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_HYSTERESIS_MASK 0x0E
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_HYSTERESIS_SHIFT 1
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ENVDET_BYP_MASK 0x10
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ENVDET_BYP_SHIFT 4
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_GAIN_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_GAIN_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_LOS_INVERT_MASK 0x02
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_LOS_INVERT_SHIFT 1
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_AGC_INVERT_MASK 0x04
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_AGC_INVERT_SHIFT 2
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_THRESHOLD_MASK 0x78
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_THRESHOLD_SHIFT 3
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_MODE_SWITCH_WAIT_7_0_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_MODE_SWITCH_WAIT_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_MODE_SWITCH_WAIT_15_8_MASK 0xFF
+#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_MODE_SWITCH_WAIT_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_EYE_DATA_PARITY_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_EYE_DATA_PARITY_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_EN_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_MODE_MASK 0x02
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_MODE_SHIFT 1
+
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_LOS_OFFSET_MASK 0x3F
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_LOS_OFFSET_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_AGC_CALIB_DONE_MASK 0x40
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_AGC_CALIB_DONE_SHIFT 6
+
+#define SERDES_25G_LANE_LOS_REFCLK_CTRL0_EN_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_CTRL0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTRL0_SRC_SELECT_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_CTRL0_SRC_SELECT_SHIFT 1
+
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_READY_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_READY_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_READY_MASK 0x02
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_READY_SHIFT 1
+
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_MASK 0x04
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_SHIFT 2
+
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_RAW_MASK 0x08
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_RAW_SHIFT 3
+
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_MASK 0x10
+#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_SHIFT 4
+
+#define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_RXLOS_SPARE_MASK 0x0F
+#define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_RXLOS_SPARE_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_PD_RXLOS_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_PD_RXLOS_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL6_REQ_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL6_REQ_SHIFT 0
+
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS2_ACK_MASK 0x01
+#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS2_ACK_SHIFT 0
+
+/********************************** GCFSM2 **********************************/
+#define SERDES_25G_LANE_GCFSM2_BASE 0x580
+
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x00)
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x01)
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x02)
+#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x03)
+#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x10)
+#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x11)
+#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x12)
+#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x13)
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x20)
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x21)
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x22)
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x23)
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x24)
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x25)
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x26)
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x30)
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x31)
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x32)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x40)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x41)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x42)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x43)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x44)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x45)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x46)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x47)
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x48)
+#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x50)
+#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x51)
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK 0x01
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_MASK 0x07
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_MASK 0x01
+#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_CODE_MASK 0x1E
+#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_CODE_SHIFT 1
+
+#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_7_0_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_MASK 0x0F
+#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_7_0_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_8_8_MASK 0x01
+#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_8_8_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_TYPE_MASK 0x03
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_TYPE_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_WIDTH_MASK 0x3C
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_WIDTH_SHIFT 2
+
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_START_7_0_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_START_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_START_11_8_MASK 0x0F
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_START_11_8_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_MIN_7_0_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_MIN_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_MIN_11_8_MASK 0x0F
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_MIN_11_8_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_MAX_7_0_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_MAX_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_MAX_11_8_MASK 0x0F
+#define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_MAX_11_8_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_STEP_SIZE_MASK 0x1F
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_STEP_SIZE_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_BOUNCE_NUM_MASK 0x0F
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_BOUNCE_NUM_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_COARSE_BOUNCE_NUM_MASK 0xF0
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_COARSE_BOUNCE_NUM_SHIFT 4
+
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_SETTLE_ON_LOWEST_AVG_EN_MASK 0x01
+#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_SETTLE_ON_LOWEST_AVG_EN_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_LEN_DELAY_AFE_EN_MASK 0x03
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_LEN_DELAY_AFE_EN_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_LEN_AFE_1ST_LATCH_SETTLE_7_0_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_LEN_AFE_1ST_LATCH_SETTLE_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_LEN_AFE_1ST_LATCH_SETTLE_15_8_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_LEN_AFE_1ST_LATCH_SETTLE_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_LEN_AFE_LATCH_SETTLE_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_LEN_AFE_LATCH_SETTLE_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_LEN_AFE_CMP_7_0_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_LEN_AFE_CMP_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_LEN_AFE_CMP_15_8_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_LEN_AFE_CMP_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_LEN_COARSE_BOUNCE_AFE_CMP_7_0_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_LEN_COARSE_BOUNCE_AFE_CMP_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_LEN_COARSE_BOUNCE_AFE_CMP_15_8_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_LEN_COARSE_BOUNCE_AFE_CMP_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_WAIT_MODE_MASK 0x01
+#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_WAIT_MODE_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_INVERT_AFE_UP_MASK 0x01
+#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_INVERT_AFE_UP_SHIFT 0
+
+#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_LEN_WAIT_AFE_UP_MASK 0x1E
+#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_LEN_WAIT_AFE_UP_SHIFT 1
+
+#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_LEN_AVG_AFE_UP_MASK 0xFF
+#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_LEN_AVG_AFE_UP_SHIFT 0
+
+/********************************** TX BIST **********************************/
+#define SERDES_25G_LANE_TX_BIST_BASE 0x600
+
+#define SERDES_25G_LANE_TX_BIST_CTRL_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x00)
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL0_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x04)
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL1_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x05)
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL2_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x06)
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL3_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x07)
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL4_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x08)
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL5_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x09)
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL6_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x0A)
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL7_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x0B)
+#define SERDES_25G_LANE_TX_BIST_UDP_SHIFT_AMOUNT_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x20)
+#define SERDES_25G_LANE_TX_BIST_UDP_ADDR(byte_num) \
+ ((SERDES_25G_LANE_TX_BIST_BASE + 0x24) + byte_num)
+#define SERDES_25G_LANE_TX_BIST_UDP_NUM_BYTES 20
+#define SERDES_25G_LANE_TX_BIST_UDP_7_0_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x24)
+#define SERDES_25G_LANE_TX_BIST_UDP_15_8_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x25)
+#define SERDES_25G_LANE_TX_BIST_UDP_23_16_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x26)
+#define SERDES_25G_LANE_TX_BIST_UDP_31_24_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x27)
+#define SERDES_25G_LANE_TX_BIST_UDP_39_32_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x28)
+#define SERDES_25G_LANE_TX_BIST_UDP_47_40_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x29)
+#define SERDES_25G_LANE_TX_BIST_UDP_55_48_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2A)
+#define SERDES_25G_LANE_TX_BIST_UDP_63_56_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2B)
+#define SERDES_25G_LANE_TX_BIST_UDP_71_64_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2C)
+#define SERDES_25G_LANE_TX_BIST_UDP_79_72_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2D)
+#define SERDES_25G_LANE_TX_BIST_UDP_87_80_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2E)
+#define SERDES_25G_LANE_TX_BIST_UDP_95_88_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2F)
+#define SERDES_25G_LANE_TX_BIST_UDP_103_96_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x30)
+#define SERDES_25G_LANE_TX_BIST_UDP_111_104_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x31)
+#define SERDES_25G_LANE_TX_BIST_UDP_119_112_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x32)
+#define SERDES_25G_LANE_TX_BIST_UDP_127_120_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x33)
+#define SERDES_25G_LANE_TX_BIST_UDP_135_128_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x34)
+#define SERDES_25G_LANE_TX_BIST_UDP_143_136_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x35)
+#define SERDES_25G_LANE_TX_BIST_UDP_151_144_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x36)
+#define SERDES_25G_LANE_TX_BIST_UDP_159_152_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x37)
+#define SERDES_25G_LANE_TX_BIST_UDP_167_160_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x38)
+#define SERDES_25G_LANE_TX_BIST_UDP_175_168_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x39)
+#define SERDES_25G_LANE_TX_BIST_UDP_183_176_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3A)
+#define SERDES_25G_LANE_TX_BIST_UDP_191_184_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3B)
+#define SERDES_25G_LANE_TX_BIST_UDP_199_192_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3C)
+
+#define SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK 0x01
+#define SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_MASK 0x1E
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_SHIFT 1
+
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS7 1
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS9 2
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS11 3
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS15 4
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS23 5
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS31 6
+#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS_USER 7
+
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL0_MODE_MASK 0x03
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL0_MODE_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL1_TIMER_7_0_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL1_TIMER_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL2_TIMER_15_8_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL2_TIMER_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL3_BIT_ERROR_FIELD_7_0_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL3_BIT_ERROR_FIELD_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL4_BIT_ERROR_FIELD_15_8_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL4_BIT_ERROR_FIELD_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL5_BIT_ERROR_FIELD_23_16_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL5_BIT_ERROR_FIELD_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL6_BIT_ERROR_FIELD_31_24_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL6_BIT_ERROR_FIELD_31_24_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL7_BIT_ERROR_FIELD_39_32_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_BER_CTRL7_BIT_ERROR_FIELD_39_32_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_SHIFT_AMOUNT_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_SHIFT_AMOUNT_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_7_0_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_15_8_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_23_16_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_31_24_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_31_24_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_39_32_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_39_32_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_47_40_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_47_40_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_55_48_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_55_48_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_63_56_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_63_56_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_71_64_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_71_64_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_79_72_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_79_72_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_87_80_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_87_80_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_95_88_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_95_88_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_103_96_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_103_96_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_111_104_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_111_104_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_119_112_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_119_112_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_127_120_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_127_120_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_135_128_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_135_128_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_143_136_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_143_136_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_151_144_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_151_144_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_159_152_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_159_152_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_167_160_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_167_160_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_175_168_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_175_168_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_183_176_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_183_176_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_191_184_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_191_184_SHIFT 0
+
+#define SERDES_25G_LANE_TX_BIST_UDP_199_192_MASK 0xFF
+#define SERDES_25G_LANE_TX_BIST_UDP_199_192_SHIFT 0
+
+/********************************** RX BIST **********************************/
+#define SERDES_25G_LANE_RX_BIST_BASE 0x680
+
+#define SERDES_25G_LANE_RX_BIST_CTRL_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x00)
+#define SERDES_25G_LANE_RX_BIST_STATUS_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x04)
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x08)
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x09)
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0A)
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS4_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0C)
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS5_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0D)
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS6_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0E)
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x14)
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x15)
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x16)
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x17)
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x20)
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x21)
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x22)
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x23)
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x24)
+#define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x30)
+#define SERDES_25G_LANE_RX_BIST_UDP_7_0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x34)
+#define SERDES_25G_LANE_RX_BIST_UDP_15_8_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x35)
+#define SERDES_25G_LANE_RX_BIST_UDP_23_16_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x36)
+#define SERDES_25G_LANE_RX_BIST_UDP_31_24_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x37)
+#define SERDES_25G_LANE_RX_BIST_UDP_39_32_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x38)
+#define SERDES_25G_LANE_RX_BIST_UDP_47_40_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x39)
+#define SERDES_25G_LANE_RX_BIST_UDP_55_48_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3A)
+#define SERDES_25G_LANE_RX_BIST_UDP_63_56_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3B)
+#define SERDES_25G_LANE_RX_BIST_UDP_71_64_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3C)
+#define SERDES_25G_LANE_RX_BIST_UDP_79_72_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3D)
+#define SERDES_25G_LANE_RX_BIST_UDP_87_80_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3E)
+#define SERDES_25G_LANE_RX_BIST_UDP_95_88_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3F)
+#define SERDES_25G_LANE_RX_BIST_UDP_103_96_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x40)
+#define SERDES_25G_LANE_RX_BIST_UDP_111_104_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x41)
+#define SERDES_25G_LANE_RX_BIST_UDP_119_112_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x42)
+#define SERDES_25G_LANE_RX_BIST_UDP_127_120_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x43)
+#define SERDES_25G_LANE_RX_BIST_UDP_135_128_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x44)
+#define SERDES_25G_LANE_RX_BIST_UDP_143_136_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x45)
+#define SERDES_25G_LANE_RX_BIST_UDP_151_144_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x46)
+#define SERDES_25G_LANE_RX_BIST_UDP_159_152_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x47)
+#define SERDES_25G_LANE_RX_BIST_UDP_167_160_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x48)
+#define SERDES_25G_LANE_RX_BIST_UDP_175_168_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x49)
+#define SERDES_25G_LANE_RX_BIST_UDP_183_176_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4A)
+#define SERDES_25G_LANE_RX_BIST_UDP_191_184_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4B)
+#define SERDES_25G_LANE_RX_BIST_UDP_199_192_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4C)
+
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK 0x01
+#define SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_MASK 0x1E
+#define SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_SHIFT 1
+
+#define SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK 0x20
+#define SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT 5
+
+#define SERDES_25G_LANE_RX_BIST_CTRL_STOP_ERROR_COUNT_MASK 0x40
+#define SERDES_25G_LANE_RX_BIST_CTRL_STOP_ERROR_COUNT_SHIFT 6
+
+#define SERDES_25G_LANE_RX_BIST_CTRL_FORCE_LFSR_WITH_RXDATA_MASK 0x80
+#define SERDES_25G_LANE_RX_BIST_CTRL_FORCE_LFSR_WITH_RXDATA_SHIFT 7
+
+#define SERDES_25G_LANE_RX_BIST_STATUS_STATE_MASK 0x07
+#define SERDES_25G_LANE_RX_BIST_STATUS_STATE_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_STATUS_PATTERN_DET_MASK 0x78
+#define SERDES_25G_LANE_RX_BIST_STATUS_PATTERN_DET_SHIFT 3
+
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS4_CYCLE_COUNT_7_0_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS4_CYCLE_COUNT_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS5_CYCLE_COUNT_15_8_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS5_CYCLE_COUNT_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS6_CYCLE_COUNT_23_16_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_BER_STATUS6_CYCLE_COUNT_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_NUM_CYCLES_7_0_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_NUM_CYCLES_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_NUM_CYCLES_15_8_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_NUM_CYCLES_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_MAX_ERRORS_7_0_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_MAX_ERRORS_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_MAX_ERRORS_15_8_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_MAX_ERRORS_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_NUM_CYCLES_7_0_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_NUM_CYCLES_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_NUM_CYCLES_15_8_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_NUM_CYCLES_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_MIN_ERRORS_7_0_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_MIN_ERRORS_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_MIN_ERRORS_15_8_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_MIN_ERRORS_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_MASK 0x01
+#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_7_0_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_15_8_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_23_16_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_31_24_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_31_24_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_39_32_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_39_32_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_47_40_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_47_40_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_55_48_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_55_48_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_63_56_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_63_56_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_71_64_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_71_64_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_79_72_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_79_72_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_87_80_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_87_80_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_95_88_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_95_88_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_103_96_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_103_96_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_111_104_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_111_104_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_119_112_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_119_112_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_127_120_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_127_120_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_135_128_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_135_128_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_143_136_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_143_136_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_151_144_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_151_144_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_159_152_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_159_152_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_167_160_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_167_160_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_175_168_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_175_168_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_183_176_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_183_176_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_191_184_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_191_184_SHIFT 0
+
+#define SERDES_25G_LANE_RX_BIST_UDP_199_192_MASK 0xFF
+#define SERDES_25G_LANE_RX_BIST_UDP_199_192_SHIFT 0
+
+/*********************************** FEATURE **********************************/
+#define SERDES_25G_LANE_FEATURE_BASE 0x700
+
+#define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x00)
+#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x04)
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x05)
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x06)
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x07)
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x08)
+#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x09)
+#define SERDES_25G_LANE_FEATURE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x0C)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x10)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x11)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x12)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x13)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x14)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x15)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x16)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x17)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x18)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x19)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1A)
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1B)
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1F)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x20)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x21)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x22)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x23)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x24)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x25)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x26)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x27)
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x28)
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x30)
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x31)
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x32)
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x33)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x40)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x41)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x42)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x43)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x44)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x45)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x46)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x47)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x48)
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x49)
+#define SERDES_25G_LANE_FEATURE_TEST_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x50)
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x58)
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x59)
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5A)
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5B)
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG4_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5C)
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG5_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5D)
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG6_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5E)
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG7_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5F)
+/*******************************************************************************
+ * masks and shifts
+ ******************************************************************************/
+#define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_AC_COUPLED_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_AC_COUPLED_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_LOS_COMP_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_LOS_COMP_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_AGC_COMP_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_AGC_COMP_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_GN_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_GN_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ1_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ1_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ2_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ2_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ3_EN_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ3_EN_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ4_EN_MASK 0x10
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ4_EN_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ5_EN_MASK 0x20
+#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ5_EN_SHIFT 5
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMODD_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMODD_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMEVEN_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMEVEN_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANODD_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANODD_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANEVEN_EN_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANEVEN_EN_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN1_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN1_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN0_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN0_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD1_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD1_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD0_EN_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD0_EN_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICEREVEN_EN_MASK 0x10
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICEREVEN_EN_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICERODD_EN_MASK 0x20
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICERODD_EN_SHIFT 5
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICEREVEN_EN_MASK 0x40
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICEREVEN_EN_SHIFT 6
+
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICERODD_EN_MASK 0x80
+#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICERODD_EN_SHIFT 7
+
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_VCO_FREQ_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_VCO_FREQ_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL1_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL1_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL2_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL2_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL3_EN_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL3_EN_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL_RESULT_SEL_MASK 0x30
+#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL_RESULT_SEL_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_REG_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_REG_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_DCD_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_DCD_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TXDP_CLOCK_PHASE_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TXDP_CLOCK_PHASE_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_ADAPT_CFG_EYE_MON_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_ADAPT_CFG_EYE_MON_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_MASK 0x03
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_MASK 0x0C
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE0_MASK 0x30
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE0_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE1_MASK 0xC0
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE1_SHIFT 6
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_INTERVAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_INTERVAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_INTERVAL_15_8_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_INTERVAL_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_INTERVAL_23_16_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_INTERVAL_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_EIE0_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_EIE0_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_EIE0_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_EIE0_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_MASK 0x03
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_MASK 0x0C
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE0_SEL_MASK 0x30
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE0_SEL_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE1_SEL_MASK 0xC0
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE1_SEL_SHIFT 6
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_EDGE_EN_MASK 0x10
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_EDGE_EN_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_DATA_EN_MASK 0x20
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_DATA_EN_SHIFT 5
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_EDGE_EN_MASK 0x40
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_EDGE_EN_SHIFT 6
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_DATA_EN_MASK 0x80
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_DATA_EN_SHIFT 7
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_MASK 0x03
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_MASK 0x0C
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE0_RESULT_SEL_MASK 0x30
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE0_RESULT_SEL_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE1_RESULT_SEL_MASK 0xC0
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE1_RESULT_SEL_SHIFT 6
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_EDGE_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_EDGE_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_DATA_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_DATA_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_RESULT_SEL_MASK 0x0C
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_RESULT_SEL_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE0_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE0_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE1_EN_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE1_EN_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_CONT_EN_MASK 0x10
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_CONT_EN_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_AGCLOS_START_VAL_SEL_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_AGCLOS_START_VAL_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_PLE_ATT_START_VAL_SEL_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_PLE_ATT_START_VAL_SEL_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GN_APG_START_VAL_SEL_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GN_APG_START_VAL_SEL_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_LFG_START_VAL_SEL_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_LFG_START_VAL_SEL_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GNEQ_CCL_LFG_START_VAL_SEL_MASK 0x10
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GNEQ_CCL_LFG_START_VAL_SEL_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_HFG_SQL_START_VAL_SEL_MASK 0x20
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_HFG_SQL_START_VAL_SEL_SHIFT 5
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBF_START_VAL_SEL_MASK 0x40
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBF_START_VAL_SEL_SHIFT 6
+
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBG_START_VAL_SEL_MASK 0x80
+#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBG_START_VAL_SEL_SHIFT 7
+
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP1_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP1_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP2_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP2_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP3_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP3_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP4_EN_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP4_EN_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP5_EN_MASK 0x10
+#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP5_EN_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_INTERVAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_INTERVAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_INTERVAL_15_8_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_INTERVAL_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_INTERVAL_23_16_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_INTERVAL_23_16_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_EIE_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_EIE_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_CONT_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_CONT_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_START_VAL_SEL_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_START_VAL_SEL_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_EIE_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_EIE_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_CONT_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_CONT_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_START_VAL_SEL_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_START_VAL_SEL_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_EIE_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_EIE_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_CONT_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_CONT_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_START_VAL_SEL_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_START_VAL_SEL_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_EIE_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_EIE_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_CONT_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_CONT_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_START_VAL_SEL_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_START_VAL_SEL_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_EIE_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_EIE_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_CONT_EN_MASK 0x04
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_CONT_EN_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_START_VAL_SEL_MASK 0x08
+#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_START_VAL_SEL_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_TIMEOUT_US_MASK 0xFE
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_TIMEOUT_US_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_CDR_LOCK_WAIT_TIME_US_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_CDR_LOCK_WAIT_TIME_US_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_CDR_FREQ_MEASURE_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_CDR_FREQ_MEASURE_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_RXCLKDIV_EN_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_RXCLKDIV_EN_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_BIST_HANDSHAKE_EN_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_BIST_HANDSHAKE_EN_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_SIG_DET_MODE_MASK 0x03
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_SIG_DET_MODE_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_LOS_DET_MODE_MASK 0x0C
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_LOS_DET_MODE_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_SIG_DET_THRESHOLD_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_SIG_DET_THRESHOLD_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_LOS_DET_THRESHOLD_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_LOS_DET_THRESHOLD_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_INTERVAL_7_0_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_INTERVAL_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_INTERVAL_15_8_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_INTERVAL_15_8_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_SAMPLE_LEN_7_0_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_SAMPLE_LEN_7_0_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_SAMPLE_LEN_11_8_MASK 0x0F
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_SAMPLE_LEN_11_8_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_PLE_ATT_MASK 0x07
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_PLE_ATT_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_EQ_LFG_MASK 0xF8
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_EQ_LFG_SHIFT 3
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_GN_APG_MASK 0x03
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_GN_APG_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_HFG_SQL_MASK 0x7C
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_HFG_SQL_SHIFT 2
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBF_MASK 0x0F
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBF_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBG_MASK 0xF0
+#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBG_SHIFT 4
+
+#define SERDES_25G_LANE_FEATURE_TEST_CFG0_LANE_MSM_DIS_MASK 0x01
+#define SERDES_25G_LANE_FEATURE_TEST_CFG0_LANE_MSM_DIS_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_TEST_CFG0_RX_CTRL_DIS_MASK 0x02
+#define SERDES_25G_LANE_FEATURE_TEST_CFG0_RX_CTRL_DIS_SHIFT 1
+
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG0_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG0_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG1_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG1_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG2_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG2_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG3_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG3_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG4_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG4_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG5_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG5_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG6_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG6_SHIFT 0
+
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG7_MASK 0xFF
+#define SERDES_25G_LANE_FEATURE_SPARE_CFG7_SHIFT 0
+
+#ifdef _cplusplus
+}
+#endif
+
+#endif
diff --git a/al_hal_serdes_25g_regs.h b/al_hal_serdes_25g_regs.h
new file mode 100644
index 000000000000..64422f7e931f
--- /dev/null
+++ b/al_hal_serdes_25g_regs.h
@@ -0,0 +1,434 @@
+/*******************************************************************************
+Copyright (C) 2013 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 or V3 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @{
+ * @file al_hal_serdes_c_regs.h
+ *
+ * @brief ... registers
+ *
+ */
+
+#ifndef __AL_HAL_serdes_c_REGS_H__
+#define __AL_HAL_serdes_c_REGS_H__
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+struct al_serdes_c_gen {
+ /* [0x0] SERDES registers Version */
+ uint32_t version;
+ uint32_t rsrvd_0[3];
+ /* [0x10] SERDES register file address */
+ uint32_t reg_addr;
+ /* [0x14] SERDES register file data */
+ uint32_t reg_data;
+ /* [0x18] SERDES control */
+ uint32_t ctrl;
+ /* [0x1c] SERDES cpu mem address */
+ uint32_t cpu_prog_addr;
+ /* [0x20] SERDES cpu mem data */
+ uint32_t cpu_prog_data;
+ /* [0x24] SERDES data mem address */
+ uint32_t cpu_data_mem_addr;
+ /* [0x28] SERDES data mem data */
+ uint32_t cpu_data_mem_data;
+ /* [0x2c] SERDES control */
+ uint32_t rst;
+ /* [0x30] SERDES control */
+ uint32_t status;
+ uint32_t rsrvd[51];
+};
+struct al_serdes_c_lane {
+ uint32_t rsrvd_0[4];
+ /* [0x10] Data configuration */
+ uint32_t cfg;
+ /* [0x14] Lane status */
+ uint32_t stat;
+ /* [0x18] SERDES control */
+ uint32_t reserved;
+ uint32_t rsrvd[25];
+};
+
+struct al_serdes_c_regs {
+ uint32_t rsrvd_0[64];
+ struct al_serdes_c_gen gen; /* [0x100] */
+ struct al_serdes_c_lane lane[2]; /* [0x200] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** version register ****/
+/* Revision number (Minor) */
+#define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
+#define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
+/* Revision number (Major) */
+#define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
+#define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
+/* date of release */
+#define SERDES_C_GEN_VERSION_DATE_DAY_MASK 0x001F0000
+#define SERDES_C_GEN_VERSION_DATE_DAY_SHIFT 16
+/* month of release */
+#define SERDES_C_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
+#define SERDES_C_GEN_VERSION_DATA_MONTH_SHIFT 21
+/* year of release (starting from 2000) */
+#define SERDES_C_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
+#define SERDES_C_GEN_VERSION_DATE_YEAR_SHIFT 25
+/* Reserved */
+#define SERDES_C_GEN_VERSION_RESERVED_MASK 0xC0000000
+#define SERDES_C_GEN_VERSION_RESERVED_SHIFT 30
+
+/**** reg_addr register ****/
+/* address value */
+#define SERDES_C_GEN_REG_ADDR_VAL_MASK 0x00007FFF
+#define SERDES_C_GEN_REG_ADDR_VAL_SHIFT 0
+
+/**** reg_data register ****/
+/* data value */
+#define SERDES_C_GEN_REG_DATA_VAL_MASK 0x000000FF
+#define SERDES_C_GEN_REG_DATA_VAL_SHIFT 0
+/* Bit-wise write enable */
+#define SERDES_C_GEN_REG_DATA_STRB_MASK 0x0000FF00
+#define SERDES_C_GEN_REG_DATA_STRB_SHIFT 8
+
+/**** ctrl register ****/
+/*
+ * 0x0 – Select reference clock from Bump
+ * 0x1 – Select inter-macro reference clock from the left side
+ * 0x2 – Same as 0x0
+ * 0x3 – Select inter-macro reference clock from the right side
+ */
+#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_MASK 0x00000003
+#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT 0
+
+#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_REF \
+ (0 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
+#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_L2R \
+ (1 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
+#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_R2L \
+ (3 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
+
+/*
+ * 0x0 – Tied to 0 to save power
+ * 0x1 – Select reference clock from Bump
+ * 0x2 – Select inter-macro reference clock input from right side
+ * 0x3 – Same as 0x2
+ */
+#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_MASK 0x00000030
+#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT 4
+
+#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_0 \
+ (0 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
+#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_REF \
+ (1 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
+#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_R2L \
+ (2 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
+
+/*
+ * 0x0 – Tied to 0 to save power
+ * 0x1 – Select reference clock from Bump
+ * 0x2 – Select inter-macro reference clock input from left side
+ * 0x3 – Same as 0x2
+ */
+#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_MASK 0x000000C0
+#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT 6
+
+#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_0 \
+ (0 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
+#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_REF \
+ (1 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
+#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_L2R \
+ (2 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
+
+/*
+ * Program memory acknowledge - Only when the access
+ * to the program memory is not
+ * ready for the microcontroller, it
+ * is driven to 0
+ */
+#define SERDES_C_GEN_CTRL_CPU_MEMPSACK (1 << 8)
+/*
+ * Data memory acknowledge - Only when the access
+ * to the program memory is not
+ * ready for the microcontroller, it
+ * is driven to 0
+ */
+#define SERDES_C_GEN_CTRL_CPU_MEMACK (1 << 12)
+/*
+ * 0 - keep cpu clk as sb clk
+ * 1 – cpu_clk is sb_clk divided by 2
+ */
+#define SERDES_C_GEN_CTRL_CPU_CLK_DIV (1 << 16)
+/*
+ * 0x0 – OIF CEI-28G-SR
+ * 0x1 – OIF CIE-25G-LR
+ * 0x8 – XFI
+ * Others – Reserved
+ *
+ * Note that phy_ctrl_cfg_i[3] is used to signify high-speed/low-speed
+ */
+#define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_MASK 0x00F00000
+#define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_SHIFT 20
+/*
+ * 0 - Internal 8051 micro- controller is allowed to access the internal APB
+ * CSR. Internal APB runs at cpu_clk_i, and the accesses from the external APB
+ * in apb_clk_i domain to APB CSR are resynchronized to cpu_clk_i. 1 – Bypass
+ * CPU. Internal 8051 micro-controller is blocked from accessing the internal
+ * APB CSR. Internal APB runs at apb_clk_i.
+ */
+#define SERDES_C_GEN_CTRL_CPU_BYPASS (1 << 24)
+
+/**** cpu_prog_addr register ****/
+/*
+ * address value 32 bit,
+ * The firmware data will be 1 byte with 64K rows
+ */
+#define SERDES_C_GEN_CPU_PROG_ADDR_VAL_MASK 0x00007FFF
+#define SERDES_C_GEN_CPU_PROG_ADDR_VAL_SHIFT 0
+
+/**** cpu_data_mem_addr register ****/
+/* address value – 8K byte memory */
+#define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_MASK 0x00001FFF
+#define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_SHIFT 0
+
+/**** cpu_data_mem_data register ****/
+/* data value */
+#define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_MASK 0x000000FF
+#define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_SHIFT 0
+
+/**** rst register ****/
+/* Power on reset Signal – active low */
+#define SERDES_C_GEN_RST_POR_N (1 << 0)
+/* CMU reset Active low */
+#define SERDES_C_GEN_RST_CM0_RST_N (1 << 1)
+/*
+ * 0x0 – Normal / Active
+ * 0x1 – Partial power down
+ * 0x2 – Near complete power down (only
+ * refclk buffers and portions of analog bias
+ * active)
+ * 0x3 – complete power down (IDDQ mode)
+ * Can be asserted when CMU is in normal
+ * mode. These modes provide an increased
+ * power savings compared to reset mode.
+ * Signal is overridden by por_n_i so has no
+ * effect in power on reset state.
+ */
+#define SERDES_C_GEN_RST_CM0_PD_MASK 0x00000030
+#define SERDES_C_GEN_RST_CM0_PD_SHIFT 4
+/* Lane0 reset signal active low */
+#define SERDES_C_GEN_RST_LN0_RST_N (1 << 6)
+/* Lane1 reset signal active low */
+#define SERDES_C_GEN_RST_LN1_RST_N (1 << 7)
+/*
+ * 0x0 – Normal / Active
+ * 0x1 – Partial power down
+ * 0x2 – Most blocks powered down (only LOS
+ * active)
+ * 0x3 – complete power down (IDDQ mode)
+ * Can be asserted when Lane is in normal
+ * mode. These modes provide an increased
+ * power savings compared to reset mode.
+ * Signal is overridden by por_n_i so has no
+ * affect in power on reset state
+ */
+#define SERDES_C_GEN_RST_LN0_PD_MASK 0x00000300
+#define SERDES_C_GEN_RST_LN0_PD_SHIFT 8
+/*
+ * 0x0 – Normal / Active
+ * 0x1 – Partial power down
+ * 0x2 – Most blocks powered down (only LOS
+ * active)
+ * 0x3 – complete power down (IDDQ mode)
+ * Can be asserted when Lane is in normal
+ * mode. These modes provide an increased
+ * power savings compared to reset mode.
+ * Signal is overridden by por_n_i so has no
+ * affect in power on reset state
+ */
+#define SERDES_C_GEN_RST_LN1_PD_MASK 0x00000C00
+#define SERDES_C_GEN_RST_LN1_PD_SHIFT 10
+
+#define SERDES_C_GEN_RST_CPU_MEM_RESET (1 << 12)
+
+#define SERDES_C_GEN_RST_CPU_MEM_SHUTDOWN (1 << 13)
+
+#define SERDES_C_GEN_RST_CAPRI_APB_RESET (1 << 14)
+
+/**** status register ****/
+/*
+ * 0x0 – No error
+ * 0x1 – PHY has an internal error
+ */
+#define SERDES_C_GEN_STATUS_ERR_O (1 << 0)
+/*
+ * 0x0 – PHY is not ready to respond to
+ * cm0_rst_n_i and cm0_pd_i[1:0]. The
+ * signals should not be changed.
+ * 0x1 - PHY is ready to respond to
+ * cm0_rst_n_i and cm0_pd_i[1:0]
+ */
+#define SERDES_C_GEN_STATUS_CM0_RST_PD_READY (1 << 1)
+/*
+ * Indicates CMU PLL has locked to the
+ * reference clock and all output clocks are at
+ * the correct frequency
+ */
+#define SERDES_C_GEN_STATUS_CM0_OK_O (1 << 2)
+/*
+ * 0x0 – PHY is not ready to respond to
+ * ln0_rst_n and ln0_pd[1:0]. The signals
+ * should not be changed.
+ * 0x1 - PHY is ready to respond to lnX_rst_n_i
+ * and lnX_pd_i[1:0]
+ */
+#define SERDES_C_GEN_STATUS_LN0_RST_PD_READY (1 << 3)
+/*
+ * 0x0 – PHY is not ready to respond to
+ * ln1_rst_n_i and ln1_pd[1:0]. The signals
+ * should not be changed.
+ * 0x1 - PHY is ready to respond to lnX_rst_n_i
+ * and lnX_pd_i[1:0]
+ */
+#define SERDES_C_GEN_STATUS_LN1_RST_PD_READY (1 << 4)
+/*
+ * Active low when the CPU performs a wait cycle (internally or externally
+ * generated)
+ */
+#define SERDES_C_GEN_STATUS_CPU_WAITSTATE (1 << 5)
+
+#define SERDES_C_GEN_STATUS_TBUS_MASK 0x000FFF00
+#define SERDES_C_GEN_STATUS_TBUS_SHIFT 8
+
+/**** cfg register ****/
+/* 1- Swap 32 bit data on RX side */
+#define SERDES_C_LANE_CFG_RX_LANE_SWAP (1 << 0)
+/* 1- Swap 32 bit data on TX side */
+#define SERDES_C_LANE_CFG_TX_LANE_SWAP (1 << 1)
+/* 1 – invert rx data polarity */
+#define SERDES_C_LANE_CFG_LN_CTRL_RXPOLARITY (1 << 2)
+/* 1 – invert tx data polarity */
+#define SERDES_C_LANE_CFG_TX_LANE_POLARITY (1 << 3)
+/*
+ * 0x0 –Data on lnX_txdata_o will not be
+ * transmitted. Transmitter will be placed into
+ * electrical idle.
+ * 0x1 – Data on the active bits of
+ * lnX_txdata_o will be transmitted
+ */
+#define SERDES_C_LANE_CFG_LN_CTRL_TX_EN (1 << 4)
+/*
+ * Informs the PHY to bypass the output of the
+ * analog LOS detector and instead rely upon
+ * a protocol LOS mechanism in the SoC/ASIC
+ * 0x0 – LOS operates as normal
+ * 0x1 – Bypass analog LOS output and
+ * instead rely upon protocol-level LOS
+ * detection via input lnX_ctrl_los_eii_value
+ */
+#define SERDES_C_LANE_CFG_LN_CTRL_LOS_EII_EN (1 << 5)
+/*
+ * If lnX_ctrl_los_eii_en_i = 1 then Informs
+ * the PHY that the received signal was lost
+ */
+#define SERDES_C_LANE_CFG_LN_CTRL_LOS_EII_VALUE (1 << 6)
+/* One hot mux */
+#define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_MASK 0x00000F00
+#define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_SHIFT 8
+/* 0x0 - 20-bit 0x1 – 40-bit */
+#define SERDES_C_LANE_CFG_LN_CTRL_DATA_WIDTH (1 << 12)
+
+/**** stat register ****/
+/*
+ * x0 – lane is not ready to send and receive data
+ * 0x1 – lane is ready to send and receive data
+ */
+#define SERDES_C_LANE_STAT_LNX_STAT_OK (1 << 0)
+/*
+ * 0x0 – received data run length has not
+ * exceed the programmable run length
+ * detector threshold
+ * 0x1 – received data run length has
+ * exceeded the programmable run length
+ * detector threshold
+ */
+#define SERDES_C_LANE_STAT_LN_STAT_RUNLEN_ERR (1 << 1)
+/*
+ * 0x0 – data on lnX_rxdata_o are invalid
+ * 0x1 – data on the active bits of
+ * lnX_rxdata_o are valid
+ */
+#define SERDES_C_LANE_STAT_LN_STAT_RXVALID (1 << 2)
+/*
+ * Loss of Signal (LOS) indicator that includes
+ * the combined functions of the digitally
+ * assisted analog LOS, digital LOS, and
+ * protocol LOS override features
+ * 0x0 – Signal detected on lnX_rxp_i /
+ * lnX_rxm_i pins
+ * 0x1 – No signal detected on lnX_rxp_i /
+ * lnX_rxm_i pins
+ */
+#define SERDES_C_LANE_STAT_LN_STAT_LOS (1 << 3)
+
+#define SERDES_C_LANE_STAT_LN_STAT_LOS_DEGLITCH (1 << 4)
+
+/**** reserved register ****/
+
+#define SERDES_C_LANE_RESERVED_DEF_0_MASK 0x0000FFFF
+#define SERDES_C_LANE_RESERVED_DEF_0_SHIFT 0
+
+#define SERDES_C_LANE_RESERVED_DEF_1_MASK 0xFFFF0000
+#define SERDES_C_LANE_RESERVED_DEF_1_SHIFT 16
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_serdes_c_REGS_H__ */
+
+/** @} end of ... group */
+
+
diff --git a/al_hal_serdes_hssp.h b/al_hal_serdes_hssp.h
new file mode 100644
index 000000000000..fe530f6a31be
--- /dev/null
+++ b/al_hal_serdes_hssp.h
@@ -0,0 +1,87 @@
+/*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_serdes_api API
+ * SerDes HAL driver API
+ * @ingroup group_serdes SerDes
+ * @{
+ *
+ * @file al_hal_serdes.h
+ *
+ * @brief Header file for the SerDes HAL driver
+ *
+ */
+
+#ifndef __AL_HAL_SERDES_H__
+#define __AL_HAL_SERDES_H__
+
+#include "al_hal_common.h"
+#include "al_hal_serdes_interface.h"
+#include "al_hal_serdes_hssp_regs.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/**
+ * Initializes a SERDES group object
+ *
+ * @param serdes_regs_base
+ * The SERDES register file base pointer
+ *
+ * @param obj
+ * An allocated, non initialized object context
+ *
+ * @return 0 if no error found.
+ *
+ */
+int al_serdes_hssp_handle_init(
+ void __iomem *serdes_regs_base,
+ struct al_serdes_grp_obj *obj);
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+}
+#endif
+
+/* *INDENT-ON* */
+#endif /* __AL_SRDS__ */
+
+/** @} end of SERDES group */
+
diff --git a/al_hal_serdes_hssp_internal_regs.h b/al_hal_serdes_hssp_internal_regs.h
new file mode 100644
index 000000000000..d5b021519942
--- /dev/null
+++ b/al_hal_serdes_hssp_internal_regs.h
@@ -0,0 +1,749 @@
+/*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __AL_SERDES_INTERNAL_REGS_H__
+#define __AL_SERDES_INTERNAL_REGS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Per lane register fields
+ ******************************************************************************/
+/*
+ * RX and TX lane hard reset
+ * 0 - Hard reset is asserted
+ * 1 - Hard reset is de-asserted
+ */
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM 2
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK 0x01
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT 0x00
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT 0x01
+
+/*
+ * RX and TX lane hard reset control
+ * 0 - Hard reset is taken from the interface pins
+ * 1 - Hard reset is taken from registers
+ */
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM 2
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK 0x02
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_IFACE 0x00
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS 0x02
+
+/* RX lane power state control */
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM 3
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK 0x1f
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD 0x01
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2 0x02
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1 0x04
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S 0x08
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0 0x10
+
+/* TX lane power state control */
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM 4
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK 0x1f
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD 0x01
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2 0x02
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1 0x04
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S 0x08
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0 0x10
+
+/* RX lane word width */
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM 5
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK 0x07
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_8 0x00
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_10 0x01
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_16 0x02
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20 0x03
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_32 0x04
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_40 0x05
+
+/* TX lane word width */
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM 5
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK 0x70
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_8 0x00
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_10 0x10
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_16 0x20
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20 0x30
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_32 0x40
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_40 0x50
+
+/* RX lane rate select */
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM 6
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_MASK 0x07
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8 0x00
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4 0x01
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2 0x02
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1 0x03
+
+/* TX lane rate select */
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM 6
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_MASK 0x70
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8 0x00
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4 0x10
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2 0x20
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1 0x30
+
+/*
+ * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
+ * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
+ * partial equalized RX signal out the transmit IO pins
+ */
+#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM 7
+#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN 0x10
+
+/*
+ * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
+ * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
+ * the TX serializer output into the CDR
+ */
+#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM 7
+#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN 0x20
+
+/*
+ * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
+ * RX pads). Serial IO loopback from the transmit lane IO pins to the receive
+ * lane IO pins: 0 - Disables loopback 1 - Loops back the driver IO signal to
+ * the RX IO pins
+ */
+#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM 7
+#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN 0x40
+
+/*
+ * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
+ * receive lane 20-bit data ports, to the transmit lane 20-bit data ports 0 -
+ * Disables loopback 1 - Loops back the 20-bit receive data port to the
+ * transmitter
+ */
+#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM 7
+#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN 0x80
+
+/*
+ * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
+ * Transmit bit clock select: 0 - Selects synthesizer bit clock for transmit 1
+ * - Selects CDR clock for transmit
+ */
+#define SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM 7
+#define SERDES_IREG_FLD_LB_CDRCLK2TXEN 0x01
+
+/* Receive lane BIST enable. Active High */
+#define SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM 8
+#define SERDES_IREG_FLD_PCSRXBIST_EN 0x01
+
+/* TX lane BIST enable. Active High */
+#define SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM 8
+#define SERDES_IREG_FLD_PCSTXBIST_EN 0x02
+
+/*
+ * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
+ * the test has completed, and will remain high until a new test is initiated
+ */
+#define SERDES_IREG_FLD_RXBIST_DONE_REG_NUM 8
+#define SERDES_IREG_FLD_RXBIST_DONE 0x04
+
+/*
+ * RX BIST error count overflow indicator. Indicates an overflow in the number
+ * of byte errors identified during the course of the test. This word is stable
+ * to sample when *_DONE_* signal has asserted
+ */
+#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM 8
+#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW 0x08
+
+/*
+ * RX BIST locked indicator 0 - Indicates BIST is not word locked and error
+ * comparisons have not begun yet 1 - Indicates BIST is word locked and error
+ * comparisons have begun
+ */
+#define SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM 8
+#define SERDES_IREG_FLD_RXBIST_RXLOCKED 0x10
+
+/*
+ * RX BIST error count word. Indicates the number of byte errors identified
+ * during the course of the test. This word is stable to sample when *_DONE_*
+ * signal has asserted
+ */
+#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM 9
+#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM 10
+
+/* Tx params */
+#define SERDES_IREG_TX_DRV_1_REG_NUM 21
+#define SERDES_IREG_TX_DRV_1_HLEV_MASK 0x7
+#define SERDES_IREG_TX_DRV_1_HLEV_SHIFT 0
+#define SERDES_IREG_TX_DRV_1_LEVN_MASK 0xf8
+#define SERDES_IREG_TX_DRV_1_LEVN_SHIFT 3
+
+#define SERDES_IREG_TX_DRV_2_REG_NUM 22
+#define SERDES_IREG_TX_DRV_2_LEVNM1_MASK 0xf
+#define SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT 0
+#define SERDES_IREG_TX_DRV_2_LEVNM2_MASK 0x30
+#define SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT 4
+
+#define SERDES_IREG_TX_DRV_3_REG_NUM 23
+#define SERDES_IREG_TX_DRV_3_LEVNP1_MASK 0x7
+#define SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT 0
+#define SERDES_IREG_TX_DRV_3_SLEW_MASK 0x18
+#define SERDES_IREG_TX_DRV_3_SLEW_SHIFT 3
+
+/* Rx params */
+#define SERDES_IREG_RX_CALEQ_1_REG_NUM 24
+#define SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK 0x7
+#define SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT 0
+/* DFE post-shaping tap 3dB frequency */
+#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK 0x38
+#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT 3
+
+#define SERDES_IREG_RX_CALEQ_2_REG_NUM 25
+/* DFE post-shaping tap gain */
+#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK 0x7
+#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT 0
+/* DFE first tap gain control */
+#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK 0x78
+#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT 3
+
+#define SERDES_IREG_RX_CALEQ_3_REG_NUM 26
+#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK 0xf
+#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT 0
+#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK 0xf0
+#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT 4
+
+#define SERDES_IREG_RX_CALEQ_4_REG_NUM 27
+#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK 0xf
+#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT 0
+#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK 0x70
+#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT 4
+
+#define SERDES_IREG_RX_CALEQ_5_REG_NUM 28
+#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK 0x7
+#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT 0
+#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK 0xf8
+#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT 3
+
+/* RX lane best eye point measurement result */
+#define SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM 29
+#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM 30
+#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK 0x3F
+
+/*
+ * Adaptive RX Equalization enable
+ * 0 - Disables adaptive RX equalization.
+ * 1 - Enables adaptive RX equalization.
+ */
+#define SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM 31
+#define SERDES_IREG_FLD_PCSRXEQ_START (1 << 0)
+
+/*
+ * Enables an eye diagram measurement
+ * within the PHY.
+ * 0 - Disables eye diagram measurement
+ * 1 - Enables eye diagram measurement
+ */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM 31
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START (1 << 1)
+
+
+/*
+ * RX lane single roam eye point measurement start signal.
+ * If asserted, single measurement at fix XADJUST and YADJUST is started.
+ */
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM 31
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START (1 << 2)
+
+
+/*
+ * PHY Eye diagram measurement status
+ * signal
+ * 0 - Indicates eye diagram results are not
+ * valid for sampling
+ * 1 - Indicates eye diagram is complete and
+ * results are valid for sampling
+ */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM 32
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE (1 << 0)
+
+/*
+ * Eye diagram error signal. Indicates if the
+ * measurement was invalid because the eye
+ * diagram was interrupted by the link entering
+ * electrical idle.
+ * 0 - Indicates eye diagram is valid
+ * 1- Indicates an error occurred, and the eye
+ * diagram measurement should be re-run
+ */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR_REG_NUM 32
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR (1 << 1)
+
+/*
+ * PHY Adaptive Equalization status
+ * 0 - Indicates Adaptive Equalization results are not valid for sampling
+ * 1 - Indicates Adaptive Equalization is complete and results are valid for
+ * sampling
+ */
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM 32
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE (1 << 2)
+
+/*
+ *
+ * PHY Adaptive Equalization Status Signal
+ * 0 – Indicates adaptive equalization results
+ * are not valid for sampling
+ * 1 – Indicates adaptive equalization is
+ * complete and results are valid for sampling.
+ */
+#define SERDES_IREG_FLD_RXEQ_DONE_REG_NUM 32
+#define SERDES_IREG_FLD_RXEQ_DONE (1 << 3)
+
+
+/*
+ * 7-bit eye diagram time adjust control
+ * - 6-bits per UI
+ * - spans 2 UI
+ */
+#define SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM 33
+
+/* 6-bit eye diagram voltage adjust control - spans +/-300mVdiff */
+#define SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM 34
+
+/*
+ * Eye diagram status signal. Safe for
+ * sampling when *DONE* signal has
+ * asserted
+ * 14'h0000 - Completely Closed Eye
+ * 14'hFFFF - Completely Open Eye
+ */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM 35
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_MAKE 0xFF
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_SHIFT 0
+
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM 36
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE 0x3F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_SHIFT 0
+
+/*
+ * RX lane single roam eye point measurement result.
+ * If 0, eye is open at current XADJUST and YADJUST settings.
+ */
+#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM 37
+#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM 38
+
+/*
+ * Override enable for CDR lock to reference clock
+ * 0 - CDR is always locked to reference
+ * 1 - CDR operation mode (Lock2Reference or Lock2data are controlled internally
+ * depending on the incoming signal and ppm status)
+ */
+#define SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM 39
+#define SERDES_IREG_FLD_RXLOCK2REF_OVREN (1 << 1)
+
+/*
+ * Selects Eye to capture based on edge
+ * 0 - Capture 1st Eye in Eye Diagram
+ * 1 - Capture 2nd Eye in Eye Diagram measurement
+ */
+#define SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM 39
+#define SERDES_IREG_FLD_RXROAM_XORBITSEL (1 << 2)
+#define SERDES_IREG_FLD_RXROAM_XORBITSEL_1ST 0
+#define SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND (1 << 2)
+
+/*
+ * RX Signal detect. 0 indicates no signal, 1 indicates signal detected.
+ */
+#define SERDES_IREG_FLD_RXRANDET_REG_NUM 41
+#define SERDES_IREG_FLD_RXRANDET_STAT 0x20
+
+/*
+ * RX data polarity inversion control:
+ * 1'b0: no inversion
+ * 1'b1: invert polarity
+ */
+#define SERDES_IREG_FLD_POLARITY_RX_REG_NUM 46
+#define SERDES_IREG_FLD_POLARITY_RX_INV (1 << 0)
+
+/*
+ * TX data polarity inversion control:
+ * 1'b0: no inversion
+ * 1'b1: invert polarity
+ */
+#define SERDES_IREG_FLD_POLARITY_TX_REG_NUM 46
+#define SERDES_IREG_FLD_POLARITY_TX_INV (1 << 1)
+
+/* LANEPCSPSTATE* override enable (Active low) */
+#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM 85
+#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN (1 << 0)
+
+/* LB* override enable (Active low) */
+#define SERDES_IREG_FLD_LB_LOCWREN_REG_NUM 85
+#define SERDES_IREG_FLD_LB_LOCWREN (1 << 1)
+
+/* PCSRX* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM 85
+#define SERDES_IREG_FLD_PCSRX_LOCWREN (1 << 4)
+
+/* PCSRXBIST* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM 85
+#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN (1 << 5)
+
+/* PCSRXEQ* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM 85
+#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN (1 << 6)
+
+/* PCSTX* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM 85
+#define SERDES_IREG_FLD_PCSTX_LOCWREN (1 << 7)
+
+/*
+ * group registers:
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN,
+ * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
+ * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
+ */
+#define SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM 86
+
+/* PCSTXBIST* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM 86
+#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN (1 << 0)
+
+/* Override RX_CALCEQ through the internal registers (Active low) */
+#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM 86
+#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN (1 << 3)
+
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM 86
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN (1 << 4)
+
+
+/* RXCALROAMEYEMEASIN* override enable - Active Low */
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM 86
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN (1 << 6)
+
+/* RXCALROAMXADJUST* override enable - Active Low */
+#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM 86
+#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN (1 << 7)
+
+/* RXCALROAMYADJUST* override enable - Active Low */
+#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM 87
+#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN (1 << 0)
+
+/* RXCDRCALFOSC* override enable. Active Low */
+#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN_REG_NUM 87
+#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN (1 << 1)
+
+/* Over-write enable for RXEYEDIAGFSM_INITXVAL */
+#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN_REG_NUM 87
+#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN (1 << 2)
+
+/* Over-write enable for CMNCLKGENMUXSEL_TXINTERNAL */
+#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN_REG_NUM 87
+#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN (1 << 3)
+
+/* TXCALTCLKDUTY* override enable. Active Low */
+#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN_REG_NUM 87
+#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN (1 << 4)
+
+/* Override TX_DRV through the internal registers (Active low) */
+#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM 87
+#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN (1 << 5)
+
+/*******************************************************************************
+ * Common lane register fields - PMA
+ ******************************************************************************/
+/*
+ * Common lane hard reset control
+ * 0 - Hard reset is taken from the interface pins
+ * 1 - Hard reset is taken from registers
+ */
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM 2
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK 0x01
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_IFACE 0x00
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS 0x01
+
+/*
+ * Common lane hard reset
+ * 0 - Hard reset is asserted
+ * 1 - Hard reset is de-asserted
+ */
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM 2
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK 0x02
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT 0x00
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT 0x02
+
+/* Synth power state control */
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM 3
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK 0x1f
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD 0x01
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2 0x02
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1 0x04
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S 0x08
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0 0x10
+
+/* Transmit datapath FIFO enable (Active High) */
+#define SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM 8
+#define SERDES_IREG_FLD_CMNPCS_TXENABLE (1 << 2)
+
+/*
+ * RX lost of signal detector enable
+ * - 0 - disable
+ * - 1 - enable
+ */
+#define SERDES_IREG_FLD_RXLOSDET_ENABLE_REG_NUM 13
+#define SERDES_IREG_FLD_RXLOSDET_ENABLE AL_BIT(4)
+
+/* Signal Detect Threshold Level */
+#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_REG_NUM 15
+#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK AL_FIELD_MASK(2, 0)
+
+/* LOS Detect Threshold Level */
+#define SERDES_IREG_FLD_RXLOSDET_THRESH_REG_NUM 15
+#define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK AL_FIELD_MASK(4, 3)
+#define SERDES_IREG_FLD_RXLOSDET_THRESH_SHIFT 3
+
+#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM 30
+#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK 0x7f
+#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT 0
+
+#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM 31
+#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK 0x7f
+#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT 0
+
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM 32
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK 0xff
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT 0
+
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM 33
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK 0x1
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT 0
+
+#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM 33
+#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK 0x3e
+#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT 1
+
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM 34
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK 0xff
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT 0
+
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM 35
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK 0x1
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT 0
+
+#define SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM 35
+#define SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK 0x3e
+#define SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT 1
+
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM 36
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK 0xff
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT 0
+
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM 37
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK 0x7
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT 0
+
+#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM 43
+#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK 0x7
+#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT 0
+
+#define SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(byte_num) (56 + (byte_num))
+#define SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES 10
+
+/*
+ * Selects the transmit BIST mode:
+ * 0 - Uses the 80-bit internal memory pattern (w/ OOB)
+ * 1 - Uses a 27 PRBS pattern
+ * 2 - Uses a 223 PRBS pattern
+ * 3 - Uses a 231 PRBS pattern
+ * 4 - Uses a 1010 clock pattern
+ * 5 and above - Reserved
+ */
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM 80
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK 0x07
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER 0x00
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7 0x01
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23 0x02
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31 0x03
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010 0x04
+
+/* Single-Bit error injection enable (on posedge) */
+#define SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM 80
+#define SERDES_IREG_FLD_TXBIST_BITERROR_EN 0x20
+
+/* CMNPCIEGEN3* override enable (Active Low) */
+#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM 95
+#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN (1 << 2)
+
+/* CMNPCS* override enable (Active Low) */
+#define SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM 95
+#define SERDES_IREG_FLD_CMNPCS_LOCWREN (1 << 3)
+
+/* CMNPCSBIST* override enable (Active Low) */
+#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM 95
+#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN (1 << 4)
+
+/* CMNPCSPSTATE* override enable (Active Low) */
+#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM 95
+#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN (1 << 5)
+
+/* PCS_EN* override enable (Active Low) */
+#define SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM 96
+#define SERDES_IREG_FLD_PCS_LOCWREN (1 << 3)
+
+/* Eye diagram sample count */
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM 150
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK 0xff
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT 0
+
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM 151
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK 0xff
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT 0
+
+/* override control */
+#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM 230
+#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN 1 << 0
+
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM 623
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK 0xff
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT 0
+
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM 624
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK 0xff
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT 0
+
+/* X and Y coefficient return value */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM 626
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_MASK 0x0F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_SHIFT 0
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_MASK 0xF0
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_SHIFT 4
+
+/* X coarse scan step */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM 627
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK 0x7F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT 0
+
+/* X fine scan step */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM 628
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK 0x7F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT 0
+
+/* Y coarse scan step */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM 629
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK 0x0F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT 0
+
+/* Y fine scan step */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM 630
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK 0x0F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT 0
+
+#define SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM 157
+
+#define SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM 158
+
+#define SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM 159
+
+#define SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM 160
+
+#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM 163
+
+#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM 164
+
+/*******************************************************************************
+ * Common lane register fields - PCS
+ ******************************************************************************/
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM 3
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK AL_FIELD_MASK(5, 4)
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT 4
+
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM 6
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA AL_BIT(2)
+
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM 18
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK 0x1F
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT 0
+
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM 19
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK 0x7C
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT 2
+
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM 20
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK 0x1F
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT 0
+
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM 21
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK 0x7C
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT 2
+
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_REG_NUM 22
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_MASK 0x7f
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_SHIFT 0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_REG_NUM 34
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_MASK 0x7f
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_SHIFT 0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_REG_NUM 23
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_MASK 0xff
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_SHIFT 0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_REG_NUM 22
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_MASK 0x80
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_SHIFT 7
+
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_REG_NUM 24
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_MASK 0x3e
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_SHIFT 1
+
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_REG_NUM 35
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_MASK 0xff
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_SHIFT 0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_REG_NUM 34
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_MASK 0x80
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_SHIFT 7
+
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_REG_NUM 36
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_MASK 0x1f
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_SHIFT 0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_REG_NUM 37
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_MASK 0xff
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_SHIFT 0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_REG_NUM 36
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_MASK 0xe0
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_SHIFT 5
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_serdes_REG_H */
+
diff --git a/al_hal_serdes_hssp_regs.h b/al_hal_serdes_hssp_regs.h
new file mode 100644
index 000000000000..20f6cbfa0206
--- /dev/null
+++ b/al_hal_serdes_hssp_regs.h
@@ -0,0 +1,494 @@
+/*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @{
+ * @file al_hal_serdes_regs.h
+ *
+ * @brief ... registers
+ *
+ */
+
+#ifndef __AL_HAL_SERDES_REGS_H__
+#define __AL_HAL_SERDES_REGS_H__
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+struct serdes_gen {
+ /* [0x0] SerDes Registers Version */
+ uint32_t version;
+ uint32_t rsrvd_0[3];
+ /* [0x10] SerDes register file address */
+ uint32_t reg_addr;
+ /* [0x14] SerDes register file data */
+ uint32_t reg_data;
+ uint32_t rsrvd_1[2];
+ /* [0x20] SerDes control */
+ uint32_t ictl_multi_bist;
+ /* [0x24] SerDes control */
+ uint32_t ictl_pcs;
+ /* [0x28] SerDes control */
+ uint32_t ictl_pma;
+ uint32_t rsrvd_2;
+ /* [0x30] SerDes control */
+ uint32_t ipd_multi_synth;
+ /* [0x34] SerDes control */
+ uint32_t irst;
+ /* [0x38] SerDes control */
+ uint32_t octl_multi_synthready;
+ /* [0x3c] SerDes control */
+ uint32_t octl_multi_synthstatus;
+ /* [0x40] SerDes control */
+ uint32_t clk_out;
+ uint32_t rsrvd[47];
+};
+struct serdes_lane {
+ uint32_t rsrvd1[4];
+ /* [0x10] SerDes status */
+ uint32_t octl_pma;
+ /* [0x14] SerDes control */
+ uint32_t ictl_multi_andme;
+ /* [0x18] SerDes control */
+ uint32_t ictl_multi_lb;
+ /* [0x1c] SerDes control */
+ uint32_t ictl_multi_rxbist;
+ /* [0x20] SerDes control */
+ uint32_t ictl_multi_txbist;
+ /* [0x24] SerDes control */
+ uint32_t ictl_multi;
+ /* [0x28] SerDes control */
+ uint32_t ictl_multi_rxeq;
+ /* [0x2c] SerDes control */
+ uint32_t ictl_multi_rxeq_l_low;
+ /* [0x30] SerDes control */
+ uint32_t ictl_multi_rxeq_l_high;
+ /* [0x34] SerDes control */
+ uint32_t ictl_multi_rxeyediag;
+ /* [0x38] SerDes control */
+ uint32_t ictl_multi_txdeemph;
+ /* [0x3c] SerDes control */
+ uint32_t ictl_multi_txmargin;
+ /* [0x40] SerDes control */
+ uint32_t ictl_multi_txswing;
+ /* [0x44] SerDes control */
+ uint32_t idat_multi;
+ /* [0x48] SerDes control */
+ uint32_t ipd_multi;
+ /* [0x4c] SerDes control */
+ uint32_t octl_multi_rxbist;
+ /* [0x50] SerDes control */
+ uint32_t octl_multi;
+ /* [0x54] SerDes control */
+ uint32_t octl_multi_rxeyediag;
+ /* [0x58] SerDes control */
+ uint32_t odat_multi_rxbist;
+ /* [0x5c] SerDes control */
+ uint32_t odat_multi_rxeq;
+ /* [0x60] SerDes control */
+ uint32_t multi_rx_dvalid;
+ /* [0x64] SerDes control */
+ uint32_t reserved;
+ uint32_t rsrvd[6];
+};
+
+struct al_serdes_regs {
+ uint32_t rsrvd_0[64];
+ struct serdes_gen gen; /* [0x100] */
+ struct serdes_lane lane[4]; /* [0x200] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** version register ****/
+/* Revision number (Minor) */
+#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
+#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
+/* Revision number (Major) */
+#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
+#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
+/* Date of release */
+#define SERDES_GEN_VERSION_DATE_DAY_MASK 0x001F0000
+#define SERDES_GEN_VERSION_DATE_DAY_SHIFT 16
+/* Month of release */
+#define SERDES_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
+#define SERDES_GEN_VERSION_DATA_MONTH_SHIFT 21
+/* Year of release (starting from 2000) */
+#define SERDES_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
+#define SERDES_GEN_VERSION_DATE_YEAR_SHIFT 25
+/* Reserved */
+#define SERDES_GEN_VERSION_RESERVED_MASK 0xC0000000
+#define SERDES_GEN_VERSION_RESERVED_SHIFT 30
+
+/**** reg_addr register ****/
+/* Address value */
+#define SERDES_GEN_REG_ADDR_VAL_MASK 0x0000FFFF
+#define SERDES_GEN_REG_ADDR_VAL_SHIFT 0
+
+/**** reg_data register ****/
+/* Data value */
+#define SERDES_GEN_REG_DATA_VAL_MASK 0x000000FF
+#define SERDES_GEN_REG_DATA_VAL_SHIFT 0
+
+/**** ICTL_MULTI_BIST register ****/
+
+#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_MASK 0x00000007
+#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_SHIFT 0
+
+/**** ICTL_PCS register ****/
+
+#define SERDES_GEN_ICTL_PCS_EN_NT (1 << 0)
+
+/**** ICTL_PMA register ****/
+
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_MASK 0x00000007
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT 0
+
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_REF \
+ (0 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_R2L \
+ (3 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_L2R \
+ (4 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
+
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_MASK 0x00000070
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT 4
+
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_0 \
+ (0 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_REF \
+ (2 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_R2L \
+ (3 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
+
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_MASK 0x00000700
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT 8
+
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_0 \
+ (0 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_REF \
+ (2 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_L2R \
+ (3 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
+
+#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC (1 << 11)
+#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_THIS (0 << 11)
+#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_MASTER (1 << 11)
+
+#define SERDES_GEN_ICTL_PMA_TXENABLE_A (1 << 12)
+
+#define SERDES_GEN_ICTL_PMA_SYNTHCKBYPASSEN_NT (1 << 13)
+
+/**** IPD_MULTI_SYNTH register ****/
+
+#define SERDES_GEN_IPD_MULTI_SYNTH_B (1 << 0)
+
+/**** IRST register ****/
+
+#define SERDES_GEN_IRST_PIPE_RST_L3_B_A (1 << 0)
+
+#define SERDES_GEN_IRST_PIPE_RST_L2_B_A (1 << 1)
+
+#define SERDES_GEN_IRST_PIPE_RST_L1_B_A (1 << 2)
+
+#define SERDES_GEN_IRST_PIPE_RST_L0_B_A (1 << 3)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A (1 << 4)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A (1 << 5)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A (1 << 6)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A (1 << 7)
+
+#define SERDES_GEN_IRST_MULTI_HARD_SYNTH_B_A (1 << 8)
+
+#define SERDES_GEN_IRST_POR_B_A (1 << 12)
+
+#define SERDES_GEN_IRST_PIPE_RST_L3_B_A_SEL (1 << 16)
+
+#define SERDES_GEN_IRST_PIPE_RST_L2_B_A_SEL (1 << 17)
+
+#define SERDES_GEN_IRST_PIPE_RST_L1_B_A_SEL (1 << 18)
+
+#define SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL (1 << 19)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A_SEL (1 << 20)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A_SEL (1 << 21)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A_SEL (1 << 22)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A_SEL (1 << 23)
+
+/**** OCTL_MULTI_SYNTHREADY register ****/
+
+#define SERDES_GEN_OCTL_MULTI_SYNTHREADY_A (1 << 0)
+
+/**** OCTL_MULTI_SYNTHSTATUS register ****/
+
+#define SERDES_GEN_OCTL_MULTI_SYNTHSTATUS_A (1 << 0)
+
+/**** clk_out register ****/
+
+#define SERDES_GEN_CLK_OUT_SEL_MASK 0x0000003F
+#define SERDES_GEN_CLK_OUT_SEL_SHIFT 0
+
+/**** OCTL_PMA register ****/
+
+#define SERDES_LANE_OCTL_PMA_TXSTATUS_L_A (1 << 0)
+
+/**** ICTL_MULTI_ANDME register ****/
+
+#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A (1 << 0)
+
+#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A_SEL (1 << 1)
+
+/**** ICTL_MULTI_LB register ****/
+
+#define SERDES_LANE_ICTL_MULTI_LB_TX2RXIOTIMEDEN_L_NT (1 << 0)
+
+#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT (1 << 1)
+
+#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT (1 << 2)
+
+#define SERDES_LANE_ICTL_MULTI_LB_PARRX2TXTIMEDEN_L_NT (1 << 3)
+
+#define SERDES_LANE_ICTL_MULTI_LB_CDRCLK2TXEN_L_NT (1 << 4)
+
+#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT_SEL (1 << 8)
+
+#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT_SEL (1 << 9)
+
+/**** ICTL_MULTI_RXBIST register ****/
+
+#define SERDES_LANE_ICTL_MULTI_RXBIST_EN_L_A (1 << 0)
+
+/**** ICTL_MULTI_TXBIST register ****/
+
+#define SERDES_LANE_ICTL_MULTI_TXBIST_EN_L_A (1 << 0)
+
+/**** ICTL_MULTI register ****/
+
+#define SERDES_LANE_ICTL_MULTI_PSTATE_L_MASK 0x00000003
+#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SHIFT 0
+
+#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SEL (1 << 2)
+
+#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_MASK 0x00000070
+#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_SHIFT 4
+
+#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATAEN_L_A (1 << 8)
+
+#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATA_L_A (1 << 9)
+
+#define SERDES_LANE_ICTL_MULTI_TXBEACON_L_A (1 << 12)
+
+#define SERDES_LANE_ICTL_MULTI_TXDETECTRXREQ_L_A (1 << 13)
+
+#define SERDES_LANE_ICTL_MULTI_RXRATE_L_MASK 0x00070000
+#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SHIFT 16
+
+#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SEL (1 << 19)
+
+#define SERDES_LANE_ICTL_MULTI_TXRATE_L_MASK 0x00700000
+#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SHIFT 20
+
+#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SEL (1 << 23)
+
+#define SERDES_LANE_ICTL_MULTI_TXAMP_L_MASK 0x07000000
+#define SERDES_LANE_ICTL_MULTI_TXAMP_L_SHIFT 24
+
+#define SERDES_LANE_ICTL_MULTI_TXAMP_EN_L (1 << 27)
+
+#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_MASK 0x70000000
+#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_SHIFT 28
+
+/**** ICTL_MULTI_RXEQ register ****/
+
+#define SERDES_LANE_ICTL_MULTI_RXEQ_EN_L (1 << 0)
+
+#define SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A (1 << 1)
+
+#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_MASK 0x00000070
+#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_SHIFT 4
+
+/**** ICTL_MULTI_RXEQ_L_high register ****/
+
+#define SERDES_LANE_ICTL_MULTI_RXEQ_L_HIGH_VAL (1 << 0)
+
+/**** ICTL_MULTI_RXEYEDIAG register ****/
+
+#define SERDES_LANE_ICTL_MULTI_RXEYEDIAG_START_L_A (1 << 0)
+
+/**** ICTL_MULTI_TXDEEMPH register ****/
+
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_MASK 0x0003FFFF
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_SHIFT 0
+
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_MASK 0x7c0
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_SHIFT 6
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_MASK 0xf000
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_SHIFT 12
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_MASK 0x7
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_SHIFT 0
+
+/**** ICTL_MULTI_TXMARGIN register ****/
+
+#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_MASK 0x00000007
+#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_SHIFT 0
+
+/**** ICTL_MULTI_TXSWING register ****/
+
+#define SERDES_LANE_ICTL_MULTI_TXSWING_L (1 << 0)
+
+/**** IDAT_MULTI register ****/
+
+#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_MASK 0x0000000F
+#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SHIFT 0
+
+#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SEL (1 << 4)
+
+/**** IPD_MULTI register ****/
+
+#define SERDES_LANE_IPD_MULTI_TX_L_B (1 << 0)
+
+#define SERDES_LANE_IPD_MULTI_RX_L_B (1 << 1)
+
+/**** OCTL_MULTI_RXBIST register ****/
+
+#define SERDES_LANE_OCTL_MULTI_RXBIST_DONE_L_A (1 << 0)
+
+#define SERDES_LANE_OCTL_MULTI_RXBIST_RXLOCKED_L_A (1 << 1)
+
+/**** OCTL_MULTI register ****/
+
+#define SERDES_LANE_OCTL_MULTI_RXCDRLOCK2DATA_L_A (1 << 0)
+
+#define SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A (1 << 1)
+
+#define SERDES_LANE_OCTL_MULTI_RXREADY_L_A (1 << 2)
+
+#define SERDES_LANE_OCTL_MULTI_RXSTATUS_L_A (1 << 3)
+
+#define SERDES_LANE_OCTL_MULTI_TXREADY_L_A (1 << 4)
+
+#define SERDES_LANE_OCTL_MULTI_TXDETECTRXSTAT_L_A (1 << 5)
+
+#define SERDES_LANE_OCTL_MULTI_TXDETECTRXACK_L_A (1 << 6)
+
+#define SERDES_LANE_OCTL_MULTI_RXSIGNALDETECT_L_A (1 << 7)
+
+/**** OCTL_MULTI_RXEYEDIAG register ****/
+
+#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_MASK 0x00003FFF
+#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_SHIFT 0
+
+#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_DONE_L_A (1 << 16)
+
+#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_ERR_L_A (1 << 17)
+
+/**** ODAT_MULTI_RXBIST register ****/
+
+#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_MASK 0x0000FFFF
+#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_SHIFT 0
+
+#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_OVERFLOW_L_A (1 << 16)
+
+/**** ODAT_MULTI_RXEQ register ****/
+
+#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_MASK 0x00003FFF
+#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_SHIFT 0
+
+/**** MULTI_RX_DVALID register ****/
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_CDR_LOCK (1 << 0)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_SIGNALDETECT (1 << 1)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_TX_READY (1 << 2)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_READY (1 << 3)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_SYNT_READY (1 << 4)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_ELECIDLE (1 << 5)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_MASK 0x00FF0000
+#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_SHIFT 16
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_00_SEL (1 << 24)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_00_VAL (1 << 25)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_01_SEL (1 << 26)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_01_VAL (1 << 27)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_10_SEL (1 << 28)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_10_VAL (1 << 29)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_11_SEL (1 << 30)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_11_VAL (1 << 31)
+
+/**** reserved register ****/
+
+#define SERDES_LANE_RESERVED_OUT_MASK 0x000000FF
+#define SERDES_LANE_RESERVED_OUT_SHIFT 0
+
+#define SERDES_LANE_RESERVED_IN_MASK 0x00FF0000
+#define SERDES_LANE_RESERVED_IN_SHIFT 16
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_serdes_REGS_H__ */
+
+/** @} end of ... group */
+
+
diff --git a/al_hal_serdes_interface.h b/al_hal_serdes_interface.h
new file mode 100644
index 000000000000..c41e6c30b69a
--- /dev/null
+++ b/al_hal_serdes_interface.h
@@ -0,0 +1,875 @@
+/*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+ * Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_serdes_api API
+ * SerDes HAL driver API
+ * @ingroup group_serdes SerDes
+ * @{
+ *
+ * @file al_hal_serdes_interface.h
+ *
+ * @brief Header file for the SerDes HAL driver
+ *
+ */
+
+#ifndef __AL_HAL_SERDES_INTERFACE_H__
+#define __AL_HAL_SERDES_INTERFACE_H__
+
+#include "al_hal_common.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+enum al_serdes_type {
+ AL_SRDS_TYPE_HSSP,
+ AL_SRDS_TYPE_25G,
+};
+
+enum al_serdes_reg_page {
+ /* Relevant to Serdes hssp and 25g */
+ AL_SRDS_REG_PAGE_0_LANE_0 = 0,
+ AL_SRDS_REG_PAGE_1_LANE_1,
+ /* Relevant to Serdes hssp only */
+ AL_SRDS_REG_PAGE_2_LANE_2,
+ AL_SRDS_REG_PAGE_3_LANE_3,
+ /* Relevant to Serdes hssp and 25g */
+ AL_SRDS_REG_PAGE_4_COMMON,
+ /* Relevant to Serdes hssp only */
+ AL_SRDS_REG_PAGE_0123_LANES_0123 = 7,
+ /* Relevant to Serdes 25g only */
+ AL_SRDS_REG_PAGE_TOP,
+};
+
+/* Relevant to Serdes hssp only */
+enum al_serdes_reg_type {
+ AL_SRDS_REG_TYPE_PMA = 0,
+ AL_SRDS_REG_TYPE_PCS,
+};
+
+enum al_serdes_lane {
+ AL_SRDS_LANE_0 = AL_SRDS_REG_PAGE_0_LANE_0,
+ AL_SRDS_LANE_1 = AL_SRDS_REG_PAGE_1_LANE_1,
+ AL_SRDS_LANE_2 = AL_SRDS_REG_PAGE_2_LANE_2,
+ AL_SRDS_LANE_3 = AL_SRDS_REG_PAGE_3_LANE_3,
+
+ AL_SRDS_NUM_LANES,
+ AL_SRDS_LANES_0123 = AL_SRDS_REG_PAGE_0123_LANES_0123,
+};
+
+/** Serdes loopback mode */
+enum al_serdes_lb_mode {
+ /** No loopback */
+ AL_SRDS_LB_MODE_OFF,
+
+ /**
+ * Transmits the untimed, partial equalized RX signal out the transmit
+ * IO pins.
+ * No clock used (untimed)
+ */
+ AL_SRDS_LB_MODE_PMA_IO_UN_TIMED_RX_TO_TX,
+
+ /**
+ * Loops back the TX serializer output into the CDR.
+ * CDR recovered bit clock used (without attenuation)
+ */
+ AL_SRDS_LB_MODE_PMA_INTERNALLY_BUFFERED_SERIAL_TX_TO_RX,
+
+ /**
+ * Loops back the TX driver IO signal to the RX IO pins
+ * CDR recovered bit clock used (only through IO)
+ */
+ AL_SRDS_LB_MODE_PMA_SERIAL_TX_IO_TO_RX_IO,
+
+ /**
+ * Parallel loopback from the PMA receive lane data ports, to the
+ * transmit lane data ports
+ * CDR recovered bit clock used
+ */
+ AL_SRDS_LB_MODE_PMA_PARALLEL_RX_TO_TX,
+
+ /** Loops received data after elastic buffer to transmit path */
+ AL_SRDS_LB_MODE_PCS_PIPE,
+
+ /** Loops TX data (to PMA) to RX path (instead of PMA data) */
+ AL_SRDS_LB_MODE_PCS_NEAR_END,
+
+ /** Loops receive data prior to interface block to transmit path */
+ AL_SRDS_LB_MODE_PCS_FAR_END,
+};
+
+enum al_serdes_clk_freq {
+ AL_SRDS_CLK_FREQ_NA,
+ AL_SRDS_CLK_FREQ_100_MHZ,
+ AL_SRDS_CLK_FREQ_125_MHZ,
+ AL_SRDS_CLK_FREQ_156_MHZ,
+};
+
+enum al_serdes_clk_src {
+ AL_SRDS_CLK_SRC_LOGIC_0,
+ AL_SRDS_CLK_SRC_REF_PINS,
+ AL_SRDS_CLK_SRC_R2L,
+ AL_SRDS_CLK_SRC_R2L_PLL,
+ AL_SRDS_CLK_SRC_L2R,
+};
+
+/** Serdes BIST pattern */
+enum al_serdes_bist_pattern {
+ AL_SRDS_BIST_PATTERN_USER,
+ AL_SRDS_BIST_PATTERN_PRBS7,
+ AL_SRDS_BIST_PATTERN_PRBS23,
+ AL_SRDS_BIST_PATTERN_PRBS31,
+ AL_SRDS_BIST_PATTERN_CLK1010,
+};
+
+/** SerDes group rate */
+enum al_serdes_rate {
+ AL_SRDS_RATE_1_8,
+ AL_SRDS_RATE_1_4,
+ AL_SRDS_RATE_1_2,
+ AL_SRDS_RATE_FULL,
+};
+
+/** SerDes power mode */
+enum al_serdes_pm {
+ AL_SRDS_PM_PD,
+ AL_SRDS_PM_P2,
+ AL_SRDS_PM_P1,
+ AL_SRDS_PM_P0S,
+ AL_SRDS_PM_P0,
+};
+
+/**
+ * Tx de-emphasis parameters
+ */
+enum al_serdes_tx_deemph_param {
+ AL_SERDES_TX_DEEMP_C_ZERO, /*< c(0) */
+ AL_SERDES_TX_DEEMP_C_PLUS, /*< c(1) */
+ AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */
+};
+
+struct al_serdes_adv_tx_params {
+ /*
+ * select the input values location.
+ * When set to true the values will be taken from the internal registers
+ * that will be override with the next following parameters.
+ * When set to false the values will be taken from external pins (the
+ * other parameters in this case is not needed)
+ */
+ al_bool override;
+ /*
+ * Transmit Amplitude control signal. Used to define the full-scale
+ * maximum swing of the driver.
+ * 000 - Not Supported
+ * 001 - 952mVdiff-pkpk
+ * 010 - 1024mVdiff-pkpk
+ * 011 - 1094mVdiff-pkpk
+ * 100 - 1163mVdiff-pkpk
+ * 101 - 1227mVdiff-pkpk
+ * 110 - 1283mVdiff-pkpk
+ * 111 - 1331mVdiff-pkpk
+ */
+ uint8_t amp;
+ /* Defines the total number of driver units allocated in the driver */
+ uint8_t total_driver_units;
+ /* Defines the total number of driver units allocated to the
+ * first post-cursor (C+1) tap. */
+ uint8_t c_plus_1;
+ /* Defines the total number of driver units allocated to the
+ * second post-cursor (C+2) tap. */
+ uint8_t c_plus_2;
+ /* Defines the total number of driver units allocated to the
+ * first pre-cursor (C-1) tap. */
+ uint8_t c_minus_1;
+ /* TX driver Slew Rate control:
+ * 00 - 31ps
+ * 01 - 33ps
+ * 10 - 68ps
+ * 11 - 170ps
+ */
+ uint8_t slew_rate;
+};
+
+struct al_serdes_adv_rx_params {
+ /*
+ * select the input values location.
+ * When set to true the values will be taken from the internal registers
+ * that will be override with the next following parameters.
+ * When set to false the values will be taken based in the equalization
+ * results (the other parameters in this case is not needed)
+ */
+ al_bool override;
+ /* RX agc high frequency dc gain:
+ * -3'b000: -3dB
+ * -3'b001: -2.5dB
+ * -3'b010: -2dB
+ * -3'b011: -1.5dB
+ * -3'b100: -1dB
+ * -3'b101: -0.5dB
+ * -3'b110: -0dB
+ * -3'b111: 0.5dB
+ */
+ uint8_t dcgain;
+ /* DFE post-shaping tap 3dB frequency
+ * -3'b000: 684MHz
+ * -3'b001: 576MHz
+ * -3'b010: 514MHz
+ * -3'b011: 435MHz
+ * -3'b100: 354MHz
+ * -3'b101: 281MHz
+ * -3'b110: 199MHz
+ * -3'b111: 125MHz
+ */
+ uint8_t dfe_3db_freq;
+ /* DFE post-shaping tap gain
+ * 0: no pulse shaping tap
+ * 1: -24mVpeak
+ * 2: -45mVpeak
+ * 3: -64mVpeak
+ * 4: -80mVpeak
+ * 5: -93mVpeak
+ * 6: -101mVpeak
+ * 7: -105mVpeak
+ */
+ uint8_t dfe_gain;
+ /* DFE first tap gain control
+ * -4'b0000: +1mVpeak
+ * -4'b0001: +10mVpeak
+ * ....
+ * -4'b0110: +55mVpeak
+ * -4'b0111: +64mVpeak
+ * -4'b1000: -1mVpeak
+ * -4'b1001: -10mVpeak
+ * ....
+ * -4'b1110: -55mVpeak
+ * -4'b1111: -64mVpeak
+ */
+ uint8_t dfe_first_tap_ctrl;
+ /* DFE second tap gain control
+ * -4'b0000: +0mVpeak
+ * -4'b0001: +9mVpeak
+ * ....
+ * -4'b0110: +46mVpeak
+ * -4'b0111: +53mVpeak
+ * -4'b1000: -0mVpeak
+ * -4'b1001: -9mVpeak
+ * ....
+ * -4'b1110: -46mVpeak
+ * -4'b1111: -53mVpeak
+ */
+ uint8_t dfe_secound_tap_ctrl;
+ /* DFE third tap gain control
+ * -4'b0000: +0mVpeak
+ * -4'b0001: +7mVpeak
+ * ....
+ * -4'b0110: +38mVpeak
+ * -4'b0111: +44mVpeak
+ * -4'b1000: -0mVpeak
+ * -4'b1001: -7mVpeak
+ * ....
+ * -4'b1110: -38mVpeak
+ * -4'b1111: -44mVpeak
+ */
+ uint8_t dfe_third_tap_ctrl;
+ /* DFE fourth tap gain control
+ * -4'b0000: +0mVpeak
+ * -4'b0001: +6mVpeak
+ * ....
+ * -4'b0110: +29mVpeak
+ * -4'b0111: +33mVpeak
+ * -4'b1000: -0mVpeak
+ * -4'b1001: -6mVpeak
+ * ....
+ * -4'b1110: -29mVpeak
+ * -4'b1111: -33mVpeak
+ */
+ uint8_t dfe_fourth_tap_ctrl;
+ /* Low frequency agc gain (att) select
+ * -3'b000: Disconnected
+ * -3'b001: -18.5dB
+ * -3'b010: -12.5dB
+ * -3'b011: -9dB
+ * -3'b100: -6.5dB
+ * -3'b101: -4.5dB
+ * -3'b110: -2.9dB
+ * -3'b111: -1.6dB
+ */
+ uint8_t low_freq_agc_gain;
+ /* Provides a RX Equalizer pre-hint, prior to beginning
+ * adaptive equalization */
+ uint8_t precal_code_sel;
+ /* High frequency agc boost control
+ * Min d0: Boost ~4dB
+ * Max d31: Boost ~20dB
+ */
+ uint8_t high_freq_agc_boost;
+};
+
+struct al_serdes_25g_adv_rx_params {
+ /* ATT (PLE Flat-Band Gain) */
+ uint8_t att;
+ /* APG (CTLE's Flat-Band Gain) */
+ uint8_t apg;
+ /* LFG (Low-Freq Gain) */
+ uint8_t lfg;
+ /* HFG (High-Freq Gain) */
+ uint8_t hfg;
+ /* MBG (MidBand-Freq-knob Gain) */
+ uint8_t mbg;
+ /* MBF (MidBand-Freq-knob Frequency position Gain) */
+ uint8_t mbf;
+ /* DFE Tap1 even#0 Value */
+ int8_t dfe_first_tap_even0_ctrl;
+ /* DFE Tap1 even#1 Value */
+ int8_t dfe_first_tap_even1_ctrl;
+ /* DFE Tap1 odd#0 Value */
+ int8_t dfe_first_tap_odd0_ctrl;
+ /* DFE Tap1 odd#1 Value */
+ int8_t dfe_first_tap_odd1_ctrl;
+ /* DFE Tap2 Value */
+ int8_t dfe_second_tap_ctrl;
+ /* DFE Tap3 Value */
+ int8_t dfe_third_tap_ctrl;
+ /* DFE Tap4 Value */
+ int8_t dfe_fourth_tap_ctrl;
+ /* DFE Tap5 Value */
+ int8_t dfe_fifth_tap_ctrl;
+};
+
+struct al_serdes_25g_tx_diag_info {
+ uint8_t regulated_supply;
+ int8_t dcd_trim;
+ uint8_t clk_delay;
+ uint8_t calp_multiplied_by_2;
+ uint8_t caln_multiplied_by_2;
+};
+
+struct al_serdes_25g_rx_diag_info {
+ int8_t los_offset;
+ int8_t agc_offset;
+ int8_t leq_gainstage_offset;
+ int8_t leq_eq1_offset;
+ int8_t leq_eq2_offset;
+ int8_t leq_eq3_offset;
+ int8_t leq_eq4_offset;
+ int8_t leq_eq5_offset;
+ int8_t summer_even_offset;
+ int8_t summer_odd_offset;
+ int8_t vscan_even_offset;
+ int8_t vscan_odd_offset;
+ int8_t data_slicer_even0_offset;
+ int8_t data_slicer_even1_offset;
+ int8_t data_slicer_odd0_offset;
+ int8_t data_slicer_odd1_offset;
+ int8_t edge_slicer_even_offset;
+ int8_t edge_slicer_odd_offset;
+ int8_t eye_slicer_even_offset;
+ int8_t eye_slicer_odd_offset;
+ uint8_t cdr_clk_i;
+ uint8_t cdr_clk_q;
+ uint8_t cdr_dll;
+ uint8_t cdr_vco_dosc;
+ uint8_t cdr_vco_fr;
+ uint16_t cdr_dlpf;
+ uint8_t ple_resistance;
+ uint8_t rx_term_mode;
+ uint8_t rx_coupling;
+ uint8_t rx_term_cal_code;
+ uint8_t rx_sheet_res_cal_code;
+};
+
+/**
+ * SRIS parameters
+ */
+struct al_serdes_sris_params {
+ /* Controls the frequency accuracy threshold (ppm) for lock detection CDR */
+ uint16_t ppm_drift_count;
+ /* Controls the frequency accuracy threshold (ppm) for lock detection in the CDR */
+ uint16_t ppm_drift_max;
+ /* Controls the frequency accuracy threshold (ppm) for lock detection in PLL */
+ uint16_t synth_ppm_drift_max;
+ /* Elastic buffer full threshold for PCIE modes: GEN1/GEN2 */
+ uint8_t full_d2r1;
+ /* Elastic buffer full threshold for PCIE modes: GEN3 */
+ uint8_t full_pcie_g3;
+ /* Elastic buffer midpoint threshold.
+ * Sets the depth of the buffer while in PCIE mode, GEN1/GEN2
+ */
+ uint8_t rd_threshold_d2r1;
+ /* Elastic buffer midpoint threshold.
+ * Sets the depth of the buffer while in PCIE mode, GEN3
+ */
+ uint8_t rd_threshold_pcie_g3;
+};
+
+/** SerDes PCIe Rate - values are important for proper behavior */
+enum al_serdes_pcie_rate {
+ AL_SRDS_PCIE_RATE_GEN1 = 0,
+ AL_SRDS_PCIE_RATE_GEN2,
+ AL_SRDS_PCIE_RATE_GEN3,
+};
+
+struct al_serdes_grp_obj {
+ void __iomem *regs_base;
+
+ /**
+ * get the type of the serdes.
+ * Must be implemented for all SerDes unit.
+ *
+ * @return the serdes type.
+ */
+ enum al_serdes_type (*type_get)(void);
+
+ /**
+ * Reads a SERDES internal register
+ *
+ * @param obj The object context
+ * @param page The SERDES register page within the group
+ * @param type The SERDES register type (PMA /PCS)
+ * @param offset The SERDES register offset (0 - 4095)
+ * @param data The read data
+ *
+ * @return 0 if no error found.
+ */
+ int (*reg_read)(struct al_serdes_grp_obj *, enum al_serdes_reg_page,
+ enum al_serdes_reg_type, uint16_t, uint8_t *);
+
+ /**
+ * Writes a SERDES internal register
+ *
+ * @param obj The object context
+ * @param page The SERDES register page within the group
+ * @param type The SERDES register type (PMA /PCS)
+ * @param offset The SERDES register offset (0 - 4095)
+ * @param data The data to write
+ *
+ * @return 0 if no error found.
+ */
+ int (*reg_write)(struct al_serdes_grp_obj *, enum al_serdes_reg_page,
+ enum al_serdes_reg_type, uint16_t, uint8_t);
+
+ /**
+ * Enable BIST required overrides
+ *
+ * @param obj The object context
+ * @param grp The SERDES group
+ * @param rate The required speed rate
+ */
+ void (*bist_overrides_enable)(struct al_serdes_grp_obj *, enum al_serdes_r