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authorNavdeep Parhar <np@FreeBSD.org>2013-03-30 02:26:20 +0000
committerNavdeep Parhar <np@FreeBSD.org>2013-03-30 02:26:20 +0000
commitd14b0ac129abd2f42171cf3a18c25f534ba2a88a (patch)
tree567c56246d7d740aad962c395d12e9b7eb5d7608
parent5f83aee5e585e899ce347b0eff42e64628f81df7 (diff)
downloadsrc-d14b0ac129abd2f42171cf3a18c25f534ba2a88a.tar.gz
src-d14b0ac129abd2f42171cf3a18c25f534ba2a88a.zip
cxgbe(4): Add support for Chelsio's Terminator 5 (aka T5) ASIC. This
includes support for the NIC and TOE features of the 40G, 10G, and 1G/100M cards based on the T5. The ASIC is mostly backward compatible with the Terminator 4 so cxgbe(4) has been updated instead of writing a brand new driver. T5 cards will show up as cxl (short for cxlgb) ports attached to the t5nex bus driver. Sponsored by: Chelsio
Notes
Notes: svn path=/head/; revision=248925
-rw-r--r--sys/dev/cxgbe/adapter.h30
-rw-r--r--sys/dev/cxgbe/common/common.h77
-rw-r--r--sys/dev/cxgbe/common/t4_hw.c338
-rw-r--r--sys/dev/cxgbe/common/t4_hw.h40
-rw-r--r--sys/dev/cxgbe/common/t4_msg.h62
-rw-r--r--sys/dev/cxgbe/common/t4_regs.h18678
-rw-r--r--sys/dev/cxgbe/osdep.h3
-rw-r--r--sys/dev/cxgbe/t4_ioctl.h1
-rw-r--r--sys/dev/cxgbe/t4_main.c1645
-rw-r--r--sys/dev/cxgbe/t4_sge.c322
-rw-r--r--sys/dev/cxgbe/tom/t4_connect.c48
-rw-r--r--sys/dev/cxgbe/tom/t4_cpl_io.c6
-rw-r--r--sys/dev/cxgbe/tom/t4_ddp.c8
-rw-r--r--sys/dev/cxgbe/tom/t4_listen.c11
-rw-r--r--sys/dev/cxgbe/tom/t4_tom.c7
-rw-r--r--sys/dev/cxgbe/tom/t4_tom.h2
-rw-r--r--sys/modules/cxgbe/Makefile3
-rw-r--r--sys/modules/cxgbe/t4_firmware/Makefile (renamed from sys/modules/cxgbe/firmware/Makefile)0
-rw-r--r--tools/tools/cxgbetool/cxgbetool.c54
-rw-r--r--tools/tools/cxgbetool/reg_defs_t5.c65039
20 files changed, 85629 insertions, 745 deletions
diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h
index eee9e1a07ff8..3563992e128e 100644
--- a/sys/dev/cxgbe/adapter.h
+++ b/sys/dev/cxgbe/adapter.h
@@ -50,9 +50,6 @@
#include "offload.h"
#include "firmware/t4fw_interface.h"
-#define T4_CFGNAME "t4fw_cfg"
-#define T4_FWNAME "t4fw"
-
MALLOC_DECLARE(M_CXGBE);
#define CXGBE_UNIMPLEMENTED(s) \
panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
@@ -144,12 +141,6 @@ enum {
TX_WR_FLITS = SGE_MAX_WR_LEN / 8
};
-#ifdef T4_PKT_TIMESTAMP
-#define RX_COPY_THRESHOLD (MINCLSIZE - 8)
-#else
-#define RX_COPY_THRESHOLD MINCLSIZE
-#endif
-
enum {
/* adapter intr_type */
INTR_INTX = (1 << 0),
@@ -327,6 +318,9 @@ enum {
EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
};
+/* Listed in order of preference. Update t4_sysctls too if you change these */
+enum {DOORBELL_UDB, DOORBELL_WRWC, DOORBELL_UDBWC, DOORBELL_KDB};
+
/*
* Egress Queue: driver is producer, T4 is consumer.
*
@@ -344,6 +338,9 @@ struct sge_eq {
struct tx_desc *desc; /* KVA of descriptor ring */
bus_addr_t ba; /* bus address of descriptor ring */
struct sge_qstat *spg; /* status page, for convenience */
+ int doorbells;
+ volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
+ u_int udb_qid; /* relative qid within the doorbell page */
uint16_t cap; /* max # of desc, for convenience */
uint16_t avail; /* available descriptors, for convenience */
uint16_t qsize; /* size (# of entries) of the queue */
@@ -496,6 +493,7 @@ struct sge {
int timer_val[SGE_NTIMERS];
int counter_val[SGE_NCOUNTERS];
int fl_starve_threshold;
+ int s_qpp;
int nrxq; /* total # of Ethernet rx queues */
int ntxq; /* total # of Ethernet tx tx queues */
@@ -541,6 +539,9 @@ struct adapter {
bus_space_handle_t bh;
bus_space_tag_t bt;
bus_size_t mmio_len;
+ int udbs_rid;
+ struct resource *udbs_res;
+ volatile uint8_t *udbs_base;
unsigned int pf;
unsigned int mbox;
@@ -570,6 +571,7 @@ struct adapter {
struct l2t_data *l2t; /* L2 table */
struct tid_info tids;
+ int doorbells;
int open_device_map;
#ifdef TCP_OFFLOAD
int offload_map;
@@ -748,13 +750,15 @@ t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
}
-static inline bool is_10G_port(const struct port_info *pi)
+static inline bool
+is_10G_port(const struct port_info *pi)
{
return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
}
-static inline int tx_resume_threshold(struct sge_eq *eq)
+static inline int
+tx_resume_threshold(struct sge_eq *eq)
{
return (eq->qsize / 4);
@@ -778,7 +782,9 @@ void end_synchronized_op(struct adapter *, int);
/* t4_sge.c */
void t4_sge_modload(void);
-int t4_sge_init(struct adapter *);
+void t4_init_sge_cpl_handlers(struct adapter *);
+void t4_tweak_chip_settings(struct adapter *);
+int t4_read_chip_settings(struct adapter *);
int t4_create_dma_tag(struct adapter *);
int t4_destroy_dma_tag(struct adapter *);
int t4_setup_adapter_queues(struct adapter *);
diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h
index ccd1195aa057..ce8a8d47de4c 100644
--- a/sys/dev/cxgbe/common/common.h
+++ b/sys/dev/cxgbe/common/common.h
@@ -42,15 +42,19 @@ enum {
MACADDR_LEN = 12, /* MAC Address length */
};
-enum { MEM_EDC0, MEM_EDC1, MEM_MC };
+enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
enum {
MEMWIN0_APERTURE = 2048,
MEMWIN0_BASE = 0x1b800,
MEMWIN1_APERTURE = 32768,
MEMWIN1_BASE = 0x28000,
- MEMWIN2_APERTURE = 65536,
- MEMWIN2_BASE = 0x30000,
+
+ MEMWIN2_APERTURE_T4 = 65536,
+ MEMWIN2_BASE_T4 = 0x30000,
+
+ MEMWIN2_APERTURE_T5 = 128 * 1024,
+ MEMWIN2_BASE_T5 = 0x60000,
};
enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
@@ -63,15 +67,20 @@ enum {
PAUSE_AUTONEG = 1 << 2
};
-#define FW_VERSION_MAJOR 1
-#define FW_VERSION_MINOR 8
-#define FW_VERSION_MICRO 4
-#define FW_VERSION_BUILD 0
+#define FW_VERSION_MAJOR_T4 1
+#define FW_VERSION_MINOR_T4 8
+#define FW_VERSION_MICRO_T4 4
+#define FW_VERSION_BUILD_T4 0
-#define FW_VERSION (V_FW_HDR_FW_VER_MAJOR(FW_VERSION_MAJOR) | \
- V_FW_HDR_FW_VER_MINOR(FW_VERSION_MINOR) | \
- V_FW_HDR_FW_VER_MICRO(FW_VERSION_MICRO) | \
- V_FW_HDR_FW_VER_BUILD(FW_VERSION_BUILD))
+#define FW_VERSION_MAJOR_T5 0
+#define FW_VERSION_MINOR_T5 5
+#define FW_VERSION_MICRO_T5 18
+#define FW_VERSION_BUILD_T5 0
+
+struct memwin {
+ uint32_t base;
+ uint32_t aperture;
+};
struct port_stats {
u64 tx_octets; /* total # of octets in good frames */
@@ -267,18 +276,20 @@ struct adapter_params {
unsigned int cim_la_size;
- /* Used as int in sysctls, do not reduce size */
- unsigned int nports; /* # of ethernet ports */
- unsigned int portvec;
- unsigned int rev; /* chip revision */
- unsigned int offload;
+ uint8_t nports; /* # of ethernet ports */
+ uint8_t portvec;
+ unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
+ unsigned int rev:4; /* chip revision */
+ unsigned int fpga:1; /* this is an FPGA */
+ unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
+ resources for TOE operation. */
+ unsigned int bypass:1; /* this is a bypass card */
unsigned int ofldq_wr_cred;
};
-enum { /* chip revisions */
- T4_REV_A = 0,
-};
+#define CHELSIO_T4 0x4
+#define CHELSIO_T5 0x5
struct trace_params {
u32 data[TRACE_LEN / 4];
@@ -316,6 +327,31 @@ static inline int is_offload(const struct adapter *adap)
return adap->params.offload;
}
+static inline int chip_id(struct adapter *adap)
+{
+ return adap->params.chipid;
+}
+
+static inline int chip_rev(struct adapter *adap)
+{
+ return adap->params.rev;
+}
+
+static inline int is_t4(struct adapter *adap)
+{
+ return adap->params.chipid == CHELSIO_T4;
+}
+
+static inline int is_t5(struct adapter *adap)
+{
+ return adap->params.chipid == CHELSIO_T5;
+}
+
+static inline int is_fpga(struct adapter *adap)
+{
+ return adap->params.fpga;
+}
+
static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
{
return adap->params.vpd.cclk / 1000;
@@ -437,7 +473,8 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
-int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
+int t4_mc_read(struct adapter *adap, int idx, u32 addr,
+ __be32 *data, u64 *parity);
int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
__be32 *data);
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index e00e779c421e..50e249063d75 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -312,6 +312,7 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
/**
* t4_mc_read - read from MC through backdoor accesses
* @adap: the adapter
+ * @idx: which MC to access
* @addr: address of first byte requested
* @data: 64 bytes of data containing the requested address
* @ecc: where to store the corresponding 64-bit ECC word
@@ -320,22 +321,40 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
* that covers the requested address @addr. If @parity is not %NULL it
* is assigned the 64-bit ECC word for the read data.
*/
-int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc)
+int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
{
int i;
+ u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
+ u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
+
+ if (is_t4(adap)) {
+ mc_bist_cmd_reg = A_MC_BIST_CMD;
+ mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
+ mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
+ mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
+ mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
+ } else {
+ mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
+ mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
+ mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
+ mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
+ idx);
+ mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
+ idx);
+ }
- if (t4_read_reg(adap, A_MC_BIST_CMD) & F_START_BIST)
+ if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
return -EBUSY;
- t4_write_reg(adap, A_MC_BIST_CMD_ADDR, addr & ~0x3fU);
- t4_write_reg(adap, A_MC_BIST_CMD_LEN, 64);
- t4_write_reg(adap, A_MC_BIST_DATA_PATTERN, 0xc);
- t4_write_reg(adap, A_MC_BIST_CMD, V_BIST_OPCODE(1) | F_START_BIST |
- V_BIST_CMD_GAP(1));
- i = t4_wait_op_done(adap, A_MC_BIST_CMD, F_START_BIST, 0, 10, 1);
+ t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
+ t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
+ t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
+ t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
+ F_START_BIST | V_BIST_CMD_GAP(1));
+ i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
if (i)
return i;
-#define MC_DATA(i) MC_BIST_STATUS_REG(A_MC_BIST_STATUS_RDATA, i)
+#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
for (i = 15; i >= 0; i--)
*data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
@@ -360,20 +379,47 @@ int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc)
int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
{
int i;
+ u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
+ u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
+
+ if (is_t4(adap)) {
+ edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
+ edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
+ edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
+ edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
+ idx);
+ edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
+ idx);
+ } else {
+/*
+ * These macro are missing in t4_regs.h file.
+ * Added temporarily for testing.
+ */
+#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
+#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
+ edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
+ edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
+ edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
+ edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
+ idx);
+ edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
+ idx);
+#undef EDC_REG_T5
+#undef EDC_STRIDE_T5
+ }
- idx *= EDC_STRIDE;
- if (t4_read_reg(adap, A_EDC_BIST_CMD + idx) & F_START_BIST)
+ if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
return -EBUSY;
- t4_write_reg(adap, A_EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU);
- t4_write_reg(adap, A_EDC_BIST_CMD_LEN + idx, 64);
- t4_write_reg(adap, A_EDC_BIST_DATA_PATTERN + idx, 0xc);
- t4_write_reg(adap, A_EDC_BIST_CMD + idx,
+ t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
+ t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
+ t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
+ t4_write_reg(adap, edc_bist_cmd_reg,
V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
- i = t4_wait_op_done(adap, A_EDC_BIST_CMD + idx, F_START_BIST, 0, 10, 1);
+ i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
if (i)
return i;
-#define EDC_DATA(i) (EDC_BIST_STATUS_REG(A_EDC_BIST_STATUS_RDATA, i) + idx)
+#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
for (i = 15; i >= 0; i--)
*data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
@@ -425,8 +471,8 @@ int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
/*
* Read the chip's memory block and bail if there's an error.
*/
- if (mtype == MEM_MC)
- ret = t4_mc_read(adap, pos, data, NULL);
+ if ((mtype == MEM_MC) || (mtype == MEM_MC1))
+ ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
else
ret = t4_edc_read(adap, mtype, pos, data, NULL);
if (ret)
@@ -464,7 +510,7 @@ struct t4_vpd_hdr {
#define EEPROM_STAT_ADDR 0x7bfc
#define VPD_BASE 0x400
#define VPD_BASE_OLD 0
-#define VPD_LEN 512
+#define VPD_LEN 1024
#define VPD_INFO_FLD_HDR_SIZE 3
/**
@@ -914,6 +960,7 @@ int t4_get_tp_version(struct adapter *adapter, u32 *vers)
int t4_check_fw_version(struct adapter *adapter)
{
int ret, major, minor, micro;
+ int exp_major, exp_minor, exp_micro;
ret = t4_get_fw_version(adapter, &adapter->params.fw_vers);
if (!ret)
@@ -925,13 +972,30 @@ int t4_check_fw_version(struct adapter *adapter)
minor = G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers);
micro = G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers);
- if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */
+ switch (chip_id(adapter)) {
+ case CHELSIO_T4:
+ exp_major = FW_VERSION_MAJOR_T4;
+ exp_minor = FW_VERSION_MINOR_T4;
+ exp_micro = FW_VERSION_MICRO_T4;
+ break;
+ case CHELSIO_T5:
+ exp_major = FW_VERSION_MAJOR_T5;
+ exp_minor = FW_VERSION_MINOR_T5;
+ exp_micro = FW_VERSION_MICRO_T5;
+ break;
+ default:
+ CH_ERR(adapter, "Unsupported chip type, %x\n",
+ chip_id(adapter));
+ return -EINVAL;
+ }
+
+ if (major != exp_major) { /* major mismatch - fail */
CH_ERR(adapter, "card FW has major version %u, driver wants "
- "%u\n", major, FW_VERSION_MAJOR);
+ "%u\n", major, exp_major);
return -EINVAL;
}
- if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO)
+ if (minor == exp_minor && micro == exp_micro)
return 0; /* perfect match */
/* Minor/micro version mismatch. Report it but often it's OK. */
@@ -1407,6 +1471,7 @@ out:
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
{
unsigned int i, v;
+ int cim_num_obq = is_t4(adap) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
for (i = 0; i < CIM_NUM_IBQ; i++) {
t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
@@ -1416,7 +1481,7 @@ void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
*size++ = G_CIMQSIZE(v) * 256; /* value is in 256-byte units */
*thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
}
- for (i = 0; i < CIM_NUM_OBQ; i++) {
+ for (i = 0; i < cim_num_obq; i++) {
t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
V_QUENUMSELECT(i));
v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
@@ -1452,8 +1517,12 @@ int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
for (i = 0; i < n; i++, addr++) {
t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
F_IBQDBGEN);
+ /*
+ * It might take 3-10ms before the IBQ debug read access is
+ * allowed. Wait for 1 Sec with a delay of 1 usec.
+ */
err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
- 2, 1);
+ 1000000, 1);
if (err)
return err;
*data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
@@ -1477,8 +1546,9 @@ int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
{
int i, err;
unsigned int addr, v, nwords;
+ int cim_num_obq = is_t4(adap) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
- if (qid > 5 || (n & 3))
+ if (qid >= cim_num_obq || (n & 3))
return -EINVAL;
t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
@@ -1933,6 +2003,47 @@ static void pcie_intr_handler(struct adapter *adapter)
{ 0 }
};
+ static struct intr_info t5_pcie_intr_info[] = {
+ { F_MSTGRPPERR, "Master Response Read Queue parity error",
+ -1, 1 },
+ { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
+ { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
+ { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
+ { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
+ { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
+ { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
+ { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
+ -1, 1 },
+ { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
+ -1, 1 },
+ { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
+ { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
+ { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
+ { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
+ { F_DREQWRPERR, "PCI DMA channel write request parity error",
+ -1, 1 },
+ { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
+ { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
+ { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
+ { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
+ { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
+ { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
+ { F_FIDPERR, "PCI FID parity error", -1, 1 },
+ { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 },
+ { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
+ { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
+ { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
+ -1, 1 },
+ { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
+ -1, 1 },
+ { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
+ { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
+ { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
+ { F_READRSPERR, "Outbound read error", -1,
+ 0 },
+ { 0 }
+ };
+
int fat;
fat = t4_handle_intr_status(adapter,
@@ -1941,7 +2052,9 @@ static void pcie_intr_handler(struct adapter *adapter)
t4_handle_intr_status(adapter,
A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
pcie_port_intr_info) +
- t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, pcie_intr_info);
+ t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
+ is_t4(adapter) ?
+ pcie_intr_info : t5_pcie_intr_info);
if (fat)
t4_fatal_err(adapter);
}
@@ -2368,9 +2481,15 @@ static void ncsi_intr_handler(struct adapter *adap)
*/
static void xgmac_intr_handler(struct adapter *adap, int port)
{
- u32 v = t4_read_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE));
+ u32 v, int_cause_reg;
- v &= F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
+ if (is_t4(adap))
+ int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
+ else
+ int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
+
+ v = t4_read_reg(adap, int_cause_reg);
+ v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR);
if (!v)
return;
@@ -2378,7 +2497,7 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", port);
if (v & F_RXFIFO_PRTY_ERR)
CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", port);
- t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE), v);
+ t4_write_reg(adap, int_cause_reg, v);
t4_fatal_err(adap);
}
@@ -3531,7 +3650,10 @@ int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, int
V_TFMINPKTSIZE(tp->min_len));
t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) |
- V_TFPORT(tp->port) | F_TFEN | V_TFINVERTMATCH(tp->invert));
+ is_t4(adap) ?
+ V_TFPORT(tp->port) | F_TFEN | V_TFINVERTMATCH(tp->invert) :
+ V_T5_TFPORT(tp->port) | F_T5_TFEN |
+ V_T5_TFINVERTMATCH(tp->invert));
return 0;
}
@@ -3555,13 +3677,18 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
- *enabled = !!(ctla & F_TFEN);
+ if (is_t4(adap)) {
+ *enabled = !!(ctla & F_TFEN);
+ tp->port = G_TFPORT(ctla);
+ } else {
+ *enabled = !!(ctla & F_T5_TFEN);
+ tp->port = G_T5_TFPORT(ctla);
+ }
tp->snap_len = G_TFCAPTUREMAX(ctlb);
tp->min_len = G_TFMINPKTSIZE(ctlb);
tp->skip_ofst = G_TFOFFSET(ctla);
tp->skip_len = G_TFLENGTH(ctla);
tp->invert = !!(ctla & F_TFINVERTMATCH);
- tp->port = G_TFPORT(ctla);
ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
@@ -3584,11 +3711,19 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
{
int i;
+ u32 data[2];
for (i = 0; i < PM_NSTATS; i++) {
t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
- cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
+ if (is_t4(adap))
+ cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
+ else {
+ t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
+ A_PM_TX_DBG_DATA, data, 2,
+ A_PM_TX_DBG_STAT_MSB);
+ cycles[i] = (((u64)data[0] << 32) | data[1]);
+ }
}
}
@@ -3603,11 +3738,19 @@ void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
{
int i;
+ u32 data[2];
for (i = 0; i < PM_NSTATS; i++) {
t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
- cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
+ if (is_t4(adap))
+ cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
+ else {
+ t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
+ A_PM_RX_DBG_DATA, data, 2,
+ A_PM_RX_DBG_STAT_MSB);
+ cycles[i] = (((u64)data[0] << 32) | data[1]);
+ }
}
}
@@ -3666,7 +3809,9 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
u32 bgmap = get_mps_bg_map(adap, idx);
#define GET_STAT(name) \
- t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))
+ t4_read_reg64(adap, \
+ (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
+ T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
p->tx_pause = GET_STAT(TX_PORT_PAUSE);
@@ -3745,13 +3890,19 @@ void t4_clr_port_stats(struct adapter *adap, int idx)
{
unsigned int i;
u32 bgmap = get_mps_bg_map(adap, idx);
+ u32 port_base_addr;
+
+ if (is_t4(adap))
+ port_base_addr = PORT_BASE(idx);
+ else
+ port_base_addr = T5_PORT_BASE(idx);
for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
- i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
- t4_write_reg(adap, PORT_REG(idx, i), 0);
+ i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
+ t4_write_reg(adap, port_base_addr + i, 0);
for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
- i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
- t4_write_reg(adap, PORT_REG(idx, i), 0);
+ i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
+ t4_write_reg(adap, port_base_addr + i, 0);
for (i = 0; i < 4; i++)
if (bgmap & (1 << i)) {
t4_write_reg(adap,
@@ -3774,7 +3925,10 @@ void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
u32 bgmap = get_mps_bg_map(adap, idx);
#define GET_STAT(name) \
- t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))
+ t4_read_reg64(adap, \
+ (is_t4(adap) ? \
+ PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
+ T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
p->octets = GET_STAT(BYTES);
@@ -3791,8 +3945,7 @@ void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
p->frames_512_1023 = GET_STAT(512B_1023B);
p->frames_1024_1518 = GET_STAT(1024B_1518B);
p->frames_1519_max = GET_STAT(1519B_MAX);
- p->drop = t4_read_reg(adap, PORT_REG(idx,
- A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES));
+ p->drop = GET_STAT(DROP_FRAMES);
p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
@@ -3818,14 +3971,26 @@ void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
const u8 *addr)
{
+ u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
+
+ if (is_t4(adap)) {
+ mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
+ mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
+ port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
+ } else {
+ mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
+ mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
+ port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
+ }
+
if (addr) {
- t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO),
+ t4_write_reg(adap, mag_id_reg_l,
(addr[2] << 24) | (addr[3] << 16) |
(addr[4] << 8) | addr[5]);
- t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI),
+ t4_write_reg(adap, mag_id_reg_h,
(addr[0] << 8) | addr[1]);
}
- t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), F_MAGICEN,
+ t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
V_MAGICEN(addr != NULL));
}
@@ -3848,16 +4013,23 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
u64 mask0, u64 mask1, unsigned int crc, bool enable)
{
int i;
+ u32 port_cfg_reg;
+
+ if (is_t4(adap))
+ port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
+ else
+ port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
if (!enable) {
- t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2),
- F_PATEN, 0);
+ t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
return 0;
}
if (map > 0xff)
return -EINVAL;
-#define EPIO_REG(name) PORT_REG(port, A_XGMAC_PORT_EPIO_##name)
+#define EPIO_REG(name) \
+ (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
+ T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
t4_write_reg(adap, EPIO_REG(DATA2), mask1);
@@ -3883,7 +4055,7 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
}
#undef EPIO_REG
- t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), 0, F_PATEN);
+ t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
return 0;
}
@@ -4763,9 +4935,12 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
int offset, ret = 0;
struct fw_vi_mac_cmd c;
unsigned int nfilters = 0;
+ unsigned int max_naddr = is_t4(adap) ?
+ NUM_MPS_CLS_SRAM_L_INSTANCES :
+ NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
unsigned int rem = naddr;
- if (naddr > NUM_MPS_CLS_SRAM_L_INSTANCES)
+ if (naddr > max_naddr)
return -EINVAL;
for (offset = 0; offset < naddr ; /**/) {
@@ -4806,10 +4981,10 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
u16 index = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx));
if (idx)
- idx[offset+i] = (index >= NUM_MPS_CLS_SRAM_L_INSTANCES
+ idx[offset+i] = (index >= max_naddr
? 0xffff
: index);
- if (index < NUM_MPS_CLS_SRAM_L_INSTANCES)
+ if (index < max_naddr)
nfilters++;
else if (hash)
*hash |= (1ULL << hash_mac_addr(addr[offset+i]));
@@ -4853,6 +5028,9 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
int ret, mode;
struct fw_vi_mac_cmd c;
struct fw_vi_mac_exact *p = c.u.exact;
+ unsigned int max_mac_addr = is_t4(adap) ?
+ NUM_MPS_CLS_SRAM_L_INSTANCES :
+ NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
if (idx < 0) /* new allocation */
idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
@@ -4867,10 +5045,10 @@ int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
V_FW_VI_MAC_CMD_IDX(idx));
memcpy(p->macaddr, addr, sizeof(p->macaddr));
- ret = t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), &c);
+ ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
if (ret == 0) {
ret = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx));
- if (ret >= NUM_MPS_CLS_SRAM_L_INSTANCES)
+ if (ret >= max_mac_addr)
ret = -ENOMEM;
}
return ret;
@@ -5188,21 +5366,6 @@ static void __devinit init_link_config(struct link_config *lc,
}
}
-static int __devinit wait_dev_ready(struct adapter *adap)
-{
- u32 whoami;
-
- whoami = t4_read_reg(adap, A_PL_WHOAMI);
-
- if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
- return 0;
-
- msleep(500);
- whoami = t4_read_reg(adap, A_PL_WHOAMI);
- return (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS
- ? 0 : -EIO);
-}
-
static int __devinit get_flash_params(struct adapter *adapter)
{
int ret;
@@ -5255,21 +5418,26 @@ static void __devinit set_pcie_completion_timeout(struct adapter *adapter,
int __devinit t4_prep_adapter(struct adapter *adapter)
{
int ret;
-
- ret = wait_dev_ready(adapter);
- if (ret < 0)
- return ret;
+ uint16_t device_id;
+ uint32_t pl_rev;
get_pci_mode(adapter, &adapter->params.pci);
- adapter->params.rev = t4_read_reg(adapter, A_PL_REV);
- /* T4A1 chip is no longer supported */
- if (adapter->params.rev == 1) {
- CH_ALERT(adapter, "T4 rev 1 chip is no longer supported\n");
- return -EINVAL;
+ pl_rev = t4_read_reg(adapter, A_PL_REV);
+ adapter->params.chipid = G_CHIPID(pl_rev);
+ adapter->params.rev = G_REV(pl_rev);
+ if (adapter->params.chipid == 0) {
+ /* T4 did not have chipid in PL_REV (T5 onwards do) */
+ adapter->params.chipid = CHELSIO_T4;
+
+ /* T4A1 chip is not supported */
+ if (adapter->params.rev == 1) {
+ CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
+ return -EINVAL;
+ }
}
adapter->params.pci.vpd_cap_addr =
- t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
+ t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
ret = get_flash_params(adapter);
if (ret < 0)
@@ -5279,12 +5447,14 @@ int __devinit t4_prep_adapter(struct adapter *adapter)
if (ret < 0)
return ret;
- if (t4_read_reg(adapter, A_PCIE_REVISION) != 0) {
+ /* Cards with real ASICs have the chipid in the PCIe device id */
+ t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
+ if (device_id >> 12 == adapter->params.chipid)
+ adapter->params.cim_la_size = CIMLA_SIZE;
+ else {
/* FPGA */
+ adapter->params.fpga = 1;
adapter->params.cim_la_size = 2 * CIMLA_SIZE;
- } else {
- /* ASIC */
- adapter->params.cim_la_size = CIMLA_SIZE;
}
init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
diff --git a/sys/dev/cxgbe/common/t4_hw.h b/sys/dev/cxgbe/common/t4_hw.h
index acc383aaf625..8b94169c0d74 100644
--- a/sys/dev/cxgbe/common/t4_hw.h
+++ b/sys/dev/cxgbe/common/t4_hw.h
@@ -33,27 +33,32 @@
#include "osdep.h"
enum {
- NCHAN = 4, /* # of HW channels */
- MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
- EEPROMSIZE = 17408, /* Serial EEPROM physical size */
- EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
- EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
- RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
- TCB_SIZE = 128, /* TCB size */
- NMTUS = 16, /* size of MTU table */
- NCCTRL_WIN = 32, /* # of congestion control windows */
- NTX_SCHED = 8, /* # of HW Tx scheduling queues */
- PM_NSTATS = 5, /* # of PM stats */
- MBOX_LEN = 64, /* mailbox size in bytes */
- TRACE_LEN = 112, /* length of trace data and mask */
- FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
- NWOL_PAT = 8, /* # of WoL patterns */
- WOL_PAT_LEN = 128, /* length of WoL patterns */
+ NCHAN = 4, /* # of HW channels */
+ MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
+ EEPROMSIZE = 17408, /* Serial EEPROM physical size */
+ EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
+ EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
+ RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
+ TCB_SIZE = 128, /* TCB size */
+ NMTUS = 16, /* size of MTU table */
+ NCCTRL_WIN = 32, /* # of congestion control windows */
+ NTX_SCHED = 8, /* # of HW Tx scheduling queues */
+ PM_NSTATS = 5, /* # of PM stats */
+ MBOX_LEN = 64, /* mailbox size in bytes */
+ TRACE_LEN = 112, /* length of trace data and mask */
+ FILTER_OPT_LEN = 36, /* filter tuple width of optional components */
+ NWOL_PAT = 8, /* # of WoL patterns */
+ WOL_PAT_LEN = 128, /* length of WoL patterns */
+ UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */
+ UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */
+ UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */
+ UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */
};
enum {
CIM_NUM_IBQ = 6, /* # of CIM IBQs */
CIM_NUM_OBQ = 6, /* # of CIM OBQs */
+ CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
@@ -80,6 +85,7 @@ enum {
SGE_CTXT_SIZE = 24, /* size of SGE context */
SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
+ SGE_MAX_IQ_SIZE = 65520,
};
struct sge_qstat { /* data written to SGE queue status entries */
@@ -221,7 +227,7 @@ enum {
* Location of firmware image in FLASH.
*/
FLASH_FW_START_SEC = 8,
- FLASH_FW_NSECS = 8,
+ FLASH_FW_NSECS = 16,
FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
diff --git a/sys/dev/cxgbe/common/t4_msg.h b/sys/dev/cxgbe/common/t4_msg.h
index 2111d30ffb5d..598807089792 100644
--- a/sys/dev/cxgbe/common/t4_msg.h
+++ b/sys/dev/cxgbe/common/t4_msg.h
@@ -104,6 +104,7 @@ enum {
CPL_RX_ISCSI_DDP = 0x49,
CPL_RX_FCOE_DIF = 0x4A,
CPL_RX_DATA_DIF = 0x4B,
+ CPL_ERR_NOTIFY = 0x4D,
CPL_RDMA_READ_REQ = 0x60,
CPL_RX_ISCSI_DIF = 0x60,
@@ -125,6 +126,7 @@ enum {
CPL_RDMA_IMM_DATA_SE = 0xAD,
CPL_TRACE_PKT = 0xB0,
+ CPL_TRACE_PKT_T5 = 0x48,
CPL_RX2TX_DATA = 0xB1,
CPL_ISCSI_DATA = 0xB2,
CPL_FCOE_DATA = 0xB3,
@@ -478,6 +480,11 @@ struct work_request_hdr {
#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
+#define S_FILT_INFO 28
+#define M_FILT_INFO 0xfffffffffULL
+#define V_FILT_INFO(x) ((x) << S_FILT_INFO)
+#define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO)
+
/* option 2 fields */
#define S_RSS_QUEUE 0
#define M_RSS_QUEUE 0x3FF
@@ -552,6 +559,10 @@ struct work_request_hdr {
#define V_SACK_EN(x) ((x) << S_SACK_EN)
#define F_SACK_EN V_SACK_EN(1U)
+#define S_T5_OPT_2_VALID 31
+#define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
+#define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
+
struct cpl_pass_open_req {
WR_HDR;
union opcode_tid ot;
@@ -679,6 +690,10 @@ struct cpl_act_open_req {
__be32 opt2;
};
+#define S_FILTER_TUPLE 24
+#define M_FILTER_TUPLE 0xFFFFFFFFFF
+#define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
+#define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
struct cpl_t5_act_open_req {
WR_HDR;
union opcode_tid ot;
@@ -1053,6 +1068,12 @@ struct cpl_tx_pkt {
#define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
#define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
+#define S_TXPKT_T5_OVLAN_IDX 12
+#define M_TXPKT_T5_OVLAN_IDX 0x7
+#define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX)
+#define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \
+ M_TXPKT_T5_OVLAN_IDX)
+
#define S_TXPKT_INTF 16
#define M_TXPKT_INTF 0xF
#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
@@ -1062,10 +1083,18 @@ struct cpl_tx_pkt {
#define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
#define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
+#define S_TXPKT_T5_FCS_DIS 21
+#define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS)
+#define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U)
+
#define S_TXPKT_INS_OVLAN 21
#define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
#define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
+#define S_TXPKT_T5_INS_OVLAN 15
+#define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN)
+#define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U)
+
#define S_TXPKT_STAT_DIS 22
#define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
#define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
@@ -1208,6 +1237,11 @@ struct cpl_tx_pkt_ufo {
#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
+#define S_LSO_T5_XFER_SIZE 0
+#define M_LSO_T5_XFER_SIZE 0xFFFFFFF
+#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
+#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
+
/* cpl_tx_pkt_lso_core.mss fields */
#define S_LSO_MSS 0
#define M_LSO_MSS 0x3FFF
@@ -1906,14 +1940,24 @@ struct cpl_l2t_write_req {
#define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
#define S_L2T_W_PORT 8
-#define M_L2T_W_PORT 0xF
+#define M_L2T_W_PORT 0x3
#define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
#define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
+#define S_L2T_W_LPBK 10
+#define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK)
+#define F_L2T_W_PKBK V_L2T_W_LPBK(1U)
+
+#define S_L2T_W_ARPMISS 11
+#define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS)
+#define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U)
+
#define S_L2T_W_NOREPLY 15
#define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
#define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
+#define CPL_L2T_VLAN_NONE 0xfff
+
struct cpl_l2t_write_rpl {
RSS_HDR
union opcode_tid ot;
@@ -2394,6 +2438,14 @@ struct ulp_mem_io {
#define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
#define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
+#define S_T5_ULP_MEMIO_IMM 23
+#define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
+#define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
+
+#define S_T5_ULP_MEMIO_ORDER 22
+#define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
+#define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
+
/* ulp_mem_io.lock_addr fields */
#define S_ULP_MEMIO_ADDR 0
#define M_ULP_MEMIO_ADDR 0x7FFFFFF
@@ -2408,6 +2460,14 @@ struct ulp_mem_io {
#define M_ULP_MEMIO_DATA_LEN 0x1F
#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
+/* ULP_TXPKT field values */
+enum {
+ ULP_TXPKT_DEST_TP = 0,
+ ULP_TXPKT_DEST_SGE,
+ ULP_TXPKT_DEST_UP,
+ ULP_TXPKT_DEST_DEVNULL,
+};
+
struct ulp_txpkt {
__be32 cmd_dest;
__be32 len;
diff --git a/sys/dev/cxgbe/common/t4_regs.h b/sys/dev/cxgbe/common/t4_regs.h
index dfe733b342b8..f205298841fd 100644
--- a/sys/dev/cxgbe/common/t4_regs.h
+++ b/sys/dev/cxgbe/common/t4_regs.h
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011 Chelsio Communications, Inc.
+ * Copyright (c) 2013 Chelsio Communications, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -60,6 +60,21 @@
#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
+#define VF_SGE_BASE 0x0
+#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
+
+#define VF_MPS_BASE 0x100
+#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
+
+#define VF_PL_BASE 0x200
+#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
+
+#define VF_MBDATA_BASE 0x240
+#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
+
+#define VF_CIM_BASE 0x300
+#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
+
#define MYPORT_BASE 0x1c000
#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
@@ -79,24 +94,6 @@
#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
-#define VF_SGE_BASE 0x0
-#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
-
-#define VF_MPS_BASE 0x100
-#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
-
-#define VF_PL_BASE 0x200
-#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
-
-#define VF_MBDATA_BASE 0x240
-#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
-
-#define VF_CIM_BASE 0x300
-#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
-
-#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
-#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
-
#define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
#define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
@@ -265,6 +262,115 @@
#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
+#define T5_MYPORT_BASE 0x2c000
+#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
+
+#define T5_PORT0_BASE 0x30000
+#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
+
+#define T5_PORT1_BASE 0x34000
+#define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))
+
+#define T5_PORT2_BASE 0x38000
+#define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))
+
+#define T5_PORT3_BASE 0x3c000
+#define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))
+
+#define T5_PORT_STRIDE 0x4000
+#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
+#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
+
+#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
+#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
+
+#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_PF_INT_INSTANCES 8
+
+#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_VF_INT_INSTANCES 128
+
+#define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
+#define NUM_PCIE_FID_VFID_INSTANCES 2048
+
+#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_PCIE_COOKIE_INSTANCES 8
+
+#define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T5_DMA_INSTANCES 4
+
+#define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T5_CMD_INSTANCES 3
+
+#define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T5_HMA_INSTANCES 1
+
+#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_PCIE_PHY_PRESET_INSTANCES 11
+
+#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
+#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
+
+#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
+#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
+
+#define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5
+
+#define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5
+
+#define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5
+
+#define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12
+
+#define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5
+
+#define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12
+
+#define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5
+
+#define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5
+
+#define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5
+
+#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
+#define NUM_MC_ADR_INSTANCES 2
+
+#define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
+#define NUM_MC_DDRPHY_DP18_INSTANCES 5
+
+#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_CE_ERR_DATA_INSTANCES 8
+
+#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_CE_COR_DATA_INSTANCES 8
+
+#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_UE_ERR_DATA_INSTANCES 8
+
+#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_UE_COR_DATA_INSTANCES 8
+
+#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_P_BIST_STATUS_INSTANCES 18
+
+#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_EDC_H_BIST_STATUS_INSTANCES 18
+
+#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
+
+#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
+#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
+
/* registers for module SGE */
#define SGE_BASE_ADDR 0x1000
@@ -285,6 +391,16 @@
#define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
#define A_SGE_VF_KDOORBELL 0x0
+
+#define S_DBTYPE 13
+#define V_DBTYPE(x) ((x) << S_DBTYPE)
+#define F_DBTYPE V_DBTYPE(1U)
+
+#define S_PIDX_T5 0
+#define M_PIDX_T5 0x1fffU
+#define V_PIDX_T5(x) ((x) << S_PIDX_T5)
+#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
+
#define A_SGE_PF_GTS 0x4
#define S_INGRESSQID 16
@@ -307,6 +423,16 @@
#define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
#define A_SGE_VF_GTS 0x4
+#define A_SGE_PF_KTIMESTAMP_LO 0x8
+#define A_SGE_VF_KTIMESTAMP_LO 0x8
+#define A_SGE_PF_KTIMESTAMP_HI 0xc
+
+#define S_TSTAMPVAL 0
+#define M_TSTAMPVAL 0xfffffffU
+#define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
+#define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
+
+#define A_SGE_VF_KTIMESTAMP_HI 0xc
#define A_SGE_CONTROL 0x1008
#define S_IGRALLCPLTOFL 31
@@ -663,6 +789,10 @@
#define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
#define F_PERR_EGR_CTXT_MIFRSP V_PERR_EGR_CTXT_MIFRSP(1U)
+#define S_PERR_PC_CHPI_RSP2 31
+#define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
+#define F_PERR_PC_CHPI_RSP2 V_PERR_PC_CHPI_RSP2(1U)
+
#define A_SGE_INT_ENABLE1 0x1028
#define A_SGE_PERR_ENABLE1 0x102c
#define A_SGE_INT_CAUSE2 0x1030
@@ -791,6 +921,22 @@
#define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
#define F_PERR_BASE_SIZE V_PERR_BASE_SIZE(1U)
+#define S_PERR_DBP_HINT_FL_FIFO 24
+#define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
+#define F_PERR_DBP_HINT_FL_FIFO V_PERR_DBP_HINT_FL_FIFO(1U)
+
+#define S_PERR_EGR_DBP_TX_COAL 23
+#define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
+#define F_PERR_EGR_DBP_TX_COAL V_PERR_EGR_DBP_TX_COAL(1U)
+
+#define S_PERR_DBP_FL_FIFO 22
+#define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
+#define F_PERR_DBP_FL_FIFO V_PERR_DBP_FL_FIFO(1U)
+
+#define S_PERR_PC_DBP2 15
+#define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
+#define F_PERR_PC_DBP2 V_PERR_PC_DBP2(1U)
+
#define A_SGE_INT_ENABLE2 0x1034
#define A_SGE_PERR_ENABLE2 0x1038
#define A_SGE_INT_CAUSE3 0x103c
@@ -995,6 +1141,11 @@
#define V_NOEDRAM(x) ((x) << S_NOEDRAM)
#define F_NOEDRAM V_NOEDRAM(1U)
+#define S_CREDITCNTPACKING 2
+#define M_CREDITCNTPACKING 0x3U
+#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
+#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
+
#define A_SGE_CONM_CTRL 0x1094
#define S_EGRTHRESHOLD 8
@@ -1015,6 +1166,11 @@
#define V_TP_ENABLE(x) ((x) << S_TP_ENABLE)
#define F_TP_ENABLE V_TP_ENABLE(1U)
+#define S_EGRTHRESHOLDPACKING 14
+#define M_EGRTHRESHOLDPACKING 0x3fU
+#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
+#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
+
#define A_SGE_TIMESTAMP_LO 0x1098
#define A_SGE_TIMESTAMP_HI 0x109c
@@ -1072,6 +1228,24 @@
#define V_LP_COUNT(x) ((x) << S_LP_COUNT)
#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
+#define S_BAR2VALID 31
+#define V_BAR2VALID(x) ((x) << S_BAR2VALID)
+#define F_BAR2VALID V_BAR2VALID(1U)
+
+#define S_BAR2FULL 30
+#define V_BAR2FULL(x) ((x) << S_BAR2FULL)
+#define F_BAR2FULL V_BAR2FULL(1U)
+
+#define S_LP_INT_THRESH_T5 18
+#define M_LP_INT_THRESH_T5 0xfffU
+#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
+#define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
+
+#define S_LP_COUNT_T5 0
+#define M_LP_COUNT_T5 0x3ffffU
+#define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
+#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
+
#define A_SGE_DOORBELL_CONTROL 0x10a8
#define S_HINTDEPTHCTL 27
@@ -1153,6 +1327,23 @@
#define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE)
#define F_THROTTLE_ENABLE V_THROTTLE_ENABLE(1U)
+#define S_BAR2THROTTLECOUNT 16
+#define M_BAR2THROTTLECOUNT 0xffU
+#define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
+#define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
+
+#define S_CLRCOALESCEDISABLE 15
+#define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
+#define F_CLRCOALESCEDISABLE V_CLRCOALESCEDISABLE(1U)
+
+#define S_OPENBAR2GATEONCE 14
+#define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
+#define F_OPENBAR2GATEONCE V_OPENBAR2GATEONCE(1U)
+
+#define S_FORCEOPENBAR2GATE 13
+#define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
+#define F_FORCEOPENBAR2GATE V_FORCEOPENBAR2GATE(1U)
+
#define A_SGE_ITP_CONTROL 0x10b4
#define S_CRITICAL_TIME 10
@@ -1307,6 +1498,90 @@
#define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
#define F_ERR_UNEXPECTED_TIMER V_ERR_UNEXPECTED_TIMER(1U)
+#define S_BAR2_EGRESS_LEN_OR_ADDR_ERR 29
+#define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
+#define F_BAR2_EGRESS_LEN_OR_ADDR_ERR V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
+
+#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1 28
+#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
+#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1 V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
+
+#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0 27
+#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
+#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0 V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
+
+#define S_ERR_WR_LEN_TOO_LARGE3 26
+#define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
+#define F_ERR_WR_LEN_TOO_LARGE3 V_ERR_WR_LEN_TOO_LARGE3(1U)
+
+#define S_ERR_WR_LEN_TOO_LARGE2 25
+#define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
+#define F_ERR_WR_LEN_TOO_LARGE2 V_ERR_WR_LEN_TOO_LARGE2(1U)
+
+#define S_ERR_WR_LEN_TOO_LARGE1 24
+#define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
+#define F_ERR_WR_LEN_TOO_LARGE1 V_ERR_WR_LEN_TOO_LARGE1(1U)
+
+#define S_ERR_WR_LEN_TOO_LARGE0 23
+#define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
+#define F_ERR_WR_LEN_TOO_LARGE0 V_ERR_WR_LEN_TOO_LARGE0(1U)
+
+#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3 22
+#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
+#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3 V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
+
+#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2 21
+#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
+#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2 V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
+
+#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1 20
+#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
+#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1 V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
+
+#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0 19
+#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
+#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0 V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
+
+#define S_COAL_WITH_HP_DISABLE_ERR 18
+#define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
+#define F_COAL_WITH_HP_DISABLE_ERR V_COAL_WITH_HP_DISABLE_ERR(1U)
+
+#define S_BAR2_EGRESS_COAL0_ERR 17
+#define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
+#define F_BAR2_EGRESS_COAL0_ERR V_BAR2_EGRESS_COAL0_ERR(1U)
+
+#define S_BAR2_EGRESS_SIZE_ERR 16
+#define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
+#define F_BAR2_EGRESS_SIZE_ERR V_BAR2_EGRESS_SIZE_ERR(1U)
+
+#define S_FLM_PC_RSP_ERR 15
+#define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
+#define F_FLM_PC_RSP_ERR V_FLM_PC_RSP_ERR(1U)
+
+#define S_DBFIFO_HP_INT_LOW 14
+#define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
+#define F_DBFIFO_HP_INT_LOW V_DBFIFO_HP_INT_LOW(1U)
+
+#define S_DBFIFO_LP_INT_LOW 13
+#define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
+#define F_DBFIFO_LP_INT_LOW V_DBFIFO_LP_INT_LOW(1U)
+
+#define S_DBFIFO_FL_INT_LOW 12
+#define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
+#define F_DBFIFO_FL_INT_LOW V_DBFIFO_FL_INT_LOW(1U)
+
+#define S_DBFIFO_FL_INT 11
+#define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
+#define F_DBFIFO_FL_INT V_DBFIFO_FL_INT(1U)
+
+#define S_ERR_RX_CPL_PACKET_SIZE1 10
+#define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
+#define F_ERR_RX_CPL_PACKET_SIZE1 V_ERR_RX_CPL_PACKET_SIZE1(1U)
+
+#define S_ERR_RX_CPL_PACKET_SIZE0 9
+#define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
+#define F_ERR_RX_CPL_PACKET_SIZE0 V_ERR_RX_CPL_PACKET_SIZE0(1U)
+
#define A_SGE_INT_ENABLE4 0x10e0
#define A_SGE_STAT_TOTAL 0x10e4
#define A_SGE_STAT_MATCH 0x10e8
@@ -1336,6 +1611,11 @@
#define V_STATSOURCE(x) ((x) << S_STATSOURCE)
#define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
+#define S_STATSOURCE_T5 9
+#define M_STATSOURCE_T5 0xfU
+#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
+#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
+
#define A_SGE_HINT_CFG 0x10f0
#define S_HINTSALLOWEDNOHDR 6
@@ -1348,6 +1628,11 @@
#define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
#define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
+#define S_UPCUTOFFTHRESHLP 12
+#define M_UPCUTOFFTHRESHLP 0x7ffU
+#define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
+#define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
+
#define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
#define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
#define A_SGE_PD_WRR_CONFIG 0x10fc
@@ -1372,6 +1657,16 @@
#define V_ERROR_QID(x) ((x) << S_ERROR_QID)
#define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
+#define S_CAUSE_REGISTER 24
+#define M_CAUSE_REGISTER 0x7U
+#define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
+#define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
+
+#define S_CAUSE_BIT 19
+#define M_CAUSE_BIT 0x1fU
+#define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
+#define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
+
#define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
#define S_MINTAG3 24
@@ -1401,6 +1696,403 @@
#define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
#define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
+#define A_SGE_INT_CAUSE5 0x110c
+
+#define S_ERR_T_RXCRC 31
+#define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
+#define F_ERR_T_RXCRC V_ERR_T_RXCRC(1U)
+
+#define S_PERR_MC_RSPDATA 30
+#define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
+#define F_PERR_MC_RSPDATA V_PERR_MC_RSPDATA(1U)
+
+#define S_PERR_PC_RSPDATA 29
+#define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
+#define F_PERR_PC_RSPDATA V_PERR_PC_RSPDATA(1U)
+
+#define S_PERR_PD_RDRSPDATA 28
+#define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
+#define F_PERR_PD_RDRSPDATA V_PERR_PD_RDRSPDATA(1U)
+
+#define S_PERR_U_RXDATA 27
+#define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
+#define F_PERR_U_RXDATA V_PERR_U_RXDATA(1U)
+
+#define S_PERR_UD_RXDATA 26
+#define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
+#define F_PERR_UD_RXDATA V_PERR_UD_RXDATA(1U)
+
+#define S_PERR_UP_DATA 25
+#define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
+#define F_PERR_UP_DATA V_PERR_UP_DATA(1U)
+
+#define S_PERR_CIM2SGE_RXDATA 24
+#define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
+#define F_PERR_CIM2SGE_RXDATA V_PERR_CIM2SGE_RXDATA(1U)
+
+#define S_PERR_HINT_DELAY_FIFO1_T5 23
+#define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
+#define F_PERR_HINT_DELAY_FIFO1_T5 V_PERR_HINT_DELAY_FIFO1_T5(1U)
+
+#define S_PERR_HINT_DELAY_FIFO0_T5 22
+#define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
+#define F_PERR_HINT_DELAY_FIFO0_T5 V_PERR_HINT_DELAY_FIFO0_T5(1U)
+
+#define S_PERR_IMSG_PD_FIFO_T5 21
+#define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
+#define F_PERR_IMSG_PD_FIFO_T5 V_PERR_IMSG_PD_FIFO_T5(1U)
+
+#define S_PERR_ULPTX_FIFO1_T5 20
+#define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
+#define F_PERR_ULPTX_FIFO1_T5 V_PERR_ULPTX_FIFO1_T5(1U)
+
+#define S_PERR_ULPTX_FIFO0_T5 19
+#define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
+#define F_PERR_ULPTX_FIFO0_T5 V_PERR_ULPTX_FIFO0_T5(1U)
+
+#define S_PERR_IDMA2IMSG_FIFO1_T5 18
+#define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
+#define F_PERR_IDMA2IMSG_FIFO1_T5 V_PERR_IDMA2IMSG_FIFO1_T5(1U)
+
+#define S_PERR_IDMA2IMSG_FIFO0_T5 17
+#define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
+#define F_PERR_IDMA2IMSG_FIFO0_T5 V_PERR_IDMA2IMSG_FIFO0_T5(1U)
+
+#define S_PERR_POINTER_DATA_FIFO0 16
+#define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
+#define F_PERR_POINTER_DATA_FIFO0 V_PERR_POINTER_DATA_FIFO0(1U)
+
+#define S_PERR_POINTER_DATA_FIFO1 15
+#define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
+#define F_PERR_POINTER_DATA_FIFO1 V_PERR_POINTER_DATA_FIFO1(1U)
+
+#define S_PERR_POINTER_HDR_FIFO0 14
+#define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
+#define F_PERR_POINTER_HDR_FIFO0 V_PERR_POINTER_HDR_FIFO0(1U)
+
+#define S_PERR_POINTER_HDR_FIFO1 13
+#define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
+#define F_PERR_POINTER_HDR_FIFO1 V_PERR_POINTER_HDR_FIFO1(1U)
+
+#define S_PERR_PAYLOAD_FIFO0 12
+#define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
+#define F_PERR_PAYLOAD_FIFO0 V_PERR_PAYLOAD_FIFO0(1U)
+
+#define S_PERR_PAYLOAD_FIFO1 11
+#define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
+#define F_PERR_PAYLOAD_FIFO1 V_PERR_PAYLOAD_FIFO1(1U)
+
+#define S_PERR_EDMA_INPUT_FIFO3 10
+#define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
+#define F_PERR_EDMA_INPUT_FIFO3 V_PERR_EDMA_INPUT_FIFO3(1U)
+
+#define S_PERR_EDMA_INPUT_FIFO2 9
+#define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
+#define F_PERR_EDMA_INPUT_FIFO2 V_PERR_EDMA_INPUT_FIFO2(1U)
+
+#define S_PERR_EDMA_INPUT_FIFO1 8
+#define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
+#define F_PERR_EDMA_INPUT_FIFO1 V_PERR_EDMA_INPUT_FIFO1(1U)
+
+#define S_PERR_EDMA_INPUT_FIFO0 7
+#define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
+#define F_PERR_EDMA_INPUT_FIFO0 V_PERR_EDMA_INPUT_FIFO0(1U)
+
+#define S_PERR_MGT_BAR2_FIFO 6
+#define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
+#define F_PERR_MGT_BAR2_FIFO V_PERR_MGT_BAR2_FIFO(1U)
+
+#define S_PERR_HEADERSPLIT_FIFO1_T5 5
+#define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
+#define F_PERR_HEADERSPLIT_FIFO1_T5 V_PERR_HEADERSPLIT_FIFO1_T5(1U)
+
+#define S_PERR_HEADERSPLIT_FIFO0_T5 4
+#define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
+#define F_PERR_HEADERSPLIT_FIFO0_T5 V_PERR_HEADERSPLIT_FIFO0_T5(1U)
+
+#define S_PERR_CIM_FIFO1 3
+#define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
+#define F_PERR_CIM_FIFO1 V_PERR_CIM_FIFO1(1U)
+
+#define S_PERR_CIM_FIFO0 2
+#define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
+#define F_PERR_CIM_FIFO0 V_PERR_CIM_FIFO0(1U)
+
+#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1 1
+#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
+#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1 V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
+
+#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0 0
+#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
+#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0 V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
+
+#define A_SGE_INT_ENABLE5 0x1110
+#define A_SGE_PERR_ENABLE5 0x1114
+#define A_SGE_DBFIFO_STATUS2 0x1118
+
+#define S_FL_INT_THRESH 24
+#define M_FL_INT_THRESH 0xfU
+#define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
+#define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
+
+#define S_FL_COUNT 14
+#define M_FL_COUNT 0x3ffU
+#define V_FL_COUNT(x) ((x) << S_FL_COUNT)
+#define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
+
+#define S_HP_INT_THRESH_T5 10
+#define M_HP_INT_THRESH_T5 0xfU
+#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
+#define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
+
+#define S_HP_COUNT_T5 0
+#define M_HP_COUNT_T5 0x3ffU
+#define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
+#define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
+
+#define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
+
+#define S_FETCHBURSTMAX0 16
+#define M_FETCHBURSTMAX0 0x3ffU
+#define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
+#define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
+
+#define S_FETCHBURSTMAX1 0
+#define M_FETCHBURSTMAX1 0x3ffU
+#define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
+#define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
+
+#define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
+
+#define S_FETCHBURSTMAX2 16
+#define M_FETCHBURSTMAX2 0x3ffU
+#define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
+#define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
+
+#define S_FETCHBURSTMAX3 0
+#define M_FETCHBURSTMAX3 0x3ffU
+#define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
+#define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
+
+#define A_SGE_CONTROL2 0x1124
+
+#define S_UPFLCUTOFFDIS 21
+#define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
+#define F_UPFLCUTOFFDIS V_UPFLCUTOFFDIS(1U)
+
+#define S_RXCPLSIZEAUTOCORRECT 20
+#define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
+#define F_RXCPLSIZEAUTOCORRECT V_RXCPLSIZEAUTOCORRECT(1U)
+
+#define S_IDMAARBROUNDROBIN 19
+#define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
+#define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U)
+
+#define S_INGPACKBOUNDARY 16
+#define M_INGPACKBOUNDARY 0x7U
+#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
+#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
+
+#define S_CGEN_EGRESS_CONTEXT 15
+#define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
+#define F_CGEN_EGRESS_CONTEXT V_CGEN_EGRESS_CONTEXT(1U)
+
+#define S_CGEN_INGRESS_CONTEXT 14
+#define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
+#define F_CGEN_INGRESS_CONTEXT V_CGEN_INGRESS_CONTEXT(1U)
+
+#define S_CGEN_IDMA 13
+#define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
+#define F_CGEN_IDMA V_CGEN_IDMA(1U)
+
+#define S_CGEN_DBP 12
+#define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
+#define F_CGEN_DBP V_CGEN_DBP(1U)
+
+#define S_CGEN_EDMA 11
+#define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
+#define F_CGEN_EDMA V_CGEN_EDMA(1U)
+
+#define S_VFIFO_ENABLE 10
+#define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
+#define F_VFIFO_ENABLE V_VFIFO_ENABLE(1U)
+
+#define S_FLM_RESCHEDULE_MODE 9
+#define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
+#define F_FLM_RESCHEDULE_MODE V_FLM_RESCHEDULE_MODE(1U)
+
+#define S_HINTDEPTHCTLFL 4
+#define M_HINTDEPTHCTLFL 0x1fU
+#define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
+#define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
+
+#define S_FORCE_ORDERING 3
+#define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
+#define F_FORCE_ORDERING V_FORCE_ORDERING(1U)
+
+#define S_TX_COALESCE_SIZE 2
+#define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
+#define F_TX_COALESCE_SIZE V_TX_COALESCE_SIZE(1U)
+
+#define S_COAL_STRICT_CIM_PRI 1
+#define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
+#define F_COAL_STRICT_CIM_PRI V_COAL_STRICT_CIM_PRI(1U)
+
+#define S_TX_COALESCE_PRI 0
+#define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
+#define F_TX_COALESCE_PRI V_TX_COALESCE_PRI(1U)
+
+#define A_SGE_DEEP_SLEEP 0x1128
+
+#define S_IDMA1_SLEEP_STATUS 11
+#define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS)
+#define F_IDMA1_SLEEP_STATUS V_IDMA1_SLEEP_STATUS(1U)
+
+#define S_IDMA0_SLEEP_STATUS 10
+#define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS)
+#define F_IDMA0_SLEEP_STATUS V_IDMA0_SLEEP_STATUS(1U)
+
+#define S_IDMA1_SLEEP_REQ 9
+#define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ)
+#define F_IDMA1_SLEEP_REQ V_IDMA1_SLEEP_REQ(1U)
+
+#define S_IDMA0_SLEEP_REQ 8
+#define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ)
+#define F_IDMA0_SLEEP_REQ V_IDMA0_SLEEP_REQ(1U)
+
+#define S_EDMA3_SLEEP_STATUS 7
+#define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS)
+#define F_EDMA3_SLEEP_STATUS V_EDMA3_SLEEP_STATUS(1U)
+
+#define S_EDMA2_SLEEP_STATUS 6
+#define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS)
+#define F_EDMA2_SLEEP_STATUS V_EDMA2_SLEEP_STATUS(1U)
+
+#define S_EDMA1_SLEEP_STATUS 5
+#define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS)
+#define F_EDMA1_SLEEP_STATUS V_EDMA1_SLEEP_STATUS(1U)
+
+#define S_EDMA0_SLEEP_STATUS 4
+#define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS)
+#define F_EDMA0_SLEEP_STATUS V_EDMA0_SLEEP_STATUS(1U)
+
+#define S_EDMA3_SLEEP_REQ 3
+#define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ)
+#define F_EDMA3_SLEEP_REQ V_EDMA3_SLEEP_REQ(1U)
+
+#define S_EDMA2_SLEEP_REQ 2
+#define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ)
+#define F_EDMA2_SLEEP_REQ V_EDMA2_SLEEP_REQ(1U)
+
+#define S_EDMA1_SLEEP_REQ 1
+#define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ)
+#define F_EDMA1_SLEEP_REQ V_EDMA1_SLEEP_REQ(1U)
+
+#define S_EDMA0_SLEEP_REQ 0
+#define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
+#define F_EDMA0_SLEEP_REQ V_EDMA0_SLEEP_REQ(1U)
+
+#define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
+
+#define S_THROTTLE_THRESHOLD_FL 16
+#define M_THROTTLE_THRESHOLD_FL 0xfU
+#define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL)
+#define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL)
+
+#define S_THROTTLE_THRESHOLD_HP 12
+#define M_THROTTLE_THRESHOLD_HP 0xfU
+#define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP)
+#define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP)
+
+#define S_THROTTLE_THRESHOLD_LP 0
+#define M_THROTTLE_THRESHOLD_LP 0xfffU
+#define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP)
+#define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP)
+
+#define A_SGE_DBP_FETCH_THRESHOLD 0x1130
+
+#define S_DBP_FETCH_THRESHOLD_FL 21
+#define M_DBP_FETCH_THRESHOLD_FL 0xfU
+#define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL)
+#define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL)
+
+#define S_DBP_FETCH_THRESHOLD_HP 17
+#define M_DBP_FETCH_THRESHOLD_HP 0xfU
+#define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP)
+#define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP)
+
+#define S_DBP_FETCH_THRESHOLD_LP 5
+#define M_DBP_FETCH_THRESHOLD_LP 0xfffU
+#define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP)
+#define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP)
+
+#define S_DBP_FETCH_THRESHOLD_MODE 4
+#define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE)
+#define F_DBP_FETCH_THRESHOLD_MODE V_DBP_FETCH_THRESHOLD_MODE(1U)
+
+#define S_DBP_FETCH_THRESHOLD_EN3 3
+#define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3)
+#define F_DBP_FETCH_THRESHOLD_EN3 V_DBP_FETCH_THRESHOLD_EN3(1U)
+
+#define S_DBP_FETCH_THRESHOLD_EN2 2
+#define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2)
+#define F_DBP_FETCH_THRESHOLD_EN2 V_DBP_FETCH_THRESHOLD_EN2(1U)
+
+#define S_DBP_FETCH_THRESHOLD_EN1 1
+#define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1)
+#define F_DBP_FETCH_THRESHOLD_EN1 V_DBP_FETCH_THRESHOLD_EN1(1U)
+
+#define S_DBP_FETCH_THRESHOLD_EN0 0
+#define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0)
+#define F_DBP_FETCH_THRESHOLD_EN0 V_DBP_FETCH_THRESHOLD_EN0(1U)
+
+#define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134
+
+#define S_DBP_FETCH_THRESHOLD_IQ1 16
+#define M_DBP_FETCH_THRESHOLD_IQ1 0xffffU
+#define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1)
+#define G_DBP_FETCH_THRESHOLD_IQ1(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1)
+
+#define S_DBP_FETCH_THRESHOLD_IQ0 0
+#define M_DBP_FETCH_THRESHOLD_IQ0 0xffffU
+#define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0)
+#define G_DBP_FETCH_THRESHOLD_IQ0(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0)
+
+#define A_SGE_DBVFIFO_BADDR 0x1138
+#define A_SGE_DBVFIFO_SIZE 0x113c
+
+#define S_DBVFIFO_SIZE 6
+#define M_DBVFIFO_SIZE 0xfffU
+#define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
+#define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
+
+#define A_SGE_DBFIFO_STATUS3 0x1140
+
+#define S_LP_PTRS_EQUAL 21
+#define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
+#define F_LP_PTRS_EQUAL V_LP_PTRS_EQUAL(1U)
+
+#define S_LP_SNAPHOT 20
+#define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
+#define F_LP_SNAPHOT V_LP_SNAPHOT(1U)
+
+#define S_FL_INT_THRESH_LOW 16
+#define M_FL_INT_THRESH_LOW 0xfU
+#define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
+#define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
+
+#define S_HP_INT_THRESH_LOW 12
+#define M_HP_INT_THRESH_LOW 0xfU
+#define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
+#define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
+
+#define S_LP_INT_THRESH_LOW 0
+#define M_LP_INT_THRESH_LOW 0xfffU
+#define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
+#define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
+
+#define A_SGE_CHANGESET 0x1144
+#define A_SGE_PC_RSP_ERROR 0x1148
#define A_SGE_PC0_REQ_BIST_CMD 0x1180
#define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
#define A_SGE_PC1_REQ_BIST_CMD 0x1190
@@ -1446,6 +2138,891 @@
#define A_SGE_CTXT_MASK5 0x1234
#define A_SGE_CTXT_MASK6 0x1238
#define A_SGE_CTXT_MASK7 0x123c
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
+
+#define S_CIM_WM 24
+#define M_CIM_WM 0x3U
+#define V_CIM_WM(x) ((x) << S_CIM_WM)
+#define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
+
+#define S_DEBUG_UP_SOP_CNT 20
+#define M_DEBUG_UP_SOP_CNT 0xfU
+#define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
+#define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
+
+#define S_DEBUG_UP_EOP_CNT 16
+#define M_DEBUG_UP_EOP_CNT 0xfU
+#define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
+#define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
+
+#define S_DEBUG_CIM_SOP1_CNT 12
+#define M_DEBUG_CIM_SOP1_CNT 0xfU
+#define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
+#define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
+
+#define S_DEBUG_CIM_EOP1_CNT 8
+#define M_DEBUG_CIM_EOP1_CNT 0xfU
+#define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
+#define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
+
+#define S_DEBUG_CIM_SOP0_CNT 4
+#define M_DEBUG_CIM_SOP0_CNT 0xfU
+#define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
+#define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
+
+#define S_DEBUG_CIM_EOP0_CNT 0
+#define M_DEBUG_CIM_EOP0_CNT 0xfU
+#define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
+#define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
+
+#define S_DEBUG_T_RX_SOP1_CNT 28
+#define M_DEBUG_T_RX_SOP1_CNT 0xfU
+#define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
+#define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
+
+#define S_DEBUG_T_RX_EOP1_CNT 24
+#define M_DEBUG_T_RX_EOP1_CNT 0xfU
+#define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
+#define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
+
+#define S_DEBUG_T_RX_SOP0_CNT 20
+#define M_DEBUG_T_RX_SOP0_CNT 0xfU
+#define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
+#define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
+
+#define S_DEBUG_T_RX_EOP0_CNT 16
+#define M_DEBUG_T_RX_EOP0_CNT 0xfU
+#define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
+#define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
+
+#define S_DEBUG_U_RX_SOP1_CNT 12
+#define M_DEBUG_U_RX_SOP1_CNT 0xfU
+#define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
+#define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
+
+#define S_DEBUG_U_RX_EOP1_CNT 8
+#define M_DEBUG_U_RX_EOP1_CNT 0xfU
+#define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
+#define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
+
+#define S_DEBUG_U_RX_SOP0_CNT 4
+#define M_DEBUG_U_RX_SOP0_CNT 0xfU
+#define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
+#define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
+
+#define S_DEBUG_U_RX_EOP0_CNT 0
+#define M_DEBUG_U_RX_EOP0_CNT 0xfU
+#define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
+#define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
+
+#define S_DEBUG_UD_RX_SOP3_CNT 28
+#define M_DEBUG_UD_RX_SOP3_CNT 0xfU
+#define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
+#define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
+
+#define S_DEBUG_UD_RX_EOP3_CNT 24
+#define M_DEBUG_UD_RX_EOP3_CNT 0xfU
+#define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
+#define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
+
+#define S_DEBUG_UD_RX_SOP2_CNT 20
+#define M_DEBUG_UD_RX_SOP2_CNT 0xfU
+#define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
+#define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
+
+#define S_DEBUG_UD_RX_EOP2_CNT 16
+#define M_DEBUG_UD_RX_EOP2_CNT 0xfU
+#define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
+#define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
+
+#define S_DEBUG_UD_RX_SOP1_CNT 12
+#define M_DEBUG_UD_RX_SOP1_CNT 0xfU
+#define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
+#define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
+
+#define S_DEBUG_UD_RX_EOP1_CNT 8
+#define M_DEBUG_UD_RX_EOP1_CNT 0xfU
+#define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
+#define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
+
+#define S_DEBUG_UD_RX_SOP0_CNT 4
+#define M_DEBUG_UD_RX_SOP0_CNT 0xfU
+#define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
+#define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
+
+#define S_DEBUG_UD_RX_EOP0_CNT 0
+#define M_DEBUG_UD_RX_EOP0_CNT 0xfU
+#define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
+#define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
+
+#define S_DEBUG_U_TX_SOP3_CNT 28
+#define M_DEBUG_U_TX_SOP3_CNT 0xfU
+#define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
+#define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
+
+#define S_DEBUG_U_TX_EOP3_CNT 24
+#define M_DEBUG_U_TX_EOP3_CNT 0xfU
+#define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
+#define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
+
+#define S_DEBUG_U_TX_SOP2_CNT 20
+#define M_DEBUG_U_TX_SOP2_CNT 0xfU
+#define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
+#define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
+
+#define S_DEBUG_U_TX_EOP2_CNT 16
+#define M_DEBUG_U_TX_EOP2_CNT 0xfU
+#define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
+#define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
+
+#define S_DEBUG_U_TX_SOP1_CNT 12
+#define M_DEBUG_U_TX_SOP1_CNT 0xfU
+#define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
+#define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
+
+#define S_DEBUG_U_TX_EOP1_CNT 8
+#define M_DEBUG_U_TX_EOP1_CNT 0xfU
+#define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
+#define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
+
+#define S_DEBUG_U_TX_SOP0_CNT 4
+#define M_DEBUG_U_TX_SOP0_CNT 0xfU
+#define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
+#define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
+
+#define S_DEBUG_U_TX_EOP0_CNT 0
+#define M_DEBUG_U_TX_EOP0_CNT 0xfU
+#define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
+#define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
+
+#define S_DEBUG_PC_RSP_SOP1_CNT 28
+#define M_DEBUG_PC_RSP_SOP1_CNT 0xfU
+#define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
+#define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
+
+#define S_DEBUG_PC_RSP_EOP1_CNT 24
+#define M_DEBUG_PC_RSP_EOP1_CNT 0xfU
+#define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
+#define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
+
+#define S_DEBUG_PC_RSP_SOP0_CNT 20
+#define M_DEBUG_PC_RSP_SOP0_CNT 0xfU
+#define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
+#define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
+
+#define S_DEBUG_PC_RSP_EOP0_CNT 16
+#define M_DEBUG_PC_RSP_EOP0_CNT 0xfU
+#define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
+#define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
+
+#define S_DEBUG_PC_REQ_SOP1_CNT 12
+#define M_DEBUG_PC_REQ_SOP1_CNT 0xfU
+#define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
+#define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
+
+#define S_DEBUG_PC_REQ_EOP1_CNT 8
+#define M_DEBUG_PC_REQ_EOP1_CNT 0xfU
+#define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
+#define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
+
+#define S_DEBUG_PC_REQ_SOP0_CNT 4
+#define M_DEBUG_PC_REQ_SOP0_CNT 0xfU
+#define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
+#define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
+
+#define S_DEBUG_PC_REQ_EOP0_CNT 0
+#define M_DEBUG_PC_REQ_EOP0_CNT 0xfU
+#define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
+#define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
+
+#define S_DEBUG_PD_RDREQ_SOP3_CNT 28
+#define M_DEBUG_PD_RDREQ_SOP3_CNT 0xfU
+#define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
+#define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
+
+#define S_DEBUG_PD_RDREQ_EOP3_CNT 24
+#define M_DEBUG_PD_RDREQ_EOP3_CNT 0xfU
+#define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
+#define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
+
+#define S_DEBUG_PD_RDREQ_SOP2_CNT 20
+#define M_DEBUG_PD_RDREQ_SOP2_CNT 0xfU
+#define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
+#define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
+
+#define S_DEBUG_PD_RDREQ_EOP2_CNT 16
+#define M_DEBUG_PD_RDREQ_EOP2_CNT 0xfU
+#define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
+#define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
+
+#define S_DEBUG_PD_RDREQ_SOP1_CNT 12
+#define M_DEBUG_PD_RDREQ_SOP1_CNT 0xfU
+#define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
+#define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
+
+#define S_DEBUG_PD_RDREQ_EOP1_CNT 8
+#define M_DEBUG_PD_RDREQ_EOP1_CNT 0xfU
+#define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
+#define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
+
+#define S_DEBUG_PD_RDREQ_SOP0_CNT 4
+#define M_DEBUG_PD_RDREQ_SOP0_CNT 0xfU
+#define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
+#define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
+
+#define S_DEBUG_PD_RDREQ_EOP0_CNT 0
+#define M_DEBUG_PD_RDREQ_EOP0_CNT 0xfU
+#define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
+#define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
+
+#define S_DEBUG_PD_RDRSP_SOP3_CNT 28
+#define M_DEBUG_PD_RDRSP_SOP3_CNT 0xfU
+#define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
+#define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
+
+#define S_DEBUG_PD_RDRSP_EOP3_CNT 24
+#define M_DEBUG_PD_RDRSP_EOP3_CNT 0xfU
+#define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
+#define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
+
+#define S_DEBUG_PD_RDRSP_SOP2_CNT 20
+#define M_DEBUG_PD_RDRSP_SOP2_CNT 0xfU
+#define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
+#define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
+
+#define S_DEBUG_PD_RDRSP_EOP2_CNT 16
+#define M_DEBUG_PD_RDRSP_EOP2_CNT 0xfU
+#define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
+#define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
+
+#define S_DEBUG_PD_RDRSP_SOP1_CNT 12
+#define M_DEBUG_PD_RDRSP_SOP1_CNT 0xfU
+#define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
+#define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
+
+#define S_DEBUG_PD_RDRSP_EOP1_CNT 8
+#define M_DEBUG_PD_RDRSP_EOP1_CNT 0xfU
+#define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
+#define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
+
+#define S_DEBUG_PD_RDRSP_SOP0_CNT 4
+#define M_DEBUG_PD_RDRSP_SOP0_CNT 0xfU
+#define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
+#define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
+
+#define S_DEBUG_PD_RDRSP_EOP0_CNT 0
+#define M_DEBUG_PD_RDRSP_EOP0_CNT 0xfU
+#define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
+#define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
+
+#define S_DEBUG_PD_WRREQ_SOP3_CNT 28
+#define M_DEBUG_PD_WRREQ_SOP3_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
+#define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
+
+#define S_DEBUG_PD_WRREQ_EOP3_CNT 24
+#define M_DEBUG_PD_WRREQ_EOP3_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
+#define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
+
+#define S_DEBUG_PD_WRREQ_SOP2_CNT 20
+#define M_DEBUG_PD_WRREQ_SOP2_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
+#define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
+
+#define S_DEBUG_PD_WRREQ_EOP2_CNT 16
+#define M_DEBUG_PD_WRREQ_EOP2_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
+#define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
+
+#define S_DEBUG_PD_WRREQ_SOP1_CNT 12
+#define M_DEBUG_PD_WRREQ_SOP1_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
+#define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
+
+#define S_DEBUG_PD_WRREQ_EOP1_CNT 8
+#define M_DEBUG_PD_WRREQ_EOP1_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
+#define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
+
+#define S_DEBUG_PD_WRREQ_SOP0_CNT 4
+#define M_DEBUG_PD_WRREQ_SOP0_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
+#define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
+
+#define S_DEBUG_PD_WRREQ_EOP0_CNT 0
+#define M_DEBUG_PD_WRREQ_EOP0_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
+#define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
+
+#define S_GLOBALENABLE_OFF 29
+#define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
+#define F_GLOBALENABLE_OFF V_GLOBALENABLE_OFF(1U)
+
+#define S_DEBUG_CIM2SGE_RXAFULL_D 27
+#define M_DEBUG_CIM2SGE_RXAFULL_D 0x3U
+#define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
+#define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
+
+#define S_DEBUG_CPLSW_CIM_TXAFULL_D 25
+#define M_DEBUG_CPLSW_CIM_TXAFULL_D 0x3U
+#define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
+#define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
+
+#define S_DEBUG_UP_FULL 24
+#define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
+#define F_DEBUG_UP_FULL V_DEBUG_UP_FULL(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_PC 23
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_PC V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO 22
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG 21
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB 20
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM 19
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
+
+#define S_DEBUG_M_REQVLD 18
+#define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
+#define F_DEBUG_M_REQVLD V_DEBUG_M_REQVLD(1U)
+
+#define S_DEBUG_M_REQRDY 17
+#define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
+#define F_DEBUG_M_REQRDY V_DEBUG_M_REQRDY(1U)
+
+#define S_DEBUG_M_RSPVLD 16
+#define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
+#define F_DEBUG_M_RSPVLD V_DEBUG_M_RSPVLD(1U)
+
+#define S_DEBUG_PD_WRREQ_INT3_CNT 12
+#define M_DEBUG_PD_WRREQ_INT3_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
+#define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
+
+#define S_DEBUG_PD_WRREQ_INT2_CNT 8
+#define M_DEBUG_PD_WRREQ_INT2_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
+#define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
+
+#define S_DEBUG_PD_WRREQ_INT1_CNT 4
+#define M_DEBUG_PD_WRREQ_INT1_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
+#define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
+
+#define S_DEBUG_PD_WRREQ_INT0_CNT 0
+#define M_DEBUG_PD_WRREQ_INT0_CNT 0xfU
+#define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
+#define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
+
+#define S_DEBUG_CPLSW_TP_RX_SOP1_CNT 28
+#define M_DEBUG_CPLSW_TP_RX_SOP1_CNT 0xfU
+#define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
+#define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
+
+#define S_DEBUG_CPLSW_TP_RX_EOP1_CNT 24
+#define M_DEBUG_CPLSW_TP_RX_EOP1_CNT 0xfU
+#define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
+#define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
+
+#define S_DEBUG_CPLSW_TP_RX_SOP0_CNT 20
+#define M_DEBUG_CPLSW_TP_RX_SOP0_CNT 0xfU
+#define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
+#define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
+
+#define S_DEBUG_CPLSW_TP_RX_EOP0_CNT 16
+#define M_DEBUG_CPLSW_TP_RX_EOP0_CNT 0xfU
+#define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
+#define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
+
+#define S_DEBUG_CPLSW_CIM_SOP1_CNT 12
+#define M_DEBUG_CPLSW_CIM_SOP1_CNT 0xfU
+#define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
+#define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
+
+#define S_DEBUG_CPLSW_CIM_EOP1_CNT 8
+#define M_DEBUG_CPLSW_CIM_EOP1_CNT 0xfU
+#define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
+#define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
+
+#define S_DEBUG_CPLSW_CIM_SOP0_CNT 4
+#define M_DEBUG_CPLSW_CIM_SOP0_CNT 0xfU
+#define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
+#define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
+
+#define S_DEBUG_CPLSW_CIM_EOP0_CNT 0
+#define M_DEBUG_CPLSW_CIM_EOP0_CNT 0xfU
+#define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
+#define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
+
+#define S_DEBUG_T_RXAFULL_D 30
+#define M_DEBUG_T_RXAFULL_D 0x3U
+#define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
+#define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
+
+#define S_DEBUG_PD_RDRSPAFULL_D 26
+#define M_DEBUG_PD_RDRSPAFULL_D 0xfU
+#define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
+#define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
+
+#define S_DEBUG_PD_RDREQAFULL_D 22
+#define M_DEBUG_PD_RDREQAFULL_D 0xfU
+#define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
+#define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
+
+#define S_DEBUG_PD_WRREQAFULL_D 18
+#define M_DEBUG_PD_WRREQAFULL_D 0xfU
+#define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
+#define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
+
+#define S_DEBUG_PC_RSPAFULL_D 15
+#define M_DEBUG_PC_RSPAFULL_D 0x7U
+#define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
+#define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
+
+#define S_DEBUG_PC_REQAFULL_D 12
+#define M_DEBUG_PC_REQAFULL_D 0x7U
+#define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
+#define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
+
+#define S_DEBUG_U_TXAFULL_D 8
+#define M_DEBUG_U_TXAFULL_D 0xfU
+#define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
+#define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
+
+#define S_DEBUG_UD_RXAFULL_D 4
+#define M_DEBUG_UD_RXAFULL_D 0xfU
+#define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
+#define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
+
+#define S_DEBUG_U_RXAFULL_D 2
+#define M_DEBUG_U_RXAFULL_D 0x3U
+#define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
+#define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
+
+#define S_DEBUG_CIM_AFULL_D 0
+#define M_DEBUG_CIM_AFULL_D 0x3U
+#define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
+#define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
+
+#define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE 24
+#define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
+#define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE 23
+#define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
+#define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE 22
+#define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
+#define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE 21
+#define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
+#define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
+
+#define S_DEBUG_ST_FLM_IDMA1_CACHE 19
+#define M_DEBUG_ST_FLM_IDMA1_CACHE 0x3U
+#define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
+#define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
+
+#define S_DEBUG_ST_FLM_IDMA1_CTXT 16
+#define M_DEBUG_ST_FLM_IDMA1_CTXT 0x7U
+#define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
+#define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
+
+#define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE 8
+#define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
+#define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE 7
+#define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
+#define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE 6
+#define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
+#define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE 5
+#define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
+#define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
+
+#define S_DEBUG_ST_FLM_IDMA0_CACHE 3
+#define M_DEBUG_ST_FLM_IDMA0_CACHE 0x3U
+#define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
+#define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
+
+#define S_DEBUG_ST_FLM_IDMA0_CTXT 0
+#define M_DEBUG_ST_FLM_IDMA0_CTXT 0x7U
+#define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
+#define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
+
+#define S_DEBUG_CPLSW_SOP1_CNT 28
+#define M_DEBUG_CPLSW_SOP1_CNT 0xfU
+#define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
+#define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
+
+#define S_DEBUG_CPLSW_EOP1_CNT 24
+#define M_DEBUG_CPLSW_EOP1_CNT 0xfU
+#define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
+#define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
+
+#define S_DEBUG_CPLSW_SOP0_CNT 20
+#define M_DEBUG_CPLSW_SOP0_CNT 0xfU
+#define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
+#define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
+
+#define S_DEBUG_CPLSW_EOP0_CNT 16
+#define M_DEBUG_CPLSW_EOP0_CNT 0xfU
+#define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
+#define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
+
+#define S_DEBUG_PC_RSP_SOP2_CNT 12
+#define M_DEBUG_PC_RSP_SOP2_CNT 0xfU
+#define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
+#define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
+
+#define S_DEBUG_PC_RSP_EOP2_CNT 8
+#define M_DEBUG_PC_RSP_EOP2_CNT 0xfU
+#define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
+#define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
+
+#define S_DEBUG_PC_REQ_SOP2_CNT 4
+#define M_DEBUG_PC_REQ_SOP2_CNT 0xfU
+#define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
+#define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
+
+#define S_DEBUG_PC_REQ_EOP2_CNT 0
+#define M_DEBUG_PC_REQ_EOP2_CNT 0xfU
+#define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
+#define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
+#define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
+
+#define S_DEBUG_ST_IDMA1_FLM_REQ 29
+#define M_DEBUG_ST_IDMA1_FLM_REQ 0x7U
+#define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
+#define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
+
+#define S_DEBUG_ST_IDMA0_FLM_REQ 26
+#define M_DEBUG_ST_IDMA0_FLM_REQ 0x7U
+#define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
+#define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
+
+#define S_DEBUG_ST_IMSG_CTXT 23
+#define M_DEBUG_ST_IMSG_CTXT 0x7U
+#define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
+#define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
+
+#define S_DEBUG_ST_IMSG 18
+#define M_DEBUG_ST_IMSG 0x1fU
+#define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
+#define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
+
+#define S_DEBUG_ST_IDMA1_IALN 16
+#define M_DEBUG_ST_IDMA1_IALN 0x3U
+#define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
+#define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
+
+#define S_DEBUG_ST_IDMA1_IDMA_SM 9
+#define M_DEBUG_ST_IDMA1_IDMA_SM 0x3fU
+#define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
+#define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
+
+#define S_DEBUG_ST_IDMA0_IALN 7
+#define M_DEBUG_ST_IDMA0_IALN 0x3U
+#define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
+#define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
+
+#define S_DEBUG_ST_IDMA0_IDMA_SM 0
+#define M_DEBUG_ST_IDMA0_IDMA_SM 0x3fU
+#define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
+#define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
+
+#define S_DEBUG_ITP_EMPTY 12
+#define M_DEBUG_ITP_EMPTY 0x3fU
+#define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
+#define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
+
+#define S_DEBUG_ITP_EXPIRED 6
+#define M_DEBUG_ITP_EXPIRED 0x3fU
+#define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
+#define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
+
+#define S_DEBUG_ITP_PAUSE 5
+#define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
+#define F_DEBUG_ITP_PAUSE V_DEBUG_ITP_PAUSE(1U)
+
+#define S_DEBUG_ITP_DEL_DONE 4
+#define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
+#define F_DEBUG_ITP_DEL_DONE V_DEBUG_ITP_DEL_DONE(1U)
+
+#define S_DEBUG_ITP_ADD_DONE 3
+#define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
+#define F_DEBUG_ITP_ADD_DONE V_DEBUG_ITP_ADD_DONE(1U)
+
+#define S_DEBUG_ITP_EVR_STATE 0
+#define M_DEBUG_ITP_EVR_STATE 0x7U
+#define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
+#define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
+
+#define S_DEBUG_ST_DBP_THREAD2_CIMFL 25
+#define M_DEBUG_ST_DBP_THREAD2_CIMFL 0x1fU
+#define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
+#define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
+
+#define S_DEBUG_ST_DBP_THREAD2_MAIN 20
+#define M_DEBUG_ST_DBP_THREAD2_MAIN 0x1fU
+#define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
+#define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
+
+#define S_DEBUG_ST_DBP_THREAD1_CIMFL 15
+#define M_DEBUG_ST_DBP_THREAD1_CIMFL 0x1fU
+#define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
+#define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
+
+#define S_DEBUG_ST_DBP_THREAD1_MAIN 10
+#define M_DEBUG_ST_DBP_THREAD1_MAIN 0x1fU
+#define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
+#define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
+
+#define S_DEBUG_ST_DBP_THREAD0_CIMFL 5
+#define M_DEBUG_ST_DBP_THREAD0_CIMFL 0x1fU
+#define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
+#define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
+
+#define S_DEBUG_ST_DBP_THREAD0_MAIN 0
+#define M_DEBUG_ST_DBP_THREAD0_MAIN 0x1fU
+#define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
+#define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
+
+#define S_DEBUG_ST_DBP_UPCP_MAIN 14
+#define M_DEBUG_ST_DBP_UPCP_MAIN 0x1fU
+#define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
+#define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
+
+#define S_DEBUG_ST_DBP_DBFIFO_MAIN 13
+#define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
+#define F_DEBUG_ST_DBP_DBFIFO_MAIN V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
+
+#define S_DEBUG_ST_DBP_CTXT 10
+#define M_DEBUG_ST_DBP_CTXT 0x7U
+#define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
+#define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
+
+#define S_DEBUG_ST_DBP_THREAD3_CIMFL 5
+#define M_DEBUG_ST_DBP_THREAD3_CIMFL 0x1fU
+#define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
+#define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
+
+#define S_DEBUG_ST_DBP_THREAD3_MAIN 0
+#define M_DEBUG_ST_DBP_THREAD3_MAIN 0x1fU
+#define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
+#define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
+
+#define S_DEBUG_ST_EDMA3_ALIGN_SUB 29
+#define M_DEBUG_ST_EDMA3_ALIGN_SUB 0x7U
+#define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
+#define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
+
+#define S_DEBUG_ST_EDMA3_ALIGN 27
+#define M_DEBUG_ST_EDMA3_ALIGN 0x3U
+#define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
+#define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
+
+#define S_DEBUG_ST_EDMA3_REQ 24
+#define M_DEBUG_ST_EDMA3_REQ 0x7U
+#define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
+#define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
+
+#define S_DEBUG_ST_EDMA2_ALIGN_SUB 21
+#define M_DEBUG_ST_EDMA2_ALIGN_SUB 0x7U
+#define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
+#define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
+
+#define S_DEBUG_ST_EDMA2_ALIGN 19
+#define M_DEBUG_ST_EDMA2_ALIGN 0x3U
+#define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
+#define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
+
+#define S_DEBUG_ST_EDMA2_REQ 16
+#define M_DEBUG_ST_EDMA2_REQ 0x7U
+#define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
+#define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
+
+#define S_DEBUG_ST_EDMA1_ALIGN_SUB 13
+#define M_DEBUG_ST_EDMA1_ALIGN_SUB 0x7U
+#define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
+#define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
+
+#define S_DEBUG_ST_EDMA1_ALIGN 11
+#define M_DEBUG_ST_EDMA1_ALIGN 0x3U
+#define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
+#define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
+
+#define S_DEBUG_ST_EDMA1_REQ 8
+#define M_DEBUG_ST_EDMA1_REQ 0x7U
+#define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
+#define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
+
+#define S_DEBUG_ST_EDMA0_ALIGN_SUB 5
+#define M_DEBUG_ST_EDMA0_ALIGN_SUB 0x7U
+#define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
+#define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
+
+#define S_DEBUG_ST_EDMA0_ALIGN 3
+#define M_DEBUG_ST_EDMA0_ALIGN 0x3U
+#define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
+#define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
+
+#define S_DEBUG_ST_EDMA0_REQ 0
+#define M_DEBUG_ST_EDMA0_REQ 0x7U
+#define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
+#define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
+
+#define S_DEBUG_ST_FLM_DBPTR 30
+#define M_DEBUG_ST_FLM_DBPTR 0x3U
+#define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
+#define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
+
+#define S_DEBUG_FLM_CACHE_LOCKED_COUNT 23
+#define M_DEBUG_FLM_CACHE_LOCKED_COUNT 0x7fU
+#define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
+#define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
+
+#define S_DEBUG_FLM_CACHE_AGENT 20
+#define M_DEBUG_FLM_CACHE_AGENT 0x7U
+#define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
+#define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
+
+#define S_DEBUG_ST_FLM_CACHE 16
+#define M_DEBUG_ST_FLM_CACHE 0xfU
+#define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
+#define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
+
+#define S_DEBUG_FLM_DBPTR_CIDX_STALL 12
+#define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
+#define F_DEBUG_FLM_DBPTR_CIDX_STALL V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
+
+#define S_DEBUG_FLM_DBPTR_QID 0
+#define M_DEBUG_FLM_DBPTR_QID 0xfffU
+#define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
+#define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
+
+#define S_DEBUG_DBP_THREAD0_QID 0
+#define M_DEBUG_DBP_THREAD0_QID 0x1ffffU
+#define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
+#define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
+
+#define S_DEBUG_DBP_THREAD1_QID 0
+#define M_DEBUG_DBP_THREAD1_QID 0x1ffffU
+#define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
+#define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
+
+#define S_DEBUG_DBP_THREAD2_QID 0
+#define M_DEBUG_DBP_THREAD2_QID 0x1ffffU
+#define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
+#define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
+
+#define S_DEBUG_DBP_THREAD3_QID 0
+#define M_DEBUG_DBP_THREAD3_QID 0x1ffffU
+#define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
+#define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
+
+#define S_DEBUG_IMSG_CPL 16
+#define M_DEBUG_IMSG_CPL 0xffU
+#define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
+#define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)
+
+#define S_DEBUG_IMSG_QID 0
+#define M_DEBUG_IMSG_QID 0xffffU
+#define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
+#define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
+
+#define S_DEBUG_IDMA1_QID 16
+#define M_DEBUG_IDMA1_QID 0xffffU
+#define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
+#define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)
+
+#define S_DEBUG_IDMA0_QID 0
+#define M_DEBUG_IDMA0_QID 0xffffU
+#define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
+#define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
+
+#define S_DEBUG_IDMA1_FLM_REQ_QID 16
+#define M_DEBUG_IDMA1_FLM_REQ_QID 0xffffU
+#define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
+#define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)
+
+#define S_DEBUG_IDMA0_FLM_REQ_QID 0
+#define M_DEBUG_IDMA0_FLM_REQ_QID 0xffffU
+#define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
+#define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
+#define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
+#define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
#define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
#define S_EGRESS_LOG2SIZE 27
@@ -1468,6 +3045,21 @@
#define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE)
#define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
+#define S_EGRESS_SIZE 27
+#define M_EGRESS_SIZE 0x1fU
+#define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE)
+#define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE)
+
+#define S_INGRESS2_SIZE 5
+#define M_INGRESS2_SIZE 0x1fU
+#define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE)
+#define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE)
+
+#define S_INGRESS1_SIZE 0
+#define M_INGRESS1_SIZE 0x1fU
+#define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
+#define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
+
#define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
#define S_INGRESS2_BASE 16
@@ -1721,6 +3313,94 @@
#define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
#define F_MSIADDRLPERR V_MSIADDRLPERR(1U)
+#define S_IPGRPPERR 31
+#define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
+#define F_IPGRPPERR V_IPGRPPERR(1U)
+
+#define S_READRSPERR 29
+#define V_READRSPERR(x) ((x) << S_READRSPERR)
+#define F_READRSPERR V_READRSPERR(1U)
+
+#define S_TRGT1GRPPERR 28
+#define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
+#define F_TRGT1GRPPERR V_TRGT1GRPPERR(1U)
+
+#define S_IPSOTPERR 27
+#define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
+#define F_IPSOTPERR V_IPSOTPERR(1U)
+
+#define S_IPRETRYPERR 26
+#define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
+#define F_IPRETRYPERR V_IPRETRYPERR(1U)
+
+#define S_IPRXDATAGRPPERR 25
+#define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
+#define F_IPRXDATAGRPPERR V_IPRXDATAGRPPERR(1U)
+
+#define S_IPRXHDRGRPPERR 24
+#define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
+#define F_IPRXHDRGRPPERR V_IPRXHDRGRPPERR(1U)
+
+#define S_PIOTAGQPERR 23
+#define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
+#define F_PIOTAGQPERR V_PIOTAGQPERR(1U)
+
+#define S_MAGRPPERR 22
+#define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
+#define F_MAGRPPERR V_MAGRPPERR(1U)
+
+#define S_VFIDPERR 21
+#define V_VFIDPERR(x) ((x) << S_VFIDPERR)
+#define F_VFIDPERR V_VFIDPERR(1U)
+
+#define S_HREQRDPERR 17
+#define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
+#define F_HREQRDPERR V_HREQRDPERR(1U)
+
+#define S_HREQWRPERR 16
+#define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
+#define F_HREQWRPERR V_HREQWRPERR(1U)
+
+#define S_DREQRDPERR 14
+#define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
+#define F_DREQRDPERR V_DREQRDPERR(1U)
+
+#define S_DREQWRPERR 13
+#define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
+#define F_DREQWRPERR V_DREQWRPERR(1U)
+
+#define S_CREQRDPERR 11
+#define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
+#define F_CREQRDPERR V_CREQRDPERR(1U)
+
+#define S_MSTTAGQPERR 10
+#define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
+#define F_MSTTAGQPERR V_MSTTAGQPERR(1U)
+
+#define S_TGTTAGQPERR 9
+#define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
+#define F_TGTTAGQPERR V_TGTTAGQPERR(1U)
+
+#define S_PIOREQGRPPERR 8
+#define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
+#define F_PIOREQGRPPERR V_PIOREQGRPPERR(1U)
+
+#define S_PIOCPLGRPPERR 7
+#define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
+#define F_PIOCPLGRPPERR V_PIOCPLGRPPERR(1U)
+
+#define S_MSIXSTIPERR 2
+#define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
+#define F_MSIXSTIPERR V_MSIXSTIPERR(1U)
+
+#define S_MSTTIMEOUTPERR 1
+#define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
+#define F_MSTTIMEOUTPERR V_MSTTIMEOUTPERR(1U)
+
+#define S_MSTGRPPERR 0
+#define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
+#define F_MSTGRPPERR V_MSTGRPPERR(1U)
+
#define A_PCIE_INT_CAUSE 0x3004
#define A_PCIE_PERR_ENABLE 0x3008
#define A_PCIE_PERR_INJECT 0x300c
@@ -1771,6 +3451,90 @@
#define V_CFGSNP(x) ((x) << S_CFGSNP)
#define F_CFGSNP V_CFGSNP(1U)
+#define S_MAREQTIMEOUT 29
+#define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
+#define F_MAREQTIMEOUT V_MAREQTIMEOUT(1U)
+
+#define S_TRGT1BARTYPEERR 28
+#define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
+#define F_TRGT1BARTYPEERR V_TRGT1BARTYPEERR(1U)
+
+#define S_MAEXTRARSPERR 27
+#define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
+#define F_MAEXTRARSPERR V_MAEXTRARSPERR(1U)
+
+#define S_MARSPTIMEOUT 26
+#define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
+#define F_MARSPTIMEOUT V_MARSPTIMEOUT(1U)
+
+#define S_INTVFALLMSIDISERR 25
+#define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
+#define F_INTVFALLMSIDISERR V_INTVFALLMSIDISERR(1U)
+
+#define S_INTVFRANGEERR 24
+#define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
+#define F_INTVFRANGEERR V_INTVFRANGEERR(1U)
+
+#define S_INTPLIRSPERR 23
+#define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
+#define F_INTPLIRSPERR V_INTPLIRSPERR(1U)
+
+#define S_MEMREQRDTAGERR 22
+#define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
+#define F_MEMREQRDTAGERR V_MEMREQRDTAGERR(1U)
+
+#define S_CFGINITDONEERR 21
+#define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
+#define F_CFGINITDONEERR V_CFGINITDONEERR(1U)
+
+#define S_BAR2TIMEOUT 20
+#define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
+#define F_BAR2TIMEOUT V_BAR2TIMEOUT(1U)
+
+#define S_VPDTIMEOUT 19
+#define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
+#define F_VPDTIMEOUT V_VPDTIMEOUT(1U)
+
+#define S_MEMRSPRDTAGERR 18
+#define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
+#define F_MEMRSPRDTAGERR V_MEMRSPRDTAGERR(1U)
+
+#define S_MEMRSPWRTAGERR 17
+#define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
+#define F_MEMRSPWRTAGERR V_MEMRSPWRTAGERR(1U)
+
+#define S_PIORSPRDTAGERR 16
+#define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
+#define F_PIORSPRDTAGERR V_PIORSPRDTAGERR(1U)
+
+#define S_PIORSPWRTAGERR 15
+#define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
+#define F_PIORSPWRTAGERR V_PIORSPWRTAGERR(1U)
+
+#define S_DBITIMEOUT 14
+#define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
+#define F_DBITIMEOUT V_DBITIMEOUT(1U)
+
+#define S_PIOUNALINDWR 13
+#define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
+#define F_PIOUNALINDWR V_PIOUNALINDWR(1U)
+
+#define S_BAR2RDERR 12
+#define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
+#define F_BAR2RDERR V_BAR2RDERR(1U)
+
+#define S_MAWREOPERR 11
+#define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
+#define F_MAWREOPERR V_MAWREOPERR(1U)
+
+#define S_MARDEOPERR 10
+#define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
+#define F_MARDEOPERR V_MARDEOPERR(1U)
+
+#define S_BAR2REQ 2
+#define V_BAR2REQ(x) ((x) << S_BAR2REQ)
+#define F_BAR2REQ V_BAR2REQ(1U)
+
#define A_PCIE_CFG 0x3014
#define S_CFGDMAXPYLDSZRX 26
@@ -1861,12 +3625,80 @@
#define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
#define F_LINKDNRSTEN V_LINKDNRSTEN(1U)
+#define S_DIAGCTRLBUS 28
+#define M_DIAGCTRLBUS 0x7U
+#define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS)
+#define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS)
+
+#define S_IPPERREN 27
+#define V_IPPERREN(x) ((x) << S_IPPERREN)
+#define F_IPPERREN V_IPPERREN(1U)
+
+#define S_CFGDEXTTAGEN 26
+#define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN)
+#define F_CFGDEXTTAGEN V_CFGDEXTTAGEN(1U)
+
+#define S_CFGDMAXPYLDSZ 23
+#define M_CFGDMAXPYLDSZ 0x7U
+#define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ)
+#define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ)
+
+#define S_DCAEN 17
+#define V_DCAEN(x) ((x) << S_DCAEN)
+#define F_DCAEN V_DCAEN(1U)
+
+#define S_T5CMDREQPRIORITY 16
+#define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY)
+#define F_T5CMDREQPRIORITY V_T5CMDREQPRIORITY(1U)
+
+#define S_T5VPDREQPROTECT 14
+#define M_T5VPDREQPROTECT 0x3U
+#define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT)
+#define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT)
+
+#define S_DROPPEDRDRSPDATA 12
+#define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA)
+#define F_DROPPEDRDRSPDATA V_DROPPEDRDRSPDATA(1U)
+
+#define S_AI_INTX_REASSERTEN 11
+#define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN)
+#define F_AI_INTX_REASSERTEN V_AI_INTX_REASSERTEN(1U)
+
+#define S_AUTOTXNDISABLE 10
+#define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE)
+#define F_AUTOTXNDISABLE V_AUTOTXNDISABLE(1U)
+
+#define S_LINKREQRSTPCIECRSTMODE 3
+#define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
+#define F_LINKREQRSTPCIECRSTMODE V_LINKREQRSTPCIECRSTMODE(1U)
+
#define A_PCIE_DMA_CTRL 0x3018
#define S_LITTLEENDIAN 7
#define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN)
#define F_LITTLEENDIAN V_LITTLEENDIAN(1U)
+#define A_PCIE_CFG2 0x3018
+
+#define S_VPDTIMER 16
+#define M_VPDTIMER 0xffffU
+#define V_VPDTIMER(x) ((x) << S_VPDTIMER)
+#define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER)
+
+#define S_BAR2TIMER 4
+#define M_BAR2TIMER 0xfffU
+#define V_BAR2TIMER(x) ((x) << S_BAR2TIMER)
+#define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER)
+
+#define S_MSTREQRDRRASIMPLE 3
+#define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE)
+#define F_MSTREQRDRRASIMPLE V_MSTREQRDRRASIMPLE(1U)
+
+#define S_TOTMAXTAG 0
+#define M_TOTMAXTAG 0x3U
+#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
+#define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
+
#define A_PCIE_DMA_CFG 0x301c
#define S_MAXPYLDSIZE 28
@@ -1894,6 +3726,29 @@
#define V_MAXTAG(x) ((x) << S_MAXTAG)
#define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG)
+#define A_PCIE_CFG3 0x301c
+
+#define S_AUTOPIOCOOKIEMATCH 6
+#define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH)
+#define F_AUTOPIOCOOKIEMATCH V_AUTOPIOCOOKIEMATCH(1U)
+
+#define S_FLRPNDCPLMODE 4
+#define M_FLRPNDCPLMODE 0x3U
+#define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE)
+#define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE)
+
+#define S_HMADCASTFIRSTONLY 2
+#define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY)
+#define F_HMADCASTFIRSTONLY V_HMADCASTFIRSTONLY(1U)
+
+#define S_CMDDCASTFIRSTONLY 1
+#define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY)
+#define F_CMDDCASTFIRSTONLY V_CMDDCASTFIRSTONLY(1U)
+
+#define S_DMADCASTFIRSTONLY 0
+#define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY)
+#define F_DMADCASTFIRSTONLY V_DMADCASTFIRSTONLY(1U)
+
#define A_PCIE_DMA_STAT 0x3020
#define S_STATEREQ 28
@@ -1920,6 +3775,59 @@
#define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT)
#define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT)
+#define A_PCIE_CFG4 0x3020
+
+#define S_L1CLKREMOVALEN 17
+#define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN)
+#define F_L1CLKREMOVALEN V_L1CLKREMOVALEN(1U)
+
+#define S_READYENTERL23 16
+#define V_READYENTERL23(x) ((x) << S_READYENTERL23)
+#define F_READYENTERL23 V_READYENTERL23(1U)
+
+#define S_EXITL1 12
+#define V_EXITL1(x) ((x) << S_EXITL1)
+#define F_EXITL1 V_EXITL1(1U)
+
+#define S_ENTERL1 8
+#define V_ENTERL1(x) ((x) << S_ENTERL1)
+#define F_ENTERL1 V_ENTERL1(1U)
+
+#define S_GENPME 0
+#define M_GENPME 0xffU
+#define V_GENPME(x) ((x) << S_GENPME)
+#define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME)
+
+#define A_PCIE_CFG5 0x3024
+
+#define S_ENABLESKPPARITYFIX 2
+#define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX)
+#define F_ENABLESKPPARITYFIX V_ENABLESKPPARITYFIX(1U)
+
+#define S_ENABLEL2ENTRYINL1 1
+#define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1)
+#define F_ENABLEL2ENTRYINL1 V_ENABLEL2ENTRYINL1(1U)
+
+#define S_HOLDCPLENTERINGL1 0
+#define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1)
+#define F_HOLDCPLENTERINGL1 V_HOLDCPLENTERINGL1(1U)
+
+#define A_PCIE_CFG6 0x3028
+
+#define S_PERSTTIMERCOUNT 12
+#define M_PERSTTIMERCOUNT 0x3fffU
+#define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT)
+#define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT)
+
+#define S_PERSTTIMEOUT 8
+#define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT)
+#define F_PERSTTIMEOUT V_PERSTTIMEOUT(1U)
+
+#define S_PERSTTIMER 0
+#define M_PERSTTIMER 0xfU
+#define V_PERSTTIMER(x) ((x) << S_PERSTTIMER)
+#define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
+
#define A_PCIE_CMD_CTRL 0x303c
#define A_PCIE_CMD_CFG 0x3040
@@ -2034,6 +3942,29 @@
#define V_REGISTER(x) ((x) << S_REGISTER)
#define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
+#define S_CS2 28
+#define V_CS2(x) ((x) << S_CS2)
+#define F_CS2 V_CS2(1U)
+
+#define S_WRBE 24
+#define M_WRBE 0xfU
+#define V_WRBE(x) ((x) << S_WRBE)
+#define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)
+
+#define S_CFG_SPACE_VFVLD 23
+#define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
+#define F_CFG_SPACE_VFVLD V_CFG_SPACE_VFVLD(1U)
+
+#define S_CFG_SPACE_RVF 16
+#define M_CFG_SPACE_RVF 0x7fU
+#define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
+#define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)
+
+#define S_CFG_SPACE_PF 12
+#define M_CFG_SPACE_PF 0x7U
+#define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
+#define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
+
#define A_PCIE_CFG_SPACE_DATA 0x3064
#define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
@@ -2053,6 +3984,12 @@
#define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
#define A_PCIE_MEM_ACCESS_OFFSET 0x306c
+
+#define S_MEMOFST 7
+#define M_MEMOFST 0x1ffffffU
+#define V_MEMOFST(x) ((x) << S_MEMOFST)
+#define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
+
#define A_PCIE_MAILBOX_BASE_WIN 0x30a8
#define S_MBOXPCIEOFST 6
@@ -2106,6 +4043,16 @@
#define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG)
#define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG)
+#define S_T5_MA_MAXREQCNT 16
+#define M_T5_MA_MAXREQCNT 0x7fU
+#define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT)
+#define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT)
+
+#define S_MA_MAXREQSIZE 8
+#define M_MA_MAXREQSIZE 0x7U
+#define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE)
+#define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE)
+
#define A_PCIE_MA_SYNC 0x30b4
#define A_PCIE_FW 0x30b8
#define A_PCIE_FW_PF 0x30bc
@@ -2124,7 +4071,16 @@
#define V_PIOPAUSE(x) ((x) << S_PIOPAUSE)
#define F_PIOPAUSE V_PIOPAUSE(1U)
+#define S_MSTPAUSEDONE 30
+#define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE)
+#define F_MSTPAUSEDONE V_MSTPAUSEDONE(1U)
+
+#define S_MSTPAUSE 1
+#define V_MSTPAUSE(x) ((x) << S_MSTPAUSE)
+#define F_MSTPAUSE V_MSTPAUSE(1U)
+
#define A_PCIE_SYS_CFG_READY 0x30e0
+#define A_PCIE_MA_STAT 0x30e0
#define A_PCIE_STATIC_CFG1 0x30e4
#define S_LINKDOWN_RESET_EN 26
@@ -2180,6 +4136,22 @@
#define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE)
#define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE)
+#define S_AUXPOWER_DETECTED 27
+#define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED)
+#define F_AUXPOWER_DETECTED V_AUXPOWER_DETECTED(1U)
+
+#define A_PCIE_STATIC_CFG2 0x30e8
+
+#define S_PL_CONTROL 16
+#define M_PL_CONTROL 0xffffU
+#define V_PL_CONTROL(x) ((x) << S_PL_CONTROL)
+#define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL)
+
+#define S_STATIC_SPARE3 0
+#define M_STATIC_SPARE3 0x3fffU
+#define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3)
+#define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3)
+
#define A_PCIE_DBG_INDIR_REQ 0x30ec
#define S_DBGENABLE 31
@@ -2254,6 +4226,74 @@
#define V_PFNUM(x) ((x) << S_PFNUM)
#define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
+#define A_PCIE_PF_INT_CFG 0x3140
+#define A_PCIE_PF_INT_CFG2 0x3144
+#define A_PCIE_VF_INT_CFG 0x3180
+#define A_PCIE_VF_INT_CFG2 0x3184
+#define A_PCIE_PF_MSI_EN 0x35a8
+
+#define S_PFMSIEN_7_0 0
+#define M_PFMSIEN_7_0 0xffU
+#define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0)
+#define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0)
+
+#define A_PCIE_VF_MSI_EN_0 0x35ac
+#define A_PCIE_VF_MSI_EN_1 0x35b0
+#define A_PCIE_VF_MSI_EN_2 0x35b4
+#define A_PCIE_VF_MSI_EN_3 0x35b8
+#define A_PCIE_PF_MSIX_EN 0x35bc
+
+#define S_PFMSIXEN_7_0 0
+#define M_PFMSIXEN_7_0 0xffU
+#define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0)
+#define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0)
+
+#define A_PCIE_VF_MSIX_EN_0 0x35c0
+#define A_PCIE_VF_MSIX_EN_1 0x35c4
+#define A_PCIE_VF_MSIX_EN_2 0x35c8
+#define A_PCIE_VF_MSIX_EN_3 0x35cc
+#define A_PCIE_FID_VFID_SEL 0x35ec
+
+#define S_FID_VFID_SEL_SELECT 0
+#define M_FID_VFID_SEL_SELECT 0x3U
+#define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT)
+#define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT)
+
+#define A_PCIE_FID_VFID 0x3600
+
+#define S_FID_VFID_SELECT 30
+#define M_FID_VFID_SELECT 0x3U
+#define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT)
+#define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT)
+
+#define S_IDO 24
+#define V_IDO(x) ((x) << S_IDO)
+#define F_IDO V_IDO(1U)
+
+#define S_FID_VFID_VFID 16
+#define M_FID_VFID_VFID 0xffU
+#define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID)
+#define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID)
+
+#define S_FID_VFID_TC 11
+#define M_FID_VFID_TC 0x7U
+#define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC)
+#define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC)
+
+#define S_FID_VFID_VFVLD 10
+#define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD)
+#define F_FID_VFID_VFVLD V_FID_VFID_VFVLD(1U)
+
+#define S_FID_VFID_PF 7
+#define M_FID_VFID_PF 0x7U
+#define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF)
+#define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF)
+
+#define S_FID_VFID_RVF 0
+#define M_FID_VFID_RVF 0x7fU
+#define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF)
+#define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF)
+
#define A_PCIE_FID 0x3900
#define S_PAD 11
@@ -2270,6 +4310,695 @@
#define V_FUNC(x) ((x) << S_FUNC)
#define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
+#define A_PCIE_COOKIE_STAT 0x5600
+
+#define S_COOKIEB 16
+#define M_COOKIEB 0x3ffU
+#define V_COOKIEB(x) ((x) << S_COOKIEB)
+#define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB)
+
+#define S_COOKIEA 0
+#define M_COOKIEA 0x3ffU
+#define V_COOKIEA(x) ((x) << S_COOKIEA)
+#define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA)
+
+#define A_PCIE_FLR_PIO 0x5620
+
+#define S_RCVDBAR2COOKIE 24
+#define M_RCVDBAR2COOKIE 0xffU
+#define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE)
+#define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE)
+
+#define S_RCVDMARSPCOOKIE 16
+#define M_RCVDMARSPCOOKIE 0xffU
+#define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE)
+#define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE)
+
+#define S_RCVDPIORSPCOOKIE 8
+#define M_RCVDPIORSPCOOKIE 0xffU
+#define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE)
+#define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE)
+
+#define S_EXPDCOOKIE 0
+#define M_EXPDCOOKIE 0xffU
+#define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE)
+#define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE)
+
+#define A_PCIE_FLR_PIO2 0x5624
+
+#define S_RCVDMAREQCOOKIE 16
+#define M_RCVDMAREQCOOKIE 0xffU
+#define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE)
+#define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE)
+
+#define S_RCVDPIOREQCOOKIE 8
+#define M_RCVDPIOREQCOOKIE 0xffU
+#define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE)
+#define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE)
+
+#define A_PCIE_VC0_CDTS0 0x56cc
+
+#define S_CPLD0 20
+#define M_CPLD0 0xfffU
+#define V_CPLD0(x) ((x) << S_CPLD0)
+#define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0)
+
+#define S_PH0 12
+#define M_PH0 0xffU
+#define V_PH0(x) ((x) << S_PH0)
+#define G_PH0(x) (((x) >> S_PH0) & M_PH0)
+
+#define S_PD0 0
+#define M_PD0 0xfffU
+#define V_PD0(x) ((x) << S_PD0)
+#define G_PD0(x) (((x) >> S_PD0) & M_PD0)
+
+#define A_PCIE_VC0_CDTS1 0x56d0
+
+#define S_CPLH0 20
+#define M_CPLH0 0xffU
+#define V_CPLH0(x) ((x) << S_CPLH0)
+#define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0)
+
+#define S_NPH0 12
+#define M_NPH0 0xffU
+#define V_NPH0(x) ((x) << S_NPH0)
+#define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0)
+
+#define S_NPD0 0
+#define M_NPD0 0xfffU
+#define V_NPD0(x) ((x) << S_NPD0)
+#define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0)
+
+#define A_PCIE_VC1_CDTS0 0x56d4
+
+#define S_CPLD1 20
+#define M_CPLD1 0xfffU
+#define V_CPLD1(x) ((x) << S_CPLD1)
+#define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1)
+
+#define S_PH1 12
+#define M_PH1 0xffU
+#define V_PH1(x) ((x) << S_PH1)
+#define G_PH1(x) (((x) >> S_PH1) & M_PH1)
+
+#define S_PD1 0
+#define M_PD1 0xfffU
+#define V_PD1(x) ((x) << S_PD1)
+#define G_PD1(x) (((x) >> S_PD1) & M_PD1)
+
+#define A_PCIE_VC1_CDTS1 0x56d8
+
+#define S_CPLH1 20
+#define M_CPLH1 0xffU
+#define V_CPLH1(x) ((x) << S_CPLH1)
+#define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1)
+
+#define S_NPH1 12
+#define M_NPH1 0xffU
+#define V_NPH1(x) ((x) << S_NPH1)
+#define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1)
+
+#define S_NPD1 0
+#define M_NPD1 0xfffU
+#define V_NPD1(x) ((x) << S_NPD1)
+#define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1)
+
+#define A_PCIE_FLR_PF_STATUS 0x56dc
+#define A_PCIE_FLR_VF0_STATUS 0x56e0
+#define A_PCIE_FLR_VF1_STATUS 0x56e4
+#define A_PCIE_FLR_VF2_STATUS 0x56e8
+#define A_PCIE_FLR_VF3_STATUS 0x56ec
+#define A_PCIE_STAT 0x56f4
+
+#define S_PM_STATUS 24
+#define M_PM_STATUS 0xffU
+#define V_PM_STATUS(x) ((x) << S_PM_STATUS)
+#define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS)
+
+#define S_PM_CURRENTSTATE 20
+#define M_PM_CURRENTSTATE 0x7U
+#define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE)
+#define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE)
+
+#define S_LTSSMENABLE 12
+#define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE)
+#define F_LTSSMENABLE V_LTSSMENABLE(1U)
+
+#define S_STATECFGINITF 4
+#define M_STATECFGINITF 0x7fU
+#define V_STATECFGINITF(x) ((x) << S_STATECFGINITF)
+#define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF)
+
+#define S_STATECFGINIT 0
+#define M_STATECFGINIT 0xfU
+#define V_STATECFGINIT(x) ((x) << S_STATECFGINIT)
+#define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT)
+
+#define A_PCIE_CRS 0x56f8
+
+#define S_CRS_ENABLE 0
+#define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE)
+#define F_CRS_ENABLE V_CRS_ENABLE(1U)
+
+#define A_PCIE_LTSSM 0x56fc
+
+#define S_LTSSM_ENABLE 0
+#define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE)
+#define F_LTSSM_ENABLE V_LTSSM_ENABLE(1U)
+
+#define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
+
+#define S_REPLAY_TIME_LIMIT 16
+#define M_REPLAY_TIME_LIMIT 0xffffU
+#define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT)
+#define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT)
+
+#define S_ACK_LATENCY_TIMER_LIMIT 0
+#define M_ACK_LATENCY_TIMER_LIMIT 0xffffU
+#define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT)
+#define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT)
+
+#define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704
+#define A_PCIE_CORE_PORT_FORCE_LINK 0x5708
+
+#define S_LOW_POWER_ENTRANCE_COUNT 24
+#define M_LOW_POWER_ENTRANCE_COUNT 0xffU
+#define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT)
+#define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT)
+
+#define S_LINK_STATE 16
+#define M_LINK_STATE 0x3fU
+#define V_LINK_STATE(x) ((x) << S_LINK_STATE)
+#define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE)
+
+#define S_FORCE_LINK 15
+#define V_FORCE_LINK(x) ((x) << S_FORCE_LINK)
+#define F_FORCE_LINK V_FORCE_LINK(1U)
+
+#define S_LINK_NUMBER 0
+#define M_LINK_NUMBER 0xffU
+#define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER)
+#define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER)
+
+#define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c
+
+#define S_ENTER_ASPM_L1_WO_L0S 30
+#define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S)
+#define F_ENTER_ASPM_L1_WO_L0S V_ENTER_ASPM_L1_WO_L0S(1U)
+
+#define S_L1_ENTRANCE_LATENCY 27
+#define M_L1_ENTRANCE_LATENCY 0x7U
+#define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY)
+#define G_L1_ENTRANCE_LATENCY(x) (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY)
+
+#define S_L0S_ENTRANCE_LATENCY 24
+#define M_L0S_ENTRANCE_LATENCY 0x7U
+#define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY)
+#define G_L0S_ENTRANCE_LATENCY(x) (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY)
+
+#define S_COMMON_CLOCK_N_FTS 16
+#define M_COMMON_CLOCK_N_FTS 0xffU
+#define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS)
+#define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS)
+
+#define S_N_FTS 8
+#define M_N_FTS 0xffU
+#define V_N_FTS(x) ((x) << S_N_FTS)
+#define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS)
+
+#define S_ACK_FREQUENCY 0
+#define M_ACK_FREQUENCY 0xffU
+#define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY)
+#define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY)
+
+#define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710
+
+#define S_CROSSLINK_ACTIVE 23
+#define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE)
+#define F_CROSSLINK_ACTIVE V_CROSSLINK_ACTIVE(1U)
+
+#define S_CROSSLINK_ENABLE 22
+#define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE)
+#define F_CROSSLINK_ENABLE V_CROSSLINK_ENABLE(1U)
+
+#define S_LINK_MODE_ENABLE 16
+#define M_LINK_MODE_ENABLE 0x3fU
+#define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE)
+#define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE)
+
+#define S_FAST_LINK_MODE 7
+#define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE)
+#define F_FAST_LINK_MODE V_FAST_LINK_MODE(1U)
+
+#define S_DLL_LINK_ENABLE 5
+#define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE)
+#define F_DLL_LINK_ENABLE V_DLL_LINK_ENABLE(1U)
+
+#define S_RESET_ASSERT 3
+#define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT)
+#define F_RESET_ASSERT V_RESET_ASSERT(1U)
+
+#define S_LOOPBACK_ENABLE 2
+#define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE)
+#define F_LOOPBACK_ENABLE V_LOOPBACK_ENABLE(1U)
+
+#define S_SCRAMBLE_DISABLE 1
+#define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE)
+#define F_SCRAMBLE_DISABLE V_SCRAMBLE_DISABLE(1U)
+
+#define S_VENDOR_SPECIFIC_DLLP_REQUEST 0
+#define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST)
+#define F_VENDOR_SPECIFIC_DLLP_REQUEST V_VENDOR_SPECIFIC_DLLP_REQUEST(1U)
+
+#define A_PCIE_CORE_LANE_SKEW 0x5714
+
+#define S_DISABLE_DESKEW 31
+#define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW)
+#define F_DISABLE_DESKEW V_DISABLE_DESKEW(1U)
+
+#define S_ACK_NAK_DISABLE 25
+#define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE)
+#define F_ACK_NAK_DISABLE V_ACK_NAK_DISABLE(1U)
+
+#define S_FLOW_CONTROL_DISABLE 24
+#define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE)
+#define F_FLOW_CONTROL_DISABLE V_FLOW_CONTROL_DISABLE(1U)
+
+#define S_INSERT_TXSKEW 0
+#define M_INSERT_TXSKEW 0xffffffU
+#define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW)
+#define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW)
+
+#define A_PCIE_CORE_SYMBOL_NUMBER 0x5718
+
+#define S_FLOW_CONTROL_TIMER_MODIFIER 24
+#define M_FLOW_CONTROL_TIMER_MODIFIER 0x1fU
+#define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER)
+#define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER)
+
+#define S_ACK_NAK_TIMER_MODIFIER 19
+#define M_ACK_NAK_TIMER_MODIFIER 0x1fU
+#define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER)
+#define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER)
+
+#define S_REPLAY_TIMER_MODIFIER 14
+#define M_REPLAY_TIMER_MODIFIER 0x1fU
+#define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER)
+#define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER)
+
+#define S_MAXFUNC 0
+#define M_MAXFUNC 0x7U
+#define V_MAXFUNC(x) ((x) << S_MAXFUNC)
+#define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC)
+
+#define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c
+
+#define S_MASK_RADM_FILTER 16
+#define M_MASK_RADM_FILTER 0xffffU
+#define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER)
+#define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER)
+
+#define S_DISABLE_FC_WATCHDOG 15
+#define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG)
+#define F_DISABLE_FC_WATCHDOG V_DISABLE_FC_WATCHDOG(1U)
+
+#define S_SKP_INTERVAL 0
+#define M_SKP_INTERVAL 0x7ffU
+#define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL)
+#define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL)
+
+#define A_PCIE_CORE_FILTER_MASK2 0x5720
+#define A_PCIE_CORE_DEBUG_0 0x5728
+#define A_PCIE_CORE_DEBUG_1 0x572c
+#define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730
+
+#define S_TXPH_FC 12
+#define M_TXPH_FC 0xffU
+#define V_TXPH_FC(x) ((x) << S_TXPH_FC)
+#define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC)
+
+#define S_TXPD_FC 0
+#define M_TXPD_FC 0xfffU
+#define V_TXPD_FC(x) ((x) << S_TXPD_FC)
+#define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC)
+
+#define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734
+
+#define S_TXNPH_FC 12
+#define M_TXNPH_FC 0xffU
+#define V_TXNPH_FC(x) ((x) << S_TXNPH_FC)
+#define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC)
+
+#define S_TXNPD_FC 0
+#define M_TXNPD_FC 0xfffU
+#define V_TXNPD_FC(x) ((x) << S_TXNPD_FC)
+#define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC)
+
+#define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738
+
+#define S_TXCPLH_FC 12
+#define M_TXCPLH_FC 0xffU
+#define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC)
+#define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC)
+
+#define S_TXCPLD_FC 0
+#define M_TXCPLD_FC 0xfffU
+#define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC)
+#define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC)
+
+#define A_PCIE_CORE_QUEUE_STATUS 0x573c
+
+#define S_RXQUEUE_NOT_EMPTY 2
+#define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY)
+#define F_RXQUEUE_NOT_EMPTY V_RXQUEUE_NOT_EMPTY(1U)
+
+#define S_TXRETRYBUF_NOT_EMPTY 1
+#define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY)
+#define F_TXRETRYBUF_NOT_EMPTY V_TXRETRYBUF_NOT_EMPTY(1U)
+
+#define S_RXTLP_FC_NOT_RETURNED 0
+#define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED)
+#define F_RXTLP_FC_NOT_RETURNED V_RXTLP_FC_NOT_RETURNED(1U)
+
+#define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740
+
+#define S_VC3_WRR 24
+#define M_VC3_WRR 0xffU
+#define V_VC3_WRR(x) ((x) << S_VC3_WRR)
+#define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR)
+
+#define S_VC2_WRR 16
+#define M_VC2_WRR 0xffU
+#define V_VC2_WRR(x) ((x) << S_VC2_WRR)
+#define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR)
+
+#define S_VC1_WRR 8
+#define M_VC1_WRR 0xffU
+#define V_VC1_WRR(x) ((x) << S_VC1_WRR)
+#define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR)
+
+#define S_VC0_WRR 0
+#define M_VC0_WRR 0xffU
+#define V_VC0_WRR(x) ((x) << S_VC0_WRR)
+#define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR)
+
+#define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744
+
+#define S_VC7_WRR 24
+#define M_VC7_WRR 0xffU
+#define V_VC7_WRR(x) ((x) << S_VC7_WRR)
+#define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR)
+
+#define S_VC6_WRR 16
+#define M_VC6_WRR 0xffU
+#define V_VC6_WRR(x) ((x) << S_VC6_WRR)
+#define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR)
+
+#define S_VC5_WRR 8
+#define M_VC5_WRR 0xffU
+#define V_VC5_WRR(x) ((x) << S_VC5_WRR)
+#define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR)
+
+#define S_VC4_WRR 0
+#define M_VC4_WRR 0xffU
+#define V_VC4_WRR(x) ((x) << S_VC4_WRR)
+#define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR)
+
+#define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748
+
+#define S_VC0_RX_ORDERING 31
+#define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING)
+#define F_VC0_RX_ORDERING V_VC0_RX_ORDERING(1U)
+
+#define S_VC0_TLP_ORDERING 30
+#define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING)
+#define F_VC0_TLP_ORDERING V_VC0_TLP_ORDERING(1U)
+
+#define S_VC0_PTLP_QUEUE_MODE 21
+#define M_VC0_PTLP_QUEUE_MODE 0x7U
+#define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE)
+#define G_VC0_PTLP_QUEUE_MODE(x) (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE)
+
+#define S_VC0_PH_CREDITS 12
+#define M_VC0_PH_CREDITS 0xffU
+#define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS)
+#define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS)
+
+#define S_VC0_PD_CREDITS 0
+#define M_VC0_PD_CREDITS 0xfffU
+#define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS)
+#define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS)
+
+#define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c
+
+#define S_VC0_NPTLP_QUEUE_MODE 21
+#define M_VC0_NPTLP_QUEUE_MODE 0x7U
+#define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE)
+#define G_VC0_NPTLP_QUEUE_MODE(x) (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE)
+
+#define S_VC0_NPH_CREDITS 12
+#define M_VC0_NPH_CREDITS 0xffU
+#define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS)
+#define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS)
+
+#define S_VC0_NPD_CREDITS 0
+#define M_VC0_NPD_CREDITS 0xfffU
+#define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS)
+#define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS)
+
+#define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750
+
+#define S_VC0_CPLTLP_QUEUE_MODE 21
+#define M_VC0_CPLTLP_QUEUE_MODE 0x7U
+#define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE)
+#define G_VC0_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE)
+
+#define S_VC0_CPLH_CREDITS 12
+#define M_VC0_CPLH_CREDITS 0xffU
+#define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS)
+#define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS)
+
+#define S_VC0_CPLD_CREDITS 0
+#define M_VC0_CPLD_CREDITS 0xfffU
+#define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS)
+#define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS)
+
+#define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754
+
+#define S_VC1_TLP_ORDERING 30
+#define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING)
+#define F_VC1_TLP_ORDERING V_VC1_TLP_ORDERING(1U)
+
+#define S_VC1_PTLP_QUEUE_MODE 21
+#define M_VC1_PTLP_QUEUE_MODE 0x7U
+#define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE)
+#define G_VC1_PTLP_QUEUE_MODE(x) (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE)
+
+#define S_VC1_PH_CREDITS 12
+#define M_VC1_PH_CREDITS 0xffU
+#define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS)
+#define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS)
+
+#define S_VC1_PD_CREDITS 0
+#define M_VC1_PD_CREDITS 0xfffU
+#define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS)
+#define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS)
+
+#define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758
+
+#define S_VC1_NPTLP_QUEUE_MODE 21
+#define M_VC1_NPTLP_QUEUE_MODE 0x7U
+#define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE)
+#define G_VC1_NPTLP_QUEUE_MODE(x) (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE)
+
+#define S_VC1_NPH_CREDITS 12
+#define M_VC1_NPH_CREDITS 0xffU
+#define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS)
+#define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS)
+
+#define S_VC1_NPD_CREDITS 0
+#define M_VC1_NPD_CREDITS 0xfffU
+#define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS)
+#define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS)
+
+#define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c
+
+#define S_VC1_CPLTLP_QUEUE_MODE 21
+#define M_VC1_CPLTLP_QUEUE_MODE 0x7U
+#define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE)
+#define G_VC1_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE)
+
+#define S_VC1_CPLH_CREDITS 12
+#define M_VC1_CPLH_CREDITS 0xffU
+#define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS)
+#define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS)
+
+#define S_VC1_CPLD_CREDITS 0
+#define M_VC1_CPLD_CREDITS 0xfffU
+#define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS)
+#define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS)
+
+#define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
+
+#define S_SEL_DEEMPHASIS 20
+#define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS)
+#define F_SEL_DEEMPHASIS V_SEL_DEEMPHASIS(1U)
+
+#define S_TXCMPLRCV 19
+#define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV)
+#define F_TXCMPLRCV V_TXCMPLRCV(1U)
+
+#define S_PHYTXSWING 18
+#define V_PHYTXSWING(x) ((x) << S_PHYTXSWING)
+#define F_PHYTXSWING V_PHYTXSWING(1U)
+
+#define S_DIRSPDCHANGE 17
+#define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE)
+#define F_DIRSPDCHANGE V_DIRSPDCHANGE(1U)
+
+#define S_NUM_LANES 8
+#define M_NUM_LANES 0x1ffU
+#define V_NUM_LANES(x) ((x) << S_NUM_LANES)
+#define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)
+
+#define S_NFTS_GEN2_3 0
+#define M_NFTS_GEN2_3 0xffU
+#define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3)
+#define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3)
+
+#define A_PCIE_CORE_PHY_STATUS 0x5810
+#define A_PCIE_CORE_PHY_CONTROL 0x5814
+#define A_PCIE_CORE_GEN3_CONTROL 0x5890
+
+#define S_DC_BALANCE_DISABLE 18
+#define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE)
+#define F_DC_BALANCE_DISABLE V_DC_BALANCE_DISABLE(1U)
+
+#define S_DLLP_DELAY_DISABLE 17
+#define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE)
+#define F_DLLP_DELAY_DISABLE V_DLLP_DELAY_DISABLE(1U)
+
+#define S_EQL_DISABLE 16
+#define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE)
+#define F_EQL_DISABLE V_EQL_DISABLE(1U)
+
+#define S_EQL_REDO_DISABLE 11
+#define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE)
+#define F_EQL_REDO_DISABLE V_EQL_REDO_DISABLE(1U)
+
+#define S_EQL_EIEOS_CNTRST_DISABLE 10
+#define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE)
+#define F_EQL_EIEOS_CNTRST_DISABLE V_EQL_EIEOS_CNTRST_DISABLE(1U)
+
+#define S_EQL_PH2_PH3_DISABLE 9
+#define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE)
+#define F_EQL_PH2_PH3_DISABLE V_EQL_PH2_PH3_DISABLE(1U)
+
+#define S_DISABLE_SCRAMBLER 8
+#define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER)
+#define F_DISABLE_SCRAMBLER V_DISABLE_SCRAMBLER(1U)
+
+#define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
+
+#define S_FULL_SWING 6
+#define M_FULL_SWING 0x3fU
+#define V_FULL_SWING(x) ((x) << S_FULL_SWING)
+#define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING)
+
+#define S_LOW_FREQUENCY 0
+#define M_LOW_FREQUENCY 0x3fU
+#define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY)
+#define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY)
+
+#define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898
+
+#define S_POSTCURSOR 12
+#define M_POSTCURSOR 0x3fU
+#define V_POSTCURSOR(x) ((x) << S_POSTCURSOR)
+#define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR)
+
+#define S_CURSOR 6
+#define M_CURSOR 0x3fU
+#define V_CURSOR(x) ((x) << S_CURSOR)
+#define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR)
+
+#define S_PRECURSOR 0
+#define M_PRECURSOR 0x3fU
+#define V_PRECURSOR(x) ((x) << S_PRECURSOR)
+#define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR)
+
+#define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c
+
+#define S_INDEX 0
+#define M_INDEX 0xfU
+#define V_INDEX(x) ((x) << S_INDEX)
+#define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX)
+
+#define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4
+
+#define S_LEGALITY_STATUS 0
+#define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS)
+#define F_LEGALITY_STATUS V_LEGALITY_STATUS(1U)
+
+#define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8
+
+#define S_INCLUDE_INITIAL_FOM 24
+#define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM)
+#define F_INCLUDE_INITIAL_FOM V_INCLUDE_INITIAL_FOM(1U)
+
+#define S_PRESET_REQUEST_VECTOR 8
+#define M_PRESET_REQUEST_VECTOR 0xffffU
+#define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR)
+#define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR)
+
+#define S_PHASE23_2MS_TIMEOUT_DISABLE 5
+#define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE)
+#define F_PHASE23_2MS_TIMEOUT_DISABLE V_PHASE23_2MS_TIMEOUT_DISABLE(1U)
+
+#define S_AFTER24MS 4
+#define V_AFTER24MS(x) ((x) << S_AFTER24MS)
+#define F_AFTER24MS V_AFTER24MS(1U)
+
+#define S_FEEDBACK_MODE 0
+#define M_FEEDBACK_MODE 0xfU
+#define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE)
+#define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE)
+
+#define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac
+
+#define S_WINAPERTURE_CPLUS1 14
+#define M_WINAPERTURE_CPLUS1 0xfU
+#define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1)
+#define G_WINAPERTURE_CPLUS1(x) (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1)
+
+#define S_WINAPERTURE_CMINS1 10
+#define M_WINAPERTURE_CMINS1 0xfU
+#define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1)
+#define G_WINAPERTURE_CMINS1(x) (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1)
+
+#define S_CONVERGENCE_WINDEPTH 5
+#define M_CONVERGENCE_WINDEPTH 0x1fU
+#define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH)
+#define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH)
+
+#define S_EQMASTERPHASE_MINTIME 0
+#define M_EQMASTERPHASE_MINTIME 0x1fU
+#define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME)
+#define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME)
+
+#define A_PCIE_CORE_PIPE_CONTROL 0x58b8
+
+#define S_PIPE_LOOPBACK_EN 0
+#define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN)
+#define F_PIPE_LOOPBACK_EN V_PIPE_LOOPBACK_EN(1U)
+
+#define A_PCIE_CORE_DBI_RO_WE 0x58bc
+
+#define S_READONLY_WRITEEN 0
+#define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN)
+#define F_READONLY_WRITEEN V_READONLY_WRITEEN(1U)
+
#define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
#define S_SMTD 27
@@ -2489,6 +5218,105 @@
#define V_BRVN(x) ((x) << S_BRVN)
#define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN)
+#define A_PCIE_T5_DMA_CFG 0x5940
+
+#define S_T5_DMA_MAXREQCNT 20
+#define M_T5_DMA_MAXREQCNT 0xffU
+#define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT)
+#define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT)
+
+#define S_T5_DMA_MAXRDREQSIZE 17
+#define M_T5_DMA_MAXRDREQSIZE 0x7U
+#define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE)
+#define G_T5_DMA_MAXRDREQSIZE(x) (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE)
+
+#define S_T5_DMA_MAXRSPCNT 8
+#define M_T5_DMA_MAXRSPCNT 0x1ffU
+#define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT)
+#define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT)
+
+#define S_SEQCHKDIS 7
+#define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS)
+#define F_SEQCHKDIS V_SEQCHKDIS(1U)
+
+#define S_MINTAG 0
+#define M_MINTAG 0x7fU
+#define V_MINTAG(x) ((x) << S_MINTAG)
+#define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG)
+
+#define A_PCIE_T5_DMA_STAT 0x5944
+
+#define S_DMA_RESPCNT 20
+#define M_DMA_RESPCNT 0xfffU
+#define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT)
+#define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT)
+
+#define S_DMA_RDREQCNT 12
+#define M_DMA_RDREQCNT 0xffU
+#define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT)
+#define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT)
+
+#define S_DMA_WRREQCNT 0
+#define M_DMA_WRREQCNT 0x7ffU
+#define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT)
+#define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT)
+
+#define A_PCIE_T5_DMA_STAT2 0x5948
+
+#define S_COOKIECNT 24
+#define M_COOKIECNT 0xfU
+#define V_COOKIECNT(x) ((x) << S_COOKIECNT)
+#define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)
+
+#define S_RDSEQNUMUPDCNT 20
+#define M_RDSEQNUMUPDCNT 0xfU
+#define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
+#define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)
+
+#define S_SIREQCNT 16
+#define M_SIREQCNT 0xfU
+#define V_SIREQCNT(x) ((x) << S_SIREQCNT)
+#define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)
+
+#define S_WREOPMATCHSOP 12
+#define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
+#define F_WREOPMATCHSOP V_WREOPMATCHSOP(1U)
+
+#define S_WRSOPCNT 8
+#define M_WRSOPCNT 0xfU
+#define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
+#define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)
+
+#define S_RDSOPCNT 0
+#define M_RDSOPCNT 0xffU
+#define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
+#define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
+
+#define A_PCIE_T5_DMA_STAT3 0x594c
+
+#define S_ATMREQSOPCNT 24
+#define M_ATMREQSOPCNT 0xffU
+#define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
+#define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)
+
+#define S_ATMEOPMATCHSOP 17
+#define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
+#define F_ATMEOPMATCHSOP V_ATMEOPMATCHSOP(1U)
+
+#define S_RSPEOPMATCHSOP 16
+#define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
+#define F_RSPEOPMATCHSOP V_RSPEOPMATCHSOP(1U)
+
+#define S_RSPERRCNT 8
+#define M_RSPERRCNT 0xffU
+#define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
+#define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)
+
+#define S_RSPSOPCNT 0
+#define M_RSPSOPCNT 0xffU
+#define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
+#define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
+
#define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
#define S_OP0H 24
@@ -2599,6 +5427,34 @@
#define V_ON3H(x) ((x) << S_ON3H)
#define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H)
+#define A_PCIE_T5_CMD_CFG 0x5980
+
+#define S_T5_CMD_MAXRDREQSIZE 17
+#define M_T5_CMD_MAXRDREQSIZE 0x7U
+#define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE)
+#define G_T5_CMD_MAXRDREQSIZE(x) (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE)
+
+#define S_T5_CMD_MAXRSPCNT 8
+#define M_T5_CMD_MAXRSPCNT 0xffU
+#define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT)
+#define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT)
+
+#define S_USECMDPOOL 7
+#define V_USECMDPOOL(x) ((x) << S_USECMDPOOL)
+#define F_USECMDPOOL V_USECMDPOOL(1U)
+
+#define A_PCIE_T5_CMD_STAT 0x5984
+
+#define S_T5_STAT_RSPCNT 20
+#define M_T5_STAT_RSPCNT 0x7ffU
+#define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT)
+#define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT)
+
+#define S_RDREQCNT 12
+#define M_RDREQCNT 0x1fU
+#define V_RDREQCNT(x) ((x) << S_RDREQCNT)
+#define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT)
+
#define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
#define S_IN0H 24
@@ -2621,6 +5477,8 @@
#define V_IN3H(x) ((x) << S_IN3H)
#define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H)
+#define A_PCIE_T5_CMD_STAT2 0x5988
+#define A_PCIE_T5_CMD_STAT3 0x598c
#define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
#define S_OC0T 24
@@ -2904,6 +5762,23 @@
#define V_CRSE(x) ((x) << S_CRSE)
#define F_CRSE V_CRSE(1U)
+#define A_PCIE_T5_HMA_CFG 0x59b0
+
+#define S_HMA_MAXREQCNT 20
+#define M_HMA_MAXREQCNT 0x1fU
+#define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT)
+#define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT)
+
+#define S_T5_HMA_MAXRDREQSIZE 17
+#define M_T5_HMA_MAXRDREQSIZE 0x7U
+#define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE)
+#define G_T5_HMA_MAXRDREQSIZE(x) (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE)
+
+#define S_T5_HMA_MAXRSPCNT 8
+#define M_T5_HMA_MAXRSPCNT 0x1fU
+#define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT)
+#define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT)
+
#define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
#define S_RLCS 31
@@ -2950,6 +5825,23 @@
#define V_CRSS(x) ((x) << S_CRSS)
#define F_CRSS V_CRSS(1U)
+#define A_PCIE_T5_HMA_STAT 0x59b4
+
+#define S_HMA_RESPCNT 20
+#define M_HMA_RESPCNT 0x1ffU
+#define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT)
+#define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT)
+
+#define S_HMA_RDREQCNT 12
+#define M_HMA_RDREQCNT 0x3fU
+#define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT)
+#define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT)
+
+#define S_HMA_WRREQCNT 0
+#define M_HMA_WRREQCNT 0x1ffU
+#define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT)
+#define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT)
+
#define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
#define S_RLCI 31
@@ -2996,6 +5888,7 @@
#define V_CRSI(x) ((x) << S_CRSI)
#define F_CRSI V_CRSI(1U)
+#define A_PCIE_T5_HMA_STAT2 0x59b8
#define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
#define S_PTOM 31
@@ -3038,6 +5931,7 @@
#define V_PMC7(x) ((x) << S_PMC7)
#define F_PMC7 V_PMC7(1U)
+#define A_PCIE_T5_HMA_STAT3 0x59bc
#define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
#define S_PTOS 31
@@ -3112,6 +6006,84 @@
#define V_PME7(x) ((x) << S_PME7)
#define F_PME7 V_PME7(1U)
+#define A_PCIE_CGEN 0x59c0
+
+#define S_VPD_DYNAMIC_CGEN 26
+#define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN)
+#define F_VPD_DYNAMIC_CGEN V_VPD_DYNAMIC_CGEN(1U)
+
+#define S_MA_DYNAMIC_CGEN 25
+#define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN)
+#define F_MA_DYNAMIC_CGEN V_MA_DYNAMIC_CGEN(1U)
+
+#define S_TAGQ_DYNAMIC_CGEN 24
+#define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN)
+#define F_TAGQ_DYNAMIC_CGEN V_TAGQ_DYNAMIC_CGEN(1U)
+
+#define S_REQCTL_DYNAMIC_CGEN 23
+#define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN)
+#define F_REQCTL_DYNAMIC_CGEN V_REQCTL_DYNAMIC_CGEN(1U)
+
+#define S_RSPDATAPROC_DYNAMIC_CGEN 22
+#define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN)
+#define F_RSPDATAPROC_DYNAMIC_CGEN V_RSPDATAPROC_DYNAMIC_CGEN(1U)
+
+#define S_RSPRDQ_DYNAMIC_CGEN 21
+#define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN)
+#define F_RSPRDQ_DYNAMIC_CGEN V_RSPRDQ_DYNAMIC_CGEN(1U)
+
+#define S_RSPIPIF_DYNAMIC_CGEN 20
+#define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN)
+#define F_RSPIPIF_DYNAMIC_CGEN V_RSPIPIF_DYNAMIC_CGEN(1U)
+
+#define S_HMA_STATIC_CGEN 19
+#define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN)
+#define F_HMA_STATIC_CGEN V_HMA_STATIC_CGEN(1U)
+
+#define S_HMA_DYNAMIC_CGEN 18
+#define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN)
+#define F_HMA_DYNAMIC_CGEN V_HMA_DYNAMIC_CGEN(1U)
+
+#define S_CMD_STATIC_CGEN 16
+#define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN)
+#define F_CMD_STATIC_CGEN V_CMD_STATIC_CGEN(1U)
+
+#define S_CMD_DYNAMIC_CGEN 15
+#define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN)
+#define F_CMD_DYNAMIC_CGEN V_CMD_DYNAMIC_CGEN(1U)
+
+#define S_DMA_STATIC_CGEN 13
+#define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN)
+#define F_DMA_STATIC_CGEN V_DMA_STATIC_CGEN(1U)
+
+#define S_DMA_DYNAMIC_CGEN 12
+#define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN)
+#define F_DMA_DYNAMIC_CGEN V_DMA_DYNAMIC_CGEN(1U)
+
+#define S_VFID_SLEEPSTATUS 10
+#define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS)
+#define F_VFID_SLEEPSTATUS V_VFID_SLEEPSTATUS(1U)
+
+#define S_VC1_SLEEPSTATUS 9
+#define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS)
+#define F_VC1_SLEEPSTATUS V_VC1_SLEEPSTATUS(1U)
+
+#define S_STI_SLEEPSTATUS 8
+#define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS)
+#define F_STI_SLEEPSTATUS V_STI_SLEEPSTATUS(1U)
+
+#define S_VFID_SLEEPREQ 2
+#define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ)
+#define F_VFID_SLEEPREQ V_VFID_SLEEPREQ(1U)
+
+#define S_VC1_SLEEPREQ 1
+#define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ)
+#define F_VC1_SLEEPREQ V_VC1_SLEEPREQ(1U)
+
+#define S_STI_SLEEPREQ 0
+#define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ)
+#define F_STI_SLEEPREQ V_STI_SLEEPREQ(1U)
+
#define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
#define S_PTOI 31
@@ -3154,6 +6126,21 @@
#define V_PC7I(x) ((x) << S_PC7I)
#define F_PC7I V_PC7I(1U)
+#define A_PCIE_MA_RSP 0x59c4
+
+#define S_TIMERVALUE 8
+#define M_TIMERVALUE 0xffffffU
+#define V_TIMERVALUE(x) ((x) << S_TIMERVALUE)
+#define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE)
+
+#define S_MAREQTIMEREN 1
+#define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN)
+#define F_MAREQTIMEREN V_MAREQTIMEREN(1U)
+
+#define S_MARSPTIMEREN 0
+#define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN)
+#define F_MARSPTIMEREN V_MARSPTIMEREN(1U)
+
#define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
#define S_TOAK 31
@@ -3176,6 +6163,52 @@
#define V_ALET(x) ((x) << S_ALET)
#define F_ALET V_ALET(1U)
+#define A_PCIE_HPRD 0x59c8
+
+#define S_NPH_CREDITSAVAILVC0 19
+#define M_NPH_CREDITSAVAILVC0 0x3U
+#define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0)
+#define G_NPH_CREDITSAVAILVC0(x) (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0)
+
+#define S_NPD_CREDITSAVAILVC0 17
+#define M_NPD_CREDITSAVAILVC0 0x3U
+#define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0)
+#define G_NPD_CREDITSAVAILVC0(x) (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0)
+
+#define S_NPH_CREDITSAVAILVC1 15
+#define M_NPH_CREDITSAVAILVC1 0x3U
+#define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1)
+#define G_NPH_CREDITSAVAILVC1(x) (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1)
+
+#define S_NPD_CREDITSAVAILVC1 13
+#define M_NPD_CREDITSAVAILVC1 0x3U
+#define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1)
+#define G_NPD_CREDITSAVAILVC1(x) (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1)
+
+#define S_NPH_CREDITSREQUIRED 11
+#define M_NPH_CREDITSREQUIRED 0x3U
+#define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED)
+#define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED)
+
+#define S_NPD_CREDITSREQUIRED 9
+#define M_NPD_CREDITSREQUIRED 0x3U
+#define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED)
+#define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED)
+
+#define S_REQBURSTCOUNT 5
+#define M_REQBURSTCOUNT 0xfU
+#define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT)
+#define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT)
+
+#define S_REQBURSTFREQUENCY 1
+#define M_REQBURSTFREQUENCY 0xfU
+#define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY)
+#define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY)
+
+#define S_ENABLEVC1 0
+#define V_ENABLEVC1(x) ((x) << S_ENABLEVC1)
+#define F_ENABLEVC1 V_ENABLEVC1(1U)
+
#define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
#define S_CPM0 30
@@ -3259,7 +6292,204 @@
#define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7)
#define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
+#define A_PCIE_PERR_GROUP 0x59d0
+
+#define S_MST_DATAPATHPERR 25
+#define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR)
+#define F_MST_DATAPATHPERR V_MST_DATAPATHPERR(1U)
+
+#define S_MST_RSPRDQPERR 24
+#define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR)
+#define F_MST_RSPRDQPERR V_MST_RSPRDQPERR(1U)
+
+#define S_IP_RXPERR 23
+#define V_IP_RXPERR(x) ((x) << S_IP_RXPERR)
+#define F_IP_RXPERR V_IP_RXPERR(1U)
+
+#define S_IP_BACKTXPERR 22
+#define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR)
+#define F_IP_BACKTXPERR V_IP_BACKTXPERR(1U)
+
+#define S_IP_FRONTTXPERR 21
+#define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR)
+#define F_IP_FRONTTXPERR V_IP_FRONTTXPERR(1U)
+
+#define S_TRGT1_FIDLKUPHDRPERR 20
+#define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR)
+#define F_TRGT1_FIDLKUPHDRPERR V_TRGT1_FIDLKUPHDRPERR(1U)
+
+#define S_TRGT1_ALINDDATAPERR 19
+#define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR)
+#define F_TRGT1_ALINDDATAPERR V_TRGT1_ALINDDATAPERR(1U)
+
+#define S_TRGT1_UNALINDATAPERR 18
+#define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR)
+#define F_TRGT1_UNALINDATAPERR V_TRGT1_UNALINDATAPERR(1U)
+
+#define S_TRGT1_REQDATAPERR 17
+#define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR)
+#define F_TRGT1_REQDATAPERR V_TRGT1_REQDATAPERR(1U)
+
+#define S_TRGT1_REQHDRPERR 16
+#define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR)
+#define F_TRGT1_REQHDRPERR V_TRGT1_REQHDRPERR(1U)
+
+#define S_IPRXDATA_VC1PERR 15
+#define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR)
+#define F_IPRXDATA_VC1PERR V_IPRXDATA_VC1PERR(1U)
+
+#define S_IPRXDATA_VC0PERR 14
+#define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR)
+#define F_IPRXDATA_VC0PERR V_IPRXDATA_VC0PERR(1U)
+
+#define S_IPRXHDR_VC1PERR 13
+#define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR)
+#define F_IPRXHDR_VC1PERR V_IPRXHDR_VC1PERR(1U)
+
+#define S_IPRXHDR_VC0PERR 12
+#define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR)
+#define F_IPRXHDR_VC0PERR V_IPRXHDR_VC0PERR(1U)
+
+#define S_MA_RSPDATAPERR 11
+#define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR)
+#define F_MA_RSPDATAPERR V_MA_RSPDATAPERR(1U)
+
+#define S_MA_CPLTAGQPERR 10
+#define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR)
+#define F_MA_CPLTAGQPERR V_MA_CPLTAGQPERR(1U)
+
+#define S_MA_REQTAGQPERR 9
+#define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR)
+#define F_MA_REQTAGQPERR V_MA_REQTAGQPERR(1U)
+
+#define S_PIOREQ_BAR2CTLPERR 8
+#define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR)
+#define F_PIOREQ_BAR2CTLPERR V_PIOREQ_BAR2CTLPERR(1U)
+
+#define S_PIOREQ_MEMCTLPERR 7
+#define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR)
+#define F_PIOREQ_MEMCTLPERR V_PIOREQ_MEMCTLPERR(1U)
+
+#define S_PIOREQ_PLMCTLPERR 6
+#define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR)
+#define F_PIOREQ_PLMCTLPERR V_PIOREQ_PLMCTLPERR(1U)
+
+#define S_PIOREQ_BAR2DATAPERR 5
+#define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR)
+#define F_PIOREQ_BAR2DATAPERR V_PIOREQ_BAR2DATAPERR(1U)
+
+#define S_PIOREQ_MEMDATAPERR 4
+#define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR)
+#define F_PIOREQ_MEMDATAPERR V_PIOREQ_MEMDATAPERR(1U)
+
+#define S_PIOREQ_PLMDATAPERR 3
+#define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR)
+#define F_PIOREQ_PLMDATAPERR V_PIOREQ_PLMDATAPERR(1U)
+
+#define S_PIOCPL_CTLPERR 2
+#define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR)
+#define F_PIOCPL_CTLPERR V_PIOCPL_CTLPERR(1U)
+
+#define S_PIOCPL_DATAPERR 1
+#define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR)
+#define F_PIOCPL_DATAPERR V_PIOCPL_DATAPERR(1U)
+
+#define S_PIOCPL_PLMRSPPERR 0
+#define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR)
+#define F_PIOCPL_PLMRSPPERR V_PIOCPL_PLMRSPPERR(1U)
+
#define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
+#define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
+
+#define S_CPLSTATUSINTEN 12
+#define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN)
+#define F_CPLSTATUSINTEN V_CPLSTATUSINTEN(1U)
+
+#define S_REQTIMEOUTINTEN 11
+#define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN)
+#define F_REQTIMEOUTINTEN V_REQTIMEOUTINTEN(1U)
+
+#define S_DISABLEDINTEN 10
+#define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN)
+#define F_DISABLEDINTEN V_DISABLEDINTEN(1U)
+
+#define S_RSPDROPFLRINTEN 9
+#define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN)
+#define F_RSPDROPFLRINTEN V_RSPDROPFLRINTEN(1U)
+
+#define S_REQUNDERFLRINTEN 8
+#define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN)
+#define F_REQUNDERFLRINTEN V_REQUNDERFLRINTEN(1U)
+
+#define S_CPLSTATUSLOGEN 4
+#define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN)
+#define F_CPLSTATUSLOGEN V_CPLSTATUSLOGEN(1U)
+
+#define S_TIMEOUTLOGEN 3
+#define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN)
+#define F_TIMEOUTLOGEN V_TIMEOUTLOGEN(1U)
+
+#define S_DISABLEDLOGEN 2
+#define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN)
+#define F_DISABLEDLOGEN V_DISABLEDLOGEN(1U)
+
+#define S_RSPDROPFLRLOGEN 1
+#define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN)
+#define F_RSPDROPFLRLOGEN V_RSPDROPFLRLOGEN(1U)
+
+#define S_REQUNDERFLRLOGEN 0
+#define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN)
+#define F_REQUNDERFLRLOGEN V_REQUNDERFLRLOGEN(1U)
+
+#define A_PCIE_RSP_ERR_LOG1 0x59d8
+
+#define S_REQTAG 25
+#define M_REQTAG 0x7fU
+#define V_REQTAG(x) ((x) << S_REQTAG)
+#define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG)
+
+#define S_CID 22
+#define M_CID 0x7U
+#define V_CID(x) ((x) << S_CID)
+#define G_CID(x) (((x) >> S_CID) & M_CID)
+
+#define S_CHNUM 19
+#define M_CHNUM 0x7U
+#define V_CHNUM(x) ((x) << S_CHNUM)
+#define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM)
+
+#define S_BYTELEN 6
+#define M_BYTELEN 0x1fffU
+#define V_BYTELEN(x) ((x) << S_BYTELEN)
+#define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN)
+
+#define S_REASON 3
+#define M_REASON 0x7U
+#define V_REASON(x) ((x) << S_REASON)
+#define G_REASON(x) (((x) >> S_REASON) & M_REASON)
+
+#define S_CPLSTATUS 0
+#define M_CPLSTATUS 0x7U
+#define V_CPLSTATUS(x) ((x) << S_CPLSTATUS)
+#define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS)
+
+#define A_PCIE_RSP_ERR_LOG2 0x59dc
+
+#define S_LOGVALID 31
+#define V_LOGVALID(x) ((x) << S_LOGVALID)
+#define F_LOGVALID V_LOGVALID(1U)
+
+#define S_ADDR10B 8
+#define M_ADDR10B 0x3ffU
+#define V_ADDR10B(x) ((x) << S_ADDR10B)
+#define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B)
+
+#define S_REQVFID 0
+#define M_REQVFID 0xffU
+#define V_REQVFID(x) ((x) << S_REQVFID)
+#define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID)
+
+#define A_PCIE_CHANGESET 0x59fc
#define A_PCIE_REVISION 0x5a00
#define A_PCIE_PDEBUG_INDEX 0x5a04
@@ -3402,6 +6632,12 @@
#define A_PCIE_BUS_MST_STAT_2 0x5a68
#define A_PCIE_BUS_MST_STAT_3 0x5a6c
#define A_PCIE_BUS_MST_STAT_4 0x5a70
+
+#define S_BUSMST_135_128 0
+#define M_BUSMST_135_128 0xffU
+#define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128)
+#define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128)
+
#define A_PCIE_BUS_MST_STAT_5 0x5a74
#define A_PCIE_BUS_MST_STAT_6 0x5a78
#define A_PCIE_BUS_MST_STAT_7 0x5a7c
@@ -3410,9 +6646,53 @@
#define A_PCIE_RSP_ERR_STAT_2 0x5a88
#define A_PCIE_RSP_ERR_STAT_3 0x5a8c
#define A_PCIE_RSP_ERR_STAT_4 0x5a90
+
+#define S_RSPERR_135_128 0
+#define M_RSPERR_135_128 0xffU
+#define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128)
+#define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128)
+
#define A_PCIE_RSP_ERR_STAT_5 0x5a94
+#define A_PCIE_DBI_TIMEOUT_CTL 0x5a94
+
+#define S_DBI_TIMER 0
+#define M_DBI_TIMER 0xffffU
+#define V_DBI_TIMER(x) ((x) << S_DBI_TIMER)
+#define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER)
+
#define A_PCIE_RSP_ERR_STAT_6 0x5a98
+#define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98
#define A_PCIE_RSP_ERR_STAT_7 0x5a9c
+#define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c
+
+#define S_SOURCE 16
+#define M_SOURCE 0x3U
+#define V_SOURCE(x) ((x) << S_SOURCE)
+#define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE)
+
+#define S_DBI_WRITE 12
+#define M_DBI_WRITE 0xfU
+#define V_DBI_WRITE(x) ((x) << S_DBI_WRITE)
+#define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE)
+
+#define S_DBI_CS2 11
+#define V_DBI_CS2(x) ((x) << S_DBI_CS2)
+#define F_DBI_CS2 V_DBI_CS2(1U)
+
+#define S_DBI_PF 8
+#define M_DBI_PF 0x7U
+#define V_DBI_PF(x) ((x) << S_DBI_PF)
+#define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF)
+
+#define S_PL_TOVFVLD 7
+#define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD)
+#define F_PL_TOVFVLD V_PL_TOVFVLD(1U)
+
+#define S_PL_TOVF 0
+#define M_PL_TOVF 0x7fU
+#define V_PL_TOVF(x) ((x) << S_PL_TOVF)
+#define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF)
+
#define A_PCIE_MSI_EN_0 0x5aa0
#define A_PCIE_MSI_EN_1 0x5aa4
#define A_PCIE_MSI_EN_2 0x5aa8
@@ -3446,6 +6726,388 @@
#define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ)
#define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ)
+#define A_PCIE_PB_CTL 0x5b94
+
+#define S_PB_SEL 16
+#define M_PB_SEL 0xffU
+#define V_PB_SEL(x) ((x) << S_PB_SEL)
+#define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL)
+
+#define S_PB_SELREG 8
+#define M_PB_SELREG 0xffU
+#define V_PB_SELREG(x) ((x) << S_PB_SELREG)
+#define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG)
+
+#define S_PB_FUNC 0
+#define M_PB_FUNC 0x7U
+#define V_PB_FUNC(x) ((x) << S_PB_FUNC)
+#define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC)
+
+#define A_PCIE_PB_DATA 0x5b98
+#define A_PCIE_CUR_LINK 0x5b9c
+
+#define S_CFGINITCOEFFDONESEEN 22
+#define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN)
+#define F_CFGINITCOEFFDONESEEN V_CFGINITCOEFFDONESEEN(1U)
+
+#define S_CFGINITCOEFFDONE 21
+#define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE)
+#define F_CFGINITCOEFFDONE V_CFGINITCOEFFDONE(1U)
+
+#define S_XMLH_LINK_UP 20
+#define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP)
+#define F_XMLH_LINK_UP V_XMLH_LINK_UP(1U)
+
+#define S_PM_LINKST_IN_L0S 19
+#define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S)
+#define F_PM_LINKST_IN_L0S V_PM_LINKST_IN_L0S(1U)
+
+#define S_PM_LINKST_IN_L1 18
+#define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1)
+#define F_PM_LINKST_IN_L1 V_PM_LINKST_IN_L1(1U)
+
+#define S_PM_LINKST_IN_L2 17
+#define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2)
+#define F_PM_LINKST_IN_L2 V_PM_LINKST_IN_L2(1U)
+
+#define S_PM_LINKST_L2_EXIT 16
+#define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT)
+#define F_PM_LINKST_L2_EXIT V_PM_LINKST_L2_EXIT(1U)
+
+#define S_XMLH_IN_RL0S 15
+#define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S)
+#define F_XMLH_IN_RL0S V_XMLH_IN_RL0S(1U)
+
+#define S_XMLH_LTSSM_STATE_RCVRY_EQ 14
+#define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ)
+#define F_XMLH_LTSSM_STATE_RCVRY_EQ V_XMLH_LTSSM_STATE_RCVRY_EQ(1U)
+
+#define S_NEGOTIATEDWIDTH 8
+#define M_NEGOTIATEDWIDTH 0x3fU
+#define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH)
+#define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH)
+
+#define S_ACTIVELANES 0
+#define M_ACTIVELANES 0xffU
+#define V_ACTIVELANES(x) ((x) << S_ACTIVELANES)
+#define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES)
+
+#define A_PCIE_PHY_REQRXPWR 0x5ba0
+
+#define S_LNH_RXSTATEDONE 31
+#define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE)
+#define F_LNH_RXSTATEDONE V_LNH_RXSTATEDONE(1U)
+
+#define S_LNH_RXSTATEREQ 30
+#define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ)
+#define F_LNH_RXSTATEREQ V_LNH_RXSTATEREQ(1U)
+
+#define S_LNH_RXPWRSTATE 28
+#define M_LNH_RXPWRSTATE 0x3U
+#define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE)
+#define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE)
+
+#define S_LNG_RXSTATEDONE 27
+#define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE)
+#define F_LNG_RXSTATEDONE V_LNG_RXSTATEDONE(1U)
+
+#define S_LNG_RXSTATEREQ 26
+#define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ)
+#define F_LNG_RXSTATEREQ V_LNG_RXSTATEREQ(1U)
+
+#define S_LNG_RXPWRSTATE 24
+#define M_LNG_RXPWRSTATE 0x3U
+#define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE)
+#define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE)
+
+#define S_LNF_RXSTATEDONE 23
+#define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE)
+#define F_LNF_RXSTATEDONE V_LNF_RXSTATEDONE(1U)
+
+#define S_LNF_RXSTATEREQ 22
+#define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ)
+#define F_LNF_RXSTATEREQ V_LNF_RXSTATEREQ(1U)
+
+#define S_LNF_RXPWRSTATE 20
+#define M_LNF_RXPWRSTATE 0x3U
+#define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE)
+#define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE)
+
+#define S_LNE_RXSTATEDONE 19
+#define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE)
+#define F_LNE_RXSTATEDONE V_LNE_RXSTATEDONE(1U)
+
+#define S_LNE_RXSTATEREQ 18
+#define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ)
+#define F_LNE_RXSTATEREQ V_LNE_RXSTATEREQ(1U)
+
+#define S_LNE_RXPWRSTATE 16
+#define M_LNE_RXPWRSTATE 0x3U
+#define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE)
+#define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE)
+
+#define S_LND_RXSTATEDONE 15
+#define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE)
+#define F_LND_RXSTATEDONE V_LND_RXSTATEDONE(1U)
+
+#define S_LND_RXSTATEREQ 14
+#define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ)
+#define F_LND_RXSTATEREQ V_LND_RXSTATEREQ(1U)
+
+#define S_LND_RXPWRSTATE 12
+#define M_LND_RXPWRSTATE 0x3U
+#define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE)
+#define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE)
+
+#define S_LNC_RXSTATEDONE 11
+#define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE)
+#define F_LNC_RXSTATEDONE V_LNC_RXSTATEDONE(1U)
+
+#define S_LNC_RXSTATEREQ 10
+#define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ)
+#define F_LNC_RXSTATEREQ V_LNC_RXSTATEREQ(1U)
+
+#define S_LNC_RXPWRSTATE 8
+#define M_LNC_RXPWRSTATE 0x3U
+#define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE)
+#define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE)
+
+#define S_LNB_RXSTATEDONE 7
+#define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE)
+#define F_LNB_RXSTATEDONE V_LNB_RXSTATEDONE(1U)
+
+#define S_LNB_RXSTATEREQ 6
+#define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ)
+#define F_LNB_RXSTATEREQ V_LNB_RXSTATEREQ(1U)
+
+#define S_LNB_RXPWRSTATE 4
+#define M_LNB_RXPWRSTATE 0x3U
+#define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE)
+#define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE)
+
+#define S_LNA_RXSTATEDONE 3
+#define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE)
+#define F_LNA_RXSTATEDONE V_LNA_RXSTATEDONE(1U)
+
+#define S_LNA_RXSTATEREQ 2
+#define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ)
+#define F_LNA_RXSTATEREQ V_LNA_RXSTATEREQ(1U)
+
+#define S_LNA_RXPWRSTATE 0
+#define M_LNA_RXPWRSTATE 0x3U
+#define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE)
+#define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE)
+
+#define A_PCIE_PHY_CURRXPWR 0x5ba4
+#define A_PCIE_PHY_GEN3_AE0 0x5ba8
+
+#define S_LND_STAT 28
+#define M_LND_STAT 0x7U
+#define V_LND_STAT(x) ((x) << S_LND_STAT)
+#define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT)
+
+#define S_LND_CMD 24
+#define M_LND_CMD 0x7U
+#define V_LND_CMD(x) ((x) << S_LND_CMD)
+#define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD)
+
+#define S_LNC_STAT 20
+#define M_LNC_STAT 0x7U
+#define V_LNC_STAT(x) ((x) << S_LNC_STAT)
+#define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT)
+
+#define S_LNC_CMD 16
+#define M_LNC_CMD 0x7U
+#define V_LNC_CMD(x) ((x) << S_LNC_CMD)
+#define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD)
+
+#define S_LNB_STAT 12
+#define M_LNB_STAT 0x7U
+#define V_LNB_STAT(x) ((x) << S_LNB_STAT)
+#define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT)
+
+#define S_LNB_CMD 8
+#define M_LNB_CMD 0x7U
+#define V_LNB_CMD(x) ((x) << S_LNB_CMD)
+#define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD)
+
+#define S_LNA_STAT 4
+#define M_LNA_STAT 0x7U
+#define V_LNA_STAT(x) ((x) << S_LNA_STAT)
+#define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT)
+
+#define S_LNA_CMD 0
+#define M_LNA_CMD 0x7U
+#define V_LNA_CMD(x) ((x) << S_LNA_CMD)
+#define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD)
+
+#define A_PCIE_PHY_GEN3_AE1 0x5bac
+
+#define S_LNH_STAT 28
+#define M_LNH_STAT 0x7U
+#define V_LNH_STAT(x) ((x) << S_LNH_STAT)
+#define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT)
+
+#define S_LNH_CMD 24
+#define M_LNH_CMD 0x7U
+#define V_LNH_CMD(x) ((x) << S_LNH_CMD)
+#define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD)
+
+#define S_LNG_STAT 20
+#define M_LNG_STAT 0x7U
+#define V_LNG_STAT(x) ((x) << S_LNG_STAT)
+#define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT)
+
+#define S_LNG_CMD 16
+#define M_LNG_CMD 0x7U
+#define V_LNG_CMD(x) ((x) << S_LNG_CMD)
+#define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD)
+
+#define S_LNF_STAT 12
+#define M_LNF_STAT 0x7U
+#define V_LNF_STAT(x) ((x) << S_LNF_STAT)
+#define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT)
+
+#define S_LNF_CMD 8
+#define M_LNF_CMD 0x7U
+#define V_LNF_CMD(x) ((x) << S_LNF_CMD)
+#define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD)
+
+#define S_LNE_STAT 4
+#define M_LNE_STAT 0x7U
+#define V_LNE_STAT(x) ((x) << S_LNE_STAT)
+#define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT)
+
+#define S_LNE_CMD 0
+#define M_LNE_CMD 0x7U
+#define V_LNE_CMD(x) ((x) << S_LNE_CMD)
+#define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD)
+
+#define A_PCIE_PHY_FS_LF0 0x5bb0
+
+#define S_LANE1LF 24
+#define M_LANE1LF 0x3fU
+#define V_LANE1LF(x) ((x) << S_LANE1LF)
+#define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF)
+
+#define S_LANE1FS 16
+#define M_LANE1FS 0x3fU
+#define V_LANE1FS(x) ((x) << S_LANE1FS)
+#define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS)
+
+#define S_LANE0LF 8
+#define M_LANE0LF 0x3fU
+#define V_LANE0LF(x) ((x) << S_LANE0LF)
+#define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF)
+
+#define S_LANE0FS 0
+#define M_LANE0FS 0x3fU
+#define V_LANE0FS(x) ((x) << S_LANE0FS)
+#define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS)
+
+#define A_PCIE_PHY_FS_LF1 0x5bb4
+
+#define S_LANE3LF 24
+#define M_LANE3LF 0x3fU
+#define V_LANE3LF(x) ((x) << S_LANE3LF)
+#define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF)
+
+#define S_LANE3FS 16
+#define M_LANE3FS 0x3fU
+#define V_LANE3FS(x) ((x) << S_LANE3FS)
+#define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS)
+
+#define S_LANE2LF 8
+#define M_LANE2LF 0x3fU
+#define V_LANE2LF(x) ((x) << S_LANE2LF)
+#define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF)
+
+#define S_LANE2FS 0
+#define M_LANE2FS 0x3fU
+#define V_LANE2FS(x) ((x) << S_LANE2FS)
+#define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS)
+
+#define A_PCIE_PHY_FS_LF2 0x5bb8
+
+#define S_LANE5LF 24
+#define M_LANE5LF 0x3fU
+#define V_LANE5LF(x) ((x) << S_LANE5LF)
+#define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF)
+
+#define S_LANE5FS 16
+#define M_LANE5FS 0x3fU
+#define V_LANE5FS(x) ((x) << S_LANE5FS)
+#define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS)
+
+#define S_LANE4LF 8
+#define M_LANE4LF 0x3fU
+#define V_LANE4LF(x) ((x) << S_LANE4LF)
+#define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF)
+
+#define S_LANE4FS 0
+#define M_LANE4FS 0x3fU
+#define V_LANE4FS(x) ((x) << S_LANE4FS)
+#define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS)
+
+#define A_PCIE_PHY_FS_LF3 0x5bbc
+
+#define S_LANE7LF 24
+#define M_LANE7LF 0x3fU
+#define V_LANE7LF(x) ((x) << S_LANE7LF)
+#define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF)
+
+#define S_LANE7FS 16
+#define M_LANE7FS 0x3fU
+#define V_LANE7FS(x) ((x) << S_LANE7FS)
+#define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS)
+
+#define S_LANE6LF 8
+#define M_LANE6LF 0x3fU
+#define V_LANE6LF(x) ((x) << S_LANE6LF)
+#define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF)
+
+#define S_LANE6FS 0
+#define M_LANE6FS 0x3fU
+#define V_LANE6FS(x) ((x) << S_LANE6FS)
+#define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS)
+
+#define A_PCIE_PHY_PRESET_REQ 0x5bc0
+
+#define S_COEFFDONE 16
+#define V_COEFFDONE(x) ((x) << S_COEFFDONE)
+#define F_COEFFDONE V_COEFFDONE(1U)
+
+#define S_COEFFLANE 8
+#define M_COEFFLANE 0x7U
+#define V_COEFFLANE(x) ((x) << S_COEFFLANE)
+#define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE)
+
+#define S_COEFFSTART 0
+#define V_COEFFSTART(x) ((x) << S_COEFFSTART)
+#define F_COEFFSTART V_COEFFSTART(1U)
+
+#define A_PCIE_PHY_PRESET_COEFF 0x5bc4
+
+#define S_COEFF 0
+#define M_COEFF 0x3ffffU
+#define V_COEFF(x) ((x) << S_COEFF)
+#define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF)
+
+#define A_PCIE_PHY_INDIR_REQ 0x5bf0
+
+#define S_PHYENABLE 31
+#define V_PHYENABLE(x) ((x) << S_PHYENABLE)
+#define F_PHYENABLE V_PHYENABLE(1U)
+
+#define S_PCIE_PHY_REGADDR 0
+#define M_PCIE_PHY_REGADDR 0xffffU
+#define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR)
+#define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR)
+
+#define A_PCIE_PHY_INDIR_DATA 0x5bf4
+#define A_PCIE_STATIC_SPARE1 0x5bf8
+#define A_PCIE_STATIC_SPARE2 0x5bfc
+
/* registers for module DBG */
#define DBG_BASE_ADDR 0x6000
@@ -3490,6 +7152,11 @@
#define A_DBG_DBG1_CFG 0x6008
#define A_DBG_DBG1_EN 0x600c
+
+#define S_CLK_EN_ON_DBG1 20
+#define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1)
+#define F_CLK_EN_ON_DBG1 V_CLK_EN_ON_DBG1(1U)
+
#define A_DBG_GPIO_EN 0x6010
#define S_GPIO15_OEN 31
@@ -3856,6 +7523,22 @@
#define V_GPIO0(x) ((x) << S_GPIO0)
#define F_GPIO0 V_GPIO0(1U)
+#define S_GPIO19 29
+#define V_GPIO19(x) ((x) << S_GPIO19)
+#define F_GPIO19 V_GPIO19(1U)
+
+#define S_GPIO18 28
+#define V_GPIO18(x) ((x) << S_GPIO18)
+#define F_GPIO18 V_GPIO18(1U)
+
+#define S_GPIO17 27
+#define V_GPIO17(x) ((x) << S_GPIO17)
+#define F_GPIO17 V_GPIO17(1U)
+
+#define S_GPIO16 26
+#define V_GPIO16(x) ((x) << S_GPIO16)
+#define F_GPIO16 V_GPIO16(1U)
+
#define A_DBG_INT_CAUSE 0x601c
#define S_IBM_FDL_FAIL_INT_CAUSE 25
@@ -4029,6 +7712,22 @@
#define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
#define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U)
+#define S_GPIO19_ACT_LOW 25
+#define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW)
+#define F_GPIO19_ACT_LOW V_GPIO19_ACT_LOW(1U)
+
+#define S_GPIO18_ACT_LOW 24
+#define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW)
+#define F_GPIO18_ACT_LOW V_GPIO18_ACT_LOW(1U)
+
+#define S_GPIO17_ACT_LOW 23
+#define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW)
+#define F_GPIO17_ACT_LOW V_GPIO17_ACT_LOW(1U)
+
+#define S_GPIO16_ACT_LOW 22
+#define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW)
+#define F_GPIO16_ACT_LOW V_GPIO16_ACT_LOW(1U)
+
#define A_DBG_EFUSE_BYTE0_3 0x6034
#define A_DBG_EFUSE_BYTE4_7 0x6038
#define A_DBG_EFUSE_BYTE8_11 0x603c
@@ -4294,6 +7993,11 @@
#define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL)
#define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL)
+#define S_T5_P_OCLK_MUXSEL 13
+#define M_T5_P_OCLK_MUXSEL 0xfU
+#define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL)
+#define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL)
+
#define A_DBG_TRACE0_CONF_COMPREG0 0x6060
#define A_DBG_TRACE0_CONF_COMPREG1 0x6064
#define A_DBG_TRACE1_CONF_COMPREG0 0x6068
@@ -4381,6 +8085,513 @@
#define A_DBG_TRACE0_DATA_OUT 0x6094
#define A_DBG_TRACE1_DATA_OUT 0x6098
+#define A_DBG_FUSE_SENSE_DONE 0x609c
+
+#define S_STATIC_JTAG_VERSIONNR 5
+#define M_STATIC_JTAG_VERSIONNR 0xfU
+#define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR)
+#define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR)
+
+#define S_UNQ0 1
+#define M_UNQ0 0xfU
+#define V_UNQ0(x) ((x) << S_UNQ0)
+#define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0)
+
+#define S_FUSE_DONE_SENSE 0
+#define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE)
+#define F_FUSE_DONE_SENSE V_FUSE_DONE_SENSE(1U)
+
+#define A_DBG_TVSENSE_EN 0x60a8
+
+#define S_MCIMPED1_OUT 29
+#define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT)
+#define F_MCIMPED1_OUT V_MCIMPED1_OUT(1U)
+
+#define S_MCIMPED2_OUT 28
+#define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT)
+#define F_MCIMPED2_OUT V_MCIMPED2_OUT(1U)
+
+#define S_TVSENSE_SNSOUT 17
+#define M_TVSENSE_SNSOUT 0x1ffU
+#define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT)
+#define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT)
+
+#define S_TVSENSE_OUTPUTVALID 16
+#define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID)
+#define F_TVSENSE_OUTPUTVALID V_TVSENSE_OUTPUTVALID(1U)
+
+#define S_TVSENSE_SLEEP 10
+#define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP)
+#define F_TVSENSE_SLEEP V_TVSENSE_SLEEP(1U)
+
+#define S_TVSENSE_SENSV 9
+#define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV)
+#define F_TVSENSE_SENSV V_TVSENSE_SENSV(1U)
+
+#define S_TVSENSE_RST 8
+#define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST)
+#define F_TVSENSE_RST V_TVSENSE_RST(1U)
+
+#define S_TVSENSE_RATIO 0
+#define M_TVSENSE_RATIO 0xffU
+#define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO)
+#define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO)
+
+#define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
+#define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
+#define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
+
+#define S_DBG_FEENABLE 29
+#define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE)
+#define F_DBG_FEENABLE V_DBG_FEENABLE(1U)
+
+#define S_DBG_FEF 23
+#define M_DBG_FEF 0x3fU
+#define V_DBG_FEF(x) ((x) << S_DBG_FEF)
+#define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF)
+
+#define S_DBG_FEMIMICN 22
+#define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN)
+#define F_DBG_FEMIMICN V_DBG_FEMIMICN(1U)
+
+#define S_DBG_FEGATEC 21
+#define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC)
+#define F_DBG_FEGATEC V_DBG_FEGATEC(1U)
+
+#define S_DBG_FEPROGP 20
+#define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP)
+#define F_DBG_FEPROGP V_DBG_FEPROGP(1U)
+
+#define S_DBG_FEREADCLK 19
+#define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK)
+#define F_DBG_FEREADCLK V_DBG_FEREADCLK(1U)
+
+#define S_DBG_FERSEL 3
+#define M_DBG_FERSEL 0xffffU
+#define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL)
+#define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL)
+
+#define S_DBG_FETIME 0
+#define M_DBG_FETIME 0x7U
+#define V_DBG_FETIME(x) ((x) << S_DBG_FETIME)
+#define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8
+
+#define S_T5_STATIC_M_PLL_MULTFRAC 8
+#define M_T5_STATIC_M_PLL_MULTFRAC 0xffffffU
+#define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC)
+#define G_T5_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC)
+
+#define S_T5_STATIC_M_PLL_FFSLEWRATE 0
+#define M_T5_STATIC_M_PLL_FFSLEWRATE 0xffU
+#define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE)
+#define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
+
+#define S_T5_STATIC_M_PLL_DCO_BYPASS 23
+#define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS)
+#define F_T5_STATIC_M_PLL_DCO_BYPASS V_T5_STATIC_M_PLL_DCO_BYPASS(1U)
+
+#define S_T5_STATIC_M_PLL_SDORDER 21
+#define M_T5_STATIC_M_PLL_SDORDER 0x3U
+#define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER)
+#define G_T5_STATIC_M_PLL_SDORDER(x) (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER)
+
+#define S_T5_STATIC_M_PLL_FFENABLE 20
+#define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE)
+#define F_T5_STATIC_M_PLL_FFENABLE V_T5_STATIC_M_PLL_FFENABLE(1U)
+
+#define S_T5_STATIC_M_PLL_STOPCLKB 19
+#define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB)
+#define F_T5_STATIC_M_PLL_STOPCLKB V_T5_STATIC_M_PLL_STOPCLKB(1U)
+
+#define S_T5_STATIC_M_PLL_STOPCLKA 18
+#define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA)
+#define F_T5_STATIC_M_PLL_STOPCLKA V_T5_STATIC_M_PLL_STOPCLKA(1U)
+
+#define S_T5_STATIC_M_PLL_SLEEP 17
+#define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP)
+#define F_T5_STATIC_M_PLL_SLEEP V_T5_STATIC_M_PLL_SLEEP(1U)
+
+#define S_T5_STATIC_M_PLL_BYPASS 16
+#define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS)
+#define F_T5_STATIC_M_PLL_BYPASS V_T5_STATIC_M_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_M_PLL_LOCKTUNE 0
+#define M_T5_STATIC_M_PLL_LOCKTUNE 0xffffU
+#define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE)
+#define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
+
+#define S_T5_STATIC_M_PLL_MULTPRE 30
+#define M_T5_STATIC_M_PLL_MULTPRE 0x3U
+#define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE)
+#define G_T5_STATIC_M_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE)
+
+#define S_T5_STATIC_M_PLL_LOCKSEL 28
+#define M_T5_STATIC_M_PLL_LOCKSEL 0x3U
+#define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL)
+#define G_T5_STATIC_M_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL)
+
+#define S_T5_STATIC_M_PLL_FFTUNE 12
+#define M_T5_STATIC_M_PLL_FFTUNE 0xffffU
+#define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE)
+#define G_T5_STATIC_M_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE)
+
+#define S_T5_STATIC_M_PLL_RANGEPRE 10
+#define M_T5_STATIC_M_PLL_RANGEPRE 0x3U
+#define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE)
+#define G_T5_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE)
+
+#define S_T5_STATIC_M_PLL_RANGEB 5
+#define M_T5_STATIC_M_PLL_RANGEB 0x1fU
+#define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB)
+#define G_T5_STATIC_M_PLL_RANGEB(x) (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB)
+
+#define S_T5_STATIC_M_PLL_RANGEA 0
+#define M_T5_STATIC_M_PLL_RANGEA 0x1fU
+#define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA)
+#define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
+#define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
+
+#define S_T5_STATIC_M_PLL_VCVTUNE 24
+#define M_T5_STATIC_M_PLL_VCVTUNE 0x7U
+#define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE)
+#define G_T5_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE)
+
+#define S_T5_STATIC_M_PLL_RESET 23
+#define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET)
+#define F_T5_STATIC_M_PLL_RESET V_T5_STATIC_M_PLL_RESET(1U)
+
+#define S_T5_STATIC_MPLL_REFCLK_SEL 22
+#define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL)
+#define F_T5_STATIC_MPLL_REFCLK_SEL V_T5_STATIC_MPLL_REFCLK_SEL(1U)
+
+#define S_T5_STATIC_M_PLL_LFTUNE_32_40 13
+#define M_T5_STATIC_M_PLL_LFTUNE_32_40 0x1ffU
+#define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40)
+#define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & M_T5_STATIC_M_PLL_LFTUNE_32_40)
+
+#define S_T5_STATIC_M_PLL_PREDIV 8
+#define M_T5_STATIC_M_PLL_PREDIV 0x1fU
+#define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV)
+#define G_T5_STATIC_M_PLL_PREDIV(x) (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV)
+
+#define S_T5_STATIC_M_PLL_MULT 0
+#define M_T5_STATIC_M_PLL_MULT 0xffU
+#define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT)
+#define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
+
+#define S_T5_STATIC_PHY0RECRST_ 5
+#define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_)
+#define F_T5_STATIC_PHY0RECRST_ V_T5_STATIC_PHY0RECRST_(1U)
+
+#define S_T5_STATIC_PHY1RECRST_ 4
+#define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_)
+#define F_T5_STATIC_PHY1RECRST_ V_T5_STATIC_PHY1RECRST_(1U)
+
+#define S_T5_STATIC_SWMC0RST_ 3
+#define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_)
+#define F_T5_STATIC_SWMC0RST_ V_T5_STATIC_SWMC0RST_(1U)
+
+#define S_T5_STATIC_SWMC0CFGRST_ 2
+#define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_)
+#define F_T5_STATIC_SWMC0CFGRST_ V_T5_STATIC_SWMC0CFGRST_(1U)
+
+#define S_T5_STATIC_SWMC1RST_ 1
+#define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_)
+#define F_T5_STATIC_SWMC1RST_ V_T5_STATIC_SWMC1RST_(1U)
+
+#define S_T5_STATIC_SWMC1CFGRST_ 0
+#define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_)
+#define F_T5_STATIC_SWMC1CFGRST_ V_T5_STATIC_SWMC1CFGRST_(1U)
+
+#define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
+
+#define S_T5_STATIC_C_PLL_MULTFRAC 8
+#define M_T5_STATIC_C_PLL_MULTFRAC 0xffffffU
+#define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC)
+#define G_T5_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC)
+
+#define S_T5_STATIC_C_PLL_FFSLEWRATE 0
+#define M_T5_STATIC_C_PLL_FFSLEWRATE 0xffU
+#define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE)
+#define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE)
+
+#define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
+
+#define S_T5_STATIC_C_PLL_DCO_BYPASS 23
+#define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS)
+#define F_T5_STATIC_C_PLL_DCO_BYPASS V_T5_STATIC_C_PLL_DCO_BYPASS(1U)
+
+#define S_T5_STATIC_C_PLL_SDORDER 21
+#define M_T5_STATIC_C_PLL_SDORDER 0x3U
+#define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER)
+#define G_T5_STATIC_C_PLL_SDORDER(x) (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER)
+
+#define S_T5_STATIC_C_PLL_FFENABLE 20
+#define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE)
+#define F_T5_STATIC_C_PLL_FFENABLE V_T5_STATIC_C_PLL_FFENABLE(1U)
+
+#define S_T5_STATIC_C_PLL_STOPCLKB 19
+#define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB)
+#define F_T5_STATIC_C_PLL_STOPCLKB V_T5_STATIC_C_PLL_STOPCLKB(1U)
+
+#define S_T5_STATIC_C_PLL_STOPCLKA 18
+#define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA)
+#define F_T5_STATIC_C_PLL_STOPCLKA V_T5_STATIC_C_PLL_STOPCLKA(1U)
+
+#define S_T5_STATIC_C_PLL_SLEEP 17
+#define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP)
+#define F_T5_STATIC_C_PLL_SLEEP V_T5_STATIC_C_PLL_SLEEP(1U)
+
+#define S_T5_STATIC_C_PLL_BYPASS 16
+#define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS)
+#define F_T5_STATIC_C_PLL_BYPASS V_T5_STATIC_C_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_C_PLL_LOCKTUNE 0
+#define M_T5_STATIC_C_PLL_LOCKTUNE 0xffffU
+#define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE)
+#define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE)
+
+#define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
+
+#define S_T5_STATIC_C_PLL_MULTPRE 30
+#define M_T5_STATIC_C_PLL_MULTPRE 0x3U
+#define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE)
+#define G_T5_STATIC_C_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE)
+
+#define S_T5_STATIC_C_PLL_LOCKSEL 28
+#define M_T5_STATIC_C_PLL_LOCKSEL 0x3U
+#define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL)
+#define G_T5_STATIC_C_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL)
+
+#define S_T5_STATIC_C_PLL_FFTUNE 12
+#define M_T5_STATIC_C_PLL_FFTUNE 0xffffU
+#define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE)
+#define G_T5_STATIC_C_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE)
+
+#define S_T5_STATIC_C_PLL_RANGEPRE 10
+#define M_T5_STATIC_C_PLL_RANGEPRE 0x3U
+#define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE)
+#define G_T5_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE)
+
+#define S_T5_STATIC_C_PLL_RANGEB 5
+#define M_T5_STATIC_C_PLL_RANGEB 0x1fU
+#define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB)
+#define G_T5_STATIC_C_PLL_RANGEB(x) (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB)
+
+#define S_T5_STATIC_C_PLL_RANGEA 0
+#define M_T5_STATIC_C_PLL_RANGEA 0x1fU
+#define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA)
+#define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA)
+
+#define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
+#define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
+
+#define S_T5_STATIC_C_PLL_VCVTUNE 22
+#define M_T5_STATIC_C_PLL_VCVTUNE 0x7U
+#define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE)
+#define G_T5_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE)
+
+#define S_T5_STATIC_C_PLL_LFTUNE_32_40 13
+#define M_T5_STATIC_C_PLL_LFTUNE_32_40 0x1ffU
+#define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40)
+#define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & M_T5_STATIC_C_PLL_LFTUNE_32_40)
+
+#define S_T5_STATIC_C_PLL_PREDIV 8
+#define M_T5_STATIC_C_PLL_PREDIV 0x1fU
+#define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV)
+#define G_T5_STATIC_C_PLL_PREDIV(x) (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV)
+
+#define S_T5_STATIC_C_PLL_MULT 0
+#define M_T5_STATIC_C_PLL_MULT 0xffU
+#define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT)
+#define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT)
+
+#define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
+
+#define S_T5_STATIC_U_PLL_MULTFRAC 8
+#define M_T5_STATIC_U_PLL_MULTFRAC 0xffffffU
+#define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC)
+#define G_T5_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC)
+
+#define S_T5_STATIC_U_PLL_FFSLEWRATE 0
+#define M_T5_STATIC_U_PLL_FFSLEWRATE 0xffU
+#define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE)
+#define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE)
+
+#define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
+
+#define S_T5_STATIC_U_PLL_DCO_BYPASS 23
+#define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS)
+#define F_T5_STATIC_U_PLL_DCO_BYPASS V_T5_STATIC_U_PLL_DCO_BYPASS(1U)
+
+#define S_T5_STATIC_U_PLL_SDORDER 21
+#define M_T5_STATIC_U_PLL_SDORDER 0x3U
+#define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER)
+#define G_T5_STATIC_U_PLL_SDORDER(x) (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER)
+
+#define S_T5_STATIC_U_PLL_FFENABLE 20
+#define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE)
+#define F_T5_STATIC_U_PLL_FFENABLE V_T5_STATIC_U_PLL_FFENABLE(1U)
+
+#define S_T5_STATIC_U_PLL_STOPCLKB 19
+#define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB)
+#define F_T5_STATIC_U_PLL_STOPCLKB V_T5_STATIC_U_PLL_STOPCLKB(1U)
+
+#define S_T5_STATIC_U_PLL_STOPCLKA 18
+#define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA)
+#define F_T5_STATIC_U_PLL_STOPCLKA V_T5_STATIC_U_PLL_STOPCLKA(1U)
+
+#define S_T5_STATIC_U_PLL_SLEEP 17
+#define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP)
+#define F_T5_STATIC_U_PLL_SLEEP V_T5_STATIC_U_PLL_SLEEP(1U)
+
+#define S_T5_STATIC_U_PLL_BYPASS 16
+#define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS)
+#define F_T5_STATIC_U_PLL_BYPASS V_T5_STATIC_U_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_U_PLL_LOCKTUNE 0
+#define M_T5_STATIC_U_PLL_LOCKTUNE 0xffffU
+#define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE)
+#define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE)
+
+#define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
+
+#define S_T5_STATIC_U_PLL_MULTPRE 30
+#define M_T5_STATIC_U_PLL_MULTPRE 0x3U
+#define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE)
+#define G_T5_STATIC_U_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE)
+
+#define S_T5_STATIC_U_PLL_LOCKSEL 28
+#define M_T5_STATIC_U_PLL_LOCKSEL 0x3U
+#define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL)
+#define G_T5_STATIC_U_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL)
+
+#define S_T5_STATIC_U_PLL_FFTUNE 12
+#define M_T5_STATIC_U_PLL_FFTUNE 0xffffU
+#define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE)
+#define G_T5_STATIC_U_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE)
+
+#define S_T5_STATIC_U_PLL_RANGEPRE 10
+#define M_T5_STATIC_U_PLL_RANGEPRE 0x3U
+#define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE)
+#define G_T5_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE)
+
+#define S_T5_STATIC_U_PLL_RANGEB 5
+#define M_T5_STATIC_U_PLL_RANGEB 0x1fU
+#define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB)
+#define G_T5_STATIC_U_PLL_RANGEB(x) (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB)
+
+#define S_T5_STATIC_U_PLL_RANGEA 0
+#define M_T5_STATIC_U_PLL_RANGEA 0x1fU
+#define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA)
+#define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA)
+
+#define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
+#define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
+
+#define S_T5_STATIC_U_PLL_VCVTUNE 22
+#define M_T5_STATIC_U_PLL_VCVTUNE 0x7U
+#define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE)
+#define G_T5_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE)
+
+#define S_T5_STATIC_U_PLL_LFTUNE_32_40 13
+#define M_T5_STATIC_U_PLL_LFTUNE_32_40 0x1ffU
+#define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40)
+#define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & M_T5_STATIC_U_PLL_LFTUNE_32_40)
+
+#define S_T5_STATIC_U_PLL_PREDIV 8
+#define M_T5_STATIC_U_PLL_PREDIV 0x1fU
+#define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV)
+#define G_T5_STATIC_U_PLL_PREDIV(x) (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV)
+
+#define S_T5_STATIC_U_PLL_MULT 0
+#define M_T5_STATIC_U_PLL_MULT 0xffU
+#define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT)
+#define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT)
+
+#define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
+
+#define S_T5_STATIC_KR_PLL_BYPASS 30
+#define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS)
+#define F_T5_STATIC_KR_PLL_BYPASS V_T5_STATIC_KR_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_KR_PLL_VBOOSTDIV 27
+#define M_T5_STATIC_KR_PLL_VBOOSTDIV 0x7U
+#define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV)
+#define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV)
+
+#define S_T5_STATIC_KR_PLL_CPISEL 24
+#define M_T5_STATIC_KR_PLL_CPISEL 0x7U
+#define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL)
+#define G_T5_STATIC_KR_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL)
+
+#define S_T5_STATIC_KR_PLL_CCALMETHOD 23
+#define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD)
+#define F_T5_STATIC_KR_PLL_CCALMETHOD V_T5_STATIC_KR_PLL_CCALMETHOD(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALLOAD 22
+#define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD)
+#define F_T5_STATIC_KR_PLL_CCALLOAD V_T5_STATIC_KR_PLL_CCALLOAD(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALFMIN 21
+#define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN)
+#define F_T5_STATIC_KR_PLL_CCALFMIN V_T5_STATIC_KR_PLL_CCALFMIN(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALFMAX 20
+#define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX)
+#define F_T5_STATIC_KR_PLL_CCALFMAX V_T5_STATIC_KR_PLL_CCALFMAX(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALCVHOLD 19
+#define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD)
+#define F_T5_STATIC_KR_PLL_CCALCVHOLD V_T5_STATIC_KR_PLL_CCALCVHOLD(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALBANDSEL 15
+#define M_T5_STATIC_KR_PLL_CCALBANDSEL 0xfU
+#define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL)
+#define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & M_T5_STATIC_KR_PLL_CCALBANDSEL)
+
+#define S_T5_STATIC_KR_PLL_BGOFFSET 11
+#define M_T5_STATIC_KR_PLL_BGOFFSET 0xfU
+#define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET)
+#define G_T5_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET)
+
+#define S_T5_STATIC_KR_PLL_P 8
+#define M_T5_STATIC_KR_PLL_P 0x7U
+#define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P)
+#define G_T5_STATIC_KR_PLL_P(x) (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P)
+
+#define S_T5_STATIC_KR_PLL_N2 4
+#define M_T5_STATIC_KR_PLL_N2 0xfU
+#define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2)
+#define G_T5_STATIC_KR_PLL_N2(x) (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2)
+
+#define S_T5_STATIC_KR_PLL_N1 0
+#define M_T5_STATIC_KR_PLL_N1 0xfU
+#define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1)
+#define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1)
+
+#define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
+
+#define S_T5_STATIC_KR_PLL_M 11
+#define M_T5_STATIC_KR_PLL_M 0x1ffU
+#define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M)
+#define G_T5_STATIC_KR_PLL_M(x) (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M)
+
+#define S_T5_STATIC_KR_PLL_ANALOGTUNE 0
+#define M_T5_STATIC_KR_PLL_ANALOGTUNE 0x7ffU
+#define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE)
+#define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE)
+
#define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
#define S_HALT_CALIBRATE 1
@@ -4391,6 +8602,40 @@
#define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE)
#define F_RESET_CALIBRATE V_RESET_CALIBRATE(1U)
+#define A_DBG_GPIO_EN_NEW 0x6100
+
+#define S_GPIO16_OEN 7
+#define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN)
+#define F_GPIO16_OEN V_GPIO16_OEN(1U)
+
+#define S_GPIO17_OEN 6
+#define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN)
+#define F_GPIO17_OEN V_GPIO17_OEN(1U)
+
+#define S_GPIO18_OEN 5
+#define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN)
+#define F_GPIO18_OEN V_GPIO18_OEN(1U)
+
+#define S_GPIO19_OEN 4
+#define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN)
+#define F_GPIO19_OEN V_GPIO19_OEN(1U)
+
+#define S_GPIO16_OUT_VAL 3
+#define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL)
+#define F_GPIO16_OUT_VAL V_GPIO16_OUT_VAL(1U)
+
+#define S_GPIO17_OUT_VAL 2
+#define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL)
+#define F_GPIO17_OUT_VAL V_GPIO17_OUT_VAL(1U)
+
+#define S_GPIO18_OUT_VAL 1
+#define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL)
+#define F_GPIO18_OUT_VAL V_GPIO18_OUT_VAL(1U)
+
+#define S_GPIO19_OUT_VAL 0
+#define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL)
+#define F_GPIO19_OUT_VAL V_GPIO19_OUT_VAL(1U)
+
#define A_DBG_PVT_REG_UPDATE_CTL 0x6104
#define S_FAST_UPDATE 8
@@ -4405,6 +8650,40 @@
#define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE)
#define F_HALT_UPDATE V_HALT_UPDATE(1U)
+#define A_DBG_GPIO_IN_NEW 0x6104
+
+#define S_GPIO16_CHG_DET 7
+#define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET)
+#define F_GPIO16_CHG_DET V_GPIO16_CHG_DET(1U)
+
+#define S_GPIO17_CHG_DET 6
+#define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET)
+#define F_GPIO17_CHG_DET V_GPIO17_CHG_DET(1U)
+
+#define S_GPIO18_CHG_DET 5
+#define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET)
+#define F_GPIO18_CHG_DET V_GPIO18_CHG_DET(1U)
+
+#define S_GPIO19_CHG_DET 4
+#define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET)
+#define F_GPIO19_CHG_DET V_GPIO19_CHG_DET(1U)
+
+#define S_GPIO16_IN 3
+#define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
+#define F_GPIO16_IN V_GPIO16_IN(1U)
+
+#define S_GPIO17_IN 2
+#define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
+#define F_GPIO17_IN V_GPIO17_IN(1U)
+
+#define S_GPIO18_IN 1
+#define V_GPIO18_IN(x) ((x) << S_GPIO18_IN)
+#define F_GPIO18_IN V_GPIO18_IN(1U)
+
+#define S_GPIO19_IN 0
+#define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
+#define F_GPIO19_IN V_GPIO19_IN(1U)
+
#define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
#define S_LAST_MEASUREMENT_SELECT 8
@@ -4422,6 +8701,67 @@
#define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
#define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A)
+#define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108
+
+#define S_T5_STATIC_KX_PLL_BYPASS 30
+#define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS)
+#define F_T5_STATIC_KX_PLL_BYPASS V_T5_STATIC_KX_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_KX_PLL_VBOOSTDIV 27
+#define M_T5_STATIC_KX_PLL_VBOOSTDIV 0x7U
+#define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV)
+#define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV)
+
+#define S_T5_STATIC_KX_PLL_CPISEL 24
+#define M_T5_STATIC_KX_PLL_CPISEL 0x7U
+#define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL)
+#define G_T5_STATIC_KX_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL)
+
+#define S_T5_STATIC_KX_PLL_CCALMETHOD 23
+#define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD)
+#define F_T5_STATIC_KX_PLL_CCALMETHOD V_T5_STATIC_KX_PLL_CCALMETHOD(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALLOAD 22
+#define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD)
+#define F_T5_STATIC_KX_PLL_CCALLOAD V_T5_STATIC_KX_PLL_CCALLOAD(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALFMIN 21
+#define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN)
+#define F_T5_STATIC_KX_PLL_CCALFMIN V_T5_STATIC_KX_PLL_CCALFMIN(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALFMAX 20
+#define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX)
+#define F_T5_STATIC_KX_PLL_CCALFMAX V_T5_STATIC_KX_PLL_CCALFMAX(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALCVHOLD 19
+#define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD)
+#define F_T5_STATIC_KX_PLL_CCALCVHOLD V_T5_STATIC_KX_PLL_CCALCVHOLD(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALBANDSEL 15
+#define M_T5_STATIC_KX_PLL_CCALBANDSEL 0xfU
+#define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL)
+#define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & M_T5_STATIC_KX_PLL_CCALBANDSEL)
+
+#define S_T5_STATIC_KX_PLL_BGOFFSET 11
+#define M_T5_STATIC_KX_PLL_BGOFFSET 0xfU
+#define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET)
+#define G_T5_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET)
+
+#define S_T5_STATIC_KX_PLL_P 8
+#define M_T5_STATIC_KX_PLL_P 0x7U
+#define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P)
+#define G_T5_STATIC_KX_PLL_P(x) (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P)
+
+#define S_T5_STATIC_KX_PLL_N2 4
+#define M_T5_STATIC_KX_PLL_N2 0xfU
+#define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2)
+#define G_T5_STATIC_KX_PLL_N2(x) (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2)
+
+#define S_T5_STATIC_KX_PLL_N1 0
+#define M_T5_STATIC_KX_PLL_N1 0xfU
+#define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1)
+#define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1)
+
#define A_DBG_PVT_REG_DRVN 0x610c
#define S_PVT_REG_DRVN_EN 8
@@ -4438,6 +8778,18 @@
#define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A)
#define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A)
+#define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c
+
+#define S_T5_STATIC_KX_PLL_M 11
+#define M_T5_STATIC_KX_PLL_M 0x1ffU
+#define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M)
+#define G_T5_STATIC_KX_PLL_M(x) (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M)
+
+#define S_T5_STATIC_KX_PLL_ANALOGTUNE 0
+#define M_T5_STATIC_KX_PLL_ANALOGTUNE 0x7ffU
+#define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE)
+#define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE)
+
#define A_DBG_PVT_REG_DRVP 0x6110
#define S_PVT_REG_DRVP_EN 8
@@ -4454,6 +8806,30 @@
#define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A)
#define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A)
+#define A_DBG_T5_STATIC_C_DFS_CONF 0x6110
+
+#define S_STATIC_C_DFS_RANGEA 8
+#define M_STATIC_C_DFS_RANGEA 0x1fU
+#define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA)
+#define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA)
+
+#define S_STATIC_C_DFS_RANGEB 3
+#define M_STATIC_C_DFS_RANGEB 0x1fU
+#define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB)
+#define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB)
+
+#define S_STATIC_C_DFS_FFTUNE4 2
+#define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4)
+#define F_STATIC_C_DFS_FFTUNE4 V_STATIC_C_DFS_FFTUNE4(1U)
+
+#define S_STATIC_C_DFS_FFTUNE5 1
+#define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5)
+#define F_STATIC_C_DFS_FFTUNE5 V_STATIC_C_DFS_FFTUNE5(1U)
+
+#define S_STATIC_C_DFS_ENABLE 0
+#define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE)
+#define F_STATIC_C_DFS_ENABLE V_STATIC_C_DFS_ENABLE(1U)
+
#define A_DBG_PVT_REG_TERMN 0x6114
#define S_PVT_REG_TERMN_EN 8
@@ -4470,6 +8846,30 @@
#define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A)
#define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A)
+#define A_DBG_T5_STATIC_U_DFS_CONF 0x6114
+
+#define S_STATIC_U_DFS_RANGEA 8
+#define M_STATIC_U_DFS_RANGEA 0x1fU
+#define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA)
+#define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA)
+
+#define S_STATIC_U_DFS_RANGEB 3
+#define M_STATIC_U_DFS_RANGEB 0x1fU
+#define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB)
+#define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB)
+
+#define S_STATIC_U_DFS_FFTUNE4 2
+#define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4)
+#define F_STATIC_U_DFS_FFTUNE4 V_STATIC_U_DFS_FFTUNE4(1U)
+
+#define S_STATIC_U_DFS_FFTUNE5 1
+#define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5)
+#define F_STATIC_U_DFS_FFTUNE5 V_STATIC_U_DFS_FFTUNE5(1U)
+
+#define S_STATIC_U_DFS_ENABLE 0
+#define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE)
+#define F_STATIC_U_DFS_ENABLE V_STATIC_U_DFS_ENABLE(1U)
+
#define A_DBG_PVT_REG_TERMP 0x6118
#define S_PVT_REG_TERMP_EN 8
@@ -4486,6 +8886,88 @@
#define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A)
#define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A)
+#define A_DBG_GPIO_PE_EN 0x6118
+
+#define S_GPIO19_PE_EN 19
+#define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN)
+#define F_GPIO19_PE_EN V_GPIO19_PE_EN(1U)
+
+#define S_GPIO18_PE_EN 18
+#define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN)
+#define F_GPIO18_PE_EN V_GPIO18_PE_EN(1U)
+
+#define S_GPIO17_PE_EN 17
+#define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN)
+#define F_GPIO17_PE_EN V_GPIO17_PE_EN(1U)
+
+#define S_GPIO16_PE_EN 16
+#define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN)
+#define F_GPIO16_PE_EN V_GPIO16_PE_EN(1U)
+
+#define S_GPIO15_PE_EN 15
+#define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN)
+#define F_GPIO15_PE_EN V_GPIO15_PE_EN(1U)
+
+#define S_GPIO14_PE_EN 14
+#define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN)
+#define F_GPIO14_PE_EN V_GPIO14_PE_EN(1U)
+
+#define S_GPIO13_PE_EN 13
+#define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN)
+#define F_GPIO13_PE_EN V_GPIO13_PE_EN(1U)
+
+#define S_GPIO12_PE_EN 12
+#define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN)
+#define F_GPIO12_PE_EN V_GPIO12_PE_EN(1U)
+
+#define S_GPIO11_PE_EN 11
+#define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN)
+#define F_GPIO11_PE_EN V_GPIO11_PE_EN(1U)
+
+#define S_GPIO10_PE_EN 10
+#define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN)
+#define F_GPIO10_PE_EN V_GPIO10_PE_EN(1U)
+
+#define S_GPIO9_PE_EN 9
+#define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN)
+#define F_GPIO9_PE_EN V_GPIO9_PE_EN(1U)
+
+#define S_GPIO8_PE_EN 8
+#define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN)
+#define F_GPIO8_PE_EN V_GPIO8_PE_EN(1U)
+
+#define S_GPIO7_PE_EN 7
+#define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN)
+#define F_GPIO7_PE_EN V_GPIO7_PE_EN(1U)
+
+#define S_GPIO6_PE_EN 6
+#define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN)
+#define F_GPIO6_PE_EN V_GPIO6_PE_EN(1U)
+
+#define S_GPIO5_PE_EN 5
+#define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN)
+#define F_GPIO5_PE_EN V_GPIO5_PE_EN(1U)
+
+#define S_GPIO4_PE_EN 4
+#define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN)
+#define F_GPIO4_PE_EN V_GPIO4_PE_EN(1U)
+
+#define S_GPIO3_PE_EN 3
+#define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN)
+#define F_GPIO3_PE_EN V_GPIO3_PE_EN(1U)
+
+#define S_GPIO2_PE_EN 2
+#define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN)
+#define F_GPIO2_PE_EN V_GPIO2_PE_EN(1U)
+
+#define S_GPIO1_PE_EN 1
+#define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN)
+#define F_GPIO1_PE_EN V_GPIO1_PE_EN(1U)
+
+#define S_GPIO0_PE_EN 0
+#define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN)
+#define F_GPIO0_PE_EN V_GPIO0_PE_EN(1U)
+
#define A_DBG_PVT_REG_THRESHOLD 0x611c
#define S_PVT_CALIBRATION_DONE 8
@@ -4524,6 +9006,88 @@
#define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC)
#define F_THRESHOLD_DRVN_MIN_SYNC V_THRESHOLD_DRVN_MIN_SYNC(1U)
+#define A_DBG_GPIO_PS_EN 0x611c
+
+#define S_GPIO19_PS_EN 19
+#define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN)
+#define F_GPIO19_PS_EN V_GPIO19_PS_EN(1U)
+
+#define S_GPIO18_PS_EN 18
+#define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN)
+#define F_GPIO18_PS_EN V_GPIO18_PS_EN(1U)
+
+#define S_GPIO17_PS_EN 17
+#define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN)
+#define F_GPIO17_PS_EN V_GPIO17_PS_EN(1U)
+
+#define S_GPIO16_PS_EN 16
+#define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN)
+#define F_GPIO16_PS_EN V_GPIO16_PS_EN(1U)
+
+#define S_GPIO15_PS_EN 15
+#define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN)
+#define F_GPIO15_PS_EN V_GPIO15_PS_EN(1U)
+
+#define S_GPIO14_PS_EN 14
+#define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN)
+#define F_GPIO14_PS_EN V_GPIO14_PS_EN(1U)
+
+#define S_GPIO13_PS_EN 13
+#define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN)
+#define F_GPIO13_PS_EN V_GPIO13_PS_EN(1U)
+
+#define S_GPIO12_PS_EN 12
+#define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN)
+#define F_GPIO12_PS_EN V_GPIO12_PS_EN(1U)
+
+#define S_GPIO11_PS_EN 11
+#define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN)
+#define F_GPIO11_PS_EN V_GPIO11_PS_EN(1U)
+
+#define S_GPIO10_PS_EN 10
+#define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN)
+#define F_GPIO10_PS_EN V_GPIO10_PS_EN(1U)
+
+#define S_GPIO9_PS_EN 9
+#define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN)
+#define F_GPIO9_PS_EN V_GPIO9_PS_EN(1U)
+
+#define S_GPIO8_PS_EN 8
+#define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN)
+#define F_GPIO8_PS_EN V_GPIO8_PS_EN(1U)
+
+#define S_GPIO7_PS_EN 7
+#define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN)
+#define F_GPIO7_PS_EN V_GPIO7_PS_EN(1U)
+
+#define S_GPIO6_PS_EN 6
+#define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN)
+#define F_GPIO6_PS_EN V_GPIO6_PS_EN(1U)
+
+#define S_GPIO5_PS_EN 5
+#define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN)
+#define F_GPIO5_PS_EN V_GPIO5_PS_EN(1U)
+
+#define S_GPIO4_PS_EN 4
+#define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN)
+#define F_GPIO4_PS_EN V_GPIO4_PS_EN(1U)
+
+#define S_GPIO3_PS_EN 3
+#define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN)
+#define F_GPIO3_PS_EN V_GPIO3_PS_EN(1U)
+
+#define S_GPIO2_PS_EN 2
+#define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN)
+#define F_GPIO2_PS_EN V_GPIO2_PS_EN(1U)
+
+#define S_GPIO1_PS_EN 1
+#define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN)
+#define F_GPIO1_PS_EN V_GPIO1_PS_EN(1U)
+
+#define S_GPIO0_PS_EN 0
+#define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN)
+#define F_GPIO0_PS_EN V_GPIO0_PS_EN(1U)
+
#define A_DBG_PVT_REG_IN_TERMP 0x6120
#define S_REG_IN_TERMP_B 4
@@ -4536,6 +9100,7 @@
#define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A)
#define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A)
+#define A_DBG_EFUSE_BYTE16_19 0x6120
#define A_DBG_PVT_REG_IN_TERMN 0x6124
#define S_REG_IN_TERMN_B 4
@@ -4548,6 +9113,7 @@
#define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A)
#define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A)
+#define A_DBG_EFUSE_BYTE20_23 0x6124
#define A_DBG_PVT_REG_IN_DRVP 0x6128
#define S_REG_IN_DRVP_B 4
@@ -4560,6 +9126,7 @@
#define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A)
#define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A)
+#define A_DBG_EFUSE_BYTE24_27 0x6128
#define A_DBG_PVT_REG_IN_DRVN 0x612c
#define S_REG_IN_DRVN_B 4
@@ -4572,6 +9139,7 @@
#define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A)
#define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A)
+#define A_DBG_EFUSE_BYTE28_31 0x612c
#define A_DBG_PVT_REG_OUT_TERMP 0x6130
#define S_REG_OUT_TERMP_B 4
@@ -4584,6 +9152,7 @@
#define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A)
#define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A)
+#define A_DBG_EFUSE_BYTE32_35 0x6130
#define A_DBG_PVT_REG_OUT_TERMN 0x6134
#define S_REG_OUT_TERMN_B 4
@@ -4596,6 +9165,7 @@
#define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A)
#define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A)
+#define A_DBG_EFUSE_BYTE36_39 0x6134
#define A_DBG_PVT_REG_OUT_DRVP 0x6138
#define S_REG_OUT_DRVP_B 4
@@ -4608,6 +9178,7 @@
#define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A)
#define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A)
+#define A_DBG_EFUSE_BYTE40_43 0x6138
#define A_DBG_PVT_REG_OUT_DRVN 0x613c
#define S_REG_OUT_DRVN_B 4
@@ -4620,6 +9191,7 @@
#define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A)
#define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A)
+#define A_DBG_EFUSE_BYTE44_47 0x613c
#define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
#define S_TERMP_B_HISTORY 4
@@ -4632,6 +9204,7 @@
#define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY)
#define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY)
+#define A_DBG_EFUSE_BYTE48_51 0x6140
#define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
#define S_TERMN_B_HISTORY 4
@@ -4644,6 +9217,7 @@
#define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY)
#define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY)
+#define A_DBG_EFUSE_BYTE52_55 0x6144
#define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
#define S_DRVP_B_HISTORY 4
@@ -4656,6 +9230,7 @@
#define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY)
#define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY)
+#define A_DBG_EFUSE_BYTE56_59 0x6148
#define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
#define S_DRVN_B_HISTORY 4
@@ -4668,6 +9243,7 @@
#define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY)
#define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY)
+#define A_DBG_EFUSE_BYTE60_63 0x614c
#define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
#define S_SAMPLE_WAIT_CLKS 0
@@ -6507,6 +11083,18 @@
#define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
#define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
+#define A_MA_EXT_MEMORY0_BAR 0x77c8
+
+#define S_EXT_MEM0_BASE 16
+#define M_EXT_MEM0_BASE 0xfffU
+#define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
+#define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)
+
+#define S_EXT_MEM0_SIZE 0
+#define M_EXT_MEM0_SIZE 0xfffU
+#define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
+#define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
+
#define A_MA_HOST_MEMORY_BAR 0x77cc
#define S_HMA_BASE 16
@@ -6530,6 +11118,15 @@
#define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE)
#define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
+#define S_BRC_MODE1 6
+#define V_BRC_MODE1(x) ((x) << S_BRC_MODE1)
+#define F_BRC_MODE1 V_BRC_MODE1(1U)
+
+#define S_EXT_MEM_PAGE_SIZE1 4
+#define M_EXT_MEM_PAGE_SIZE1 0x3U
+#define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1)
+#define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1)
+
#define A_MA_ARB_CTRL 0x77d4
#define S_DIS_PAGE_HINT 1
@@ -6540,6 +11137,10 @@
#define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB)
#define F_DIS_ADV_ARB V_DIS_ADV_ARB(1U)
+#define S_DIS_BANK_FAIR 2
+#define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR)
+#define F_DIS_BANK_FAIR V_DIS_BANK_FAIR(1U)
+
#define A_MA_TARGET_MEM_ENABLE 0x77d8
#define S_HMA_ENABLE 3
@@ -6558,6 +11159,18 @@
#define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
#define F_EDRAM0_ENABLE V_EDRAM0_ENABLE(1U)
+#define S_HMA_MUX 5
+#define V_HMA_MUX(x) ((x) << S_HMA_MUX)
+#define F_HMA_MUX V_HMA_MUX(1U)
+
+#define S_EXT_MEM1_ENABLE 4
+#define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
+#define F_EXT_MEM1_ENABLE V_EXT_MEM1_ENABLE(1U)
+
+#define S_EXT_MEM0_ENABLE 2
+#define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
+#define F_EXT_MEM0_ENABLE V_EXT_MEM0_ENABLE(1U)
+
#define A_MA_INT_ENABLE 0x77dc
#define S_MEM_PERR_INT_ENABLE 1
@@ -6568,6 +11181,10 @@
#define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE)
#define F_MEM_WRAP_INT_ENABLE V_MEM_WRAP_INT_ENABLE(1U)
+#define S_MEM_TO_INT_ENABLE 2
+#define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE)
+#define F_MEM_TO_INT_ENABLE V_MEM_TO_INT_ENABLE(1U)
+
#define A_MA_INT_CAUSE 0x77e0
#define S_MEM_PERR_INT_CAUSE 1
@@ -6578,6 +11195,10 @@
#define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
#define F_MEM_WRAP_INT_CAUSE V_MEM_WRAP_INT_CAUSE(1U)
+#define S_MEM_TO_INT_CAUSE 2
+#define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE)
+#define F_MEM_TO_INT_CAUSE V_MEM_TO_INT_CAUSE(1U)
+
#define A_MA_INT_WRAP_STATUS 0x77e4
#define S_MEM_WRAP_ADDRESS 4
@@ -6734,6 +11355,7 @@
#define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN)
#define F_CL0_PAR_RDQUEUE_ERROR_EN V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
+#define A_MA_PARITY_ERROR_ENABLE1 0x77f0
#define A_MA_PARITY_ERROR_STATUS 0x77f4
#define S_TP_DMARBT_PAR_ERROR 31
@@ -6864,6 +11486,7 @@
#define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
#define F_CL0_PAR_RDQUEUE_ERROR V_CL0_PAR_RDQUEUE_ERROR(1U)
+#define A_MA_PARITY_ERROR_STATUS1 0x77f4
#define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
#define S_BONUS_REG 6
@@ -6891,6 +11514,737 @@
#define V_UE_ENABLE(x) ((x) << S_UE_ENABLE)
#define F_UE_ENABLE V_UE_ENABLE(1U)
+#define S_FUTURE_EXPANSION 1
+#define M_FUTURE_EXPANSION 0x7fffffffU
+#define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION)
+#define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION)
+
+#define A_MA_PARITY_ERROR_ENABLE2 0x7800
+
+#define S_ARB4_PAR_WRQUEUE_ERROR_EN 1
+#define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN)
+#define F_ARB4_PAR_WRQUEUE_ERROR_EN V_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB4_PAR_RDQUEUE_ERROR_EN 0
+#define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN)
+#define F_ARB4_PAR_RDQUEUE_ERROR_EN V_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define A_MA_PARITY_ERROR_STATUS2 0x7804
+
+#define S_ARB4_PAR_WRQUEUE_ERROR 1
+#define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
+#define F_ARB4_PAR_WRQUEUE_ERROR V_ARB4_PAR_WRQUEUE_ERROR(1U)
+
+#define S_ARB4_PAR_RDQUEUE_ERROR 0
+#define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
+#define F_ARB4_PAR_RDQUEUE_ERROR V_ARB4_PAR_RDQUEUE_ERROR(1U)
+
+#define A_MA_EXT_MEMORY1_BAR 0x7808
+
+#define S_EXT_MEM1_BASE 16
+#define M_EXT_MEM1_BASE 0xfffU
+#define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
+#define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)
+
+#define S_EXT_MEM1_SIZE 0
+#define M_EXT_MEM1_SIZE 0xfffU
+#define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
+#define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
+
+#define A_MA_PMTX_THROTTLE 0x780c
+
+#define S_FL_ENABLE 31
+#define V_FL_ENABLE(x) ((x) << S_FL_ENABLE)
+#define F_FL_ENABLE V_FL_ENABLE(1U)
+
+#define S_FL_LIMIT 0
+#define M_FL_LIMIT 0xffU
+#define V_FL_LIMIT(x) ((x) << S_FL_LIMIT)
+#define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT)
+
+#define A_MA_PMRX_THROTTLE 0x7810
+#define A_MA_SGE_TH0_WRDATA_CNT 0x7814
+#define A_MA_SGE_TH1_WRDATA_CNT 0x7818
+#define A_MA_ULPTX_WRDATA_CNT 0x781c
+#define A_MA_ULPRX_WRDATA_CNT 0x7820
+#define A_MA_ULPTXRX_WRDATA_CNT 0x7824
+#define A_MA_TP_TH0_WRDATA_CNT 0x7828
+#define A_MA_TP_TH1_WRDATA_CNT 0x782c
+#define A_MA_LE_WRDATA_CNT 0x7830
+#define A_MA_CIM_WRDATA_CNT 0x7834
+#define A_MA_PCIE_WRDATA_CNT 0x7838
+#define A_MA_PMTX_WRDATA_CNT 0x783c
+#define A_MA_PMRX_WRDATA_CNT 0x7840
+#define A_MA_HMA_WRDATA_CNT 0x7844
+#define A_MA_SGE_TH0_RDDATA_CNT 0x7848
+#define A_MA_SGE_TH1_RDDATA_CNT 0x784c
+#define A_MA_ULPTX_RDDATA_CNT 0x7850
+#define A_MA_ULPRX_RDDATA_CNT 0x7854
+#define A_MA_ULPTXRX_RDDATA_CNT 0x7858
+#define A_MA_TP_TH0_RDDATA_CNT 0x785c
+#define A_MA_TP_TH1_RDDATA_CNT 0x7860
+#define A_MA_LE_RDDATA_CNT 0x7864
+#define A_MA_CIM_RDDATA_CNT 0x7868
+#define A_MA_PCIE_RDDATA_CNT 0x786c
+#define A_MA_PMTX_RDDATA_CNT 0x7870
+#define A_MA_PMRX_RDDATA_CNT 0x7874
+#define A_MA_HMA_RDDATA_CNT 0x7878
+#define A_MA_EDRAM0_WRDATA_CNT1 0x787c
+#define A_MA_EDRAM0_WRDATA_CNT0 0x7880
+#define A_MA_EDRAM1_WRDATA_CNT1 0x7884
+#define A_MA_EDRAM1_WRDATA_CNT0 0x7888
+#define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
+#define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
+#define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
+#define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898
+#define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c
+#define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0
+#define A_MA_EDRAM0_RDDATA_CNT1 0x78a4
+#define A_MA_EDRAM0_RDDATA_CNT0 0x78a8
+#define A_MA_EDRAM1_RDDATA_CNT1 0x78ac
+#define A_MA_EDRAM1_RDDATA_CNT0 0x78b0
+#define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4
+#define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8
+#define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc
+#define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0
+#define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4
+#define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8
+#define A_MA_TIMEOUT_CFG 0x78cc
+
+#define S_CLR 31
+#define V_CLR(x) ((x) << S_CLR)
+#define F_CLR V_CLR(1U)
+
+#define S_CNT_LOCK 30
+#define V_CNT_LOCK(x) ((x) << S_CNT_LOCK)
+#define F_CNT_LOCK V_CNT_LOCK(1U)
+
+#define S_WRN 24
+#define V_WRN(x) ((x) << S_WRN)
+#define F_WRN V_WRN(1U)
+
+#define S_DIR 23
+#define V_DIR(x) ((x) << S_DIR)
+#define F_DIR V_DIR(1U)
+
+#define S_TO_BUS 22
+#define V_TO_BUS(x) ((x) << S_TO_BUS)
+#define F_TO_BUS V_TO_BUS(1U)
+
+#define S_CLIENT 16
+#define M_CLIENT 0xfU
+#define V_CLIENT(x) ((x) << S_CLIENT)
+#define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT)
+
+#define S_DELAY 0
+#define M_DELAY 0xffffU
+#define V_DELAY(x) ((x) << S_DELAY)
+#define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY)
+
+#define A_MA_TIMEOUT_CNT 0x78d0
+
+#define S_CNT_VAL 0
+#define M_CNT_VAL 0xffffU
+#define V_CNT_VAL(x) ((x) << S_CNT_VAL)
+#define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL)
+
+#define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4
+
+#define S_FUTURE_CEXPANSION 29
+#define M_FUTURE_CEXPANSION 0x7U
+#define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION)
+#define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION)
+
+#define S_CL12_WR_CMD_TO_EN 28
+#define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN)
+#define F_CL12_WR_CMD_TO_EN V_CL12_WR_CMD_TO_EN(1U)
+
+#define S_CL11_WR_CMD_TO_EN 27
+#define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN)
+#define F_CL11_WR_CMD_TO_EN V_CL11_WR_CMD_TO_EN(1U)
+
+#define S_CL10_WR_CMD_TO_EN 26
+#define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN)
+#define F_CL10_WR_CMD_TO_EN V_CL10_WR_CMD_TO_EN(1U)
+
+#define S_CL9_WR_CMD_TO_EN 25
+#define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN)
+#define F_CL9_WR_CMD_TO_EN V_CL9_WR_CMD_TO_EN(1U)
+
+#define S_CL8_WR_CMD_TO_EN 24
+#define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN)
+#define F_CL8_WR_CMD_TO_EN V_CL8_WR_CMD_TO_EN(1U)
+
+#define S_CL7_WR_CMD_TO_EN 23
+#define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN)
+#define F_CL7_WR_CMD_TO_EN V_CL7_WR_CMD_TO_EN(1U)
+
+#define S_CL6_WR_CMD_TO_EN 22
+#define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN)
+#define F_CL6_WR_CMD_TO_EN V_CL6_WR_CMD_TO_EN(1U)
+
+#define S_CL5_WR_CMD_TO_EN 21
+#define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN)
+#define F_CL5_WR_CMD_TO_EN V_CL5_WR_CMD_TO_EN(1U)
+
+#define S_CL4_WR_CMD_TO_EN 20
+#define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN)
+#define F_CL4_WR_CMD_TO_EN V_CL4_WR_CMD_TO_EN(1U)
+
+#define S_CL3_WR_CMD_TO_EN 19
+#define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN)
+#define F_CL3_WR_CMD_TO_EN V_CL3_WR_CMD_TO_EN(1U)
+
+#define S_CL2_WR_CMD_TO_EN 18
+#define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN)
+#define F_CL2_WR_CMD_TO_EN V_CL2_WR_CMD_TO_EN(1U)
+
+#define S_CL1_WR_CMD_TO_EN 17
+#define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN)
+#define F_CL1_WR_CMD_TO_EN V_CL1_WR_CMD_TO_EN(1U)
+
+#define S_CL0_WR_CMD_TO_EN 16
+#define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN)
+#define F_CL0_WR_CMD_TO_EN V_CL0_WR_CMD_TO_EN(1U)
+
+#define S_FUTURE_DEXPANSION 13
+#define M_FUTURE_DEXPANSION 0x7U
+#define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION)
+#define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION)
+
+#define S_CL12_WR_DATA_TO_EN 12
+#define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN)
+#define F_CL12_WR_DATA_TO_EN V_CL12_WR_DATA_TO_EN(1U)
+
+#define S_CL11_WR_DATA_TO_EN 11
+#define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN)
+#define F_CL11_WR_DATA_TO_EN V_CL11_WR_DATA_TO_EN(1U)
+
+#define S_CL10_WR_DATA_TO_EN 10
+#define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN)
+#define F_CL10_WR_DATA_TO_EN V_CL10_WR_DATA_TO_EN(1U)
+
+#define S_CL9_WR_DATA_TO_EN 9
+#define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN)
+#define F_CL9_WR_DATA_TO_EN V_CL9_WR_DATA_TO_EN(1U)
+
+#define S_CL8_WR_DATA_TO_EN 8
+#define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN)
+#define F_CL8_WR_DATA_TO_EN V_CL8_WR_DATA_TO_EN(1U)
+
+#define S_CL7_WR_DATA_TO_EN 7
+#define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN)
+#define F_CL7_WR_DATA_TO_EN V_CL7_WR_DATA_TO_EN(1U)
+
+#define S_CL6_WR_DATA_TO_EN 6
+#define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN)
+#define F_CL6_WR_DATA_TO_EN V_CL6_WR_DATA_TO_EN(1U)
+
+#define S_CL5_WR_DATA_TO_EN 5
+#define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN)
+#define F_CL5_WR_DATA_TO_EN V_CL5_WR_DATA_TO_EN(1U)
+
+#define S_CL4_WR_DATA_TO_EN 4
+#define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN)
+#define F_CL4_WR_DATA_TO_EN V_CL4_WR_DATA_TO_EN(1U)
+
+#define S_CL3_WR_DATA_TO_EN 3
+#define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN)
+#define F_CL3_WR_DATA_TO_EN V_CL3_WR_DATA_TO_EN(1U)
+
+#define S_CL2_WR_DATA_TO_EN 2
+#define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN)
+#define F_CL2_WR_DATA_TO_EN V_CL2_WR_DATA_TO_EN(1U)
+
+#define S_CL1_WR_DATA_TO_EN 1
+#define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN)
+#define F_CL1_WR_DATA_TO_EN V_CL1_WR_DATA_TO_EN(1U)
+
+#define S_CL0_WR_DATA_TO_EN 0
+#define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN)
+#define F_CL0_WR_DATA_TO_EN V_CL0_WR_DATA_TO_EN(1U)
+
+#define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
+
+#define S_CL12_WR_CMD_TO_ERROR 28
+#define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR)
+#define F_CL12_WR_CMD_TO_ERROR V_CL12_WR_CMD_TO_ERROR(1U)
+
+#define S_CL11_WR_CMD_TO_ERROR 27
+#define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR)
+#define F_CL11_WR_CMD_TO_ERROR V_CL11_WR_CMD_TO_ERROR(1U)
+
+#define S_CL10_WR_CMD_TO_ERROR 26
+#define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR)
+#define F_CL10_WR_CMD_TO_ERROR V_CL10_WR_CMD_TO_ERROR(1U)
+
+#define S_CL9_WR_CMD_TO_ERROR 25
+#define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR)
+#define F_CL9_WR_CMD_TO_ERROR V_CL9_WR_CMD_TO_ERROR(1U)
+
+#define S_CL8_WR_CMD_TO_ERROR 24
+#define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR)
+#define F_CL8_WR_CMD_TO_ERROR V_CL8_WR_CMD_TO_ERROR(1U)
+
+#define S_CL7_WR_CMD_TO_ERROR 23
+#define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR)
+#define F_CL7_WR_CMD_TO_ERROR V_CL7_WR_CMD_TO_ERROR(1U)
+
+#define S_CL6_WR_CMD_TO_ERROR 22
+#define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR)
+#define F_CL6_WR_CMD_TO_ERROR V_CL6_WR_CMD_TO_ERROR(1U)
+
+#define S_CL5_WR_CMD_TO_ERROR 21
+#define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR)
+#define F_CL5_WR_CMD_TO_ERROR V_CL5_WR_CMD_TO_ERROR(1U)
+
+#define S_CL4_WR_CMD_TO_ERROR 20
+#define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR)
+#define F_CL4_WR_CMD_TO_ERROR V_CL4_WR_CMD_TO_ERROR(1U)
+
+#define S_CL3_WR_CMD_TO_ERROR 19
+#define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR)
+#define F_CL3_WR_CMD_TO_ERROR V_CL3_WR_CMD_TO_ERROR(1U)
+
+#define S_CL2_WR_CMD_TO_ERROR 18
+#define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR)
+#define F_CL2_WR_CMD_TO_ERROR V_CL2_WR_CMD_TO_ERROR(1U)
+
+#define S_CL1_WR_CMD_TO_ERROR 17
+#define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR)
+#define F_CL1_WR_CMD_TO_ERROR V_CL1_WR_CMD_TO_ERROR(1U)
+
+#define S_CL0_WR_CMD_TO_ERROR 16
+#define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR)
+#define F_CL0_WR_CMD_TO_ERROR V_CL0_WR_CMD_TO_ERROR(1U)
+
+#define S_CL12_WR_DATA_TO_ERROR 12
+#define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR)
+#define F_CL12_WR_DATA_TO_ERROR V_CL12_WR_DATA_TO_ERROR(1U)
+
+#define S_CL11_WR_DATA_TO_ERROR 11
+#define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR)
+#define F_CL11_WR_DATA_TO_ERROR V_CL11_WR_DATA_TO_ERROR(1U)
+
+#define S_CL10_WR_DATA_TO_ERROR 10
+#define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR)
+#define F_CL10_WR_DATA_TO_ERROR V_CL10_WR_DATA_TO_ERROR(1U)
+
+#define S_CL9_WR_DATA_TO_ERROR 9
+#define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR)
+#define F_CL9_WR_DATA_TO_ERROR V_CL9_WR_DATA_TO_ERROR(1U)
+
+#define S_CL8_WR_DATA_TO_ERROR 8
+#define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR)
+#define F_CL8_WR_DATA_TO_ERROR V_CL8_WR_DATA_TO_ERROR(1U)
+
+#define S_CL7_WR_DATA_TO_ERROR 7
+#define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR)
+#define F_CL7_WR_DATA_TO_ERROR V_CL7_WR_DATA_TO_ERROR(1U)
+
+#define S_CL6_WR_DATA_TO_ERROR 6
+#define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR)
+#define F_CL6_WR_DATA_TO_ERROR V_CL6_WR_DATA_TO_ERROR(1U)
+
+#define S_CL5_WR_DATA_TO_ERROR 5
+#define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR)
+#define F_CL5_WR_DATA_TO_ERROR V_CL5_WR_DATA_TO_ERROR(1U)
+
+#define S_CL4_WR_DATA_TO_ERROR 4
+#define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR)
+#define F_CL4_WR_DATA_TO_ERROR V_CL4_WR_DATA_TO_ERROR(1U)
+
+#define S_CL3_WR_DATA_TO_ERROR 3
+#define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR)
+#define F_CL3_WR_DATA_TO_ERROR V_CL3_WR_DATA_TO_ERROR(1U)
+
+#define S_CL2_WR_DATA_TO_ERROR 2
+#define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR)
+#define F_CL2_WR_DATA_TO_ERROR V_CL2_WR_DATA_TO_ERROR(1U)
+
+#define S_CL1_WR_DATA_TO_ERROR 1
+#define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR)
+#define F_CL1_WR_DATA_TO_ERROR V_CL1_WR_DATA_TO_ERROR(1U)
+
+#define S_CL0_WR_DATA_TO_ERROR 0
+#define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR)
+#define F_CL0_WR_DATA_TO_ERROR V_CL0_WR_DATA_TO_ERROR(1U)
+
+#define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
+
+#define S_CL12_RD_CMD_TO_EN 28
+#define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN)
+#define F_CL12_RD_CMD_TO_EN V_CL12_RD_CMD_TO_EN(1U)
+
+#define S_CL11_RD_CMD_TO_EN 27
+#define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN)
+#define F_CL11_RD_CMD_TO_EN V_CL11_RD_CMD_TO_EN(1U)
+
+#define S_CL10_RD_CMD_TO_EN 26
+#define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN)
+#define F_CL10_RD_CMD_TO_EN V_CL10_RD_CMD_TO_EN(1U)
+
+#define S_CL9_RD_CMD_TO_EN 25
+#define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN)
+#define F_CL9_RD_CMD_TO_EN V_CL9_RD_CMD_TO_EN(1U)
+
+#define S_CL8_RD_CMD_TO_EN 24
+#define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN)
+#define F_CL8_RD_CMD_TO_EN V_CL8_RD_CMD_TO_EN(1U)
+
+#define S_CL7_RD_CMD_TO_EN 23
+#define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN)
+#define F_CL7_RD_CMD_TO_EN V_CL7_RD_CMD_TO_EN(1U)
+
+#define S_CL6_RD_CMD_TO_EN 22
+#define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN)
+#define F_CL6_RD_CMD_TO_EN V_CL6_RD_CMD_TO_EN(1U)
+
+#define S_CL5_RD_CMD_TO_EN 21
+#define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN)
+#define F_CL5_RD_CMD_TO_EN V_CL5_RD_CMD_TO_EN(1U)
+
+#define S_CL4_RD_CMD_TO_EN 20
+#define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN)
+#define F_CL4_RD_CMD_TO_EN V_CL4_RD_CMD_TO_EN(1U)
+
+#define S_CL3_RD_CMD_TO_EN 19
+#define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN)
+#define F_CL3_RD_CMD_TO_EN V_CL3_RD_CMD_TO_EN(1U)
+
+#define S_CL2_RD_CMD_TO_EN 18
+#define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN)
+#define F_CL2_RD_CMD_TO_EN V_CL2_RD_CMD_TO_EN(1U)
+
+#define S_CL1_RD_CMD_TO_EN 17
+#define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN)
+#define F_CL1_RD_CMD_TO_EN V_CL1_RD_CMD_TO_EN(1U)
+
+#define S_CL0_RD_CMD_TO_EN 16
+#define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN)
+#define F_CL0_RD_CMD_TO_EN V_CL0_RD_CMD_TO_EN(1U)
+
+#define S_CL12_RD_DATA_TO_EN 12
+#define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN)
+#define F_CL12_RD_DATA_TO_EN V_CL12_RD_DATA_TO_EN(1U)
+
+#define S_CL11_RD_DATA_TO_EN 11
+#define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN)
+#define F_CL11_RD_DATA_TO_EN V_CL11_RD_DATA_TO_EN(1U)
+
+#define S_CL10_RD_DATA_TO_EN 10
+#define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN)
+#define F_CL10_RD_DATA_TO_EN V_CL10_RD_DATA_TO_EN(1U)
+
+#define S_CL9_RD_DATA_TO_EN 9
+#define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN)
+#define F_CL9_RD_DATA_TO_EN V_CL9_RD_DATA_TO_EN(1U)
+
+#define S_CL8_RD_DATA_TO_EN 8
+#define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN)
+#define F_CL8_RD_DATA_TO_EN V_CL8_RD_DATA_TO_EN(1U)
+
+#define S_CL7_RD_DATA_TO_EN 7
+#define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN)
+#define F_CL7_RD_DATA_TO_EN V_CL7_RD_DATA_TO_EN(1U)
+
+#define S_CL6_RD_DATA_TO_EN 6
+#define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN)
+#define F_CL6_RD_DATA_TO_EN V_CL6_RD_DATA_TO_EN(1U)
+
+#define S_CL5_RD_DATA_TO_EN 5
+#define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN)
+#define F_CL5_RD_DATA_TO_EN V_CL5_RD_DATA_TO_EN(1U)
+
+#define S_CL4_RD_DATA_TO_EN 4
+#define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN)
+#define F_CL4_RD_DATA_TO_EN V_CL4_RD_DATA_TO_EN(1U)
+
+#define S_CL3_RD_DATA_TO_EN 3
+#define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN)
+#define F_CL3_RD_DATA_TO_EN V_CL3_RD_DATA_TO_EN(1U)
+
+#define S_CL2_RD_DATA_TO_EN 2
+#define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN)
+#define F_CL2_RD_DATA_TO_EN V_CL2_RD_DATA_TO_EN(1U)
+
+#define S_CL1_RD_DATA_TO_EN 1
+#define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN)
+#define F_CL1_RD_DATA_TO_EN V_CL1_RD_DATA_TO_EN(1U)
+
+#define S_CL0_RD_DATA_TO_EN 0
+#define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN)
+#define F_CL0_RD_DATA_TO_EN V_CL0_RD_DATA_TO_EN(1U)
+
+#define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
+
+#define S_CL12_RD_CMD_TO_ERROR 28
+#define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR)
+#define F_CL12_RD_CMD_TO_ERROR V_CL12_RD_CMD_TO_ERROR(1U)
+
+#define S_CL11_RD_CMD_TO_ERROR 27
+#define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR)
+#define F_CL11_RD_CMD_TO_ERROR V_CL11_RD_CMD_TO_ERROR(1U)
+
+#define S_CL10_RD_CMD_TO_ERROR 26
+#define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR)
+#define F_CL10_RD_CMD_TO_ERROR V_CL10_RD_CMD_TO_ERROR(1U)
+
+#define S_CL9_RD_CMD_TO_ERROR 25
+#define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR)
+#define F_CL9_RD_CMD_TO_ERROR V_CL9_RD_CMD_TO_ERROR(1U)
+
+#define S_CL8_RD_CMD_TO_ERROR 24
+#define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR)
+#define F_CL8_RD_CMD_TO_ERROR V_CL8_RD_CMD_TO_ERROR(1U)
+
+#define S_CL7_RD_CMD_TO_ERROR 23
+#define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR)
+#define F_CL7_RD_CMD_TO_ERROR V_CL7_RD_CMD_TO_ERROR(1U)
+
+#define S_CL6_RD_CMD_TO_ERROR 22
+#define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR)
+#define F_CL6_RD_CMD_TO_ERROR V_CL6_RD_CMD_TO_ERROR(1U)
+
+#define S_CL5_RD_CMD_TO_ERROR 21
+#define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR)
+#define F_CL5_RD_CMD_TO_ERROR V_CL5_RD_CMD_TO_ERROR(1U)
+
+#define S_CL4_RD_CMD_TO_ERROR 20
+#define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR)
+#define F_CL4_RD_CMD_TO_ERROR V_CL4_RD_CMD_TO_ERROR(1U)
+
+#define S_CL3_RD_CMD_TO_ERROR 19
+#define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR)
+#define F_CL3_RD_CMD_TO_ERROR V_CL3_RD_CMD_TO_ERROR(1U)
+
+#define S_CL2_RD_CMD_TO_ERROR 18
+#define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR)
+#define F_CL2_RD_CMD_TO_ERROR V_CL2_RD_CMD_TO_ERROR(1U)
+
+#define S_CL1_RD_CMD_TO_ERROR 17
+#define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR)
+#define F_CL1_RD_CMD_TO_ERROR V_CL1_RD_CMD_TO_ERROR(1U)
+
+#define S_CL0_RD_CMD_TO_ERROR 16
+#define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR)
+#define F_CL0_RD_CMD_TO_ERROR V_CL0_RD_CMD_TO_ERROR(1U)
+
+#define S_CL12_RD_DATA_TO_ERROR 12
+#define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR)
+#define F_CL12_RD_DATA_TO_ERROR V_CL12_RD_DATA_TO_ERROR(1U)
+
+#define S_CL11_RD_DATA_TO_ERROR 11
+#define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR)
+#define F_CL11_RD_DATA_TO_ERROR V_CL11_RD_DATA_TO_ERROR(1U)
+
+#define S_CL10_RD_DATA_TO_ERROR 10
+#define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR)
+#define F_CL10_RD_DATA_TO_ERROR V_CL10_RD_DATA_TO_ERROR(1U)
+
+#define S_CL9_RD_DATA_TO_ERROR 9
+#define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR)
+#define F_CL9_RD_DATA_TO_ERROR V_CL9_RD_DATA_TO_ERROR(1U)
+
+#define S_CL8_RD_DATA_TO_ERROR 8
+#define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR)
+#define F_CL8_RD_DATA_TO_ERROR V_CL8_RD_DATA_TO_ERROR(1U)
+
+#define S_CL7_RD_DATA_TO_ERROR 7
+#define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR)
+#define F_CL7_RD_DATA_TO_ERROR V_CL7_RD_DATA_TO_ERROR(1U)
+
+#define S_CL6_RD_DATA_TO_ERROR 6
+#define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR)
+#define F_CL6_RD_DATA_TO_ERROR V_CL6_RD_DATA_TO_ERROR(1U)
+
+#define S_CL5_RD_DATA_TO_ERROR 5
+#define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR)
+#define F_CL5_RD_DATA_TO_ERROR V_CL5_RD_DATA_TO_ERROR(1U)
+
+#define S_CL4_RD_DATA_TO_ERROR 4
+#define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR)
+#define F_CL4_RD_DATA_TO_ERROR V_CL4_RD_DATA_TO_ERROR(1U)
+
+#define S_CL3_RD_DATA_TO_ERROR 3
+#define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR)
+#define F_CL3_RD_DATA_TO_ERROR V_CL3_RD_DATA_TO_ERROR(1U)
+
+#define S_CL2_RD_DATA_TO_ERROR 2
+#define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR)
+#define F_CL2_RD_DATA_TO_ERROR V_CL2_RD_DATA_TO_ERROR(1U)
+
+#define S_CL1_RD_DATA_TO_ERROR 1
+#define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR)
+#define F_CL1_RD_DATA_TO_ERROR V_CL1_RD_DATA_TO_ERROR(1U)
+
+#define S_CL0_RD_DATA_TO_ERROR 0
+#define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR)
+#define F_CL0_RD_DATA_TO_ERROR V_CL0_RD_DATA_TO_ERROR(1U)
+
+#define A_MA_BKP_CNT_SEL 0x78e4
+
+#define S_BKP_CNT_TYPE 30
+#define M_BKP_CNT_TYPE 0x3U
+#define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE)
+#define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE)
+
+#define S_BKP_CLIENT 24
+#define M_BKP_CLIENT 0xfU
+#define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT)
+#define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT)
+
+#define A_MA_BKP_CNT 0x78e8
+#define A_MA_WRT_ARB 0x78ec
+
+#define S_WRT_EN 31
+#define V_WRT_EN(x) ((x) << S_WRT_EN)
+#define F_WRT_EN V_WRT_EN(1U)
+
+#define S_WR_TIM 16
+#define M_WR_TIM 0xffU
+#define V_WR_TIM(x) ((x) << S_WR_TIM)
+#define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM)
+
+#define S_RD_WIN 8
+#define M_RD_WIN 0xffU
+#define V_RD_WIN(x) ((x) << S_RD_WIN)
+#define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN)
+
+#define S_WR_WIN 0
+#define M_WR_WIN 0xffU
+#define V_WR_WIN(x) ((x) << S_WR_WIN)
+#define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN)
+
+#define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
+
+#define S_CL12_IF_PAR_EN 12
+#define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN)
+#define F_CL12_IF_PAR_EN V_CL12_IF_PAR_EN(1U)
+
+#define S_CL11_IF_PAR_EN 11
+#define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN)
+#define F_CL11_IF_PAR_EN V_CL11_IF_PAR_EN(1U)
+
+#define S_CL10_IF_PAR_EN 10
+#define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN)
+#define F_CL10_IF_PAR_EN V_CL10_IF_PAR_EN(1U)
+
+#define S_CL9_IF_PAR_EN 9
+#define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN)
+#define F_CL9_IF_PAR_EN V_CL9_IF_PAR_EN(1U)
+
+#define S_CL8_IF_PAR_EN 8
+#define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN)
+#define F_CL8_IF_PAR_EN V_CL8_IF_PAR_EN(1U)
+
+#define S_CL7_IF_PAR_EN 7
+#define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN)
+#define F_CL7_IF_PAR_EN V_CL7_IF_PAR_EN(1U)
+
+#define S_CL6_IF_PAR_EN 6
+#define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN)
+#define F_CL6_IF_PAR_EN V_CL6_IF_PAR_EN(1U)
+
+#define S_CL5_IF_PAR_EN 5
+#define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN)
+#define F_CL5_IF_PAR_EN V_CL5_IF_PAR_EN(1U)
+
+#define S_CL4_IF_PAR_EN 4
+#define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN)
+#define F_CL4_IF_PAR_EN V_CL4_IF_PAR_EN(1U)
+
+#define S_CL3_IF_PAR_EN 3
+#define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN)
+#define F_CL3_IF_PAR_EN V_CL3_IF_PAR_EN(1U)
+
+#define S_CL2_IF_PAR_EN 2
+#define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN)
+#define F_CL2_IF_PAR_EN V_CL2_IF_PAR_EN(1U)
+
+#define S_CL1_IF_PAR_EN 1
+#define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN)
+#define F_CL1_IF_PAR_EN V_CL1_IF_PAR_EN(1U)
+
+#define S_CL0_IF_PAR_EN 0
+#define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN)
+#define F_CL0_IF_PAR_EN V_CL0_IF_PAR_EN(1U)
+
+#define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
+
+#define S_CL12_IF_PAR_ERROR 12
+#define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
+#define F_CL12_IF_PAR_ERROR V_CL12_IF_PAR_ERROR(1U)
+
+#define S_CL11_IF_PAR_ERROR 11
+#define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR)
+#define F_CL11_IF_PAR_ERROR V_CL11_IF_PAR_ERROR(1U)
+
+#define S_CL10_IF_PAR_ERROR 10
+#define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR)
+#define F_CL10_IF_PAR_ERROR V_CL10_IF_PAR_ERROR(1U)
+
+#define S_CL9_IF_PAR_ERROR 9
+#define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR)
+#define F_CL9_IF_PAR_ERROR V_CL9_IF_PAR_ERROR(1U)
+
+#define S_CL8_IF_PAR_ERROR 8
+#define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR)
+#define F_CL8_IF_PAR_ERROR V_CL8_IF_PAR_ERROR(1U)
+
+#define S_CL7_IF_PAR_ERROR 7
+#define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR)
+#define F_CL7_IF_PAR_ERROR V_CL7_IF_PAR_ERROR(1U)
+
+#define S_CL6_IF_PAR_ERROR 6
+#define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR)
+#define F_CL6_IF_PAR_ERROR V_CL6_IF_PAR_ERROR(1U)
+
+#define S_CL5_IF_PAR_ERROR 5
+#define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR)
+#define F_CL5_IF_PAR_ERROR V_CL5_IF_PAR_ERROR(1U)
+
+#define S_CL4_IF_PAR_ERROR 4
+#define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR)
+#define F_CL4_IF_PAR_ERROR V_CL4_IF_PAR_ERROR(1U)
+
+#define S_CL3_IF_PAR_ERROR 3
+#define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR)
+#define F_CL3_IF_PAR_ERROR V_CL3_IF_PAR_ERROR(1U)
+
+#define S_CL2_IF_PAR_ERROR 2
+#define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR)
+#define F_CL2_IF_PAR_ERROR V_CL2_IF_PAR_ERROR(1U)
+
+#define S_CL1_IF_PAR_ERROR 1
+#define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR)
+#define F_CL1_IF_PAR_ERROR V_CL1_IF_PAR_ERROR(1U)
+
+#define S_CL0_IF_PAR_ERROR 0
+#define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR)
+#define F_CL0_IF_PAR_ERROR V_CL0_IF_PAR_ERROR(1U)
+
+#define A_MA_LOCAL_DEBUG_CFG 0x78f8
+
+#define S_DEBUG_OR 15
+#define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
+#define F_DEBUG_OR V_DEBUG_OR(1U)
+
+#define S_DEBUG_HI 14
+#define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
+#define F_DEBUG_HI V_DEBUG_HI(1U)
+
+#define S_DEBUG_RPT 13
+#define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
+#define F_DEBUG_RPT V_DEBUG_RPT(1U)
+
+#define S_DEBUGPAGE 10
+#define M_DEBUGPAGE 0x7U
+#define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
+#define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
+
+#define A_MA_LOCAL_DEBUG_RPT 0x78fc
+
/* registers for module EDC_0 */
#define EDC_0_BASE_ADDR 0x7900
@@ -7011,6 +12365,7 @@
#define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
#define F_MBMSGRDYINT V_MBMSGRDYINT(1U)
+#define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
#define A_CIM_BOOT_CFG 0x7b00
#define S_BOOTADDR 8
@@ -7180,6 +12535,38 @@
#define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
#define F_PREFDROPINTEN V_PREFDROPINTEN(1U)
+#define S_MA_CIM_INTFPERR 28
+#define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
+#define F_MA_CIM_INTFPERR V_MA_CIM_INTFPERR(1U)
+
+#define S_PLCIM_MSTRSPDATAPARERR 27
+#define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
+#define F_PLCIM_MSTRSPDATAPARERR V_PLCIM_MSTRSPDATAPARERR(1U)
+
+#define S_NCSI2CIMINTFPARERR 26
+#define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
+#define F_NCSI2CIMINTFPARERR V_NCSI2CIMINTFPARERR(1U)
+
+#define S_SGE2CIMINTFPARERR 25
+#define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
+#define F_SGE2CIMINTFPARERR V_SGE2CIMINTFPARERR(1U)
+
+#define S_ULP2CIMINTFPARERR 24
+#define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
+#define F_ULP2CIMINTFPARERR V_ULP2CIMINTFPARERR(1U)
+
+#define S_TP2CIMINTFPARERR 23
+#define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
+#define F_TP2CIMINTFPARERR V_TP2CIMINTFPARERR(1U)
+
+#define S_OBQSGERX1PARERR 22
+#define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
+#define F_OBQSGERX1PARERR V_OBQSGERX1PARERR(1U)
+
+#define S_OBQSGERX0PARERR 21
+#define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
+#define F_OBQSGERX0PARERR V_OBQSGERX0PARERR(1U)
+
#define A_CIM_HOST_INT_CAUSE 0x7b2c
#define S_TIEQOUTPARERRINT 20
@@ -7738,6 +13125,11 @@
#define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK)
#define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK)
+#define S_T5_DPIFHOSTMASK 0
+#define M_T5_DPIFHOSTMASK 0x1fffffffU
+#define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK)
+#define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK)
+
#define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
#define S_DPIFHUPAMASK 0
@@ -7752,6 +13144,11 @@
#define V_DUPMASK(x) ((x) << S_DUPMASK)
#define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK)
+#define S_T5_DUPMASK 0
+#define M_T5_DUPMASK 0x1fffffffU
+#define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK)
+#define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK)
+
#define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
#define S_DUPUACCMASK 0
@@ -7767,6 +13164,11 @@
#define V_PERREN(x) ((x) << S_PERREN)
#define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN)
+#define S_T5_PERREN 0
+#define M_T5_PERREN 0x1fffffffU
+#define V_T5_PERREN(x) ((x) << S_T5_PERREN)
+#define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN)
+
#define A_CIM_EEPROM_BUSY_BIT 0x7c28
#define S_EEPROMBUSY 0
@@ -7787,6 +13189,69 @@
#define A_CIM_CIM_DEBUG_SPARE 0x7c34
#define A_CIM_UP_OPERATION_FREQ 0x7c38
+#define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c
+
+#define S_CIM_ULP_TX_PKT_ERR_CODE 16
+#define M_CIM_ULP_TX_PKT_ERR_CODE 0xffU
+#define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE)
+#define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE)
+
+#define S_CIM_SGE1_PKT_ERR_CODE 8
+#define M_CIM_SGE1_PKT_ERR_CODE 0xffU
+#define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE)
+#define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE)
+
+#define S_CIM_SGE0_PKT_ERR_CODE 0
+#define M_CIM_SGE0_PKT_ERR_CODE 0xffU
+#define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
+#define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
+
+#define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
+#define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
+
+#define S_PIO_UP_MST_CFG_SEL 0
+#define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL)
+#define F_PIO_UP_MST_CFG_SEL V_PIO_UP_MST_CFG_SEL(1U)
+
+#define A_CIM_CGEN 0x7c48
+
+#define S_TSCH_CGEN 0
+#define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN)
+#define F_TSCH_CGEN V_TSCH_CGEN(1U)
+
+#define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c
+
+#define S_OBQ_THROUTTLE_ON_EOP 4
+#define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP)
+#define F_OBQ_THROUTTLE_ON_EOP V_OBQ_THROUTTLE_ON_EOP(1U)
+
+#define S_OBQ_READ_CTL_PERF_MODE_DISABLE 3
+#define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE)
+#define F_OBQ_READ_CTL_PERF_MODE_DISABLE V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U)
+
+#define S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE 2
+#define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE)
+#define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U)
+
+#define S_IBQ_RRA_DSBL 1
+#define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL)
+#define F_IBQ_RRA_DSBL V_IBQ_RRA_DSBL(1U)
+
+#define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL 0
+#define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL)
+#define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U)
+
+#define A_CIM_CGEN_GLOBAL 0x7c50
+
+#define S_CGEN_GLOBAL 0
+#define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL)
+#define F_CGEN_GLOBAL V_CGEN_GLOBAL(1U)
+
+#define A_CIM_DPSLP_EN 0x7c54
+
+#define S_PIFDBGLA_DPSLP_EN 0
+#define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN)
+#define F_PIFDBGLA_DPSLP_EN V_PIFDBGLA_DPSLP_EN(1U)
/* registers for module TP */
#define TP_BASE_ADDR 0x7d00
@@ -7897,6 +13362,58 @@
#define V_CTUNNEL(x) ((x) << S_CTUNNEL)
#define F_CTUNNEL V_CTUNNEL(1U)
+#define S_VLANEXTENPORT3 31
+#define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3)
+#define F_VLANEXTENPORT3 V_VLANEXTENPORT3(1U)
+
+#define S_VLANEXTENPORT2 30
+#define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2)
+#define F_VLANEXTENPORT2 V_VLANEXTENPORT2(1U)
+
+#define S_VLANEXTENPORT1 29
+#define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1)
+#define F_VLANEXTENPORT1 V_VLANEXTENPORT1(1U)
+
+#define S_VLANEXTENPORT0 28
+#define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0)
+#define F_VLANEXTENPORT0 V_VLANEXTENPORT0(1U)
+
+#define S_VNTAGDEFAULTVAL 13
+#define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL)
+#define F_VNTAGDEFAULTVAL V_VNTAGDEFAULTVAL(1U)
+
+#define S_ECHECKUDPLEN 12
+#define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN)
+#define F_ECHECKUDPLEN V_ECHECKUDPLEN(1U)
+
+#define S_FCOEFPMA 10
+#define V_FCOEFPMA(x) ((x) << S_FCOEFPMA)
+#define F_FCOEFPMA V_FCOEFPMA(1U)
+
+#define S_VNTAGETHENABLE 8
+#define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE)
+#define F_VNTAGETHENABLE V_VNTAGETHENABLE(1U)
+
+#define S_IP_CCSM 7
+#define V_IP_CCSM(x) ((x) << S_IP_CCSM)
+#define F_IP_CCSM V_IP_CCSM(1U)
+
+#define S_CCHECKSUMCHECKUDP 6
+#define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP)
+#define F_CCHECKSUMCHECKUDP V_CCHECKSUMCHECKUDP(1U)
+
+#define S_TCP_CCSM 5
+#define V_TCP_CCSM(x) ((x) << S_TCP_CCSM)
+#define F_TCP_CCSM V_TCP_CCSM(1U)
+
+#define S_CDEMUX 3
+#define V_CDEMUX(x) ((x) << S_CDEMUX)
+#define F_CDEMUX V_CDEMUX(1U)
+
+#define S_ETHUPEN 2
+#define V_ETHUPEN(x) ((x) << S_ETHUPEN)
+#define F_ETHUPEN V_ETHUPEN(1U)
+
#define A_TP_OUT_CONFIG 0x7d04
#define S_PORTQFCEN 28
@@ -7988,6 +13505,10 @@
#define V_CETHERNET(x) ((x) << S_CETHERNET)
#define F_CETHERNET V_CETHERNET(1U)
+#define S_EVNTAGEN 9
+#define V_EVNTAGEN(x) ((x) << S_EVNTAGEN)
+#define F_EVNTAGEN V_EVNTAGEN(1U)
+
#define A_TP_GLOBAL_CONFIG 0x7d08
#define S_SYNCOOKIEPARAMS 26
@@ -8066,6 +13587,14 @@
#define V_IPTTL(x) ((x) << S_IPTTL)
#define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
+#define S_RSSSYNSTEERENABLE 12
+#define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
+#define F_RSSSYNSTEERENABLE V_RSSSYNSTEERENABLE(1U)
+
+#define S_ISSFROMCPLENABLE 11
+#define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
+#define F_ISSFROMCPLENABLE V_ISSFROMCPLENABLE(1U)
+
#define A_TP_DB_CONFIG 0x7d0c
#define S_DBMAXOPCNT 24
@@ -8346,6 +13875,10 @@
#define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE)
#define F_TXDATAACKPAGEENABLE V_TXDATAACKPAGEENABLE(1U)
+#define S_ENABLEFILTERNAT 5
+#define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT)
+#define F_ENABLEFILTERNAT V_ENABLEFILTERNAT(1U)
+
#define A_TP_PC_CONFIG2 0x7d4c
#define S_ENABLEMTUVFMODE 31
@@ -8476,6 +14009,10 @@
#define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED)
#define F_ENABLETNLOFDCLOSED V_ENABLETNLOFDCLOSED(1U)
+#define S_ENABLEFINDDPOFF 14
+#define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF)
+#define F_ENABLEFINDDPOFF V_ENABLEFINDDPOFF(1U)
+
#define A_TP_TCP_BACKOFF_REG0 0x7d50
#define S_TIMERBACKOFFINDEX3 24
@@ -8626,6 +14163,19 @@
#define V_SWSTIMER(x) ((x) << S_SWSTIMER)
#define F_SWSTIMER V_SWSTIMER(1U)
+#define S_LIMTXTHRESH 28
+#define M_LIMTXTHRESH 0xfU
+#define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH)
+#define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH)
+
+#define S_CHNERRENABLE 14
+#define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE)
+#define F_CHNERRENABLE V_CHNERRENABLE(1U)
+
+#define S_SETTIMEENABLE 13
+#define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE)
+#define F_SETTIMEENABLE V_SETTIMEENABLE(1U)
+
#define A_TP_PARA_REG1 0x7d64
#define S_INITRWND 16
@@ -8777,6 +14327,74 @@
#define V_RENOCFG(x) ((x) << S_RENOCFG)
#define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
+#define S_IDLECWNDHIGHSPEED 28
+#define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED)
+#define F_IDLECWNDHIGHSPEED V_IDLECWNDHIGHSPEED(1U)
+
+#define S_RXMTCWNDHIGHSPEED 27
+#define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED)
+#define F_RXMTCWNDHIGHSPEED V_RXMTCWNDHIGHSPEED(1U)
+
+#define S_OVERDRIVEHIGHSPEED 25
+#define M_OVERDRIVEHIGHSPEED 0x3U
+#define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED)
+#define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED)
+
+#define S_BYTECOUNTHIGHSPEED 24
+#define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED)
+#define F_BYTECOUNTHIGHSPEED V_BYTECOUNTHIGHSPEED(1U)
+
+#define S_IDLECWNDNEWRENO 20
+#define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO)
+#define F_IDLECWNDNEWRENO V_IDLECWNDNEWRENO(1U)
+
+#define S_RXMTCWNDNEWRENO 19
+#define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO)
+#define F_RXMTCWNDNEWRENO V_RXMTCWNDNEWRENO(1U)
+
+#define S_OVERDRIVENEWRENO 17
+#define M_OVERDRIVENEWRENO 0x3U
+#define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO)
+#define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO)
+
+#define S_BYTECOUNTNEWRENO 16
+#define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO)
+#define F_BYTECOUNTNEWRENO V_BYTECOUNTNEWRENO(1U)
+
+#define S_IDLECWNDTAHOE 12
+#define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE)
+#define F_IDLECWNDTAHOE V_IDLECWNDTAHOE(1U)
+
+#define S_RXMTCWNDTAHOE 11
+#define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE)
+#define F_RXMTCWNDTAHOE V_RXMTCWNDTAHOE(1U)
+
+#define S_OVERDRIVETAHOE 9
+#define M_OVERDRIVETAHOE 0x3U
+#define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE)
+#define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE)
+
+#define S_BYTECOUNTTAHOE 8
+#define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE)
+#define F_BYTECOUNTTAHOE V_BYTECOUNTTAHOE(1U)
+
+#define S_IDLECWNDRENO 4
+#define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO)
+#define F_IDLECWNDRENO V_IDLECWNDRENO(1U)
+
+#define S_RXMTCWNDRENO 3
+#define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO)
+#define F_RXMTCWNDRENO V_RXMTCWNDRENO(1U)
+
+#define S_OVERDRIVERENO 1
+#define M_OVERDRIVERENO 0x3U
+#define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO)
+#define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO)
+
+#define S_BYTECOUNTRENO 0
+#define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO)
+#define F_BYTECOUNTRENO V_BYTECOUNTRENO(1U)
+
#define A_TP_PARA_REG5 0x7d74
#define S_INDICATESIZE 16
@@ -8825,6 +14443,18 @@
#define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
#define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U)
+#define S_ENABLEXOFFPDU 7
+#define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU)
+#define F_ENABLEXOFFPDU V_ENABLEXOFFPDU(1U)
+
+#define S_ENABLENEWFAR 6
+#define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR)
+#define F_ENABLENEWFAR V_ENABLENEWFAR(1U)
+
+#define S_ENABLEFRAGCHECK 5
+#define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK)
+#define F_ENABLEFRAGCHECK V_ENABLEFRAGCHECK(1U)
+
#define A_TP_PARA_REG6 0x7d78
#define S_TXPDUSIZEADJ 24
@@ -8917,6 +14547,10 @@
#define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
#define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U)
+#define S_DISABLEPDUACK 20
+#define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK)
+#define F_DISABLEPDUACK V_DISABLEPDUACK(1U)
+
#define A_TP_PARA_REG7 0x7d7c
#define S_PMMAXXFERLEN1 16
@@ -9072,6 +14706,14 @@
#define V_DROPERRORANY(x) ((x) << S_DROPERRORANY)
#define F_DROPERRORANY V_DROPERRORANY(1U)
+#define S_TNLERRORFPMA 31
+#define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA)
+#define F_TNLERRORFPMA V_TNLERRORFPMA(1U)
+
+#define S_DROPERRORFPMA 15
+#define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA)
+#define F_DROPERRORFPMA V_DROPERRORFPMA(1U)
+
#define A_TP_TIMER_RESOLUTION 0x7d90
#define S_TIMERRESOLUTION 16
@@ -9448,6 +15090,18 @@
#define V_DISABLE(x) ((x) << S_DISABLE)
#define F_DISABLE V_DISABLE(1U)
+#define S_TNLFCOEMODE 23
+#define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
+#define F_TNLFCOEMODE V_TNLFCOEMODE(1U)
+
+#define S_TNLFCOEEN 21
+#define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
+#define F_TNLFCOEEN V_TNLFCOEEN(1U)
+
+#define S_HASHXOR 20
+#define V_HASHXOR(x) ((x) << S_HASHXOR)
+#define F_HASHXOR V_HASHXOR(1U)
+
#define A_TP_RSS_CONFIG_TNL 0x7df4
#define S_MASKSIZE 28
@@ -9475,6 +15129,11 @@
#define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
#define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
+#define S_FRMWRQUEMASK 12
+#define M_FRMWRQUEMASK 0xfU
+#define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
+#define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
+
#define A_TP_RSS_CONFIG_SYN 0x7dfc
#define A_TP_RSS_CONFIG_VRT 0x7e00
@@ -9530,6 +15189,14 @@
#define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
#define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
+#define S_VFVLANEN 21
+#define V_VFVLANEN(x) ((x) << S_VFVLANEN)
+#define F_VFVLANEN V_VFVLANEN(1U)
+
+#define S_VFFWEN 20
+#define V_VFFWEN(x) ((x) << S_VFFWEN)
+#define F_VFFWEN V_VFFWEN(1U)
+
#define A_TP_RSS_CONFIG_CNG 0x7e04
#define S_CHNCOUNT3 31
@@ -9909,6 +15576,10 @@
#define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR)
#define F_DELINVFIFOPERR V_DELINVFIFOPERR(1U)
+#define S_CTPOUTPLDFIFOPERR 7
+#define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR)
+#define F_CTPOUTPLDFIFOPERR V_CTPOUTPLDFIFOPERR(1U)
+
#define A_TP_INT_CAUSE 0x7e74
#define A_TP_PER_ENABLE 0x7e78
#define A_TP_FLM_FREE_PS_CNT 0x7e80
@@ -9958,6 +15629,7 @@
#define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE)
#define F_DISABLETIMEFREEZE V_DISABLETIMEFREEZE(1U)
+#define A_TP_STAMP_TIME 0x7ea8
#define A_TP_DEBUG_FLAGS 0x7eac
#define S_RXTIMERDACKFIRST 26
@@ -10052,6 +15724,18 @@
#define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
#define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U)
+#define S_RXTIMERCOMPBUFFER 27
+#define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER)
+#define F_RXTIMERCOMPBUFFER V_RXTIMERCOMPBUFFER(1U)
+
+#define S_TXDFRFAST 13
+#define V_TXDFRFAST(x) ((x) << S_TXDFRFAST)
+#define F_TXDFRFAST V_TXDFRFAST(1U)
+
+#define S_TXRXMMISC 12
+#define V_TXRXMMISC(x) ((x) << S_TXRXMMISC)
+#define F_TXRXMMISC V_TXRXMMISC(1U)
+
#define A_TP_RX_SCHED 0x7eb0
#define S_RXCOMMITRESET1 31
@@ -10852,6 +16536,28 @@
#define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0)
#define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0)
+#define A_TP_RX_SCHED_FIFO 0x2b
+
+#define S_COMMITLIMIT1H 24
+#define M_COMMITLIMIT1H 0xffU
+#define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H)
+#define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H)
+
+#define S_COMMITLIMIT1L 16
+#define M_COMMITLIMIT1L 0xffU
+#define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L)
+#define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L)
+
+#define S_COMMITLIMIT0H 8
+#define M_COMMITLIMIT0H 0xffU
+#define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H)
+#define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H)
+
+#define S_COMMITLIMIT0L 0
+#define M_COMMITLIMIT0L 0xffU
+#define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L)
+#define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L)
+
#define A_TP_IPMI_CFG1 0x2e
#define S_VLANENABLE 31
@@ -11120,6 +16826,90 @@
#define V_IPV4TYPE(x) ((x) << S_IPV4TYPE)
#define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE)
+#define A_TP_ETHER_TYPE_FW 0x52
+
+#define S_ETHTYPE1 16
+#define M_ETHTYPE1 0xffffU
+#define V_ETHTYPE1(x) ((x) << S_ETHTYPE1)
+#define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1)
+
+#define S_ETHTYPE0 0
+#define M_ETHTYPE0 0xffffU
+#define V_ETHTYPE0(x) ((x) << S_ETHTYPE0)
+#define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0)
+
+#define A_TP_CORE_POWER 0x54
+
+#define S_SLEEPRDYVNT 12
+#define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT)
+#define F_SLEEPRDYVNT V_SLEEPRDYVNT(1U)
+
+#define S_SLEEPRDYTBL 11
+#define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL)
+#define F_SLEEPRDYTBL V_SLEEPRDYTBL(1U)
+
+#define S_SLEEPRDYMIB 10
+#define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB)
+#define F_SLEEPRDYMIB V_SLEEPRDYMIB(1U)
+
+#define S_SLEEPRDYARP 9
+#define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP)
+#define F_SLEEPRDYARP V_SLEEPRDYARP(1U)
+
+#define S_SLEEPRDYRSS 8
+#define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS)
+#define F_SLEEPRDYRSS V_SLEEPRDYRSS(1U)
+
+#define S_SLEEPREQVNT 4
+#define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT)
+#define F_SLEEPREQVNT V_SLEEPREQVNT(1U)
+
+#define S_SLEEPREQTBL 3
+#define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL)
+#define F_SLEEPREQTBL V_SLEEPREQTBL(1U)
+
+#define S_SLEEPREQMIB 2
+#define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB)
+#define F_SLEEPREQMIB V_SLEEPREQMIB(1U)
+
+#define S_SLEEPREQARP 1
+#define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP)
+#define F_SLEEPREQARP V_SLEEPREQARP(1U)
+
+#define S_SLEEPREQRSS 0
+#define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS)
+#define F_SLEEPREQRSS V_SLEEPREQRSS(1U)
+
+#define A_TP_CORE_RDMA 0x55
+
+#define S_IMMEDIATEOP 20
+#define M_IMMEDIATEOP 0xfU
+#define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP)
+#define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP)
+
+#define S_IMMEDIATESE 16
+#define M_IMMEDIATESE 0xfU
+#define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE)
+#define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE)
+
+#define S_ATOMICREQOP 12
+#define M_ATOMICREQOP 0xfU
+#define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP)
+#define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP)
+
+#define S_ATOMICRSPOP 8
+#define M_ATOMICRSPOP 0xfU
+#define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP)
+#define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP)
+
+#define S_IMMEDIASEEN 1
+#define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN)
+#define F_IMMEDIASEEN V_IMMEDIASEEN(1U)
+
+#define S_IMMEDIATEEN 0
+#define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN)
+#define F_IMMEDIATEEN V_IMMEDIATEEN(1U)
+
#define A_TP_DBG_CLEAR 0x60
#define A_TP_DBG_CORE_HDR0 0x61
@@ -11239,16 +17029,16 @@
#define V_SRAMFATAL(x) ((x) << S_SRAMFATAL)
#define F_SRAMFATAL V_SRAMFATAL(1U)
-#define S_EPCMDCONG 24
-#define M_EPCMDCONG 0xfU
-#define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
-#define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
-
-#define S_CPCMDCONG 22
-#define M_CPCMDCONG 0x3U
+#define S_CPCMDCONG 24
+#define M_CPCMDCONG 0xfU
#define V_CPCMDCONG(x) ((x) << S_CPCMDCONG)
#define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG)
+#define S_EPCMDCONG 22
+#define M_EPCMDCONG 0x3U
+#define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
+#define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
+
#define S_CPCMDLENFATAL 21
#define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL)
#define F_CPCMDLENFATAL V_CPCMDLENFATAL(1U)
@@ -11295,6 +17085,14 @@
#define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT)
#define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT)
+#define S_CPCMDTTLFATAL 6
+#define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL)
+#define F_CPCMDTTLFATAL V_CPCMDTTLFATAL(1U)
+
+#define S_CDATACHNFATAL 5
+#define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL)
+#define F_CDATACHNFATAL V_CDATACHNFATAL(1U)
+
#define A_TP_DBG_CORE_OUT 0x64
#define S_CCPLENC 26
@@ -11385,6 +17183,46 @@
#define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY)
#define F_EPLDTXZEROPDRDY V_EPLDTXZEROPDRDY(1U)
+#define S_CRXBUSYOUT 31
+#define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT)
+#define F_CRXBUSYOUT V_CRXBUSYOUT(1U)
+
+#define S_CTXBUSYOUT 30
+#define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT)
+#define F_CTXBUSYOUT V_CTXBUSYOUT(1U)
+
+#define S_CRDCPLPKT 29
+#define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT)
+#define F_CRDCPLPKT V_CRDCPLPKT(1U)
+
+#define S_CRDTCPPKT 28
+#define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT)
+#define F_CRDTCPPKT V_CRDTCPPKT(1U)
+
+#define S_CNEWMSG 27
+#define V_CNEWMSG(x) ((x) << S_CNEWMSG)
+#define F_CNEWMSG V_CNEWMSG(1U)
+
+#define S_ERXBUSYOUT 15
+#define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT)
+#define F_ERXBUSYOUT V_ERXBUSYOUT(1U)
+
+#define S_ETXBUSYOUT 14
+#define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT)
+#define F_ETXBUSYOUT V_ETXBUSYOUT(1U)
+
+#define S_ERDCPLPKT 13
+#define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT)
+#define F_ERDCPLPKT V_ERDCPLPKT(1U)
+
+#define S_ERDTCPPKT 12
+#define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT)
+#define F_ERDTCPPKT V_ERDTCPPKT(1U)
+
+#define S_ENEWMSG 11
+#define V_ENEWMSG(x) ((x) << S_ENEWMSG)
+#define F_ENEWMSG V_ENEWMSG(1U)
+
#define A_TP_DBG_CORE_TID 0x65
#define S_LINENUMBER 24
@@ -11405,6 +17243,11 @@
#define V_TIDVALUE(x) ((x) << S_TIDVALUE)
#define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE)
+#define S_SRC 21
+#define M_SRC 0x3U
+#define V_SRC(x) ((x) << S_SRC)
+#define G_SRC(x) (((x) >> S_SRC) & M_SRC)
+
#define A_TP_DBG_ENG_RES0 0x66
#define S_RESOURCESREADY 31
@@ -11502,13 +17345,22 @@
#define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY)
#define F_CPCMDBUSY V_CPCMDBUSY(1U)
-#define S_ETXBUSY 1
+#define S_EPCMDBUSY 1
+#define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
+#define F_EPCMDBUSY V_EPCMDBUSY(1U)
+
+#define S_ETXBUSY 0
#define V_ETXBUSY(x) ((x) << S_ETXBUSY)
#define F_ETXBUSY V_ETXBUSY(1U)
-#define S_EPCMDBUSY 0
-#define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
-#define F_EPCMDBUSY V_EPCMDBUSY(1U)
+#define S_EFFOPCODEOUT 16
+#define M_EFFOPCODEOUT 0xfU
+#define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT)
+#define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT)
+
+#define S_DELDRDY 14
+#define V_DELDRDY(x) ((x) << S_DELDRDY)
+#define F_DELDRDY V_DELDRDY(1U)
#define A_TP_DBG_ENG_RES1 0x67
@@ -11759,6 +17611,49 @@
#define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
#define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
+#define A_TP_DBG_ERROR_CNT 0x6c
+#define A_TP_MIB_DEBUG 0x6f
+
+#define S_SRC3 31
+#define V_SRC3(x) ((x) << S_SRC3)
+#define F_SRC3 V_SRC3(1U)
+
+#define S_LINENUM3 24
+#define M_LINENUM3 0x7fU
+#define V_LINENUM3(x) ((x) << S_LINENUM3)
+#define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3)
+
+#define S_SRC2 23
+#define V_SRC2(x) ((x) << S_SRC2)
+#define F_SRC2 V_SRC2(1U)
+
+#define S_LINENUM2 16
+#define M_LINENUM2 0x7fU
+#define V_LINENUM2(x) ((x) << S_LINENUM2)
+#define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2)
+
+#define S_SRC1 15
+#define V_SRC1(x) ((x) << S_SRC1)
+#define F_SRC1 V_SRC1(1U)
+
+#define S_LINENUM1 8
+#define M_LINENUM1 0x7fU
+#define V_LINENUM1(x) ((x) << S_LINENUM1)
+#define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1)
+
+#define S_SRC0 7
+#define V_SRC0(x) ((x) << S_SRC0)
+#define F_SRC0 V_SRC0(1U)
+
+#define S_LINENUM0 0
+#define M_LINENUM0 0x7fU
+#define V_LINENUM0(x) ((x) << S_LINENUM0)
+#define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0)
+
+#define A_TP_T5_TX_DROP_CNT_CH0 0x120
+#define A_TP_T5_TX_DROP_CNT_CH1 0x121
+#define A_TP_TX_DROP_CNT_CH2 0x122
+#define A_TP_TX_DROP_CNT_CH3 0x123
#define A_TP_TX_DROP_CFG_CH0 0x12b
#define S_TIMERENABLED 31
@@ -12341,6 +18236,18 @@
#define V_FCOE(x) ((x) << S_FCOE)
#define F_FCOE V_FCOE(1U)
+#define S_FILTERMODE 15
+#define V_FILTERMODE(x) ((x) << S_FILTERMODE)
+#define F_FILTERMODE V_FILTERMODE(1U)
+
+#define S_FCOEMASK 14
+#define V_FCOEMASK(x) ((x) << S_FCOEMASK)
+#define F_FCOEMASK V_FCOEMASK(1U)
+
+#define S_SRVRSRAM 13
+#define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
+#define F_SRVRSRAM V_SRVRSRAM(1U)
+
#define A_TP_INGRESS_CONFIG 0x141
#define S_OPAQUE_TYPE 16
@@ -12385,6 +18292,10 @@
#define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
#define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
+#define S_FRAG_LEN_MOD8_COMPAT 12
+#define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
+#define F_FRAG_LEN_MOD8_COMPAT V_FRAG_LEN_MOD8_COMPAT(1U)
+
#define A_TP_TX_DROP_CFG_CH2 0x142
#define A_TP_TX_DROP_CFG_CH3 0x143
#define A_TP_EGRESS_CONFIG 0x145
@@ -12393,6 +18304,31 @@
#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
#define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U)
+#define A_TP_INGRESS_CONFIG2 0x145
+
+#define S_IPV6_UDP_CSUM_COMPAT 31
+#define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT)
+#define F_IPV6_UDP_CSUM_COMPAT V_IPV6_UDP_CSUM_COMPAT(1U)
+
+#define S_VNTAGPLDENABLE 30
+#define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE)
+#define F_VNTAGPLDENABLE V_VNTAGPLDENABLE(1U)
+
+#define S_TCP_PLD_FILTER_OFFSET 20
+#define M_TCP_PLD_FILTER_OFFSET 0x3ffU
+#define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET)
+#define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET)
+
+#define S_UDP_PLD_FILTER_OFFSET 10
+#define M_UDP_PLD_FILTER_OFFSET 0x3ffU
+#define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET)
+#define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET)
+
+#define S_TNL_PLD_FILTER_OFFSET 0
+#define M_TNL_PLD_FILTER_OFFSET 0x3ffU
+#define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET)
+#define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET)
+
#define A_TP_EHDR_CONFIG_LO 0x146
#define S_CPLLIMIT 24
@@ -12652,6 +18588,22 @@
#define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY)
#define F_RX_PKT_ATTR_DRDY V_RX_PKT_ATTR_DRDY(1U)
+#define S_RXRUNT 25
+#define V_RXRUNT(x) ((x) << S_RXRUNT)
+#define F_RXRUNT V_RXRUNT(1U)
+
+#define S_RXRUNTPARSER 24
+#define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER)
+#define F_RXRUNTPARSER V_RXRUNTPARSER(1U)
+
+#define S_ERROR_SRDY 5
+#define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY)
+#define F_ERROR_SRDY V_ERROR_SRDY(1U)
+
+#define S_ERROR_DRDY 4
+#define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY)
+#define F_ERROR_DRDY V_ERROR_DRDY(1U)
+
#define A_TP_DBG_ESIDE_IN1 0x14b
#define A_TP_DBG_ESIDE_IN2 0x14c
#define A_TP_DBG_ESIDE_IN3 0x14d
@@ -12754,6 +18706,162 @@
#define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET)
#define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET)
+#define A_TP_DBG_ESIDE_OP 0x154
+
+#define S_OPT_PARSER_FATAL_CHANNEL0 29
+#define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0)
+#define F_OPT_PARSER_FATAL_CHANNEL0 V_OPT_PARSER_FATAL_CHANNEL0(1U)
+
+#define S_OPT_PARSER_BUSY_CHANNEL0 28
+#define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0)
+#define F_OPT_PARSER_BUSY_CHANNEL0 V_OPT_PARSER_BUSY_CHANNEL0(1U)
+
+#define S_OPT_PARSER_ITCP_STATE_CHANNEL0 26
+#define M_OPT_PARSER_ITCP_STATE_CHANNEL0 0x3U
+#define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0)
+#define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & M_OPT_PARSER_ITCP_STATE_CHANNEL0)
+
+#define S_OPT_PARSER_OTK_STATE_CHANNEL0 24
+#define M_OPT_PARSER_OTK_STATE_CHANNEL0 0x3U
+#define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0)
+#define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & M_OPT_PARSER_OTK_STATE_CHANNEL0)
+
+#define S_OPT_PARSER_FATAL_CHANNEL1 21
+#define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1)
+#define F_OPT_PARSER_FATAL_CHANNEL1 V_OPT_PARSER_FATAL_CHANNEL1(1U)
+
+#define S_OPT_PARSER_BUSY_CHANNEL1 20
+#define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1)
+#define F_OPT_PARSER_BUSY_CHANNEL1 V_OPT_PARSER_BUSY_CHANNEL1(1U)
+
+#define S_OPT_PARSER_ITCP_STATE_CHANNEL1 18
+#define M_OPT_PARSER_ITCP_STATE_CHANNEL1 0x3U
+#define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1)
+#define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & M_OPT_PARSER_ITCP_STATE_CHANNEL1)
+
+#define S_OPT_PARSER_OTK_STATE_CHANNEL1 16
+#define M_OPT_PARSER_OTK_STATE_CHANNEL1 0x3U
+#define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1)
+#define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & M_OPT_PARSER_OTK_STATE_CHANNEL1)
+
+#define S_OPT_PARSER_FATAL_CHANNEL2 13
+#define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2)
+#define F_OPT_PARSER_FATAL_CHANNEL2 V_OPT_PARSER_FATAL_CHANNEL2(1U)
+
+#define S_OPT_PARSER_BUSY_CHANNEL2 12
+#define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2)
+#define F_OPT_PARSER_BUSY_CHANNEL2 V_OPT_PARSER_BUSY_CHANNEL2(1U)
+
+#define S_OPT_PARSER_ITCP_STATE_CHANNEL2 10
+#define M_OPT_PARSER_ITCP_STATE_CHANNEL2 0x3U
+#define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2)
+#define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & M_OPT_PARSER_ITCP_STATE_CHANNEL2)
+
+#define S_OPT_PARSER_OTK_STATE_CHANNEL2 8
+#define M_OPT_PARSER_OTK_STATE_CHANNEL2 0x3U
+#define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2)
+#define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & M_OPT_PARSER_OTK_STATE_CHANNEL2)
+
+#define S_OPT_PARSER_FATAL_CHANNEL3 5
+#define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3)
+#define F_OPT_PARSER_FATAL_CHANNEL3 V_OPT_PARSER_FATAL_CHANNEL3(1U)
+
+#define S_OPT_PARSER_BUSY_CHANNEL3 4
+#define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3)
+#define F_OPT_PARSER_BUSY_CHANNEL3 V_OPT_PARSER_BUSY_CHANNEL3(1U)
+
+#define S_OPT_PARSER_ITCP_STATE_CHANNEL3 2
+#define M_OPT_PARSER_ITCP_STATE_CHANNEL3 0x3U
+#define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3)
+#define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & M_OPT_PARSER_ITCP_STATE_CHANNEL3)
+
+#define S_OPT_PARSER_OTK_STATE_CHANNEL3 0
+#define M_OPT_PARSER_OTK_STATE_CHANNEL3 0x3U
+#define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3)
+#define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & M_OPT_PARSER_OTK_STATE_CHANNEL3)
+
+#define A_TP_DBG_ESIDE_OP_ALT 0x155
+
+#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL0 29
+#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0)
+#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0 V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U)
+
+#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 24
+#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 0x1fU
+#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
+#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
+
+#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL1 21
+#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1)
+#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1 V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U)
+
+#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 16
+#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 0x1fU
+#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
+#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
+
+#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL2 13
+#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2)
+#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2 V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U)
+
+#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 8
+#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 0x1fU
+#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
+#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
+
+#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL3 5
+#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3)
+#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3 V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U)
+
+#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0
+#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0x1fU
+#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
+#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
+
+#define A_TP_DBG_ESIDE_OP_BUSY 0x156
+
+#define S_OPT_PARSER_BUSY_VEC_CHANNEL3 24
+#define M_OPT_PARSER_BUSY_VEC_CHANNEL3 0xffU
+#define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3)
+#define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & M_OPT_PARSER_BUSY_VEC_CHANNEL3)
+
+#define S_OPT_PARSER_BUSY_VEC_CHANNEL2 16
+#define M_OPT_PARSER_BUSY_VEC_CHANNEL2 0xffU
+#define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2)
+#define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & M_OPT_PARSER_BUSY_VEC_CHANNEL2)
+
+#define S_OPT_PARSER_BUSY_VEC_CHANNEL1 8
+#define M_OPT_PARSER_BUSY_VEC_CHANNEL1 0xffU
+#define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1)
+#define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & M_OPT_PARSER_BUSY_VEC_CHANNEL1)
+
+#define S_OPT_PARSER_BUSY_VEC_CHANNEL0 0
+#define M_OPT_PARSER_BUSY_VEC_CHANNEL0 0xffU
+#define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0)
+#define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & M_OPT_PARSER_BUSY_VEC_CHANNEL0)
+
+#define A_TP_DBG_ESIDE_OP_COOKIE 0x157
+
+#define S_OPT_PARSER_COOKIE_CHANNEL3 24
+#define M_OPT_PARSER_COOKIE_CHANNEL3 0xffU
+#define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3)
+#define G_OPT_PARSER_COOKIE_CHANNEL3(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3)
+
+#define S_OPT_PARSER_COOKIE_CHANNEL2 16
+#define M_OPT_PARSER_COOKIE_CHANNEL2 0xffU
+#define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2)
+#define G_OPT_PARSER_COOKIE_CHANNEL2(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2)
+
+#define S_OPT_PARSER_COOKIE_CHANNEL1 8
+#define M_OPT_PARSER_COOKIE_CHANNEL1 0xffU
+#define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1)
+#define G_OPT_PARSER_COOKIE_CHANNEL1(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1)
+
+#define S_OPT_PARSER_COOKIE_CHANNEL0 0
+#define M_OPT_PARSER_COOKIE_CHANNEL0 0xffU
+#define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0)
+#define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0)
+
#define A_TP_DBG_CSIDE_RX0 0x230
#define S_CRXSOPCNT 28
@@ -13166,6 +19274,50 @@
#define V_CMD_SEL(x) ((x) << S_CMD_SEL)
#define F_CMD_SEL V_CMD_SEL(1U)
+#define S_CPL5RXFULL 26
+#define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL)
+#define F_CPL5RXFULL V_CPL5RXFULL(1U)
+
+#define S_PLD2XRXVALID 23
+#define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID)
+#define F_PLD2XRXVALID V_PLD2XRXVALID(1U)
+
+#define S_DDPSTATE 16
+#define M_DDPSTATE 0x1fU
+#define V_DDPSTATE(x) ((x) << S_DDPSTATE)
+#define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE)
+
+#define S_DDPMSGCODE 12
+#define M_DDPMSGCODE 0xfU
+#define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE)
+#define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE)
+
+#define S_CPL5SOCPCNT 8
+#define M_CPL5SOCPCNT 0xfU
+#define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT)
+#define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT)
+
+#define S_PLDRXZEROPCNT 4
+#define M_PLDRXZEROPCNT 0xfU
+#define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT)
+#define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT)
+
+#define S_TXFRMERR2 3
+#define V_TXFRMERR2(x) ((x) << S_TXFRMERR2)
+#define F_TXFRMERR2 V_TXFRMERR2(1U)
+
+#define S_TXFRMERR1 2
+#define V_TXFRMERR1(x) ((x) << S_TXFRMERR1)
+#define F_TXFRMERR1 V_TXFRMERR1(1U)
+
+#define S_TXVALID2X 1
+#define V_TXVALID2X(x) ((x) << S_TXVALID2X)
+#define F_TXVALID2X V_TXVALID2X(1U)
+
+#define S_TXFULL2X 0
+#define V_TXFULL2X(x) ((x) << S_TXFULL2X)
+#define F_TXFULL2X V_TXFULL2X(1U)
+
#define A_TP_DBG_CSIDE_DISP1 0x23b
#define A_TP_DBG_CSIDE_DDP0 0x23c
@@ -13365,6 +19517,48 @@
#define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP)
#define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP)
+#define S_STARTSKIPPLD 7
+#define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD)
+#define F_STARTSKIPPLD V_STARTSKIPPLD(1U)
+
+#define S_ATOMICCMDEN 5
+#define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN)
+#define F_ATOMICCMDEN V_ATOMICCMDEN(1U)
+
+#define A_TP_CSPI_POWER 0x243
+
+#define S_GATECHNTX3 11
+#define V_GATECHNTX3(x) ((x) << S_GATECHNTX3)
+#define F_GATECHNTX3 V_GATECHNTX3(1U)
+
+#define S_GATECHNTX2 10
+#define V_GATECHNTX2(x) ((x) << S_GATECHNTX2)
+#define F_GATECHNTX2 V_GATECHNTX2(1U)
+
+#define S_GATECHNTX1 9
+#define V_GATECHNTX1(x) ((x) << S_GATECHNTX1)
+#define F_GATECHNTX1 V_GATECHNTX1(1U)
+
+#define S_GATECHNTX0 8
+#define V_GATECHNTX0(x) ((x) << S_GATECHNTX0)
+#define F_GATECHNTX0 V_GATECHNTX0(1U)
+
+#define S_GATECHNRX1 7
+#define V_GATECHNRX1(x) ((x) << S_GATECHNRX1)
+#define F_GATECHNRX1 V_GATECHNRX1(1U)
+
+#define S_GATECHNRX0 6
+#define V_GATECHNRX0(x) ((x) << S_GATECHNRX0)
+#define F_GATECHNRX0 V_GATECHNRX0(1U)
+
+#define S_SLEEPRDYUTRN 4
+#define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN)
+#define F_SLEEPRDYUTRN V_SLEEPRDYUTRN(1U)
+
+#define S_SLEEPREQUTRN 0
+#define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN)
+#define F_SLEEPREQUTRN V_SLEEPREQUTRN(1U)
+
#define A_TP_TRC_CONFIG 0x244
#define S_TRCRR 1
@@ -13404,6 +19598,70 @@
#define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0)
#define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0)
+#define S_C4TUPBUSY3 31
+#define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3)
+#define F_C4TUPBUSY3 V_C4TUPBUSY3(1U)
+
+#define S_CDBVALID3 30
+#define V_CDBVALID3(x) ((x) << S_CDBVALID3)
+#define F_CDBVALID3 V_CDBVALID3(1U)
+
+#define S_CRXVALID3 29
+#define V_CRXVALID3(x) ((x) << S_CRXVALID3)
+#define F_CRXVALID3 V_CRXVALID3(1U)
+
+#define S_CRXFULL3 28
+#define V_CRXFULL3(x) ((x) << S_CRXFULL3)
+#define F_CRXFULL3 V_CRXFULL3(1U)
+
+#define S_C4TUPBUSY2 23
+#define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2)
+#define F_C4TUPBUSY2 V_C4TUPBUSY2(1U)
+
+#define S_CDBVALID2 22
+#define V_CDBVALID2(x) ((x) << S_CDBVALID2)
+#define F_CDBVALID2 V_CDBVALID2(1U)
+
+#define S_CRXVALID2 21
+#define V_CRXVALID2(x) ((x) << S_CRXVALID2)
+#define F_CRXVALID2 V_CRXVALID2(1U)
+
+#define S_CRXFULL2 20
+#define V_CRXFULL2(x) ((x) << S_CRXFULL2)
+#define F_CRXFULL2 V_CRXFULL2(1U)
+
+#define S_C4TUPBUSY1 15
+#define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1)
+#define F_C4TUPBUSY1 V_C4TUPBUSY1(1U)
+
+#define S_CDBVALID1 14
+#define V_CDBVALID1(x) ((x) << S_CDBVALID1)
+#define F_CDBVALID1 V_CDBVALID1(1U)
+
+#define S_CRXVALID1 13
+#define V_CRXVALID1(x) ((x) << S_CRXVALID1)
+#define F_CRXVALID1 V_CRXVALID1(1U)
+
+#define S_CRXFULL1 12
+#define V_CRXFULL1(x) ((x) << S_CRXFULL1)
+#define F_CRXFULL1 V_CRXFULL1(1U)
+
+#define S_C4TUPBUSY0 7
+#define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0)
+#define F_C4TUPBUSY0 V_C4TUPBUSY0(1U)
+
+#define S_CDBVALID0 6
+#define V_CDBVALID0(x) ((x) << S_CDBVALID0)
+#define F_CDBVALID0 V_CDBVALID0(1U)
+
+#define S_CRXVALID0 5
+#define V_CRXVALID0(x) ((x) << S_CRXVALID0)
+#define F_CRXVALID0 V_CRXVALID0(1U)
+
+#define S_CRXFULL0 4
+#define V_CRXFULL0(x) ((x) << S_CRXFULL0)
+#define F_CRXFULL0 V_CRXFULL0(1U)
+
#define A_TP_DBG_CSIDE_DEMUX 0x247
#define S_CALLDONE 28
@@ -13446,6 +19704,151 @@
#define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE)
#define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE)
+#define S_CARBVALID 28
+#define M_CARBVALID 0xfU
+#define V_CARBVALID(x) ((x) << S_CARBVALID)
+#define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID)
+
+#define S_CCPL5DONE 24
+#define M_CCPL5DONE 0xfU
+#define V_CCPL5DONE(x) ((x) << S_CCPL5DONE)
+#define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE)
+
+#define S_CTCPOPDONE 12
+#define M_CTCPOPDONE 0xfU
+#define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE)
+#define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE)
+
+#define A_TP_DBG_CSIDE_ARBIT 0x248
+
+#define S_CPLVALID3 31
+#define V_CPLVALID3(x) ((x) << S_CPLVALID3)
+#define F_CPLVALID3 V_CPLVALID3(1U)
+
+#define S_PLDVALID3 30
+#define V_PLDVALID3(x) ((x) << S_PLDVALID3)
+#define F_PLDVALID3 V_PLDVALID3(1U)
+
+#define S_CRCVALID3 29
+#define V_CRCVALID3(x) ((x) << S_CRCVALID3)
+#define F_CRCVALID3 V_CRCVALID3(1U)
+
+#define S_ISSVALID3 28
+#define V_ISSVALID3(x) ((x) << S_ISSVALID3)
+#define F_ISSVALID3 V_ISSVALID3(1U)
+
+#define S_DBVALID3 27
+#define V_DBVALID3(x) ((x) << S_DBVALID3)
+#define F_DBVALID3 V_DBVALID3(1U)
+
+#define S_CHKVALID3 26
+#define V_CHKVALID3(x) ((x) << S_CHKVALID3)
+#define F_CHKVALID3 V_CHKVALID3(1U)
+
+#define S_ZRPVALID3 25
+#define V_ZRPVALID3(x) ((x) << S_ZRPVALID3)
+#define F_ZRPVALID3 V_ZRPVALID3(1U)
+
+#define S_ERRVALID3 24
+#define V_ERRVALID3(x) ((x) << S_ERRVALID3)
+#define F_ERRVALID3 V_ERRVALID3(1U)
+
+#define S_CPLVALID2 23
+#define V_CPLVALID2(x) ((x) << S_CPLVALID2)
+#define F_CPLVALID2 V_CPLVALID2(1U)
+
+#define S_PLDVALID2 22
+#define V_PLDVALID2(x) ((x) << S_PLDVALID2)
+#define F_PLDVALID2 V_PLDVALID2(1U)
+
+#define S_CRCVALID2 21
+#define V_CRCVALID2(x) ((x) << S_CRCVALID2)
+#define F_CRCVALID2 V_CRCVALID2(1U)
+
+#define S_ISSVALID2 20
+#define V_ISSVALID2(x) ((x) << S_ISSVALID2)
+#define F_ISSVALID2 V_ISSVALID2(1U)
+
+#define S_DBVALID2 19
+#define V_DBVALID2(x) ((x) << S_DBVALID2)
+#define F_DBVALID2 V_DBVALID2(1U)
+
+#define S_CHKVALID2 18
+#define V_CHKVALID2(x) ((x) << S_CHKVALID2)
+#define F_CHKVALID2 V_CHKVALID2(1U)
+
+#define S_ZRPVALID2 17
+#define V_ZRPVALID2(x) ((x) << S_ZRPVALID2)
+#define F_ZRPVALID2 V_ZRPVALID2(1U)
+
+#define S_ERRVALID2 16
+#define V_ERRVALID2(x) ((x) << S_ERRVALID2)
+#define F_ERRVALID2 V_ERRVALID2(1U)
+
+#define S_CPLVALID1 15
+#define V_CPLVALID1(x) ((x) << S_CPLVALID1)
+#define F_CPLVALID1 V_CPLVALID1(1U)
+
+#define S_PLDVALID1 14
+#define V_PLDVALID1(x) ((x) << S_PLDVALID1)
+#define F_PLDVALID1 V_PLDVALID1(1U)
+
+#define S_CRCVALID1 13
+#define V_CRCVALID1(x) ((x) << S_CRCVALID1)
+#define F_CRCVALID1 V_CRCVALID1(1U)
+
+#define S_ISSVALID1 12
+#define V_ISSVALID1(x) ((x) << S_ISSVALID1)
+#define F_ISSVALID1 V_ISSVALID1(1U)
+
+#define S_DBVALID1 11
+#define V_DBVALID1(x) ((x) << S_DBVALID1)
+#define F_DBVALID1 V_DBVALID1(1U)
+
+#define S_CHKVALID1 10
+#define V_CHKVALID1(x) ((x) << S_CHKVALID1)
+#define F_CHKVALID1 V_CHKVALID1(1U)
+
+#define S_ZRPVALID1 9
+#define V_ZRPVALID1(x) ((x) << S_ZRPVALID1)
+#define F_ZRPVALID1 V_ZRPVALID1(1U)
+
+#define S_ERRVALID1 8
+#define V_ERRVALID1(x) ((x) << S_ERRVALID1)
+#define F_ERRVALID1 V_ERRVALID1(1U)
+
+#define S_CPLVALID0 7
+#define V_CPLVALID0(x) ((x) << S_CPLVALID0)
+#define F_CPLVALID0 V_CPLVALID0(1U)
+
+#define S_PLDVALID0 6
+#define V_PLDVALID0(x) ((x) << S_PLDVALID0)
+#define F_PLDVALID0 V_PLDVALID0(1U)
+
+#define S_CRCVALID0 5
+#define V_CRCVALID0(x) ((x) << S_CRCVALID0)
+#define F_CRCVALID0 V_CRCVALID0(1U)
+
+#define S_ISSVALID0 4
+#define V_ISSVALID0(x) ((x) << S_ISSVALID0)
+#define F_ISSVALID0 V_ISSVALID0(1U)
+
+#define S_DBVALID0 3
+#define V_DBVALID0(x) ((x) << S_DBVALID0)
+#define F_DBVALID0 V_DBVALID0(1U)
+
+#define S_CHKVALID0 2
+#define V_CHKVALID0(x) ((x) << S_CHKVALID0)
+#define F_CHKVALID0 V_CHKVALID0(1U)
+
+#define S_ZRPVALID0 1
+#define V_ZRPVALID0(x) ((x) << S_ZRPVALID0)
+#define F_ZRPVALID0 V_ZRPVALID0(1U)
+
+#define S_ERRVALID0 0
+#define V_ERRVALID0(x) ((x) << S_ERRVALID0)
+#define F_ERRVALID0 V_ERRVALID0(1U)
+
#define A_TP_FIFO_CONFIG 0x8c0
#define S_CH1_OUTPUT 27
@@ -13573,12 +19976,16 @@
#define A_TP_MIB_TID_INV 0x61
#define A_TP_MIB_TID_ACT 0x62
#define A_TP_MIB_TID_PAS 0x63
-#define A_TP_MIB_RQE_DFR_MOD 0x64
-#define A_TP_MIB_RQE_DFR_PKT 0x65
+#define A_TP_MIB_RQE_DFR_PKT 0x64
+#define A_TP_MIB_RQE_DFR_MOD 0x65
#define A_TP_MIB_CPL_OUT_ERR_0 0x68
#define A_TP_MIB_CPL_OUT_ERR_1 0x69
#define A_TP_MIB_CPL_OUT_ERR_2 0x6a
#define A_TP_MIB_CPL_OUT_ERR_3 0x6b
+#define A_TP_MIB_ENG_LINE_0 0x6c
+#define A_TP_MIB_ENG_LINE_1 0x6d
+#define A_TP_MIB_ENG_LINE_2 0x6e
+#define A_TP_MIB_ENG_LINE_3 0x6f
/* registers for module ULP_TX */
#define ULP_TX_BASE_ADDR 0x8dc0
@@ -13597,6 +20004,30 @@
#define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE)
#define F_EXTRA_TAG_INSERTION_ENABLE V_EXTRA_TAG_INSERTION_ENABLE(1U)
+#define S_PHYS_ADDR_RESP_EN 6
+#define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN)
+#define F_PHYS_ADDR_RESP_EN V_PHYS_ADDR_RESP_EN(1U)
+
+#define S_ENDIANESS_CHANGE 5
+#define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE)
+#define F_ENDIANESS_CHANGE V_ENDIANESS_CHANGE(1U)
+
+#define S_ERR_RTAG_EN 4
+#define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN)
+#define F_ERR_RTAG_EN V_ERR_RTAG_EN(1U)
+
+#define S_TSO_ETHLEN_EN 3
+#define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN)
+#define F_TSO_ETHLEN_EN V_TSO_ETHLEN_EN(1U)
+
+#define S_EMSG_MORE_INFO 2
+#define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO)
+#define F_EMSG_MORE_INFO V_EMSG_MORE_INFO(1U)
+
+#define S_LOSDR 1
+#define V_LOSDR(x) ((x) << S_LOSDR)
+#define F_LOSDR V_LOSDR(1U)
+
#define A_ULP_TX_PERR_INJECT 0x8dc4
#define A_ULP_TX_INT_ENABLE 0x8dc8
@@ -13813,25 +20244,193 @@
#define V_ERR_CNT3(x) ((x) << S_ERR_CNT3)
#define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3)
+#define A_ULP_TX_FC_SOF 0x8e20
+
+#define S_SOF_FS3 24
+#define M_SOF_FS3 0xffU
+#define V_SOF_FS3(x) ((x) << S_SOF_FS3)
+#define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3)
+
+#define S_SOF_FS2 16
+#define M_SOF_FS2 0xffU
+#define V_SOF_FS2(x) ((x) << S_SOF_FS2)
+#define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2)
+
+#define S_SOF_3 8
+#define M_SOF_3 0xffU
+#define V_SOF_3(x) ((x) << S_SOF_3)
+#define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3)
+
+#define S_SOF_2 0
+#define M_SOF_2 0xffU
+#define V_SOF_2(x) ((x) << S_SOF_2)
+#define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2)
+
+#define A_ULP_TX_FC_EOF 0x8e24
+
+#define S_EOF_LS3 24
+#define M_EOF_LS3 0xffU
+#define V_EOF_LS3(x) ((x) << S_EOF_LS3)
+#define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3)
+
+#define S_EOF_LS2 16
+#define M_EOF_LS2 0xffU
+#define V_EOF_LS2(x) ((x) << S_EOF_LS2)
+#define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2)
+
+#define S_EOF_3 8
+#define M_EOF_3 0xffU
+#define V_EOF_3(x) ((x) << S_EOF_3)
+#define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3)
+
+#define S_EOF_2 0
+#define M_EOF_2 0xffU
+#define V_EOF_2(x) ((x) << S_EOF_2)
+#define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2)
+
+#define A_ULP_TX_CGEN_GLOBAL 0x8e28
+
+#define S_ULP_TX_GLOBAL_CGEN 0
+#define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN)
+#define F_ULP_TX_GLOBAL_CGEN V_ULP_TX_GLOBAL_CGEN(1U)
+
+#define A_ULP_TX_CGEN 0x8e2c
+
+#define S_ULP_TX_CGEN_STORAGE 8
+#define M_ULP_TX_CGEN_STORAGE 0xfU
+#define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE)
+#define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE)
+
+#define S_ULP_TX_CGEN_RDMA 4
+#define M_ULP_TX_CGEN_RDMA 0xfU
+#define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA)
+#define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA)
+
+#define S_ULP_TX_CGEN_CHANNEL 0
+#define M_ULP_TX_CGEN_CHANNEL 0xfU
+#define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL)
+#define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL)
+
#define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
+#define A_ULP_TX_MEM_CFG 0x8e30
+
+#define S_WRREQ_SZ 0
+#define M_WRREQ_SZ 0x7U
+#define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ)
+#define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ)
+
#define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
+#define A_ULP_TX_PERR_INJECT_2 0x8e34
#define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
+#define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
+
+#define S_CHANNEL_SEL 12
+#define M_CHANNEL_SEL 0x3U
+#define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL)
+#define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL)
+
+#define S_INTF_SEL 4
+#define M_INTF_SEL 0xfU
+#define V_INTF_SEL(x) ((x) << S_INTF_SEL)
+#define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL)
+
+#define S_NUM_FLITS 1
+#define M_NUM_FLITS 0x7U
+#define V_NUM_FLITS(x) ((x) << S_NUM_FLITS)
+#define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS)
+
+#define S_CMD_GEN_EN 0
+#define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN)
+#define F_CMD_GEN_EN V_CMD_GEN_EN(1U)
+
#define A_ULP_TX_FPGA_CMD_0 0x8e3c
+#define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c
#define A_ULP_TX_FPGA_CMD_1 0x8e40
+#define A_ULP_TX_T5_FPGA_CMD_1 0x8e40
#define A_ULP_TX_FPGA_CMD_2 0x8e44
+#define A_ULP_TX_T5_FPGA_CMD_2 0x8e44
#define A_ULP_TX_FPGA_CMD_3 0x8e48
+#define A_ULP_TX_T5_FPGA_CMD_3 0x8e48
#define A_ULP_TX_FPGA_CMD_4 0x8e4c
+#define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c
#define A_ULP_TX_FPGA_CMD_5 0x8e50
+#define A_ULP_TX_T5_FPGA_CMD_5 0x8e50
#define A_ULP_TX_FPGA_CMD_6 0x8e54
+#define A_ULP_TX_T5_FPGA_CMD_6 0x8e54
#define A_ULP_TX_FPGA_CMD_7 0x8e58
+#define A_ULP_TX_T5_FPGA_CMD_7 0x8e58
#define A_ULP_TX_FPGA_CMD_8 0x8e5c
+#define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c
#define A_ULP_TX_FPGA_CMD_9 0x8e60
+#define A_ULP_TX_T5_FPGA_CMD_9 0x8e60
#define A_ULP_TX_FPGA_CMD_10 0x8e64
+#define A_ULP_TX_T5_FPGA_CMD_10 0x8e64
#define A_ULP_TX_FPGA_CMD_11 0x8e68
+#define A_ULP_TX_T5_FPGA_CMD_11 0x8e68
#define A_ULP_TX_FPGA_CMD_12 0x8e6c
+#define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c
#define A_ULP_TX_FPGA_CMD_13 0x8e70
+#define A_ULP_TX_T5_FPGA_CMD_13 0x8e70
#define A_ULP_TX_FPGA_CMD_14 0x8e74
+#define A_ULP_TX_T5_FPGA_CMD_14 0x8e74
#define A_ULP_TX_FPGA_CMD_15 0x8e78
+#define A_ULP_TX_T5_FPGA_CMD_15 0x8e78
+#define A_ULP_TX_INT_ENABLE_2 0x8e7c
+
+#define S_SMARBT2ULP_DATA_PERR_SET 12
+#define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
+#define F_SMARBT2ULP_DATA_PERR_SET V_SMARBT2ULP_DATA_PERR_SET(1U)
+
+#define S_ULP2TP_DATA_PERR_SET 11
+#define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
+#define F_ULP2TP_DATA_PERR_SET V_ULP2TP_DATA_PERR_SET(1U)
+
+#define S_MA2ULP_DATA_PERR_SET 10
+#define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
+#define F_MA2ULP_DATA_PERR_SET V_MA2ULP_DATA_PERR_SET(1U)
+
+#define S_SGE2ULP_DATA_PERR_SET 9
+#define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
+#define F_SGE2ULP_DATA_PERR_SET V_SGE2ULP_DATA_PERR_SET(1U)
+
+#define S_CIM2ULP_DATA_PERR_SET 8
+#define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
+#define F_CIM2ULP_DATA_PERR_SET V_CIM2ULP_DATA_PERR_SET(1U)
+
+#define S_FSO_HDR_SRAM_PERR_SET3 7
+#define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
+#define F_FSO_HDR_SRAM_PERR_SET3 V_FSO_HDR_SRAM_PERR_SET3(1U)
+
+#define S_FSO_HDR_SRAM_PERR_SET2 6
+#define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
+#define F_FSO_HDR_SRAM_PERR_SET2 V_FSO_HDR_SRAM_PERR_SET2(1U)
+
+#define S_FSO_HDR_SRAM_PERR_SET1 5
+#define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
+#define F_FSO_HDR_SRAM_PERR_SET1 V_FSO_HDR_SRAM_PERR_SET1(1U)
+
+#define S_FSO_HDR_SRAM_PERR_SET0 4
+#define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
+#define F_FSO_HDR_SRAM_PERR_SET0 V_FSO_HDR_SRAM_PERR_SET0(1U)
+
+#define S_T10_PI_SRAM_PERR_SET3 3
+#define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
+#define F_T10_PI_SRAM_PERR_SET3 V_T10_PI_SRAM_PERR_SET3(1U)
+
+#define S_T10_PI_SRAM_PERR_SET2 2
+#define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
+#define F_T10_PI_SRAM_PERR_SET2 V_T10_PI_SRAM_PERR_SET2(1U)
+
+#define S_T10_PI_SRAM_PERR_SET1 1
+#define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
+#define F_T10_PI_SRAM_PERR_SET1 V_T10_PI_SRAM_PERR_SET1(1U)
+
+#define S_T10_PI_SRAM_PERR_SET0 0
+#define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
+#define F_T10_PI_SRAM_PERR_SET0 V_T10_PI_SRAM_PERR_SET0(1U)
+
+#define A_ULP_TX_INT_CAUSE_2 0x8e80
+#define A_ULP_TX_PERR_ENABLE_2 0x8e84
#define A_ULP_TX_SE_CNT_ERR 0x8ea0
#define S_ERR_CH3 12
@@ -13854,6 +20453,7 @@
#define V_ERR_CH0(x) ((x) << S_ERR_CH0)
#define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0)
+#define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0
#define A_ULP_TX_SE_CNT_CLR 0x8ea4
#define S_CLR_DROP 16
@@ -13881,6 +20481,7 @@
#define V_CLR_CH0(x) ((x) << S_CLR_CH0)
#define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0)
+#define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4
#define A_ULP_TX_SE_CNT_CH0 0x8ea8
#define S_SOP_CNT_ULP2TP 28
@@ -13923,9 +20524,13 @@
#define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
#define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
+#define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
#define A_ULP_TX_SE_CNT_CH1 0x8eac
+#define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
#define A_ULP_TX_SE_CNT_CH2 0x8eb0
+#define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
#define A_ULP_TX_SE_CNT_CH3 0x8eb4
+#define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
#define A_ULP_TX_DROP_CNT 0x8eb8
#define S_DROP_CH3 12
@@ -13948,6 +20553,8 @@
#define V_DROP_CH0(x) ((x) << S_DROP_CH0)
#define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
+#define A_ULP_TX_T5_DROP_CNT 0x8eb8
+#define A_ULP_TX_CSU_REVISION 0x8ebc
#define A_ULP_TX_LA_RDPTR_0 0x8ec0
#define A_ULP_TX_LA_RDDATA_0 0x8ec4
#define A_ULP_TX_LA_WRPTR_0 0x8ec8
@@ -13992,6 +20599,17 @@
#define A_ULP_TX_LA_RDDATA_10 0x8f64
#define A_ULP_TX_LA_WRPTR_10 0x8f68
#define A_ULP_TX_LA_RESERVED_10 0x8f6c
+#define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
+
+#define S_LA_WR0 0
+#define V_LA_WR0(x) ((x) << S_LA_WR0)
+#define F_LA_WR0 V_LA_WR0(1U)
+
+#define A_ULP_TX_ASIC_DEBUG_0 0x8f74
+#define A_ULP_TX_ASIC_DEBUG_1 0x8f78
+#define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
+#define A_ULP_TX_ASIC_DEBUG_3 0x8f80
+#define A_ULP_TX_ASIC_DEBUG_4 0x8f84
/* registers for module PM_RX */
#define PM_RX_BASE_ADDR 0x8fc0
@@ -14019,7 +20637,25 @@
#define A_PM_RX_STAT_CONFIG 0x8fc8
#define A_PM_RX_STAT_COUNT 0x8fcc
#define A_PM_RX_STAT_LSB 0x8fd0
+#define A_PM_RX_DBG_CTRL 0x8fd0
+
+#define S_OSPIWRBUSY_T5 21
+#define M_OSPIWRBUSY_T5 0x3U
+#define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
+#define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)
+
+#define S_ISPIWRBUSY 17
+#define M_ISPIWRBUSY 0xfU
+#define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
+#define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)
+
+#define S_PMDBGADDR 0
+#define M_PMDBGADDR 0x1ffffU
+#define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
+#define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
+
#define A_PM_RX_STAT_MSB 0x8fd4
+#define A_PM_RX_DBG_DATA 0x8fd4
#define A_PM_RX_INT_ENABLE 0x8fd8
#define S_ZERO_E_CMD_ERROR 22
@@ -14114,7 +20750,573 @@
#define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
#define F_E_PCMD_PAR_ERROR V_E_PCMD_PAR_ERROR(1U)
+#define S_OSPI_OVERFLOW1 28
+#define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
+#define F_OSPI_OVERFLOW1 V_OSPI_OVERFLOW1(1U)
+
+#define S_OSPI_OVERFLOW0 27
+#define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
+#define F_OSPI_OVERFLOW0 V_OSPI_OVERFLOW0(1U)
+
+#define S_MA_INTF_SDC_ERR 26
+#define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
+#define F_MA_INTF_SDC_ERR V_MA_INTF_SDC_ERR(1U)
+
+#define S_BUNDLE_LEN_PARERR 25
+#define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
+#define F_BUNDLE_LEN_PARERR V_BUNDLE_LEN_PARERR(1U)
+
+#define S_BUNDLE_LEN_OVFL 24
+#define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
+#define F_BUNDLE_LEN_OVFL V_BUNDLE_LEN_OVFL(1U)
+
+#define S_SDC_ERR 23
+#define V_SDC_ERR(x) ((x) << S_SDC_ERR)
+#define F_SDC_ERR V_SDC_ERR(1U)
+
#define A_PM_RX_INT_CAUSE 0x8fdc
+#define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
+#define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
+#define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
+#define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003
+#define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004
+#define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005
+#define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006
+#define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007
+#define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008
+#define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009
+#define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a
+#define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b
+#define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c
+#define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d
+#define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e
+#define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f
+#define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010
+#define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011
+#define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012
+#define A_PM_RX_DBG_STAT_MSB 0x10013
+#define A_PM_RX_DBG_STAT_LSB 0x10014
+#define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015
+
+#define S_I_TO_O_PATH_RSVD_FLIT_BACKUP 12
+#define M_I_TO_O_PATH_RSVD_FLIT_BACKUP 0xfU
+#define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP)
+#define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP)
+
+#define S_I_TO_O_PATH_RSVD_FLIT 8
+#define M_I_TO_O_PATH_RSVD_FLIT 0xfU
+#define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT)
+#define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT)
+
+#define S_PRFCH_RSVD_FLIT 4
+#define M_PRFCH_RSVD_FLIT 0xfU
+#define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT)
+#define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT)
+
+#define S_OSPI_RSVD_FLIT 0
+#define M_OSPI_RSVD_FLIT 0xfU
+#define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT)
+#define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT)
+
+#define A_PM_RX_SDC_EN 0x10016
+
+#define S_SDC_EN 0
+#define V_SDC_EN(x) ((x) << S_SDC_EN)
+#define F_SDC_EN V_SDC_EN(1U)
+
+#define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017
+
+#define S_CHNL_3_SEL 3
+#define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL)
+#define F_CHNL_3_SEL V_CHNL_3_SEL(1U)
+
+#define S_CHNL_2_SEL 2
+#define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL)
+#define F_CHNL_2_SEL V_CHNL_2_SEL(1U)
+
+#define S_CHNL_1_SEL 1
+#define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL)
+#define F_CHNL_1_SEL V_CHNL_1_SEL(1U)
+
+#define S_CHNL_0_SEL 0
+#define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL)
+#define F_CHNL_0_SEL V_CHNL_0_SEL(1U)
+
+#define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018
+
+#define S_O_FIFO_WRITE 3
+#define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE)
+#define F_O_FIFO_WRITE V_O_FIFO_WRITE(1U)
+
+#define S_I_FIFO_WRITE 2
+#define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE)
+#define F_I_FIFO_WRITE V_I_FIFO_WRITE(1U)
+
+#define S_O_FIFO_READ 1
+#define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ)
+#define F_O_FIFO_READ V_O_FIFO_READ(1U)
+
+#define S_I_FIFO_READ 0
+#define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ)
+#define F_I_FIFO_READ V_I_FIFO_READ(1U)
+
+#define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019
+
+#define S_ISPI_STR_FWD_EN 0
+#define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN)
+#define F_ISPI_STR_FWD_EN V_ISPI_STR_FWD_EN(1U)
+
+#define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a
+
+#define S_PRFTCH_ACROSS_BNDLE_EN 0
+#define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN)
+#define F_PRFTCH_ACROSS_BNDLE_EN V_PRFTCH_ACROSS_BNDLE_EN(1U)
+
+#define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b
+
+#define S_PRFTCH_WRR_ENABLE 0
+#define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE)
+#define F_PRFTCH_WRR_ENABLE V_PRFTCH_WRR_ENABLE(1U)
+
+#define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c
+
+#define S_CHNL1_MAX_DEFICIT_CNT 16
+#define M_CHNL1_MAX_DEFICIT_CNT 0xffffU
+#define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT)
+#define G_CHNL1_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT)
+
+#define S_CHNL0_MAX_DEFICIT_CNT 0
+#define M_CHNL0_MAX_DEFICIT_CNT 0xffffU
+#define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT)
+#define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT)
+
+#define A_PM_RX_FEATURE_EN 0x1001d
+
+#define S_PIO_CH_DEFICIT_CTL_EN_RX 0
+#define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX)
+#define F_PIO_CH_DEFICIT_CTL_EN_RX V_PIO_CH_DEFICIT_CTL_EN_RX(1U)
+
+#define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
+
+#define S_CH0_OSPI_DEFICIT_THRSHLD 0
+#define M_CH0_OSPI_DEFICIT_THRSHLD 0xfffU
+#define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD)
+#define G_CH0_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD)
+
+#define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f
+
+#define S_CH1_OSPI_DEFICIT_THRSHLD 0
+#define M_CH1_OSPI_DEFICIT_THRSHLD 0xfffU
+#define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD)
+#define G_CH1_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD)
+
+#define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020
+#define A_PM_RX_DBG_STAT0 0x10021
+
+#define S_RX_RD_I_BUSY 29
+#define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY)
+#define F_RX_RD_I_BUSY V_RX_RD_I_BUSY(1U)
+
+#define S_RX_WR_TO_O_BUSY 28
+#define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY)
+#define F_RX_WR_TO_O_BUSY V_RX_WR_TO_O_BUSY(1U)
+
+#define S_RX_M_TO_O_BUSY 27
+#define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY)
+#define F_RX_M_TO_O_BUSY V_RX_M_TO_O_BUSY(1U)
+
+#define S_RX_I_TO_M_BUSY 26
+#define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY)
+#define F_RX_I_TO_M_BUSY V_RX_I_TO_M_BUSY(1U)
+
+#define S_RX_PCMD_FB_ONLY 25
+#define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY)
+#define F_RX_PCMD_FB_ONLY V_RX_PCMD_FB_ONLY(1U)
+
+#define S_RX_PCMD_MEM 24
+#define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM)
+#define F_RX_PCMD_MEM V_RX_PCMD_MEM(1U)
+
+#define S_RX_PCMD_BYPASS 23
+#define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS)
+#define F_RX_PCMD_BYPASS V_RX_PCMD_BYPASS(1U)
+
+#define S_RX_PCMD_EOP 22
+#define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP)
+#define F_RX_PCMD_EOP V_RX_PCMD_EOP(1U)
+
+#define S_RX_DUMPLICATE_PCMD_EOP 21
+#define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP)
+#define F_RX_DUMPLICATE_PCMD_EOP V_RX_DUMPLICATE_PCMD_EOP(1U)
+
+#define S_RX_PCMD_EOB 20
+#define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB)
+#define F_RX_PCMD_EOB V_RX_PCMD_EOB(1U)
+
+#define S_RX_PCMD_FB 16
+#define M_RX_PCMD_FB 0xfU
+#define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB)
+#define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB)
+
+#define S_RX_PCMD_LEN 0
+#define M_RX_PCMD_LEN 0xffffU
+#define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN)
+#define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN)
+
+#define A_PM_RX_DBG_STAT1 0x10022
+
+#define S_RX_PCMD0_MEM 30
+#define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM)
+#define F_RX_PCMD0_MEM V_RX_PCMD0_MEM(1U)
+
+#define S_RX_FREE_OSPI_CNT0 18
+#define M_RX_FREE_OSPI_CNT0 0xfffU
+#define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0)
+#define G_RX_FREE_OSPI_CNT0(x) (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0)
+
+#define S_RX_PCMD0_FLIT_LEN 6
+#define M_RX_PCMD0_FLIT_LEN 0xfffU
+#define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN)
+#define G_RX_PCMD0_FLIT_LEN(x) (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN)
+
+#define S_RX_PCMD0_CMD 2
+#define M_RX_PCMD0_CMD 0xfU
+#define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD)
+#define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD)
+
+#define S_RX_OFIFO_FULL0 1
+#define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0)
+#define F_RX_OFIFO_FULL0 V_RX_OFIFO_FULL0(1U)
+
+#define S_RX_PCMD0_BYPASS 0
+#define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS)
+#define F_RX_PCMD0_BYPASS V_RX_PCMD0_BYPASS(1U)
+
+#define A_PM_RX_DBG_STAT2 0x10023
+
+#define S_RX_PCMD1_MEM 30
+#define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM)
+#define F_RX_PCMD1_MEM V_RX_PCMD1_MEM(1U)
+
+#define S_RX_FREE_OSPI_CNT1 18
+#define M_RX_FREE_OSPI_CNT1 0xfffU
+#define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1)
+#define G_RX_FREE_OSPI_CNT1(x) (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1)
+
+#define S_RX_PCMD1_FLIT_LEN 6
+#define M_RX_PCMD1_FLIT_LEN 0xfffU
+#define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN)
+#define G_RX_PCMD1_FLIT_LEN(x) (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN)
+
+#define S_RX_PCMD1_CMD 2
+#define M_RX_PCMD1_CMD 0xfU
+#define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD)
+#define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD)
+
+#define S_RX_OFIFO_FULL1 1
+#define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1)
+#define F_RX_OFIFO_FULL1 V_RX_OFIFO_FULL1(1U)
+
+#define S_RX_PCMD1_BYPASS 0
+#define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS)
+#define F_RX_PCMD1_BYPASS V_RX_PCMD1_BYPASS(1U)
+
+#define A_PM_RX_DBG_STAT3 0x10024
+
+#define S_RX_SET_PCMD_RES_RDY_RD 10
+#define M_RX_SET_PCMD_RES_RDY_RD 0x3U
+#define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD)
+#define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD)
+
+#define S_RX_ISSUED_PREFETCH_RD_E_CLR 8
+#define M_RX_ISSUED_PREFETCH_RD_E_CLR 0x3U
+#define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR)
+#define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR)
+
+#define S_RX_ISSUED_PREFETCH_RD 6
+#define M_RX_ISSUED_PREFETCH_RD 0x3U
+#define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD)
+#define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD)
+
+#define S_RX_PCMD_RES_RDY 4
+#define M_RX_PCMD_RES_RDY 0x3U
+#define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY)
+#define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY)
+
+#define S_RX_DB_VLD 3
+#define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD)
+#define F_RX_DB_VLD V_RX_DB_VLD(1U)
+
+#define S_RX_FIRST_BUNDLE 1
+#define M_RX_FIRST_BUNDLE 0x3U
+#define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE)
+#define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE)
+
+#define S_RX_SDC_DRDY 0
+#define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY)
+#define F_RX_SDC_DRDY V_RX_SDC_DRDY(1U)
+
+#define A_PM_RX_DBG_STAT4 0x10025
+
+#define S_RX_PCMD_VLD 26
+#define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD)
+#define F_RX_PCMD_VLD V_RX_PCMD_VLD(1U)
+
+#define S_RX_PCMD_TO_CH 25
+#define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH)
+#define F_RX_PCMD_TO_CH V_RX_PCMD_TO_CH(1U)
+
+#define S_RX_PCMD_FROM_CH 23
+#define M_RX_PCMD_FROM_CH 0x3U
+#define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH)
+#define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH)
+
+#define S_RX_LINE 18
+#define M_RX_LINE 0x1fU
+#define V_RX_LINE(x) ((x) << S_RX_LINE)
+#define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE)
+
+#define S_RX_IESPI_TXVALID 14
+#define M_RX_IESPI_TXVALID 0xfU
+#define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID)
+#define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID)
+
+#define S_RX_IESPI_TXFULL 10
+#define M_RX_IESPI_TXFULL 0xfU
+#define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL)
+#define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL)
+
+#define S_RX_PCMD_SRDY 8
+#define M_RX_PCMD_SRDY 0x3U
+#define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY)
+#define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY)
+
+#define S_RX_PCMD_DRDY 6
+#define M_RX_PCMD_DRDY 0x3U
+#define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY)
+#define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY)
+
+#define S_RX_PCMD_CMD 2
+#define M_RX_PCMD_CMD 0xfU
+#define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD)
+#define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD)
+
+#define S_DUPLICATE 0
+#define M_DUPLICATE 0x3U
+#define V_DUPLICATE(x) ((x) << S_DUPLICATE)
+#define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE)
+
+#define A_PM_RX_DBG_STAT5 0x10026
+
+#define S_RX_ATLST_1_PCMD_CH1 29
+#define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1)
+#define F_RX_ATLST_1_PCMD_CH1 V_RX_ATLST_1_PCMD_CH1(1U)
+
+#define S_RX_ATLST_1_PCMD_CH0 28
+#define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0)
+#define F_RX_ATLST_1_PCMD_CH0 V_RX_ATLST_1_PCMD_CH0(1U)
+
+#define S_RX_ISPI_TXVALID 20
+#define M_RX_ISPI_TXVALID 0xfU
+#define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID)
+#define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID)
+
+#define S_RX_ISPI_FULL 16
+#define M_RX_ISPI_FULL 0xfU
+#define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL)
+#define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL)
+
+#define S_RX_OSPI_TXVALID 14
+#define M_RX_OSPI_TXVALID 0x3U
+#define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID)
+#define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID)
+
+#define S_RX_OSPI_FULL 12
+#define M_RX_OSPI_FULL 0x3U
+#define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL)
+#define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL)
+
+#define S_RX_E_RXVALID 8
+#define M_RX_E_RXVALID 0xfU
+#define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID)
+#define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID)
+
+#define S_RX_E_RXAFULL 4
+#define M_RX_E_RXAFULL 0xfU
+#define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL)
+#define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL)
+
+#define S_RX_C_TXVALID 2
+#define M_RX_C_TXVALID 0x3U
+#define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID)
+#define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID)
+
+#define S_RX_C_TXAFULL 0
+#define M_RX_C_TXAFULL 0x3U
+#define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
+#define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
+
+#define A_PM_RX_DBG_STAT6 0x10027
+
+#define S_RX_M_INTRNL_FIFO_CNT 4
+#define M_RX_M_INTRNL_FIFO_CNT 0x3U
+#define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT)
+#define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT)
+
+#define S_RX_M_REQADDRRDY 3
+#define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY)
+#define F_RX_M_REQADDRRDY V_RX_M_REQADDRRDY(1U)
+
+#define S_RX_M_REQWRITE 2
+#define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE)
+#define F_RX_M_REQWRITE V_RX_M_REQWRITE(1U)
+
+#define S_RX_M_REQDATAVLD 1
+#define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD)
+#define F_RX_M_REQDATAVLD V_RX_M_REQDATAVLD(1U)
+
+#define S_RX_M_REQDATARDY 0
+#define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY)
+#define F_RX_M_REQDATARDY V_RX_M_REQDATARDY(1U)
+
+#define A_PM_RX_DBG_STAT7 0x10028
+
+#define S_RX_PCMD1_FREE_CNT 7
+#define M_RX_PCMD1_FREE_CNT 0x7fU
+#define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT)
+#define G_RX_PCMD1_FREE_CNT(x) (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT)
+
+#define S_RX_PCMD0_FREE_CNT 0
+#define M_RX_PCMD0_FREE_CNT 0x7fU
+#define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT)
+#define G_RX_PCMD0_FREE_CNT(x) (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT)
+
+#define A_PM_RX_DBG_STAT8 0x10029
+
+#define S_RX_IN_EOP_CNT3 28
+#define M_RX_IN_EOP_CNT3 0xfU
+#define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3)
+#define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3)
+
+#define S_RX_IN_EOP_CNT2 24
+#define M_RX_IN_EOP_CNT2 0xfU
+#define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2)
+#define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2)
+
+#define S_RX_IN_EOP_CNT1 20
+#define M_RX_IN_EOP_CNT1 0xfU
+#define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1)
+#define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1)
+
+#define S_RX_IN_EOP_CNT0 16
+#define M_RX_IN_EOP_CNT0 0xfU
+#define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0)
+#define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0)
+
+#define S_RX_IN_SOP_CNT3 12
+#define M_RX_IN_SOP_CNT3 0xfU
+#define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3)
+#define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3)
+
+#define S_RX_IN_SOP_CNT2 8
+#define M_RX_IN_SOP_CNT2 0xfU
+#define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2)
+#define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2)
+
+#define S_RX_IN_SOP_CNT1 4
+#define M_RX_IN_SOP_CNT1 0xfU
+#define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1)
+#define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1)
+
+#define S_RX_IN_SOP_CNT0 0
+#define M_RX_IN_SOP_CNT0 0xfU
+#define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0)
+#define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0)
+
+#define A_PM_RX_DBG_STAT9 0x1002a
+
+#define S_RX_RSVD0 28
+#define M_RX_RSVD0 0xfU
+#define V_RX_RSVD0(x) ((x) << S_RX_RSVD0)
+#define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0)
+
+#define S_RX_RSVD1 24
+#define M_RX_RSVD1 0xfU
+#define V_RX_RSVD1(x) ((x) << S_RX_RSVD1)
+#define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1)
+
+#define S_RX_OUT_EOP_CNT1 20
+#define M_RX_OUT_EOP_CNT1 0xfU
+#define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1)
+#define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1)
+
+#define S_RX_OUT_EOP_CNT0 16
+#define M_RX_OUT_EOP_CNT0 0xfU
+#define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0)
+#define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0)
+
+#define S_RX_RSVD2 12
+#define M_RX_RSVD2 0xfU
+#define V_RX_RSVD2(x) ((x) << S_RX_RSVD2)
+#define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2)
+
+#define S_RX_RSVD3 8
+#define M_RX_RSVD3 0xfU
+#define V_RX_RSVD3(x) ((x) << S_RX_RSVD3)
+#define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3)
+
+#define S_RX_OUT_SOP_CNT1 4
+#define M_RX_OUT_SOP_CNT1 0xfU
+#define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1)
+#define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1)
+
+#define S_RX_OUT_SOP_CNT0 0
+#define M_RX_OUT_SOP_CNT0 0xfU
+#define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0)
+#define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0)
+
+#define A_PM_RX_DBG_STAT10 0x1002b
+
+#define S_RX_CH_DEFICIT_BLOWED 24
+#define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED)
+#define F_RX_CH_DEFICIT_BLOWED V_RX_CH_DEFICIT_BLOWED(1U)
+
+#define S_RX_CH1_DEFICIT 12
+#define M_RX_CH1_DEFICIT 0xfffU
+#define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT)
+#define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT)
+
+#define S_RX_CH0_DEFICIT 0
+#define M_RX_CH0_DEFICIT 0xfffU
+#define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT)
+#define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT)
+
+#define A_PM_RX_DBG_STAT11 0x1002c
+
+#define S_RX_BUNDLE_LEN_SRDY 30
+#define M_RX_BUNDLE_LEN_SRDY 0x3U
+#define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY)
+#define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY)
+
+#define S_RX_RSVD11_1 28
+#define M_RX_RSVD11_1 0x3U
+#define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1)
+#define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1)
+
+#define S_RX_BUNDLE_LEN1 16
+#define M_RX_BUNDLE_LEN1 0xfffU
+#define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1)
+#define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1)
+
+#define S_RX_RSVD11 12
+#define M_RX_RSVD11 0xfU
+#define V_RX_RSVD11(x) ((x) << S_RX_RSVD11)
+#define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11)
+
+#define S_RX_BUNDLE_LEN0 0
+#define M_RX_BUNDLE_LEN0 0xfffU
+#define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0)
+#define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0)
/* registers for module PM_TX */
#define PM_TX_BASE_ADDR 0x8fe0
@@ -14160,7 +21362,15 @@
#define A_PM_TX_STAT_CONFIG 0x8fe8
#define A_PM_TX_STAT_COUNT 0x8fec
#define A_PM_TX_STAT_LSB 0x8ff0
+#define A_PM_TX_DBG_CTRL 0x8ff0
+
+#define S_OSPIWRBUSY 21
+#define M_OSPIWRBUSY 0xfU
+#define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
+#define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)
+
#define A_PM_TX_STAT_MSB 0x8ff4
+#define A_PM_TX_DBG_DATA 0x8ff4
#define A_PM_TX_INT_ENABLE 0x8ff8
#define S_PCMD_LEN_OVFL0 31
@@ -14293,6 +21503,636 @@
#define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
#define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U)
+#define S_OSPI_OR_BUNDLE_LEN_PAR_ERR 3
+#define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
+#define F_OSPI_OR_BUNDLE_LEN_PAR_ERR V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
+
+#define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
+#define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
+#define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
+#define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
+#define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
+#define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
+#define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
+#define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
+#define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
+#define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
+#define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
+#define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
+#define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
+#define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
+#define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
+#define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
+#define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
+#define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
+#define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
+#define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
+#define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
+#define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015
+#define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016
+#define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017
+#define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018
+#define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019
+#define A_PM_TX_DBG_STAT_MSB 0x1001a
+#define A_PM_TX_DBG_STAT_LSB 0x1001b
+#define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c
+#define A_PM_TX_SDC_EN 0x1001d
+#define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e
+#define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f
+#define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020
+#define A_PM_TX_FEATURE_EN 0x10021
+
+#define S_PIO_CH_DEFICIT_CTL_EN 2
+#define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN)
+#define F_PIO_CH_DEFICIT_CTL_EN V_PIO_CH_DEFICIT_CTL_EN(1U)
+
+#define S_PIO_WRR_BASED_PRFTCH_EN 1
+#define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN)
+#define F_PIO_WRR_BASED_PRFTCH_EN V_PIO_WRR_BASED_PRFTCH_EN(1U)
+
+#define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022
+
+#define S_OSPI_OVERFLOW3 7
+#define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3)
+#define F_OSPI_OVERFLOW3 V_OSPI_OVERFLOW3(1U)
+
+#define S_OSPI_OVERFLOW2 6
+#define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2)
+#define F_OSPI_OVERFLOW2 V_OSPI_OVERFLOW2(1U)
+
+#define S_M_INTFPERREN 3
+#define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN)
+#define F_M_INTFPERREN V_M_INTFPERREN(1U)
+
+#define S_BUNDLE_LEN_PARERR_EN 2
+#define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN)
+#define F_BUNDLE_LEN_PARERR_EN V_BUNDLE_LEN_PARERR_EN(1U)
+
+#define S_BUNDLE_LEN_OVFL_EN 1
+#define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN)
+#define F_BUNDLE_LEN_OVFL_EN V_BUNDLE_LEN_OVFL_EN(1U)
+
+#define S_SDC_ERR_EN 0
+#define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN)
+#define F_SDC_ERR_EN V_SDC_ERR_EN(1U)
+
+#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
+#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
+#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
+#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
+#define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
+#define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
+#define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
+
+#define S_CH2_OSPI_DEFICIT_THRSHLD 0
+#define M_CH2_OSPI_DEFICIT_THRSHLD 0xfffU
+#define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD)
+#define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD)
+
+#define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
+
+#define S_CH3_OSPI_DEFICIT_THRSHLD 0
+#define M_CH3_OSPI_DEFICIT_THRSHLD 0xfffU
+#define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD)
+#define G_CH3_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD)
+
+#define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
+#define A_PM_TX_DBG_STAT0 0x1002c
+
+#define S_RD_I_BUSY 28
+#define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY)
+#define F_RD_I_BUSY V_RD_I_BUSY(1U)
+
+#define S_WR_O_ONLY 27
+#define V_WR_O_ONLY(x) ((x) << S_WR_O_ONLY)
+#define F_WR_O_ONLY V_WR_O_ONLY(1U)
+
+#define S_M_TO_BUSY 26
+#define V_M_TO_BUSY(x) ((x) << S_M_TO_BUSY)
+#define F_M_TO_BUSY V_M_TO_BUSY(1U)
+
+#define S_I_TO_M_BUSY 25
+#define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY)
+#define F_I_TO_M_BUSY V_I_TO_M_BUSY(1U)
+
+#define S_PCMD_FB_ONLY 24
+#define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY)
+#define F_PCMD_FB_ONLY V_PCMD_FB_ONLY(1U)
+
+#define S_PCMD_MEM 23
+#define V_PCMD_MEM(x) ((x) << S_PCMD_MEM)
+#define F_PCMD_MEM V_PCMD_MEM(1U)
+
+#define S_PCMD_BYPASS 22
+#define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS)
+#define F_PCMD_BYPASS V_PCMD_BYPASS(1U)
+
+#define S_PCMD_EOP 21
+#define V_PCMD_EOP(x) ((x) << S_PCMD_EOP)
+#define F_PCMD_EOP V_PCMD_EOP(1U)
+
+#define S_PCMD_END_BUNDLE 20
+#define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE)
+#define F_PCMD_END_BUNDLE V_PCMD_END_BUNDLE(1U)
+
+#define S_PCMD_FB_CMD 16
+#define M_PCMD_FB_CMD 0xfU
+#define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD)
+#define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD)
+
+#define S_CUR_PCMD_LEN 0
+#define M_CUR_PCMD_LEN 0xffffU
+#define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN)
+#define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN)
+
+#define A_PM_TX_DBG_STAT1 0x1002d
+
+#define S_PCMD_MEM0 31
+#define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0)
+#define F_PCMD_MEM0 V_PCMD_MEM0(1U)
+
+#define S_FREE_OESPI_CNT0 19
+#define M_FREE_OESPI_CNT0 0xfffU
+#define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0)
+#define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0)
+
+#define S_PCMD_FLIT_LEN0 7
+#define M_PCMD_FLIT_LEN0 0xfffU
+#define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0)
+#define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0)
+
+#define S_PCMD_CMD0 3
+#define M_PCMD_CMD0 0xfU
+#define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0)
+#define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0)
+
+#define S_OFIFO_FULL0 2
+#define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0)
+#define F_OFIFO_FULL0 V_OFIFO_FULL0(1U)
+
+#define S_GCSUM_DRDY0 1
+#define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0)
+#define F_GCSUM_DRDY0 V_GCSUM_DRDY0(1U)
+
+#define S_BYPASS0 0
+#define V_BYPASS0(x) ((x) << S_BYPASS0)
+#define F_BYPASS0 V_BYPASS0(1U)
+
+#define A_PM_TX_DBG_STAT2 0x1002e
+
+#define S_PCMD_MEM1 31
+#define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1)
+#define F_PCMD_MEM1 V_PCMD_MEM1(1U)
+
+#define S_FREE_OESPI_CNT1 19
+#define M_FREE_OESPI_CNT1 0xfffU
+#define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1)
+#define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1)
+
+#define S_PCMD_FLIT_LEN1 7
+#define M_PCMD_FLIT_LEN1 0xfffU
+#define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1)
+#define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1)
+
+#define S_PCMD_CMD1 3
+#define M_PCMD_CMD1 0xfU
+#define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1)
+#define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1)
+
+#define S_OFIFO_FULL1 2
+#define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1)
+#define F_OFIFO_FULL1 V_OFIFO_FULL1(1U)
+
+#define S_GCSUM_DRDY1 1
+#define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1)
+#define F_GCSUM_DRDY1 V_GCSUM_DRDY1(1U)
+
+#define S_BYPASS1 0
+#define V_BYPASS1(x) ((x) << S_BYPASS1)
+#define F_BYPASS1 V_BYPASS1(1U)
+
+#define A_PM_TX_DBG_STAT3 0x1002f
+
+#define S_PCMD_MEM2 31
+#define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2)
+#define F_PCMD_MEM2 V_PCMD_MEM2(1U)
+
+#define S_FREE_OESPI_CNT2 19
+#define M_FREE_OESPI_CNT2 0xfffU
+#define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2)
+#define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2)
+
+#define S_PCMD_FLIT_LEN2 7
+#define M_PCMD_FLIT_LEN2 0xfffU
+#define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2)
+#define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2)
+
+#define S_PCMD_CMD2 3
+#define M_PCMD_CMD2 0xfU
+#define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2)
+#define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2)
+
+#define S_OFIFO_FULL2 2
+#define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2)
+#define F_OFIFO_FULL2 V_OFIFO_FULL2(1U)
+
+#define S_GCSUM_DRDY2 1
+#define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2)
+#define F_GCSUM_DRDY2 V_GCSUM_DRDY2(1U)
+
+#define S_BYPASS2 0
+#define V_BYPASS2(x) ((x) << S_BYPASS2)
+#define F_BYPASS2 V_BYPASS2(1U)
+
+#define A_PM_TX_DBG_STAT4 0x10030
+
+#define S_PCMD_MEM3 31
+#define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3)
+#define F_PCMD_MEM3 V_PCMD_MEM3(1U)
+
+#define S_FREE_OESPI_CNT3 19
+#define M_FREE_OESPI_CNT3 0xfffU
+#define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3)
+#define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3)
+
+#define S_PCMD_FLIT_LEN3 7
+#define M_PCMD_FLIT_LEN3 0xfffU
+#define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3)
+#define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3)
+
+#define S_PCMD_CMD3 3
+#define M_PCMD_CMD3 0xfU
+#define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3)
+#define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3)
+
+#define S_OFIFO_FULL3 2
+#define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3)
+#define F_OFIFO_FULL3 V_OFIFO_FULL3(1U)
+
+#define S_GCSUM_DRDY3 1
+#define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3)
+#define F_GCSUM_DRDY3 V_GCSUM_DRDY3(1U)
+
+#define S_BYPASS3 0
+#define V_BYPASS3(x) ((x) << S_BYPASS3)
+#define F_BYPASS3 V_BYPASS3(1U)
+
+#define A_PM_TX_DBG_STAT5 0x10031
+
+#define S_SET_PCMD_RES_RDY_RD 24
+#define M_SET_PCMD_RES_RDY_RD 0xfU
+#define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD)
+#define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD)
+
+#define S_ISSUED_PREF_RD_ER_CLR 20
+#define M_ISSUED_PREF_RD_ER_CLR 0xfU
+#define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR)
+#define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR)
+
+#define S_ISSUED_PREF_RD 16
+#define M_ISSUED_PREF_RD 0xfU
+#define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD)
+#define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD)
+
+#define S_PCMD_RES_RDY 12
+#define M_PCMD_RES_RDY 0xfU
+#define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY)
+#define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY)
+
+#define S_DB_VLD 11
+#define V_DB_VLD(x) ((x) << S_DB_VLD)
+#define F_DB_VLD V_DB_VLD(1U)
+
+#define S_INJECT0_DRDY 10
+#define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY)
+#define F_INJECT0_DRDY V_INJECT0_DRDY(1U)
+
+#define S_INJECT1_DRDY 9
+#define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY)
+#define F_INJECT1_DRDY V_INJECT1_DRDY(1U)
+
+#define S_FIRST_BUNDLE 5
+#define M_FIRST_BUNDLE 0xfU
+#define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE)
+#define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE)
+
+#define S_GCSUM_MORE_THAN_2_LEFT 1
+#define M_GCSUM_MORE_THAN_2_LEFT 0xfU
+#define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT)
+#define G_GCSUM_MORE_THAN_2_LEFT(x) (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT)
+
+#define S_SDC_DRDY 0
+#define V_SDC_DRDY(x) ((x) << S_SDC_DRDY)
+#define F_SDC_DRDY V_SDC_DRDY(1U)
+
+#define A_PM_TX_DBG_STAT6 0x10032
+
+#define S_PCMD_VLD 31
+#define V_PCMD_VLD(x) ((x) << S_PCMD_VLD)
+#define F_PCMD_VLD V_PCMD_VLD(1U)
+
+#define S_PCMD_CH 29
+#define M_PCMD_CH 0x3U
+#define V_PCMD_CH(x) ((x) << S_PCMD_CH)
+#define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH)
+
+#define S_STATE_MACHINE_LOC 24
+#define M_STATE_MACHINE_LOC 0x1fU
+#define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC)
+#define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC)
+
+#define S_ICSPI_TXVALID 20
+#define M_ICSPI_TXVALID 0xfU
+#define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID)
+#define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID)
+
+#define S_ICSPI_TXFULL 16
+#define M_ICSPI_TXFULL 0xfU
+#define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL)
+#define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL)
+
+#define S_PCMD_SRDY 12
+#define M_PCMD_SRDY 0xfU
+#define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY)
+#define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY)
+
+#define S_PCMD_DRDY 8
+#define M_PCMD_DRDY 0xfU
+#define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY)
+#define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY)
+
+#define S_PCMD_CMD 4
+#define M_PCMD_CMD 0xfU
+#define V_PCMD_CMD(x) ((x) << S_PCMD_CMD)
+#define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD)
+
+#define S_OEFIFO_FULL3 3
+#define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3)
+#define F_OEFIFO_FULL3 V_OEFIFO_FULL3(1U)
+
+#define S_OEFIFO_FULL2 2
+#define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2)
+#define F_OEFIFO_FULL2 V_OEFIFO_FULL2(1U)
+
+#define S_OEFIFO_FULL1 1
+#define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1)
+#define F_OEFIFO_FULL1 V_OEFIFO_FULL1(1U)
+
+#define S_OEFIFO_FULL0 0
+#define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0)
+#define F_OEFIFO_FULL0 V_OEFIFO_FULL0(1U)
+
+#define A_PM_TX_DBG_STAT7 0x10033
+
+#define S_ICSPI_RXVALID 28
+#define M_ICSPI_RXVALID 0xfU
+#define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID)
+#define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID)
+
+#define S_ICSPI_RXFULL 24
+#define M_ICSPI_RXFULL 0xfU
+#define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL)
+#define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL)
+
+#define S_OESPI_VALID 20
+#define M_OESPI_VALID 0xfU
+#define V_OESPI_VALID(x) ((x) << S_OESPI_VALID)
+#define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID)
+
+#define S_OESPI_FULL 16
+#define M_OESPI_FULL 0xfU
+#define V_OESPI_FULL(x) ((x) << S_OESPI_FULL)
+#define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL)
+
+#define S_C_RXVALID 12
+#define M_C_RXVALID 0xfU
+#define V_C_RXVALID(x) ((x) << S_C_RXVALID)
+#define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID)
+
+#define S_C_RXAFULL 8
+#define M_C_RXAFULL 0xfU
+#define V_C_RXAFULL(x) ((x) << S_C_RXAFULL)
+#define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL)
+
+#define S_E_TXVALID3 7
+#define V_E_TXVALID3(x) ((x) << S_E_TXVALID3)
+#define F_E_TXVALID3 V_E_TXVALID3(1U)
+
+#define S_E_TXVALID2 6
+#define V_E_TXVALID2(x) ((x) << S_E_TXVALID2)
+#define F_E_TXVALID2 V_E_TXVALID2(1U)
+
+#define S_E_TXVALID1 5
+#define V_E_TXVALID1(x) ((x) << S_E_TXVALID1)
+#define F_E_TXVALID1 V_E_TXVALID1(1U)
+
+#define S_E_TXVALID0 4
+#define V_E_TXVALID0(x) ((x) << S_E_TXVALID0)
+#define F_E_TXVALID0 V_E_TXVALID0(1U)
+
+#define S_E_TXFULL3 3
+#define V_E_TXFULL3(x) ((x) << S_E_TXFULL3)
+#define F_E_TXFULL3 V_E_TXFULL3(1U)
+
+#define S_E_TXFULL2 2
+#define V_E_TXFULL2(x) ((x) << S_E_TXFULL2)
+#define F_E_TXFULL2 V_E_TXFULL2(1U)
+
+#define S_E_TXFULL1 1
+#define V_E_TXFULL1(x) ((x) << S_E_TXFULL1)
+#define F_E_TXFULL1 V_E_TXFULL1(1U)
+
+#define S_E_TXFULL0 0
+#define V_E_TXFULL0(x) ((x) << S_E_TXFULL0)
+#define F_E_TXFULL0 V_E_TXFULL0(1U)
+
+#define A_PM_TX_DBG_STAT8 0x10034
+
+#define S_MC_RSP_FIFO_CNT 24
+#define M_MC_RSP_FIFO_CNT 0x3U
+#define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT)
+#define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT)
+
+#define S_PCMD_FREE_CNT0 14
+#define M_PCMD_FREE_CNT0 0x3ffU
+#define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0)
+#define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0)
+
+#define S_PCMD_FREE_CNT1 4
+#define M_PCMD_FREE_CNT1 0x3ffU
+#define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1)
+#define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1)
+
+#define S_M_REQADDRRDY 3
+#define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY)
+#define F_M_REQADDRRDY V_M_REQADDRRDY(1U)
+
+#define S_M_REQWRITE 2
+#define V_M_REQWRITE(x) ((x) << S_M_REQWRITE)
+#define F_M_REQWRITE V_M_REQWRITE(1U)
+
+#define S_M_REQDATAVLD 1
+#define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD)
+#define F_M_REQDATAVLD V_M_REQDATAVLD(1U)
+
+#define S_M_REQDATARDY 0
+#define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY)
+#define F_M_REQDATARDY V_M_REQDATARDY(1U)
+
+#define A_PM_TX_DBG_STAT9 0x10035
+
+#define S_PCMD_FREE_CNT2 10
+#define M_PCMD_FREE_CNT2 0x3ffU
+#define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2)
+#define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2)
+
+#define S_PCMD_FREE_CNT3 0
+#define M_PCMD_FREE_CNT3 0x3ffU
+#define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3)
+#define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3)
+
+#define A_PM_TX_DBG_STAT10 0x10036
+
+#define S_IN_EOP_CNT3 28
+#define M_IN_EOP_CNT3 0xfU
+#define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3)
+#define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3)
+
+#define S_IN_EOP_CNT2 24
+#define M_IN_EOP_CNT2 0xfU
+#define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2)
+#define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2)
+
+#define S_IN_EOP_CNT1 20
+#define M_IN_EOP_CNT1 0xfU
+#define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1)
+#define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1)
+
+#define S_IN_EOP_CNT0 16
+#define M_IN_EOP_CNT0 0xfU
+#define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0)
+#define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0)
+
+#define S_IN_SOP_CNT3 12
+#define M_IN_SOP_CNT3 0xfU
+#define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3)
+#define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3)
+
+#define S_IN_SOP_CNT2 8
+#define M_IN_SOP_CNT2 0xfU
+#define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2)
+#define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2)
+
+#define S_IN_SOP_CNT1 4
+#define M_IN_SOP_CNT1 0xfU
+#define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1)
+#define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1)
+
+#define S_IN_SOP_CNT0 0
+#define M_IN_SOP_CNT0 0xfU
+#define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0)
+#define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0)
+
+#define A_PM_TX_DBG_STAT11 0x10037
+
+#define S_OUT_EOP_CNT3 28
+#define M_OUT_EOP_CNT3 0xfU
+#define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3)
+#define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3)
+
+#define S_OUT_EOP_CNT2 24
+#define M_OUT_EOP_CNT2 0xfU
+#define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2)
+#define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2)
+
+#define S_OUT_EOP_CNT1 20
+#define M_OUT_EOP_CNT1 0xfU
+#define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1)
+#define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1)
+
+#define S_OUT_EOP_CNT0 16
+#define M_OUT_EOP_CNT0 0xfU
+#define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0)
+#define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0)
+
+#define S_OUT_SOP_CNT3 12
+#define M_OUT_SOP_CNT3 0xfU
+#define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3)
+#define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3)
+
+#define S_OUT_SOP_CNT2 8
+#define M_OUT_SOP_CNT2 0xfU
+#define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2)
+#define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2)
+
+#define S_OUT_SOP_CNT1 4
+#define M_OUT_SOP_CNT1 0xfU
+#define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1)
+#define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1)
+
+#define S_OUT_SOP_CNT0 0
+#define M_OUT_SOP_CNT0 0xfU
+#define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0)
+#define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0)
+
+#define A_PM_TX_DBG_STAT12 0x10038
+#define A_PM_TX_DBG_STAT13 0x10039
+
+#define S_CH_DEFICIT_BLOWED 31
+#define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED)
+#define F_CH_DEFICIT_BLOWED V_CH_DEFICIT_BLOWED(1U)
+
+#define S_CH1_DEFICIT 16
+#define M_CH1_DEFICIT 0xfffU
+#define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT)
+#define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT)
+
+#define S_CH0_DEFICIT 0
+#define M_CH0_DEFICIT 0xfffU
+#define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT)
+#define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT)
+
+#define A_PM_TX_DBG_STAT14 0x1003a
+
+#define S_CH3_DEFICIT 16
+#define M_CH3_DEFICIT 0xfffU
+#define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT)
+#define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT)
+
+#define S_CH2_DEFICIT 0
+#define M_CH2_DEFICIT 0xfffU
+#define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT)
+#define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT)
+
+#define A_PM_TX_DBG_STAT15 0x1003b
+
+#define S_BUNDLE_LEN_SRDY 28
+#define M_BUNDLE_LEN_SRDY 0xfU
+#define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY)
+#define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY)
+
+#define S_BUNDLE_LEN1 16
+#define M_BUNDLE_LEN1 0xfffU
+#define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1)
+#define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1)
+
+#define S_BUNDLE_LEN0 0
+#define M_BUNDLE_LEN0 0xfffU
+#define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0)
+#define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0)
+
+#define A_PM_TX_DBG_STAT16 0x1003c
+
+#define S_BUNDLE_LEN3 16
+#define M_BUNDLE_LEN3 0xfffU
+#define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3)
+#define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3)
+
+#define S_BUNDLE_LEN2 0
+#define M_BUNDLE_LEN2 0xfffU
+#define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2)
+#define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2)
+
/* registers for module MPS */
#define MPS_BASE_ADDR 0x9000
@@ -14456,6 +22296,48 @@
#define V_PRTY0(x) ((x) << S_PRTY0)
#define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0)
+#define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30
+
+#define S_TXPRTY7 28
+#define M_TXPRTY7 0xfU
+#define V_TXPRTY7(x) ((x) << S_TXPRTY7)
+#define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7)
+
+#define S_TXPRTY6 24
+#define M_TXPRTY6 0xfU
+#define V_TXPRTY6(x) ((x) << S_TXPRTY6)
+#define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6)
+
+#define S_TXPRTY5 20
+#define M_TXPRTY5 0xfU
+#define V_TXPRTY5(x) ((x) << S_TXPRTY5)
+#define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5)
+
+#define S_TXPRTY4 16
+#define M_TXPRTY4 0xfU
+#define V_TXPRTY4(x) ((x) << S_TXPRTY4)
+#define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4)
+
+#define S_TXPRTY3 12
+#define M_TXPRTY3 0xfU
+#define V_TXPRTY3(x) ((x) << S_TXPRTY3)
+#define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3)
+
+#define S_TXPRTY2 8
+#define M_TXPRTY2 0xfU
+#define V_TXPRTY2(x) ((x) << S_TXPRTY2)
+#define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2)
+
+#define S_TXPRTY1 4
+#define M_TXPRTY1 0xfU
+#define V_TXPRTY1(x) ((x) << S_TXPRTY1)
+#define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1)
+
+#define S_TXPRTY0 0
+#define M_TXPRTY0 0xfU
+#define V_TXPRTY0(x) ((x) << S_TXPRTY0)
+#define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0)
+
#define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
#define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
#define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
@@ -14571,6 +22453,10 @@
#define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
#define F_OVLAN_EN0 V_OVLAN_EN0(1U)
+#define S_PTP_FWD_UP 21
+#define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP)
+#define F_PTP_FWD_UP V_PTP_FWD_UP(1U)
+
#define A_MPS_PORT_RX_MTU 0x104
#define A_MPS_PORT_RX_PF_MAP 0x108
#define A_MPS_PORT_RX_VF_MAP0 0x10c
@@ -14641,6 +22527,8 @@
#define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
#define A_MPS_PORT_RX_SPARE 0x13c
+#define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
+#define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
#define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
#define S_CREDIT 0
@@ -14674,6 +22562,23 @@
#define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
#define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
+
+#define S_FPGAPAUSEEN 0
+#define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN)
+#define F_FPGAPAUSEEN V_FPGAPAUSEEN(1U)
+
+#define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0
+
+#define S_OFF_PENDING 8
+#define M_OFF_PENDING 0xffU
+#define V_OFF_PENDING(x) ((x) << S_OFF_PENDING)
+#define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING)
+
+#define S_ON_PENDING 0
+#define M_ON_PENDING 0xffU
+#define V_ON_PENDING(x) ((x) << S_ON_PENDING)
+#define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING)
+
#define A_MPS_PORT_CLS_HASH_SRAM 0x200
#define S_VALID 20
@@ -14789,6 +22694,50 @@
#define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL)
#define F_PF_VLAN_SEL V_PF_VLAN_SEL(1U)
+#define S_LPBK_TCAM1_HIT_PRIORITY 14
+#define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY)
+#define F_LPBK_TCAM1_HIT_PRIORITY V_LPBK_TCAM1_HIT_PRIORITY(1U)
+
+#define S_LPBK_TCAM0_HIT_PRIORITY 13
+#define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY)
+#define F_LPBK_TCAM0_HIT_PRIORITY V_LPBK_TCAM0_HIT_PRIORITY(1U)
+
+#define S_LPBK_TCAM_PRIORITY 12
+#define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY)
+#define F_LPBK_TCAM_PRIORITY V_LPBK_TCAM_PRIORITY(1U)
+
+#define S_LPBK_SMAC_TCAM_SEL 10
+#define M_LPBK_SMAC_TCAM_SEL 0x3U
+#define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL)
+#define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL)
+
+#define S_LPBK_DMAC_TCAM_SEL 8
+#define M_LPBK_DMAC_TCAM_SEL 0x3U
+#define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL)
+#define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL)
+
+#define S_TCAM1_HIT_PRIORITY 7
+#define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY)
+#define F_TCAM1_HIT_PRIORITY V_TCAM1_HIT_PRIORITY(1U)
+
+#define S_TCAM0_HIT_PRIORITY 6
+#define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY)
+#define F_TCAM0_HIT_PRIORITY V_TCAM0_HIT_PRIORITY(1U)
+
+#define S_TCAM_PRIORITY 5
+#define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY)
+#define F_TCAM_PRIORITY V_TCAM_PRIORITY(1U)
+
+#define S_SMAC_TCAM_SEL 3
+#define M_SMAC_TCAM_SEL 0x3U
+#define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL)
+#define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL)
+
+#define S_DMAC_TCAM_SEL 1
+#define M_DMAC_TCAM_SEL 0x3U
+#define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL)
+#define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
+
#define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
#define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
#define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
@@ -14889,6 +22838,8 @@
#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
+#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
+#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
#define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
#define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
#define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
@@ -14943,6 +22894,8 @@
#define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
+#define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
+#define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
#define A_MPS_CMN_CTL 0x9000
#define S_DETECT8023 3
@@ -14958,6 +22911,10 @@
#define V_NUMPORTS(x) ((x) << S_NUMPORTS)
#define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
+#define S_LPBKCRDTCTRL 4
+#define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
+#define F_LPBKCRDTCTRL V_LPBKCRDTCTRL(1U)
+
#define A_MPS_INT_ENABLE 0x9004
#define S_STATINTENB 5
@@ -15010,6 +22967,12 @@
#define V_PLINT(x) ((x) << S_PLINT)
#define F_PLINT V_PLINT(1U)
+#define A_MPS_CGEN_GLOBAL 0x900c
+
+#define S_MPS_GLOBAL_CGEN 0
+#define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN)
+#define F_MPS_GLOBAL_CGEN V_MPS_GLOBAL_CGEN(1U)
+
#define A_MPS_VF_TX_CTL_31_0 0x9010
#define A_MPS_VF_TX_CTL_63_32 0x9014
#define A_MPS_VF_TX_CTL_95_64 0x9018
@@ -15072,6 +23035,11 @@
#define V_CH_MAP0(x) ((x) << S_CH_MAP0)
#define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0)
+#define S_FPGA_PTP_PORT 9
+#define M_FPGA_PTP_PORT 0x3U
+#define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT)
+#define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT)
+
#define A_MPS_DEBUG_CTL 0x9068
#define S_DBGMODECTL_H 11
@@ -15096,16 +23064,11 @@
#define A_MPS_DEBUG_DATA_REG_H 0x9070
#define A_MPS_TOP_SPARE 0x9074
-#define S_TOPSPARE 12
-#define M_TOPSPARE 0xfffffU
+#define S_TOPSPARE 8
+#define M_TOPSPARE 0xffffffU
#define V_TOPSPARE(x) ((x) << S_TOPSPARE)
#define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE)
-#define S_CHIKN_14463 8
-#define M_CHIKN_14463 0xfU
-#define V_CHIKN_14463(x) ((x) << S_CHIKN_14463)
-#define G_CHIKN_14463(x) (((x) >> S_CHIKN_14463) & M_CHIKN_14463)
-
#define S_OVLANSELLPBK3 7
#define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3)
#define F_OVLANSELLPBK3 V_OVLANSELLPBK3(1U)
@@ -15138,6 +23101,44 @@
#define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0)
#define F_OVLANSELMAC0 V_OVLANSELMAC0(1U)
+#define S_T5_TOPSPARE 8
+#define M_T5_TOPSPARE 0xffffffU
+#define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE)
+#define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE)
+
+#define A_MPS_T5_BUILD_REVISION 0x9078
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
#define A_MPS_BUILD_REVISION 0x90fc
#define A_MPS_TX_PRTY_SEL 0x9400
@@ -15250,6 +23251,15 @@
#define V_BUBBLECLR(x) ((x) << S_BUBBLECLR)
#define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR)
+#define S_NCSISECNT 20
+#define V_NCSISECNT(x) ((x) << S_NCSISECNT)
+#define F_NCSISECNT V_NCSISECNT(1U)
+
+#define S_LPBKSECNT 16
+#define M_LPBKSECNT 0xfU
+#define V_LPBKSECNT(x) ((x) << S_LPBKSECNT)
+#define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT)
+
#define A_MPS_TX_PORT_ERR 0x9430
#define S_LPBKPT3 7
@@ -15552,6 +23562,13 @@
#define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR)
#define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR)
+#define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454
+
+#define S_T5SGEPAUSEIGNR 0
+#define M_T5SGEPAUSEIGNR 0xffffU
+#define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR)
+#define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR)
+
#define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
#define S_SUBPRTH 11
@@ -15574,6 +23591,182 @@
#define V_PORTL(x) ((x) << S_PORTL)
#define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL)
+#define A_MPS_TX_PAD_CTL 0x945c
+
+#define S_LPBKPADENPT3 7
+#define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3)
+#define F_LPBKPADENPT3 V_LPBKPADENPT3(1U)
+
+#define S_LPBKPADENPT2 6
+#define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2)
+#define F_LPBKPADENPT2 V_LPBKPADENPT2(1U)
+
+#define S_LPBKPADENPT1 5
+#define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1)
+#define F_LPBKPADENPT1 V_LPBKPADENPT1(1U)
+
+#define S_LPBKPADENPT0 4
+#define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0)
+#define F_LPBKPADENPT0 V_LPBKPADENPT0(1U)
+
+#define S_MACPADENPT3 3
+#define V_MACPADENPT3(x) ((x) << S_MACPADENPT3)
+#define F_MACPADENPT3 V_MACPADENPT3(1U)
+
+#define S_MACPADENPT2 2
+#define V_MACPADENPT2(x) ((x) << S_MACPADENPT2)
+#define F_MACPADENPT2 V_MACPADENPT2(1U)
+
+#define S_MACPADENPT1 1
+#define V_MACPADENPT1(x) ((x) << S_MACPADENPT1)
+#define F_MACPADENPT1 V_MACPADENPT1(1U)
+
+#define S_MACPADENPT0 0
+#define V_MACPADENPT0(x) ((x) << S_MACPADENPT0)
+#define F_MACPADENPT0 V_MACPADENPT0(1U)
+
+#define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460
+
+#define S_TP2MPS_CH3 24
+#define M_TP2MPS_CH3 0xffU
+#define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3)
+#define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3)
+
+#define S_TP2MPS_CH2 16
+#define M_TP2MPS_CH2 0xffU
+#define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2)
+#define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2)
+
+#define S_TP2MPS_CH1 8
+#define M_TP2MPS_CH1 0xffU
+#define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1)
+#define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1)
+
+#define S_TP2MPS_CH0 0
+#define M_TP2MPS_CH0 0xffU
+#define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0)
+#define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0)
+
+#define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464
+
+#define S_NCSI_CH4 0
+#define M_NCSI_CH4 0xffU
+#define V_NCSI_CH4(x) ((x) << S_NCSI_CH4)
+#define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4)
+
+#define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468
+
+#define S_PFNOVFDROP 5
+#define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP)
+#define F_PFNOVFDROP V_PFNOVFDROP(1U)
+
+#define S_NCSI_CH4_CLR 4
+#define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR)
+#define F_NCSI_CH4_CLR V_NCSI_CH4_CLR(1U)
+
+#define S_TP2MPS_CH3_CLR 3
+#define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR)
+#define F_TP2MPS_CH3_CLR V_TP2MPS_CH3_CLR(1U)
+
+#define S_TP2MPS_CH2_CLR 2
+#define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR)
+#define F_TP2MPS_CH2_CLR V_TP2MPS_CH2_CLR(1U)
+
+#define S_TP2MPS_CH1_CLR 1
+#define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR)
+#define F_TP2MPS_CH1_CLR V_TP2MPS_CH1_CLR(1U)
+
+#define S_TP2MPS_CH0_CLR 0
+#define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR)
+#define F_TP2MPS_CH0_CLR V_TP2MPS_CH0_CLR(1U)
+
+#define A_MPS_TX_CGEN 0x946c
+
+#define S_TXOUTLPBK3_CGEN 31
+#define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN)
+#define F_TXOUTLPBK3_CGEN V_TXOUTLPBK3_CGEN(1U)
+
+#define S_TXOUTLPBK2_CGEN 30
+#define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN)
+#define F_TXOUTLPBK2_CGEN V_TXOUTLPBK2_CGEN(1U)
+
+#define S_TXOUTLPBK1_CGEN 29
+#define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN)
+#define F_TXOUTLPBK1_CGEN V_TXOUTLPBK1_CGEN(1U)
+
+#define S_TXOUTLPBK0_CGEN 28
+#define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN)
+#define F_TXOUTLPBK0_CGEN V_TXOUTLPBK0_CGEN(1U)
+
+#define S_TXOUTMAC3_CGEN 27
+#define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN)
+#define F_TXOUTMAC3_CGEN V_TXOUTMAC3_CGEN(1U)
+
+#define S_TXOUTMAC2_CGEN 26
+#define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN)
+#define F_TXOUTMAC2_CGEN V_TXOUTMAC2_CGEN(1U)
+
+#define S_TXOUTMAC1_CGEN 25
+#define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN)
+#define F_TXOUTMAC1_CGEN V_TXOUTMAC1_CGEN(1U)
+
+#define S_TXOUTMAC0_CGEN 24
+#define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN)
+#define F_TXOUTMAC0_CGEN V_TXOUTMAC0_CGEN(1U)
+
+#define S_TXSCHLPBK3_CGEN 23
+#define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN)
+#define F_TXSCHLPBK3_CGEN V_TXSCHLPBK3_CGEN(1U)
+
+#define S_TXSCHLPBK2_CGEN 22
+#define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN)
+#define F_TXSCHLPBK2_CGEN V_TXSCHLPBK2_CGEN(1U)
+
+#define S_TXSCHLPBK1_CGEN 21
+#define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN)
+#define F_TXSCHLPBK1_CGEN V_TXSCHLPBK1_CGEN(1U)
+
+#define S_TXSCHLPBK0_CGEN 20
+#define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN)
+#define F_TXSCHLPBK0_CGEN V_TXSCHLPBK0_CGEN(1U)
+
+#define S_TXSCHMAC3_CGEN 19
+#define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN)
+#define F_TXSCHMAC3_CGEN V_TXSCHMAC3_CGEN(1U)
+
+#define S_TXSCHMAC2_CGEN 18
+#define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN)
+#define F_TXSCHMAC2_CGEN V_TXSCHMAC2_CGEN(1U)
+
+#define S_TXSCHMAC1_CGEN 17
+#define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN)
+#define F_TXSCHMAC1_CGEN V_TXSCHMAC1_CGEN(1U)
+
+#define S_TXSCHMAC0_CGEN 16
+#define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN)
+#define F_TXSCHMAC0_CGEN V_TXSCHMAC0_CGEN(1U)
+
+#define S_TXINCH4_CGEN 15
+#define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN)
+#define F_TXINCH4_CGEN V_TXINCH4_CGEN(1U)
+
+#define S_TXINCH3_CGEN 14
+#define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN)
+#define F_TXINCH3_CGEN V_TXINCH3_CGEN(1U)
+
+#define S_TXINCH2_CGEN 13
+#define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN)
+#define F_TXINCH2_CGEN V_TXINCH2_CGEN(1U)
+
+#define S_TXINCH1_CGEN 12
+#define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN)
+#define F_TXINCH1_CGEN V_TXINCH1_CGEN(1U)
+
+#define S_TXINCH0_CGEN 11
+#define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN)
+#define F_TXINCH0_CGEN V_TXINCH0_CGEN(1U)
+
+#define A_MPS_TX_CGEN_DYNAMIC 0x9470
#define A_MPS_STAT_CTL 0x9600
#define S_COUNTVFINPF 1
@@ -15584,6 +23777,42 @@
#define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT)
#define F_LPBKERRSTAT V_LPBKERRSTAT(1U)
+#define S_STATSTOPCTRL 10
+#define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
+#define F_STATSTOPCTRL V_STATSTOPCTRL(1U)
+
+#define S_STOPSTAT 9
+#define V_STOPSTAT(x) ((x) << S_STOPSTAT)
+#define F_STOPSTAT V_STOPSTAT(1U)
+
+#define S_STATWRITECTRL 8
+#define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
+#define F_STATWRITECTRL V_STATWRITECTRL(1U)
+
+#define S_COUNTLBPF 7
+#define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
+#define F_COUNTLBPF V_COUNTLBPF(1U)
+
+#define S_COUNTLBVF 6
+#define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
+#define F_COUNTLBVF V_COUNTLBVF(1U)
+
+#define S_COUNTPAUSEMCRX 5
+#define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
+#define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U)
+
+#define S_COUNTPAUSESTATRX 4
+#define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
+#define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U)
+
+#define S_COUNTPAUSEMCTX 3
+#define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
+#define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U)
+
+#define S_COUNTPAUSESTATTX 2
+#define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
+#define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U)
+
#define A_MPS_STAT_INT_ENABLE 0x9608
#define S_PLREADSYNCERR 0
@@ -15632,6 +23861,36 @@
#define V_TXPORT(x) ((x) << S_TXPORT)
#define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
+#define S_T5_RXBG 27
+#define M_T5_RXBG 0x3U
+#define V_T5_RXBG(x) ((x) << S_T5_RXBG)
+#define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)
+
+#define S_T5_RXPF 22
+#define M_T5_RXPF 0x1fU
+#define V_T5_RXPF(x) ((x) << S_T5_RXPF)
+#define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)
+
+#define S_T5_TXPF 18
+#define M_T5_TXPF 0xfU
+#define V_T5_TXPF(x) ((x) << S_T5_TXPF)
+#define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)
+
+#define S_T5_RXPORT 11
+#define M_T5_RXPORT 0x7fU
+#define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
+#define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)
+
+#define S_T5_LBPORT 6
+#define M_T5_LBPORT 0x1fU
+#define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
+#define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)
+
+#define S_T5_TXPORT 0
+#define M_T5_TXPORT 0x3fU
+#define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
+#define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
+
#define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
#define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
#define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
@@ -15651,6 +23910,11 @@
#define V_DROP(x) ((x) << S_DROP)
#define G_DROP(x) (((x) >> S_DROP) & M_DROP)
+#define S_TXCH 20
+#define M_TXCH 0xfU
+#define V_TXCH(x) ((x) << S_TXCH)
+#define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)
+
#define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
#define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
#define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
@@ -15690,6 +23954,22 @@
#define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL)
#define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
+
+#define S_STATSSUBPRTH 5
+#define M_STATSSUBPRTH 0x1fU
+#define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH)
+#define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH)
+
+#define S_STATSSUBPRTL 0
+#define M_STATSSUBPRTL 0x1fU
+#define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL)
+#define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL)
+
+#define S_STATSUBPRTH 5
+#define M_STATSUBPRTH 0x1fU
+#define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH)
+#define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH)
+
#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
@@ -15722,6 +24002,64 @@
#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
+#define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0
+
+#define S_T5_RXVF 5
+#define M_T5_RXVF 0x7U
+#define V_T5_RXVF(x) ((x) << S_T5_RXVF)
+#define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)
+
+#define S_T5_TXVF 0
+#define M_T5_TXVF 0x1fU
+#define V_T5_TXVF(x) ((x) << S_T5_TXVF)
+#define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
+
+#define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
+#define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
+#define A_MPS_STAT_STOP_UPD_BG 0x96cc
+
+#define S_BGRX 0
+#define M_BGRX 0xfU
+#define V_BGRX(x) ((x) << S_BGRX)
+#define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX)
+
+#define A_MPS_STAT_STOP_UPD_PORT 0x96d0
+
+#define S_PTLPBK 8
+#define M_PTLPBK 0xfU
+#define V_PTLPBK(x) ((x) << S_PTLPBK)
+#define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK)
+
+#define S_PTTX 4
+#define M_PTTX 0xfU
+#define V_PTTX(x) ((x) << S_PTTX)
+#define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX)
+
+#define S_PTRX 0
+#define M_PTRX 0xfU
+#define V_PTRX(x) ((x) << S_PTRX)
+#define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX)
+
+#define A_MPS_STAT_STOP_UPD_PF 0x96d4
+
+#define S_PFTX 8
+#define M_PFTX 0xffU
+#define V_PFTX(x) ((x) << S_PFTX)
+#define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX)
+
+#define S_PFRX 0
+#define M_PFRX 0xffU
+#define V_PFRX(x) ((x) << S_PFRX)
+#define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX)
+
+#define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8
+#define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc
+#define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0
+#define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4
+#define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8
+#define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
+#define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
+#define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
#define A_MPS_TRC_CFG 0x9800
#define S_TRCFIFOEMPTY 4
@@ -15744,7 +24082,12 @@
#define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
#define F_TRCMULTIFILTER V_TRCMULTIFILTER(1U)
+#define S_TRCMULTIRSSFILTER 5
+#define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
+#define F_TRCMULTIRSSFILTER V_TRCMULTIRSSFILTER(1U)
+
#define A_MPS_TRC_RSS_HASH 0x9804
+#define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
#define A_MPS_TRC_RSS_CONTROL 0x9808
#define S_RSSCONTROL 16
@@ -15757,6 +24100,7 @@
#define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
#define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
+#define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808
#define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
#define S_TFINVERTMATCH 24
@@ -15794,6 +24138,31 @@
#define V_TFOFFSET(x) ((x) << S_TFOFFSET)
#define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
+#define S_TFINSERTACTLEN 27
+#define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
+#define F_TFINSERTACTLEN V_TFINSERTACTLEN(1U)
+
+#define S_TFINSERTTIMER 26
+#define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
+#define F_TFINSERTTIMER V_TFINSERTTIMER(1U)
+
+#define S_T5_TFINVERTMATCH 25
+#define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
+#define F_T5_TFINVERTMATCH V_T5_TFINVERTMATCH(1U)
+
+#define S_T5_TFPKTTOOLARGE 24
+#define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
+#define F_T5_TFPKTTOOLARGE V_T5_TFPKTTOOLARGE(1U)
+
+#define S_T5_TFEN 23
+#define V_T5_TFEN(x) ((x) << S_T5_TFEN)
+#define F_T5_TFEN V_T5_TFEN(1U)
+
+#define S_T5_TFPORT 18
+#define M_T5_TFPORT 0x1fU
+#define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
+#define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)
+
#define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
#define S_TFMINPKTSIZE 16
@@ -15865,6 +24234,64 @@
#define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
#define A_MPS_TRC_FILTER3_MATCH 0x9f00
#define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
+#define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0
+#define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4
+#define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
+#define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
+#define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
+#define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
+#define A_MPS_T5_TRC_RSS_HASH 0xa008
+#define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
+#define A_MPS_TRC_VF_OFF_FILTER_0 0xa010
+
+#define S_TRCMPS2TP_MACONLY 20
+#define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY)
+#define F_TRCMPS2TP_MACONLY V_TRCMPS2TP_MACONLY(1U)
+
+#define S_TRCALLMPS2TP 19
+#define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP)
+#define F_TRCALLMPS2TP V_TRCALLMPS2TP(1U)
+
+#define S_TRCALLTP2MPS 18
+#define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS)
+#define F_TRCALLTP2MPS V_TRCALLTP2MPS(1U)
+
+#define S_TRCALLVF 17
+#define V_TRCALLVF(x) ((x) << S_TRCALLVF)
+#define F_TRCALLVF V_TRCALLVF(1U)
+
+#define S_TRC_OFLD_EN 16
+#define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN)
+#define F_TRC_OFLD_EN V_TRC_OFLD_EN(1U)
+
+#define S_VFFILTEN 15
+#define V_VFFILTEN(x) ((x) << S_VFFILTEN)
+#define F_VFFILTEN V_VFFILTEN(1U)
+
+#define S_VFFILTMASK 8
+#define M_VFFILTMASK 0x7fU
+#define V_VFFILTMASK(x) ((x) << S_VFFILTMASK)
+#define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK)
+
+#define S_VFFILTVALID 7
+#define V_VFFILTVALID(x) ((x) << S_VFFILTVALID)
+#define F_VFFILTVALID V_VFFILTVALID(1U)
+
+#define S_VFFILTDATA 0
+#define M_VFFILTDATA 0x7fU
+#define V_VFFILTDATA(x) ((x) << S_VFFILTDATA)
+#define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA)
+
+#define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
+#define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
+#define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
+#define A_MPS_TRC_CGEN 0xa020
+
+#define S_MPSTRCCGEN 0
+#define M_MPSTRCCGEN 0xfU
+#define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN)
+#define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN)
+
#define A_MPS_CLS_CTL 0xd000
#define S_MEMWRITEFAULT 4
@@ -16042,6 +24469,7 @@
#define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
#define F_SRAM_VLD V_SRAM_VLD(1U)
+#define A_MPS_T5_CLS_SRAM_L 0xe000
#define A_MPS_CLS_SRAM_H 0xe004
#define S_MACPARITY1 9
@@ -16062,6 +24490,7 @@
#define V_PORTMAP(x) ((x) << S_PORTMAP)
#define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
+#define A_MPS_T5_CLS_SRAM_H 0xe004
#define A_MPS_CLS_TCAM_Y_L 0xf000
#define A_MPS_CLS_TCAM_Y_H 0xf004
@@ -16157,6 +24586,16 @@
#define V_ALLOC(x) ((x) << S_ALLOC)
#define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
+#define S_T5_USED 16
+#define M_T5_USED 0xfffU
+#define V_T5_USED(x) ((x) << S_T5_USED)
+#define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)
+
+#define S_T5_ALLOC 0
+#define M_T5_ALLOC 0xfffU
+#define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
+#define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
+
#define A_MPS_RX_PG_RSV1 0x11014
#define A_MPS_RX_PG_RSV2 0x11018
#define A_MPS_RX_PG_RSV3 0x1101c
@@ -16184,6 +24623,16 @@
#define V_BORW(x) ((x) << S_BORW)
#define G_BORW(x) (((x) >> S_BORW) & M_BORW)
+#define S_T5_MAX 16
+#define M_T5_MAX 0xfffU
+#define V_T5_MAX(x) ((x) << S_T5_MAX)
+#define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX)
+
+#define S_T5_BORW 0
+#define M_T5_BORW 0xfffU
+#define V_T5_BORW(x) ((x) << S_T5_BORW)
+#define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW)
+
#define A_MPS_RX_PG_SHR_BG1 0x11034
#define A_MPS_RX_PG_SHR_BG2 0x11038
#define A_MPS_RX_PG_SHR_BG3 0x1103c
@@ -16199,6 +24648,16 @@
#define V_SHR_USED(x) ((x) << S_SHR_USED)
#define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED)
+#define S_T5_QUOTA 16
+#define M_T5_QUOTA 0xfffU
+#define V_T5_QUOTA(x) ((x) << S_T5_QUOTA)
+#define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA)
+
+#define S_T5_SHR_USED 0
+#define M_T5_SHR_USED 0xfffU
+#define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED)
+#define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED)
+
#define A_MPS_RX_PG_SHR1 0x11044
#define A_MPS_RX_PG_HYST_BG0 0x11048
@@ -16207,6 +24666,11 @@
#define V_TH(x) ((x) << S_TH)
#define G_TH(x) (((x) >> S_TH) & M_TH)
+#define S_T5_TH 0
+#define M_T5_TH 0xfffU
+#define V_T5_TH(x) ((x) << S_T5_TH)
+#define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH)
+
#define A_MPS_RX_PG_HYST_BG1 0x1104c
#define A_MPS_RX_PG_HYST_BG2 0x11050
#define A_MPS_RX_PG_HYST_BG3 0x11054
@@ -16395,6 +24859,34 @@
#define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0)
#define F_PG_TH_INT0 V_PG_TH_INT0(1U)
+#define S_MTU_ERR_INT3 19
+#define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3)
+#define F_MTU_ERR_INT3 V_MTU_ERR_INT3(1U)
+
+#define S_MTU_ERR_INT2 18
+#define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2)
+#define F_MTU_ERR_INT2 V_MTU_ERR_INT2(1U)
+
+#define S_MTU_ERR_INT1 17
+#define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1)
+#define F_MTU_ERR_INT1 V_MTU_ERR_INT1(1U)
+
+#define S_MTU_ERR_INT0 16
+#define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0)
+#define F_MTU_ERR_INT0 V_MTU_ERR_INT0(1U)
+
+#define S_SE_CNT_ERR_INT 15
+#define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT)
+#define F_SE_CNT_ERR_INT V_SE_CNT_ERR_INT(1U)
+
+#define S_FRM_ERR_INT 14
+#define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT)
+#define F_FRM_ERR_INT V_FRM_ERR_INT(1U)
+
+#define S_LEN_ERR_INT 13
+#define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
+#define F_LEN_ERR_INT V_LEN_ERR_INT(1U)
+
#define A_MPS_RX_FUNC_INT_ENABLE 0x11088
#define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
@@ -16752,6 +25244,123 @@
#define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
#define A_MPS_RX_SPARE 0x11190
+#define A_MPS_RX_PTP_ETYPE 0x11194
+
+#define S_PETYPE2 16
+#define M_PETYPE2 0xffffU
+#define V_PETYPE2(x) ((x) << S_PETYPE2)
+#define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2)
+
+#define S_PETYPE1 0
+#define M_PETYPE1 0xffffU
+#define V_PETYPE1(x) ((x) << S_PETYPE1)
+#define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1)
+
+#define A_MPS_RX_PTP_TCP 0x11198
+
+#define S_PTCPORT2 16
+#define M_PTCPORT2 0xffffU
+#define V_PTCPORT2(x) ((x) << S_PTCPORT2)
+#define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2)
+
+#define S_PTCPORT1 0
+#define M_PTCPORT1 0xffffU
+#define V_PTCPORT1(x) ((x) << S_PTCPORT1)
+#define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1)
+
+#define A_MPS_RX_PTP_UDP 0x1119c
+
+#define S_PUDPORT2 16
+#define M_PUDPORT2 0xffffU
+#define V_PUDPORT2(x) ((x) << S_PUDPORT2)
+#define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2)
+
+#define S_PUDPORT1 0
+#define M_PUDPORT1 0xffffU
+#define V_PUDPORT1(x) ((x) << S_PUDPORT1)
+#define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1)
+
+#define A_MPS_RX_PTP_CTL 0x111a0
+
+#define S_MIN_PTP_SPACE 24
+#define M_MIN_PTP_SPACE 0x7fU
+#define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE)
+#define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE)
+
+#define S_PUDP2EN 20
+#define M_PUDP2EN 0xfU
+#define V_PUDP2EN(x) ((x) << S_PUDP2EN)
+#define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN)
+
+#define S_PUDP1EN 16
+#define M_PUDP1EN 0xfU
+#define V_PUDP1EN(x) ((x) << S_PUDP1EN)
+#define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN)
+
+#define S_PTCP2EN 12
+#define M_PTCP2EN 0xfU
+#define V_PTCP2EN(x) ((x) << S_PTCP2EN)
+#define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN)
+
+#define S_PTCP1EN 8
+#define M_PTCP1EN 0xfU
+#define V_PTCP1EN(x) ((x) << S_PTCP1EN)
+#define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN)
+
+#define S_PETYPE2EN 4
+#define M_PETYPE2EN 0xfU
+#define V_PETYPE2EN(x) ((x) << S_PETYPE2EN)
+#define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN)
+
+#define S_PETYPE1EN 0
+#define M_PETYPE1EN 0xfU
+#define V_PETYPE1EN(x) ((x) << S_PETYPE1EN)
+#define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN)
+
+#define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4
+#define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8
+#define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac
+#define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0
+#define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4
+#define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8
+#define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc
+#define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0
+#define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4
+#define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8
+#define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc
+#define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0
+#define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4
+#define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8
+#define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc
+#define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0
+#define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
+#define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
+#define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
+#define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
+#define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
+#define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
+#define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
+#define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
+#define A_MPS_RX_CGEN 0x11204
+
+#define S_MPS_RX_CGEN_NCSI 12
+#define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI)
+#define F_MPS_RX_CGEN_NCSI V_MPS_RX_CGEN_NCSI(1U)
+
+#define S_MPS_RX_CGEN_OUT 8
+#define M_MPS_RX_CGEN_OUT 0xfU
+#define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT)
+#define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT)
+
+#define S_MPS_RX_CGEN_LPBK_IN 4
+#define M_MPS_RX_CGEN_LPBK_IN 0xfU
+#define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN)
+#define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN)
+
+#define S_MPS_RX_CGEN_MAC_IN 0
+#define M_MPS_RX_CGEN_MAC_IN 0xfU
+#define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN)
+#define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN)
/* registers for module CPL_SWITCH */
#define CPL_SWITCH_BASE_ADDR 0x19040
@@ -16787,6 +25396,10 @@
#define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
#define F_CIM_ENABLE V_CIM_ENABLE(1U)
+#define S_CIM_SPLIT_ENABLE 6
+#define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE)
+#define F_CIM_SPLIT_ENABLE V_CIM_SPLIT_ENABLE(1U)
+
#define A_CPL_SWITCH_TBL_IDX 0x19044
#define S_SWITCH_TBL_IDX 0
@@ -16833,6 +25446,14 @@
#define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
#define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U)
+#define S_PERR_CPL_128TO128_1 7
+#define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
+#define F_PERR_CPL_128TO128_1 V_PERR_CPL_128TO128_1(1U)
+
+#define S_PERR_CPL_128TO128_0 6
+#define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
+#define F_PERR_CPL_128TO128_0 V_PERR_CPL_128TO128_0(1U)
+
#define A_CPL_INTR_CAUSE 0x19054
#define A_CPL_MAP_TBL_IDX 0x19058
@@ -16841,6 +25462,10 @@
#define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX)
#define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX)
+#define S_CIM_SPLIT_OPCODE_PROGRAM 8
+#define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM)
+#define F_CIM_SPLIT_OPCODE_PROGRAM V_CIM_SPLIT_OPCODE_PROGRAM(1U)
+
#define A_CPL_MAP_TBL_DATA 0x1905c
#define S_MAP_TBL_DATA 0
@@ -17194,6 +25819,18 @@
#define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN)
#define F_SLVFIFOPERREN V_SLVFIFOPERREN(1U)
+#define S_MSTTXFIFO 21
+#define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO)
+#define F_MSTTXFIFO V_MSTTXFIFO(1U)
+
+#define S_MSTRXFIFO 19
+#define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO)
+#define F_MSTRXFIFO V_MSTRXFIFO(1U)
+
+#define S_SLVFIFO 18
+#define V_SLVFIFO(x) ((x) << S_SLVFIFO)
+#define F_SLVFIFO V_SLVFIFO(1U)
+
#define A_SMB_PERR_INJ 0x1909c
#define S_MSTTXINJDATAERR 3
@@ -17381,6 +26018,20 @@
#define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG)
#define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG)
+#define A_SMB_CTL_STATUS 0x190e8
+
+#define S_MSTBUSBUSY 2
+#define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY)
+#define F_MSTBUSBUSY V_MSTBUSBUSY(1U)
+
+#define S_SLVBUSBUSY 1
+#define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY)
+#define F_SLVBUSBUSY V_SLVBUSBUSY(1U)
+
+#define S_BUSBUSY 0
+#define V_BUSBUSY(x) ((x) << S_BUSBUSY)
+#define F_BUSBUSY V_BUSBUSY(1U)
+
/* registers for module I2CM */
#define I2CM_BASE_ADDR 0x190f0
@@ -17391,6 +26042,11 @@
#define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
#define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
+#define S_I2C_CLKDIV16B 0
+#define M_I2C_CLKDIV16B 0xffffU
+#define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
+#define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)
+
#define A_I2CM_DATA 0x190f4
#define S_I2C_DATA 0
@@ -17536,6 +26192,46 @@
#define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE)
#define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE)
+#define S_SGE_PART_CGEN 19
+#define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN)
+#define F_SGE_PART_CGEN V_SGE_PART_CGEN(1U)
+
+#define S_PDP_PART_CGEN 18
+#define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN)
+#define F_PDP_PART_CGEN V_PDP_PART_CGEN(1U)
+
+#define S_TP_PART_CGEN 17
+#define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN)
+#define F_TP_PART_CGEN V_TP_PART_CGEN(1U)
+
+#define S_EDC0_PART_CGEN 16
+#define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN)
+#define F_EDC0_PART_CGEN V_EDC0_PART_CGEN(1U)
+
+#define S_EDC1_PART_CGEN 15
+#define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN)
+#define F_EDC1_PART_CGEN V_EDC1_PART_CGEN(1U)
+
+#define S_LE_PART_CGEN 14
+#define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN)
+#define F_LE_PART_CGEN V_LE_PART_CGEN(1U)
+
+#define S_MA_PART_CGEN 13
+#define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN)
+#define F_MA_PART_CGEN V_MA_PART_CGEN(1U)
+
+#define S_MC0_PART_CGEN 12
+#define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN)
+#define F_MC0_PART_CGEN V_MC0_PART_CGEN(1U)
+
+#define S_MC1_PART_CGEN 11
+#define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN)
+#define F_MC1_PART_CGEN V_MC1_PART_CGEN(1U)
+
+#define S_PCIE_PART_CGEN 10
+#define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN)
+#define F_PCIE_PART_CGEN V_PCIE_PART_CGEN(1U)
+
#define A_PMU_SLEEPMODE_WAKEUP 0x19124
#define S_HWWAKEUPEN 5
@@ -17562,6 +26258,10 @@
#define V_WAKEUP(x) ((x) << S_WAKEUP)
#define F_WAKEUP V_WAKEUP(1U)
+#define S_GLOBALDEEPSLEEPEN 6
+#define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN)
+#define F_GLOBALDEEPSLEEPEN V_GLOBALDEEPSLEEPEN(1U)
+
/* registers for module ULP_RX */
#define ULP_RX_BASE_ADDR 0x19150
@@ -17656,78 +26356,86 @@
#define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0)
#define F_ENABLE_AF_0 V_ENABLE_AF_0(1U)
-#define S_ENABLE_PCMDF_1 17
-#define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
-#define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U)
-
-#define S_ENABLE_MPARC_1 16
-#define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
-#define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U)
-
-#define S_ENABLE_MPARF_1 15
-#define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
-#define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U)
-
-#define S_ENABLE_DDPCF_1 14
-#define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
-#define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U)
-
-#define S_ENABLE_TPTCF_1 13
-#define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
-#define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U)
-
-#define S_ENABLE_PCMDF_0 12
-#define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
-#define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U)
-
-#define S_ENABLE_MPARC_0 11
-#define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
-#define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U)
-
-#define S_ENABLE_MPARF_0 10
-#define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
-#define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U)
-
-#define S_ENABLE_DDPCF_0 9
-#define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
-#define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U)
-
-#define S_ENABLE_TPTCF_0 8
-#define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
-#define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U)
-
-#define S_ENABLE_DDPDF_1 7
+#define S_ENABLE_DDPDF_1 17
#define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1)
#define F_ENABLE_DDPDF_1 V_ENABLE_DDPDF_1(1U)
-#define S_ENABLE_DDPMF_1 6
+#define S_ENABLE_DDPMF_1 16
#define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1)
#define F_ENABLE_DDPMF_1 V_ENABLE_DDPMF_1(1U)
-#define S_ENABLE_MEMRF_1 5
+#define S_ENABLE_MEMRF_1 15
#define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1)
#define F_ENABLE_MEMRF_1 V_ENABLE_MEMRF_1(1U)
-#define S_ENABLE_PRSDF_1 4
+#define S_ENABLE_PRSDF_1 14
#define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1)
#define F_ENABLE_PRSDF_1 V_ENABLE_PRSDF_1(1U)
-#define S_ENABLE_DDPDF_0 3
+#define S_ENABLE_DDPDF_0 13
#define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0)
#define F_ENABLE_DDPDF_0 V_ENABLE_DDPDF_0(1U)
-#define S_ENABLE_DDPMF_0 2
+#define S_ENABLE_DDPMF_0 12
#define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0)
#define F_ENABLE_DDPMF_0 V_ENABLE_DDPMF_0(1U)
-#define S_ENABLE_MEMRF_0 1
+#define S_ENABLE_MEMRF_0 11
#define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0)
#define F_ENABLE_MEMRF_0 V_ENABLE_MEMRF_0(1U)
-#define S_ENABLE_PRSDF_0 0
+#define S_ENABLE_PRSDF_0 10
#define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0)
#define F_ENABLE_PRSDF_0 V_ENABLE_PRSDF_0(1U)
+#define S_ENABLE_PCMDF_1 9
+#define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
+#define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U)
+
+#define S_ENABLE_TPTCF_1 8
+#define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
+#define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U)
+
+#define S_ENABLE_DDPCF_1 7
+#define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
+#define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U)
+
+#define S_ENABLE_MPARF_1 6
+#define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
+#define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U)
+
+#define S_ENABLE_MPARC_1 5
+#define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
+#define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U)
+
+#define S_ENABLE_PCMDF_0 4
+#define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
+#define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U)
+
+#define S_ENABLE_TPTCF_0 3
+#define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
+#define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U)
+
+#define S_ENABLE_DDPCF_0 2
+#define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
+#define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U)
+
+#define S_ENABLE_MPARF_0 1
+#define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
+#define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U)
+
+#define S_ENABLE_MPARC_0 0
+#define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
+#define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U)
+
+#define S_SE_CNT_MISMATCH_1 26
+#define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
+#define F_SE_CNT_MISMATCH_1 V_SE_CNT_MISMATCH_1(1U)
+
+#define S_SE_CNT_MISMATCH_0 25
+#define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
+#define F_SE_CNT_MISMATCH_0 V_SE_CNT_MISMATCH_0(1U)
+
#define A_ULP_RX_INT_CAUSE 0x19158
#define S_CAUSE_CTX_1 24
@@ -17758,78 +26466,78 @@
#define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
#define F_CAUSE_AF_0 V_CAUSE_AF_0(1U)
-#define S_CAUSE_PCMDF_1 17
-#define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
-#define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U)
-
-#define S_CAUSE_MPARC_1 16
-#define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
-#define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U)
-
-#define S_CAUSE_MPARF_1 15
-#define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
-#define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U)
-
-#define S_CAUSE_DDPCF_1 14
-#define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
-#define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U)
-
-#define S_CAUSE_TPTCF_1 13
-#define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
-#define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U)
-
-#define S_CAUSE_PCMDF_0 12
-#define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
-#define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U)
-
-#define S_CAUSE_MPARC_0 11
-#define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
-#define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U)
-
-#define S_CAUSE_MPARF_0 10
-#define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
-#define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U)
-
-#define S_CAUSE_DDPCF_0 9
-#define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
-#define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U)
-
-#define S_CAUSE_TPTCF_0 8
-#define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
-#define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U)
-
-#define S_CAUSE_DDPDF_1 7
+#define S_CAUSE_DDPDF_1 17
#define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
#define F_CAUSE_DDPDF_1 V_CAUSE_DDPDF_1(1U)
-#define S_CAUSE_DDPMF_1 6
+#define S_CAUSE_DDPMF_1 16
#define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
#define F_CAUSE_DDPMF_1 V_CAUSE_DDPMF_1(1U)
-#define S_CAUSE_MEMRF_1 5
+#define S_CAUSE_MEMRF_1 15
#define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
#define F_CAUSE_MEMRF_1 V_CAUSE_MEMRF_1(1U)
-#define S_CAUSE_PRSDF_1 4
+#define S_CAUSE_PRSDF_1 14
#define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
#define F_CAUSE_PRSDF_1 V_CAUSE_PRSDF_1(1U)
-#define S_CAUSE_DDPDF_0 3
+#define S_CAUSE_DDPDF_0 13
#define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
#define F_CAUSE_DDPDF_0 V_CAUSE_DDPDF_0(1U)
-#define S_CAUSE_DDPMF_0 2
+#define S_CAUSE_DDPMF_0 12
#define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
#define F_CAUSE_DDPMF_0 V_CAUSE_DDPMF_0(1U)
-#define S_CAUSE_MEMRF_0 1
+#define S_CAUSE_MEMRF_0 11
#define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
#define F_CAUSE_MEMRF_0 V_CAUSE_MEMRF_0(1U)
-#define S_CAUSE_PRSDF_0 0
+#define S_CAUSE_PRSDF_0 10
#define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
#define F_CAUSE_PRSDF_0 V_CAUSE_PRSDF_0(1U)
+#define S_CAUSE_PCMDF_1 9
+#define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
+#define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U)
+
+#define S_CAUSE_TPTCF_1 8
+#define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
+#define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U)
+
+#define S_CAUSE_DDPCF_1 7
+#define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
+#define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U)
+
+#define S_CAUSE_MPARF_1 6
+#define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
+#define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U)
+
+#define S_CAUSE_MPARC_1 5
+#define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
+#define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U)
+
+#define S_CAUSE_PCMDF_0 4
+#define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
+#define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U)
+
+#define S_CAUSE_TPTCF_0 3
+#define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
+#define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U)
+
+#define S_CAUSE_DDPCF_0 2
+#define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
+#define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U)
+
+#define S_CAUSE_MPARF_0 1
+#define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
+#define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U)
+
+#define S_CAUSE_MPARC_0 0
+#define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
+#define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U)
+
#define A_ULP_RX_ISCSI_LLIMIT 0x1915c
#define S_ISCSILLIMIT 6
@@ -17903,6 +26611,115 @@
#define A_ULP_RX_PBL_ULIMIT 0x19190
#define A_ULP_RX_CTX_BASE 0x19194
#define A_ULP_RX_PERR_ENABLE 0x1919c
+
+#define S_PERR_ENABLE_FF 22
+#define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF)
+#define F_PERR_ENABLE_FF V_PERR_ENABLE_FF(1U)
+
+#define S_PERR_ENABLE_APF_1 21
+#define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1)
+#define F_PERR_ENABLE_APF_1 V_PERR_ENABLE_APF_1(1U)
+
+#define S_PERR_ENABLE_APF_0 20
+#define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0)
+#define F_PERR_ENABLE_APF_0 V_PERR_ENABLE_APF_0(1U)
+
+#define S_PERR_ENABLE_AF_1 19
+#define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1)
+#define F_PERR_ENABLE_AF_1 V_PERR_ENABLE_AF_1(1U)
+
+#define S_PERR_ENABLE_AF_0 18
+#define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0)
+#define F_PERR_ENABLE_AF_0 V_PERR_ENABLE_AF_0(1U)
+
+#define S_PERR_ENABLE_DDPDF_1 17
+#define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1)
+#define F_PERR_ENABLE_DDPDF_1 V_PERR_ENABLE_DDPDF_1(1U)
+
+#define S_PERR_ENABLE_DDPMF_1 16
+#define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1)
+#define F_PERR_ENABLE_DDPMF_1 V_PERR_ENABLE_DDPMF_1(1U)
+
+#define S_PERR_ENABLE_MEMRF_1 15
+#define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1)
+#define F_PERR_ENABLE_MEMRF_1 V_PERR_ENABLE_MEMRF_1(1U)
+
+#define S_PERR_ENABLE_PRSDF_1 14
+#define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1)
+#define F_PERR_ENABLE_PRSDF_1 V_PERR_ENABLE_PRSDF_1(1U)
+
+#define S_PERR_ENABLE_DDPDF_0 13
+#define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0)
+#define F_PERR_ENABLE_DDPDF_0 V_PERR_ENABLE_DDPDF_0(1U)
+
+#define S_PERR_ENABLE_DDPMF_0 12
+#define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0)
+#define F_PERR_ENABLE_DDPMF_0 V_PERR_ENABLE_DDPMF_0(1U)
+
+#define S_PERR_ENABLE_MEMRF_0 11
+#define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0)
+#define F_PERR_ENABLE_MEMRF_0 V_PERR_ENABLE_MEMRF_0(1U)
+
+#define S_PERR_ENABLE_PRSDF_0 10
+#define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0)
+#define F_PERR_ENABLE_PRSDF_0 V_PERR_ENABLE_PRSDF_0(1U)
+
+#define S_PERR_ENABLE_PCMDF_1 9
+#define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1)
+#define F_PERR_ENABLE_PCMDF_1 V_PERR_ENABLE_PCMDF_1(1U)
+
+#define S_PERR_ENABLE_TPTCF_1 8
+#define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1)
+#define F_PERR_ENABLE_TPTCF_1 V_PERR_ENABLE_TPTCF_1(1U)
+
+#define S_PERR_ENABLE_DDPCF_1 7
+#define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1)
+#define F_PERR_ENABLE_DDPCF_1 V_PERR_ENABLE_DDPCF_1(1U)
+
+#define S_PERR_ENABLE_MPARF_1 6
+#define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1)
+#define F_PERR_ENABLE_MPARF_1 V_PERR_ENABLE_MPARF_1(1U)
+
+#define S_PERR_ENABLE_MPARC_1 5
+#define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1)
+#define F_PERR_ENABLE_MPARC_1 V_PERR_ENABLE_MPARC_1(1U)
+
+#define S_PERR_ENABLE_PCMDF_0 4
+#define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0)
+#define F_PERR_ENABLE_PCMDF_0 V_PERR_ENABLE_PCMDF_0(1U)
+
+#define S_PERR_ENABLE_TPTCF_0 3
+#define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0)
+#define F_PERR_ENABLE_TPTCF_0 V_PERR_ENABLE_TPTCF_0(1U)
+
+#define S_PERR_ENABLE_DDPCF_0 2
+#define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0)
+#define F_PERR_ENABLE_DDPCF_0 V_PERR_ENABLE_DDPCF_0(1U)
+
+#define S_PERR_ENABLE_MPARF_0 1
+#define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0)
+#define F_PERR_ENABLE_MPARF_0 V_PERR_ENABLE_MPARF_0(1U)
+
+#define S_PERR_ENABLE_MPARC_0 0
+#define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0)
+#define F_PERR_ENABLE_MPARC_0 V_PERR_ENABLE_MPARC_0(1U)
+
+#define S_PERR_SE_CNT_MISMATCH_1 26
+#define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1)
+#define F_PERR_SE_CNT_MISMATCH_1 V_PERR_SE_CNT_MISMATCH_1(1U)
+
+#define S_PERR_SE_CNT_MISMATCH_0 25
+#define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0)
+#define F_PERR_SE_CNT_MISMATCH_0 V_PERR_SE_CNT_MISMATCH_0(1U)
+
+#define S_PERR_RSVD0 24
+#define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0)
+#define F_PERR_RSVD0 V_PERR_RSVD0(1U)
+
+#define S_PERR_RSVD1 23
+#define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1)
+#define F_PERR_RSVD1 V_PERR_RSVD1(1U)
+
#define A_ULP_RX_PERR_INJECT 0x191a0
#define A_ULP_RX_RQUDP_LLIMIT 0x191a4
#define A_ULP_RX_RQUDP_ULIMIT 0x191a8
@@ -18069,6 +26886,262 @@
#define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
#define A_ULP_RX_LA_RESERVED 0x1924c
+#define A_ULP_RX_CQE_GEN_EN 0x19250
+
+#define S_TERMIMATE_MSG 1
+#define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG)
+#define F_TERMIMATE_MSG V_TERMIMATE_MSG(1U)
+
+#define S_TERMINATE_WITH_ERR 0
+#define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR)
+#define F_TERMINATE_WITH_ERR V_TERMINATE_WITH_ERR(1U)
+
+#define A_ULP_RX_ATOMIC_OPCODES 0x19254
+
+#define S_ATOMIC_REQ_QNO 22
+#define M_ATOMIC_REQ_QNO 0x3U
+#define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO)
+#define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO)
+
+#define S_ATOMIC_RSP_QNO 20
+#define M_ATOMIC_RSP_QNO 0x3U
+#define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO)
+#define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO)
+
+#define S_IMMEDIATE_QNO 18
+#define M_IMMEDIATE_QNO 0x3U
+#define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO)
+#define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO)
+
+#define S_IMMEDIATE_WITH_SE_QNO 16
+#define M_IMMEDIATE_WITH_SE_QNO 0x3U
+#define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO)
+#define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO)
+
+#define S_ATOMIC_WR_OPCODE 12
+#define M_ATOMIC_WR_OPCODE 0xfU
+#define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE)
+#define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE)
+
+#define S_ATOMIC_RD_OPCODE 8
+#define M_ATOMIC_RD_OPCODE 0xfU
+#define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE)
+#define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE)
+
+#define S_IMMEDIATE_OPCODE 4
+#define M_IMMEDIATE_OPCODE 0xfU
+#define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE)
+#define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE)
+
+#define S_IMMEDIATE_WITH_SE_OPCODE 0
+#define M_IMMEDIATE_WITH_SE_OPCODE 0xfU
+#define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE)
+#define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE)
+
+#define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258
+
+#define S_EN_ORIG_DATA 0
+#define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA)
+#define F_EN_ORIG_DATA V_EN_ORIG_DATA(1U)
+
+#define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c
+
+#define S_TERMINATE_STATUS_EN 4
+#define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN)
+#define F_TERMINATE_STATUS_EN V_TERMINATE_STATUS_EN(1U)
+
+#define S_MULTIPLE_PREF_ENABLE 3
+#define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE)
+#define F_MULTIPLE_PREF_ENABLE V_MULTIPLE_PREF_ENABLE(1U)
+
+#define S_UMUDP_PBL_PREF_ENABLE 2
+#define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE)
+#define F_UMUDP_PBL_PREF_ENABLE V_UMUDP_PBL_PREF_ENABLE(1U)
+
+#define S_RDMA_PBL_PREF_EN 1
+#define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN)
+#define F_RDMA_PBL_PREF_EN V_RDMA_PBL_PREF_EN(1U)
+
+#define S_SDC_CRC_PROT_EN 0
+#define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN)
+#define F_SDC_CRC_PROT_EN V_SDC_CRC_PROT_EN(1U)
+
+#define A_ULP_RX_CH0_CGEN 0x19260
+
+#define S_BYPASS_CGEN 7
+#define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN)
+#define F_BYPASS_CGEN V_BYPASS_CGEN(1U)
+
+#define S_TDDP_CGEN 6
+#define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN)
+#define F_TDDP_CGEN V_TDDP_CGEN(1U)
+
+#define S_ISCSI_CGEN 5
+#define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN)
+#define F_ISCSI_CGEN V_ISCSI_CGEN(1U)
+
+#define S_RDMA_CGEN 4
+#define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN)
+#define F_RDMA_CGEN V_RDMA_CGEN(1U)
+
+#define S_CHANNEL_CGEN 3
+#define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN)
+#define F_CHANNEL_CGEN V_CHANNEL_CGEN(1U)
+
+#define S_ALL_DATAPATH_CGEN 2
+#define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN)
+#define F_ALL_DATAPATH_CGEN V_ALL_DATAPATH_CGEN(1U)
+
+#define S_T10DIFF_DATAPATH_CGEN 1
+#define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN)
+#define F_T10DIFF_DATAPATH_CGEN V_T10DIFF_DATAPATH_CGEN(1U)
+
+#define S_RDMA_DATAPATH_CGEN 0
+#define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN)
+#define F_RDMA_DATAPATH_CGEN V_RDMA_DATAPATH_CGEN(1U)
+
+#define A_ULP_RX_CH1_CGEN 0x19264
+#define A_ULP_RX_RFE_DISABLE 0x19268
+
+#define S_RQE_LIM_CHECK_RFE_DISABLE 0
+#define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE)
+#define F_RQE_LIM_CHECK_RFE_DISABLE V_RQE_LIM_CHECK_RFE_DISABLE(1U)
+
+#define A_ULP_RX_INT_ENABLE_2 0x1926c
+
+#define S_ULPRX2MA_INTFPERR 8
+#define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
+#define F_ULPRX2MA_INTFPERR V_ULPRX2MA_INTFPERR(1U)
+
+#define S_ALN_SDC_ERR_1 7
+#define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
+#define F_ALN_SDC_ERR_1 V_ALN_SDC_ERR_1(1U)
+
+#define S_ALN_SDC_ERR_0 6
+#define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
+#define F_ALN_SDC_ERR_0 V_ALN_SDC_ERR_0(1U)
+
+#define S_PF_UNTAGGED_TPT_1 5
+#define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
+#define F_PF_UNTAGGED_TPT_1 V_PF_UNTAGGED_TPT_1(1U)
+
+#define S_PF_UNTAGGED_TPT_0 4
+#define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
+#define F_PF_UNTAGGED_TPT_0 V_PF_UNTAGGED_TPT_0(1U)
+
+#define S_PF_PBL_1 3
+#define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
+#define F_PF_PBL_1 V_PF_PBL_1(1U)
+
+#define S_PF_PBL_0 2
+#define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
+#define F_PF_PBL_0 V_PF_PBL_0(1U)
+
+#define S_DDP_HINT_1 1
+#define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
+#define F_DDP_HINT_1 V_DDP_HINT_1(1U)
+
+#define S_DDP_HINT_0 0
+#define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
+#define F_DDP_HINT_0 V_DDP_HINT_0(1U)
+
+#define A_ULP_RX_INT_CAUSE_2 0x19270
+#define A_ULP_RX_PERR_ENABLE_2 0x19274
+
+#define S_ENABLE_ULPRX2MA_INTFPERR 8
+#define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR)
+#define F_ENABLE_ULPRX2MA_INTFPERR V_ENABLE_ULPRX2MA_INTFPERR(1U)
+
+#define S_ENABLE_ALN_SDC_ERR_1 7
+#define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1)
+#define F_ENABLE_ALN_SDC_ERR_1 V_ENABLE_ALN_SDC_ERR_1(1U)
+
+#define S_ENABLE_ALN_SDC_ERR_0 6
+#define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0)
+#define F_ENABLE_ALN_SDC_ERR_0 V_ENABLE_ALN_SDC_ERR_0(1U)
+
+#define S_ENABLE_PF_UNTAGGED_TPT_1 5
+#define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1)
+#define F_ENABLE_PF_UNTAGGED_TPT_1 V_ENABLE_PF_UNTAGGED_TPT_1(1U)
+
+#define S_ENABLE_PF_UNTAGGED_TPT_0 4
+#define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0)
+#define F_ENABLE_PF_UNTAGGED_TPT_0 V_ENABLE_PF_UNTAGGED_TPT_0(1U)
+
+#define S_ENABLE_PF_PBL_1 3
+#define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1)
+#define F_ENABLE_PF_PBL_1 V_ENABLE_PF_PBL_1(1U)
+
+#define S_ENABLE_PF_PBL_0 2
+#define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0)
+#define F_ENABLE_PF_PBL_0 V_ENABLE_PF_PBL_0(1U)
+
+#define S_ENABLE_DDP_HINT_1 1
+#define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1)
+#define F_ENABLE_DDP_HINT_1 V_ENABLE_DDP_HINT_1(1U)
+
+#define S_ENABLE_DDP_HINT_0 0
+#define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0)
+#define F_ENABLE_DDP_HINT_0 V_ENABLE_DDP_HINT_0(1U)
+
+#define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278
+
+#define S_PIO_RQE_PBL_MULTIPLE_CNT 0
+#define M_PIO_RQE_PBL_MULTIPLE_CNT 0xfU
+#define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT)
+#define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT)
+
+#define A_ULP_RX_ATOMIC_LEN 0x1927c
+
+#define S_ATOMIC_RPL_LEN 16
+#define M_ATOMIC_RPL_LEN 0xffU
+#define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN)
+#define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN)
+
+#define S_ATOMIC_REQ_LEN 8
+#define M_ATOMIC_REQ_LEN 0xffU
+#define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN)
+#define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN)
+
+#define S_ATOMIC_IMMEDIATE_LEN 0
+#define M_ATOMIC_IMMEDIATE_LEN 0xffU
+#define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN)
+#define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN)
+
+#define A_ULP_RX_CGEN_GLOBAL 0x19280
+#define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284
+
+#define S_CLEAR_CTX_ERR_CNT1 3
+#define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1)
+#define F_CLEAR_CTX_ERR_CNT1 V_CLEAR_CTX_ERR_CNT1(1U)
+
+#define S_CLEAR_CTX_ERR_CNT0 2
+#define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0)
+#define F_CLEAR_CTX_ERR_CNT0 V_CLEAR_CTX_ERR_CNT0(1U)
+
+#define S_SKIP_MA_REQ_EN1 1
+#define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1)
+#define F_SKIP_MA_REQ_EN1 V_SKIP_MA_REQ_EN1(1U)
+
+#define S_SKIP_MA_REQ_EN0 0
+#define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0)
+#define F_SKIP_MA_REQ_EN0 V_SKIP_MA_REQ_EN0(1U)
+
+#define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
+#define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
+#define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
+
+#define S_RD_OR_TERM_MSN_CHECK_ENABLE 2
+#define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE)
+#define F_RD_OR_TERM_MSN_CHECK_ENABLE V_RD_OR_TERM_MSN_CHECK_ENABLE(1U)
+
+#define S_ATOMIC_OP_MSN_CHECK_ENABLE 1
+#define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE)
+#define F_ATOMIC_OP_MSN_CHECK_ENABLE V_ATOMIC_OP_MSN_CHECK_ENABLE(1U)
+
+#define S_SEND_MSN_CHECK_ENABLE 0
+#define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
+#define F_SEND_MSN_CHECK_ENABLE V_SEND_MSN_CHECK_ENABLE(1U)
/* registers for module SF */
#define SF_BASE_ADDR 0x193f8
@@ -18118,6 +27191,14 @@
#define V_VFID(x) ((x) << S_VFID)
#define G_VFID(x) (((x) >> S_VFID) & M_VFID)
+#define A_PL_VF_REV 0x4
+
+#define S_CHIPID 4
+#define M_CHIPID 0xfU
+#define V_CHIPID(x) ((x) << S_CHIPID)
+#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
+
+#define A_PL_VF_REVISION 0x8
#define A_PL_PF_INT_CAUSE 0x3c0
#define S_PFSW 3
@@ -18262,6 +27343,18 @@
#define V_CIM(x) ((x) << S_CIM)
#define F_CIM V_CIM(1U)
+#define S_MC1 31
+#define V_MC1(x) ((x) << S_MC1)
+#define F_MC1 V_MC1(1U)
+
+#define S_MC0 15
+#define V_MC0(x) ((x) << S_MC0)
+#define F_MC0 V_MC0(1U)
+
+#define S_ANYMAC 9
+#define V_ANYMAC(x) ((x) << S_ANYMAC)
+#define F_ANYMAC V_ANYMAC(1U)
+
#define A_PL_PERR_ENABLE 0x19408
#define A_PL_INT_CAUSE 0x1940c
@@ -18273,6 +27366,22 @@
#define V_SW_CIM(x) ((x) << S_SW_CIM)
#define F_SW_CIM V_SW_CIM(1U)
+#define S_MAC3 12
+#define V_MAC3(x) ((x) << S_MAC3)
+#define F_MAC3 V_MAC3(1U)
+
+#define S_MAC2 11
+#define V_MAC2(x) ((x) << S_MAC2)
+#define F_MAC2 V_MAC2(1U)
+
+#define S_MAC1 10
+#define V_MAC1(x) ((x) << S_MAC1)
+#define F_MAC1 V_MAC1(1U)
+
+#define S_MAC0 9
+#define V_MAC0(x) ((x) << S_MAC0)
+#define F_MAC0 V_MAC0(1U)
+
#define A_PL_INT_ENABLE 0x19410
#define A_PL_INT_MAP0 0x19414
@@ -18298,6 +27407,16 @@
#define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0)
#define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0)
+#define S_MAPMAC1 16
+#define M_MAPMAC1 0x1ffU
+#define V_MAPMAC1(x) ((x) << S_MAPMAC1)
+#define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1)
+
+#define S_MAPMAC0 0
+#define M_MAPMAC0 0x1ffU
+#define V_MAPMAC0(x) ((x) << S_MAPMAC0)
+#define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0)
+
#define A_PL_INT_MAP2 0x1941c
#define S_MAPXGMAC_KR1 16
@@ -18310,6 +27429,16 @@
#define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0)
#define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0)
+#define S_MAPMAC3 16
+#define M_MAPMAC3 0x1ffU
+#define V_MAPMAC3(x) ((x) << S_MAPMAC3)
+#define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3)
+
+#define S_MAPMAC2 0
+#define M_MAPMAC2 0x1ffU
+#define V_MAPMAC2(x) ((x) << S_MAPMAC2)
+#define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2)
+
#define A_PL_INT_MAP3 0x19420
#define S_MAPMI 16
@@ -18352,6 +27481,10 @@
#define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
#define F_PIORSTMODE V_PIORSTMODE(1U)
+#define S_AUTOPCIEPAUSE 4
+#define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
+#define F_AUTOPCIEPAUSE V_AUTOPCIEPAUSE(1U)
+
#define A_PL_PL_PERR_INJECT 0x1942c
#define S_PL_MEMSEL 1
@@ -18384,6 +27517,10 @@
#define V_PERRVFID(x) ((x) << S_PERRVFID)
#define F_PERRVFID V_PERRVFID(1U)
+#define S_PL_BUSPERR 6
+#define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
+#define F_PL_BUSPERR V_PL_BUSPERR(1U)
+
#define A_PL_PL_INT_ENABLE 0x19434
#define A_PL_PL_PERR_ENABLE 0x19438
#define A_PL_REV 0x1943c
@@ -18393,6 +27530,40 @@
#define V_REV(x) ((x) << S_REV)
#define G_REV(x) (((x) >> S_REV) & M_REV)
+#define A_PL_PCIE_LINK 0x19440
+
+#define S_LN0_AESTAT 26
+#define M_LN0_AESTAT 0x7U
+#define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT)
+#define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT)
+
+#define S_LN0_AECMD 23
+#define M_LN0_AECMD 0x7U
+#define V_LN0_AECMD(x) ((x) << S_LN0_AECMD)
+#define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD)
+
+#define S_PCIE_SPEED 8
+#define M_PCIE_SPEED 0x3U
+#define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED)
+#define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED)
+
+#define S_LTSSM 0
+#define M_LTSSM 0x3fU
+#define V_LTSSM(x) ((x) << S_LTSSM)
+#define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM)
+
+#define A_PL_PCIE_CTL_STAT 0x19444
+
+#define S_PCIE_STATUS 16
+#define M_PCIE_STATUS 0xffffU
+#define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS)
+#define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS)
+
+#define S_PCIE_CONTROL 0
+#define M_PCIE_CONTROL 0xffffU
+#define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL)
+#define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL)
+
#define A_PL_SEMAPHORE_CTL 0x1944c
#define S_LOCKSTATUS 16
@@ -18513,6 +27684,10 @@
#define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT)
#define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT)
+#define S_PERRCAPTURE 16
+#define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE)
+#define F_PERRCAPTURE V_PERRCAPTURE(1U)
+
#define A_PL_TIMEOUT_STATUS0 0x194f4
#define S_PL_TOADDR 2
@@ -18549,6 +27724,15 @@
#define V_PL_TORID(x) ((x) << S_PL_TORID)
#define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
+#define S_VALIDPERR 30
+#define V_VALIDPERR(x) ((x) << S_VALIDPERR)
+#define F_VALIDPERR V_VALIDPERR(1U)
+
+#define S_PL_TOVFID 0
+#define M_PL_TOVFID 0xffU
+#define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
+#define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
+
#define A_PL_VFID_MAP 0x19800
#define S_VFID_VLD 7
@@ -18614,6 +27798,58 @@
#define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
#define F_CMDOVERLAPDIS V_CMDOVERLAPDIS(1U)
+#define S_MASKCMDOLAPDIS 26
+#define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
+#define F_MASKCMDOLAPDIS V_MASKCMDOLAPDIS(1U)
+
+#define S_IPV4HASHSIZEEN 25
+#define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
+#define F_IPV4HASHSIZEEN V_IPV4HASHSIZEEN(1U)
+
+#define S_PROTOCOLMASKEN 24
+#define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
+#define F_PROTOCOLMASKEN V_PROTOCOLMASKEN(1U)
+
+#define S_TUPLESIZEEN 23
+#define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
+#define F_TUPLESIZEEN V_TUPLESIZEEN(1U)
+
+#define S_SRVRSRAMEN 22
+#define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
+#define F_SRVRSRAMEN V_SRVRSRAMEN(1U)
+
+#define S_ASBOTHSRCHENPR 19
+#define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
+#define F_ASBOTHSRCHENPR V_ASBOTHSRCHENPR(1U)
+
+#define S_POCLIPTID0 15
+#define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
+#define F_POCLIPTID0 V_POCLIPTID0(1U)
+
+#define S_TCAMARBOFF 14
+#define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
+#define F_TCAMARBOFF V_TCAMARBOFF(1U)
+
+#define S_ACCNTFULLEN 13
+#define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
+#define F_ACCNTFULLEN V_ACCNTFULLEN(1U)
+
+#define S_FILTERRWNOCLIP 12
+#define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
+#define F_FILTERRWNOCLIP V_FILTERRWNOCLIP(1U)
+
+#define S_CRCHASH 10
+#define V_CRCHASH(x) ((x) << S_CRCHASH)
+#define F_CRCHASH V_CRCHASH(1U)
+
+#define S_COMPTID 9
+#define V_COMPTID(x) ((x) << S_COMPTID)
+#define F_COMPTID V_COMPTID(1U)
+
+#define S_SINGLETHREAD 6
+#define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
+#define F_SINGLETHREAD V_SINGLETHREAD(1U)
+
#define A_LE_MISC 0x19c08
#define S_CMPUNVAIL 0
@@ -18621,6 +27857,38 @@
#define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL)
#define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL)
+#define S_SRAMDEEPSLEEP_STAT 11
+#define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT)
+#define F_SRAMDEEPSLEEP_STAT V_SRAMDEEPSLEEP_STAT(1U)
+
+#define S_TCAMDEEPSLEEP1_STAT 10
+#define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT)
+#define F_TCAMDEEPSLEEP1_STAT V_TCAMDEEPSLEEP1_STAT(1U)
+
+#define S_TCAMDEEPSLEEP0_STAT 9
+#define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT)
+#define F_TCAMDEEPSLEEP0_STAT V_TCAMDEEPSLEEP0_STAT(1U)
+
+#define S_SRAMDEEPSLEEP 8
+#define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP)
+#define F_SRAMDEEPSLEEP V_SRAMDEEPSLEEP(1U)
+
+#define S_TCAMDEEPSLEEP1 7
+#define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1)
+#define F_TCAMDEEPSLEEP1 V_TCAMDEEPSLEEP1(1U)
+
+#define S_TCAMDEEPSLEEP0 6
+#define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0)
+#define F_TCAMDEEPSLEEP0 V_TCAMDEEPSLEEP0(1U)
+
+#define S_SRVRAMCLKOFF 5
+#define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF)
+#define F_SRVRAMCLKOFF V_SRVRAMCLKOFF(1U)
+
+#define S_HASHCLKOFF 4
+#define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF)
+#define F_HASHCLKOFF V_HASHCLKOFF(1U)
+
#define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
#define S_RTINDX 7
@@ -18749,6 +28017,30 @@
#define V_SERVERHIT(x) ((x) << S_SERVERHIT)
#define F_SERVERHIT V_SERVERHIT(1U)
+#define S_ACTCNTIPV6TZERO 21
+#define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
+#define F_ACTCNTIPV6TZERO V_ACTCNTIPV6TZERO(1U)
+
+#define S_ACTCNTIPV4TZERO 20
+#define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
+#define F_ACTCNTIPV4TZERO V_ACTCNTIPV4TZERO(1U)
+
+#define S_ACTCNTIPV6ZERO 19
+#define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
+#define F_ACTCNTIPV6ZERO V_ACTCNTIPV6ZERO(1U)
+
+#define S_ACTCNTIPV4ZERO 18
+#define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
+#define F_ACTCNTIPV4ZERO V_ACTCNTIPV4ZERO(1U)
+
+#define S_MARSPPARERR 17
+#define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
+#define F_MARSPPARERR V_MARSPPARERR(1U)
+
+#define S_VFPARERR 14
+#define V_VFPARERR(x) ((x) << S_VFPARERR)
+#define F_VFPARERR V_VFPARERR(1U)
+
#define A_LE_DB_INT_CAUSE 0x19c3c
#define A_LE_DB_INT_TID 0x19c40
@@ -18779,8 +28071,29 @@
#define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD)
#define A_LE_DB_MASK_IPV4 0x19c50
+#define A_LE_T5_DB_MASK_IPV4 0x19c50
+#define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
+#define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
+#define A_LE_ACT_CNT_THRSH 0x19c9c
+
+#define S_ACT_CNT_THRSH 0
+#define M_ACT_CNT_THRSH 0x1fffffU
+#define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
+#define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
+
#define A_LE_DB_MASK_IPV6 0x19ca0
#define A_LE_DB_REQ_RSP_CNT 0x19ce4
+
+#define S_RSPCNTLE 16
+#define M_RSPCNTLE 0xffffU
+#define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
+#define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)
+
+#define S_REQCNTLE 0
+#define M_REQCNTLE 0xffffU
+#define V_REQCNTLE(x) ((x) << S_REQCNTLE)
+#define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
+
#define A_LE_DB_DBGI_CONFIG 0x19cf0
#define S_DBGICMDPERR 31
@@ -18860,6 +28173,22 @@
#define V_TCAM(x) ((x) << S_TCAM)
#define F_TCAM V_TCAM(1U)
+#define S_MARSPPARERRLE 17
+#define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE)
+#define F_MARSPPARERRLE V_MARSPPARERRLE(1U)
+
+#define S_REQQUEUELE 16
+#define V_REQQUEUELE(x) ((x) << S_REQQUEUELE)
+#define F_REQQUEUELE V_REQQUEUELE(1U)
+
+#define S_VFPARERRLE 14
+#define V_VFPARERRLE(x) ((x) << S_VFPARERRLE)
+#define F_VFPARERRLE V_VFPARERRLE(1U)
+
+#define S_TCAMLE 6
+#define V_TCAMLE(x) ((x) << S_TCAMLE)
+#define F_TCAMLE V_TCAMLE(1U)
+
#define A_LE_SPARE 0x19cfc
#define A_LE_DB_DBGI_REQ_DATA 0x19d00
#define A_LE_DB_DBGI_REQ_MASK 0x19d50
@@ -18952,16 +28281,76 @@
#define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
#define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
+#define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
#define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
#define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
+#define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
#define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
+#define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
#define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
+#define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
#define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
+#define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
#define A_LE_DEBUG_LA_CONFIG 0x19f20
#define A_LE_REQ_DEBUG_LA_DATA 0x19f24
#define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
#define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
#define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
+#define A_LE_DEBUG_LA_SELECTOR 0x19f34
+#define A_LE_SRVR_SRAM_INIT 0x19f34
+
+#define S_SRVRSRAMBASE 2
+#define M_SRVRSRAMBASE 0xfffffU
+#define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
+#define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)
+
+#define S_SRVRINITBUSY 1
+#define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
+#define F_SRVRINITBUSY V_SRVRINITBUSY(1U)
+
+#define S_SRVRINIT 0
+#define V_SRVRINIT(x) ((x) << S_SRVRINIT)
+#define F_SRVRINIT V_SRVRINIT(1U)
+
+#define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
+#define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
+
+#define S_RDWR 21
+#define V_RDWR(x) ((x) << S_RDWR)
+#define F_RDWR V_RDWR(1U)
+
+#define S_VFINDEX 14
+#define M_VFINDEX 0x7fU
+#define V_VFINDEX(x) ((x) << S_VFINDEX)
+#define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX)
+
+#define S_SRCHHADDR 7
+#define M_SRCHHADDR 0x7fU
+#define V_SRCHHADDR(x) ((x) << S_SRCHHADDR)
+#define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR)
+
+#define S_SRCHLADDR 0
+#define M_SRCHLADDR 0x7fU
+#define V_SRCHLADDR(x) ((x) << S_SRCHLADDR)
+#define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR)
+
+#define A_LE_MA_DEBUG_LA_DATA 0x19f3c
+#define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
+#define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
+#define A_LE_HASH_DEBUG_LA_DATA 0x19f44
+#define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
+#define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
+#define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
+#define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
+#define A_LE_HASH_COLLISION 0x19fc4
+#define A_LE_GLOBAL_COLLISION 0x19fc8
+#define A_LE_FULL_CNT_COLLISION 0x19fcc
+#define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
+#define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
+#define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
+#define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
+#define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
+#define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
/* registers for module NCSI */
#define NCSI_BASE_ADDR 0x1a000
@@ -19304,12 +28693,26 @@
#define V_DEBUGSEL(x) ((x) << S_DEBUGSEL)
#define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL)
+#define S_TXFIFO_EMPTY 4
+#define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
+#define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U)
+
+#define S_TXFIFO_FULL 3
+#define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
+#define F_TXFIFO_FULL V_TXFIFO_FULL(1U)
+
+#define S_PKG_ID 0
+#define M_PKG_ID 0x7U
+#define V_PKG_ID(x) ((x) << S_PKG_ID)
+#define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID)
+
#define A_NCSI_PERR_INJECT 0x1a0f4
#define S_MCSIMELSEL 1
#define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL)
#define F_MCSIMELSEL V_MCSIMELSEL(1U)
+#define A_NCSI_PERR_ENABLE 0x1a0f8
#define A_NCSI_MACB_NETWORK_CTRL 0x1a100
#define S_TXSNDZEROPAUSE 12
@@ -23323,6 +32726,16 @@
#define V_OBQFULL(x) ((x) << S_OBQFULL)
#define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL)
+#define S_T5_OBQGEN 8
+#define M_T5_OBQGEN 0xffffffU
+#define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN)
+#define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN)
+
+#define S_T5_OBQFULL 0
+#define M_T5_OBQFULL 0xffU
+#define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL)
+#define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL)
+
#define A_UP_IBQ_0_RDADDR 0x10
#define S_QUEID 13
@@ -23541,6 +32954,10 @@
#define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
#define F_UPDBGLAEN V_UPDBGLAEN(1U)
+#define S_UPDBGLABUSY 14
+#define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
+#define F_UPDBGLABUSY V_UPDBGLABUSY(1U)
+
#define A_UP_UP_DBG_LA_DATA 0x144
#define A_UP_PIO_MST_CONFIG 0x148
@@ -23572,6 +32989,15 @@
#define V_UPRID(x) ((x) << S_UPRID)
#define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID)
+#define S_REQVFVLD 27
+#define V_REQVFVLD(x) ((x) << S_REQVFVLD)
+#define F_REQVFVLD V_REQVFVLD(1U)
+
+#define S_T5_UPRID 0
+#define M_T5_UPRID 0xffU
+#define V_T5_UPRID(x) ((x) << S_T5_UPRID)
+#define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID)
+
#define A_UP_UP_SELF_CONTROL 0x14c
#define S_UPSELFRESET 0
@@ -23587,6 +33013,20 @@
#define A_UP_MAILBOX_PF6_CTL 0x1e0
#define A_UP_MAILBOX_PF7_CTL 0x1f0
#define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
+
+#define S_ECO_15444_SGE_DB_BUSY 31
+#define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY)
+#define F_ECO_15444_SGE_DB_BUSY V_ECO_15444_SGE_DB_BUSY(1U)
+
+#define S_ECO_15444_PL_INTF_BUSY 30
+#define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY)
+#define F_ECO_15444_PL_INTF_BUSY V_ECO_15444_PL_INTF_BUSY(1U)
+
+#define S_TSCHCHNLCRDY 0
+#define M_TSCHCHNLCRDY 0x3fffffffU
+#define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY)
+#define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY)
+
#define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
#define S_TSCHWRRLIMIT 16
@@ -23631,6 +33071,90 @@
#define A_UP_UPLADBGPCCHKMASK_2 0x264
#define A_UP_UPLADBGPCCHKDATA_3 0x270
#define A_UP_UPLADBGPCCHKMASK_3 0x274
+#define A_UP_IBQ_0_SHADOW_RDADDR 0x280
+#define A_UP_IBQ_0_SHADOW_WRADDR 0x284
+#define A_UP_IBQ_0_SHADOW_STATUS 0x288
+#define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
+#define A_UP_IBQ_1_SHADOW_RDADDR 0x290
+#define A_UP_IBQ_1_SHADOW_WRADDR 0x294
+#define A_UP_IBQ_1_SHADOW_STATUS 0x298
+#define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
+#define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
+#define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
+#define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
+#define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
+#define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
+#define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
+#define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
+#define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
+#define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
+#define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
+#define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
+#define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
+#define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
+#define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
+#define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
+#define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
+#define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
+#define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
+#define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
+#define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
+#define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
+#define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
+#define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
+#define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
+#define A_UP_OBQ_2_SHADOW_RDADDR 0x300
+#define A_UP_OBQ_2_SHADOW_WRADDR 0x304
+#define A_UP_OBQ_2_SHADOW_STATUS 0x308
+#define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
+#define A_UP_OBQ_3_SHADOW_RDADDR 0x310
+#define A_UP_OBQ_3_SHADOW_WRADDR 0x314
+#define A_UP_OBQ_3_SHADOW_STATUS 0x318
+#define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
+#define A_UP_OBQ_4_SHADOW_RDADDR 0x320
+#define A_UP_OBQ_4_SHADOW_WRADDR 0x324
+#define A_UP_OBQ_4_SHADOW_STATUS 0x328
+#define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
+#define A_UP_OBQ_5_SHADOW_RDADDR 0x330
+#define A_UP_OBQ_5_SHADOW_WRADDR 0x334
+#define A_UP_OBQ_5_SHADOW_STATUS 0x338
+#define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
+#define A_UP_OBQ_6_SHADOW_RDADDR 0x340
+#define A_UP_OBQ_6_SHADOW_WRADDR 0x344
+#define A_UP_OBQ_6_SHADOW_STATUS 0x348
+#define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
+#define A_UP_OBQ_7_SHADOW_RDADDR 0x350
+#define A_UP_OBQ_7_SHADOW_WRADDR 0x354
+#define A_UP_OBQ_7_SHADOW_STATUS 0x358
+#define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
+#define A_UP_IBQ_0_SHADOW_CONFIG 0x360
+#define A_UP_IBQ_0_SHADOW_REALADDR 0x364
+#define A_UP_IBQ_1_SHADOW_CONFIG 0x368
+#define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
+#define A_UP_IBQ_2_SHADOW_CONFIG 0x370
+#define A_UP_IBQ_2_SHADOW_REALADDR 0x374
+#define A_UP_IBQ_3_SHADOW_CONFIG 0x378
+#define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
+#define A_UP_IBQ_4_SHADOW_CONFIG 0x380
+#define A_UP_IBQ_4_SHADOW_REALADDR 0x384
+#define A_UP_IBQ_5_SHADOW_CONFIG 0x388
+#define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
+#define A_UP_OBQ_0_SHADOW_CONFIG 0x390
+#define A_UP_OBQ_0_SHADOW_REALADDR 0x394
+#define A_UP_OBQ_1_SHADOW_CONFIG 0x398
+#define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
+#define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
+#define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
+#define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
+#define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
+#define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
+#define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
+#define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
+#define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
+#define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
+#define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
+#define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
+#define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
/* registers for module CIM_CTL */
#define CIM_CTL_BASE_ADDR 0x0
@@ -23941,6 +33465,17 @@
#define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT)
#define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT)
+#define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920
+
+#define S_TSCCLRATENEG 31
+#define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG)
+#define F_TSCCLRATENEG V_TSCCLRATENEG(1U)
+
+#define S_TSCCLRATEL 0
+#define M_TSCCLRATEL 0xffffffU
+#define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL)
+#define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL)
+
#define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
#define S_TSCCLRMAX 16
@@ -23970,3 +33505,8876 @@
#define M_TSCCLWEIGHT 0xffffU
#define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
#define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)
+
+#define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
+#define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
+#define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
+#define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
+#define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
+#define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
+#define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
+#define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
+#define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
+
+#define S_PF7_OWNER_PL 15
+#define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL)
+#define F_PF7_OWNER_PL V_PF7_OWNER_PL(1U)
+
+#define S_PF6_OWNER_PL 14
+#define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL)
+#define F_PF6_OWNER_PL V_PF6_OWNER_PL(1U)
+
+#define S_PF5_OWNER_PL 13
+#define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL)
+#define F_PF5_OWNER_PL V_PF5_OWNER_PL(1U)
+
+#define S_PF4_OWNER_PL 12
+#define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL)
+#define F_PF4_OWNER_PL V_PF4_OWNER_PL(1U)
+
+#define S_PF3_OWNER_PL 11
+#define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL)
+#define F_PF3_OWNER_PL V_PF3_OWNER_PL(1U)
+
+#define S_PF2_OWNER_PL 10
+#define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL)
+#define F_PF2_OWNER_PL V_PF2_OWNER_PL(1U)
+
+#define S_PF1_OWNER_PL 9
+#define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL)
+#define F_PF1_OWNER_PL V_PF1_OWNER_PL(1U)
+
+#define S_PF0_OWNER_PL 8
+#define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL)
+#define F_PF0_OWNER_PL V_PF0_OWNER_PL(1U)
+
+#define S_PF7_OWNER_UP 7
+#define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP)
+#define F_PF7_OWNER_UP V_PF7_OWNER_UP(1U)
+
+#define S_PF6_OWNER_UP 6
+#define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP)
+#define F_PF6_OWNER_UP V_PF6_OWNER_UP(1U)
+
+#define S_PF5_OWNER_UP 5
+#define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP)
+#define F_PF5_OWNER_UP V_PF5_OWNER_UP(1U)
+
+#define S_PF4_OWNER_UP 4
+#define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP)
+#define F_PF4_OWNER_UP V_PF4_OWNER_UP(1U)
+
+#define S_PF3_OWNER_UP 3
+#define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP)
+#define F_PF3_OWNER_UP V_PF3_OWNER_UP(1U)
+
+#define S_PF2_OWNER_UP 2
+#define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP)
+#define F_PF2_OWNER_UP V_PF2_OWNER_UP(1U)
+
+#define S_PF1_OWNER_UP 1
+#define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP)
+#define F_PF1_OWNER_UP V_PF1_OWNER_UP(1U)
+
+#define S_PF0_OWNER_UP 0
+#define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP)
+#define F_PF0_OWNER_UP V_PF0_OWNER_UP(1U)
+
+#define A_CIM_CTL_PIO_MST_CONFIG 0xda8
+
+#define S_T5_CTLRID 0
+#define M_T5_CTLRID 0xffU
+#define V_T5_CTLRID(x) ((x) << S_T5_CTLRID)
+#define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
+
+/* registers for module MAC */
+#define MAC_BASE_ADDR 0x0
+
+#define A_MAC_PORT_CFG 0x800
+
+#define S_MAC_CLK_SEL 29
+#define M_MAC_CLK_SEL 0x7U
+#define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
+#define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)
+
+#define S_SMUXTXSEL 9
+#define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
+#define F_SMUXTXSEL V_SMUXTXSEL(1U)
+
+#define S_SMUXRXSEL 8
+#define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
+#define F_SMUXRXSEL V_SMUXRXSEL(1U)
+
+#define S_PORTSPEED 4
+#define M_PORTSPEED 0x3U
+#define V_PORTSPEED(x) ((x) << S_PORTSPEED)
+#define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
+
+#define A_MAC_PORT_RESET_CTRL 0x804
+
+#define S_TWGDSK_HSSC16B 31
+#define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
+#define F_TWGDSK_HSSC16B V_TWGDSK_HSSC16B(1U)
+
+#define S_EEE_RESET 30
+#define V_EEE_RESET(x) ((x) << S_EEE_RESET)
+#define F_EEE_RESET V_EEE_RESET(1U)
+
+#define S_PTP_TIMER 29
+#define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
+#define F_PTP_TIMER V_PTP_TIMER(1U)
+
+#define S_MTIPREFRESET 28
+#define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
+#define F_MTIPREFRESET V_MTIPREFRESET(1U)
+
+#define S_MTIPTXFFRESET 27
+#define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET)
+#define F_MTIPTXFFRESET V_MTIPTXFFRESET(1U)
+
+#define S_MTIPRXFFRESET 26
+#define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET)
+#define F_MTIPRXFFRESET V_MTIPRXFFRESET(1U)
+
+#define S_MTIPREGRESET 25
+#define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
+#define F_MTIPREGRESET V_MTIPREGRESET(1U)
+
+#define S_AEC3RESET 23
+#define V_AEC3RESET(x) ((x) << S_AEC3RESET)
+#define F_AEC3RESET V_AEC3RESET(1U)
+
+#define S_AEC2RESET 22
+#define V_AEC2RESET(x) ((x) << S_AEC2RESET)
+#define F_AEC2RESET V_AEC2RESET(1U)
+
+#define S_AEC1RESET 21
+#define V_AEC1RESET(x) ((x) << S_AEC1RESET)
+#define F_AEC1RESET V_AEC1RESET(1U)
+
+#define S_AEC0RESET 20
+#define V_AEC0RESET(x) ((x) << S_AEC0RESET)
+#define F_AEC0RESET V_AEC0RESET(1U)
+
+#define S_AET3RESET 19
+#define V_AET3RESET(x) ((x) << S_AET3RESET)
+#define F_AET3RESET V_AET3RESET(1U)
+
+#define S_AET2RESET 18
+#define V_AET2RESET(x) ((x) << S_AET2RESET)
+#define F_AET2RESET V_AET2RESET(1U)
+
+#define S_AET1RESET 17
+#define V_AET1RESET(x) ((x) << S_AET1RESET)
+#define F_AET1RESET V_AET1RESET(1U)
+
+#define S_AET0RESET 16
+#define V_AET0RESET(x) ((x) << S_AET0RESET)
+#define F_AET0RESET V_AET0RESET(1U)
+
+#define S_TXIF_RESET 12
+#define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
+#define F_TXIF_RESET V_TXIF_RESET(1U)
+
+#define S_RXIF_RESET 11
+#define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
+#define F_RXIF_RESET V_RXIF_RESET(1U)
+
+#define S_MTIPSD3TXRST 9
+#define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
+#define F_MTIPSD3TXRST V_MTIPSD3TXRST(1U)
+
+#define S_MTIPSD2TXRST 8
+#define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
+#define F_MTIPSD2TXRST V_MTIPSD2TXRST(1U)
+
+#define S_MTIPSD1TXRST 7
+#define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
+#define F_MTIPSD1TXRST V_MTIPSD1TXRST(1U)
+
+#define S_MTIPSD0TXRST 6
+#define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
+#define F_MTIPSD0TXRST V_MTIPSD0TXRST(1U)
+
+#define S_MTIPSD3RXRST 5
+#define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
+#define F_MTIPSD3RXRST V_MTIPSD3RXRST(1U)
+
+#define S_MTIPSD2RXRST 4
+#define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
+#define F_MTIPSD2RXRST V_MTIPSD2RXRST(1U)
+
+#define S_MTIPSD1RXRST 3
+#define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
+#define F_MTIPSD1RXRST V_MTIPSD1RXRST(1U)
+
+#define S_MTIPSD0RXRST 1
+#define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
+#define F_MTIPSD0RXRST V_MTIPSD0RXRST(1U)
+
+#define A_MAC_PORT_LED_CFG 0x808
+#define A_MAC_PORT_LED_COUNTHI 0x80c
+#define A_MAC_PORT_LED_COUNTLO 0x810
+#define A_MAC_PORT_CFG3 0x814
+
+#define S_FCSDISCTRL 25
+#define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL)
+#define F_FCSDISCTRL V_FCSDISCTRL(1U)
+
+#define S_SIGDETCTRL 24
+#define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL)
+#define F_SIGDETCTRL V_SIGDETCTRL(1U)
+
+#define S_TX_LANE 23
+#define V_TX_LANE(x) ((x) << S_TX_LANE)
+#define F_TX_LANE V_TX_LANE(1U)
+
+#define S_RX_LANE 22
+#define V_RX_LANE(x) ((x) << S_RX_LANE)
+#define F_RX_LANE V_RX_LANE(1U)
+
+#define S_SE_CLR 21
+#define V_SE_CLR(x) ((x) << S_SE_CLR)
+#define F_SE_CLR V_SE_CLR(1U)
+
+#define S_AN_ENA 17
+#define M_AN_ENA 0xfU
+#define V_AN_ENA(x) ((x) << S_AN_ENA)
+#define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA)
+
+#define S_SD_RX_CLK_ENA 13
+#define M_SD_RX_CLK_ENA 0xfU
+#define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA)
+#define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA)
+
+#define S_SD_TX_CLK_ENA 9
+#define M_SD_TX_CLK_ENA 0xfU
+#define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA)
+#define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA)
+
+#define S_SGMIISEL 8
+#define V_SGMIISEL(x) ((x) << S_SGMIISEL)
+#define F_SGMIISEL V_SGMIISEL(1U)
+
+#define S_HSSPLLSEL 4
+#define M_HSSPLLSEL 0xfU
+#define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL)
+#define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL)
+
+#define S_HSSC16C20SEL 0
+#define M_HSSC16C20SEL 0xfU
+#define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL)
+#define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL)
+
+#define A_MAC_PORT_CFG2 0x818
+
+#define S_T5_AEC_PMA_TX_READY 4
+#define M_T5_AEC_PMA_TX_READY 0xfU
+#define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY)
+#define G_T5_AEC_PMA_TX_READY(x) (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY)
+
+#define S_T5_AEC_PMA_RX_READY 0
+#define M_T5_AEC_PMA_RX_READY 0xfU
+#define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY)
+#define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY)
+
+#define A_MAC_PORT_PKT_COUNT 0x81c
+#define A_MAC_PORT_CFG4 0x820
+
+#define S_AEC3_RX_WIDTH 14
+#define M_AEC3_RX_WIDTH 0x3U
+#define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH)
+#define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH)
+
+#define S_AEC2_RX_WIDTH 12
+#define M_AEC2_RX_WIDTH 0x3U
+#define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH)
+#define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH)
+
+#define S_AEC1_RX_WIDTH 10
+#define M_AEC1_RX_WIDTH 0x3U
+#define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH)
+#define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH)
+
+#define S_AEC0_RX_WIDTH 8
+#define M_AEC0_RX_WIDTH 0x3U
+#define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH)
+#define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH)
+
+#define S_AEC3_TX_WIDTH 6
+#define M_AEC3_TX_WIDTH 0x3U
+#define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH)
+#define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH)
+
+#define S_AEC2_TX_WIDTH 4
+#define M_AEC2_TX_WIDTH 0x3U
+#define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH)
+#define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH)
+
+#define S_AEC1_TX_WIDTH 2
+#define M_AEC1_TX_WIDTH 0x3U
+#define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH)
+#define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH)
+
+#define S_AEC0_TX_WIDTH 0
+#define M_AEC0_TX_WIDTH 0x3U
+#define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH)
+#define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH)
+
+#define A_MAC_PORT_MAGIC_MACID_LO 0x824
+#define A_MAC_PORT_MAGIC_MACID_HI 0x828
+#define A_MAC_PORT_LINK_STATUS 0x834
+
+#define S_AN_DONE 6
+#define V_AN_DONE(x) ((x) << S_AN_DONE)
+#define F_AN_DONE V_AN_DONE(1U)
+
+#define S_ALIGN_DONE 5
+#define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE)
+#define F_ALIGN_DONE V_ALIGN_DONE(1U)
+
+#define S_BLOCK_LOCK 4
+#define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK)
+#define F_BLOCK_LOCK V_BLOCK_LOCK(1U)
+
+#define A_MAC_PORT_EPIO_DATA0 0x8c0
+#define A_MAC_PORT_EPIO_DATA1 0x8c4
+#define A_MAC_PORT_EPIO_DATA2 0x8c8
+#define A_MAC_PORT_EPIO_DATA3 0x8cc
+#define A_MAC_PORT_EPIO_OP 0x8d0
+#define A_MAC_PORT_WOL_STATUS 0x8d4
+#define A_MAC_PORT_INT_EN 0x8d8
+
+#define S_TX_TS_AVAIL 29
+#define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
+#define F_TX_TS_AVAIL V_TX_TS_AVAIL(1U)
+
+#define S_AN_PAGE_RCVD 2
+#define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
+#define F_AN_PAGE_RCVD V_AN_PAGE_RCVD(1U)
+
+#define A_MAC_PORT_INT_CAUSE 0x8dc
+#define A_MAC_PORT_PERR_INT_EN 0x8e0
+
+#define S_PERR_PKT_RAM 24
+#define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
+#define F_PERR_PKT_RAM V_PERR_PKT_RAM(1U)
+
+#define S_PERR_MASK_RAM 23
+#define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
+#define F_PERR_MASK_RAM V_PERR_MASK_RAM(1U)
+
+#define S_PERR_CRC_RAM 22
+#define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
+#define F_PERR_CRC_RAM V_PERR_CRC_RAM(1U)
+
+#define S_RX_DFF_SEG0 21
+#define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
+#define F_RX_DFF_SEG0 V_RX_DFF_SEG0(1U)
+
+#define S_RX_SFF_SEG0 20
+#define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
+#define F_RX_SFF_SEG0 V_RX_SFF_SEG0(1U)
+
+#define S_RX_DFF_MAC10 19
+#define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
+#define F_RX_DFF_MAC10 V_RX_DFF_MAC10(1U)
+
+#define S_RX_SFF_MAC10 18
+#define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
+#define F_RX_SFF_MAC10 V_RX_SFF_MAC10(1U)
+
+#define S_TX_DFF_SEG0 17
+#define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
+#define F_TX_DFF_SEG0 V_TX_DFF_SEG0(1U)
+
+#define S_TX_SFF_SEG0 16
+#define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
+#define F_TX_SFF_SEG0 V_TX_SFF_SEG0(1U)
+
+#define S_TX_DFF_MAC10 15
+#define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
+#define F_TX_DFF_MAC10 V_TX_DFF_MAC10(1U)
+
+#define S_TX_SFF_MAC10 14
+#define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
+#define F_TX_SFF_MAC10 V_TX_SFF_MAC10(1U)
+
+#define S_RX_STATS 13
+#define V_RX_STATS(x) ((x) << S_RX_STATS)
+#define F_RX_STATS V_RX_STATS(1U)
+
+#define S_TX_STATS 12
+#define V_TX_STATS(x) ((x) << S_TX_STATS)
+#define F_TX_STATS V_TX_STATS(1U)
+
+#define S_PERR3_RX_MIX 11
+#define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
+#define F_PERR3_RX_MIX V_PERR3_RX_MIX(1U)
+
+#define S_PERR3_RX_SD 10
+#define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
+#define F_PERR3_RX_SD V_PERR3_RX_SD(1U)
+
+#define S_PERR3_TX 9
+#define V_PERR3_TX(x) ((x) << S_PERR3_TX)
+#define F_PERR3_TX V_PERR3_TX(1U)
+
+#define S_PERR2_RX_MIX 8
+#define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
+#define F_PERR2_RX_MIX V_PERR2_RX_MIX(1U)
+
+#define S_PERR2_RX_SD 7
+#define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
+#define F_PERR2_RX_SD V_PERR2_RX_SD(1U)
+
+#define S_PERR2_TX 6
+#define V_PERR2_TX(x) ((x) << S_PERR2_TX)
+#define F_PERR2_TX V_PERR2_TX(1U)
+
+#define S_PERR1_RX_MIX 5
+#define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
+#define F_PERR1_RX_MIX V_PERR1_RX_MIX(1U)
+
+#define S_PERR1_RX_SD 4
+#define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
+#define F_PERR1_RX_SD V_PERR1_RX_SD(1U)
+
+#define S_PERR1_TX 3
+#define V_PERR1_TX(x) ((x) << S_PERR1_TX)
+#define F_PERR1_TX V_PERR1_TX(1U)
+
+#define S_PERR0_RX_MIX 2
+#define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
+#define F_PERR0_RX_MIX V_PERR0_RX_MIX(1U)
+
+#define S_PERR0_RX_SD 1
+#define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
+#define F_PERR0_RX_SD V_PERR0_RX_SD(1U)
+
+#define S_PERR0_TX 0
+#define V_PERR0_TX(x) ((x) << S_PERR0_TX)
+#define F_PERR0_TX V_PERR0_TX(1U)
+
+#define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
+#define A_MAC_PORT_PERR_ENABLE 0x8e8
+#define A_MAC_PORT_PERR_INJECT 0x8ec
+#define A_MAC_PORT_HSS_CFG0 0x8f0
+
+#define S_HSSREFCLKVALIDA 20
+#define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA)
+#define F_HSSREFCLKVALIDA V_HSSREFCLKVALIDA(1U)
+
+#define S_HSSREFCLKVALIDB 19
+#define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB)
+#define F_HSSREFCLKVALIDB V_HSSREFCLKVALIDB(1U)
+
+#define S_HSSRESYNCA 18
+#define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA)
+#define F_HSSRESYNCA V_HSSRESYNCA(1U)
+
+#define S_HSSRESYNCB 16
+#define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB)
+#define F_HSSRESYNCB V_HSSRESYNCB(1U)
+
+#define S_HSSRECCALA 15
+#define V_HSSRECCALA(x) ((x) << S_HSSRECCALA)
+#define F_HSSRECCALA V_HSSRECCALA(1U)
+
+#define S_HSSRECCALB 13
+#define V_HSSRECCALB(x) ((x) << S_HSSRECCALB)
+#define F_HSSRECCALB V_HSSRECCALB(1U)
+
+#define S_HSSPLLBYPA 12
+#define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA)
+#define F_HSSPLLBYPA V_HSSPLLBYPA(1U)
+
+#define S_HSSPLLBYPB 11
+#define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB)
+#define F_HSSPLLBYPB V_HSSPLLBYPB(1U)
+
+#define S_HSSPDWNPLLA 10
+#define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA)
+#define F_HSSPDWNPLLA V_HSSPDWNPLLA(1U)
+
+#define S_HSSPDWNPLLB 9
+#define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB)
+#define F_HSSPDWNPLLB V_HSSPDWNPLLB(1U)
+
+#define S_HSSVCOSELA 8
+#define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA)
+#define F_HSSVCOSELA V_HSSVCOSELA(1U)
+
+#define S_HSSVCOSELB 7
+#define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB)
+#define F_HSSVCOSELB V_HSSVCOSELB(1U)
+
+#define S_HSSCALCOMP 6
+#define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP)
+#define F_HSSCALCOMP V_HSSCALCOMP(1U)
+
+#define S_HSSCALENAB 5
+#define V_HSSCALENAB(x) ((x) << S_HSSCALENAB)
+#define F_HSSCALENAB V_HSSCALENAB(1U)
+
+#define A_MAC_PORT_HSS_CFG1 0x8f4
+
+#define S_RXACONFIGSEL 30
+#define M_RXACONFIGSEL 0x3U
+#define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL)
+#define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL)
+
+#define S_RXAQUIET 29
+#define V_RXAQUIET(x) ((x) << S_RXAQUIET)
+#define F_RXAQUIET V_RXAQUIET(1U)
+
+#define S_RXAREFRESH 28
+#define V_RXAREFRESH(x) ((x) << S_RXAREFRESH)
+#define F_RXAREFRESH V_RXAREFRESH(1U)
+
+#define S_RXBCONFIGSEL 26
+#define M_RXBCONFIGSEL 0x3U
+#define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL)
+#define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL)
+
+#define S_RXBQUIET 25
+#define V_RXBQUIET(x) ((x) << S_RXBQUIET)
+#define F_RXBQUIET V_RXBQUIET(1U)
+
+#define S_RXBREFRESH 24
+#define V_RXBREFRESH(x) ((x) << S_RXBREFRESH)
+#define F_RXBREFRESH V_RXBREFRESH(1U)
+
+#define S_RXCCONFIGSEL 22
+#define M_RXCCONFIGSEL 0x3U
+#define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL)
+#define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL)
+
+#define S_RXCQUIET 21
+#define V_RXCQUIET(x) ((x) << S_RXCQUIET)
+#define F_RXCQUIET V_RXCQUIET(1U)
+
+#define S_RXCREFRESH 20
+#define V_RXCREFRESH(x) ((x) << S_RXCREFRESH)
+#define F_RXCREFRESH V_RXCREFRESH(1U)
+
+#define S_RXDCONFIGSEL 18
+#define M_RXDCONFIGSEL 0x3U
+#define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL)
+#define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL)
+
+#define S_RXDQUIET 17
+#define V_RXDQUIET(x) ((x) << S_RXDQUIET)
+#define F_RXDQUIET V_RXDQUIET(1U)
+
+#define S_RXDREFRESH 16
+#define V_RXDREFRESH(x) ((x) << S_RXDREFRESH)
+#define F_RXDREFRESH V_RXDREFRESH(1U)
+
+#define S_TXACONFIGSEL 14
+#define M_TXACONFIGSEL 0x3U
+#define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL)
+#define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL)
+
+#define S_TXAQUIET 13
+#define V_TXAQUIET(x) ((x) << S_TXAQUIET)
+#define F_TXAQUIET V_TXAQUIET(1U)
+
+#define S_TXAREFRESH 12
+#define V_TXAREFRESH(x) ((x) << S_TXAREFRESH)
+#define F_TXAREFRESH V_TXAREFRESH(1U)
+
+#define S_TXBCONFIGSEL 10
+#define M_TXBCONFIGSEL 0x3U
+#define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL)
+#define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL)
+
+#define S_TXBQUIET 9
+#define V_TXBQUIET(x) ((x) << S_TXBQUIET)
+#define F_TXBQUIET V_TXBQUIET(1U)
+
+#define S_TXBREFRESH 8
+#define V_TXBREFRESH(x) ((x) << S_TXBREFRESH)
+#define F_TXBREFRESH V_TXBREFRESH(1U)
+
+#define S_TXCCONFIGSEL 6
+#define M_TXCCONFIGSEL 0x3U
+#define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL)
+#define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL)
+
+#define S_TXCQUIET 5
+#define V_TXCQUIET(x) ((x) << S_TXCQUIET)
+#define F_TXCQUIET V_TXCQUIET(1U)
+
+#define S_TXCREFRESH 4
+#define V_TXCREFRESH(x) ((x) << S_TXCREFRESH)
+#define F_TXCREFRESH V_TXCREFRESH(1U)
+
+#define S_TXDCONFIGSEL 2
+#define M_TXDCONFIGSEL 0x3U
+#define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL)
+#define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL)
+
+#define S_TXDQUIET 1
+#define V_TXDQUIET(x) ((x) << S_TXDQUIET)
+#define F_TXDQUIET V_TXDQUIET(1U)
+
+#define S_TXDREFRESH 0
+#define V_TXDREFRESH(x) ((x) << S_TXDREFRESH)
+#define F_TXDREFRESH V_TXDREFRESH(1U)
+
+#define A_MAC_PORT_HSS_CFG2 0x8f8
+
+#define S_RXAASSTCLK 31
+#define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK)
+#define F_RXAASSTCLK V_RXAASSTCLK(1U)
+
+#define S_T5RXAPRBSRST 30
+#define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST)
+#define F_T5RXAPRBSRST V_T5RXAPRBSRST(1U)
+
+#define S_RXBASSTCLK 29
+#define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK)
+#define F_RXBASSTCLK V_RXBASSTCLK(1U)
+
+#define S_T5RXBPRBSRST 28
+#define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST)
+#define F_T5RXBPRBSRST V_T5RXBPRBSRST(1U)
+
+#define S_RXCASSTCLK 27
+#define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK)
+#define F_RXCASSTCLK V_RXCASSTCLK(1U)
+
+#define S_T5RXCPRBSRST 26
+#define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST)
+#define F_T5RXCPRBSRST V_T5RXCPRBSRST(1U)
+
+#define S_RXDASSTCLK 25
+#define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK)
+#define F_RXDASSTCLK V_RXDASSTCLK(1U)
+
+#define S_T5RXDPRBSRST 24
+#define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST)
+#define F_T5RXDPRBSRST V_T5RXDPRBSRST(1U)
+
+#define A_MAC_PORT_HSS_CFG3 0x8fc
+
+#define S_HSSCALSSTN 25
+#define M_HSSCALSSTN 0x7U
+#define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN)
+#define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN)
+
+#define S_HSSCALSSTP 22
+#define M_HSSCALSSTP 0x7U
+#define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP)
+#define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP)
+
+#define S_HSSVBOOSTDIVB 19
+#define M_HSSVBOOSTDIVB 0x7U
+#define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB)
+#define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB)
+
+#define S_HSSVBOOSTDIVA 16
+#define M_HSSVBOOSTDIVA 0x7U
+#define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA)
+#define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA)
+
+#define S_HSSPLLCONFIGB 8
+#define M_HSSPLLCONFIGB 0xffU
+#define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB)
+#define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB)
+
+#define S_HSSPLLCONFIGA 0
+#define M_HSSPLLCONFIGA 0xffU
+#define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA)
+#define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA)
+
+#define A_MAC_PORT_HSS_CFG4 0x900
+
+#define S_HSSDIVSELA 9
+#define M_HSSDIVSELA 0x1ffU
+#define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA)
+#define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA)
+
+#define S_HSSDIVSELB 0
+#define M_HSSDIVSELB 0x1ffU
+#define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB)
+#define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB)
+
+#define A_MAC_PORT_HSS_STATUS 0x904
+
+#define S_HSSPLLLOCKB 3
+#define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB)
+#define F_HSSPLLLOCKB V_HSSPLLLOCKB(1U)
+
+#define S_HSSPLLLOCKA 2
+#define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA)
+#define F_HSSPLLLOCKA V_HSSPLLLOCKA(1U)
+
+#define S_HSSPRTREADYB 1
+#define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB)
+#define F_HSSPRTREADYB V_HSSPRTREADYB(1U)
+
+#define S_HSSPRTREADYA 0
+#define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA)
+#define F_HSSPRTREADYA V_HSSPRTREADYA(1U)
+
+#define A_MAC_PORT_HSS_EEE_STATUS 0x908
+
+#define S_RXAQUIET_STATUS 15
+#define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS)
+#define F_RXAQUIET_STATUS V_RXAQUIET_STATUS(1U)
+
+#define S_RXAREFRESH_STATUS 14
+#define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS)
+#define F_RXAREFRESH_STATUS V_RXAREFRESH_STATUS(1U)
+
+#define S_RXBQUIET_STATUS 13
+#define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS)
+#define F_RXBQUIET_STATUS V_RXBQUIET_STATUS(1U)
+
+#define S_RXBREFRESH_STATUS 12
+#define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS)
+#define F_RXBREFRESH_STATUS V_RXBREFRESH_STATUS(1U)
+
+#define S_RXCQUIET_STATUS 11
+#define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS)
+#define F_RXCQUIET_STATUS V_RXCQUIET_STATUS(1U)
+
+#define S_RXCREFRESH_STATUS 10
+#define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS)
+#define F_RXCREFRESH_STATUS V_RXCREFRESH_STATUS(1U)
+
+#define S_RXDQUIET_STATUS 9
+#define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS)
+#define F_RXDQUIET_STATUS V_RXDQUIET_STATUS(1U)
+
+#define S_RXDREFRESH_STATUS 8
+#define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS)
+#define F_RXDREFRESH_STATUS V_RXDREFRESH_STATUS(1U)
+
+#define S_TXAQUIET_STATUS 7
+#define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS)
+#define F_TXAQUIET_STATUS V_TXAQUIET_STATUS(1U)
+
+#define S_TXAREFRESH_STATUS 6
+#define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS)
+#define F_TXAREFRESH_STATUS V_TXAREFRESH_STATUS(1U)
+
+#define S_TXBQUIET_STATUS 5
+#define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS)
+#define F_TXBQUIET_STATUS V_TXBQUIET_STATUS(1U)
+
+#define S_TXBREFRESH_STATUS 4
+#define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS)
+#define F_TXBREFRESH_STATUS V_TXBREFRESH_STATUS(1U)
+
+#define S_TXCQUIET_STATUS 3
+#define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS)
+#define F_TXCQUIET_STATUS V_TXCQUIET_STATUS(1U)
+
+#define S_TXCREFRESH_STATUS 2
+#define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS)
+#define F_TXCREFRESH_STATUS V_TXCREFRESH_STATUS(1U)
+
+#define S_TXDQUIET_STATUS 1
+#define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS)
+#define F_TXDQUIET_STATUS V_TXDQUIET_STATUS(1U)
+
+#define S_TXDREFRESH_STATUS 0
+#define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS)
+#define F_TXDREFRESH_STATUS V_TXDREFRESH_STATUS(1U)
+
+#define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c
+#define A_MAC_PORT_HSS_PL_CTL 0x910
+
+#define S_TOV 16
+#define M_TOV 0xffU
+#define V_TOV(x) ((x) << S_TOV)
+#define G_TOV(x) (((x) >> S_TOV) & M_TOV)
+
+#define S_TSU 8
+#define M_TSU 0xffU
+#define V_TSU(x) ((x) << S_TSU)
+#define G_TSU(x) (((x) >> S_TSU) & M_TSU)
+
+#define S_IPW 0
+#define M_IPW 0xffU
+#define V_IPW(x) ((x) << S_IPW)
+#define G_IPW(x) (((x) >> S_IPW) & M_IPW)
+
+#define A_MAC_PORT_RUNT_FRAME 0x914
+
+#define S_RUNTCLEAR 16
+#define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR)
+#define F_RUNTCLEAR V_RUNTCLEAR(1U)
+
+#define S_RUNT 0
+#define M_RUNT 0xffffU
+#define V_RUNT(x) ((x) << S_RUNT)
+#define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT)
+
+#define A_MAC_PORT_EEE_STATUS 0x918
+
+#define S_EEE_TX_10G_STATE 10
+#define M_EEE_TX_10G_STATE 0x3U
+#define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE)
+#define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE)
+
+#define S_EEE_RX_10G_STATE 8
+#define M_EEE_RX_10G_STATE 0x3U
+#define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE)
+#define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE)
+
+#define S_EEE_TX_1G_STATE 6
+#define M_EEE_TX_1G_STATE 0x3U
+#define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE)
+#define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE)
+
+#define S_EEE_RX_1G_STATE 4
+#define M_EEE_RX_1G_STATE 0x3U
+#define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE)
+#define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE)
+
+#define S_PMA_RX_REFRESH 3
+#define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH)
+#define F_PMA_RX_REFRESH V_PMA_RX_REFRESH(1U)
+
+#define S_PMA_RX_QUIET 2
+#define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET)
+#define F_PMA_RX_QUIET V_PMA_RX_QUIET(1U)
+
+#define S_PMA_TX_REFRESH 1
+#define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH)
+#define F_PMA_TX_REFRESH V_PMA_TX_REFRESH(1U)
+
+#define S_PMA_TX_QUIET 0
+#define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET)
+#define F_PMA_TX_QUIET V_PMA_TX_QUIET(1U)
+
+#define A_MAC_PORT_CGEN 0x91c
+
+#define S_CGEN 8
+#define V_CGEN(x) ((x) << S_CGEN)
+#define F_CGEN V_CGEN(1U)
+
+#define S_SD7_CGEN 7
+#define V_SD7_CGEN(x) ((x) << S_SD7_CGEN)
+#define F_SD7_CGEN V_SD7_CGEN(1U)
+
+#define S_SD6_CGEN 6
+#define V_SD6_CGEN(x) ((x) << S_SD6_CGEN)
+#define F_SD6_CGEN V_SD6_CGEN(1U)
+
+#define S_SD5_CGEN 5
+#define V_SD5_CGEN(x) ((x) << S_SD5_CGEN)
+#define F_SD5_CGEN V_SD5_CGEN(1U)
+
+#define S_SD4_CGEN 4
+#define V_SD4_CGEN(x) ((x) << S_SD4_CGEN)
+#define F_SD4_CGEN V_SD4_CGEN(1U)
+
+#define S_SD3_CGEN 3
+#define V_SD3_CGEN(x) ((x) << S_SD3_CGEN)
+#define F_SD3_CGEN V_SD3_CGEN(1U)
+
+#define S_SD2_CGEN 2
+#define V_SD2_CGEN(x) ((x) << S_SD2_CGEN)
+#define F_SD2_CGEN V_SD2_CGEN(1U)
+
+#define S_SD1_CGEN 1
+#define V_SD1_CGEN(x) ((x) << S_SD1_CGEN)
+#define F_SD1_CGEN V_SD1_CGEN(1U)
+
+#define S_SD0_CGEN 0
+#define V_SD0_CGEN(x) ((x) << S_SD0_CGEN)
+#define F_SD0_CGEN V_SD0_CGEN(1U)
+
+#define A_MAC_PORT_CGEN_MTIP 0x920
+
+#define S_MACSEG5_CGEN 11
+#define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN)
+#define F_MACSEG5_CGEN V_MACSEG5_CGEN(1U)
+
+#define S_PCSSEG5_CGEN 10
+#define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN)
+#define F_PCSSEG5_CGEN V_PCSSEG5_CGEN(1U)
+
+#define S_MACSEG4_CGEN 9
+#define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN)
+#define F_MACSEG4_CGEN V_MACSEG4_CGEN(1U)
+
+#define S_PCSSEG4_CGEN 8
+#define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN)
+#define F_PCSSEG4_CGEN V_PCSSEG4_CGEN(1U)
+
+#define S_MACSEG3_CGEN 7
+#define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN)
+#define F_MACSEG3_CGEN V_MACSEG3_CGEN(1U)
+
+#define S_PCSSEG3_CGEN 6
+#define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN)
+#define F_PCSSEG3_CGEN V_PCSSEG3_CGEN(1U)
+
+#define S_MACSEG2_CGEN 5
+#define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN)
+#define F_MACSEG2_CGEN V_MACSEG2_CGEN(1U)
+
+#define S_PCSSEG2_CGEN 4
+#define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN)
+#define F_PCSSEG2_CGEN V_PCSSEG2_CGEN(1U)
+
+#define S_MACSEG1_CGEN 3
+#define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN)
+#define F_MACSEG1_CGEN V_MACSEG1_CGEN(1U)
+
+#define S_PCSSEG1_CGEN 2
+#define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN)
+#define F_PCSSEG1_CGEN V_PCSSEG1_CGEN(1U)
+
+#define S_MACSEG0_CGEN 1
+#define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN)
+#define F_MACSEG0_CGEN V_MACSEG0_CGEN(1U)
+
+#define S_PCSSEG0_CGEN 0
+#define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN)
+#define F_PCSSEG0_CGEN V_PCSSEG0_CGEN(1U)
+
+#define A_MAC_PORT_TX_TS_ID 0x924
+
+#define S_TS_ID 0
+#define M_TS_ID 0x7U
+#define V_TS_ID(x) ((x) << S_TS_ID)
+#define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID)
+
+#define A_MAC_PORT_TX_TS_VAL_LO 0x928
+#define A_MAC_PORT_TX_TS_VAL_HI 0x92c
+#define A_MAC_PORT_EEE_CTL 0x930
+
+#define S_EEE_CTRL 2
+#define M_EEE_CTRL 0x3fffffffU
+#define V_EEE_CTRL(x) ((x) << S_EEE_CTRL)
+#define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL)
+
+#define S_TICK_START 1
+#define V_TICK_START(x) ((x) << S_TICK_START)
+#define F_TICK_START V_TICK_START(1U)
+
+#define S_EEE_ENABLE 0
+#define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE)
+#define F_EEE_ENABLE V_EEE_ENABLE(1U)
+
+#define A_MAC_PORT_EEE_TX_CTL 0x934
+
+#define S_WAKE_TIMER 16
+#define M_WAKE_TIMER 0xffffU
+#define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER)
+#define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER)
+
+#define S_HSS_TIMER 5
+#define M_HSS_TIMER 0xfU
+#define V_HSS_TIMER(x) ((x) << S_HSS_TIMER)
+#define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER)
+
+#define S_HSS_CTL 4
+#define V_HSS_CTL(x) ((x) << S_HSS_CTL)
+#define F_HSS_CTL V_HSS_CTL(1U)
+
+#define S_LPI_ACTIVE 3
+#define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE)
+#define F_LPI_ACTIVE V_LPI_ACTIVE(1U)
+
+#define S_LPI_TXHOLD 2
+#define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD)
+#define F_LPI_TXHOLD V_LPI_TXHOLD(1U)
+
+#define S_LPI_REQ 1
+#define V_LPI_REQ(x) ((x) << S_LPI_REQ)
+#define F_LPI_REQ V_LPI_REQ(1U)
+
+#define S_EEE_TX_RESET 0
+#define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET)
+#define F_EEE_TX_RESET V_EEE_TX_RESET(1U)
+
+#define A_MAC_PORT_EEE_RX_CTL 0x938
+
+#define S_LPI_IND 1
+#define V_LPI_IND(x) ((x) << S_LPI_IND)
+#define F_LPI_IND V_LPI_IND(1U)
+
+#define S_EEE_RX_RESET 0
+#define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET)
+#define F_EEE_RX_RESET V_EEE_RX_RESET(1U)
+
+#define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c
+#define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940
+#define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944
+#define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948
+#define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c
+#define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950
+#define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954
+#define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958
+#define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c
+#define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960
+#define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964
+#define A_MAC_PORT_EEE_WF_COUNT 0x968
+
+#define S_WAKE_CNT_CLR 16
+#define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR)
+#define F_WAKE_CNT_CLR V_WAKE_CNT_CLR(1U)
+
+#define S_WAKE_CNT 0
+#define M_WAKE_CNT 0xffffU
+#define V_WAKE_CNT(x) ((x) << S_WAKE_CNT)
+#define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT)
+
+#define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c
+#define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970
+#define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974
+#define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978
+#define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c
+#define A_MAC_PORT_PTP_TIMER_WR_HI 0x980
+#define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984
+#define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988
+#define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c
+
+#define S_PTP_OFFSET 0
+#define M_PTP_OFFSET 0xffU
+#define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET)
+#define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET)
+
+#define A_MAC_PORT_PTP_SUM_LO 0x990
+#define A_MAC_PORT_PTP_SUM_HI 0x994
+#define A_MAC_PORT_PTP_TIMER_INCR0 0x998
+
+#define S_Y 16
+#define M_Y 0xffffU
+#define V_Y(x) ((x) << S_Y)
+#define G_Y(x) (((x) >> S_Y) & M_Y)
+
+#define S_X 0
+#define M_X 0xffffU
+#define V_X(x) ((x) << S_X)
+#define G_X(x) (((x) >> S_X) & M_X)
+
+#define A_MAC_PORT_PTP_TIMER_INCR1 0x99c
+
+#define S_Y_TICK 16
+#define M_Y_TICK 0xffffU
+#define V_Y_TICK(x) ((x) << S_Y_TICK)
+#define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK)
+
+#define S_X_TICK 0
+#define M_X_TICK 0xffffU
+#define V_X_TICK(x) ((x) << S_X_TICK)
+#define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK)
+
+#define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
+#define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
+
+#define S_B 16
+#define M_B 0xffffU
+#define V_B(x) ((x) << S_B)
+#define G_B(x) (((x) >> S_B) & M_B)
+
+#define S_A 0
+#define M_A 0xffffU
+#define V_A(x) ((x) << S_A)
+#define G_A(x) (((x) >> S_A) & M_A)
+
+#define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
+#define A_MAC_PORT_PTP_CFG 0x9ac
+
+#define S_FRZ 18
+#define V_FRZ(x) ((x) << S_FRZ)
+#define F_FRZ V_FRZ(1U)
+
+#define S_OFFSER_ADJUST_SIGN 17
+#define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN)
+#define F_OFFSER_ADJUST_SIGN V_OFFSER_ADJUST_SIGN(1U)
+
+#define S_ADD_OFFSET 16
+#define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET)
+#define F_ADD_OFFSET V_ADD_OFFSET(1U)
+
+#define S_CYCLE1 8
+#define M_CYCLE1 0xffU
+#define V_CYCLE1(x) ((x) << S_CYCLE1)
+#define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1)
+
+#define S_Q 0
+#define M_Q 0xffU
+#define V_Q(x) ((x) << S_Q)
+#define G_Q(x) (((x) >> S_Q) & M_Q)
+
+#define A_MAC_PORT_MTIP_REVISION 0xa00
+
+#define S_CUSTREV 16
+#define M_CUSTREV 0xffffU
+#define V_CUSTREV(x) ((x) << S_CUSTREV)
+#define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV)
+
+#define S_VER 8
+#define M_VER 0xffU
+#define V_VER(x) ((x) << S_VER)
+#define G_VER(x) (((x) >> S_VER) & M_VER)
+
+#define S_MTIP_REV 0
+#define M_MTIP_REV 0xffU
+#define V_MTIP_REV(x) ((x) << S_MTIP_REV)
+#define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV)
+
+#define A_MAC_PORT_MTIP_SCRATCH 0xa04
+#define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08
+
+#define S_TX_FLUSH_ENABLE 22
+#define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE)
+#define F_TX_FLUSH_ENABLE V_TX_FLUSH_ENABLE(1U)
+
+#define S_RX_SFD_ANY 21
+#define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY)
+#define F_RX_SFD_ANY V_RX_SFD_ANY(1U)
+
+#define S_PAUSE_PFC_COMP 20
+#define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP)
+#define F_PAUSE_PFC_COMP V_PAUSE_PFC_COMP(1U)
+
+#define S_PFC_MODE 19
+#define V_PFC_MODE(x) ((x) << S_PFC_MODE)
+#define F_PFC_MODE V_PFC_MODE(1U)
+
+#define S_RS_COL_CNT_EXT 18
+#define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT)
+#define F_RS_COL_CNT_EXT V_RS_COL_CNT_EXT(1U)
+
+#define S_NO_LGTH_CHECK 17
+#define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK)
+#define F_NO_LGTH_CHECK V_NO_LGTH_CHECK(1U)
+
+#define S_SEND_IDLE 16
+#define V_SEND_IDLE(x) ((x) << S_SEND_IDLE)
+#define F_SEND_IDLE V_SEND_IDLE(1U)
+
+#define S_PHY_TXENA 15
+#define V_PHY_TXENA(x) ((x) << S_PHY_TXENA)
+#define F_PHY_TXENA V_PHY_TXENA(1U)
+
+#define S_RX_ERR_DISC 14
+#define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC)
+#define F_RX_ERR_DISC V_RX_ERR_DISC(1U)
+
+#define S_CMD_FRAME_ENA 13
+#define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA)
+#define F_CMD_FRAME_ENA V_CMD_FRAME_ENA(1U)
+
+#define S_SW_RESET 12
+#define V_SW_RESET(x) ((x) << S_SW_RESET)
+#define F_SW_RESET V_SW_RESET(1U)
+
+#define S_TX_PAD_EN 11
+#define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN)
+#define F_TX_PAD_EN V_TX_PAD_EN(1U)
+
+#define S_PHY_LOOPBACK_EN 10
+#define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN)
+#define F_PHY_LOOPBACK_EN V_PHY_LOOPBACK_EN(1U)
+
+#define S_TX_ADDR_INS 9
+#define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS)
+#define F_TX_ADDR_INS V_TX_ADDR_INS(1U)
+
+#define S_PAUSE_IGNORE 8
+#define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE)
+#define F_PAUSE_IGNORE V_PAUSE_IGNORE(1U)
+
+#define S_PAUSE_FWD 7
+#define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD)
+#define F_PAUSE_FWD V_PAUSE_FWD(1U)
+
+#define S_CRC_FWD 6
+#define V_CRC_FWD(x) ((x) << S_CRC_FWD)
+#define F_CRC_FWD V_CRC_FWD(1U)
+
+#define S_PAD_EN 5
+#define V_PAD_EN(x) ((x) << S_PAD_EN)
+#define F_PAD_EN V_PAD_EN(1U)
+
+#define S_PROMIS_EN 4
+#define V_PROMIS_EN(x) ((x) << S_PROMIS_EN)
+#define F_PROMIS_EN V_PROMIS_EN(1U)
+
+#define S_WAN_MODE 3
+#define V_WAN_MODE(x) ((x) << S_WAN_MODE)
+#define F_WAN_MODE V_WAN_MODE(1U)
+
+#define S_RX_ENA 1
+#define V_RX_ENA(x) ((x) << S_RX_ENA)
+#define F_RX_ENA V_RX_ENA(1U)
+
+#define S_TX_ENA 0
+#define V_TX_ENA(x) ((x) << S_TX_ENA)
+#define F_TX_ENA V_TX_ENA(1U)
+
+#define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c
+#define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10
+
+#define S_MACADDRHI 0
+#define M_MACADDRHI 0xffffU
+#define V_MACADDRHI(x) ((x) << S_MACADDRHI)
+#define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI)
+
+#define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14
+
+#define S_LEN 0
+#define M_LEN 0xffffU
+#define V_LEN(x) ((x) << S_LEN)
+#define G_LEN(x) (((x) >> S_LEN) & M_LEN)
+
+#define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c
+
+#define S_AVAIL 16
+#define M_AVAIL 0xffffU
+#define V_AVAIL(x) ((x) << S_AVAIL)
+#define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL)
+
+#define S_EMPTY 0
+#define M_EMPTY 0xffffU
+#define V_EMPTY(x) ((x) << S_EMPTY)
+#define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY)
+
+#define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20
+#define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24
+
+#define S_ALMSTFULL 16
+#define M_ALMSTFULL 0xffffU
+#define V_ALMSTFULL(x) ((x) << S_ALMSTFULL)
+#define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL)
+
+#define S_ALMSTEMPTY 0
+#define M_ALMSTEMPTY 0xffffU
+#define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY)
+#define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY)
+
+#define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28
+#define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c
+
+#define S_ENABLE_MCAST_RX 8
+#define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX)
+#define F_ENABLE_MCAST_RX V_ENABLE_MCAST_RX(1U)
+
+#define S_HASHTABLE_ADDR 0
+#define M_HASHTABLE_ADDR 0x3fU
+#define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR)
+#define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR)
+
+#define A_MAC_PORT_MTIP_MAC_STATUS 0xa40
+
+#define S_TS_AVAIL 3
+#define V_TS_AVAIL(x) ((x) << S_TS_AVAIL)
+#define F_TS_AVAIL V_TS_AVAIL(1U)
+
+#define S_PHY_LOS 2
+#define V_PHY_LOS(x) ((x) << S_PHY_LOS)
+#define F_PHY_LOS V_PHY_LOS(1U)
+
+#define S_RX_REM_FAULT 1
+#define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT)
+#define F_RX_REM_FAULT V_RX_REM_FAULT(1U)
+
+#define S_RX_LOC_FAULT 0
+#define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT)
+#define F_RX_LOC_FAULT V_RX_LOC_FAULT(1U)
+
+#define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44
+
+#define S_IPG 0
+#define M_IPG 0x7fU
+#define V_IPG(x) ((x) << S_IPG)
+#define G_IPG(x) (((x) >> S_IPG) & M_IPG)
+
+#define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48
+
+#define S_RXFIFORST 0
+#define V_RXFIFORST(x) ((x) << S_RXFIFORST)
+#define F_RXFIFORST V_RXFIFORST(1U)
+
+#define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c
+
+#define S_MACCRDRST 0
+#define M_MACCRDRST 0xffU
+#define V_MACCRDRST(x) ((x) << S_MACCRDRST)
+#define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST)
+
+#define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50
+
+#define S_INITCREDIT 0
+#define M_INITCREDIT 0xffU
+#define V_INITCREDIT(x) ((x) << S_INITCREDIT)
+#define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT)
+
+#define A_MAC_PORT_RX_PAUSE_STATUS 0xa74
+
+#define S_STATUS 0
+#define M_STATUS 0xffU
+#define V_STATUS(x) ((x) << S_STATUS)
+#define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS)
+
+#define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c
+#define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
+#define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
+#define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
+#define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
+#define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90
+#define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94
+#define A_MAC_PORT_AALIGNMENTERRORS 0xa98
+#define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c
+#define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0
+#define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4
+#define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8
+#define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac
+#define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0
+#define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4
+#define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8
+#define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc
+#define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0
+#define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4
+#define A_MAC_PORT_VLANRECEIVEDOK 0xac8
+#define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc
+#define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0
+#define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4
+#define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8
+#define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc
+#define A_MAC_PORT_IFINUCASTPKTS 0xae0
+#define A_MAC_PORT_IFINUCASTPKTSHI 0xae4
+#define A_MAC_PORT_IFINMULTICASTPKTS 0xae8
+#define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec
+#define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0
+#define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4
+#define A_MAC_PORT_IFOUTERRORS 0xaf8
+#define A_MAC_PORT_IFOUTERRORSHI 0xafc
+#define A_MAC_PORT_IFOUTUCASTPKTS 0xb08
+#define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c
+#define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10
+#define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14
+#define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18
+#define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c
+#define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20
+#define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24
+#define A_MAC_PORT_ETHERSTATSOCTETS 0xb28
+#define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c
+#define A_MAC_PORT_ETHERSTATSPKTS 0xb30
+#define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34
+#define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38
+#define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c
+#define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40
+#define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44
+#define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48
+#define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c
+#define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50
+#define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54
+#define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58
+#define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c
+#define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60
+#define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64
+#define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68
+#define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c
+#define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70
+#define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74
+#define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78
+#define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c
+#define A_MAC_PORT_ETHERSTATSJABBERS 0xb80
+#define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84
+#define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88
+#define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c
+#define A_MAC_PORT_IFINERRORS 0xb90
+#define A_MAC_PORT_IFINERRORSHI 0xb94
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14
+#define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18
+#define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c
+#define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20
+#define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24
+#define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00
+
+#define S_RESET 15
+#define V_RESET(x) ((x) << S_RESET)
+#define F_RESET V_RESET(1U)
+
+#define S_LOOPBACK 14
+#define V_LOOPBACK(x) ((x) << S_LOOPBACK)
+#define F_LOOPBACK V_LOOPBACK(1U)
+
+#define S_SPPEDSEL1 13
+#define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1)
+#define F_SPPEDSEL1 V_SPPEDSEL1(1U)
+
+#define S_AN_EN 12
+#define V_AN_EN(x) ((x) << S_AN_EN)
+#define F_AN_EN V_AN_EN(1U)
+
+#define S_PWRDWN 11
+#define V_PWRDWN(x) ((x) << S_PWRDWN)
+#define F_PWRDWN V_PWRDWN(1U)
+
+#define S_ISOLATE 10
+#define V_ISOLATE(x) ((x) << S_ISOLATE)
+#define F_ISOLATE V_ISOLATE(1U)
+
+#define S_AN_RESTART 9
+#define V_AN_RESTART(x) ((x) << S_AN_RESTART)
+#define F_AN_RESTART V_AN_RESTART(1U)
+
+#define S_DPLX 8
+#define V_DPLX(x) ((x) << S_DPLX)
+#define F_DPLX V_DPLX(1U)
+
+#define S_COLLISIONTEST 7
+#define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST)
+#define F_COLLISIONTEST V_COLLISIONTEST(1U)
+
+#define S_SPEEDSEL0 6
+#define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0)
+#define F_SPEEDSEL0 V_SPEEDSEL0(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
+
+#define S_100BASET4 15
+#define V_100BASET4(x) ((x) << S_100BASET4)
+#define F_100BASET4 V_100BASET4(1U)
+
+#define S_100BASEXFULLDPLX 14
+#define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX)
+#define F_100BASEXFULLDPLX V_100BASEXFULLDPLX(1U)
+
+#define S_100BASEXHALFDPLX 13
+#define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX)
+#define F_100BASEXHALFDPLX V_100BASEXHALFDPLX(1U)
+
+#define S_10MBPSFULLDPLX 12
+#define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX)
+#define F_10MBPSFULLDPLX V_10MBPSFULLDPLX(1U)
+
+#define S_10MBPSHALFDPLX 11
+#define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX)
+#define F_10MBPSHALFDPLX V_10MBPSHALFDPLX(1U)
+
+#define S_100BASET2FULLDPLX 10
+#define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX)
+#define F_100BASET2FULLDPLX V_100BASET2FULLDPLX(1U)
+
+#define S_100BASET2HALFDPLX 9
+#define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX)
+#define F_100BASET2HALFDPLX V_100BASET2HALFDPLX(1U)
+
+#define S_EXTDSTATUS 8
+#define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS)
+#define F_EXTDSTATUS V_EXTDSTATUS(1U)
+
+#define S_SGMII_REM_FAULT 4
+#define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT)
+#define F_SGMII_REM_FAULT V_SGMII_REM_FAULT(1U)
+
+#define S_JABBERDETECT 1
+#define V_JABBERDETECT(x) ((x) << S_JABBERDETECT)
+#define F_JABBERDETECT V_JABBERDETECT(1U)
+
+#define S_EXTDCAPABILITY 0
+#define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY)
+#define F_EXTDCAPABILITY V_EXTDCAPABILITY(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
+#define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
+#define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
+
+#define S_RF2 13
+#define V_RF2(x) ((x) << S_RF2)
+#define F_RF2 V_RF2(1U)
+
+#define S_RF1 12
+#define V_RF1(x) ((x) << S_RF1)
+#define F_RF1 V_RF1(1U)
+
+#define S_PS2 8
+#define V_PS2(x) ((x) << S_PS2)
+#define F_PS2 V_PS2(1U)
+
+#define S_PS1 7
+#define V_PS1(x) ((x) << S_PS1)
+#define F_PS1 V_PS1(1U)
+
+#define S_HD 6
+#define V_HD(x) ((x) << S_HD)
+#define F_HD V_HD(1U)
+
+#define S_FD 5
+#define V_FD(x) ((x) << S_FD)
+#define F_FD V_FD(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
+
+#define S_CULINKSTATUS 15
+#define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS)
+#define F_CULINKSTATUS V_CULINKSTATUS(1U)
+
+#define S_CUDPLXSTATUS 12
+#define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS)
+#define F_CUDPLXSTATUS V_CUDPLXSTATUS(1U)
+
+#define S_CUSPEED 10
+#define M_CUSPEED 0x3U
+#define V_CUSPEED(x) ((x) << S_CUSPEED)
+#define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED)
+
+#define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
+
+#define S_PGRCVD 1
+#define V_PGRCVD(x) ((x) << S_PGRCVD)
+#define F_PGRCVD V_PGRCVD(1U)
+
+#define S_REALTIMEPGRCVD 0
+#define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD)
+#define F_REALTIMEPGRCVD V_REALTIMEPGRCVD(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
+#define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
+#define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
+#define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
+
+#define S_COUNT_LO 0
+#define M_COUNT_LO 0xffffU
+#define V_COUNT_LO(x) ((x) << S_COUNT_LO)
+#define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO)
+
+#define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
+
+#define S_COUNT_HI 0
+#define M_COUNT_HI 0x1fU
+#define V_COUNT_HI(x) ((x) << S_COUNT_HI)
+#define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI)
+
+#define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
+
+#define S_SGMII_PCS_ENABLE 5
+#define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE)
+#define F_SGMII_PCS_ENABLE V_SGMII_PCS_ENABLE(1U)
+
+#define S_SGMII_HDUPLEX 4
+#define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX)
+#define F_SGMII_HDUPLEX V_SGMII_HDUPLEX(1U)
+
+#define S_SGMII_SPEED 2
+#define M_SGMII_SPEED 0x3U
+#define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED)
+#define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED)
+
+#define S_USE_SGMII_AN 1
+#define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN)
+#define F_USE_SGMII_AN V_USE_SGMII_AN(1U)
+
+#define S_SGMII_ENA 0
+#define V_SGMII_ENA(x) ((x) << S_SGMII_ENA)
+#define F_SGMII_ENA V_SGMII_ENA(1U)
+
+#define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
+
+#define S_ACTIVE 0
+#define M_ACTIVE 0x3fU
+#define V_ACTIVE(x) ((x) << S_ACTIVE)
+#define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE)
+
+#define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
+
+#define S_MODE_CTL 0
+#define M_MODE_CTL 0x3U
+#define V_MODE_CTL(x) ((x) << S_MODE_CTL)
+#define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL)
+
+#define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
+
+#define S_TXCLK_CTL 0
+#define M_TXCLK_CTL 0xffffU
+#define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL)
+#define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL)
+
+#define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
+#define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
+
+#define S_COL_CNT 0
+#define M_COL_CNT 0xffffU
+#define V_COL_CNT(x) ((x) << S_COL_CNT)
+#define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT)
+
+#define A_MAC_PORT_MTIP_VL_INTVL 0x1240
+
+#define S_VL_INTVL 1
+#define V_VL_INTVL(x) ((x) << S_VL_INTVL)
+#define F_VL_INTVL V_VL_INTVL(1U)
+
+#define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
+
+#define S_CLK_DIV 7
+#define M_CLK_DIV 0x1ffU
+#define V_CLK_DIV(x) ((x) << S_CLK_DIV)
+#define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV)
+
+#define S_CL45_EN 6
+#define V_CL45_EN(x) ((x) << S_CL45_EN)
+#define F_CL45_EN V_CL45_EN(1U)
+
+#define S_DISABLE_PREAMBLE 5
+#define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE)
+#define F_DISABLE_PREAMBLE V_DISABLE_PREAMBLE(1U)
+
+#define S_MDIO_HOLD_TIME 2
+#define M_MDIO_HOLD_TIME 0x7U
+#define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME)
+#define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME)
+
+#define S_MDIO_READ_ERR 1
+#define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR)
+#define F_MDIO_READ_ERR V_MDIO_READ_ERR(1U)
+
+#define S_MDIO_BUSY 0
+#define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY)
+#define F_MDIO_BUSY V_MDIO_BUSY(1U)
+
+#define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604
+
+#define S_MDIO_CMD_READ 15
+#define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ)
+#define F_MDIO_CMD_READ V_MDIO_CMD_READ(1U)
+
+#define S_READ_INCR 14
+#define V_READ_INCR(x) ((x) << S_READ_INCR)
+#define F_READ_INCR V_READ_INCR(1U)
+
+#define S_PORT_ADDR 5
+#define M_PORT_ADDR 0x1fU
+#define V_PORT_ADDR(x) ((x) << S_PORT_ADDR)
+#define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR)
+
+#define S_DEV_ADDR 0
+#define M_DEV_ADDR 0x1fU
+#define V_DEV_ADDR(x) ((x) << S_DEV_ADDR)
+#define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR)
+
+#define A_MAC_PORT_MTIP_MDIO_DATA 0x1608
+
+#define S_READBUSY 31
+#define V_READBUSY(x) ((x) << S_READBUSY)
+#define F_READBUSY V_READBUSY(1U)
+
+#define S_DATA_WORD 0
+#define M_DATA_WORD 0xffffU
+#define V_DATA_WORD(x) ((x) << S_DATA_WORD)
+#define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD)
+
+#define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c
+
+#define S_MDIO_ADDR 0
+#define M_MDIO_ADDR 0xffffU
+#define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR)
+#define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR)
+
+#define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
+
+#if 0 /* M_VLANTAG collides with M_VLANTAG in sys/mbuf.h */
+#define S_VLANTAG 0
+#define M_VLANTAG 0xffffU
+#define V_VLANTAG(x) ((x) << S_VLANTAG)
+#define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG)
+#endif
+
+#define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
+#define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
+#define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c
+#define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10
+#define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
+#define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
+#define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
+#define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
+
+#define S_PCS_LPBK 14
+#define V_PCS_LPBK(x) ((x) << S_PCS_LPBK)
+#define F_PCS_LPBK V_PCS_LPBK(1U)
+
+#define S_SPEED_SEL1 13
+#define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1)
+#define F_SPEED_SEL1 V_SPEED_SEL1(1U)
+
+#define S_LP_MODE 11
+#define V_LP_MODE(x) ((x) << S_LP_MODE)
+#define F_LP_MODE V_LP_MODE(1U)
+
+#define S_SPEED_SEL0 6
+#define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0)
+#define F_SPEED_SEL0 V_SPEED_SEL0(1U)
+
+#define S_PCS_SPEED 2
+#define M_PCS_SPEED 0xfU
+#define V_PCS_SPEED(x) ((x) << S_PCS_SPEED)
+#define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED)
+
+#define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04
+
+#define S_FAULTDET 7
+#define V_FAULTDET(x) ((x) << S_FAULTDET)
+#define F_FAULTDET V_FAULTDET(1U)
+
+#define S_RX_LINK_STATUS 2
+#define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS)
+#define F_RX_LINK_STATUS V_RX_LINK_STATUS(1U)
+
+#define S_LOPWRABL 1
+#define V_LOPWRABL(x) ((x) << S_LOPWRABL)
+#define F_LOPWRABL V_LOPWRABL(1U)
+
+#define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08
+
+#define S_DEVICE_ID0 0
+#define M_DEVICE_ID0 0xffffU
+#define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0)
+#define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0)
+
+#define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c
+
+#define S_DEVICE_ID1 0
+#define M_DEVICE_ID1 0xffffU
+#define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1)
+#define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1)
+
+#define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10
+
+#define S_100G 8
+#define V_100G(x) ((x) << S_100G)
+#define F_100G V_100G(1U)
+
+#define S_40G 7
+#define V_40G(x) ((x) << S_40G)
+#define F_40G V_40G(1U)
+
+#define S_10BASE_TL 1
+#define V_10BASE_TL(x) ((x) << S_10BASE_TL)
+#define F_10BASE_TL V_10BASE_TL(1U)
+
+#define S_10G 0
+#define V_10G(x) ((x) << S_10G)
+#define F_10G V_10G(1U)
+
+#define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14
+
+#define S_TC_PRESENT 6
+#define V_TC_PRESENT(x) ((x) << S_TC_PRESENT)
+#define F_TC_PRESENT V_TC_PRESENT(1U)
+
+#define S_DTEXS 5
+#define V_DTEXS(x) ((x) << S_DTEXS)
+#define F_DTEXS V_DTEXS(1U)
+
+#define S_PHYXS 4
+#define V_PHYXS(x) ((x) << S_PHYXS)
+#define F_PHYXS V_PHYXS(1U)
+
+#define S_PCS 3
+#define V_PCS(x) ((x) << S_PCS)
+#define F_PCS V_PCS(1U)
+
+#define S_WIS 2
+#define V_WIS(x) ((x) << S_WIS)
+#define F_WIS V_WIS(1U)
+
+#define S_PMD_PMA 1
+#define V_PMD_PMA(x) ((x) << S_PMD_PMA)
+#define F_PMD_PMA V_PMD_PMA(1U)
+
+#define S_CL22 0
+#define V_CL22(x) ((x) << S_CL22)
+#define F_CL22 V_CL22(1U)
+
+#define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18
+
+#define S_VENDDEV2 15
+#define V_VENDDEV2(x) ((x) << S_VENDDEV2)
+#define F_VENDDEV2 V_VENDDEV2(1U)
+
+#define S_VENDDEV1 14
+#define V_VENDDEV1(x) ((x) << S_VENDDEV1)
+#define F_VENDDEV1 V_VENDDEV1(1U)
+
+#define S_CL22EXT 13
+#define V_CL22EXT(x) ((x) << S_CL22EXT)
+#define F_CL22EXT V_CL22EXT(1U)
+
+#define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c
+
+#define S_PCSTYPE 0
+#define M_PCSTYPE 0x7U
+#define V_PCSTYPE(x) ((x) << S_PCSTYPE)
+#define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE)
+
+#define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20
+
+#define S_PCS_STAT2_DEVICE 15
+#define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE)
+#define F_PCS_STAT2_DEVICE V_PCS_STAT2_DEVICE(1U)
+
+#define S_TXFAULT 7
+#define V_TXFAULT(x) ((x) << S_TXFAULT)
+#define F_TXFAULT V_TXFAULT(1U)
+
+#define S_RXFAULT 6
+#define V_RXFAULT(x) ((x) << S_RXFAULT)
+#define F_RXFAULT V_RXFAULT(1U)
+
+#define S_100BASE_R 5
+#define V_100BASE_R(x) ((x) << S_100BASE_R)
+#define F_100BASE_R V_100BASE_R(1U)
+
+#define S_40GBASE_R 4
+#define V_40GBASE_R(x) ((x) << S_40GBASE_R)
+#define F_40GBASE_R V_40GBASE_R(1U)
+
+#define S_10GBASE_T 3
+#define V_10GBASE_T(x) ((x) << S_10GBASE_T)
+#define F_10GBASE_T V_10GBASE_T(1U)
+
+#define S_10GBASE_W 2
+#define V_10GBASE_W(x) ((x) << S_10GBASE_W)
+#define F_10GBASE_W V_10GBASE_W(1U)
+
+#define S_10GBASE_X 1
+#define V_10GBASE_X(x) ((x) << S_10GBASE_X)
+#define F_10GBASE_X V_10GBASE_X(1U)
+
+#define S_10GBASE_R 0
+#define V_10GBASE_R(x) ((x) << S_10GBASE_R)
+#define F_10GBASE_R V_10GBASE_R(1U)
+
+#define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
+
+#define S_PKG_ID0 0
+#define M_PKG_ID0 0xffffU
+#define V_PKG_ID0(x) ((x) << S_PKG_ID0)
+#define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0)
+
+#define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
+
+#define S_PKG_ID1 0
+#define M_PKG_ID1 0xffffU
+#define V_PKG_ID1(x) ((x) << S_PKG_ID1)
+#define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1)
+
+#define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
+
+#define S_RXLINKSTATUS 12
+#define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS)
+#define F_RXLINKSTATUS V_RXLINKSTATUS(1U)
+
+#define S_RESEREVED 4
+#define M_RESEREVED 0xffU
+#define V_RESEREVED(x) ((x) << S_RESEREVED)
+#define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED)
+
+#define S_10GPRBS9 3
+#define V_10GPRBS9(x) ((x) << S_10GPRBS9)
+#define F_10GPRBS9 V_10GPRBS9(1U)
+
+#define S_10GPRBS31 2
+#define V_10GPRBS31(x) ((x) << S_10GPRBS31)
+#define F_10GPRBS31 V_10GPRBS31(1U)
+
+#define S_HIBER 1
+#define V_HIBER(x) ((x) << S_HIBER)
+#define F_HIBER V_HIBER(1U)
+
+#define S_BLOCKLOCK 0
+#define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK)
+#define F_BLOCKLOCK V_BLOCKLOCK(1U)
+
+#define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84
+
+#define S_BLOCKLOCKLL 15
+#define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL)
+#define F_BLOCKLOCKLL V_BLOCKLOCKLL(1U)
+
+#define S_HIBERLH 14
+#define V_HIBERLH(x) ((x) << S_HIBERLH)
+#define F_HIBERLH V_HIBERLH(1U)
+
+#define S_HIBERCOUNT 8
+#define M_HIBERCOUNT 0x3fU
+#define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT)
+#define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT)
+
+#define S_ERRBLKCNT 0
+#define M_ERRBLKCNT 0xffU
+#define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT)
+#define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88
+
+#define S_SEEDA 0
+#define M_SEEDA 0xffffU
+#define V_SEEDA(x) ((x) << S_SEEDA)
+#define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c
+
+#define S_SEEDA1 0
+#define M_SEEDA1 0xffffU
+#define V_SEEDA1(x) ((x) << S_SEEDA1)
+#define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90
+
+#define S_SEEDA2 0
+#define M_SEEDA2 0xffffU
+#define V_SEEDA2(x) ((x) << S_SEEDA2)
+#define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94
+
+#define S_SEEDA3 0
+#define M_SEEDA3 0x3ffU
+#define V_SEEDA3(x) ((x) << S_SEEDA3)
+#define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98
+
+#define S_SEEDB 0
+#define M_SEEDB 0xffffU
+#define V_SEEDB(x) ((x) << S_SEEDB)
+#define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c
+
+#define S_SEEDB1 0
+#define M_SEEDB1 0xffffU
+#define V_SEEDB1(x) ((x) << S_SEEDB1)
+#define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0
+
+#define S_SEEDB2 0
+#define M_SEEDB2 0xffffU
+#define V_SEEDB2(x) ((x) << S_SEEDB2)
+#define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4
+
+#define S_SEEDB3 0
+#define M_SEEDB3 0x3ffU
+#define V_SEEDB3(x) ((x) << S_SEEDB3)
+#define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3)
+
+#define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8
+
+#define S_TXPRBS9 6
+#define V_TXPRBS9(x) ((x) << S_TXPRBS9)
+#define F_TXPRBS9 V_TXPRBS9(1U)
+
+#define S_RXPRBS31 5
+#define V_RXPRBS31(x) ((x) << S_RXPRBS31)
+#define F_RXPRBS31 V_RXPRBS31(1U)
+
+#define S_TXPRBS31 4
+#define V_TXPRBS31(x) ((x) << S_TXPRBS31)
+#define F_TXPRBS31 V_TXPRBS31(1U)
+
+#define S_TXTESTPATEN 3
+#define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN)
+#define F_TXTESTPATEN V_TXTESTPATEN(1U)
+
+#define S_RXTESTPATEN 2
+#define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN)
+#define F_RXTESTPATEN V_RXTESTPATEN(1U)
+
+#define S_TESTPATSEL 1
+#define V_TESTPATSEL(x) ((x) << S_TESTPATSEL)
+#define F_TESTPATSEL V_TESTPATSEL(1U)
+
+#define S_DATAPATSEL 0
+#define V_DATAPATSEL(x) ((x) << S_DATAPATSEL)
+#define F_DATAPATSEL V_DATAPATSEL(1U)
+
+#define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac
+
+#define S_TEST_ERR_CNT 0
+#define M_TEST_ERR_CNT 0xffffU
+#define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT)
+#define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT)
+
+#define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0
+
+#define S_BER_CNT_HI 0
+#define M_BER_CNT_HI 0xffffU
+#define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI)
+#define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI)
+
+#define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4
+
+#define S_HICOUNTPRSNT 15
+#define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT)
+#define F_HICOUNTPRSNT V_HICOUNTPRSNT(1U)
+
+#define S_BLOCK_CNT_HI 0
+#define M_BLOCK_CNT_HI 0x3fffU
+#define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI)
+#define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI)
+
+#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8
+
+#define S_ALIGNSTATUS 12
+#define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS)
+#define F_ALIGNSTATUS V_ALIGNSTATUS(1U)
+
+#define S_LANE7 7
+#define V_LANE7(x) ((x) << S_LANE7)
+#define F_LANE7 V_LANE7(1U)
+
+#define S_LANE6 6
+#define V_LANE6(x) ((x) << S_LANE6)
+#define F_LANE6 V_LANE6(1U)
+
+#define S_LANE5 5
+#define V_LANE5(x) ((x) << S_LANE5)
+#define F_LANE5 V_LANE5(1U)
+
+#define S_LANE4 4
+#define V_LANE4(x) ((x) << S_LANE4)
+#define F_LANE4 V_LANE4(1U)
+
+#define S_LANE3 3
+#define V_LANE3(x) ((x) << S_LANE3)
+#define F_LANE3 V_LANE3(1U)
+
+#define S_LANE2 2
+#define V_LANE2(x) ((x) << S_LANE2)
+#define F_LANE2 V_LANE2(1U)
+
+#define S_LANE1 1
+#define V_LANE1(x) ((x) << S_LANE1)
+#define F_LANE1 V_LANE1(1U)
+
+#define S_LANE0 0
+#define V_LANE0(x) ((x) << S_LANE0)
+#define F_LANE0 V_LANE0(1U)
+
+#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc
+
+#define S_LANE19 11
+#define V_LANE19(x) ((x) << S_LANE19)
+#define F_LANE19 V_LANE19(1U)
+
+#define S_LANE18 10
+#define V_LANE18(x) ((x) << S_LANE18)
+#define F_LANE18 V_LANE18(1U)
+
+#define S_LANE17 9
+#define V_LANE17(x) ((x) << S_LANE17)
+#define F_LANE17 V_LANE17(1U)
+
+#define S_LANE16 8
+#define V_LANE16(x) ((x) << S_LANE16)
+#define F_LANE16 V_LANE16(1U)
+
+#define S_LANE15 7
+#define V_LANE15(x) ((x) << S_LANE15)
+#define F_LANE15 V_LANE15(1U)
+
+#define S_LANE14 6
+#define V_LANE14(x) ((x) << S_LANE14)
+#define F_LANE14 V_LANE14(1U)
+
+#define S_LANE13 5
+#define V_LANE13(x) ((x) << S_LANE13)
+#define F_LANE13 V_LANE13(1U)
+
+#define S_LANE12 4
+#define V_LANE12(x) ((x) << S_LANE12)
+#define F_LANE12 V_LANE12(1U)
+
+#define S_LANE11 3
+#define V_LANE11(x) ((x) << S_LANE11)
+#define F_LANE11 V_LANE11(1U)
+
+#define S_LANE10 2
+#define V_LANE10(x) ((x) << S_LANE10)
+#define F_LANE10 V_LANE10(1U)
+
+#define S_LANE9 1
+#define V_LANE9(x) ((x) << S_LANE9)
+#define F_LANE9 V_LANE9(1U)
+
+#define S_LANE8 0
+#define V_LANE8(x) ((x) << S_LANE8)
+#define F_LANE8 V_LANE8(1U)
+
+#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0
+
+#define S_AMLOCK7 7
+#define V_AMLOCK7(x) ((x) << S_AMLOCK7)
+#define F_AMLOCK7 V_AMLOCK7(1U)
+
+#define S_AMLOCK6 6
+#define V_AMLOCK6(x) ((x) << S_AMLOCK6)
+#define F_AMLOCK6 V_AMLOCK6(1U)
+
+#define S_AMLOCK5 5
+#define V_AMLOCK5(x) ((x) << S_AMLOCK5)
+#define F_AMLOCK5 V_AMLOCK5(1U)
+
+#define S_AMLOCK4 4
+#define V_AMLOCK4(x) ((x) << S_AMLOCK4)
+#define F_AMLOCK4 V_AMLOCK4(1U)
+
+#define S_AMLOCK3 3
+#define V_AMLOCK3(x) ((x) << S_AMLOCK3)
+#define F_AMLOCK3 V_AMLOCK3(1U)
+
+#define S_AMLOCK2 2
+#define V_AMLOCK2(x) ((x) << S_AMLOCK2)
+#define F_AMLOCK2 V_AMLOCK2(1U)
+
+#define S_AMLOCK1 1
+#define V_AMLOCK1(x) ((x) << S_AMLOCK1)
+#define F_AMLOCK1 V_AMLOCK1(1U)
+
+#define S_AMLOCK0 0
+#define V_AMLOCK0(x) ((x) << S_AMLOCK0)
+#define F_AMLOCK0 V_AMLOCK0(1U)
+
+#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4
+
+#define S_AMLOCK19 11
+#define V_AMLOCK19(x) ((x) << S_AMLOCK19)
+#define F_AMLOCK19 V_AMLOCK19(1U)
+
+#define S_AMLOCK18 10
+#define V_AMLOCK18(x) ((x) << S_AMLOCK18)
+#define F_AMLOCK18 V_AMLOCK18(1U)
+
+#define S_AMLOCK17 9
+#define V_AMLOCK17(x) ((x) << S_AMLOCK17)
+#define F_AMLOCK17 V_AMLOCK17(1U)
+
+#define S_AMLOCK16 8
+#define V_AMLOCK16(x) ((x) << S_AMLOCK16)
+#define F_AMLOCK16 V_AMLOCK16(1U)
+
+#define S_AMLOCK15 7
+#define V_AMLOCK15(x) ((x) << S_AMLOCK15)
+#define F_AMLOCK15 V_AMLOCK15(1U)
+
+#define S_AMLOCK14 6
+#define V_AMLOCK14(x) ((x) << S_AMLOCK14)
+#define F_AMLOCK14 V_AMLOCK14(1U)
+
+#define S_AMLOCK13 5
+#define V_AMLOCK13(x) ((x) << S_AMLOCK13)
+#define F_AMLOCK13 V_AMLOCK13(1U)
+
+#define S_AMLOCK12 4
+#define V_AMLOCK12(x) ((x) << S_AMLOCK12)
+#define F_AMLOCK12 V_AMLOCK12(1U)
+
+#define S_AMLOCK11 3
+#define V_AMLOCK11(x) ((x) << S_AMLOCK11)
+#define F_AMLOCK11 V_AMLOCK11(1U)
+
+#define S_AMLOCK10 2
+#define V_AMLOCK10(x) ((x) << S_AMLOCK10)
+#define F_AMLOCK10 V_AMLOCK10(1U)
+
+#define S_AMLOCK9 1
+#define V_AMLOCK9(x) ((x) << S_AMLOCK9)
+#define F_AMLOCK9 V_AMLOCK9(1U)
+
+#define S_AMLOCK8 0
+#define V_AMLOCK8(x) ((x) << S_AMLOCK8)
+#define F_AMLOCK8 V_AMLOCK8(1U)
+
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68
+
+#define S_BIPERR_CNT 0
+#define M_BIPERR_CNT 0xffffU
+#define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT)
+#define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT)
+
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8
+
+#define S_MAP 0
+#define M_MAP 0x1fU
+#define V_MAP(x) ((x) << S_MAP)
+#define G_MAP(x) (((x) >> S_MAP) & M_MAP)
+
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
+#define A_MAC_PORT_BEAN_CTL 0x2200
+
+#define S_AN_RESET 15
+#define V_AN_RESET(x) ((x) << S_AN_RESET)
+#define F_AN_RESET V_AN_RESET(1U)
+
+#define S_EXT_NXP_CTRL 13
+#define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL)
+#define F_EXT_NXP_CTRL V_EXT_NXP_CTRL(1U)
+
+#define S_BEAN_EN 12
+#define V_BEAN_EN(x) ((x) << S_BEAN_EN)
+#define F_BEAN_EN V_BEAN_EN(1U)
+
+#define S_RESTART_BEAN 9
+#define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN)
+#define F_RESTART_BEAN V_RESTART_BEAN(1U)
+
+#define A_MAC_PORT_BEAN_STATUS 0x2204
+
+#define S_PDF 9
+#define V_PDF(x) ((x) << S_PDF)
+#define F_PDF V_PDF(1U)
+
+#define S_EXT_NXP_STATUS 7
+#define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS)
+#define F_EXT_NXP_STATUS V_EXT_NXP_STATUS(1U)
+
+#define S_PAGE_RCVD 6
+#define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD)
+#define F_PAGE_RCVD V_PAGE_RCVD(1U)
+
+#define S_BEAN_COMPLETE 5
+#define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE)
+#define F_BEAN_COMPLETE V_BEAN_COMPLETE(1U)
+
+#define S_REM_FAULT_STATUS 4
+#define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS)
+#define F_REM_FAULT_STATUS V_REM_FAULT_STATUS(1U)
+
+#define S_BEAN_ABILITY 3
+#define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY)
+#define F_BEAN_ABILITY V_BEAN_ABILITY(1U)
+
+#define S_LP_BEAN_ABILITY 0
+#define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY)
+#define F_LP_BEAN_ABILITY V_LP_BEAN_ABILITY(1U)
+
+#define A_MAC_PORT_BEAN_ABILITY_0 0x2208
+
+#define S_NXP 15
+#define V_NXP(x) ((x) << S_NXP)
+#define F_NXP V_NXP(1U)
+
+#define S_REM_FAULT 13
+#define V_REM_FAULT(x) ((x) << S_REM_FAULT)
+#define F_REM_FAULT V_REM_FAULT(1U)
+
+#define S_PAUSE_ABILITY 10
+#define M_PAUSE_ABILITY 0x7U
+#define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY)
+#define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY)
+
+#define S_ECHO_NONCE 5
+#define M_ECHO_NONCE 0x1fU
+#define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE)
+#define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE)
+
+#define S_SELECTOR 0
+#define M_SELECTOR 0x1fU
+#define V_SELECTOR(x) ((x) << S_SELECTOR)
+#define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR)
+
+#define A_MAC_PORT_BEAN_ABILITY_1 0x220c
+
+#define S_TECH_ABILITY_1 5
+#define M_TECH_ABILITY_1 0x7ffU
+#define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1)
+#define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1)
+
+#define S_TX_NONCE 0
+#define M_TX_NONCE 0x1fU
+#define V_TX_NONCE(x) ((x) << S_TX_NONCE)
+#define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE)
+
+#define A_MAC_PORT_BEAN_ABILITY_2 0x2210
+
+#define S_T5_FEC_ABILITY 14
+#define M_T5_FEC_ABILITY 0x3U
+#define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY)
+#define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY)
+
+#define S_TECH_ABILITY_2 0
+#define M_TECH_ABILITY_2 0x3fffU
+#define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2)
+#define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2)
+
+#define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
+#define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
+#define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
+#define A_MAC_PORT_BEAN_MS_COUNT 0x2220
+
+#define S_MS_COUNT 0
+#define M_MS_COUNT 0xffffU
+#define V_MS_COUNT(x) ((x) << S_MS_COUNT)
+#define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT)
+
+#define A_MAC_PORT_BEAN_XNP_0 0x2224
+
+#define S_XNP 15
+#define V_XNP(x) ((x) << S_XNP)
+#define F_XNP V_XNP(1U)
+
+#define S_ACKNOWLEDGE 14
+#define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE)
+#define F_ACKNOWLEDGE V_ACKNOWLEDGE(1U)
+
+#define S_MP 13
+#define V_MP(x) ((x) << S_MP)
+#define F_MP V_MP(1U)
+
+#define S_ACK2 12
+#define V_ACK2(x) ((x) << S_ACK2)
+#define F_ACK2 V_ACK2(1U)
+
+#define S_MU 0
+#define M_MU 0x7ffU
+#define V_MU(x) ((x) << S_MU)
+#define G_MU(x) (((x) >> S_MU) & M_MU)
+
+#define A_MAC_PORT_BEAN_XNP_1 0x2228
+
+#define S_UNFORMATED 0
+#define M_UNFORMATED 0xffffU
+#define V_UNFORMATED(x) ((x) << S_UNFORMATED)
+#define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED)
+
+#define A_MAC_PORT_BEAN_XNP_2 0x222c
+#define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
+#define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
+#define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
+#define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
+
+#define S_100GCR10 8
+#define V_100GCR10(x) ((x) << S_100GCR10)
+#define F_100GCR10 V_100GCR10(1U)
+
+#define S_40GCR4 6
+#define V_40GCR4(x) ((x) << S_40GCR4)
+#define F_40GCR4 V_40GCR4(1U)
+
+#define S_40GKR4 5
+#define V_40GKR4(x) ((x) << S_40GKR4)
+#define F_40GKR4 V_40GKR4(1U)
+
+#define S_FEC 4
+#define V_FEC(x) ((x) << S_FEC)
+#define F_FEC V_FEC(1U)
+
+#define S_10GKR 3
+#define V_10GKR(x) ((x) << S_10GKR)
+#define F_10GKR V_10GKR(1U)
+
+#define S_10GKX4 2
+#define V_10GKX4(x) ((x) << S_10GKX4)
+#define F_10GKX4 V_10GKX4(1U)
+
+#define S_1GKX 1
+#define V_1GKX(x) ((x) << S_1GKX)
+#define F_1GKX V_1GKX(1U)
+
+#define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
+#define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
+#define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
+#define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
+#define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
+#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254
+#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258
+#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c
+#define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260
+#define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264
+#define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268
+#define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c
+#define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270
+#define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274
+#define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278
+#define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c
+#define A_MAC_PORT_BEAN_CTL_LANE2 0x2280
+#define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284
+#define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288
+#define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c
+#define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290
+#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294
+#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298
+#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c
+#define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0
+#define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4
+#define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8
+#define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac
+#define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0
+#define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4
+#define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8
+#define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc
+#define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0
+#define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4
+#define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8
+#define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc
+#define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0
+#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4
+#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8
+#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc
+#define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0
+#define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4
+#define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8
+#define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec
+#define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0
+#define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
+#define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
+#define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
+#define A_MAC_PORT_FEC_KR_CONTROL 0x2600
+
+#define S_ENABLE_TR 1
+#define V_ENABLE_TR(x) ((x) << S_ENABLE_TR)
+#define F_ENABLE_TR V_ENABLE_TR(1U)
+
+#define S_RESTART_TR 0
+#define V_RESTART_TR(x) ((x) << S_RESTART_TR)
+#define F_RESTART_TR V_RESTART_TR(1U)
+
+#define A_MAC_PORT_FEC_KR_STATUS 0x2604
+
+#define S_FECKRSIGDET 15
+#define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET)
+#define F_FECKRSIGDET V_FECKRSIGDET(1U)
+
+#define S_TRAIN_FAIL 3
+#define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL)
+#define F_TRAIN_FAIL V_TRAIN_FAIL(1U)
+
+#define S_STARTUP_STATUS 2
+#define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS)
+#define F_STARTUP_STATUS V_STARTUP_STATUS(1U)
+
+#define S_RX_STATUS 0
+#define V_RX_STATUS(x) ((x) << S_RX_STATUS)
+#define F_RX_STATUS V_RX_STATUS(1U)
+
+#define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608
+
+#define S_PRESET 13
+#define V_PRESET(x) ((x) << S_PRESET)
+#define F_PRESET V_PRESET(1U)
+
+#define S_INITIALIZE 12
+#define V_INITIALIZE(x) ((x) << S_INITIALIZE)
+#define F_INITIALIZE V_INITIALIZE(1U)
+
+#define S_CP1_UPD 4
+#define M_CP1_UPD 0x3U
+#define V_CP1_UPD(x) ((x) << S_CP1_UPD)
+#define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD)
+
+#define S_C0_UPD 2
+#define M_C0_UPD 0x3U
+#define V_C0_UPD(x) ((x) << S_C0_UPD)
+#define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD)
+
+#define S_CN1_UPD 0
+#define M_CN1_UPD 0x3U
+#define V_CN1_UPD(x) ((x) << S_CN1_UPD)
+#define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD)
+
+#define A_MAC_PORT_FEC_KR_LP_STAT 0x260c
+
+#define S_RX_READY 15
+#define V_RX_READY(x) ((x) << S_RX_READY)
+#define F_RX_READY V_RX_READY(1U)
+
+#define S_CP1_STAT 4
+#define M_CP1_STAT 0x3U
+#define V_CP1_STAT(x) ((x) << S_CP1_STAT)
+#define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT)
+
+#define S_C0_STAT 2
+#define M_C0_STAT 0x3U
+#define V_C0_STAT(x) ((x) << S_C0_STAT)
+#define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT)
+
+#define S_CN1_STAT 0
+#define M_CN1_STAT 0x3U
+#define V_CN1_STAT(x) ((x) << S_CN1_STAT)
+#define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT)
+
+#define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610
+#define A_MAC_PORT_FEC_KR_LD_STAT 0x2614
+#define A_MAC_PORT_FEC_ABILITY 0x2618
+
+#define S_FEC_IND_ABILITY 1
+#define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY)
+#define F_FEC_IND_ABILITY V_FEC_IND_ABILITY(1U)
+
+#define S_ABILITY 0
+#define V_ABILITY(x) ((x) << S_ABILITY)
+#define F_ABILITY V_ABILITY(1U)
+
+#define A_MAC_PORT_FEC_CONTROL 0x261c
+
+#define S_FEC_EN_ERR_IND 1
+#define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND)
+#define F_FEC_EN_ERR_IND V_FEC_EN_ERR_IND(1U)
+
+#define S_FEC_EN 0
+#define V_FEC_EN(x) ((x) << S_FEC_EN)
+#define F_FEC_EN V_FEC_EN(1U)
+
+#define A_MAC_PORT_FEC_STATUS 0x2620
+
+#define S_FEC_LOCKED_100 1
+#define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100)
+#define F_FEC_LOCKED_100 V_FEC_LOCKED_100(1U)
+
+#define S_FEC_LOCKED 0
+#define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED)
+#define F_FEC_LOCKED V_FEC_LOCKED(1U)
+
+#define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
+
+#define S_FEC_CERR_CNT_0 0
+#define M_FEC_CERR_CNT_0 0xffffU
+#define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0)
+#define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0)
+
+#define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
+
+#define S_FEC_CERR_CNT_1 0
+#define M_FEC_CERR_CNT_1 0xffffU
+#define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1)
+#define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1)
+
+#define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
+
+#define S_FEC_NCERR_CNT_0 0
+#define M_FEC_NCERR_CNT_0 0xffffU
+#define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0)
+#define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0)
+
+#define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
+
+#define S_FEC_NCERR_CNT_1 0
+#define M_FEC_NCERR_CNT_1 0xffffU
+#define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1)
+#define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1)
+
+#define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
+
+#define S_T5_RXREQ_C2 4
+#define M_T5_RXREQ_C2 0x3U
+#define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2)
+#define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2)
+
+#define S_T5_RXREQ_C1 2
+#define M_T5_RXREQ_C1 0x3U
+#define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1)
+#define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1)
+
+#define S_T5_RXREQ_C0 0
+#define M_T5_RXREQ_C0 0x3U
+#define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0)
+#define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0)
+
+#define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
+
+#define S_T5_AE0_RXSTAT_RDY 15
+#define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY)
+#define F_T5_AE0_RXSTAT_RDY V_T5_AE0_RXSTAT_RDY(1U)
+
+#define S_T5_AE0_RXSTAT_C2 4
+#define M_T5_AE0_RXSTAT_C2 0x3U
+#define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2)
+#define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2)
+
+#define S_T5_AE0_RXSTAT_C1 2
+#define M_T5_AE0_RXSTAT_C1 0x3U
+#define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1)
+#define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1)
+
+#define S_T5_AE0_RXSTAT_C0 0
+#define M_T5_AE0_RXSTAT_C0 0x3U
+#define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0)
+#define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
+
+#define S_T5_TXREQ_C2 4
+#define M_T5_TXREQ_C2 0x3U
+#define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2)
+#define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2)
+
+#define S_T5_TXREQ_C1 2
+#define M_T5_TXREQ_C1 0x3U
+#define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1)
+#define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1)
+
+#define S_T5_TXREQ_C0 0
+#define M_T5_TXREQ_C0 0x3U
+#define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0)
+#define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
+
+#define S_T5_TXSTAT_C2 4
+#define M_T5_TXSTAT_C2 0x3U
+#define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2)
+#define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2)
+
+#define S_T5_TXSTAT_C1 2
+#define M_T5_TXSTAT_C1 0x3U
+#define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1)
+#define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1)
+
+#define S_T5_TXSTAT_C0 0
+#define M_T5_TXSTAT_C0 0x3U
+#define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0)
+#define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0)
+
+#define A_MAC_PORT_AE_REG_MODE 0x2a10
+
+#define S_AET_RSVD 7
+#define V_AET_RSVD(x) ((x) << S_AET_RSVD)
+#define F_AET_RSVD V_AET_RSVD(1U)
+
+#define S_AET_ENABLE 6
+#define V_AET_ENABLE(x) ((x) << S_AET_ENABLE)
+#define F_AET_ENABLE V_AET_ENABLE(1U)
+
+#define A_MAC_PORT_AE_PRBS_CTL 0x2a14
+#define A_MAC_PORT_AE_FSM_CTL 0x2a18
+
+#define S_CIN_ENABLE 15
+#define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE)
+#define F_CIN_ENABLE V_CIN_ENABLE(1U)
+
+#define A_MAC_PORT_AE_FSM_STATE 0x2a1c
+#define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20
+#define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24
+
+#define S_T5_AE1_RXSTAT_RDY 15
+#define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY)
+#define F_T5_AE1_RXSTAT_RDY V_T5_AE1_RXSTAT_RDY(1U)
+
+#define S_T5_AE1_RXSTAT_C2 4
+#define M_T5_AE1_RXSTAT_C2 0x3U
+#define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2)
+#define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2)
+
+#define S_T5_AE1_RXSTAT_C1 2
+#define M_T5_AE1_RXSTAT_C1 0x3U
+#define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1)
+#define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1)
+
+#define S_T5_AE1_RXSTAT_C0 0
+#define M_T5_AE1_RXSTAT_C0 0x3U
+#define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0)
+#define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
+#define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
+#define A_MAC_PORT_AE_REG_MODE_1 0x2a30
+#define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34
+#define A_MAC_PORT_AE_FSM_CTL_1 0x2a38
+#define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c
+#define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40
+#define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44
+
+#define S_T5_AE2_RXSTAT_RDY 15
+#define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY)
+#define F_T5_AE2_RXSTAT_RDY V_T5_AE2_RXSTAT_RDY(1U)
+
+#define S_T5_AE2_RXSTAT_C2 4
+#define M_T5_AE2_RXSTAT_C2 0x3U
+#define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2)
+#define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2)
+
+#define S_T5_AE2_RXSTAT_C1 2
+#define M_T5_AE2_RXSTAT_C1 0x3U
+#define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1)
+#define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1)
+
+#define S_T5_AE2_RXSTAT_C0 0
+#define M_T5_AE2_RXSTAT_C0 0x3U
+#define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0)
+#define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
+#define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
+#define A_MAC_PORT_AE_REG_MODE_2 0x2a50
+#define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54
+#define A_MAC_PORT_AE_FSM_CTL_2 0x2a58
+#define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c
+#define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60
+#define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64
+
+#define S_T5_AE3_RXSTAT_RDY 15
+#define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY)
+#define F_T5_AE3_RXSTAT_RDY V_T5_AE3_RXSTAT_RDY(1U)
+
+#define S_T5_AE3_RXSTAT_C2 4
+#define M_T5_AE3_RXSTAT_C2 0x3U
+#define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2)
+#define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2)
+
+#define S_T5_AE3_RXSTAT_C1 2
+#define M_T5_AE3_RXSTAT_C1 0x3U
+#define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1)
+#define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1)
+
+#define S_T5_AE3_RXSTAT_C0 0
+#define M_T5_AE3_RXSTAT_C0 0x3U
+#define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0)
+#define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
+#define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
+#define A_MAC_PORT_AE_REG_MODE_3 0x2a70
+#define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74
+#define A_MAC_PORT_AE_FSM_CTL_3 0x2a78
+#define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c
+#define A_MAC_PORT_AE_TX_DIS 0x2a80
+#define A_MAC_PORT_AE_KR_CTRL 0x2a84
+#define A_MAC_PORT_AE_RX_SIGDET 0x2a88
+#define A_MAC_PORT_AE_KR_STATUS 0x2a8c
+#define A_MAC_PORT_AE_TX_DIS_1 0x2a90
+#define A_MAC_PORT_AE_KR_CTRL_1 0x2a94
+#define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98
+#define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c
+#define A_MAC_PORT_AE_TX_DIS_2 0x2aa0
+#define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4
+#define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8
+#define A_MAC_PORT_AE_KR_STATUS_2 0x2aac
+#define A_MAC_PORT_AE_TX_DIS_3 0x2ab0
+#define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4
+#define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8
+#define A_MAC_PORT_AE_KR_STATUS_3 0x2abc
+#define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00
+
+#define S_EN_HOLD_FAIL 14
+#define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL)
+#define F_EN_HOLD_FAIL V_EN_HOLD_FAIL(1U)
+
+#define S_INIT_METH 12
+#define M_INIT_METH 0x3U
+#define V_INIT_METH(x) ((x) << S_INIT_METH)
+#define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH)
+
+#define S_CE_DECS 8
+#define M_CE_DECS 0xfU
+#define V_CE_DECS(x) ((x) << S_CE_DECS)
+#define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS)
+
+#define S_EN_ZFE 7
+#define V_EN_ZFE(x) ((x) << S_EN_ZFE)
+#define F_EN_ZFE V_EN_ZFE(1U)
+
+#define S_EN_GAIN_TOG 6
+#define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG)
+#define F_EN_GAIN_TOG V_EN_GAIN_TOG(1U)
+
+#define S_EN_AI_C1 5
+#define V_EN_AI_C1(x) ((x) << S_EN_AI_C1)
+#define F_EN_AI_C1 V_EN_AI_C1(1U)
+
+#define S_EN_MAX_ST 4
+#define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST)
+#define F_EN_MAX_ST V_EN_MAX_ST(1U)
+
+#define S_EN_H1T_EQ 3
+#define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ)
+#define F_EN_H1T_EQ V_EN_H1T_EQ(1U)
+
+#define S_H1TEQ_GOAL 0
+#define M_H1TEQ_GOAL 0x7U
+#define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL)
+#define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL)
+
+#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
+
+#define S_GAIN_TH 6
+#define M_GAIN_TH 0x1fU
+#define V_GAIN_TH(x) ((x) << S_GAIN_TH)
+#define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH)
+
+#define S_EN_SD_TH 5
+#define V_EN_SD_TH(x) ((x) << S_EN_SD_TH)
+#define F_EN_SD_TH V_EN_SD_TH(1U)
+
+#define S_EN_AMIN_TH 4
+#define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH)
+#define F_EN_AMIN_TH V_EN_AMIN_TH(1U)
+
+#define S_AMIN_TH 0
+#define M_AMIN_TH 0xfU
+#define V_AMIN_TH(x) ((x) << S_AMIN_TH)
+#define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH)
+
+#define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
+
+#define S_ACC_LIM 8
+#define M_ACC_LIM 0xfU
+#define V_ACC_LIM(x) ((x) << S_ACC_LIM)
+#define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM)
+
+#define S_CNV_LIM 4
+#define M_CNV_LIM 0xfU
+#define V_CNV_LIM(x) ((x) << S_CNV_LIM)
+#define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM)
+
+#define S_TOG_LIM 0
+#define M_TOG_LIM 0xfU
+#define V_TOG_LIM(x) ((x) << S_TOG_LIM)
+#define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM)
+
+#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c
+
+#define S_BOOT_LUT7 12
+#define M_BOOT_LUT7 0xfU
+#define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7)
+#define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7)
+
+#define S_BOOT_LUT6 8
+#define M_BOOT_LUT6 0xfU
+#define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6)
+#define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6)
+
+#define S_BOOT_LUT45 4
+#define M_BOOT_LUT45 0xfU
+#define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45)
+#define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45)
+
+#define S_BOOT_LUT0123 2
+#define M_BOOT_LUT0123 0x3U
+#define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123)
+#define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123)
+
+#define S_BOOT_DEC_C0 1
+#define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0)
+#define F_BOOT_DEC_C0 V_BOOT_DEC_C0(1U)
+
+#define A_MAC_PORT_AET_STATUS_0 0x2b10
+
+#define S_AET_STAT 9
+#define M_AET_STAT 0xfU
+#define V_AET_STAT(x) ((x) << S_AET_STAT)
+#define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT)
+
+#define S_NEU_STATE 5
+#define M_NEU_STATE 0xfU
+#define V_NEU_STATE(x) ((x) << S_NEU_STATE)
+#define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE)
+
+#define S_CTRL_STATE 0
+#define M_CTRL_STATE 0x1fU
+#define V_CTRL_STATE(x) ((x) << S_CTRL_STATE)
+#define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE)
+
+#define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
+#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
+#define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
+#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
+#define A_MAC_PORT_AET_STATUS_1 0x2b30
+#define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
+#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
+#define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
+#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
+#define A_MAC_PORT_AET_STATUS_2 0x2b50
+#define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
+#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
+#define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
+#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
+#define A_MAC_PORT_AET_STATUS_3 0x2b70
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
+
+#define S_T5_TX_LINKEN 15
+#define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN)
+#define F_T5_TX_LINKEN V_T5_TX_LINKEN(1U)
+
+#define S_T5_TX_LINKRST 14
+#define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST)
+#define F_T5_TX_LINKRST V_T5_TX_LINKRST(1U)
+
+#define S_T5_TX_CFGWRT 13
+#define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT)
+#define F_T5_TX_CFGWRT V_T5_TX_CFGWRT(1U)
+
+#define S_T5_TX_CFGPTR 11
+#define M_T5_TX_CFGPTR 0x3U
+#define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR)
+#define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR)
+
+#define S_T5_TX_CFGEXT 10
+#define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT)
+#define F_T5_TX_CFGEXT V_T5_TX_CFGEXT(1U)
+
+#define S_T5_TX_CFGACT 9
+#define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT)
+#define F_T5_TX_CFGACT V_T5_TX_CFGACT(1U)
+
+#define S_T5_TX_RSYNCC 8
+#define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC)
+#define F_T5_TX_RSYNCC V_T5_TX_RSYNCC(1U)
+
+#define S_T5_TX_PLLSEL 6
+#define M_T5_TX_PLLSEL 0x3U
+#define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL)
+#define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL)
+
+#define S_T5_TX_EXTC16 5
+#define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16)
+#define F_T5_TX_EXTC16 V_T5_TX_EXTC16(1U)
+
+#define S_T5_TX_DCKSEL 4
+#define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL)
+#define F_T5_TX_DCKSEL V_T5_TX_DCKSEL(1U)
+
+#define S_T5_TX_RXLOOP 3
+#define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP)
+#define F_T5_TX_RXLOOP V_T5_TX_RXLOOP(1U)
+
+#define S_T5_TX_BWSEL 2
+#define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL)
+#define F_T5_TX_BWSEL V_T5_TX_BWSEL(1U)
+
+#define S_T5_TX_RTSEL 0
+#define M_T5_TX_RTSEL 0x3U
+#define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL)
+#define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
+
+#define S_SPSEL 11
+#define M_SPSEL 0x7U
+#define V_SPSEL(x) ((x) << S_SPSEL)
+#define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL)
+
+#define S_AFDWEN 7
+#define V_AFDWEN(x) ((x) << S_AFDWEN)
+#define F_AFDWEN V_AFDWEN(1U)
+
+#define S_TPGMD 3
+#define V_TPGMD(x) ((x) << S_TPGMD)
+#define F_TPGMD V_TPGMD(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
+
+#define S_ZCALOVRD 8
+#define V_ZCALOVRD(x) ((x) << S_ZCALOVRD)
+#define F_ZCALOVRD V_ZCALOVRD(1U)
+
+#define S_AMMODE 7
+#define V_AMMODE(x) ((x) << S_AMMODE)
+#define F_AMMODE V_AMMODE(1U)
+
+#define S_AEPOL 6
+#define V_AEPOL(x) ((x) << S_AEPOL)
+#define F_AEPOL V_AEPOL(1U)
+
+#define S_AESRC 5
+#define V_AESRC(x) ((x) << S_AESRC)
+#define F_AESRC V_AESRC(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
+
+#define S_T5DRVHIZ 5
+#define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ)
+#define F_T5DRVHIZ V_T5DRVHIZ(1U)
+
+#define S_T5SASIMP 4
+#define V_T5SASIMP(x) ((x) << S_T5SASIMP)
+#define F_T5SASIMP V_T5SASIMP(1U)
+
+#define S_T5SLEW 2
+#define M_T5SLEW 0x3U
+#define V_T5SLEW(x) ((x) << S_T5SLEW)
+#define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010
+
+#define S_T5C2BUFDCEN 5
+#define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN)
+#define F_T5C2BUFDCEN V_T5C2BUFDCEN(1U)
+
+#define S_T5DCCEN 4
+#define V_T5DCCEN(x) ((x) << S_T5DCCEN)
+#define F_T5DCCEN V_T5DCCEN(1U)
+
+#define S_T5REGBYP 3
+#define V_T5REGBYP(x) ((x) << S_T5REGBYP)
+#define F_T5REGBYP V_T5REGBYP(1U)
+
+#define S_T5REGAEN 2
+#define V_T5REGAEN(x) ((x) << S_T5REGAEN)
+#define F_T5REGAEN V_T5REGAEN(1U)
+
+#define S_T5REGAMP 0
+#define M_T5REGAMP 0x3U
+#define V_T5REGAMP(x) ((x) << S_T5REGAMP)
+#define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014
+
+#define S_RSTEP 15
+#define V_RSTEP(x) ((x) << S_RSTEP)
+#define F_RSTEP V_RSTEP(1U)
+
+#define S_RLOCK 14
+#define V_RLOCK(x) ((x) << S_RLOCK)
+#define F_RLOCK V_RLOCK(1U)
+
+#define S_RPOS 8
+#define M_RPOS 0x3fU
+#define V_RPOS(x) ((x) << S_RPOS)
+#define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS)
+
+#define S_DCLKSAM 7
+#define V_DCLKSAM(x) ((x) << S_DCLKSAM)
+#define F_DCLKSAM V_DCLKSAM(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018
+
+#define S_CALSSTN 3
+#define M_CALSSTN 0x7U
+#define V_CALSSTN(x) ((x) << S_CALSSTN)
+#define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN)
+
+#define S_CALSSTP 0
+#define M_CALSSTP 0x7U
+#define V_CALSSTP(x) ((x) << S_CALSSTP)
+#define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
+
+#define S_DRTOL 0
+#define M_DRTOL 0x1fU
+#define V_DRTOL(x) ((x) << S_DRTOL)
+#define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
+
+#define S_T5NXTT0 0
+#define M_T5NXTT0 0x1fU
+#define V_T5NXTT0(x) ((x) << S_T5NXTT0)
+#define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
+
+#define S_T5NXTT1 0
+#define M_T5NXTT1 0x3fU
+#define V_T5NXTT1(x) ((x) << S_T5NXTT1)
+#define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028
+
+#define S_T5NXTT2 0
+#define M_T5NXTT2 0x3fU
+#define V_T5NXTT2(x) ((x) << S_T5NXTT2)
+#define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
+
+#define S_T5TXPWR 0
+#define M_T5TXPWR 0x3fU
+#define V_T5TXPWR(x) ((x) << S_T5TXPWR)
+#define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034
+
+#define S_NXTPOL 0
+#define M_NXTPOL 0x7U
+#define V_NXTPOL(x) ((x) << S_NXTPOL)
+#define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
+
+#define S_CPREST 13
+#define V_CPREST(x) ((x) << S_CPREST)
+#define F_CPREST V_CPREST(1U)
+
+#define S_CINIT 12
+#define V_CINIT(x) ((x) << S_CINIT)
+#define F_CINIT V_CINIT(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
+
+#define S_T5NIDAC1 0
+#define M_T5NIDAC1 0x3fU
+#define V_T5NIDAC1(x) ((x) << S_T5NIDAC1)
+#define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
+
+#define S_T5NIDAC2 0
+#define M_T5NIDAC2 0x3fU
+#define V_T5NIDAC2(x) ((x) << S_T5NIDAC2)
+#define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
+
+#define S_T5AIDAC1 0
+#define M_T5AIDAC1 0x3fU
+#define V_T5AIDAC1(x) ((x) << S_T5AIDAC1)
+#define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
+
+#define S_MAINSC 6
+#define M_MAINSC 0x3fU
+#define V_MAINSC(x) ((x) << S_MAINSC)
+#define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC)
+
+#define S_POSTSC 0
+#define M_POSTSC 0x3fU
+#define V_POSTSC(x) ((x) << S_POSTSC)
+#define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
+
+#define S_PRESC 0
+#define M_PRESC 0x1fU
+#define V_PRESC(x) ((x) << S_PRESC)
+#define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
+
+#define S_T5XADDR 1
+#define M_T5XADDR 0x1fU
+#define V_T5XADDR(x) ((x) << S_T5XADDR)
+#define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR)
+
+#define S_T5XWR 0
+#define V_T5XWR(x) ((x) << S_T5XWR)
+#define F_T5XWR V_T5XWR(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
+
+#define S_XDAT10 0
+#define M_XDAT10 0xffffU
+#define V_XDAT10(x) ((x) << S_XDAT10)
+#define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084
+
+#define S_XDAT32 0
+#define M_XDAT32 0xffffU
+#define V_XDAT32(x) ((x) << S_XDAT32)
+#define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088
+
+#define S_XDAT4 0
+#define M_XDAT4 0xffU
+#define V_XDAT4(x) ((x) << S_XDAT4)
+#define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
+
+#define S_DCCTIMEDOUT 15
+#define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT)
+#define F_DCCTIMEDOUT V_DCCTIMEDOUT(1U)
+
+#define S_DCCTIMEEN 14
+#define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN)
+#define F_DCCTIMEEN V_DCCTIMEEN(1U)
+
+#define S_DCCLOCK 13
+#define V_DCCLOCK(x) ((x) << S_DCCLOCK)
+#define F_DCCLOCK V_DCCLOCK(1U)
+
+#define S_DCCOFFSET 8
+#define M_DCCOFFSET 0x1fU
+#define V_DCCOFFSET(x) ((x) << S_DCCOFFSET)
+#define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET)
+
+#define S_DCCSTEP 6
+#define M_DCCSTEP 0x3U
+#define V_DCCSTEP(x) ((x) << S_DCCSTEP)
+#define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP)
+
+#define S_DCCASTEP 1
+#define M_DCCASTEP 0x1fU
+#define V_DCCASTEP(x) ((x) << S_DCCASTEP)
+#define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP)
+
+#define S_DCCAEN 0
+#define V_DCCAEN(x) ((x) << S_DCCAEN)
+#define F_DCCAEN V_DCCAEN(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
+
+#define S_DCCOUT 12
+#define V_DCCOUT(x) ((x) << S_DCCOUT)
+#define F_DCCOUT V_DCCOUT(1U)
+
+#define S_DCCCLK 11
+#define V_DCCCLK(x) ((x) << S_DCCCLK)
+#define F_DCCCLK V_DCCCLK(1U)
+
+#define S_DCCHOLD 10
+#define V_DCCHOLD(x) ((x) << S_DCCHOLD)
+#define F_DCCHOLD V_DCCHOLD(1U)
+
+#define S_DCCSIGN 8
+#define M_DCCSIGN 0x3U
+#define V_DCCSIGN(x) ((x) << S_DCCSIGN)
+#define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN)
+
+#define S_DCCAMP 1
+#define M_DCCAMP 0x7fU
+#define V_DCCAMP(x) ((x) << S_DCCAMP)
+#define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP)
+
+#define S_DCCOEN 0
+#define V_DCCOEN(x) ((x) << S_DCCOEN)
+#define F_DCCOEN V_DCCOEN(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094
+
+#define S_DCCASIGN 7
+#define M_DCCASIGN 0x3U
+#define V_DCCASIGN(x) ((x) << S_DCCASIGN)
+#define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN)
+
+#define S_DCCAAMP 0
+#define M_DCCAAMP 0x7fU
+#define V_DCCAAMP(x) ((x) << S_DCCAAMP)
+#define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098
+
+#define S_DCCTIMEOUTVAL 0
+#define M_DCCTIMEOUTVAL 0xffffU
+#define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL)
+#define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c
+
+#define S_LPIDCLK 4
+#define V_LPIDCLK(x) ((x) << S_LPIDCLK)
+#define F_LPIDCLK V_LPIDCLK(1U)
+
+#define S_LPITERM 2
+#define M_LPITERM 0x3U
+#define V_LPITERM(x) ((x) << S_LPITERM)
+#define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM)
+
+#define S_LPIPRCD 0
+#define M_LPIPRCD 0x3U
+#define V_LPIPRCD(x) ((x) << S_LPIPRCD)
+#define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
+
+#define S_SDOVRDEN 8
+#define V_SDOVRDEN(x) ((x) << S_SDOVRDEN)
+#define F_SDOVRDEN V_SDOVRDEN(1U)
+
+#define S_SDOVRD 0
+#define M_SDOVRD 0xffU
+#define V_SDOVRD(x) ((x) << S_SDOVRD)
+#define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
+
+#define S_SLEWCODE 1
+#define M_SLEWCODE 0x3U
+#define V_SLEWCODE(x) ((x) << S_SLEWCODE)
+#define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE)
+
+#define S_ASEGEN 0
+#define V_ASEGEN(x) ((x) << S_ASEGEN)
+#define F_ASEGEN V_ASEGEN(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
+
+#define S_AECMDVAL 14
+#define V_AECMDVAL(x) ((x) << S_AECMDVAL)
+#define F_AECMDVAL V_AECMDVAL(1U)
+
+#define S_AECMD1312 12
+#define M_AECMD1312 0x3U
+#define V_AECMD1312(x) ((x) << S_AECMD1312)
+#define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312)
+
+#define S_AECMD70 0
+#define M_AECMD70 0xffU
+#define V_AECMD70(x) ((x) << S_AECMD70)
+#define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc
+
+#define S_C48DIVCTL 12
+#define M_C48DIVCTL 0x7U
+#define V_C48DIVCTL(x) ((x) << S_C48DIVCTL)
+#define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL)
+
+#define S_RATEDIVCTL 9
+#define M_RATEDIVCTL 0x7U
+#define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL)
+#define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL)
+
+#define S_ANLGFLSH 8
+#define V_ANLGFLSH(x) ((x) << S_ANLGFLSH)
+#define F_ANLGFLSH V_ANLGFLSH(1U)
+
+#define S_DCCTSTOUT 7
+#define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT)
+#define F_DCCTSTOUT V_DCCTSTOUT(1U)
+
+#define S_BSOUT 6
+#define V_BSOUT(x) ((x) << S_BSOUT)
+#define F_BSOUT V_BSOUT(1U)
+
+#define S_BSIN 5
+#define V_BSIN(x) ((x) << S_BSIN)
+#define F_BSIN V_BSIN(1U)
+
+#define S_JTAGAMPL 3
+#define M_JTAGAMPL 0x3U
+#define V_JTAGAMPL(x) ((x) << S_JTAGAMPL)
+#define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL)
+
+#define S_JTAGTS 2
+#define V_JTAGTS(x) ((x) << S_JTAGTS)
+#define F_JTAGTS V_JTAGTS(1U)
+
+#define S_TS 1
+#define V_TS(x) ((x) << S_TS)
+#define F_TS V_TS(1U)
+
+#define S_OBS 0
+#define V_OBS(x) ((x) << S_OBS)
+#define F_OBS V_OBS(1U)
+
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
+#define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
+
+#define S_T5_RX_LINKEN 15
+#define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN)
+#define F_T5_RX_LINKEN V_T5_RX_LINKEN(1U)
+
+#define S_T5_RX_LINKRST 14
+#define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST)
+#define F_T5_RX_LINKRST V_T5_RX_LINKRST(1U)
+
+#define S_T5_RX_CFGWRT 13
+#define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT)
+#define F_T5_RX_CFGWRT V_T5_RX_CFGWRT(1U)
+
+#define S_T5_RX_CFGPTR 11
+#define M_T5_RX_CFGPTR 0x3U
+#define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR)
+#define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR)
+
+#define S_T5_RX_CFGEXT 10
+#define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT)
+#define F_T5_RX_CFGEXT V_T5_RX_CFGEXT(1U)
+
+#define S_T5_RX_CFGACT 9
+#define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT)
+#define F_T5_RX_CFGACT V_T5_RX_CFGACT(1U)
+
+#define S_T5_RX_AUXCLK 8
+#define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK)
+#define F_T5_RX_AUXCLK V_T5_RX_AUXCLK(1U)
+
+#define S_T5_RX_PLLSEL 6
+#define M_T5_RX_PLLSEL 0x3U
+#define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL)
+#define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL)
+
+#define S_T5_RX_DMSEL 4
+#define M_T5_RX_DMSEL 0x3U
+#define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL)
+#define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL)
+
+#define S_T5_RX_BWSEL 2
+#define M_T5_RX_BWSEL 0x3U
+#define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL)
+#define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL)
+
+#define S_T5_RX_RTSEL 0
+#define M_T5_RX_RTSEL 0x3U
+#define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL)
+#define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
+
+#define S_FERRST 10
+#define V_FERRST(x) ((x) << S_FERRST)
+#define F_FERRST V_FERRST(1U)
+
+#define S_ERRST 9
+#define V_ERRST(x) ((x) << S_ERRST)
+#define F_ERRST V_ERRST(1U)
+
+#define S_SYNCST 8
+#define V_SYNCST(x) ((x) << S_SYNCST)
+#define F_SYNCST V_SYNCST(1U)
+
+#define S_WRPSM 7
+#define V_WRPSM(x) ((x) << S_WRPSM)
+#define F_WRPSM V_WRPSM(1U)
+
+#define S_WPLPEN 6
+#define V_WPLPEN(x) ((x) << S_WPLPEN)
+#define F_WPLPEN V_WPLPEN(1U)
+
+#define S_WRPMD 5
+#define V_WRPMD(x) ((x) << S_WRPMD)
+#define F_WRPMD V_WRPMD(1U)
+
+#define S_PATSEL 0
+#define M_PATSEL 0x7U
+#define V_PATSEL(x) ((x) << S_PATSEL)
+#define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL)
+
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
+
+#define S_RSTUCK 3
+#define V_RSTUCK(x) ((x) << S_RSTUCK)
+#define F_RSTUCK V_RSTUCK(1U)
+
+#define S_FRZFW 2
+#define V_FRZFW(x) ((x) << S_FRZFW)
+#define F_FRZFW V_FRZFW(1U)
+
+#define S_RSTFW 1
+#define V_RSTFW(x) ((x) << S_RSTFW)
+#define F_RSTFW V_RSTFW(1U)
+
+#define S_SSCEN 0
+#define V_SSCEN(x) ((x) << S_SSCEN)
+#define F_SSCEN V_SSCEN(1U)
+
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
+
+#define S_ROT00 0
+#define M_ROT00 0x3fU
+#define V_ROT00(x) ((x) << S_ROT00)
+#define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00)
+
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
+
+#define S_FREQFW 8
+#define M_FREQFW 0xffU
+#define V_FREQFW(x) ((x) << S_FREQFW)
+#define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW)
+
+#define S_FWSNAP 7
+#define V_FWSNAP(x) ((x) << S_FWSNAP)
+#define F_FWSNAP V_FWSNAP(1U)
+
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
+
+#define S_RBOOFF 10
+#define M_RBOOFF 0x1fU
+#define V_RBOOFF(x) ((x) << S_RBOOFF)
+#define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF)
+
+#define S_RBEOFF 5
+#define M_RBEOFF 0x1fU
+#define V_RBEOFF(x) ((x) << S_RBEOFF)
+#define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF)
+
+#define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
+#define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
+
+#define S_T5BYTE1 8
+#define M_T5BYTE1 0xffU
+#define V_T5BYTE1(x) ((x) << S_T5BYTE1)
+#define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1)
+
+#define S_T5BYTE0 0
+#define M_T5BYTE0 0xffU
+#define V_T5BYTE0(x) ((x) << S_T5BYTE0)
+#define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0)
+
+#define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228
+
+#define S_T5_RX_SMODE 8
+#define M_T5_RX_SMODE 0x7U
+#define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE)
+#define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE)
+
+#define S_T5_RX_ADCORR 7
+#define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR)
+#define F_T5_RX_ADCORR V_T5_RX_ADCORR(1U)
+
+#define S_T5_RX_TRAINEN 6
+#define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN)
+#define F_T5_RX_TRAINEN V_T5_RX_TRAINEN(1U)
+
+#define S_T5_RX_ASAMPQ 3
+#define M_T5_RX_ASAMPQ 0x7U
+#define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ)
+#define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ)
+
+#define S_T5_RX_ASAMP 0
+#define M_T5_RX_ASAMP 0x7U
+#define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP)
+#define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
+#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
+
+#define S_T5SHORTV 10
+#define V_T5SHORTV(x) ((x) << S_T5SHORTV)
+#define F_T5SHORTV V_T5SHORTV(1U)
+
+#define S_T5VGAIN 0
+#define M_T5VGAIN 0x1fU
+#define V_T5VGAIN(x) ((x) << S_T5VGAIN)
+#define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
+
+#define S_IQSEP 10
+#define M_IQSEP 0x1fU
+#define V_IQSEP(x) ((x) << S_IQSEP)
+#define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP)
+
+#define S_DUTYQ 5
+#define M_DUTYQ 0x1fU
+#define V_DUTYQ(x) ((x) << S_DUTYQ)
+#define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ)
+
+#define S_DUTYI 0
+#define M_DUTYI 0x1fU
+#define V_DUTYI(x) ((x) << S_DUTYI)
+#define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
+
+#define S_DTHR 8
+#define M_DTHR 0x3fU
+#define V_DTHR(x) ((x) << S_DTHR)
+#define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR)
+
+#define S_SNUL 0
+#define M_SNUL 0x1fU
+#define V_SNUL(x) ((x) << S_SNUL)
+#define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
+#define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
+
+#define S_ADSN_READWRITE 8
+#define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE)
+#define F_ADSN_READWRITE V_ADSN_READWRITE(1U)
+
+#define S_ADSN_READONLY 7
+#define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY)
+#define F_ADSN_READONLY V_ADSN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
+
+#define S_H1O2 8
+#define M_H1O2 0x3fU
+#define V_H1O2(x) ((x) << S_H1O2)
+#define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2)
+
+#define S_H1E2 0
+#define M_H1E2 0x3fU
+#define V_H1E2(x) ((x) << S_H1E2)
+#define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
+
+#define S_H1O3 8
+#define M_H1O3 0x3fU
+#define V_H1O3(x) ((x) << S_H1O3)
+#define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3)
+
+#define S_H1E3 0
+#define M_H1E3 0x3fU
+#define V_H1E3(x) ((x) << S_H1E3)
+#define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
+
+#define S_H1O4 8
+#define M_H1O4 0x3fU
+#define V_H1O4(x) ((x) << S_H1O4)
+#define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4)
+
+#define S_H1E4 0
+#define M_H1E4 0x3fU
+#define V_H1E4(x) ((x) << S_H1E4)
+#define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4)
+
+#define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
+
+#define S_DPCMD 14
+#define V_DPCMD(x) ((x) << S_DPCMD)
+#define F_DPCMD V_DPCMD(1U)
+
+#define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
+#define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
+
+#define S_T5BER6VAL 15
+#define V_T5BER6VAL(x) ((x) << S_T5BER6VAL)
+#define F_T5BER6VAL V_T5BER6VAL(1U)
+
+#define S_T5BER6 14
+#define V_T5BER6(x) ((x) << S_T5BER6)
+#define F_T5BER6 V_T5BER6(1U)
+
+#define S_T5BER3VAL 13
+#define V_T5BER3VAL(x) ((x) << S_T5BER3VAL)
+#define F_T5BER3VAL V_T5BER3VAL(1U)
+
+#define S_T5TOOFAST 12
+#define V_T5TOOFAST(x) ((x) << S_T5TOOFAST)
+#define F_T5TOOFAST V_T5TOOFAST(1U)
+
+#define S_T5DPCCMP 9
+#define V_T5DPCCMP(x) ((x) << S_T5DPCCMP)
+#define F_T5DPCCMP V_T5DPCCMP(1U)
+
+#define S_T5DACCMP 8
+#define V_T5DACCMP(x) ((x) << S_T5DACCMP)
+#define F_T5DACCMP V_T5DACCMP(1U)
+
+#define S_T5DDCCMP 7
+#define V_T5DDCCMP(x) ((x) << S_T5DDCCMP)
+#define F_T5DDCCMP V_T5DDCCMP(1U)
+
+#define S_T5AERRFLG 6
+#define V_T5AERRFLG(x) ((x) << S_T5AERRFLG)
+#define F_T5AERRFLG V_T5AERRFLG(1U)
+
+#define S_T5WERRFLG 5
+#define V_T5WERRFLG(x) ((x) << S_T5WERRFLG)
+#define F_T5WERRFLG V_T5WERRFLG(1U)
+
+#define S_T5TRCMP 4
+#define V_T5TRCMP(x) ((x) << S_T5TRCMP)
+#define F_T5TRCMP V_T5TRCMP(1U)
+
+#define S_T5VLCKF 3
+#define V_T5VLCKF(x) ((x) << S_T5VLCKF)
+#define F_T5VLCKF V_T5VLCKF(1U)
+
+#define S_T5ROCCMP 2
+#define V_T5ROCCMP(x) ((x) << S_T5ROCCMP)
+#define F_T5ROCCMP V_T5ROCCMP(1U)
+
+#define S_T5DQCCCMP 1
+#define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP)
+#define F_T5DQCCCMP V_T5DQCCCMP(1U)
+
+#define S_T5OCCMP 0
+#define V_T5OCCMP(x) ((x) << S_T5OCCMP)
+#define F_T5OCCMP V_T5OCCMP(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
+
+#define S_FLOFF 1
+#define V_FLOFF(x) ((x) << S_FLOFF)
+#define F_FLOFF V_FLOFF(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280
+
+#define S_H25SPC 15
+#define V_H25SPC(x) ((x) << S_H25SPC)
+#define F_H25SPC V_H25SPC(1U)
+
+#define S_FTOOFAST 8
+#define V_FTOOFAST(x) ((x) << S_FTOOFAST)
+#define F_FTOOFAST V_FTOOFAST(1U)
+
+#define S_FINTTRIM 7
+#define V_FINTTRIM(x) ((x) << S_FINTTRIM)
+#define F_FINTTRIM V_FINTTRIM(1U)
+
+#define S_FDINV 6
+#define V_FDINV(x) ((x) << S_FDINV)
+#define F_FDINV V_FDINV(1U)
+
+#define S_FHGS 5
+#define V_FHGS(x) ((x) << S_FHGS)
+#define F_FHGS V_FHGS(1U)
+
+#define S_FH6H12 4
+#define V_FH6H12(x) ((x) << S_FH6H12)
+#define F_FH6H12 V_FH6H12(1U)
+
+#define S_FH1CAL 3
+#define V_FH1CAL(x) ((x) << S_FH1CAL)
+#define F_FH1CAL V_FH1CAL(1U)
+
+#define S_FINTCAL 2
+#define V_FINTCAL(x) ((x) << S_FINTCAL)
+#define F_FINTCAL V_FINTCAL(1U)
+
+#define S_FDCA 1
+#define V_FDCA(x) ((x) << S_FDCA)
+#define F_FDCA V_FDCA(1U)
+
+#define S_FDQCC 0
+#define V_FDQCC(x) ((x) << S_FDQCC)
+#define F_FDQCC V_FDQCC(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
+
+#define S_LOFE2S_READWRITE 16
+#define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE)
+#define F_LOFE2S_READWRITE V_LOFE2S_READWRITE(1U)
+
+#define S_LOFE2S_READONLY 14
+#define M_LOFE2S_READONLY 0x3U
+#define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY)
+#define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY)
+
+#define S_LOFE2 8
+#define M_LOFE2 0x3fU
+#define V_LOFE2(x) ((x) << S_LOFE2)
+#define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2)
+
+#define S_LOFE1S_READWRITE 7
+#define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE)
+#define F_LOFE1S_READWRITE V_LOFE1S_READWRITE(1U)
+
+#define S_LOFE1S_READONLY 6
+#define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY)
+#define F_LOFE1S_READONLY V_LOFE1S_READONLY(1U)
+
+#define S_LOFE1 0
+#define M_LOFE1 0x3fU
+#define V_LOFE1(x) ((x) << S_LOFE1)
+#define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1)
+
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
+
+#define S_LOFO2S_READWRITE 15
+#define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE)
+#define F_LOFO2S_READWRITE V_LOFO2S_READWRITE(1U)
+
+#define S_LOFO2S_READONLY 14
+#define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY)
+#define F_LOFO2S_READONLY V_LOFO2S_READONLY(1U)
+
+#define S_LOFO2 8
+#define M_LOFO2 0x3fU
+#define V_LOFO2(x) ((x) << S_LOFO2)
+#define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2)
+
+#define S_LOFO1S_READWRITE 7
+#define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE)
+#define F_LOFO1S_READWRITE V_LOFO1S_READWRITE(1U)
+
+#define S_LOFO1S_READONLY 6
+#define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY)
+#define F_LOFO1S_READONLY V_LOFO1S_READONLY(1U)
+
+#define S_LOFO1 0
+#define M_LOFO1 0x3fU
+#define V_LOFO1(x) ((x) << S_LOFO1)
+#define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1)
+
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
+
+#define S_LOFE4S_READWRITE 15
+#define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE)
+#define F_LOFE4S_READWRITE V_LOFE4S_READWRITE(1U)
+
+#define S_LOFE4S_READONLY 14
+#define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY)
+#define F_LOFE4S_READONLY V_LOFE4S_READONLY(1U)
+
+#define S_LOFE 8
+#define M_LOFE 0x3fU
+#define V_LOFE(x) ((x) << S_LOFE)
+#define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE)
+
+#define S_LOFE3S_READWRITE 7
+#define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE)
+#define F_LOFE3S_READWRITE V_LOFE3S_READWRITE(1U)
+
+#define S_LOFE3S_READONLY 6
+#define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY)
+#define F_LOFE3S_READONLY V_LOFE3S_READONLY(1U)
+
+#define S_LOFE3 0
+#define M_LOFE3 0x3fU
+#define V_LOFE3(x) ((x) << S_LOFE3)
+#define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3)
+
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
+
+#define S_LOFO4S_READWRITE 15
+#define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE)
+#define F_LOFO4S_READWRITE V_LOFO4S_READWRITE(1U)
+
+#define S_LOFO4S_READONLY 14
+#define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY)
+#define F_LOFO4S_READONLY V_LOFO4S_READONLY(1U)
+
+#define S_LOFO4 8
+#define M_LOFO4 0x3fU
+#define V_LOFO4(x) ((x) << S_LOFO4)
+#define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4)
+
+#define S_LOFO3S_READWRITE 7
+#define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE)
+#define F_LOFO3S_READWRITE V_LOFO3S_READWRITE(1U)
+
+#define S_LOFO3S_READONLY 6
+#define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY)
+#define F_LOFO3S_READONLY V_LOFO3S_READONLY(1U)
+
+#define S_LOFO3 0
+#define M_LOFO3 0x3fU
+#define V_LOFO3(x) ((x) << S_LOFO3)
+#define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3)
+
+#define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
+
+#define S_T5E1SN_READWRITE 15
+#define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE)
+#define F_T5E1SN_READWRITE V_T5E1SN_READWRITE(1U)
+
+#define S_T5E1SN_READONLY 14
+#define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY)
+#define F_T5E1SN_READONLY V_T5E1SN_READONLY(1U)
+
+#define S_T5E1AMP 8
+#define M_T5E1AMP 0x3fU
+#define V_T5E1AMP(x) ((x) << S_T5E1AMP)
+#define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP)
+
+#define S_T5E0SN_READWRITE 7
+#define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE)
+#define F_T5E0SN_READWRITE V_T5E0SN_READWRITE(1U)
+
+#define S_T5E0SN_READONLY 6
+#define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY)
+#define F_T5E0SN_READONLY V_T5E0SN_READONLY(1U)
+
+#define S_T5E0AMP 0
+#define M_T5E0AMP 0x3fU
+#define V_T5E0AMP(x) ((x) << S_T5E0AMP)
+#define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298
+
+#define S_T5LFREG 12
+#define V_T5LFREG(x) ((x) << S_T5LFREG)
+#define F_T5LFREG V_T5LFREG(1U)
+
+#define S_T5LFRC 11
+#define V_T5LFRC(x) ((x) << S_T5LFRC)
+#define F_T5LFRC V_T5LFRC(1U)
+
+#define S_T5LFSEL 8
+#define M_T5LFSEL 0x7U
+#define V_T5LFSEL(x) ((x) << S_T5LFSEL)
+#define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
+
+#define S_OFFSN_READWRITE 14
+#define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE)
+#define F_OFFSN_READWRITE V_OFFSN_READWRITE(1U)
+
+#define S_OFFSN_READONLY 13
+#define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY)
+#define F_OFFSN_READONLY V_OFFSN_READONLY(1U)
+
+#define S_OFFAMP 8
+#define M_OFFAMP 0x1fU
+#define V_OFFAMP(x) ((x) << S_OFFAMP)
+#define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP)
+
+#define S_SDACDC 7
+#define V_SDACDC(x) ((x) << S_SDACDC)
+#define F_SDACDC V_SDACDC(1U)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
+
+#define S_T5_RX_SETHDIS 7
+#define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS)
+#define F_T5_RX_SETHDIS V_T5_RX_SETHDIS(1U)
+
+#define S_T5_RX_PDTERM 6
+#define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM)
+#define F_T5_RX_PDTERM V_T5_RX_PDTERM(1U)
+
+#define S_T5_RX_BYPASS 5
+#define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS)
+#define F_T5_RX_BYPASS V_T5_RX_BYPASS(1U)
+
+#define S_T5_RX_LPFEN 4
+#define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN)
+#define F_T5_RX_LPFEN V_T5_RX_LPFEN(1U)
+
+#define S_T5_RX_VGABOD 3
+#define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD)
+#define F_T5_RX_VGABOD V_T5_RX_VGABOD(1U)
+
+#define S_T5_RX_VTBYP 2
+#define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP)
+#define F_T5_RX_VTBYP V_T5_RX_VTBYP(1U)
+
+#define S_T5_RX_VTERM 0
+#define M_T5_RX_VTERM 0x3U
+#define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM)
+#define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM)
+
+#define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
+
+#define S_ISTRIMS 14
+#define M_ISTRIMS 0x3U
+#define V_ISTRIMS(x) ((x) << S_ISTRIMS)
+#define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS)
+
+#define S_ISTRIM 8
+#define M_ISTRIM 0x3fU
+#define V_ISTRIM(x) ((x) << S_ISTRIM)
+#define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM)
+
+#define S_HALF1 7
+#define V_HALF1(x) ((x) << S_HALF1)
+#define F_HALF1 V_HALF1(1U)
+
+#define S_HALF2 6
+#define V_HALF2(x) ((x) << S_HALF2)
+#define F_HALF2 V_HALF2(1U)
+
+#define S_INTDAC 0
+#define M_INTDAC 0x3fU
+#define V_INTDAC(x) ((x) << S_INTDAC)
+#define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
+
+#define S_MINWDTH 5
+#define M_MINWDTH 0x1fU
+#define V_MINWDTH(x) ((x) << S_MINWDTH)
+#define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac
+
+#define S_T5SMQM 13
+#define M_T5SMQM 0x7U
+#define V_T5SMQM(x) ((x) << S_T5SMQM)
+#define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM)
+
+#define S_T5SMQ 5
+#define M_T5SMQ 0xffU
+#define V_T5SMQ(x) ((x) << S_T5SMQ)
+#define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ)
+
+#define S_T5EMMD 3
+#define M_T5EMMD 0x3U
+#define V_T5EMMD(x) ((x) << S_T5EMMD)
+#define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD)
+
+#define S_T5EMBRDY 2
+#define V_T5EMBRDY(x) ((x) << S_T5EMBRDY)
+#define F_T5EMBRDY V_T5EMBRDY(1U)
+
+#define S_T5EMBUMP 1
+#define V_T5EMBUMP(x) ((x) << S_T5EMBUMP)
+#define F_T5EMBUMP V_T5EMBUMP(1U)
+
+#define S_T5EMEN 0
+#define V_T5EMEN(x) ((x) << S_T5EMEN)
+#define F_T5EMEN V_T5EMEN(1U)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
+
+#define S_EMF8 15
+#define V_EMF8(x) ((x) << S_EMF8)
+#define F_EMF8 V_EMF8(1U)
+
+#define S_EMCNT 4
+#define M_EMCNT 0xffU
+#define V_EMCNT(x) ((x) << S_EMCNT)
+#define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT)
+
+#define S_EMOFLO 2
+#define V_EMOFLO(x) ((x) << S_EMOFLO)
+#define F_EMOFLO V_EMOFLO(1U)
+
+#define S_EMCRST 1
+#define V_EMCRST(x) ((x) << S_EMCRST)
+#define F_EMCRST V_EMCRST(1U)
+
+#define S_EMCEN 0
+#define V_EMCEN(x) ((x) << S_EMCEN)
+#define F_EMCEN V_EMCEN(1U)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
+
+#define S_SM2RDY 15
+#define V_SM2RDY(x) ((x) << S_SM2RDY)
+#define F_SM2RDY V_SM2RDY(1U)
+
+#define S_SM2RST 14
+#define V_SM2RST(x) ((x) << S_SM2RST)
+#define F_SM2RST V_SM2RST(1U)
+
+#define S_APDF 0
+#define M_APDF 0xfffU
+#define V_APDF(x) ((x) << S_APDF)
+#define G_APDF(x) (((x) >> S_APDF) & M_APDF)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8
+
+#define S_SM0LEN 0
+#define M_SM0LEN 0x7fffU
+#define V_SM0LEN(x) ((x) << S_SM0LEN)
+#define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN)
+
+#define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
+
+#define S_H_EN 1
+#define M_H_EN 0xfffU
+#define V_H_EN(x) ((x) << S_H_EN)
+#define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
+#define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
+
+#define S_H2OSN_READWRITE 14
+#define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE)
+#define F_H2OSN_READWRITE V_H2OSN_READWRITE(1U)
+
+#define S_H2OSN_READONLY 13
+#define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY)
+#define F_H2OSN_READONLY V_H2OSN_READONLY(1U)
+
+#define S_H2ESN_READWRITE 6
+#define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE)
+#define F_H2ESN_READWRITE V_H2ESN_READWRITE(1U)
+
+#define S_H2ESN_READONLY 5
+#define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY)
+#define F_H2ESN_READONLY V_H2ESN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc
+
+#define S_H3OSN_READWRITE 13
+#define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE)
+#define F_H3OSN_READWRITE V_H3OSN_READWRITE(1U)
+
+#define S_H3OSN_READONLY 12
+#define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY)
+#define F_H3OSN_READONLY V_H3OSN_READONLY(1U)
+
+#define S_H3ESN_READWRITE 5
+#define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE)
+#define F_H3ESN_READWRITE V_H3ESN_READWRITE(1U)
+
+#define S_H3ESN_READONLY 4
+#define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY)
+#define F_H3ESN_READONLY V_H3ESN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0
+
+#define S_H4OGS 14
+#define M_H4OGS 0x3U
+#define V_H4OGS(x) ((x) << S_H4OGS)
+#define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS)
+
+#define S_H4OSN_READWRITE 13
+#define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE)
+#define F_H4OSN_READWRITE V_H4OSN_READWRITE(1U)
+
+#define S_H4OSN_READONLY 12
+#define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY)
+#define F_H4OSN_READONLY V_H4OSN_READONLY(1U)
+
+#define S_H4EGS 6
+#define M_H4EGS 0x3U
+#define V_H4EGS(x) ((x) << S_H4EGS)
+#define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS)
+
+#define S_H4ESN_READWRITE 5
+#define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE)
+#define F_H4ESN_READWRITE V_H4ESN_READWRITE(1U)
+
+#define S_H4ESN_READONLY 4
+#define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY)
+#define F_H4ESN_READONLY V_H4ESN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4
+
+#define S_H5OGS 14
+#define M_H5OGS 0x3U
+#define V_H5OGS(x) ((x) << S_H5OGS)
+#define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS)
+
+#define S_H5OSN_READWRITE 13
+#define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE)
+#define F_H5OSN_READWRITE V_H5OSN_READWRITE(1U)
+
+#define S_H5OSN_READONLY 12
+#define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY)
+#define F_H5OSN_READONLY V_H5OSN_READONLY(1U)
+
+#define S_H5EGS 6
+#define M_H5EGS 0x3U
+#define V_H5EGS(x) ((x) << S_H5EGS)
+#define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS)
+
+#define S_H5ESN_READWRITE 5
+#define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE)
+#define F_H5ESN_READWRITE V_H5ESN_READWRITE(1U)
+
+#define S_H5ESN_READONLY 4
+#define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY)
+#define F_H5ESN_READONLY V_H5ESN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8
+
+#define S_H7GS 14
+#define M_H7GS 0x3U
+#define V_H7GS(x) ((x) << S_H7GS)
+#define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS)
+
+#define S_H7SN_READWRITE 13
+#define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE)
+#define F_H7SN_READWRITE V_H7SN_READWRITE(1U)
+
+#define S_H7SN_READONLY 12
+#define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY)
+#define F_H7SN_READONLY V_H7SN_READONLY(1U)
+
+#define S_H7MAG 8
+#define M_H7MAG 0xfU
+#define V_H7MAG(x) ((x) << S_H7MAG)
+#define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG)
+
+#define S_H6GS 6
+#define M_H6GS 0x3U
+#define V_H6GS(x) ((x) << S_H6GS)
+#define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS)
+
+#define S_H6SN_READWRITE 5
+#define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE)
+#define F_H6SN_READWRITE V_H6SN_READWRITE(1U)
+
+#define S_H6SN_READONLY 4
+#define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY)
+#define F_H6SN_READONLY V_H6SN_READONLY(1U)
+
+#define S_H6MAG 0
+#define M_H6MAG 0xfU
+#define V_H6MAG(x) ((x) << S_H6MAG)
+#define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc
+
+#define S_H9GS 14
+#define M_H9GS 0x3U
+#define V_H9GS(x) ((x) << S_H9GS)
+#define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS)
+
+#define S_H9SN_READWRITE 13
+#define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE)
+#define F_H9SN_READWRITE V_H9SN_READWRITE(1U)
+
+#define S_H9SN_READONLY 12
+#define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY)
+#define F_H9SN_READONLY V_H9SN_READONLY(1U)
+
+#define S_H9MAG 8
+#define M_H9MAG 0xfU
+#define V_H9MAG(x) ((x) << S_H9MAG)
+#define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG)
+
+#define S_H8GS 6
+#define M_H8GS 0x3U
+#define V_H8GS(x) ((x) << S_H8GS)
+#define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS)
+
+#define S_H8SN_READWRITE 5
+#define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE)
+#define F_H8SN_READWRITE V_H8SN_READWRITE(1U)
+
+#define S_H8SN_READONLY 4
+#define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY)
+#define F_H8SN_READONLY V_H8SN_READONLY(1U)
+
+#define S_H8MAG 0
+#define M_H8MAG 0xfU
+#define V_H8MAG(x) ((x) << S_H8MAG)
+#define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0
+
+#define S_H11GS 14
+#define M_H11GS 0x3U
+#define V_H11GS(x) ((x) << S_H11GS)
+#define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS)
+
+#define S_H11SN_READWRITE 13
+#define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE)
+#define F_H11SN_READWRITE V_H11SN_READWRITE(1U)
+
+#define S_H11SN_READONLY 12
+#define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY)
+#define F_H11SN_READONLY V_H11SN_READONLY(1U)
+
+#define S_H11MAG 8
+#define M_H11MAG 0xfU
+#define V_H11MAG(x) ((x) << S_H11MAG)
+#define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG)
+
+#define S_H10GS 6
+#define M_H10GS 0x3U
+#define V_H10GS(x) ((x) << S_H10GS)
+#define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS)
+
+#define S_H10SN_READWRITE 5
+#define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE)
+#define F_H10SN_READWRITE V_H10SN_READWRITE(1U)
+
+#define S_H10SN_READONLY 4
+#define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY)
+#define F_H10SN_READONLY V_H10SN_READONLY(1U)
+
+#define S_H10MAG 0
+#define M_H10MAG 0xfU
+#define V_H10MAG(x) ((x) << S_H10MAG)
+#define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4
+
+#define S_H12GS 6
+#define M_H12GS 0x3U
+#define V_H12GS(x) ((x) << S_H12GS)
+#define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS)
+
+#define S_H12SN_READWRITE 5
+#define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE)
+#define F_H12SN_READWRITE V_H12SN_READWRITE(1U)
+
+#define S_H12SN_READONLY 4
+#define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY)
+#define F_H12SN_READONLY V_H12SN_READONLY(1U)
+
+#define S_H12MAG 0
+#define M_H12MAG 0xfU
+#define V_H12MAG(x) ((x) << S_H12MAG)
+#define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
+
+#define S_DFEDACLSSD 6
+#define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD)
+#define F_DFEDACLSSD V_DFEDACLSSD(1U)
+
+#define S_SDLSSD 5
+#define V_SDLSSD(x) ((x) << S_SDLSSD)
+#define F_SDLSSD V_SDLSSD(1U)
+
+#define S_DFEOBSBIAS 4
+#define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS)
+#define F_DFEOBSBIAS V_DFEOBSBIAS(1U)
+
+#define S_GBOFSTLSSD 3
+#define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD)
+#define F_GBOFSTLSSD V_GBOFSTLSSD(1U)
+
+#define S_RXDOBS 2
+#define V_RXDOBS(x) ((x) << S_RXDOBS)
+#define F_RXDOBS V_RXDOBS(1U)
+
+#define S_ACJZPT 1
+#define V_ACJZPT(x) ((x) << S_ACJZPT)
+#define F_ACJZPT V_ACJZPT(1U)
+
+#define S_ACJZNT 0
+#define V_ACJZNT(x) ((x) << S_ACJZNT)
+#define F_ACJZNT V_ACJZNT(1U)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
+
+#define S_PHSLOCK 10
+#define V_PHSLOCK(x) ((x) << S_PHSLOCK)
+#define F_PHSLOCK V_PHSLOCK(1U)
+
+#define S_TESTMODE 9
+#define V_TESTMODE(x) ((x) << S_TESTMODE)
+#define F_TESTMODE V_TESTMODE(1U)
+
+#define S_CALMODE 8
+#define V_CALMODE(x) ((x) << S_CALMODE)
+#define F_CALMODE V_CALMODE(1U)
+
+#define S_AMPSEL 7
+#define V_AMPSEL(x) ((x) << S_AMPSEL)
+#define F_AMPSEL V_AMPSEL(1U)
+
+#define S_WHICHNRZ 6
+#define V_WHICHNRZ(x) ((x) << S_WHICHNRZ)
+#define F_WHICHNRZ V_WHICHNRZ(1U)
+
+#define S_BANKA 5
+#define V_BANKA(x) ((x) << S_BANKA)
+#define F_BANKA V_BANKA(1U)
+
+#define S_BANKB 4
+#define V_BANKB(x) ((x) << S_BANKB)
+#define F_BANKB V_BANKB(1U)
+
+#define S_ACJPDP 3
+#define V_ACJPDP(x) ((x) << S_ACJPDP)
+#define F_ACJPDP V_ACJPDP(1U)
+
+#define S_ACJPDN 2
+#define V_ACJPDN(x) ((x) << S_ACJPDN)
+#define F_ACJPDN V_ACJPDN(1U)
+
+#define S_LSSDT 1
+#define V_LSSDT(x) ((x) << S_LSSDT)
+#define F_LSSDT V_LSSDT(1U)
+
+#define S_MTHOLD 0
+#define V_MTHOLD(x) ((x) << S_MTHOLD)
+#define F_MTHOLD V_MTHOLD(1U)
+
+#define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
+#define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
+#define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
+#define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
+#define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
+#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
+#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
+#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
+#define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
+#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
+#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
+#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
+#define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
+#define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
+#define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
+#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
+#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
+#define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
+#define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
+#define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
+#define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
+#define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
+#define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
+#define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
+#define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
+#define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
+#define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
+#define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4
+#define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8
+#define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
+#define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
+#define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
+#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
+#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
+#define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
+#define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
+#define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
+#define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
+#define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
+#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
+#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
+#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
+#define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
+#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
+#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
+#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
+#define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
+#define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
+#define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
+#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
+#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
+#define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
+#define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
+#define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
+#define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
+#define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
+#define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
+#define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
+#define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
+#define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
+#define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
+#define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4
+#define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8
+#define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
+#define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
+#define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
+#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
+#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
+#define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
+#define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
+#define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
+#define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
+#define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
+#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
+#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
+#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
+#define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
+#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
+#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
+#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
+#define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
+#define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
+#define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
+#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
+#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
+#define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
+#define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
+#define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
+#define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
+#define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
+#define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
+#define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
+#define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
+#define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
+#define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
+#define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4
+#define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8
+#define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
+#define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
+#define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
+#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
+#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
+#define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
+#define A_MAC_PORT_BANDGAP_CONTROL 0x382c
+
+#define S_T5BGCTL 0
+#define M_T5BGCTL 0xfU
+#define V_T5BGCTL(x) ((x) << S_T5BGCTL)
+#define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL)
+
+#define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
+
+#define S_RCCTL1 5
+#define V_RCCTL1(x) ((x) << S_RCCTL1)
+#define F_RCCTL1 V_RCCTL1(1U)
+
+#define S_RCCTL0 4
+#define V_RCCTL0(x) ((x) << S_RCCTL0)
+#define F_RCCTL0 V_RCCTL0(1U)
+
+#define S_RCAMP1 3
+#define V_RCAMP1(x) ((x) << S_RCAMP1)
+#define F_RCAMP1 V_RCAMP1(1U)
+
+#define S_RCAMP0 2
+#define V_RCAMP0(x) ((x) << S_RCAMP0)
+#define F_RCAMP0 V_RCAMP0(1U)
+
+#define S_RCAMPEN 1
+#define V_RCAMPEN(x) ((x) << S_RCAMPEN)
+#define F_RCAMPEN V_RCAMPEN(1U)
+
+#define S_RCRST 0
+#define V_RCRST(x) ((x) << S_RCRST)
+#define F_RCRST V_RCRST(1U)
+
+#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
+
+#define S_RCERR 1
+#define V_RCERR(x) ((x) << S_RCERR)
+#define F_RCERR V_RCERR(1U)
+
+#define S_RCCOMP 0
+#define V_RCCOMP(x) ((x) << S_RCCOMP)
+#define F_RCCOMP V_RCCOMP(1U)
+
+#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
+
+#define S_RESREG2 0
+#define M_RESREG2 0xffU
+#define V_RESREG2(x) ((x) << S_RESREG2)
+#define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2)
+
+#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
+
+#define S_RESREG3 0
+#define M_RESREG3 0xffU
+#define V_RESREG3(x) ((x) << S_RESREG3)
+#define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3)
+
+#define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
+
+#define S_LBIST 7
+#define V_LBIST(x) ((x) << S_LBIST)
+#define F_LBIST V_LBIST(1U)
+
+#define S_LOGICTEST 6
+#define V_LOGICTEST(x) ((x) << S_LOGICTEST)
+#define F_LOGICTEST V_LOGICTEST(1U)
+
+#define S_MAVDHI 5
+#define V_MAVDHI(x) ((x) << S_MAVDHI)
+#define F_MAVDHI V_MAVDHI(1U)
+
+#define S_AUXEN 4
+#define V_AUXEN(x) ((x) << S_AUXEN)
+#define F_AUXEN V_AUXEN(1U)
+
+#define S_JTAGMD 3
+#define V_JTAGMD(x) ((x) << S_JTAGMD)
+#define F_JTAGMD V_JTAGMD(1U)
+
+#define S_RXACMODE 2
+#define V_RXACMODE(x) ((x) << S_RXACMODE)
+#define F_RXACMODE V_RXACMODE(1U)
+
+#define S_HSSACJPC 1
+#define V_HSSACJPC(x) ((x) << S_HSSACJPC)
+#define F_HSSACJPC V_HSSACJPC(1U)
+
+#define S_HSSACJAC 0
+#define V_HSSACJAC(x) ((x) << S_HSSACJAC)
+#define F_HSSACJAC V_HSSACJAC(1U)
+
+#define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec
+
+#define S_REFVALIDD 6
+#define V_REFVALIDD(x) ((x) << S_REFVALIDD)
+#define F_REFVALIDD V_REFVALIDD(1U)
+
+#define S_REFVALIDC 5
+#define V_REFVALIDC(x) ((x) << S_REFVALIDC)
+#define F_REFVALIDC V_REFVALIDC(1U)
+
+#define S_REFVALIDB 4
+#define V_REFVALIDB(x) ((x) << S_REFVALIDB)
+#define F_REFVALIDB V_REFVALIDB(1U)
+
+#define S_REFVALIDA 3
+#define V_REFVALIDA(x) ((x) << S_REFVALIDA)
+#define F_REFVALIDA V_REFVALIDA(1U)
+
+#define S_REFSELRESET 2
+#define V_REFSELRESET(x) ((x) << S_REFSELRESET)
+#define F_REFSELRESET V_REFSELRESET(1U)
+
+#define S_SOFTRESET 1
+#define V_SOFTRESET(x) ((x) << S_SOFTRESET)
+#define F_SOFTRESET V_SOFTRESET(1U)
+
+#define S_MACROTEST 0
+#define V_MACROTEST(x) ((x) << S_MACROTEST)
+#define F_MACROTEST V_MACROTEST(1U)
+
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRI